#include "math.h"

extern "C" const size_t SUB_MATRIX_DIM = 32;
extern "C" const size_t SUB_VECTOR_LEN = 256;

typedef struct {
  size_t rows;
  size_t cols;
  float *elements;
} Matrix;

__device__ float *sub_block(Matrix m, int block_row, int block_col) {
  return m.elements + (block_row * SUB_MATRIX_DIM * m.cols) +
         (block_col * SUB_MATRIX_DIM);
}

__device__ float atomicMaxf(float *addr, float val) {
  return val >= 0
    ? __int_as_float(atomicMax((int *)addr, __float_as_int(val)))
    : __uint_as_float(atomicMax((unsigned int *)addr, __float_as_uint(val)));
}

__global__
void kernel_eq_mats(float *lhs, float *rhs, size_t len, float epsilon, bool *equal) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; *equal && i < len; i += stride)
    if (fabs(lhs[i] - rhs[i]) >= epsilon)
      *equal = false;
}

__global__
void kernel_add_mats(float *lhs1, float *lhs2, float *rhs, size_t len) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < len; i += stride)
    rhs[i] = lhs1[i] + lhs2[i];
}

__global__
void kernel_mul_scalar_mat(float scalar, float *lhs, float *rhs, size_t len) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < len; i += stride)
    rhs[i] = scalar * lhs[i];
}

__global__
void kernel_mul_mats(Matrix lhs1, Matrix lhs2, Matrix rhs) {
  int block_row = blockIdx.y;
  int block_col = blockIdx.x;

  int thread_row = threadIdx.y;
  int thread_col = threadIdx.x;

  float *rhs_sub = sub_block(rhs, block_row, block_col);

  float rhs_elem_val = 0;

  int block_cols =
      (lhs1.cols / SUB_MATRIX_DIM) + (lhs1.cols % SUB_MATRIX_DIM != 0);
  for (int sub_i = 0; sub_i < block_cols; ++sub_i) {
    float *lhs1_sub = sub_block(lhs1, block_row, sub_i);
    float *lhs2_sub = sub_block(lhs2, sub_i, block_col);

    __shared__ float shared_lhs1_sub[SUB_MATRIX_DIM][SUB_MATRIX_DIM];
    __shared__ float shared_lhs2_sub[SUB_MATRIX_DIM][SUB_MATRIX_DIM];

    shared_lhs1_sub[thread_row][thread_col]
      = lhs1_sub[thread_row * lhs1.cols + thread_col];
    shared_lhs2_sub[thread_row][thread_col]
      = lhs2_sub[thread_row * lhs2.cols + thread_col];

    __syncthreads();

    for (int rhs_i = 0; rhs_i < SUB_MATRIX_DIM; ++rhs_i) {
      rhs_elem_val +=
        shared_lhs1_sub[thread_row][rhs_i] * shared_lhs2_sub[rhs_i][thread_col];
    }

    __syncthreads();
  }

  rhs_sub[thread_row * rhs.cols + thread_col] = rhs_elem_val;
}

__global__
void kernel_transpose_mat(Matrix lhs, Matrix rhs) {
  int block_row = blockIdx.y;
  int block_col = blockIdx.x;

  int thread_row = threadIdx.y;
  int thread_col = threadIdx.x;

  float *lhs_sub = sub_block(lhs, block_row, block_col);
  float *rhs_sub = sub_block(rhs, block_col, block_row);

  __shared__ float shared_lhs_sub[SUB_MATRIX_DIM][SUB_MATRIX_DIM];

  shared_lhs_sub[thread_row][thread_col]
    = lhs_sub[thread_row * lhs.cols + thread_col];

  __syncthreads();

  rhs_sub[thread_col * rhs.cols + thread_row]
    = shared_lhs_sub[thread_row][thread_col];
}

__global__
void kernel_dot_vecs(float *lhs1, float *lhs2, float *rhs) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;

  __shared__ float sub_vec[SUB_VECTOR_LEN];
  sub_vec[threadIdx.x] = lhs1[index] * lhs2[index];

  __syncthreads();

  if (threadIdx.x == 0) {
    float sub_vec_sum = 0.0f;
    for (int i = 0; i < SUB_VECTOR_LEN; ++i)
      sub_vec_sum += sub_vec[i];

    atomicAdd(rhs, sub_vec_sum);
  }
}

__global__
void kernel_p_norm_vec(float *lhs, float p, float *rhs) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;

  __shared__ float sub_vec[SUB_VECTOR_LEN];
  sub_vec[threadIdx.x] = powf(fabsf(lhs[index]), p);

  __syncthreads();

  if (threadIdx.x == 0) {
    float sub_vec_sum = 0.0f;
    for (int i = 0; i < SUB_VECTOR_LEN; ++i)
      sub_vec_sum += sub_vec[i];

    atomicAdd(rhs, sub_vec_sum);
  }
}

__global__
void kernel_inf_norm_vec(float *lhs, float *rhs) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;

  __shared__ float sub_vec[SUB_VECTOR_LEN];
  sub_vec[threadIdx.x] = fabs(lhs[index]);

  __syncthreads();

  if (threadIdx.x == 0) {
    float sub_vec_max = 0.0f;
    for (int i = 0; i < SUB_VECTOR_LEN; ++i)
      sub_vec_max = fmaxf(sub_vec_max, sub_vec[i]);

    atomicMaxf(rhs, sub_vec_max);
  }
}

	.file	"tmpxft_003650a7_00000000-6_kernels_linear.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9sub_block6Matrixii
	.type	_Z9sub_block6Matrixii, @function
_Z9sub_block6Matrixii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z9sub_block6Matrixii, .-_Z9sub_block6Matrixii
	.globl	_Z10atomicMaxfPff
	.type	_Z10atomicMaxfPff, @function
_Z10atomicMaxfPff:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z10atomicMaxfPff, .-_Z10atomicMaxfPff
	.globl	_Z40__device_stub__Z14kernel_eq_matsPfS_mfPbPfS_mfPb
	.type	_Z40__device_stub__Z14kernel_eq_matsPfS_mfPbPfS_mfPb, @function
_Z40__device_stub__Z14kernel_eq_matsPfS_mfPbPfS_mfPb:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z14kernel_eq_matsPfS_mfPb(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L6:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z40__device_stub__Z14kernel_eq_matsPfS_mfPbPfS_mfPb, .-_Z40__device_stub__Z14kernel_eq_matsPfS_mfPbPfS_mfPb
	.globl	_Z14kernel_eq_matsPfS_mfPb
	.type	_Z14kernel_eq_matsPfS_mfPb, @function
_Z14kernel_eq_matsPfS_mfPb:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z14kernel_eq_matsPfS_mfPbPfS_mfPb
	.cfi_endproc
.LFE2035:
	.size	_Z14kernel_eq_matsPfS_mfPb, .-_Z14kernel_eq_matsPfS_mfPb
	.globl	_Z40__device_stub__Z15kernel_add_matsPfS_S_mPfS_S_m
	.type	_Z40__device_stub__Z15kernel_add_matsPfS_S_mPfS_S_m, @function
_Z40__device_stub__Z15kernel_add_matsPfS_S_mPfS_S_m:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15kernel_add_matsPfS_S_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z40__device_stub__Z15kernel_add_matsPfS_S_mPfS_S_m, .-_Z40__device_stub__Z15kernel_add_matsPfS_S_mPfS_S_m
	.globl	_Z15kernel_add_matsPfS_S_m
	.type	_Z15kernel_add_matsPfS_S_m, @function
_Z15kernel_add_matsPfS_S_m:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15kernel_add_matsPfS_S_mPfS_S_m
	.cfi_endproc
.LFE2037:
	.size	_Z15kernel_add_matsPfS_S_m, .-_Z15kernel_add_matsPfS_S_m
	.globl	_Z45__device_stub__Z21kernel_mul_scalar_matfPfS_mfPfS_m
	.type	_Z45__device_stub__Z21kernel_mul_scalar_matfPfS_mfPfS_m, @function
_Z45__device_stub__Z21kernel_mul_scalar_matfPfS_mfPfS_m:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 8(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	40(%rsp), %rdx
	movss	%xmm0, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21kernel_mul_scalar_matfPfS_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L17:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z45__device_stub__Z21kernel_mul_scalar_matfPfS_mfPfS_m, .-_Z45__device_stub__Z21kernel_mul_scalar_matfPfS_mfPfS_m
	.globl	_Z21kernel_mul_scalar_matfPfS_m
	.type	_Z21kernel_mul_scalar_matfPfS_m, @function
_Z21kernel_mul_scalar_matfPfS_m:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z21kernel_mul_scalar_matfPfS_mfPfS_m
	.cfi_endproc
.LFE2039:
	.size	_Z21kernel_mul_scalar_matfPfS_m, .-_Z21kernel_mul_scalar_matfPfS_m
	.globl	_Z44__device_stub__Z15kernel_mul_mats6MatrixS_S_R6MatrixS0_S0_
	.type	_Z44__device_stub__Z15kernel_mul_mats6MatrixS_S_R6MatrixS0_S0_, @function
_Z44__device_stub__Z15kernel_mul_mats6MatrixS_S_R6MatrixS0_S0_:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 72(%rsp)
	leaq	16(%rsp), %rdi
	leaq	28(%rsp), %rsi
	movq	%rdx, 80(%rsp)
	movq	%rsp, %rdx
	movq	%rax, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	8(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z15kernel_mul_mats6MatrixS_S_(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 128
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L22:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z44__device_stub__Z15kernel_mul_mats6MatrixS_S_R6MatrixS0_S0_, .-_Z44__device_stub__Z15kernel_mul_mats6MatrixS_S_R6MatrixS0_S0_
	.globl	_Z15kernel_mul_mats6MatrixS_S_
	.type	_Z15kernel_mul_mats6MatrixS_S_, @function
_Z15kernel_mul_mats6MatrixS_S_:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	64(%rsp), %rdx
	leaq	40(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	_Z44__device_stub__Z15kernel_mul_mats6MatrixS_S_R6MatrixS0_S0_
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z15kernel_mul_mats6MatrixS_S_, .-_Z15kernel_mul_mats6MatrixS_S_
	.globl	_Z47__device_stub__Z20kernel_transpose_mat6MatrixS_R6MatrixS0_
	.type	_Z47__device_stub__Z20kernel_transpose_mat6MatrixS_R6MatrixS0_, @function
_Z47__device_stub__Z20kernel_transpose_mat6MatrixS_R6MatrixS0_:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rcx
	movq	%rdi, 72(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 80(%rsp)
	leaq	8(%rsp), %rdx
	leaq	36(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movq	%rax, 24(%rsp)
	movl	$1, 32(%rsp)
	movq	%rax, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	16(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z20kernel_transpose_mat6MatrixS_(%rip), %rdi
	pushq	16(%rsp)
	.cfi_def_cfa_offset 128
	movq	52(%rsp), %rcx
	movl	60(%rsp), %r8d
	movq	40(%rsp), %rsi
	movl	48(%rsp), %edx
	leaq	88(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L28:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z47__device_stub__Z20kernel_transpose_mat6MatrixS_R6MatrixS0_, .-_Z47__device_stub__Z20kernel_transpose_mat6MatrixS_R6MatrixS0_
	.globl	_Z20kernel_transpose_mat6MatrixS_
	.type	_Z20kernel_transpose_mat6MatrixS_, @function
_Z20kernel_transpose_mat6MatrixS_:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	40(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	_Z47__device_stub__Z20kernel_transpose_mat6MatrixS_R6MatrixS0_
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z20kernel_transpose_mat6MatrixS_, .-_Z20kernel_transpose_mat6MatrixS_
	.globl	_Z39__device_stub__Z15kernel_dot_vecsPfS_S_PfS_S_
	.type	_Z39__device_stub__Z15kernel_dot_vecsPfS_S_PfS_S_, @function
_Z39__device_stub__Z15kernel_dot_vecsPfS_S_PfS_S_:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15kernel_dot_vecsPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L34:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z39__device_stub__Z15kernel_dot_vecsPfS_S_PfS_S_, .-_Z39__device_stub__Z15kernel_dot_vecsPfS_S_PfS_S_
	.globl	_Z15kernel_dot_vecsPfS_S_
	.type	_Z15kernel_dot_vecsPfS_S_, @function
_Z15kernel_dot_vecsPfS_S_:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15kernel_dot_vecsPfS_S_PfS_S_
	.cfi_endproc
.LFE2045:
	.size	_Z15kernel_dot_vecsPfS_S_, .-_Z15kernel_dot_vecsPfS_S_
	.globl	_Z40__device_stub__Z17kernel_p_norm_vecPffS_PffS_
	.type	_Z40__device_stub__Z17kernel_p_norm_vecPffS_PffS_, @function
_Z40__device_stub__Z17kernel_p_norm_vecPffS_PffS_:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17kernel_p_norm_vecPffS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L39:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z40__device_stub__Z17kernel_p_norm_vecPffS_PffS_, .-_Z40__device_stub__Z17kernel_p_norm_vecPffS_PffS_
	.globl	_Z17kernel_p_norm_vecPffS_
	.type	_Z17kernel_p_norm_vecPffS_, @function
_Z17kernel_p_norm_vecPffS_:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17kernel_p_norm_vecPffS_PffS_
	.cfi_endproc
.LFE2047:
	.size	_Z17kernel_p_norm_vecPffS_, .-_Z17kernel_p_norm_vecPffS_
	.globl	_Z41__device_stub__Z19kernel_inf_norm_vecPfS_PfS_
	.type	_Z41__device_stub__Z19kernel_inf_norm_vecPfS_PfS_, @function
_Z41__device_stub__Z19kernel_inf_norm_vecPfS_PfS_:
.LFB2048:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z19kernel_inf_norm_vecPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L44:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z41__device_stub__Z19kernel_inf_norm_vecPfS_PfS_, .-_Z41__device_stub__Z19kernel_inf_norm_vecPfS_PfS_
	.globl	_Z19kernel_inf_norm_vecPfS_
	.type	_Z19kernel_inf_norm_vecPfS_, @function
_Z19kernel_inf_norm_vecPfS_:
.LFB2049:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z19kernel_inf_norm_vecPfS_PfS_
	.cfi_endproc
.LFE2049:
	.size	_Z19kernel_inf_norm_vecPfS_, .-_Z19kernel_inf_norm_vecPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19kernel_inf_norm_vecPfS_"
.LC1:
	.string	"_Z17kernel_p_norm_vecPffS_"
.LC2:
	.string	"_Z15kernel_dot_vecsPfS_S_"
.LC3:
	.string	"_Z20kernel_transpose_mat6MatrixS_"
.LC4:
	.string	"_Z15kernel_mul_mats6MatrixS_S_"
.LC5:
	.string	"_Z21kernel_mul_scalar_matfPfS_m"
.LC6:
	.string	"_Z15kernel_add_matsPfS_S_m"
.LC7:
	.string	"_Z14kernel_eq_matsPfS_mfPb"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2051:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19kernel_inf_norm_vecPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17kernel_p_norm_vecPffS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15kernel_dot_vecsPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20kernel_transpose_mat6MatrixS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15kernel_mul_mats6MatrixS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z21kernel_mul_scalar_matfPfS_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15kernel_add_matsPfS_S_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14kernel_eq_matsPfS_mfPb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2051:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	SUB_VECTOR_LEN
	.section	.rodata
	.align 8
	.type	SUB_VECTOR_LEN, @object
	.size	SUB_VECTOR_LEN, 8
SUB_VECTOR_LEN:
	.quad	256
	.globl	SUB_MATRIX_DIM
	.align 8
	.type	SUB_MATRIX_DIM, @object
	.size	SUB_MATRIX_DIM, 8
SUB_MATRIX_DIM:
	.quad	32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "math.h"

extern "C" const size_t SUB_MATRIX_DIM = 32;
extern "C" const size_t SUB_VECTOR_LEN = 256;

typedef struct {
  size_t rows;
  size_t cols;
  float *elements;
} Matrix;

__device__ float *sub_block(Matrix m, int block_row, int block_col) {
  return m.elements + (block_row * SUB_MATRIX_DIM * m.cols) +
         (block_col * SUB_MATRIX_DIM);
}

__device__ float atomicMaxf(float *addr, float val) {
  return val >= 0
    ? __int_as_float(atomicMax((int *)addr, __float_as_int(val)))
    : __uint_as_float(atomicMax((unsigned int *)addr, __float_as_uint(val)));
}

__global__
void kernel_eq_mats(float *lhs, float *rhs, size_t len, float epsilon, bool *equal) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; *equal && i < len; i += stride)
    if (fabs(lhs[i] - rhs[i]) >= epsilon)
      *equal = false;
}

__global__
void kernel_add_mats(float *lhs1, float *lhs2, float *rhs, size_t len) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < len; i += stride)
    rhs[i] = lhs1[i] + lhs2[i];
}

__global__
void kernel_mul_scalar_mat(float scalar, float *lhs, float *rhs, size_t len) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < len; i += stride)
    rhs[i] = scalar * lhs[i];
}

__global__
void kernel_mul_mats(Matrix lhs1, Matrix lhs2, Matrix rhs) {
  int block_row = blockIdx.y;
  int block_col = blockIdx.x;

  int thread_row = threadIdx.y;
  int thread_col = threadIdx.x;

  float *rhs_sub = sub_block(rhs, block_row, block_col);

  float rhs_elem_val = 0;

  int block_cols =
      (lhs1.cols / SUB_MATRIX_DIM) + (lhs1.cols % SUB_MATRIX_DIM != 0);
  for (int sub_i = 0; sub_i < block_cols; ++sub_i) {
    float *lhs1_sub = sub_block(lhs1, block_row, sub_i);
    float *lhs2_sub = sub_block(lhs2, sub_i, block_col);

    __shared__ float shared_lhs1_sub[SUB_MATRIX_DIM][SUB_MATRIX_DIM];
    __shared__ float shared_lhs2_sub[SUB_MATRIX_DIM][SUB_MATRIX_DIM];

    shared_lhs1_sub[thread_row][thread_col]
      = lhs1_sub[thread_row * lhs1.cols + thread_col];
    shared_lhs2_sub[thread_row][thread_col]
      = lhs2_sub[thread_row * lhs2.cols + thread_col];

    __syncthreads();

    for (int rhs_i = 0; rhs_i < SUB_MATRIX_DIM; ++rhs_i) {
      rhs_elem_val +=
        shared_lhs1_sub[thread_row][rhs_i] * shared_lhs2_sub[rhs_i][thread_col];
    }

    __syncthreads();
  }

  rhs_sub[thread_row * rhs.cols + thread_col] = rhs_elem_val;
}

__global__
void kernel_transpose_mat(Matrix lhs, Matrix rhs) {
  int block_row = blockIdx.y;
  int block_col = blockIdx.x;

  int thread_row = threadIdx.y;
  int thread_col = threadIdx.x;

  float *lhs_sub = sub_block(lhs, block_row, block_col);
  float *rhs_sub = sub_block(rhs, block_col, block_row);

  __shared__ float shared_lhs_sub[SUB_MATRIX_DIM][SUB_MATRIX_DIM];

  shared_lhs_sub[thread_row][thread_col]
    = lhs_sub[thread_row * lhs.cols + thread_col];

  __syncthreads();

  rhs_sub[thread_col * rhs.cols + thread_row]
    = shared_lhs_sub[thread_row][thread_col];
}

__global__
void kernel_dot_vecs(float *lhs1, float *lhs2, float *rhs) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;

  __shared__ float sub_vec[SUB_VECTOR_LEN];
  sub_vec[threadIdx.x] = lhs1[index] * lhs2[index];

  __syncthreads();

  if (threadIdx.x == 0) {
    float sub_vec_sum = 0.0f;
    for (int i = 0; i < SUB_VECTOR_LEN; ++i)
      sub_vec_sum += sub_vec[i];

    atomicAdd(rhs, sub_vec_sum);
  }
}

__global__
void kernel_p_norm_vec(float *lhs, float p, float *rhs) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;

  __shared__ float sub_vec[SUB_VECTOR_LEN];
  sub_vec[threadIdx.x] = powf(fabsf(lhs[index]), p);

  __syncthreads();

  if (threadIdx.x == 0) {
    float sub_vec_sum = 0.0f;
    for (int i = 0; i < SUB_VECTOR_LEN; ++i)
      sub_vec_sum += sub_vec[i];

    atomicAdd(rhs, sub_vec_sum);
  }
}

__global__
void kernel_inf_norm_vec(float *lhs, float *rhs) {
  int index = blockDim.x * blockIdx.x + threadIdx.x;

  __shared__ float sub_vec[SUB_VECTOR_LEN];
  sub_vec[threadIdx.x] = fabs(lhs[index]);

  __syncthreads();

  if (threadIdx.x == 0) {
    float sub_vec_max = 0.0f;
    for (int i = 0; i < SUB_VECTOR_LEN; ++i)
      sub_vec_max = fmaxf(sub_vec_max, sub_vec[i]);

    atomicMaxf(rhs, sub_vec_max);
  }
}

	.text
	.file	"kernels_linear.hip"
	.globl	_Z29__device_stub__kernel_eq_matsPfS_mfPb # -- Begin function _Z29__device_stub__kernel_eq_matsPfS_mfPb
	.type	_Z29__device_stub__kernel_eq_matsPfS_mfPb,@function
_Z29__device_stub__kernel_eq_matsPfS_mfPb: # @_Z29__device_stub__kernel_eq_matsPfS_mfPb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	32(%rsp), %r8
	movq	%rcx, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14kernel_eq_matsPfS_mfPb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__kernel_eq_matsPfS_mfPb, .Lfunc_end0-_Z29__device_stub__kernel_eq_matsPfS_mfPb
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__kernel_add_matsPfS_S_m # -- Begin function _Z30__device_stub__kernel_add_matsPfS_S_m
	.type	_Z30__device_stub__kernel_add_matsPfS_S_m,@function
_Z30__device_stub__kernel_add_matsPfS_S_m: # @_Z30__device_stub__kernel_add_matsPfS_S_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15kernel_add_matsPfS_S_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__kernel_add_matsPfS_S_m, .Lfunc_end1-_Z30__device_stub__kernel_add_matsPfS_S_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__kernel_mul_scalar_matfPfS_m # -- Begin function _Z36__device_stub__kernel_mul_scalar_matfPfS_m
	.type	_Z36__device_stub__kernel_mul_scalar_matfPfS_m,@function
_Z36__device_stub__kernel_mul_scalar_matfPfS_m: # @_Z36__device_stub__kernel_mul_scalar_matfPfS_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21kernel_mul_scalar_matfPfS_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z36__device_stub__kernel_mul_scalar_matfPfS_m, .Lfunc_end2-_Z36__device_stub__kernel_mul_scalar_matfPfS_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__kernel_mul_mats6MatrixS_S_ # -- Begin function _Z30__device_stub__kernel_mul_mats6MatrixS_S_
	.type	_Z30__device_stub__kernel_mul_mats6MatrixS_S_,@function
_Z30__device_stub__kernel_mul_mats6MatrixS_S_: # @_Z30__device_stub__kernel_mul_mats6MatrixS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	128(%rsp), %rax
	leaq	48(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	152(%rsp), %rax
	movq	%rax, 8(%rbx)
	leaq	176(%rsp), %rax
	movq	%rax, 16(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15kernel_mul_mats6MatrixS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__kernel_mul_mats6MatrixS_S_, .Lfunc_end3-_Z30__device_stub__kernel_mul_mats6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__kernel_transpose_mat6MatrixS_ # -- Begin function _Z35__device_stub__kernel_transpose_mat6MatrixS_
	.type	_Z35__device_stub__kernel_transpose_mat6MatrixS_,@function
_Z35__device_stub__kernel_transpose_mat6MatrixS_: # @_Z35__device_stub__kernel_transpose_mat6MatrixS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	112(%rsp), %rax
	leaq	48(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	136(%rsp), %rax
	movq	%rax, 8(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20kernel_transpose_mat6MatrixS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z35__device_stub__kernel_transpose_mat6MatrixS_, .Lfunc_end4-_Z35__device_stub__kernel_transpose_mat6MatrixS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__kernel_dot_vecsPfS_S_ # -- Begin function _Z30__device_stub__kernel_dot_vecsPfS_S_
	.type	_Z30__device_stub__kernel_dot_vecsPfS_S_,@function
_Z30__device_stub__kernel_dot_vecsPfS_S_: # @_Z30__device_stub__kernel_dot_vecsPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15kernel_dot_vecsPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z30__device_stub__kernel_dot_vecsPfS_S_, .Lfunc_end5-_Z30__device_stub__kernel_dot_vecsPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__kernel_p_norm_vecPffS_ # -- Begin function _Z32__device_stub__kernel_p_norm_vecPffS_
	.type	_Z32__device_stub__kernel_p_norm_vecPffS_,@function
_Z32__device_stub__kernel_p_norm_vecPffS_: # @_Z32__device_stub__kernel_p_norm_vecPffS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	32(%rsp), %rdx
	movq	%rsi, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17kernel_p_norm_vecPffS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z32__device_stub__kernel_p_norm_vecPffS_, .Lfunc_end6-_Z32__device_stub__kernel_p_norm_vecPffS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__kernel_inf_norm_vecPfS_ # -- Begin function _Z34__device_stub__kernel_inf_norm_vecPfS_
	.type	_Z34__device_stub__kernel_inf_norm_vecPfS_,@function
_Z34__device_stub__kernel_inf_norm_vecPfS_: # @_Z34__device_stub__kernel_inf_norm_vecPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19kernel_inf_norm_vecPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z34__device_stub__kernel_inf_norm_vecPfS_, .Lfunc_end7-_Z34__device_stub__kernel_inf_norm_vecPfS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14kernel_eq_matsPfS_mfPb, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15kernel_add_matsPfS_S_m, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21kernel_mul_scalar_matfPfS_m, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15kernel_mul_mats6MatrixS_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20kernel_transpose_mat6MatrixS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15kernel_dot_vecsPfS_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17kernel_p_norm_vecPffS_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19kernel_inf_norm_vecPfS_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	SUB_MATRIX_DIM,@object          # @SUB_MATRIX_DIM
	.section	.rodata,"a",@progbits
	.globl	SUB_MATRIX_DIM
	.p2align	3, 0x0
SUB_MATRIX_DIM:
	.quad	32                              # 0x20
	.size	SUB_MATRIX_DIM, 8

	.type	SUB_VECTOR_LEN,@object          # @SUB_VECTOR_LEN
	.globl	SUB_VECTOR_LEN
	.p2align	3, 0x0
SUB_VECTOR_LEN:
	.quad	256                             # 0x100
	.size	SUB_VECTOR_LEN, 8

	.type	_Z14kernel_eq_matsPfS_mfPb,@object # @_Z14kernel_eq_matsPfS_mfPb
	.globl	_Z14kernel_eq_matsPfS_mfPb
	.p2align	3, 0x0
_Z14kernel_eq_matsPfS_mfPb:
	.quad	_Z29__device_stub__kernel_eq_matsPfS_mfPb
	.size	_Z14kernel_eq_matsPfS_mfPb, 8

	.type	_Z15kernel_add_matsPfS_S_m,@object # @_Z15kernel_add_matsPfS_S_m
	.globl	_Z15kernel_add_matsPfS_S_m
	.p2align	3, 0x0
_Z15kernel_add_matsPfS_S_m:
	.quad	_Z30__device_stub__kernel_add_matsPfS_S_m
	.size	_Z15kernel_add_matsPfS_S_m, 8

	.type	_Z21kernel_mul_scalar_matfPfS_m,@object # @_Z21kernel_mul_scalar_matfPfS_m
	.globl	_Z21kernel_mul_scalar_matfPfS_m
	.p2align	3, 0x0
_Z21kernel_mul_scalar_matfPfS_m:
	.quad	_Z36__device_stub__kernel_mul_scalar_matfPfS_m
	.size	_Z21kernel_mul_scalar_matfPfS_m, 8

	.type	_Z15kernel_mul_mats6MatrixS_S_,@object # @_Z15kernel_mul_mats6MatrixS_S_
	.globl	_Z15kernel_mul_mats6MatrixS_S_
	.p2align	3, 0x0
_Z15kernel_mul_mats6MatrixS_S_:
	.quad	_Z30__device_stub__kernel_mul_mats6MatrixS_S_
	.size	_Z15kernel_mul_mats6MatrixS_S_, 8

	.type	_Z20kernel_transpose_mat6MatrixS_,@object # @_Z20kernel_transpose_mat6MatrixS_
	.globl	_Z20kernel_transpose_mat6MatrixS_
	.p2align	3, 0x0
_Z20kernel_transpose_mat6MatrixS_:
	.quad	_Z35__device_stub__kernel_transpose_mat6MatrixS_
	.size	_Z20kernel_transpose_mat6MatrixS_, 8

	.type	_Z15kernel_dot_vecsPfS_S_,@object # @_Z15kernel_dot_vecsPfS_S_
	.globl	_Z15kernel_dot_vecsPfS_S_
	.p2align	3, 0x0
_Z15kernel_dot_vecsPfS_S_:
	.quad	_Z30__device_stub__kernel_dot_vecsPfS_S_
	.size	_Z15kernel_dot_vecsPfS_S_, 8

	.type	_Z17kernel_p_norm_vecPffS_,@object # @_Z17kernel_p_norm_vecPffS_
	.globl	_Z17kernel_p_norm_vecPffS_
	.p2align	3, 0x0
_Z17kernel_p_norm_vecPffS_:
	.quad	_Z32__device_stub__kernel_p_norm_vecPffS_
	.size	_Z17kernel_p_norm_vecPffS_, 8

	.type	_Z19kernel_inf_norm_vecPfS_,@object # @_Z19kernel_inf_norm_vecPfS_
	.globl	_Z19kernel_inf_norm_vecPfS_
	.p2align	3, 0x0
_Z19kernel_inf_norm_vecPfS_:
	.quad	_Z34__device_stub__kernel_inf_norm_vecPfS_
	.size	_Z19kernel_inf_norm_vecPfS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14kernel_eq_matsPfS_mfPb"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15kernel_add_matsPfS_S_m"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z21kernel_mul_scalar_matfPfS_m"
	.size	.L__unnamed_3, 32

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15kernel_mul_mats6MatrixS_S_"
	.size	.L__unnamed_4, 31

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z20kernel_transpose_mat6MatrixS_"
	.size	.L__unnamed_5, 34

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z15kernel_dot_vecsPfS_S_"
	.size	.L__unnamed_6, 26

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z17kernel_p_norm_vecPffS_"
	.size	.L__unnamed_7, 27

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z19kernel_inf_norm_vecPfS_"
	.size	.L__unnamed_8, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__kernel_eq_matsPfS_mfPb
	.addrsig_sym _Z30__device_stub__kernel_add_matsPfS_S_m
	.addrsig_sym _Z36__device_stub__kernel_mul_scalar_matfPfS_m
	.addrsig_sym _Z30__device_stub__kernel_mul_mats6MatrixS_S_
	.addrsig_sym _Z35__device_stub__kernel_transpose_mat6MatrixS_
	.addrsig_sym _Z30__device_stub__kernel_dot_vecsPfS_S_
	.addrsig_sym _Z32__device_stub__kernel_p_norm_vecPffS_
	.addrsig_sym _Z34__device_stub__kernel_inf_norm_vecPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14kernel_eq_matsPfS_mfPb
	.addrsig_sym _Z15kernel_add_matsPfS_S_m
	.addrsig_sym _Z21kernel_mul_scalar_matfPfS_m
	.addrsig_sym _Z15kernel_mul_mats6MatrixS_S_
	.addrsig_sym _Z20kernel_transpose_mat6MatrixS_
	.addrsig_sym _Z15kernel_dot_vecsPfS_S_
	.addrsig_sym _Z17kernel_p_norm_vecPffS_
	.addrsig_sym _Z19kernel_inf_norm_vecPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14kernel_eq_matsPfS_mfPb ; -- Begin function _Z14kernel_eq_matsPfS_mfPb
	.globl	_Z14kernel_eq_matsPfS_mfPb
	.p2align	8
	.type	_Z14kernel_eq_matsPfS_mfPb,@function
_Z14kernel_eq_matsPfS_mfPb:             ; @_Z14kernel_eq_matsPfS_mfPb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x34
	v_mov_b32_e32 v5, 0
	s_load_b64 s[10:11], s[0:1], 0x10
	s_add_u32 s4, s0, 40
	s_addc_u32 s5, s1, 0
	s_mov_b32 s14, 0
	s_waitcnt lgkmcnt(0)
	global_load_u8 v6, v5, s[8:9]
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[3:4]
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e64 s2, 0, v6
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s2
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[4:5], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s1, s[0:1], 0x18
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s15, s2
	s_mul_i32 s2, s2, s3
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[2:3], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v7, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b32 v0, v[7:8], off
	global_load_b32 v2, v[9:10], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e64 |v0|, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v6, 0
	global_store_b8 v5, v6, s[8:9]
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v2, 31, v1
	v_and_b32_e32 v0, 0xff, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[1:2]
	v_cmp_eq_u16_e64 s0, 0, v0
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s14, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow31
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14kernel_eq_matsPfS_mfPb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14kernel_eq_matsPfS_mfPb, .Lfunc_end0-_Z14kernel_eq_matsPfS_mfPb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15kernel_add_matsPfS_S_m ; -- Begin function _Z15kernel_add_matsPfS_S_m
	.globl	_Z15kernel_add_matsPfS_S_m
	.p2align	8
	.type	_Z15kernel_add_matsPfS_S_m,@function
_Z15kernel_add_matsPfS_S_m:             ; @_Z15kernel_add_matsPfS_S_m
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[10:11], v[1:2]
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s15, s0
	s_mul_i32 s1, s0, s2
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_ashr_i32 s2, s1, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v3
	v_sub_co_u32 v3, vcc_lo, v3, s1
	v_subrev_co_ci_u32_e32 v4, vcc_lo, s2, v0, vcc_lo
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s1
	global_load_b32 v9, v[5:6], off
	global_load_b32 v7, v[7:8], off
	v_add_co_ci_u32_e32 v4, vcc_lo, s2, v4, vcc_lo
	v_add_co_u32 v5, s0, s8, v0
	v_ashrrev_i32_e32 v2, 31, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[3:4]
	v_add_co_ci_u32_e64 v6, s0, s9, v1, s0
	v_mov_b32_e32 v1, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v9, v7
	global_store_b32 v[5:6], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow27
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15kernel_add_matsPfS_S_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15kernel_add_matsPfS_S_m, .Lfunc_end1-_Z15kernel_add_matsPfS_S_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21kernel_mul_scalar_matfPfS_m ; -- Begin function _Z21kernel_mul_scalar_matfPfS_m
	.globl	_Z21kernel_mul_scalar_matfPfS_m
	.p2align	8
	.type	_Z21kernel_mul_scalar_matfPfS_m,@function
_Z21kernel_mul_scalar_matfPfS_m:        ; @_Z21kernel_mul_scalar_matfPfS_m
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s6, 0xffff
	s_mov_b32 s6, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmpx_gt_u64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[4:5], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s1, s[0:1], 0x0
	s_mov_b32 s10, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s15, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s15, s8, v[0:1]
	s_mul_i32 s8, s9, s8
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v3
	v_sub_co_u32 v3, vcc_lo, v3, s8
	v_subrev_co_ci_u32_e32 v4, vcc_lo, s9, v0, vcc_lo
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_b32 v7, v[5:6], off
	v_add_co_u32 v5, s0, s6, v0
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
	v_ashrrev_i32_e32 v2, 31, v3
	v_add_co_ci_u32_e64 v6, s0, s7, v1, s0
	v_mov_b32_e32 v1, v3
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, s1, v7
	global_store_b32 v[5:6], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %Flow24
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21kernel_mul_scalar_matfPfS_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z21kernel_mul_scalar_matfPfS_m, .Lfunc_end2-_Z21kernel_mul_scalar_matfPfS_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 264
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15kernel_mul_mats6MatrixS_S_ ; -- Begin function _Z15kernel_mul_mats6MatrixS_S_
	.globl	_Z15kernel_mul_mats6MatrixS_S_
	.p2align	8
	.type	_Z15kernel_mul_mats6MatrixS_S_,@function
_Z15kernel_mul_mats6MatrixS_S_:         ; @_Z15kernel_mul_mats6MatrixS_S_
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x8
	s_mov_b32 s5, 0
	s_mov_b32 s10, s15
	s_ashr_i32 s11, s15, 31
	s_ashr_i32 s15, s14, 31
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	v_alignbit_b32 v1, s3, s2, 5
	s_and_b32 s4, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cselect_b32 s6, -1, 0
	v_readfirstlane_b32 s4, v1
	s_cmp_lg_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_addc_u32 s12, s4, 0
	s_cmp_gt_i32 s12, 0
	s_cbranch_scc1 .LBB3_2
; %bb.1:                                ; %.._crit_edge_crit_edge
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[6:7], s[10:11], 5
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
	s_branch .LBB3_3
.LBB3_2:
	s_mov_b32 s5, -1
                                        ; implicit-def: $sgpr6_sgpr7
                                        ; implicit-def: $vgpr1_vgpr2
.LBB3_3:                                ; %Flow75
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_lshl_b64 s[8:9], s[14:15], 5
	s_cbranch_vccnz .LBB3_8
; %bb.4:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x20
	s_load_b64 s[14:15], s[0:1], 0x10
	v_mad_u64_u32 v[8:9], null, s2, v3, 0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 7, v3
	v_alignbit_b32 v1, s11, s10, 27
	s_lshl_b64 s[16:17], s[8:9], 2
	v_lshlrev_b32_e32 v16, 2, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v4, v9
	v_readfirstlane_b32 s13, v1
	v_mov_b32_e32 v1, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v7, 0x1000, v16
	v_add_nc_u32_e32 v6, v5, v16
	v_mad_u64_u32 v[12:13], null, s3, v3, v[4:5]
	s_mul_i32 s13, s13, s2
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[10:11], null, s4, v3, 0
	s_add_u32 s16, s6, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v9, v12
	s_addc_u32 s17, s7, s17
	s_lshl_b64 s[6:7], s[10:11], 5
	s_mul_i32 s3, s6, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v4, v11
	s_mul_hi_u32 s10, s6, s2
	s_mul_i32 s2, s6, s2
	s_add_i32 s3, s10, s3
	s_add_i32 s3, s3, s13
	v_mad_u64_u32 v[13:14], null, s5, v3, v[4:5]
	v_lshlrev_b64 v[14:15], 2, v[8:9]
	s_lshl_b64 s[2:3], s[2:3], 2
	v_add_nc_u32_e32 v8, v7, v5
	s_add_u32 s2, s14, s2
	s_addc_u32 s3, s15, s3
	s_lshl_b64 s[4:5], s[4:5], 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v13
	v_add_co_u32 v4, vcc_lo, s2, v14
	v_lshlrev_b64 v[9:10], 2, v[10:11]
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v15, vcc_lo
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 s2, s3
	v_add_co_u32 v12, vcc_lo, s16, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, v4, v16
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v11, vcc_lo, v12, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	v_mov_b32_e32 v4, v2
.LBB3_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_6 Depth 2
	s_mul_i32 s10, s5, s2
	s_mul_hi_u32 s11, s4, s2
	s_lshl_b64 s[14:15], s[2:3], 7
	s_add_i32 s11, s11, s10
	s_mul_i32 s10, s4, s2
	v_add_co_u32 v13, vcc_lo, v9, s14
	s_lshl_b64 s[10:11], s[10:11], 2
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v10, vcc_lo
	v_add_co_u32 v15, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v12, vcc_lo
	global_load_b32 v14, v[13:14], off
	global_load_b32 v15, v[15:16], off
	v_mov_b32_e32 v13, v7
	s_mov_b32 s10, 0
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_6:                                ;   Parent Loop BB3_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v14, s10, v5
	s_add_i32 s10, s10, 4
	ds_load_b32 v15, v13
	ds_load_b32 v14, v14
	v_add_nc_u32_e32 v13, 0x80, v13
	s_cmpk_eq_i32 s10, 0x80
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v4, v14, v15
	s_cbranch_scc0 .LBB3_6
; %bb.7:                                ;   in Loop: Header=BB3_5 Depth=1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s12
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB3_5
	s_branch .LBB3_9
.LBB3_8:
	v_mov_b32_e32 v4, s5
.LBB3_9:                                ; %Flow76
	s_load_b128 s[0:3], s[0:1], 0x38
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v7, s1, v3
	v_mul_lo_u32 v2, s0, v2
	v_mad_u64_u32 v[5:6], null, s0, v3, 0
	s_mul_i32 s4, s6, s1
	s_mul_hi_u32 s5, s6, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_add_i32 s1, s5, s4
	s_mul_i32 s4, s7, s0
	s_mul_i32 s0, s6, s0
	v_add3_u32 v6, v6, v2, v7
	s_add_i32 s1, s1, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	s_lshl_b64 s[0:1], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15kernel_mul_mats6MatrixS_S_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 72
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15kernel_mul_mats6MatrixS_S_, .Lfunc_end3-_Z15kernel_mul_mats6MatrixS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 776
; NumSgprs: 20
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20kernel_transpose_mat6MatrixS_ ; -- Begin function _Z20kernel_transpose_mat6MatrixS_
	.globl	_Z20kernel_transpose_mat6MatrixS_
	.p2align	8
	.type	_Z20kernel_transpose_mat6MatrixS_,@function
_Z20kernel_transpose_mat6MatrixS_:      ; @_Z20kernel_transpose_mat6MatrixS_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_bfe_u32 v5, v0, 10, 10
	s_mov_b32 s8, s15
	s_ashr_i32 s9, s15, 31
	v_and_b32_e32 v6, 0x3ff, v0
	v_alignbit_b32 v3, s9, s8, 27
	s_lshl_b64 s[10:11], s[8:9], 5
	s_load_b128 s[0:3], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s11, v3
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s4, v5, 0
	s_mul_i32 s12, s10, s5
	s_mul_i32 s11, s11, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s5, v5, v[2:3]
	s_mul_hi_u32 s5, s10, s4
	s_mul_i32 s4, s10, s4
	s_add_i32 s5, s5, s12
	v_lshlrev_b32_e32 v4, 2, v6
	s_add_i32 s5, s5, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[4:5], s[4:5], 2
	v_mov_b32_e32 v2, v3
	s_add_u32 s10, s6, s4
	s_addc_u32 s11, s7, s5
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_lshl_b64 s[4:5], s[14:15], 7
	s_lshl_b64 s[6:7], s[14:15], 5
	s_add_u32 s4, s10, s4
	s_addc_u32 s5, s11, s5
	v_alignbit_b32 v2, s15, s14, 27
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s7, v2
	v_add_co_u32 v0, vcc_lo, v0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_mul_i32 s4, s6, s1
	s_mul_hi_u32 s5, s6, s0
	s_mul_i32 s7, s7, s0
	global_load_b32 v7, v[0:1], off
	v_mad_u64_u32 v[0:1], null, s0, v6, 0
	s_mul_i32 s0, s6, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s1, v6, v[1:2]
	v_lshl_add_u32 v3, v5, 7, v4
	s_add_i32 s1, s5, s4
	s_add_i32 s1, s1, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_mov_b32_e32 v1, v2
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	s_lshl_b64 s[0:1], s[8:9], 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v3
	v_lshlrev_b32_e32 v3, 2, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20kernel_transpose_mat6MatrixS_
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z20kernel_transpose_mat6MatrixS_, .Lfunc_end4-_Z20kernel_transpose_mat6MatrixS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15kernel_dot_vecsPfS_S_ ; -- Begin function _Z15kernel_dot_vecsPfS_S_
	.globl	_Z15kernel_dot_vecsPfS_S_
	.p2align	8
	.type	_Z15kernel_dot_vecsPfS_S_,@function
_Z15kernel_dot_vecsPfS_S_:              ; @_Z15kernel_dot_vecsPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v1, v3, v1 :: v_dual_lshlrev_b32 v2, 2, v0
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_6
; %bb.1:                                ; %.preheader.preheader
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
.LBB5_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s2
	s_add_i32 s2, s2, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s2, 0x400
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v1
	s_cbranch_scc0 .LBB5_2
; %bb.3:
	s_mov_b32 s3, exec_lo
	s_mov_b32 s2, 0
	v_mbcnt_lo_u32_b32 v1, s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 s4, exec_lo, vcc_lo
	s_mov_b32 exec_lo, s4
	s_cbranch_execz .LBB5_6
; %bb.4:
	s_load_b32 s4, s[0:1], 0x0
	s_bcnt1_i32_b32 s3, s3
	v_mov_b32_e32 v3, 0
	v_cvt_f32_ubyte0_e32 v1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v2, v0, v1 :: v_dual_mov_b32 v1, s4
.LBB5_5:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v2
	global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB5_5
.LBB5_6:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15kernel_dot_vecsPfS_S_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z15kernel_dot_vecsPfS_S_, .Lfunc_end5-_Z15kernel_dot_vecsPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17kernel_p_norm_vecPffS_ ; -- Begin function _Z17kernel_p_norm_vecPffS_
	.globl	_Z17kernel_p_norm_vecPffS_
	.p2align	8
	.type	_Z17kernel_p_norm_vecPffS_,@function
_Z17kernel_p_norm_vecPffS_:             ; @_Z17kernel_p_norm_vecPffS_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_load_b32 s4, s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e64 s2, |v1|, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, 1.0, s4, s2
	s_mov_b32 s2, 0x3e76c4e1
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_cmp_neq_f32_e64 s3, v2, |v2|
	v_cndmask_b32_e64 v1, 1.0, |v1|, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e32 v3, v1
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v3, v3, v4
	v_add_f32_e32 v6, -1.0, v3
	v_add_f32_e32 v4, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v7, v6, v5 :: v_dual_add_f32 v8, -1.0, v4
	v_mul_f32_e32 v9, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v8
	v_fma_f32 v4, v7, v4, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v7, v3
	v_add_f32_e32 v3, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
	v_sub_f32_e32 v4, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v8
	v_sub_f32_e32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v4, v3
	v_add_f32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v5, v3
	v_add_f32_e32 v4, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v4, v4
	v_sub_f32_e32 v5, v4, v7
	v_sub_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v4, v4, -v6
	v_add_f32_e32 v7, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v4, v7
	v_add_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, s2, v7, 0x3e91f4c4
	v_sub_f32_e32 v6, v7, v6
	v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v7, v8
	v_fma_f32 v6, v7, v8, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, v5, v8 :: v_dual_mul_f32 v11, v4, v7
	v_add_f32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v7, v4, -v11
	v_dual_sub_f32 v9, v8, v9 :: v_dual_fmac_f32 v12, v7, v3
	v_add_f32_e32 v10, 0x3f2aaaaa, v8
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v6, v6, v9
	v_fmac_f32_e32 v12, v5, v4
	v_ldexp_f32 v4, v4, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, 0x31739010, v6
	v_add_f32_e32 v9, 0xbf2aaaaa, v10
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v8
	v_add_f32_e32 v5, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v11, v12 :: v_dual_sub_f32 v8, v10, v5
	v_mul_f32_e32 v9, v7, v5
	v_sub_f32_e32 v10, v7, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v6, v8
	v_fma_f32 v8, v7, v5, -v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v12, v10
	v_fmac_f32_e32 v8, v7, v6
	v_frexp_exp_i32_f32_e32 v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v10, v5
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v9, v8
	v_cvt_f32_i32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v6, v9
	v_add_f32_e32 v7, v4, v6
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, 0x3f317218, v5 :: v_dual_add_f32 v3, v3, v8
	v_fma_f32 v9, 0x3f317218, v5, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_sub_f32 v4, v7, v4
	v_sub_f32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v5
	v_add_f32_e32 v6, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v4, v10
	v_sub_f32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v4, v6
	v_sub_f32_e32 v9, v8, v4
	v_sub_f32_e32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v8, v9
	v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v11
	v_dual_add_f32 v7, v5, v3 :: v_dual_add_f32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v7, v5
	v_add_f32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v6
	v_sub_f32_e32 v3, v3, v6
	v_sub_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v8, v4
	v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v6
	v_add_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v9, v3
	v_dual_sub_f32 v5, v4, v9 :: v_dual_mul_f32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v5
	v_fma_f32 v4, v2, v4, -v6
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v2, v3
	v_add_f32_e32 v3, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v3, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v5
	v_cndmask_b32_e64 v7, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v5|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v5, v7
	v_mul_f32_e32 v9, 0x3fb8aa3b, v8
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v10, 0x3fb8aa3b, v8, -v9
	v_rndne_f32_e32 v11, v9
	v_dual_fmamk_f32 v10, v8, 0x32a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v9, v10
	v_sub_f32_e32 v3, v3, v6
	v_cvt_i32_f32_e32 v6, v11
	v_exp_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v4, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v3, v7, v3 :: v_dual_cndmask_b32 v4, 0, v4
	v_cmp_gt_f32_e32 vcc_lo, 1.0, v1
	v_cndmask_b32_e64 v4, 0x7f800000, v4, s2
	s_xor_b32 s2, s3, vcc_lo
	v_cmp_eq_f32_e64 s3, 1.0, v1
	v_cndmask_b32_e64 v5, |v2|, 0, s2
	v_cmp_gt_f32_e32 vcc_lo, 0, v2
	v_cmp_eq_f32_e64 s2, 0, v1
	v_fma_f32 v3, v4, v3, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v5, v1, s3
	v_cmp_eq_f32_e64 s3, 0x7f800000, v4
	s_xor_b32 s4, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v4, s3
	v_cndmask_b32_e64 v4, 0x7f800000, 0, s4
	v_cmp_class_f32_e64 s4, v2, 0x204
	v_cmp_eq_f32_e64 s3, 0x7f800000, v1
	v_cndmask_b32_e64 v3, |v3|, v5, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 vcc_lo, s2, s3
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_lshlrev_b32_e32 v4, 2, v0
	v_cmp_o_f32_e32 vcc_lo, v1, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v1, 0x7fc00000, v3, vcc_lo
	ds_store_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_6
; %bb.1:                                ; %.preheader.preheader
	v_mov_b32_e32 v0, 0
.LBB6_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s2
	s_add_i32 s2, s2, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s2, 0x400
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v1
	s_cbranch_scc0 .LBB6_2
; %bb.3:
	s_mov_b32 s3, exec_lo
	s_mov_b32 s2, 0
	v_mbcnt_lo_u32_b32 v1, s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 s4, exec_lo, vcc_lo
	s_mov_b32 exec_lo, s4
	s_cbranch_execz .LBB6_6
; %bb.4:
	s_load_b64 s[0:1], s[0:1], 0x10
	s_bcnt1_i32_b32 s3, s3
	v_mov_b32_e32 v3, 0
	v_cvt_f32_ubyte0_e32 v1, s3
	s_waitcnt lgkmcnt(0)
	s_load_b32 s4, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v2, v0, v1 :: v_dual_mov_b32 v1, s4
.LBB6_5:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v2
	global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB6_5
.LBB6_6:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17kernel_p_norm_vecPffS_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z17kernel_p_norm_vecPffS_, .Lfunc_end6-_Z17kernel_p_norm_vecPffS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1360
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19kernel_inf_norm_vecPfS_ ; -- Begin function _Z19kernel_inf_norm_vecPfS_
	.globl	_Z19kernel_inf_norm_vecPfS_
	.p2align	8
	.type	_Z19kernel_inf_norm_vecPfS_,@function
_Z19kernel_inf_norm_vecPfS_:            ; @_Z19kernel_inf_norm_vecPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
	global_load_b32 v1, v[1:2], off
	v_lshlrev_b32_e32 v2, 2, v0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0x7fffffff, v1
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB7_10
; %bb.1:                                ; %.preheader.preheader
	v_mov_b32_e32 v0, 0
.LBB7_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s0 :: v_dual_max_f32 v0, v0, v0
	s_add_i32 s0, s0, 4
	s_cmpk_eq_i32 s0, 0x400
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_max_f32_e32 v1, v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_max_f32_e32 v0, v0, v1
	s_cbranch_scc0 .LBB7_2
; %bb.3:
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, 0, v0
	s_mov_b32 s0, -1
	s_cbranch_vccnz .LBB7_7
; %bb.4:
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB7_6
; %bb.5:
	v_mov_b32_e32 v1, 0
	global_atomic_max_i32 v1, v0, s[2:3]
.LBB7_6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
.LBB7_7:                                ; %Flow19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB7_10
; %bb.8:
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_10
; %bb.9:
	v_mov_b32_e32 v1, 0
	global_atomic_max_u32 v1, v0, s[2:3]
.LBB7_10:                               ; %_Z10atomicMaxfPff.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19kernel_inf_norm_vecPfS_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z19kernel_inf_norm_vecPfS_, .Lfunc_end7-_Z19kernel_inf_norm_vecPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	SUB_MATRIX_DIM          ; @SUB_MATRIX_DIM
	.type	SUB_MATRIX_DIM,@object
	.section	.rodata,"a",@progbits
	.globl	SUB_MATRIX_DIM
	.p2align	3, 0x0
SUB_MATRIX_DIM:
	.quad	32                              ; 0x20
	.size	SUB_MATRIX_DIM, 8

	.protected	SUB_VECTOR_LEN          ; @SUB_VECTOR_LEN
	.type	SUB_VECTOR_LEN,@object
	.globl	SUB_VECTOR_LEN
	.p2align	3, 0x0
SUB_VECTOR_LEN:
	.quad	256                             ; 0x100
	.size	SUB_VECTOR_LEN, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
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