#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void hypterm_0 (double * __restrict__ flux_in_0, double * __restrict__ flux_in_1, double * __restrict__ flux_in_2, double * __restrict__ flux_in_3, double * __restrict__ cons_in_1, double * __restrict__ cons_in_2, double * __restrict__ cons_in_3, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.z);

	double (*flux_0)[308][308] = (double (*)[308][308])flux_in_0;
	double (*flux_1)[308][308] = (double (*)[308][308])flux_in_1;
	double (*flux_2)[308][308] = (double (*)[308][308])flux_in_2;
	double (*flux_3)[308][308] = (double (*)[308][308])flux_in_3;
	double (*cons_1)[308][308] = (double (*)[308][308])cons_in_1;
	double (*cons_2)[308][308] = (double (*)[308][308])cons_in_2;
	double (*cons_3)[308][308] = (double (*)[308][308])cons_in_3;
    double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
    double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
    double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
    double (*q_4)[308][308] = (double (*)[308][308])q_in_4;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
double _t_1_;
double flux_0kc0jc0ic0;
double _t_2_;
double _t_3_;
double _t_4_;
double _t_10_;
double _t_5_;
double _t_7_;
double _t_8_;
double _t_9_;
double _t_12_;
double flux_1kc0jc0ic0;
double _t_13_;
double _t_14_;
double _t_15_;
double _t_32_;
double _t_27_;
double _t_29_;
double _t_30_;
double _t_31_;
double _t_18_;
double _t_16_;
double _t_19_;
double _t_20_;
double _t_21_;
double _t_23_;
double flux_2kc0jc0ic0;
double _t_24_;
double _t_25_;
double _t_26_;
double _t_34_;
double flux_3kc0jc0ic0;
double _t_35_;
double _t_36_;
double _t_37_;
double _t_40_;
double _t_38_;
double _t_41_;
double _t_42_;
double _t_43_;

_t_1_ = -cons_1[k][j][i-1];
_t_1_ += cons_1[k][j][i+1];
flux_0kc0jc0ic0 = dxinv0 * 0.8 * _t_1_;
_t_2_ = -cons_1[k][j][i-2];
_t_2_ += cons_1[k][j][i+2];
flux_0kc0jc0ic0 -= dxinv0 * 0.2 * _t_2_;
_t_3_ = -cons_1[k][j][i-3];
_t_3_ += cons_1[k][j][i+3];
flux_0kc0jc0ic0 += dxinv0 * 0.038 * _t_3_;
_t_4_ = -cons_1[k][j][i-4];
_t_4_ += cons_1[k][j][i+4];
flux_0kc0jc0ic0 -= dxinv0 * 0.0035 * _t_4_;
_t_10_ = -cons_2[k][j-4][i];
_t_10_ += cons_2[k][j+4][i];
_t_5_ = -dxinv1 * 0.0035 * _t_10_;
_t_7_ = -cons_2[k][j-1][i];
_t_7_ += cons_2[k][j+1][i];
_t_5_ += dxinv1 * 0.8 * _t_7_;
_t_8_ = -cons_2[k][j-2][i];
_t_8_ += cons_2[k][j+2][i];
_t_5_ -= dxinv1 * 0.2 * _t_8_;
_t_9_ = -cons_2[k][j-3][i];
_t_9_ += cons_2[k][j+3][i];
_t_5_ += dxinv1 * 0.038 * _t_9_;
flux_0kc0jc0ic0 -= _t_5_;
flux_0[k][j][i] = flux_0kc0jc0ic0;
_t_12_ = -cons_1[k][j][i-1] * q_1[k][j][i-1];
_t_12_ += cons_1[k][j][i+1] * q_1[k][j][i+1];
_t_12_ -= q_4[k][j][i-1];
_t_12_ += q_4[k][j][i+1];
flux_1kc0jc0ic0 = dxinv0 * 0.8 * _t_12_;
_t_13_ = -cons_1[k][j][i-2] * q_1[k][j][i-2];
_t_13_ += cons_1[k][j][i+2] * q_1[k][j][i+2];
_t_13_ -= q_4[k][j][i-2];
_t_13_ += q_4[k][j][i+2];
flux_1kc0jc0ic0 -= dxinv0 * 0.2 * _t_13_;
_t_14_ = -cons_1[k][j][i-3] * q_1[k][j][i-3];
_t_14_ += cons_1[k][j][i+3] * q_1[k][j][i+3];
_t_14_ -= q_4[k][j][i-3];
_t_14_ += q_4[k][j][i+3];
flux_1kc0jc0ic0 += dxinv0 * 0.038 * _t_14_;
_t_15_ = -cons_1[k][j][i-4] * q_1[k][j][i-4];
_t_15_ += cons_1[k][j][i+4] * q_1[k][j][i+4];
_t_15_ -= q_4[k][j][i-4];
_t_15_ += q_4[k][j][i+4];
flux_1kc0jc0ic0 -= dxinv0 * 0.0035 * _t_15_;
_t_32_ = -cons_2[k][j-4][i] * q_2[k][j-4][i];
_t_32_ += cons_2[k][j+4][i] * q_2[k][j+4][i];
_t_32_ -= q_4[k][j-4][i];
_t_32_ += q_4[k][j+4][i];
_t_27_ = -dxinv1 * 0.0035 * _t_32_;
_t_29_ = -cons_2[k][j-1][i] * q_2[k][j-1][i];
_t_29_ += cons_2[k][j+1][i] * q_2[k][j+1][i];
_t_29_ -= q_4[k][j-1][i];
_t_29_ += q_4[k][j+1][i];
_t_27_ += dxinv1 * 0.8 * _t_29_;
_t_30_ = -cons_2[k][j-2][i] * q_2[k][j-2][i];
_t_30_ += cons_2[k][j+2][i] * q_2[k][j+2][i];
_t_30_ -= q_4[k][j-2][i];
_t_30_ += q_4[k][j+2][i];
_t_27_ -= dxinv1 * 0.2 * _t_30_;
_t_31_ = -cons_2[k][j-3][i] * q_2[k][j-3][i];
_t_31_ += cons_2[k][j+3][i] * q_2[k][j+3][i];
_t_31_ -= q_4[k][j-3][i];
_t_31_ += q_4[k][j+3][i];
_t_27_ += dxinv1 * 0.038 * _t_31_;
_t_18_ = -cons_1[k][j-1][i] * q_2[k][j-1][i];
_t_18_ += cons_1[k][j+1][i] * q_2[k][j+1][i];
_t_16_ = dxinv1 * 0.8 * _t_18_;
_t_19_ = -cons_1[k][j-2][i] * q_2[k][j-2][i];
_t_19_ += cons_1[k][j+2][i] * q_2[k][j+2][i];
_t_16_ -= dxinv1 * 0.2 * _t_19_;
_t_20_ = -cons_1[k][j-3][i] * q_2[k][j-3][i];
_t_20_ += cons_1[k][j+3][i] * q_2[k][j+3][i];
_t_16_ += dxinv1 * 0.038 * _t_20_;
_t_21_ = -cons_1[k][j-4][i] * q_2[k][j-4][i];
_t_21_ += cons_1[k][j+4][i] * q_2[k][j+4][i];
_t_16_ -= dxinv1 * 0.0035 * _t_21_;
flux_1kc0jc0ic0 -= _t_16_;
flux_1[k][j][i] = flux_1kc0jc0ic0;
_t_23_ = -cons_2[k][j][i-1] * q_1[k][j][i-1];
_t_23_ += cons_2[k][j][i+1] * q_1[k][j][i+1];
flux_2kc0jc0ic0 = dxinv0 * 0.8 * _t_23_;
_t_24_ = -cons_2[k][j][i-2] * q_1[k][j][i-2];
_t_24_ += cons_2[k][j][i+2] * q_1[k][j][i+2];
flux_2kc0jc0ic0 -= dxinv0 * 0.2 * _t_24_;
_t_25_ = -cons_2[k][j][i-3] * q_1[k][j][i-3];
_t_25_ += cons_2[k][j][i+3] * q_1[k][j][i+3];
flux_2kc0jc0ic0 += dxinv0 * 0.038 * _t_25_;
_t_26_ = -cons_2[k][j][i-4] * q_1[k][j][i-4];
_t_26_ += cons_2[k][j][i+4] * q_1[k][j][i+4];
flux_2kc0jc0ic0 -= dxinv0 * 0.0035 * _t_26_;
flux_2kc0jc0ic0 -= _t_27_;
flux_2[k][j][i] = flux_2kc0jc0ic0;
_t_34_ = -cons_3[k][j][i-1] * q_1[k][j][i-1];
_t_34_ += cons_3[k][j][i+1] * q_1[k][j][i+1];
flux_3kc0jc0ic0 = dxinv0 * 0.8 * _t_34_;
_t_35_ = -cons_3[k][j][i-2] * q_1[k][j][i-2];
_t_35_ += cons_3[k][j][i+2] * q_1[k][j][i+2];
flux_3kc0jc0ic0 -= dxinv0 * 0.2 * _t_35_;
_t_36_ = -cons_3[k][j][i-3] * q_1[k][j][i-3];
_t_36_ += cons_3[k][j][i+3] * q_1[k][j][i+3];
flux_3kc0jc0ic0 += dxinv0 * 0.038 * _t_36_;
_t_37_ = -cons_3[k][j][i-4] * q_1[k][j][i-4];
_t_37_ += cons_3[k][j][i+4] * q_1[k][j][i+4];
flux_3kc0jc0ic0 -= dxinv0 * 0.0035 * _t_37_;
_t_40_ = -cons_3[k][j-1][i] * q_2[k][j-1][i];
_t_40_ += cons_3[k][j+1][i] * q_2[k][j+1][i];
_t_38_ = dxinv1 * 0.8 * _t_40_;
_t_41_ = -cons_3[k][j-2][i] * q_2[k][j-2][i];
_t_41_ += cons_3[k][j+2][i] * q_2[k][j+2][i];
_t_38_ -= dxinv1 * 0.2 * _t_41_;
_t_42_ = -cons_3[k][j-3][i] * q_2[k][j-3][i];
_t_42_ += cons_3[k][j+3][i] * q_2[k][j+3][i];
_t_38_ += dxinv1 * 0.038 * _t_42_;
_t_43_ = -cons_3[k][j-4][i] * q_2[k][j-4][i];
_t_43_ += cons_3[k][j+4][i] * q_2[k][j+4][i];
_t_38_ -= dxinv1 * 0.0035 * _t_43_;
flux_3kc0jc0ic0 -= _t_38_;
flux_3[k][j][i] = flux_3kc0jc0ic0;
	} 
}

__global__ void hypterm_1 (double * __restrict__ flux_in_0, double * __restrict__ flux_in_1, double * __restrict__ flux_in_2, double * __restrict__ flux_in_3, double * __restrict__ cons_in_1, double * __restrict__ cons_in_2, double * __restrict__ cons_in_3, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
    //Determing the block's indices
    int blockdim_i= (int)(blockDim.x);
    int i0 = (int)(blockIdx.x)*(blockdim_i);
    int i = max (i0, 0) + (int)(threadIdx.x);
    int blockdim_j= (int)(blockDim.y);
    int j0 = (int)(blockIdx.y)*(blockdim_j);
    int j = max (j0, 0) + (int)(threadIdx.y);
    int blockdim_k= (int)(blockDim.z);
    int k0 = (int)(blockIdx.z)*(4*blockdim_k);
    int k = max (k0, 0) + (int)(4*threadIdx.z);

    double (*flux_0)[308][308] = (double (*)[308][308])flux_in_0;
    double (*flux_1)[308][308] = (double (*)[308][308])flux_in_1;
    double (*flux_2)[308][308] = (double (*)[308][308])flux_in_2;
    double (*flux_3)[308][308] = (double (*)[308][308])flux_in_3;
    double (*cons_1)[308][308] = (double (*)[308][308])cons_in_1;
    double (*cons_2)[308][308] = (double (*)[308][308])cons_in_2;
    double (*cons_3)[308][308] = (double (*)[308][308])cons_in_3;
    double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
    double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
    double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
    double (*q_4)[308][308] = (double (*)[308][308])q_in_4;
	double flux0_a, flux1_a, flux2_a, flux3_a;
	double flux0_b, flux1_b, flux2_b, flux3_b;
	double flux0_c, flux1_c, flux2_c, flux3_c;
	double flux0_d, flux1_d, flux2_d, flux3_d;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
double flux0_a;
double flux_0kc0jc0ic0;
double _t_1_;
double _t_3_;
double _t_4_;
double _t_2_;
double flux0_b;
double flux_0kp1jc0ic0;
double _t_7_;
double _t_8_;
double _t_9_;
double _t_6_;
double flux0_c;
double flux_0kp2jc0ic0;
double _t_11_;
double _t_12_;
double _t_13_;
double _t_14_;
double flux0_d;
double flux_0kp3jc0ic0;
double _t_16_;
double _t_17_;
double _t_18_;
double _t_19_;
double flux1_a;
double flux_1kc0jc0ic0;
double _t_64_;
double _t_62_;
double _t_61_;
double _t_63_;
double _t_69_;
double flux3_a;
double flux_3kc0jc0ic0;
double _t_67_;
double _t_71_;
double _t_77_;
double _t_73_;
double _t_79_;
double _t_68_;
double _t_74_;
double _t_66_;
double _t_76_;
double _t_72_;
double _t_78_;
double flux3_b;
double flux_3kp1jc0ic0;
double flux3_c;
double flux_3kp2jc0ic0;
double flux3_d;
double flux_3kp3jc0ic0;
double _t_24_;
double _t_22_;
double _t_21_;
double _t_23_;
double _t_29_;
double _t_27_;
double _t_31_;
double _t_37_;
double _t_33_;
double _t_39_;
double _t_28_;
double _t_34_;
double _t_26_;
double _t_36_;
double _t_32_;
double _t_38_;
double flux1_b;
double flux_1kp1jc0ic0;
double flux1_c;
double flux_1kp2jc0ic0;
double flux1_d;
double flux_1kp3jc0ic0;
double flux2_a;
double flux_2kc0jc0ic0;
double _t_44_;
double _t_42_;
double _t_41_;
double _t_43_;
double _t_49_;
double _t_47_;
double _t_51_;
double _t_57_;
double _t_53_;
double _t_59_;
double _t_48_;
double _t_54_;
double _t_46_;
double _t_56_;
double _t_52_;
double _t_58_;
double flux2_b;
double flux_2kp1jc0ic0;
double flux2_c;
double flux_2kp2jc0ic0;
double flux2_d;
double flux_2kp3jc0ic0;

flux0_a = flux_0[k][j][i];
flux_0kc0jc0ic0 = flux0_a;
_t_1_ = -cons_3[k-1][j][i];
_t_1_ += cons_3[k+1][j][i];
flux_0kc0jc0ic0 -= dxinv2 * 0.8 * _t_1_;
_t_3_ = cons_3[k+3][j][i];
_t_3_ -= cons_3[k-3][j][i];
flux_0kc0jc0ic0 -= dxinv2 * 0.038 * _t_3_;
_t_4_ = cons_3[k+4][j][i];
_t_4_ -= cons_3[k-4][j][i];
flux_0kc0jc0ic0 += dxinv2 * 0.0035 * _t_4_;
_t_2_ = -cons_3[k-2][j][i];
_t_2_ += cons_3[k+2][j][i];
flux_0kc0jc0ic0 += dxinv2 * 0.2 * _t_2_;
flux_0[k][j][i] = flux_0kc0jc0ic0;
flux0_b = flux_0[k+1][j][i];
flux_0kp1jc0ic0 = flux0_b;
_t_7_ = cons_3[k+3][j][i];
_t_7_ -= cons_3[k-1][j][i];
flux_0kp1jc0ic0 += dxinv2 * 0.2 * _t_7_;
_t_8_ = cons_3[k+4][j][i];
_t_8_ -= cons_3[k-2][j][i];
flux_0kp1jc0ic0 -= dxinv2 * 0.038 * _t_8_;
_t_9_ = -cons_3[k-3][j][i];
_t_9_ += cons_3[k+5][j][i];
flux_0kp1jc0ic0 += dxinv2 * 0.0035 * _t_9_;
_t_6_ = cons_3[k+2][j][i];
_t_6_ -= cons_3[k][j][i];
flux_0kp1jc0ic0 -= dxinv2 * 0.8 * _t_6_;
flux_0[k+1][j][i] = flux_0kp1jc0ic0;
flux0_c = flux_0[k+2][j][i];
flux_0kp2jc0ic0 = flux0_c;
_t_11_ = cons_3[k+3][j][i];
_t_11_ -= cons_3[k+1][j][i];
flux_0kp2jc0ic0 -= dxinv2 * 0.8 * _t_11_;
_t_12_ = cons_3[k+4][j][i];
_t_12_ -= cons_3[k][j][i];
flux_0kp2jc0ic0 += dxinv2 * 0.2 * _t_12_;
_t_13_ = cons_3[k+5][j][i];
_t_13_ -= cons_3[k-1][j][i];
flux_0kp2jc0ic0 -= dxinv2 * 0.038 * _t_13_;
_t_14_ = -cons_3[k-2][j][i];
_t_14_ += cons_3[k+6][j][i];
flux_0kp2jc0ic0 += dxinv2 * 0.0035 * _t_14_;
flux_0[k+2][j][i] = flux_0kp2jc0ic0;
flux0_d = flux_0[k+3][j][i];
flux_0kp3jc0ic0 = flux0_d;
_t_16_ = cons_3[k+4][j][i];
_t_16_ -= cons_3[k+2][j][i];
flux_0kp3jc0ic0 -= dxinv2 * 0.8 * _t_16_;
_t_17_ = cons_3[k+5][j][i];
_t_17_ -= cons_3[k+1][j][i];
flux_0kp3jc0ic0 += dxinv2 * 0.2 * _t_17_;
_t_18_ = cons_3[k+6][j][i];
_t_18_ -= cons_3[k][j][i];
flux_0kp3jc0ic0 -= dxinv2 * 0.038 * _t_18_;
_t_19_ = -cons_3[k-1][j][i];
_t_19_ += cons_3[k+7][j][i];
flux_0kp3jc0ic0 += dxinv2 * 0.0035 * _t_19_;
flux_0[k+3][j][i] = flux_0kp3jc0ic0;
flux1_a = flux_1[k][j][i];
flux_1kc0jc0ic0 = flux1_a;
_t_64_ = -cons_3[k-4][j][i] * q_3[k-4][j][i];
_t_64_ -= q_4[k-4][j][i];
_t_64_ += cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_64_ += q_4[k+4][j][i];
_t_62_ = cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_62_ += q_4[k+2][j][i];
_t_62_ -= cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_62_ -= q_4[k-2][j][i];
_t_61_ = -cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_61_ -= q_4[k-1][j][i];
_t_61_ += cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_61_ += q_4[k+1][j][i];
_t_63_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_63_ -= cons_3[k-3][j][i] * q_3[k-3][j][i];
_t_69_ = -cons_3[k-3][j][i] * q_3[k-3][j][i];
_t_63_ -= q_4[k-3][j][i];
_t_69_ -= q_4[k-3][j][i];
_t_63_ += q_4[k+3][j][i];
flux3_a = flux_3[k][j][i];
flux_3kc0jc0ic0 = dxinv2 * 0.0035 * _t_64_;
flux_3kc0jc0ic0 += dxinv2 * 0.2 * _t_62_;
flux_3kc0jc0ic0 -= dxinv2 * 0.8 * _t_61_;
flux_3kc0jc0ic0 -= dxinv2 * 0.038 * _t_63_;
flux_3kc0jc0ic0 += flux3_a;
flux_3[k][j][i] = flux_3kc0jc0ic0;
_t_67_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_67_ -= cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_67_ += q_4[k+3][j][i];
_t_67_ -= q_4[k-1][j][i];
_t_71_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_71_ -= cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_71_ += q_4[k+3][j][i];
_t_71_ -= q_4[k+1][j][i];
_t_77_ = -cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_77_ -= q_4[k+1][j][i];
_t_69_ += cons_3[k+5][j][i] * q_3[k+5][j][i];
_t_77_ += cons_3[k+5][j][i] * q_3[k+5][j][i];
_t_73_ = cons_3[k+5][j][i] * q_3[k+5][j][i];
_t_73_ -= cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_73_ -= q_4[k-1][j][i];
_t_79_ = -cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_79_ -= q_4[k-1][j][i];
_t_69_ += q_4[k+5][j][i];
_t_73_ += q_4[k+5][j][i];
_t_77_ += q_4[k+5][j][i];
_t_79_ += cons_3[k+7][j][i] * q_3[k+7][j][i];
_t_79_ += q_4[k+7][j][i];
_t_68_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_68_ -= cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_68_ += q_4[k+4][j][i];
_t_68_ -= q_4[k-2][j][i];
_t_74_ = -cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_74_ -= q_4[k-2][j][i];
_t_66_ = cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_66_ += q_4[k+2][j][i];
_t_76_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_76_ -= cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_76_ += q_4[k+4][j][i];
_t_76_ -= q_4[k+2][j][i];
_t_72_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_72_ += q_4[k+4][j][i];
_t_66_ -= cons_3[k][j][i] * q_3[k][j][i];
_t_72_ -= cons_3[k][j][i] * q_3[k][j][i];
_t_78_ = -cons_3[k][j][i] * q_3[k][j][i];
_t_66_ -= q_4[k][j][i];
_t_72_ -= q_4[k][j][i];
_t_78_ -= q_4[k][j][i];
_t_74_ += cons_3[k+6][j][i] * q_3[k+6][j][i];
_t_78_ += cons_3[k+6][j][i] * q_3[k+6][j][i];
_t_74_ += q_4[k+6][j][i];
_t_78_ += q_4[k+6][j][i];
flux3_b = flux_3[k+1][j][i];
flux_3kp1jc0ic0 = dxinv2 * 0.0035 * _t_69_;
flux_3kp1jc0ic0 -= dxinv2 * 0.038 * _t_68_;
flux_3kp1jc0ic0 += dxinv2 * 0.2 * _t_67_;
flux_3kp1jc0ic0 -= dxinv2 * 0.8 * _t_66_;
flux_3kp1jc0ic0 += flux3_b;
flux_3[k+1][j][i] = flux_3kp1jc0ic0;
flux3_c = flux_3[k+2][j][i];
flux_3kp2jc0ic0 = dxinv2 * 0.0035 * _t_74_;
flux_3kp2jc0ic0 -= dxinv2 * 0.038 * _t_73_;
flux_3kp2jc0ic0 += dxinv2 * 0.2 * _t_72_;
flux_3kp2jc0ic0 -= dxinv2 * 0.8 * _t_71_;
flux_3kp2jc0ic0 += flux3_c;
flux_3[k+2][j][i] = flux_3kp2jc0ic0;
flux3_d = flux_3[k+3][j][i];
flux_3kp3jc0ic0 = dxinv2 * 0.0035 * _t_79_;
flux_3kp3jc0ic0 -= dxinv2 * 0.038 * _t_78_;
flux_3kp3jc0ic0 += dxinv2 * 0.2 * _t_77_;
flux_3kp3jc0ic0 -= dxinv2 * 0.8 * _t_76_;
flux_3kp3jc0ic0 += flux3_d;
flux_3[k+3][j][i] = flux_3kp3jc0ic0;
_t_24_ = -cons_1[k-4][j][i] * q_3[k-4][j][i];
_t_24_ += cons_1[k+4][j][i] * q_3[k+4][j][i];
flux_1kc0jc0ic0 += dxinv2 * 0.0035 * _t_24_;
_t_22_ = cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_22_ -= cons_1[k-2][j][i] * q_3[k-2][j][i];
flux_1kc0jc0ic0 += dxinv2 * 0.2 * _t_22_;
_t_21_ = -cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_21_ += cons_1[k+1][j][i] * q_3[k+1][j][i];
flux_1kc0jc0ic0 -= dxinv2 * 0.8 * _t_21_;
_t_23_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_23_ -= cons_1[k-3][j][i] * q_3[k-3][j][i];
flux_1kc0jc0ic0 -= dxinv2 * 0.038 * _t_23_;
flux_1[k][j][i] = flux_1kc0jc0ic0;
_t_29_ = -cons_1[k-3][j][i] * q_3[k-3][j][i];
_t_27_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_27_ -= cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_31_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_31_ -= cons_1[k+1][j][i] * q_3[k+1][j][i];
_t_37_ = -cons_1[k+1][j][i] * q_3[k+1][j][i];
_t_29_ += cons_1[k+5][j][i] * q_3[k+5][j][i];
_t_37_ += cons_1[k+5][j][i] * q_3[k+5][j][i];
_t_33_ = cons_1[k+5][j][i] * q_3[k+5][j][i];
_t_33_ -= cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_39_ = -cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_39_ += cons_1[k+7][j][i] * q_3[k+7][j][i];
_t_28_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_28_ -= cons_1[k-2][j][i] * q_3[k-2][j][i];
_t_34_ = -cons_1[k-2][j][i] * q_3[k-2][j][i];
_t_26_ = cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_36_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_36_ -= cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_32_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_26_ -= cons_1[k][j][i] * q_3[k][j][i];
_t_32_ -= cons_1[k][j][i] * q_3[k][j][i];
_t_38_ = -cons_1[k][j][i] * q_3[k][j][i];
_t_34_ += cons_1[k+6][j][i] * q_3[k+6][j][i];
_t_38_ += cons_1[k+6][j][i] * q_3[k+6][j][i];
flux1_b = flux_1[k+1][j][i];
flux_1kp1jc0ic0 = dxinv2 * 0.0035 * _t_29_;
flux_1kp1jc0ic0 -= dxinv2 * 0.038 * _t_28_;
flux_1kp1jc0ic0 += dxinv2 * 0.2 * _t_27_;
flux_1kp1jc0ic0 -= dxinv2 * 0.8 * _t_26_;
flux_1kp1jc0ic0 += flux1_b;
flux_1[k+1][j][i] = flux_1kp1jc0ic0;
flux1_c = flux_1[k+2][j][i];
flux_1kp2jc0ic0 = dxinv2 * 0.0035 * _t_34_;
flux_1kp2jc0ic0 -= dxinv2 * 0.038 * _t_33_;
flux_1kp2jc0ic0 += dxinv2 * 0.2 * _t_32_;
flux_1kp2jc0ic0 -= dxinv2 * 0.8 * _t_31_;
flux_1kp2jc0ic0 += flux1_c;
flux_1[k+2][j][i] = flux_1kp2jc0ic0;
flux1_d = flux_1[k+3][j][i];
flux_1kp3jc0ic0 = dxinv2 * 0.0035 * _t_39_;
flux_1kp3jc0ic0 -= dxinv2 * 0.038 * _t_38_;
flux_1kp3jc0ic0 += dxinv2 * 0.2 * _t_37_;
flux_1kp3jc0ic0 -= dxinv2 * 0.8 * _t_36_;
flux_1kp3jc0ic0 += flux1_d;
flux_1[k+3][j][i] = flux_1kp3jc0ic0;
flux2_a = flux_2[k][j][i];
flux_2kc0jc0ic0 = flux2_a;
_t_44_ = -cons_2[k-4][j][i] * q_3[k-4][j][i];
_t_44_ += cons_2[k+4][j][i] * q_3[k+4][j][i];
flux_2kc0jc0ic0 += dxinv2 * 0.0035 * _t_44_;
_t_42_ = cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_42_ -= cons_2[k-2][j][i] * q_3[k-2][j][i];
flux_2kc0jc0ic0 += dxinv2 * 0.2 * _t_42_;
_t_41_ = -cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_41_ += cons_2[k+1][j][i] * q_3[k+1][j][i];
flux_2kc0jc0ic0 -= dxinv2 * 0.8 * _t_41_;
_t_43_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_43_ -= cons_2[k-3][j][i] * q_3[k-3][j][i];
flux_2kc0jc0ic0 -= dxinv2 * 0.038 * _t_43_;
flux_2[k][j][i] = flux_2kc0jc0ic0;
_t_49_ = -cons_2[k-3][j][i] * q_3[k-3][j][i];
_t_47_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_47_ -= cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_51_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_51_ -= cons_2[k+1][j][i] * q_3[k+1][j][i];
_t_57_ = -cons_2[k+1][j][i] * q_3[k+1][j][i];
_t_49_ += cons_2[k+5][j][i] * q_3[k+5][j][i];
_t_57_ += cons_2[k+5][j][i] * q_3[k+5][j][i];
_t_53_ = cons_2[k+5][j][i] * q_3[k+5][j][i];
_t_53_ -= cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_59_ = -cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_59_ += cons_2[k+7][j][i] * q_3[k+7][j][i];
_t_48_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_48_ -= cons_2[k-2][j][i] * q_3[k-2][j][i];
_t_54_ = -cons_2[k-2][j][i] * q_3[k-2][j][i];
_t_46_ = cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_56_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_56_ -= cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_52_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_46_ -= cons_2[k][j][i] * q_3[k][j][i];
_t_52_ -= cons_2[k][j][i] * q_3[k][j][i];
_t_58_ = -cons_2[k][j][i] * q_3[k][j][i];
_t_54_ += cons_2[k+6][j][i] * q_3[k+6][j][i];
_t_58_ += cons_2[k+6][j][i] * q_3[k+6][j][i];
flux2_b = flux_2[k+1][j][i];
flux_2kp1jc0ic0 = dxinv2 * 0.0035 * _t_49_;
flux_2kp1jc0ic0 -= dxinv2 * 0.038 * _t_48_;
flux_2kp1jc0ic0 += dxinv2 * 0.2 * _t_47_;
flux_2kp1jc0ic0 -= dxinv2 * 0.8 * _t_46_;
flux_2kp1jc0ic0 += flux2_b;
flux_2[k+1][j][i] = flux_2kp1jc0ic0;
flux2_c = flux_2[k+2][j][i];
flux_2kp2jc0ic0 = dxinv2 * 0.0035 * _t_54_;
flux_2kp2jc0ic0 -= dxinv2 * 0.038 * _t_53_;
flux_2kp2jc0ic0 += dxinv2 * 0.2 * _t_52_;
flux_2kp2jc0ic0 -= dxinv2 * 0.8 * _t_51_;
flux_2kp2jc0ic0 += flux2_c;
flux_2[k+2][j][i] = flux_2kp2jc0ic0;
flux2_d = flux_2[k+3][j][i];
flux_2kp3jc0ic0 = dxinv2 * 0.0035 * _t_59_;
flux_2kp3jc0ic0 -= dxinv2 * 0.038 * _t_58_;
flux_2kp3jc0ic0 += dxinv2 * 0.2 * _t_57_;
flux_2kp3jc0ic0 -= dxinv2 * 0.8 * _t_56_;
flux_2kp3jc0ic0 += flux2_d;
flux_2[k+3][j][i] = flux_2kp3jc0ic0;
	} 
}

__global__ void hypterm_2 (double * __restrict__ flux_in_4, double * __restrict__ cons_in_4, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(2*blockdim_k);
	int k = max (k0, 0) + (int)(2*threadIdx.z);

	double (*flux_4)[308][308] = (double (*)[308][308])flux_in_4;
	double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
	double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
	double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
	double (*q_4)[308][308] = (double (*)[308][308])q_in_4;
	double (*cons_4)[308][308] = (double (*)[308][308])cons_in_4;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
		flux_4[k][j][i] = ((0.8*(cons_4[k][j][i+1]*q_1[k][j][i+1]-cons_4[k][j][i-1]*q_1[k][j][i-1]+(q_4[k][j][i+1]*q_1[k][j][i+1]-q_4[k][j][i-1]*q_1[k][j][i-1]))-0.2*(cons_4[k][j][i+2]*q_1[k][j][i+2]-cons_4[k][j][i-2]*q_1[k][j][i-2]+(q_4[k][j][i+2]*q_1[k][j][i+2]-q_4[k][j][i-2]*q_1[k][j][i-2]))+0.038*(cons_4[k][j][i+3]*q_1[k][j][i+3]-cons_4[k][j][i-3]*q_1[k][j][i-3]+(q_4[k][j][i+3]*q_1[k][j][i+3]-q_4[k][j][i-3]*q_1[k][j][i-3]))-0.0035*(cons_4[k][j][i+4]*q_1[k][j][i+4]-cons_4[k][j][i-4]*q_1[k][j][i-4]+(q_4[k][j][i+4]*q_1[k][j][i+4]-q_4[k][j][i-4]*q_1[k][j][i-4])))*dxinv0);
		flux_4[k+1][j][i] = ((0.8*(cons_4[k+1][j][i+1]*q_1[k+1][j][i+1]-cons_4[k+1][j][i-1]*q_1[k+1][j][i-1]+(q_4[k+1][j][i+1]*q_1[k+1][j][i+1]-q_4[k+1][j][i-1]*q_1[k+1][j][i-1]))-0.2*(cons_4[k+1][j][i+2]*q_1[k+1][j][i+2]-cons_4[k+1][j][i-2]*q_1[k+1][j][i-2]+(q_4[k+1][j][i+2]*q_1[k+1][j][i+2]-q_4[k+1][j][i-2]*q_1[k+1][j][i-2]))+0.038*(cons_4[k+1][j][i+3]*q_1[k+1][j][i+3]-cons_4[k+1][j][i-3]*q_1[k+1][j][i-3]+(q_4[k+1][j][i+3]*q_1[k+1][j][i+3]-q_4[k+1][j][i-3]*q_1[k+1][j][i-3]))-0.0035*(cons_4[k+1][j][i+4]*q_1[k+1][j][i+4]-cons_4[k+1][j][i-4]*q_1[k+1][j][i-4]+(q_4[k+1][j][i+4]*q_1[k+1][j][i+4]-q_4[k+1][j][i-4]*q_1[k+1][j][i-4])))*dxinv0);
		flux_4[k][j][i] -= (0.8*(cons_4[k][j+1][i]*q_2[k][j+1][i]-cons_4[k][j-1][i]*q_2[k][j-1][i]+(q_4[k][j+1][i]*q_2[k][j+1][i]-q_4[k][j-1][i]*q_2[k][j-1][i]))-0.2*(cons_4[k][j+2][i]*q_2[k][j+2][i]-cons_4[k][j-2][i]*q_2[k][j-2][i]+(q_4[k][j+2][i]*q_2[k][j+2][i]-q_4[k][j-2][i]*q_2[k][j-2][i]))+0.038*(cons_4[k][j+3][i]*q_2[k][j+3][i]-cons_4[k][j-3][i]*q_2[k][j-3][i]+(q_4[k][j+3][i]*q_2[k][j+3][i]-q_4[k][j-3][i]*q_2[k][j-3][i]))-0.0035*(cons_4[k][j+4][i]*q_2[k][j+4][i]-cons_4[k][j-4][i]*q_2[k][j-4][i]+(q_4[k][j+4][i]*q_2[k][j+4][i]-q_4[k][j-4][i]*q_2[k][j-4][i])))*dxinv1;
		flux_4[k+1][j][i] -= (0.8*(cons_4[k+1][j+1][i]*q_2[k+1][j+1][i]-cons_4[k+1][j-1][i]*q_2[k+1][j-1][i]+(q_4[k+1][j+1][i]*q_2[k+1][j+1][i]-q_4[k+1][j-1][i]*q_2[k+1][j-1][i]))-0.2*(cons_4[k+1][j+2][i]*q_2[k+1][j+2][i]-cons_4[k+1][j-2][i]*q_2[k+1][j-2][i]+(q_4[k+1][j+2][i]*q_2[k+1][j+2][i]-q_4[k+1][j-2][i]*q_2[k+1][j-2][i]))+0.038*(cons_4[k+1][j+3][i]*q_2[k+1][j+3][i]-cons_4[k+1][j-3][i]*q_2[k+1][j-3][i]+(q_4[k+1][j+3][i]*q_2[k+1][j+3][i]-q_4[k+1][j-3][i]*q_2[k+1][j-3][i]))-0.0035*(cons_4[k+1][j+4][i]*q_2[k+1][j+4][i]-cons_4[k+1][j-4][i]*q_2[k+1][j-4][i]+(q_4[k+1][j+4][i]*q_2[k+1][j+4][i]-q_4[k+1][j-4][i]*q_2[k+1][j-4][i])))*dxinv1;
		flux_4[k][j][i] -= (0.8*(cons_4[k+1][j][i]*q_3[k+1][j][i]-cons_4[k-1][j][i]*q_3[k-1][j][i]+(q_4[k+1][j][i]*q_3[k+1][j][i]-q_4[k-1][j][i]*q_3[k-1][j][i]))-0.2*(cons_4[k+2][j][i]*q_3[k+2][j][i]-cons_4[k-2][j][i]*q_3[k-2][j][i]+(q_4[k+2][j][i]*q_3[k+2][j][i]-q_4[k-2][j][i]*q_3[k-2][j][i]))+0.038*(cons_4[k+3][j][i]*q_3[k+3][j][i]-cons_4[k-3][j][i]*q_3[k-3][j][i]+(q_4[k+3][j][i]*q_3[k+3][j][i]-q_4[k-3][j][i]*q_3[k-3][j][i]))-0.0035*(cons_4[k+4][j][i]*q_3[k+4][j][i]-cons_4[k-4][j][i]*q_3[k-4][j][i]+(q_4[k+4][j][i]*q_3[k+4][j][i]-q_4[k-4][j][i]*q_3[k-4][j][i])))*dxinv2;
		flux_4[k+1][j][i] -= (0.8*(cons_4[k+1+1][j][i]*q_3[k+1+1][j][i]-cons_4[k+1-1][j][i]*q_3[k+1-1][j][i]+(q_4[k+1+1][j][i]*q_3[k+1+1][j][i]-q_4[k+1-1][j][i]*q_3[k+1-1][j][i]))-0.2*(cons_4[k+1+2][j][i]*q_3[k+1+2][j][i]-cons_4[k+1-2][j][i]*q_3[k+1-2][j][i]+(q_4[k+1+2][j][i]*q_3[k+1+2][j][i]-q_4[k+1-2][j][i]*q_3[k+1-2][j][i]))+0.038*(cons_4[k+1+3][j][i]*q_3[k+1+3][j][i]-cons_4[k+1-3][j][i]*q_3[k+1-3][j][i]+(q_4[k+1+3][j][i]*q_3[k+1+3][j][i]-q_4[k+1-3][j][i]*q_3[k+1-3][j][i]))-0.0035*(cons_4[k+1+4][j][i]*q_3[k+1+4][j][i]-cons_4[k+1-4][j][i]*q_3[k+1-4][j][i]+(q_4[k+1+4][j][i]*q_3[k+1+4][j][i]-q_4[k+1-4][j][i]*q_3[k+1-4][j][i])))*dxinv2;
	} 
}

extern "C" void host_code (double *h_flux_0, double *h_flux_1, double *h_flux_2, double *h_flux_3, double *h_flux_4, double *h_cons_1, double *h_cons_2, double *h_cons_3, double *h_cons_4, double *h_q_1, double *h_q_2, double *h_q_3, double *h_q_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	double *flux_0;
	cudaMalloc (&flux_0, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_0\n");
	cudaMemcpy (flux_0, h_flux_0, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_1;
	cudaMalloc (&flux_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_1\n");
	cudaMemcpy (flux_1, h_flux_1, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_2;
	cudaMalloc (&flux_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_2\n");
	cudaMemcpy (flux_2, h_flux_2, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_3;
	cudaMalloc (&flux_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_3\n");
	cudaMemcpy (flux_3, h_flux_3, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_4;
	cudaMalloc (&flux_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_4\n");
	cudaMemcpy (flux_4, h_flux_4, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_1;
	cudaMalloc (&cons_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_1\n");
	cudaMemcpy (cons_1, h_cons_1, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_2;
	cudaMalloc (&cons_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_2\n");
	cudaMemcpy (cons_2, h_cons_2, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_3;
	cudaMalloc (&cons_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_3\n");
	cudaMemcpy (cons_3, h_cons_3, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_4;
	cudaMalloc (&cons_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_4\n");
	cudaMemcpy (cons_4, h_cons_4, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_1;
	cudaMalloc (&q_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_1\n");
	cudaMemcpy (q_1, h_q_1, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_2;
	cudaMalloc (&q_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_2\n");
	cudaMemcpy (q_2, h_q_2, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_3;
	cudaMalloc (&q_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_3\n");
	cudaMemcpy (q_3, h_q_3, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_4;
	cudaMalloc (&q_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_4\n");
	cudaMemcpy (q_4, h_q_4, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);

	dim3 blockconfig (16, 4, 4);
	dim3 gridconfig_0 (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, blockconfig.z));
	hypterm_0 <<<gridconfig_0, blockconfig>>> (flux_0, flux_1, flux_2, flux_3, cons_1, cons_2, cons_3, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);
	dim3 gridconfig_1 (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, 4*blockconfig.z));
	hypterm_1 <<<gridconfig_1, blockconfig>>> (flux_0, flux_1, flux_2, flux_3, cons_1, cons_2, cons_3, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);
	dim3 gridconfig_2 (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, 2*blockconfig.z));
	hypterm_2 <<<gridconfig_2, blockconfig>>> (flux_4, cons_4, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);

	cudaMemcpy (h_flux_0, flux_0, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_1, flux_1, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_3, flux_3, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_4, flux_4, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_2, flux_2, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
}

	.file	"tmpxft_00215da3_00000000-6_reordered-e.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0:
.LFB2177:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2177:
	.size	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L3
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L3:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii, @function
_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$344, %rsp
	.cfi_def_cfa_offset 352
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 328(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	352(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 88(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 240(%rsp)
	movq	360(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 96(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	368(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 104(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	376(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	384(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 320(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	136(%rsp)
	.cfi_def_cfa_offset 360
	leaq	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 368
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 360
	popq	%rdx
	.cfi_def_cfa_offset 352
.L7:
	movq	328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$344, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii, .-_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, @function
_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_endproc
.LFE2054:
	.size	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, .-_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii, @function
_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$344, %rsp
	.cfi_def_cfa_offset 352
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 328(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	352(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 88(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 240(%rsp)
	movq	360(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 96(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	368(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 104(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	376(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	384(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 320(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	136(%rsp)
	.cfi_def_cfa_offset 360
	leaq	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 368
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 360
	popq	%rdx
	.cfi_def_cfa_offset 352
.L12:
	movq	328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$344, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii, .-_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, @function
_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_endproc
.LFE2056:
	.size	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, .-_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii
	.type	_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii, @function
_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rax, 152(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	288(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 64(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 72(%rsp)
	movq	%r9, 80(%rsp)
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z9hypterm_2PdS_S_S_S_S_dddiii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L17:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii, .-_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii
	.globl	_Z9hypterm_2PdS_S_S_S_S_dddiii
	.type	_Z9hypterm_2PdS_S_S_S_S_dddiii, @function
_Z9hypterm_2PdS_S_S_S_S_dddiii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii
	.cfi_endproc
.LFE2058:
	.size	_Z9hypterm_2PdS_S_S_S_S_dddiii, .-_Z9hypterm_2PdS_S_S_S_S_dddiii
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for flux_0\n"
.LC2:
	.string	"Failed to allocate device memory for flux_1\n"
.LC3:
	.string	"Failed to allocate device memory for flux_2\n"
.LC4:
	.string	"Failed to allocate device memory for flux_3\n"
.LC5:
	.string	"Failed to allocate device memory for flux_4\n"
.LC6:
	.string	"Failed to allocate device memory for cons_1\n"
.LC7:
	.string	"Failed to allocate device memory for cons_2\n"
.LC8:
	.string	"Failed to allocate device memory for cons_3\n"
.LC9:
	.string	"Failed to allocate device memory for cons_4\n"
.LC10:
	.string	"Failed to allocate device memory for q_1\n"
.LC11:
	.string	"Failed to allocate device memory for q_2\n"
.LC12:
	.string	"Failed to allocate device memory for q_3\n"
.LC13:
	.string	"Failed to allocate device memory for q_4\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$280, %rsp
	.cfi_def_cfa_offset 336
	movq	352(%rsp), %rax
	movq	%r8, 64(%rsp)
	movsd	%xmm0, 8(%rsp)
	movq	344(%rsp), %r14
	movq	336(%rsp), %r15
	movq	%rax, 72(%rsp)
	movq	360(%rsp), %rax
	movq	%rcx, 56(%rsp)
	movq	%rax, 80(%rsp)
	movq	368(%rsp), %rax
	movq	%rdi, 32(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rax, 88(%rsp)
	movq	376(%rsp), %rax
	movq	%rsi, 40(%rsp)
	movq	%rax, 96(%rsp)
	movq	384(%rsp), %rax
	movq	%rdx, 48(%rsp)
	movq	%rax, 104(%rsp)
	movsd	%xmm1, 16(%rsp)
	movl	400(%rsp), %ebp
	movslq	408(%rsp), %rdx
	movsd	%xmm2, 24(%rsp)
	movl	392(%rsp), %ebx
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	movslq	%ebp, %rax
	movq	%rdx, %r12
	imulq	%rdx, %rax
	movslq	%ebx, %rdx
	imulq	%rdx, %rax
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	112(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	120(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	120(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	128(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC3(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	136(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC4(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	136(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	144(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC5(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	152(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC6(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r13, %rsi
	movq	152(%rsp), %rdi
	movl	%ebp, %r13d
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	160(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC7(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r15, %rsi
	movq	160(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	168(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC8(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r14, %rsi
	movq	168(%rsp), %rdi
	movl	%r12d, %r14d
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	176(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC9(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$1, %ecx
	movq	176(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	184(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC10(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$1, %ecx
	movq	184(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	192(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC11(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$1, %ecx
	movq	192(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	200(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC12(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	96(%rsp), %rsi
	movl	$1, %ecx
	movq	200(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	208(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC13(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	104(%rsp), %rsi
	movl	$1, %ecx
	movq	208(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%ebx, %eax
	movl	%ebx, %esi
	movl	$1073741825, %edx
	andl	$3, %eax
	shrl	$2, %esi
	movl	$4, %ecx
	movl	$4, 224(%rsp)
	cmpl	$1, %eax
	movl	%ebp, %eax
	sbbl	$-1, %esi
	andl	$3, %eax
	shrl	$2, %r13d
	cmpl	$1, %eax
	movl	%r12d, %eax
	sbbl	$-1, %r13d
	andl	$15, %eax
	shrl	$4, %r14d
	cmpl	$1, %eax
	movl	%r13d, 232(%rsp)
	sbbl	$-1, %r14d
	salq	$4, %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%r14d, 228(%rsp)
	movq	228(%rsp), %rdi
	movq	%rdx, 216(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movsd	8(%rsp), %xmm0
	xorps	.LC14(%rip), %xmm0
	pushq	%r12
	.cfi_def_cfa_offset 344
	pushq	%rbp
	.cfi_def_cfa_offset 352
	pushq	%rbx
	.cfi_def_cfa_offset 360
	pushq	232(%rsp)
	.cfi_def_cfa_offset 368
	pushq	232(%rsp)
	.cfi_def_cfa_offset 376
	pushq	232(%rsp)
	.cfi_def_cfa_offset 384
	pushq	232(%rsp)
	.cfi_def_cfa_offset 392
	pushq	224(%rsp)
	.cfi_def_cfa_offset 400
	movsd	88(%rsp), %xmm2
	movsd	80(%rsp), %xmm1
	movq	224(%rsp), %r9
	movq	216(%rsp), %r8
	movq	200(%rsp), %rcx
	movq	192(%rsp), %rdx
	movq	184(%rsp), %rsi
	movq	176(%rsp), %rdi
	call	_Z54__device_stub__Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 336
.L26:
	movl	%ebx, %eax
	movl	%ebx, %esi
	movl	%r14d, 240(%rsp)
	movl	224(%rsp), %ecx
	andl	$15, %eax
	shrl	$4, %esi
	movl	%r13d, 244(%rsp)
	movq	216(%rsp), %rdx
	cmpl	$1, %eax
	movq	240(%rsp), %rdi
	sbbl	$-1, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movsd	8(%rsp), %xmm0
	xorps	.LC14(%rip), %xmm0
	pushq	%r12
	.cfi_def_cfa_offset 344
	pushq	%rbp
	.cfi_def_cfa_offset 352
	pushq	%rbx
	.cfi_def_cfa_offset 360
	pushq	232(%rsp)
	.cfi_def_cfa_offset 368
	pushq	232(%rsp)
	.cfi_def_cfa_offset 376
	pushq	232(%rsp)
	.cfi_def_cfa_offset 384
	pushq	232(%rsp)
	.cfi_def_cfa_offset 392
	pushq	224(%rsp)
	.cfi_def_cfa_offset 400
	movsd	88(%rsp), %xmm2
	movsd	80(%rsp), %xmm1
	movq	224(%rsp), %r9
	movq	216(%rsp), %r8
	movq	200(%rsp), %rcx
	movq	192(%rsp), %rdx
	movq	184(%rsp), %rsi
	movq	176(%rsp), %rdi
	call	_Z54__device_stub__Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_dddiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 336
.L28:
	movl	%ebx, %eax
	movl	%ebx, %esi
	movl	%r14d, 252(%rsp)
	movl	224(%rsp), %ecx
	andl	$7, %eax
	shrl	$3, %esi
	movl	%r13d, 256(%rsp)
	movq	216(%rsp), %rdx
	cmpl	$1, %eax
	movq	252(%rsp), %rdi
	sbbl	$-1, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movsd	8(%rsp), %xmm0
	xorps	.LC14(%rip), %xmm0
	pushq	%rax
	.cfi_def_cfa_offset 344
	pushq	%r12
	.cfi_def_cfa_offset 352
	pushq	%rbp
	.cfi_def_cfa_offset 360
	pushq	%rbx
	.cfi_def_cfa_offset 368
	movsd	56(%rsp), %xmm2
	movsd	48(%rsp), %xmm1
	movq	240(%rsp), %r9
	movq	232(%rsp), %r8
	movq	224(%rsp), %rcx
	movq	216(%rsp), %rdx
	movq	208(%rsp), %rsi
	movq	176(%rsp), %rdi
	call	_Z44__device_stub__Z9hypterm_2PdS_S_S_S_S_dddiiiPdS_S_S_S_S_dddiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 336
.L30:
	movq	(%rsp), %rdx
	movq	112(%rsp), %rsi
	movl	$2, %ecx
	movq	32(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	120(%rsp), %rsi
	movl	$2, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	56(%rsp), %rdi
	movl	$2, %ecx
	movq	136(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	64(%rsp), %rdi
	movl	$2, %ecx
	movq	144(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	48(%rsp), %rdi
	movl	$2, %ecx
	movq	128(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$280, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC15:
	.string	"_Z9hypterm_2PdS_S_S_S_S_dddiii"
.LC16:
	.string	"_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii"
.LC17:
	.string	"_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9hypterm_2PdS_S_S_S_S_dddiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC14:
	.long	0
	.long	-2147483648
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void hypterm_0 (double * __restrict__ flux_in_0, double * __restrict__ flux_in_1, double * __restrict__ flux_in_2, double * __restrict__ flux_in_3, double * __restrict__ cons_in_1, double * __restrict__ cons_in_2, double * __restrict__ cons_in_3, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.z);

	double (*flux_0)[308][308] = (double (*)[308][308])flux_in_0;
	double (*flux_1)[308][308] = (double (*)[308][308])flux_in_1;
	double (*flux_2)[308][308] = (double (*)[308][308])flux_in_2;
	double (*flux_3)[308][308] = (double (*)[308][308])flux_in_3;
	double (*cons_1)[308][308] = (double (*)[308][308])cons_in_1;
	double (*cons_2)[308][308] = (double (*)[308][308])cons_in_2;
	double (*cons_3)[308][308] = (double (*)[308][308])cons_in_3;
    double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
    double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
    double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
    double (*q_4)[308][308] = (double (*)[308][308])q_in_4;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
double _t_1_;
double flux_0kc0jc0ic0;
double _t_2_;
double _t_3_;
double _t_4_;
double _t_10_;
double _t_5_;
double _t_7_;
double _t_8_;
double _t_9_;
double _t_12_;
double flux_1kc0jc0ic0;
double _t_13_;
double _t_14_;
double _t_15_;
double _t_32_;
double _t_27_;
double _t_29_;
double _t_30_;
double _t_31_;
double _t_18_;
double _t_16_;
double _t_19_;
double _t_20_;
double _t_21_;
double _t_23_;
double flux_2kc0jc0ic0;
double _t_24_;
double _t_25_;
double _t_26_;
double _t_34_;
double flux_3kc0jc0ic0;
double _t_35_;
double _t_36_;
double _t_37_;
double _t_40_;
double _t_38_;
double _t_41_;
double _t_42_;
double _t_43_;

_t_1_ = -cons_1[k][j][i-1];
_t_1_ += cons_1[k][j][i+1];
flux_0kc0jc0ic0 = dxinv0 * 0.8 * _t_1_;
_t_2_ = -cons_1[k][j][i-2];
_t_2_ += cons_1[k][j][i+2];
flux_0kc0jc0ic0 -= dxinv0 * 0.2 * _t_2_;
_t_3_ = -cons_1[k][j][i-3];
_t_3_ += cons_1[k][j][i+3];
flux_0kc0jc0ic0 += dxinv0 * 0.038 * _t_3_;
_t_4_ = -cons_1[k][j][i-4];
_t_4_ += cons_1[k][j][i+4];
flux_0kc0jc0ic0 -= dxinv0 * 0.0035 * _t_4_;
_t_10_ = -cons_2[k][j-4][i];
_t_10_ += cons_2[k][j+4][i];
_t_5_ = -dxinv1 * 0.0035 * _t_10_;
_t_7_ = -cons_2[k][j-1][i];
_t_7_ += cons_2[k][j+1][i];
_t_5_ += dxinv1 * 0.8 * _t_7_;
_t_8_ = -cons_2[k][j-2][i];
_t_8_ += cons_2[k][j+2][i];
_t_5_ -= dxinv1 * 0.2 * _t_8_;
_t_9_ = -cons_2[k][j-3][i];
_t_9_ += cons_2[k][j+3][i];
_t_5_ += dxinv1 * 0.038 * _t_9_;
flux_0kc0jc0ic0 -= _t_5_;
flux_0[k][j][i] = flux_0kc0jc0ic0;
_t_12_ = -cons_1[k][j][i-1] * q_1[k][j][i-1];
_t_12_ += cons_1[k][j][i+1] * q_1[k][j][i+1];
_t_12_ -= q_4[k][j][i-1];
_t_12_ += q_4[k][j][i+1];
flux_1kc0jc0ic0 = dxinv0 * 0.8 * _t_12_;
_t_13_ = -cons_1[k][j][i-2] * q_1[k][j][i-2];
_t_13_ += cons_1[k][j][i+2] * q_1[k][j][i+2];
_t_13_ -= q_4[k][j][i-2];
_t_13_ += q_4[k][j][i+2];
flux_1kc0jc0ic0 -= dxinv0 * 0.2 * _t_13_;
_t_14_ = -cons_1[k][j][i-3] * q_1[k][j][i-3];
_t_14_ += cons_1[k][j][i+3] * q_1[k][j][i+3];
_t_14_ -= q_4[k][j][i-3];
_t_14_ += q_4[k][j][i+3];
flux_1kc0jc0ic0 += dxinv0 * 0.038 * _t_14_;
_t_15_ = -cons_1[k][j][i-4] * q_1[k][j][i-4];
_t_15_ += cons_1[k][j][i+4] * q_1[k][j][i+4];
_t_15_ -= q_4[k][j][i-4];
_t_15_ += q_4[k][j][i+4];
flux_1kc0jc0ic0 -= dxinv0 * 0.0035 * _t_15_;
_t_32_ = -cons_2[k][j-4][i] * q_2[k][j-4][i];
_t_32_ += cons_2[k][j+4][i] * q_2[k][j+4][i];
_t_32_ -= q_4[k][j-4][i];
_t_32_ += q_4[k][j+4][i];
_t_27_ = -dxinv1 * 0.0035 * _t_32_;
_t_29_ = -cons_2[k][j-1][i] * q_2[k][j-1][i];
_t_29_ += cons_2[k][j+1][i] * q_2[k][j+1][i];
_t_29_ -= q_4[k][j-1][i];
_t_29_ += q_4[k][j+1][i];
_t_27_ += dxinv1 * 0.8 * _t_29_;
_t_30_ = -cons_2[k][j-2][i] * q_2[k][j-2][i];
_t_30_ += cons_2[k][j+2][i] * q_2[k][j+2][i];
_t_30_ -= q_4[k][j-2][i];
_t_30_ += q_4[k][j+2][i];
_t_27_ -= dxinv1 * 0.2 * _t_30_;
_t_31_ = -cons_2[k][j-3][i] * q_2[k][j-3][i];
_t_31_ += cons_2[k][j+3][i] * q_2[k][j+3][i];
_t_31_ -= q_4[k][j-3][i];
_t_31_ += q_4[k][j+3][i];
_t_27_ += dxinv1 * 0.038 * _t_31_;
_t_18_ = -cons_1[k][j-1][i] * q_2[k][j-1][i];
_t_18_ += cons_1[k][j+1][i] * q_2[k][j+1][i];
_t_16_ = dxinv1 * 0.8 * _t_18_;
_t_19_ = -cons_1[k][j-2][i] * q_2[k][j-2][i];
_t_19_ += cons_1[k][j+2][i] * q_2[k][j+2][i];
_t_16_ -= dxinv1 * 0.2 * _t_19_;
_t_20_ = -cons_1[k][j-3][i] * q_2[k][j-3][i];
_t_20_ += cons_1[k][j+3][i] * q_2[k][j+3][i];
_t_16_ += dxinv1 * 0.038 * _t_20_;
_t_21_ = -cons_1[k][j-4][i] * q_2[k][j-4][i];
_t_21_ += cons_1[k][j+4][i] * q_2[k][j+4][i];
_t_16_ -= dxinv1 * 0.0035 * _t_21_;
flux_1kc0jc0ic0 -= _t_16_;
flux_1[k][j][i] = flux_1kc0jc0ic0;
_t_23_ = -cons_2[k][j][i-1] * q_1[k][j][i-1];
_t_23_ += cons_2[k][j][i+1] * q_1[k][j][i+1];
flux_2kc0jc0ic0 = dxinv0 * 0.8 * _t_23_;
_t_24_ = -cons_2[k][j][i-2] * q_1[k][j][i-2];
_t_24_ += cons_2[k][j][i+2] * q_1[k][j][i+2];
flux_2kc0jc0ic0 -= dxinv0 * 0.2 * _t_24_;
_t_25_ = -cons_2[k][j][i-3] * q_1[k][j][i-3];
_t_25_ += cons_2[k][j][i+3] * q_1[k][j][i+3];
flux_2kc0jc0ic0 += dxinv0 * 0.038 * _t_25_;
_t_26_ = -cons_2[k][j][i-4] * q_1[k][j][i-4];
_t_26_ += cons_2[k][j][i+4] * q_1[k][j][i+4];
flux_2kc0jc0ic0 -= dxinv0 * 0.0035 * _t_26_;
flux_2kc0jc0ic0 -= _t_27_;
flux_2[k][j][i] = flux_2kc0jc0ic0;
_t_34_ = -cons_3[k][j][i-1] * q_1[k][j][i-1];
_t_34_ += cons_3[k][j][i+1] * q_1[k][j][i+1];
flux_3kc0jc0ic0 = dxinv0 * 0.8 * _t_34_;
_t_35_ = -cons_3[k][j][i-2] * q_1[k][j][i-2];
_t_35_ += cons_3[k][j][i+2] * q_1[k][j][i+2];
flux_3kc0jc0ic0 -= dxinv0 * 0.2 * _t_35_;
_t_36_ = -cons_3[k][j][i-3] * q_1[k][j][i-3];
_t_36_ += cons_3[k][j][i+3] * q_1[k][j][i+3];
flux_3kc0jc0ic0 += dxinv0 * 0.038 * _t_36_;
_t_37_ = -cons_3[k][j][i-4] * q_1[k][j][i-4];
_t_37_ += cons_3[k][j][i+4] * q_1[k][j][i+4];
flux_3kc0jc0ic0 -= dxinv0 * 0.0035 * _t_37_;
_t_40_ = -cons_3[k][j-1][i] * q_2[k][j-1][i];
_t_40_ += cons_3[k][j+1][i] * q_2[k][j+1][i];
_t_38_ = dxinv1 * 0.8 * _t_40_;
_t_41_ = -cons_3[k][j-2][i] * q_2[k][j-2][i];
_t_41_ += cons_3[k][j+2][i] * q_2[k][j+2][i];
_t_38_ -= dxinv1 * 0.2 * _t_41_;
_t_42_ = -cons_3[k][j-3][i] * q_2[k][j-3][i];
_t_42_ += cons_3[k][j+3][i] * q_2[k][j+3][i];
_t_38_ += dxinv1 * 0.038 * _t_42_;
_t_43_ = -cons_3[k][j-4][i] * q_2[k][j-4][i];
_t_43_ += cons_3[k][j+4][i] * q_2[k][j+4][i];
_t_38_ -= dxinv1 * 0.0035 * _t_43_;
flux_3kc0jc0ic0 -= _t_38_;
flux_3[k][j][i] = flux_3kc0jc0ic0;
	} 
}

__global__ void hypterm_1 (double * __restrict__ flux_in_0, double * __restrict__ flux_in_1, double * __restrict__ flux_in_2, double * __restrict__ flux_in_3, double * __restrict__ cons_in_1, double * __restrict__ cons_in_2, double * __restrict__ cons_in_3, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
    //Determing the block's indices
    int blockdim_i= (int)(blockDim.x);
    int i0 = (int)(blockIdx.x)*(blockdim_i);
    int i = max (i0, 0) + (int)(threadIdx.x);
    int blockdim_j= (int)(blockDim.y);
    int j0 = (int)(blockIdx.y)*(blockdim_j);
    int j = max (j0, 0) + (int)(threadIdx.y);
    int blockdim_k= (int)(blockDim.z);
    int k0 = (int)(blockIdx.z)*(4*blockdim_k);
    int k = max (k0, 0) + (int)(4*threadIdx.z);

    double (*flux_0)[308][308] = (double (*)[308][308])flux_in_0;
    double (*flux_1)[308][308] = (double (*)[308][308])flux_in_1;
    double (*flux_2)[308][308] = (double (*)[308][308])flux_in_2;
    double (*flux_3)[308][308] = (double (*)[308][308])flux_in_3;
    double (*cons_1)[308][308] = (double (*)[308][308])cons_in_1;
    double (*cons_2)[308][308] = (double (*)[308][308])cons_in_2;
    double (*cons_3)[308][308] = (double (*)[308][308])cons_in_3;
    double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
    double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
    double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
    double (*q_4)[308][308] = (double (*)[308][308])q_in_4;
	double flux0_a, flux1_a, flux2_a, flux3_a;
	double flux0_b, flux1_b, flux2_b, flux3_b;
	double flux0_c, flux1_c, flux2_c, flux3_c;
	double flux0_d, flux1_d, flux2_d, flux3_d;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
double flux0_a;
double flux_0kc0jc0ic0;
double _t_1_;
double _t_3_;
double _t_4_;
double _t_2_;
double flux0_b;
double flux_0kp1jc0ic0;
double _t_7_;
double _t_8_;
double _t_9_;
double _t_6_;
double flux0_c;
double flux_0kp2jc0ic0;
double _t_11_;
double _t_12_;
double _t_13_;
double _t_14_;
double flux0_d;
double flux_0kp3jc0ic0;
double _t_16_;
double _t_17_;
double _t_18_;
double _t_19_;
double flux1_a;
double flux_1kc0jc0ic0;
double _t_64_;
double _t_62_;
double _t_61_;
double _t_63_;
double _t_69_;
double flux3_a;
double flux_3kc0jc0ic0;
double _t_67_;
double _t_71_;
double _t_77_;
double _t_73_;
double _t_79_;
double _t_68_;
double _t_74_;
double _t_66_;
double _t_76_;
double _t_72_;
double _t_78_;
double flux3_b;
double flux_3kp1jc0ic0;
double flux3_c;
double flux_3kp2jc0ic0;
double flux3_d;
double flux_3kp3jc0ic0;
double _t_24_;
double _t_22_;
double _t_21_;
double _t_23_;
double _t_29_;
double _t_27_;
double _t_31_;
double _t_37_;
double _t_33_;
double _t_39_;
double _t_28_;
double _t_34_;
double _t_26_;
double _t_36_;
double _t_32_;
double _t_38_;
double flux1_b;
double flux_1kp1jc0ic0;
double flux1_c;
double flux_1kp2jc0ic0;
double flux1_d;
double flux_1kp3jc0ic0;
double flux2_a;
double flux_2kc0jc0ic0;
double _t_44_;
double _t_42_;
double _t_41_;
double _t_43_;
double _t_49_;
double _t_47_;
double _t_51_;
double _t_57_;
double _t_53_;
double _t_59_;
double _t_48_;
double _t_54_;
double _t_46_;
double _t_56_;
double _t_52_;
double _t_58_;
double flux2_b;
double flux_2kp1jc0ic0;
double flux2_c;
double flux_2kp2jc0ic0;
double flux2_d;
double flux_2kp3jc0ic0;

flux0_a = flux_0[k][j][i];
flux_0kc0jc0ic0 = flux0_a;
_t_1_ = -cons_3[k-1][j][i];
_t_1_ += cons_3[k+1][j][i];
flux_0kc0jc0ic0 -= dxinv2 * 0.8 * _t_1_;
_t_3_ = cons_3[k+3][j][i];
_t_3_ -= cons_3[k-3][j][i];
flux_0kc0jc0ic0 -= dxinv2 * 0.038 * _t_3_;
_t_4_ = cons_3[k+4][j][i];
_t_4_ -= cons_3[k-4][j][i];
flux_0kc0jc0ic0 += dxinv2 * 0.0035 * _t_4_;
_t_2_ = -cons_3[k-2][j][i];
_t_2_ += cons_3[k+2][j][i];
flux_0kc0jc0ic0 += dxinv2 * 0.2 * _t_2_;
flux_0[k][j][i] = flux_0kc0jc0ic0;
flux0_b = flux_0[k+1][j][i];
flux_0kp1jc0ic0 = flux0_b;
_t_7_ = cons_3[k+3][j][i];
_t_7_ -= cons_3[k-1][j][i];
flux_0kp1jc0ic0 += dxinv2 * 0.2 * _t_7_;
_t_8_ = cons_3[k+4][j][i];
_t_8_ -= cons_3[k-2][j][i];
flux_0kp1jc0ic0 -= dxinv2 * 0.038 * _t_8_;
_t_9_ = -cons_3[k-3][j][i];
_t_9_ += cons_3[k+5][j][i];
flux_0kp1jc0ic0 += dxinv2 * 0.0035 * _t_9_;
_t_6_ = cons_3[k+2][j][i];
_t_6_ -= cons_3[k][j][i];
flux_0kp1jc0ic0 -= dxinv2 * 0.8 * _t_6_;
flux_0[k+1][j][i] = flux_0kp1jc0ic0;
flux0_c = flux_0[k+2][j][i];
flux_0kp2jc0ic0 = flux0_c;
_t_11_ = cons_3[k+3][j][i];
_t_11_ -= cons_3[k+1][j][i];
flux_0kp2jc0ic0 -= dxinv2 * 0.8 * _t_11_;
_t_12_ = cons_3[k+4][j][i];
_t_12_ -= cons_3[k][j][i];
flux_0kp2jc0ic0 += dxinv2 * 0.2 * _t_12_;
_t_13_ = cons_3[k+5][j][i];
_t_13_ -= cons_3[k-1][j][i];
flux_0kp2jc0ic0 -= dxinv2 * 0.038 * _t_13_;
_t_14_ = -cons_3[k-2][j][i];
_t_14_ += cons_3[k+6][j][i];
flux_0kp2jc0ic0 += dxinv2 * 0.0035 * _t_14_;
flux_0[k+2][j][i] = flux_0kp2jc0ic0;
flux0_d = flux_0[k+3][j][i];
flux_0kp3jc0ic0 = flux0_d;
_t_16_ = cons_3[k+4][j][i];
_t_16_ -= cons_3[k+2][j][i];
flux_0kp3jc0ic0 -= dxinv2 * 0.8 * _t_16_;
_t_17_ = cons_3[k+5][j][i];
_t_17_ -= cons_3[k+1][j][i];
flux_0kp3jc0ic0 += dxinv2 * 0.2 * _t_17_;
_t_18_ = cons_3[k+6][j][i];
_t_18_ -= cons_3[k][j][i];
flux_0kp3jc0ic0 -= dxinv2 * 0.038 * _t_18_;
_t_19_ = -cons_3[k-1][j][i];
_t_19_ += cons_3[k+7][j][i];
flux_0kp3jc0ic0 += dxinv2 * 0.0035 * _t_19_;
flux_0[k+3][j][i] = flux_0kp3jc0ic0;
flux1_a = flux_1[k][j][i];
flux_1kc0jc0ic0 = flux1_a;
_t_64_ = -cons_3[k-4][j][i] * q_3[k-4][j][i];
_t_64_ -= q_4[k-4][j][i];
_t_64_ += cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_64_ += q_4[k+4][j][i];
_t_62_ = cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_62_ += q_4[k+2][j][i];
_t_62_ -= cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_62_ -= q_4[k-2][j][i];
_t_61_ = -cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_61_ -= q_4[k-1][j][i];
_t_61_ += cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_61_ += q_4[k+1][j][i];
_t_63_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_63_ -= cons_3[k-3][j][i] * q_3[k-3][j][i];
_t_69_ = -cons_3[k-3][j][i] * q_3[k-3][j][i];
_t_63_ -= q_4[k-3][j][i];
_t_69_ -= q_4[k-3][j][i];
_t_63_ += q_4[k+3][j][i];
flux3_a = flux_3[k][j][i];
flux_3kc0jc0ic0 = dxinv2 * 0.0035 * _t_64_;
flux_3kc0jc0ic0 += dxinv2 * 0.2 * _t_62_;
flux_3kc0jc0ic0 -= dxinv2 * 0.8 * _t_61_;
flux_3kc0jc0ic0 -= dxinv2 * 0.038 * _t_63_;
flux_3kc0jc0ic0 += flux3_a;
flux_3[k][j][i] = flux_3kc0jc0ic0;
_t_67_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_67_ -= cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_67_ += q_4[k+3][j][i];
_t_67_ -= q_4[k-1][j][i];
_t_71_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_71_ -= cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_71_ += q_4[k+3][j][i];
_t_71_ -= q_4[k+1][j][i];
_t_77_ = -cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_77_ -= q_4[k+1][j][i];
_t_69_ += cons_3[k+5][j][i] * q_3[k+5][j][i];
_t_77_ += cons_3[k+5][j][i] * q_3[k+5][j][i];
_t_73_ = cons_3[k+5][j][i] * q_3[k+5][j][i];
_t_73_ -= cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_73_ -= q_4[k-1][j][i];
_t_79_ = -cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_79_ -= q_4[k-1][j][i];
_t_69_ += q_4[k+5][j][i];
_t_73_ += q_4[k+5][j][i];
_t_77_ += q_4[k+5][j][i];
_t_79_ += cons_3[k+7][j][i] * q_3[k+7][j][i];
_t_79_ += q_4[k+7][j][i];
_t_68_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_68_ -= cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_68_ += q_4[k+4][j][i];
_t_68_ -= q_4[k-2][j][i];
_t_74_ = -cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_74_ -= q_4[k-2][j][i];
_t_66_ = cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_66_ += q_4[k+2][j][i];
_t_76_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_76_ -= cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_76_ += q_4[k+4][j][i];
_t_76_ -= q_4[k+2][j][i];
_t_72_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_72_ += q_4[k+4][j][i];
_t_66_ -= cons_3[k][j][i] * q_3[k][j][i];
_t_72_ -= cons_3[k][j][i] * q_3[k][j][i];
_t_78_ = -cons_3[k][j][i] * q_3[k][j][i];
_t_66_ -= q_4[k][j][i];
_t_72_ -= q_4[k][j][i];
_t_78_ -= q_4[k][j][i];
_t_74_ += cons_3[k+6][j][i] * q_3[k+6][j][i];
_t_78_ += cons_3[k+6][j][i] * q_3[k+6][j][i];
_t_74_ += q_4[k+6][j][i];
_t_78_ += q_4[k+6][j][i];
flux3_b = flux_3[k+1][j][i];
flux_3kp1jc0ic0 = dxinv2 * 0.0035 * _t_69_;
flux_3kp1jc0ic0 -= dxinv2 * 0.038 * _t_68_;
flux_3kp1jc0ic0 += dxinv2 * 0.2 * _t_67_;
flux_3kp1jc0ic0 -= dxinv2 * 0.8 * _t_66_;
flux_3kp1jc0ic0 += flux3_b;
flux_3[k+1][j][i] = flux_3kp1jc0ic0;
flux3_c = flux_3[k+2][j][i];
flux_3kp2jc0ic0 = dxinv2 * 0.0035 * _t_74_;
flux_3kp2jc0ic0 -= dxinv2 * 0.038 * _t_73_;
flux_3kp2jc0ic0 += dxinv2 * 0.2 * _t_72_;
flux_3kp2jc0ic0 -= dxinv2 * 0.8 * _t_71_;
flux_3kp2jc0ic0 += flux3_c;
flux_3[k+2][j][i] = flux_3kp2jc0ic0;
flux3_d = flux_3[k+3][j][i];
flux_3kp3jc0ic0 = dxinv2 * 0.0035 * _t_79_;
flux_3kp3jc0ic0 -= dxinv2 * 0.038 * _t_78_;
flux_3kp3jc0ic0 += dxinv2 * 0.2 * _t_77_;
flux_3kp3jc0ic0 -= dxinv2 * 0.8 * _t_76_;
flux_3kp3jc0ic0 += flux3_d;
flux_3[k+3][j][i] = flux_3kp3jc0ic0;
_t_24_ = -cons_1[k-4][j][i] * q_3[k-4][j][i];
_t_24_ += cons_1[k+4][j][i] * q_3[k+4][j][i];
flux_1kc0jc0ic0 += dxinv2 * 0.0035 * _t_24_;
_t_22_ = cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_22_ -= cons_1[k-2][j][i] * q_3[k-2][j][i];
flux_1kc0jc0ic0 += dxinv2 * 0.2 * _t_22_;
_t_21_ = -cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_21_ += cons_1[k+1][j][i] * q_3[k+1][j][i];
flux_1kc0jc0ic0 -= dxinv2 * 0.8 * _t_21_;
_t_23_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_23_ -= cons_1[k-3][j][i] * q_3[k-3][j][i];
flux_1kc0jc0ic0 -= dxinv2 * 0.038 * _t_23_;
flux_1[k][j][i] = flux_1kc0jc0ic0;
_t_29_ = -cons_1[k-3][j][i] * q_3[k-3][j][i];
_t_27_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_27_ -= cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_31_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_31_ -= cons_1[k+1][j][i] * q_3[k+1][j][i];
_t_37_ = -cons_1[k+1][j][i] * q_3[k+1][j][i];
_t_29_ += cons_1[k+5][j][i] * q_3[k+5][j][i];
_t_37_ += cons_1[k+5][j][i] * q_3[k+5][j][i];
_t_33_ = cons_1[k+5][j][i] * q_3[k+5][j][i];
_t_33_ -= cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_39_ = -cons_1[k-1][j][i] * q_3[k-1][j][i];
_t_39_ += cons_1[k+7][j][i] * q_3[k+7][j][i];
_t_28_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_28_ -= cons_1[k-2][j][i] * q_3[k-2][j][i];
_t_34_ = -cons_1[k-2][j][i] * q_3[k-2][j][i];
_t_26_ = cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_36_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_36_ -= cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_32_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_26_ -= cons_1[k][j][i] * q_3[k][j][i];
_t_32_ -= cons_1[k][j][i] * q_3[k][j][i];
_t_38_ = -cons_1[k][j][i] * q_3[k][j][i];
_t_34_ += cons_1[k+6][j][i] * q_3[k+6][j][i];
_t_38_ += cons_1[k+6][j][i] * q_3[k+6][j][i];
flux1_b = flux_1[k+1][j][i];
flux_1kp1jc0ic0 = dxinv2 * 0.0035 * _t_29_;
flux_1kp1jc0ic0 -= dxinv2 * 0.038 * _t_28_;
flux_1kp1jc0ic0 += dxinv2 * 0.2 * _t_27_;
flux_1kp1jc0ic0 -= dxinv2 * 0.8 * _t_26_;
flux_1kp1jc0ic0 += flux1_b;
flux_1[k+1][j][i] = flux_1kp1jc0ic0;
flux1_c = flux_1[k+2][j][i];
flux_1kp2jc0ic0 = dxinv2 * 0.0035 * _t_34_;
flux_1kp2jc0ic0 -= dxinv2 * 0.038 * _t_33_;
flux_1kp2jc0ic0 += dxinv2 * 0.2 * _t_32_;
flux_1kp2jc0ic0 -= dxinv2 * 0.8 * _t_31_;
flux_1kp2jc0ic0 += flux1_c;
flux_1[k+2][j][i] = flux_1kp2jc0ic0;
flux1_d = flux_1[k+3][j][i];
flux_1kp3jc0ic0 = dxinv2 * 0.0035 * _t_39_;
flux_1kp3jc0ic0 -= dxinv2 * 0.038 * _t_38_;
flux_1kp3jc0ic0 += dxinv2 * 0.2 * _t_37_;
flux_1kp3jc0ic0 -= dxinv2 * 0.8 * _t_36_;
flux_1kp3jc0ic0 += flux1_d;
flux_1[k+3][j][i] = flux_1kp3jc0ic0;
flux2_a = flux_2[k][j][i];
flux_2kc0jc0ic0 = flux2_a;
_t_44_ = -cons_2[k-4][j][i] * q_3[k-4][j][i];
_t_44_ += cons_2[k+4][j][i] * q_3[k+4][j][i];
flux_2kc0jc0ic0 += dxinv2 * 0.0035 * _t_44_;
_t_42_ = cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_42_ -= cons_2[k-2][j][i] * q_3[k-2][j][i];
flux_2kc0jc0ic0 += dxinv2 * 0.2 * _t_42_;
_t_41_ = -cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_41_ += cons_2[k+1][j][i] * q_3[k+1][j][i];
flux_2kc0jc0ic0 -= dxinv2 * 0.8 * _t_41_;
_t_43_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_43_ -= cons_2[k-3][j][i] * q_3[k-3][j][i];
flux_2kc0jc0ic0 -= dxinv2 * 0.038 * _t_43_;
flux_2[k][j][i] = flux_2kc0jc0ic0;
_t_49_ = -cons_2[k-3][j][i] * q_3[k-3][j][i];
_t_47_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_47_ -= cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_51_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_51_ -= cons_2[k+1][j][i] * q_3[k+1][j][i];
_t_57_ = -cons_2[k+1][j][i] * q_3[k+1][j][i];
_t_49_ += cons_2[k+5][j][i] * q_3[k+5][j][i];
_t_57_ += cons_2[k+5][j][i] * q_3[k+5][j][i];
_t_53_ = cons_2[k+5][j][i] * q_3[k+5][j][i];
_t_53_ -= cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_59_ = -cons_2[k-1][j][i] * q_3[k-1][j][i];
_t_59_ += cons_2[k+7][j][i] * q_3[k+7][j][i];
_t_48_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_48_ -= cons_2[k-2][j][i] * q_3[k-2][j][i];
_t_54_ = -cons_2[k-2][j][i] * q_3[k-2][j][i];
_t_46_ = cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_56_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_56_ -= cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_52_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_46_ -= cons_2[k][j][i] * q_3[k][j][i];
_t_52_ -= cons_2[k][j][i] * q_3[k][j][i];
_t_58_ = -cons_2[k][j][i] * q_3[k][j][i];
_t_54_ += cons_2[k+6][j][i] * q_3[k+6][j][i];
_t_58_ += cons_2[k+6][j][i] * q_3[k+6][j][i];
flux2_b = flux_2[k+1][j][i];
flux_2kp1jc0ic0 = dxinv2 * 0.0035 * _t_49_;
flux_2kp1jc0ic0 -= dxinv2 * 0.038 * _t_48_;
flux_2kp1jc0ic0 += dxinv2 * 0.2 * _t_47_;
flux_2kp1jc0ic0 -= dxinv2 * 0.8 * _t_46_;
flux_2kp1jc0ic0 += flux2_b;
flux_2[k+1][j][i] = flux_2kp1jc0ic0;
flux2_c = flux_2[k+2][j][i];
flux_2kp2jc0ic0 = dxinv2 * 0.0035 * _t_54_;
flux_2kp2jc0ic0 -= dxinv2 * 0.038 * _t_53_;
flux_2kp2jc0ic0 += dxinv2 * 0.2 * _t_52_;
flux_2kp2jc0ic0 -= dxinv2 * 0.8 * _t_51_;
flux_2kp2jc0ic0 += flux2_c;
flux_2[k+2][j][i] = flux_2kp2jc0ic0;
flux2_d = flux_2[k+3][j][i];
flux_2kp3jc0ic0 = dxinv2 * 0.0035 * _t_59_;
flux_2kp3jc0ic0 -= dxinv2 * 0.038 * _t_58_;
flux_2kp3jc0ic0 += dxinv2 * 0.2 * _t_57_;
flux_2kp3jc0ic0 -= dxinv2 * 0.8 * _t_56_;
flux_2kp3jc0ic0 += flux2_d;
flux_2[k+3][j][i] = flux_2kp3jc0ic0;
	} 
}

__global__ void hypterm_2 (double * __restrict__ flux_in_4, double * __restrict__ cons_in_4, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(2*blockdim_k);
	int k = max (k0, 0) + (int)(2*threadIdx.z);

	double (*flux_4)[308][308] = (double (*)[308][308])flux_in_4;
	double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
	double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
	double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
	double (*q_4)[308][308] = (double (*)[308][308])q_in_4;
	double (*cons_4)[308][308] = (double (*)[308][308])cons_in_4;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
		flux_4[k][j][i] = ((0.8*(cons_4[k][j][i+1]*q_1[k][j][i+1]-cons_4[k][j][i-1]*q_1[k][j][i-1]+(q_4[k][j][i+1]*q_1[k][j][i+1]-q_4[k][j][i-1]*q_1[k][j][i-1]))-0.2*(cons_4[k][j][i+2]*q_1[k][j][i+2]-cons_4[k][j][i-2]*q_1[k][j][i-2]+(q_4[k][j][i+2]*q_1[k][j][i+2]-q_4[k][j][i-2]*q_1[k][j][i-2]))+0.038*(cons_4[k][j][i+3]*q_1[k][j][i+3]-cons_4[k][j][i-3]*q_1[k][j][i-3]+(q_4[k][j][i+3]*q_1[k][j][i+3]-q_4[k][j][i-3]*q_1[k][j][i-3]))-0.0035*(cons_4[k][j][i+4]*q_1[k][j][i+4]-cons_4[k][j][i-4]*q_1[k][j][i-4]+(q_4[k][j][i+4]*q_1[k][j][i+4]-q_4[k][j][i-4]*q_1[k][j][i-4])))*dxinv0);
		flux_4[k+1][j][i] = ((0.8*(cons_4[k+1][j][i+1]*q_1[k+1][j][i+1]-cons_4[k+1][j][i-1]*q_1[k+1][j][i-1]+(q_4[k+1][j][i+1]*q_1[k+1][j][i+1]-q_4[k+1][j][i-1]*q_1[k+1][j][i-1]))-0.2*(cons_4[k+1][j][i+2]*q_1[k+1][j][i+2]-cons_4[k+1][j][i-2]*q_1[k+1][j][i-2]+(q_4[k+1][j][i+2]*q_1[k+1][j][i+2]-q_4[k+1][j][i-2]*q_1[k+1][j][i-2]))+0.038*(cons_4[k+1][j][i+3]*q_1[k+1][j][i+3]-cons_4[k+1][j][i-3]*q_1[k+1][j][i-3]+(q_4[k+1][j][i+3]*q_1[k+1][j][i+3]-q_4[k+1][j][i-3]*q_1[k+1][j][i-3]))-0.0035*(cons_4[k+1][j][i+4]*q_1[k+1][j][i+4]-cons_4[k+1][j][i-4]*q_1[k+1][j][i-4]+(q_4[k+1][j][i+4]*q_1[k+1][j][i+4]-q_4[k+1][j][i-4]*q_1[k+1][j][i-4])))*dxinv0);
		flux_4[k][j][i] -= (0.8*(cons_4[k][j+1][i]*q_2[k][j+1][i]-cons_4[k][j-1][i]*q_2[k][j-1][i]+(q_4[k][j+1][i]*q_2[k][j+1][i]-q_4[k][j-1][i]*q_2[k][j-1][i]))-0.2*(cons_4[k][j+2][i]*q_2[k][j+2][i]-cons_4[k][j-2][i]*q_2[k][j-2][i]+(q_4[k][j+2][i]*q_2[k][j+2][i]-q_4[k][j-2][i]*q_2[k][j-2][i]))+0.038*(cons_4[k][j+3][i]*q_2[k][j+3][i]-cons_4[k][j-3][i]*q_2[k][j-3][i]+(q_4[k][j+3][i]*q_2[k][j+3][i]-q_4[k][j-3][i]*q_2[k][j-3][i]))-0.0035*(cons_4[k][j+4][i]*q_2[k][j+4][i]-cons_4[k][j-4][i]*q_2[k][j-4][i]+(q_4[k][j+4][i]*q_2[k][j+4][i]-q_4[k][j-4][i]*q_2[k][j-4][i])))*dxinv1;
		flux_4[k+1][j][i] -= (0.8*(cons_4[k+1][j+1][i]*q_2[k+1][j+1][i]-cons_4[k+1][j-1][i]*q_2[k+1][j-1][i]+(q_4[k+1][j+1][i]*q_2[k+1][j+1][i]-q_4[k+1][j-1][i]*q_2[k+1][j-1][i]))-0.2*(cons_4[k+1][j+2][i]*q_2[k+1][j+2][i]-cons_4[k+1][j-2][i]*q_2[k+1][j-2][i]+(q_4[k+1][j+2][i]*q_2[k+1][j+2][i]-q_4[k+1][j-2][i]*q_2[k+1][j-2][i]))+0.038*(cons_4[k+1][j+3][i]*q_2[k+1][j+3][i]-cons_4[k+1][j-3][i]*q_2[k+1][j-3][i]+(q_4[k+1][j+3][i]*q_2[k+1][j+3][i]-q_4[k+1][j-3][i]*q_2[k+1][j-3][i]))-0.0035*(cons_4[k+1][j+4][i]*q_2[k+1][j+4][i]-cons_4[k+1][j-4][i]*q_2[k+1][j-4][i]+(q_4[k+1][j+4][i]*q_2[k+1][j+4][i]-q_4[k+1][j-4][i]*q_2[k+1][j-4][i])))*dxinv1;
		flux_4[k][j][i] -= (0.8*(cons_4[k+1][j][i]*q_3[k+1][j][i]-cons_4[k-1][j][i]*q_3[k-1][j][i]+(q_4[k+1][j][i]*q_3[k+1][j][i]-q_4[k-1][j][i]*q_3[k-1][j][i]))-0.2*(cons_4[k+2][j][i]*q_3[k+2][j][i]-cons_4[k-2][j][i]*q_3[k-2][j][i]+(q_4[k+2][j][i]*q_3[k+2][j][i]-q_4[k-2][j][i]*q_3[k-2][j][i]))+0.038*(cons_4[k+3][j][i]*q_3[k+3][j][i]-cons_4[k-3][j][i]*q_3[k-3][j][i]+(q_4[k+3][j][i]*q_3[k+3][j][i]-q_4[k-3][j][i]*q_3[k-3][j][i]))-0.0035*(cons_4[k+4][j][i]*q_3[k+4][j][i]-cons_4[k-4][j][i]*q_3[k-4][j][i]+(q_4[k+4][j][i]*q_3[k+4][j][i]-q_4[k-4][j][i]*q_3[k-4][j][i])))*dxinv2;
		flux_4[k+1][j][i] -= (0.8*(cons_4[k+1+1][j][i]*q_3[k+1+1][j][i]-cons_4[k+1-1][j][i]*q_3[k+1-1][j][i]+(q_4[k+1+1][j][i]*q_3[k+1+1][j][i]-q_4[k+1-1][j][i]*q_3[k+1-1][j][i]))-0.2*(cons_4[k+1+2][j][i]*q_3[k+1+2][j][i]-cons_4[k+1-2][j][i]*q_3[k+1-2][j][i]+(q_4[k+1+2][j][i]*q_3[k+1+2][j][i]-q_4[k+1-2][j][i]*q_3[k+1-2][j][i]))+0.038*(cons_4[k+1+3][j][i]*q_3[k+1+3][j][i]-cons_4[k+1-3][j][i]*q_3[k+1-3][j][i]+(q_4[k+1+3][j][i]*q_3[k+1+3][j][i]-q_4[k+1-3][j][i]*q_3[k+1-3][j][i]))-0.0035*(cons_4[k+1+4][j][i]*q_3[k+1+4][j][i]-cons_4[k+1-4][j][i]*q_3[k+1-4][j][i]+(q_4[k+1+4][j][i]*q_3[k+1+4][j][i]-q_4[k+1-4][j][i]*q_3[k+1-4][j][i])))*dxinv2;
	} 
}

extern "C" void host_code (double *h_flux_0, double *h_flux_1, double *h_flux_2, double *h_flux_3, double *h_flux_4, double *h_cons_1, double *h_cons_2, double *h_cons_3, double *h_cons_4, double *h_q_1, double *h_q_2, double *h_q_3, double *h_q_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	double *flux_0;
	hipMalloc (&flux_0, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_0\n");
	hipMemcpy (flux_0, h_flux_0, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_1;
	hipMalloc (&flux_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_1\n");
	hipMemcpy (flux_1, h_flux_1, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_2;
	hipMalloc (&flux_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_2\n");
	hipMemcpy (flux_2, h_flux_2, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_3;
	hipMalloc (&flux_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_3\n");
	hipMemcpy (flux_3, h_flux_3, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_4;
	hipMalloc (&flux_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_4\n");
	hipMemcpy (flux_4, h_flux_4, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_1;
	hipMalloc (&cons_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_1\n");
	hipMemcpy (cons_1, h_cons_1, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_2;
	hipMalloc (&cons_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_2\n");
	hipMemcpy (cons_2, h_cons_2, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_3;
	hipMalloc (&cons_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_3\n");
	hipMemcpy (cons_3, h_cons_3, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_4;
	hipMalloc (&cons_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_4\n");
	hipMemcpy (cons_4, h_cons_4, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_1;
	hipMalloc (&q_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_1\n");
	hipMemcpy (q_1, h_q_1, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_2;
	hipMalloc (&q_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_2\n");
	hipMemcpy (q_2, h_q_2, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_3;
	hipMalloc (&q_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_3\n");
	hipMemcpy (q_3, h_q_3, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_4;
	hipMalloc (&q_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_4\n");
	hipMemcpy (q_4, h_q_4, sizeof(double)*L*M*N, hipMemcpyHostToDevice);

	dim3 blockconfig (16, 4, 4);
	dim3 gridconfig_0 (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, blockconfig.z));
	hypterm_0 <<<gridconfig_0, blockconfig>>> (flux_0, flux_1, flux_2, flux_3, cons_1, cons_2, cons_3, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);
	dim3 gridconfig_1 (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, 4*blockconfig.z));
	hypterm_1 <<<gridconfig_1, blockconfig>>> (flux_0, flux_1, flux_2, flux_3, cons_1, cons_2, cons_3, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);
	dim3 gridconfig_2 (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, 2*blockconfig.z));
	hypterm_2 <<<gridconfig_2, blockconfig>>> (flux_4, cons_4, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);

	hipMemcpy (h_flux_0, flux_0, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_1, flux_1, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_3, flux_3, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_4, flux_4, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_2, flux_2, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
}

	.text
	.file	"reordered-e.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii # -- Begin function _Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii,@function
_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii: # @_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	movq	%r10, 96(%rbx)
	movq	%r11, 104(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, .Lfunc_end1-_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii # -- Begin function _Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii,@function
_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii: # @_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	movq	%r10, 96(%rbx)
	movq	%r11, 104(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, .Lfunc_end2-_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii # -- Begin function _Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii
	.type	_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii,@function
_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii: # @_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9hypterm_2PdS_S_S_S_S_dddiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii, .Lfunc_end3-_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function host_code
.LCPI4_0:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.text
	.globl	host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movsd	%xmm2, 8(%rsp)                  # 8-byte Spill
	movsd	%xmm1, (%rsp)                   # 8-byte Spill
	movaps	%xmm0, 128(%rsp)                # 16-byte Spill
	movq	%r9, 160(%rsp)                  # 8-byte Spill
	movq	%r8, 88(%rsp)                   # 8-byte Spill
	movq	%rcx, 80(%rsp)                  # 8-byte Spill
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %rbp
	movslq	312(%rsp), %r12
	movq	%r12, 152(%rsp)                 # 8-byte Spill
	movslq	320(%rsp), %rax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movslq	328(%rsp), %r13
	imulq	%rax, %r12
	imulq	%r13, %r12
	shlq	$3, %r12
	leaq	72(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	%rbp, 168(%rsp)                 # 8-byte Spill
	movq	%rbp, %rsi
	movabsq	$17179869200, %rbp              # imm = 0x400000010
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	%r14, 176(%rsp)                 # 8-byte Spill
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	%rbx, 184(%rsp)                 # 8-byte Spill
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	120(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.5, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	88(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	112(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.6, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	144(%rsp), %r15                 # 8-byte Reload
	movq	160(%rsp), %rsi                 # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	104(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.7, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	152(%rsp), %r14                 # 8-byte Reload
	movq	256(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.8, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	264(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	192(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.9, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	272(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.10, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	280(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.11, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	288(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.12, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	296(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.13, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	304(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r13d, %eax
	andl	$15, %eax
	movl	%r13d, %ecx
	shrl	$4, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%r15d, %eax
	andl	$3, %eax
	movl	%r15d, %ebx
	shrl	$2, %ebx
	cmpl	$1, %eax
	sbbl	$-1, %ebx
	movl	%r14d, %eax
	andl	$3, %eax
	movl	%r14d, %esi
	shrl	$2, %esi
	cmpl	$1, %eax
	sbbl	$-1, %esi
	shlq	$32, %rbx
	orq	%rcx, %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rdx
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	112(%rsp), %r8
	movq	104(%rsp), %r9
	movaps	.LCPI4_0(%rip), %xmm0           # xmm0 = [-0.0E+0,-0.0E+0]
	xorps	128(%rsp), %xmm0                # 16-byte Folded Reload
	movsd	(%rsp), %xmm1                   # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	8(%rsp), %xmm2                  # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB4_2:
	movl	%r14d, %eax
	andl	$15, %eax
	movl	%r14d, %esi
	shrl	$4, %esi
	cmpl	$1, %eax
	sbbl	$-1, %esi
	movq	%rbx, %rdi
	movq	%rbp, %rdx
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	112(%rsp), %r8
	movq	104(%rsp), %r9
	movaps	.LCPI4_0(%rip), %xmm0           # xmm0 = [-0.0E+0,-0.0E+0]
	xorps	128(%rsp), %xmm0                # 16-byte Folded Reload
	movsd	(%rsp), %xmm1                   # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	8(%rsp), %xmm2                  # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB4_4:
	movl	%r14d, %eax
	andl	$7, %eax
	movl	%r14d, %esi
	shrl	$3, %esi
	cmpl	$1, %eax
	sbbl	$-1, %esi
	movq	%rbx, %rdi
	movq	%rbp, %rdx
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	120(%rsp), %rdi
	movq	192(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	24(%rsp), %r8
	movq	16(%rsp), %r9
	movaps	128(%rsp), %xmm0                # 16-byte Reload
	xorps	.LCPI4_0(%rip), %xmm0
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movsd	8(%rsp), %xmm1                  # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	16(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB4_6:
	movq	72(%rsp), %rsi
	movq	168(%rsp), %rdi                 # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rsi
	movq	176(%rsp), %rdi                 # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	120(%rsp), %rsi
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	56(%rsp), %rsi
	movq	184(%rsp), %rdi                 # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	host_code, .Lfunc_end4-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9hypterm_2PdS_S_S_S_S_dddiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii,@object # @_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.section	.rodata,"a",@progbits
	.globl	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.p2align	3, 0x0
_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii:
	.quad	_Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.size	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, 8

	.type	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii,@object # @_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.p2align	3, 0x0
_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii:
	.quad	_Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.size	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, 8

	.type	_Z9hypterm_2PdS_S_S_S_S_dddiii,@object # @_Z9hypterm_2PdS_S_S_S_S_dddiii
	.globl	_Z9hypterm_2PdS_S_S_S_S_dddiii
	.p2align	3, 0x0
_Z9hypterm_2PdS_S_S_S_S_dddiii:
	.quad	_Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii
	.size	_Z9hypterm_2PdS_S_S_S_S_dddiii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for flux_0\n"
	.size	.L.str.1, 45

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for flux_1\n"
	.size	.L.str.2, 45

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for flux_2\n"
	.size	.L.str.3, 45

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for flux_3\n"
	.size	.L.str.4, 45

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate device memory for flux_4\n"
	.size	.L.str.5, 45

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to allocate device memory for cons_1\n"
	.size	.L.str.6, 45

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to allocate device memory for cons_2\n"
	.size	.L.str.7, 45

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate device memory for cons_3\n"
	.size	.L.str.8, 45

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to allocate device memory for cons_4\n"
	.size	.L.str.9, 45

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Failed to allocate device memory for q_1\n"
	.size	.L.str.10, 42

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Failed to allocate device memory for q_2\n"
	.size	.L.str.11, 42

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Failed to allocate device memory for q_3\n"
	.size	.L.str.12, 42

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Failed to allocate device memory for q_4\n"
	.size	.L.str.13, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii"
	.size	.L__unnamed_1, 41

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii"
	.size	.L__unnamed_2, 41

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9hypterm_2PdS_S_S_S_S_dddiii"
	.size	.L__unnamed_3, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.addrsig_sym _Z24__device_stub__hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.addrsig_sym _Z24__device_stub__hypterm_2PdS_S_S_S_S_dddiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.addrsig_sym _Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.addrsig_sym _Z9hypterm_2PdS_S_S_S_S_dddiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii ; -- Begin function _Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
	.p2align	8
	.type	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii,@function
_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii: ; @_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8c
	s_load_b32 s4, s[0:1], 0x78
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_and_b32 s5, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s13, s13, s5
	s_mul_i32 s14, s14, s2
	s_mul_i32 s15, s15, s3
	s_max_i32 s2, s13, 0
	s_max_i32 s3, s14, 0
	s_max_i32 s5, s15, 0
	v_add_nc_u32_e32 v0, s2, v1
	v_add_nc_u32_e32 v16, s3, v2
	v_add_nc_u32_e32 v1, s5, v3
	s_add_i32 s4, s4, -5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min3_u32 v2, v0, v16, v1
	v_max3_i32 v3, v0, v16, v1
	v_cmp_lt_u32_e32 vcc_lo, 3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s4, v3
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x20
	v_mad_u64_u32 v[6:7], null, 0xb9480, v1, 0
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[8:9], null, 0x9a0, v16, 0
	v_add_nc_u32_e32 v91, -4, v16
	v_add_nc_u32_e32 v16, 4, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	s_load_b64 s[2:3], s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v0, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, v2, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, v1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v57, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v58, vcc_lo, v3, v5, vcc_lo
	global_load_b128 v[0:3], v[12:13], off offset:-16
	global_load_b128 v[17:20], v[57:58], off offset:-16
	v_add_co_u32 v14, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v7, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v14, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, v15, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v5, vcc_lo
	v_add_co_u32 v25, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v26, vcc_lo, s9, v7, vcc_lo
	s_load_b64 s[8:9], s[0:1], 0x40
	global_load_b128 v[21:24], v[10:11], off offset:-16
	v_add_co_u32 v25, vcc_lo, v25, v8
	v_add_co_ci_u32_e32 v26, vcc_lo, v26, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v81, vcc_lo, v25, v4
	v_add_co_ci_u32_e32 v82, vcc_lo, v26, v5, vcc_lo
	global_load_b128 v[25:28], v[81:82], off offset:-16
	global_load_b128 v[29:32], v[12:13], off offset:8
	global_load_b128 v[33:36], v[57:58], off offset:8
	global_load_b128 v[37:40], v[12:13], off offset:-32
	global_load_b128 v[41:44], v[57:58], off offset:-32
	global_load_b128 v[45:48], v[10:11], off offset:8
	v_add_co_u32 v49, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v50, vcc_lo, s3, v7, vcc_lo
	s_mov_b32 s2, 0x9999999a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v53, vcc_lo, v49, v8
	v_add_co_ci_u32_e32 v54, vcc_lo, v50, v9, vcc_lo
	global_load_b128 v[49:52], v[81:82], off offset:8
	v_add_co_u32 v83, vcc_lo, v53, v4
	v_add_co_ci_u32_e32 v84, vcc_lo, v54, v5, vcc_lo
	global_load_b128 v[53:56], v[83:84], off offset:-16
	global_load_b128 v[57:60], v[57:58], off offset:24
	global_load_b128 v[61:64], v[12:13], off offset:24
	global_load_b128 v[65:68], v[10:11], off offset:-32
	global_load_b128 v[69:72], v[81:82], off offset:-32
	s_clause 0x1
	global_load_b128 v[73:76], v[83:84], off offset:-32
	global_load_b128 v[77:80], v[83:84], off offset:8
	s_mov_b32 s3, 0x3fe99999
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[101:102], s[6:7], s[2:3]
	s_waitcnt vmcnt(15)
	v_mul_f64 v[85:86], v[2:3], v[19:20]
	v_mul_f64 v[87:88], v[0:1], v[17:18]
	s_waitcnt vmcnt(14)
	v_mul_f64 v[23:24], v[19:20], v[23:24]
	v_mul_f64 v[21:22], v[17:18], v[21:22]
	s_waitcnt vmcnt(13)
	v_mul_f64 v[19:20], v[19:20], v[27:28]
	v_mul_f64 v[17:18], v[17:18], v[25:26]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[89:90], v[37:38], v[41:42]
	v_add_f64 v[0:1], v[31:32], -v[0:1]
	v_add_f64 v[2:3], v[29:30], -v[2:3]
	v_fma_f64 v[25:26], v[29:30], v[33:34], -v[85:86]
	v_fma_f64 v[27:28], v[31:32], v[35:36], -v[87:88]
	v_mul_f64 v[87:88], v[39:40], v[43:44]
	global_load_b64 v[85:86], v[12:13], off offset:-2464
	v_mul_f64 v[29:30], s[4:5], s[2:3]
	s_waitcnt vmcnt(5)
	v_add_f64 v[39:40], v[61:62], -v[39:40]
	s_waitcnt vmcnt(4)
	v_mul_f64 v[65:66], v[41:42], v[65:66]
	s_waitcnt vmcnt(3)
	v_mul_f64 v[41:42], v[41:42], v[69:70]
	v_mul_f64 v[67:68], v[43:44], v[67:68]
	v_mul_f64 v[43:44], v[43:44], v[71:72]
	v_add_f64 v[37:38], v[63:64], -v[37:38]
	v_fma_f64 v[23:24], v[33:34], v[45:46], -v[23:24]
	v_add_co_u32 v45, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v46, vcc_lo, s9, v7, vcc_lo
	v_fma_f64 v[21:22], v[35:36], v[47:48], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v47, vcc_lo, v45, v8
	v_add_co_ci_u32_e32 v48, vcc_lo, v46, v9, vcc_lo
	s_mov_b32 s9, 0x3fc99999
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, v47, v4
	v_add_co_ci_u32_e32 v48, vcc_lo, v48, v5, vcc_lo
	v_fma_f64 v[19:20], v[33:34], v[49:50], -v[19:20]
	v_fma_f64 v[17:18], v[35:36], v[51:52], -v[17:18]
	global_load_b64 v[35:36], v[47:48], off offset:-2464
	global_load_b64 v[49:50], v[12:13], off offset:2464
	global_load_b64 v[51:52], v[81:82], off offset:-2464
	v_add_f64 v[25:26], v[25:26], -v[55:56]
	global_load_b64 v[55:56], v[10:11], off offset:-2464
	s_mov_b32 s8, s2
	v_add_f64 v[27:28], v[27:28], -v[53:54]
	v_mul_f64 v[33:34], s[4:5], s[8:9]
	v_fma_f64 v[31:32], v[61:62], v[57:58], -v[87:88]
	global_load_b64 v[87:88], v[10:11], off offset:2464
	v_fma_f64 v[53:54], v[63:64], v[59:60], -v[89:90]
	v_add_co_u32 v69, vcc_lo, 0xfffff000, v47
	v_add_co_ci_u32_e32 v70, vcc_lo, -1, v48, vcc_lo
	v_add_co_u32 v71, vcc_lo, 0xfffff000, v12
	v_add_co_ci_u32_e32 v72, vcc_lo, -1, v13, vcc_lo
	global_load_b64 v[61:62], v[47:48], off offset:2464
	global_load_b64 v[63:64], v[83:84], off offset:-2464
	global_load_b64 v[89:90], v[81:82], off offset:2464
	v_mul_f64 v[97:98], s[6:7], s[8:9]
	s_mov_b32 s2, 0x3126e979
	s_mov_b32 s3, 0xbf6cac08
	s_mov_b32 s8, 0x6a7ef9db
	s_mov_b32 s9, 0x3fa374bc
	s_waitcnt vmcnt(9)
	v_add_f64 v[25:26], v[77:78], v[25:26]
	v_mad_i64_i32 v[77:78], null, 0x9a0, v91, v[14:15]
	v_add_f64 v[27:28], v[79:80], v[27:28]
	v_mul_f64 v[0:1], v[33:34], v[0:1]
	v_add_f64 v[31:32], v[31:32], -v[75:76]
	v_mad_u64_u32 v[79:80], null, 0x9a0, v16, v[14:15]
	v_add_f64 v[53:54], v[53:54], -v[73:74]
	global_load_b64 v[73:74], v[69:70], off offset:-832
	global_load_b64 v[75:76], v[71:72], off offset:-832
	v_mad_i64_i32 v[14:15], null, 0x9a0, v91, v[45:46]
	v_mad_u64_u32 v[91:92], null, 0x9a0, v16, v[45:46]
	v_add_co_u32 v45, vcc_lo, v77, v4
	v_add_co_ci_u32_e32 v46, vcc_lo, v78, v5, vcc_lo
	v_add_co_u32 v77, vcc_lo, v79, v4
	v_add_co_ci_u32_e32 v78, vcc_lo, v80, v5, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v5, vcc_lo
	v_add_co_u32 v79, vcc_lo, v91, v4
	v_add_co_ci_u32_e32 v80, vcc_lo, v92, v5, vcc_lo
	v_add_co_u32 v47, vcc_lo, 0x1000, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v48, vcc_lo
	v_add_co_u32 v91, vcc_lo, 0x1000, v12
	v_add_co_ci_u32_e32 v92, vcc_lo, 0, v13, vcc_lo
	v_mul_f64 v[16:17], v[33:34], v[17:18]
	v_fma_f64 v[93:94], v[29:30], v[2:3], -v[0:1]
	global_load_b64 v[0:1], v[47:48], off offset:832
	v_mul_f64 v[2:3], v[33:34], v[21:22]
	v_mul_f64 v[21:22], v[33:34], v[27:28]
	global_load_b64 v[27:28], v[91:92], off offset:832
	global_load_b64 v[33:34], v[69:70], off offset:-3296
	v_fma_f64 v[18:19], v[29:30], v[19:20], -v[16:17]
	v_fma_f64 v[23:24], v[29:30], v[23:24], -v[2:3]
	v_add_co_u32 v2, vcc_lo, 0xfffff000, v10
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v11, vcc_lo
	v_add_co_u32 v16, vcc_lo, 0x1000, v10
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v11, vcc_lo
	v_fma_f64 v[20:21], v[29:30], v[25:26], -v[21:22]
	v_add_co_u32 v25, vcc_lo, 0xffffe000, v12
	v_add_co_ci_u32_e32 v26, vcc_lo, -1, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, 0x2000, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	v_add_co_u32 v29, vcc_lo, 0xfffff000, v81
	v_add_co_ci_u32_e32 v30, vcc_lo, -1, v82, vcc_lo
	s_waitcnt vmcnt(12)
	v_mul_f64 v[69:70], v[35:36], v[85:86]
	s_waitcnt vmcnt(10)
	v_mul_f64 v[51:52], v[35:36], v[51:52]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[35:36], v[55:56], v[35:36]
	s_waitcnt vmcnt(8)
	v_add_f64 v[55:56], v[87:88], -v[55:56]
	s_waitcnt vmcnt(7)
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[49:50], v[61:62], v[49:50], -v[69:70]
	global_load_b64 v[69:70], v[16:17], off offset:832
	s_waitcnt vmcnt(6)
	v_fma_f64 v[51:52], v[61:62], v[89:90], -v[51:52]
	global_load_b64 v[85:86], v[2:3], off offset:-3296
	s_clause 0x1
	global_load_b64 v[89:90], v[91:92], off offset:3296
	global_load_b64 v[71:72], v[71:72], off offset:-3296
	v_fma_f64 v[35:36], v[87:88], v[61:62], -v[35:36]
	global_load_b64 v[61:62], v[29:30], off offset:-832
	v_add_co_u32 v87, vcc_lo, 0x1000, v81
	v_add_co_ci_u32_e32 v88, vcc_lo, 0, v82, vcc_lo
	global_load_b64 v[47:48], v[47:48], off offset:3296
	s_waitcnt vmcnt(9)
	v_mul_f64 v[75:76], v[73:74], v[75:76]
	v_add_f64 v[35:36], v[35:36], -v[63:64]
	s_waitcnt vmcnt(7)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[27:28], v[0:1], v[27:28], -v[75:76]
	global_load_b64 v[75:76], v[87:88], off offset:832
	global_load_b64 v[2:3], v[2:3], off offset:-832
	s_clause 0x1
	global_load_b64 v[87:88], v[87:88], off offset:3296
	global_load_b64 v[29:30], v[29:30], off offset:-3296
	global_load_b64 v[45:46], v[45:46], off
	global_load_b64 v[14:15], v[14:15], off
	s_waitcnt vmcnt(8)
	v_mul_f64 v[71:72], v[33:34], v[71:72]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[61:62], v[73:74], v[61:62]
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[61:62], v[0:1], v[75:76], -v[61:62]
	v_add_co_u32 v75, vcc_lo, 0xffffe000, v81
	v_add_co_ci_u32_e32 v76, vcc_lo, -1, v82, vcc_lo
	global_load_b64 v[25:26], v[25:26], off offset:-1664
	global_load_b64 v[75:76], v[75:76], off offset:-1664
	global_load_b64 v[77:78], v[77:78], off
	global_load_b64 v[79:80], v[79:80], off
	global_load_b64 v[91:92], v[16:17], off offset:3296
	s_waitcnt vmcnt(9)
	v_mul_f64 v[16:17], v[2:3], v[73:74]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[69:70], v[0:1], -v[16:17]
	v_add_f64 v[69:70], v[69:70], -v[2:3]
	v_add_co_u32 v2, vcc_lo, 0x2000, v81
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v82, vcc_lo
	s_waitcnt vmcnt(5)
	v_mul_f64 v[16:17], v[45:46], v[14:15]
	global_load_b64 v[73:74], v[12:13], off offset:1664
	global_load_b64 v[95:96], v[2:3], off offset:1664
	v_add_co_u32 v2, vcc_lo, 0xffffe000, v83
	v_mul_f64 v[12:13], v[33:34], v[29:30]
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v84, vcc_lo
	v_mul_f64 v[33:34], v[85:86], v[33:34]
	v_fma_f64 v[29:30], v[47:48], v[89:90], -v[71:72]
	global_load_b64 v[2:3], v[2:3], off offset:-1664
	s_waitcnt vmcnt(7)
	v_mul_f64 v[25:26], v[14:15], v[25:26]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[75:76], v[14:15], v[75:76]
	s_waitcnt vmcnt(5)
	v_add_f64 v[45:46], v[77:78], -v[45:46]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[14:15], v[77:78], v[79:80], -v[16:17]
	v_add_co_u32 v16, vcc_lo, 0xfffff000, v83
	v_add_co_ci_u32_e32 v17, vcc_lo, -1, v84, vcc_lo
	v_fma_f64 v[77:78], v[47:48], v[87:88], -v[12:13]
	v_add_co_u32 v12, vcc_lo, 0x2000, v83
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v84, vcc_lo
	global_load_b64 v[71:72], v[16:17], off offset:-832
	s_waitcnt vmcnt(4)
	v_fma_f64 v[33:34], v[91:92], v[47:48], -v[33:34]
	s_clause 0x1
	global_load_b64 v[47:48], v[83:84], off offset:2464
	global_load_b64 v[12:13], v[12:13], off offset:1664
	s_waitcnt vmcnt(5)
	v_fma_f64 v[25:26], v[79:80], v[73:74], -v[25:26]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[14:15], -v[2:3]
	v_add_co_u32 v14, vcc_lo, 0x1000, v83
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v84, vcc_lo
	s_clause 0x2
	global_load_b64 v[63:64], v[14:15], off offset:832
	global_load_b64 v[87:88], v[14:15], off offset:3296
	global_load_b64 v[89:90], v[16:17], off offset:-3296
	v_mul_f64 v[14:15], v[97:98], v[61:62]
	s_waitcnt vmcnt(5)
	v_add_f64 v[71:72], v[0:1], -v[71:72]
	s_waitcnt vmcnt(3)
	v_add_f64 v[99:100], v[12:13], v[2:3]
	v_mul_f64 v[12:13], v[97:98], v[27:28]
	v_add_f64 v[27:28], v[47:48], v[35:36]
	global_load_b128 v[0:3], v[10:11], off offset:24
	v_fma_f64 v[47:48], v[101:102], v[51:52], -v[14:15]
	global_load_b128 v[14:17], v[83:84], off offset:24
	v_mul_f64 v[51:52], s[6:7], s[2:3]
	v_fma_f64 v[35:36], v[101:102], v[49:50], -v[12:13]
	global_load_b128 v[10:13], v[81:82], off offset:24
	v_mul_f64 v[49:50], v[101:102], v[55:56]
	v_mul_f64 v[27:28], v[101:102], v[27:28]
	v_mul_f64 v[55:56], s[4:5], s[2:3]
	s_waitcnt vmcnt(3)
	v_add_f64 v[33:34], v[33:34], -v[89:90]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[45:46], v[51:52], v[45:46], v[49:50]
	v_mul_f64 v[49:50], s[4:5], s[8:9]
	v_fma_f64 v[27:28], v[51:52], v[99:100], v[27:28]
	v_add_f64 v[33:34], v[87:88], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[45:46], -v[97:98], v[69:70], v[45:46]
	v_fma_f64 v[39:40], v[49:50], v[39:40], v[93:94]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[0:1], v[57:58], v[0:1], -v[67:68]
	v_fma_f64 v[2:3], v[59:60], v[2:3], -v[65:66]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[14:15], v[31:32]
	v_add_f64 v[31:32], v[63:64], v[71:72]
	v_add_f64 v[16:17], v[16:17], v[53:54]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], v[57:58], v[10:11], -v[43:44]
	v_mul_f64 v[43:44], s[6:7], s[8:9]
	v_add_f64 v[57:58], v[91:92], -v[85:86]
	v_fma_f64 v[12:13], v[59:60], v[12:13], -v[41:42]
	v_fma_f64 v[0:1], v[49:50], v[0:1], v[23:24]
	v_fma_f64 v[14:15], v[49:50], v[14:15], v[20:21]
	v_fma_f64 v[20:21], -v[97:98], v[31:32], v[27:28]
	v_fma_f64 v[41:42], v[79:80], v[95:96], -v[75:76]
	v_fma_f64 v[27:28], v[55:56], v[37:38], v[39:40]
	s_load_b256 s[0:7], s[0:1], 0x0
	v_fma_f64 v[10:11], v[49:50], v[10:11], v[18:19]
	v_fma_f64 v[18:19], v[43:44], v[29:30], v[35:36]
	v_fma_f64 v[22:23], v[43:44], v[77:78], v[47:48]
	v_fma_f64 v[29:30], v[43:44], v[57:58], v[45:46]
	v_fma_f64 v[0:1], v[55:56], v[2:3], v[0:1]
	v_fma_f64 v[14:15], v[55:56], v[16:17], v[14:15]
	v_fma_f64 v[16:17], v[43:44], v[33:34], v[20:21]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v20, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v21, vcc_lo, s1, v7, vcc_lo
	v_fma_f64 v[2:3], v[55:56], v[12:13], v[10:11]
	v_fma_f64 v[10:11], v[51:52], v[25:26], v[18:19]
	v_fma_f64 v[12:13], v[51:52], v[41:42], v[22:23]
	v_add_f64 v[18:19], v[27:28], -v[29:30]
	v_add_co_u32 v22, vcc_lo, s2, v6
	v_add_f64 v[0:1], v[0:1], -v[16:17]
	v_add_co_ci_u32_e32 v23, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v24, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_add_f64 v[10:11], v[14:15], -v[10:11]
	v_add_f64 v[2:3], v[2:3], -v[12:13]
	v_add_co_u32 v12, vcc_lo, v20, v8
	v_add_co_ci_u32_e32 v13, vcc_lo, v21, v9, vcc_lo
	v_add_co_u32 v14, vcc_lo, v22, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, v23, v9, vcc_lo
	v_add_co_u32 v16, vcc_lo, v24, v8
	v_add_co_ci_u32_e32 v17, vcc_lo, v25, v9, vcc_lo
	v_add_co_u32 v20, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v21, vcc_lo, v7, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v12, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, v13, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, v14, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, v16, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, v17, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, v20, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v21, v5, vcc_lo
	global_store_b64 v[6:7], v[18:19], off
	global_store_b64 v[8:9], v[10:11], off
	global_store_b64 v[12:13], v[0:1], off
	global_store_b64 v[4:5], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 103
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii, .Lfunc_end0-_Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2704
; NumSgprs: 18
; NumVgprs: 103
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 103
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii ; -- Begin function _Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
	.p2align	8
	.type	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii,@function
_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii: ; @_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8c
	s_load_b32 s4, s[0:1], 0x78
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_and_b32 s3, s3, 0xffff
	s_mul_i32 s13, s13, s5
	s_mul_i32 s14, s14, s2
	s_mul_i32 s15, s15, s3
	s_max_i32 s2, s13, 0
	s_max_i32 s3, s14, 0
	v_add_nc_u32_e32 v4, s2, v1
	v_add_nc_u32_e32 v8, s3, v2
	s_lshl_b32 s5, s15, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_max_i32 s2, s5, 0
	s_add_i32 s5, s4, -5
	v_lshl_add_u32 v24, v0, 2, s2
	v_min_u32_e32 v0, v4, v8
	v_cmp_ge_i32_e64 s3, s5, v4
	v_cmp_ge_i32_e64 s4, s5, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v24
	v_cmp_lt_u32_e64 s2, 3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, s5, v24
	s_and_b32 s2, s3, s2
	s_and_b32 s2, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[12:15], s[0:1], 0x20
	v_mad_u64_u32 v[2:3], null, 0xb9480, v24, 0
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, -1, v24
	v_mad_u64_u32 v[0:1], null, 0x9a0, v8, 0
	v_or_b32_e32 v7, 1, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_mad_i64_i32 v[50:51], null, 0xb9480, v6, 0
	v_or_b32_e32 v10, 3, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[20:21], null, 0xb9480, v7, 0
	v_add_nc_u32_e32 v14, -3, v24
	v_add_nc_u32_e32 v16, 4, v24
	v_mad_u64_u32 v[18:19], null, 0xb9480, v10, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_mad_i64_i32 v[52:53], null, 0xb9480, v14, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v50
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, v4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, s2, v20
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v11, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, v12, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v18
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v19, vcc_lo
	v_mad_u64_u32 v[94:95], null, 0xb9480, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, v12, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, v10, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, v12, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, v13, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v52
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v53, vcc_lo
	s_load_b128 s[16:19], s[0:1], 0x48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v12, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v1, vcc_lo
	v_add_nc_u32_e32 v28, -4, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v12, v8
	v_add_co_ci_u32_e32 v17, vcc_lo, v13, v9, vcc_lo
	global_load_b64 v[78:79], v[4:5], off
	s_clause 0x3
	global_load_b64 v[12:13], v[6:7], off
	global_load_b64 v[38:39], v[10:11], off
	global_load_b64 v[44:45], v[14:15], off
	global_load_b64 v[16:17], v[16:17], off
	v_add_co_u32 v6, vcc_lo, s2, v94
	v_or_b32_e32 v10, 2, v24
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v95, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v0
	v_mad_u64_u32 v[22:23], null, 0xb9480, v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v1, vcc_lo
	v_add_nc_u32_e32 v11, -2, v24
	v_add_co_u32 v6, vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mad_i64_i32 v[70:71], null, 0xb9480, v11, 0
	v_add_co_u32 v10, vcc_lo, s2, v22
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v23, vcc_lo
	global_load_b64 v[46:47], v[6:7], off
	v_add_co_u32 v6, vcc_lo, v10, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v70
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v71, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v30, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v31, vcc_lo, v7, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v20
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v21, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, v14, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_add_co_u32 v25, vcc_lo, v10, v0
	v_add_co_ci_u32_e32 v26, vcc_lo, v11, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, v14, v8
	v_add_nc_u32_e32 v14, 5, v24
	v_add_co_ci_u32_e32 v11, vcc_lo, v15, v9, vcc_lo
	v_add_co_u32 v32, vcc_lo, v25, v8
	v_add_co_ci_u32_e32 v33, vcc_lo, v26, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[60:61], null, 0xb9480, v14, 0
	v_add_co_u32 v14, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v25, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v1, vcc_lo
	v_add_co_u32 v25, vcc_lo, v25, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v26, vcc_lo, v26, v1, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v9, vcc_lo
	v_add_co_u32 v42, vcc_lo, v25, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v43, vcc_lo, v26, v9, vcc_lo
	v_add_co_u32 v25, vcc_lo, s2, v60
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v61, vcc_lo
	v_mad_i64_i32 v[100:101], null, 0xb9480, v28, 0
	v_add_co_u32 v25, vcc_lo, v25, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v27, vcc_lo, v26, v1, vcc_lo
	v_add_nc_u32_e32 v40, 7, v24
	v_add_co_u32 v26, vcc_lo, v25, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v25, vcc_lo, s16, v50
	v_add_co_ci_u32_e32 v29, vcc_lo, s17, v51, vcc_lo
	v_add_co_u32 v34, vcc_lo, s18, v50
	v_add_co_ci_u32_e32 v35, vcc_lo, s19, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, v25, v0
	v_add_co_ci_u32_e32 v29, vcc_lo, v29, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v34, v0
	v_add_co_ci_u32_e32 v37, vcc_lo, v35, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v34, vcc_lo, v25, v8
	v_add_co_ci_u32_e32 v35, vcc_lo, v29, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v36, v8
	v_add_co_ci_u32_e32 v37, vcc_lo, v37, v9, vcc_lo
	s_clause 0x2
	global_load_b64 v[92:93], v[6:7], off
	global_load_b64 v[90:91], v[10:11], off
	global_load_b64 v[88:89], v[14:15], off
	s_clause 0x1
	global_load_b64 v[24:25], v[42:43], off
	global_load_b64 v[28:29], v[26:27], off
	global_load_b64 v[56:57], v[34:35], off
	v_mad_u64_u32 v[74:75], null, 0xb9480, v40, 0
	v_add_co_u32 v26, vcc_lo, s2, v100
	v_add_co_ci_u32_e32 v27, vcc_lo, s3, v101, vcc_lo
	global_load_b64 v[54:55], v[36:37], off
	v_add_co_u32 v34, vcc_lo, v26, v0
	v_add_co_ci_u32_e32 v35, vcc_lo, v27, v1, vcc_lo
	v_add_co_u32 v36, vcc_lo, s16, v74
	v_add_co_ci_u32_e32 v37, vcc_lo, s17, v75, vcc_lo
	v_add_co_u32 v26, vcc_lo, 0x510000, v42
	v_add_co_ci_u32_e32 v27, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v36, v0
	v_add_co_ci_u32_e32 v37, vcc_lo, v37, v1, vcc_lo
	v_add_co_u32 v40, vcc_lo, s16, v100
	v_add_co_ci_u32_e32 v41, vcc_lo, s17, v101, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v82, vcc_lo, v36, v8
	v_add_co_ci_u32_e32 v83, vcc_lo, v37, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v40, v0
	v_add_co_ci_u32_e32 v37, vcc_lo, v41, v1, vcc_lo
	v_add_co_u32 v40, vcc_lo, s18, v100
	v_add_co_ci_u32_e32 v41, vcc_lo, s19, v101, vcc_lo
	v_add_co_u32 v34, vcc_lo, v34, v8
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v40, vcc_lo, v40, v0
	v_add_co_ci_u32_e32 v41, vcc_lo, v41, v1, vcc_lo
	v_add_co_u32 v36, vcc_lo, v36, v8
	v_add_co_ci_u32_e32 v37, vcc_lo, v37, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v40, vcc_lo, v40, v8
	v_add_co_ci_u32_e32 v41, vcc_lo, v41, v9, vcc_lo
	s_clause 0x3
	global_load_b64 v[26:27], v[26:27], off offset:3968
	global_load_b64 v[30:31], v[30:31], off
	global_load_b64 v[32:33], v[32:33], off
	global_load_b64 v[58:59], v[34:35], off
	global_load_b64 v[80:81], v[36:37], off
	global_load_b64 v[98:99], v[40:41], off
	v_add_co_u32 v34, vcc_lo, s16, v94
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v95, vcc_lo
	v_add_co_u32 v36, vcc_lo, s18, v94
	v_add_co_ci_u32_e32 v37, vcc_lo, s19, v95, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v34, vcc_lo, v34, v0
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v36, v0
	v_add_co_ci_u32_e32 v37, vcc_lo, v37, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v34, vcc_lo, v34, v8
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v9, vcc_lo
	v_add_co_u32 v48, vcc_lo, s16, v22
	v_add_co_ci_u32_e32 v49, vcc_lo, s17, v23, vcc_lo
	v_add_co_u32 v40, vcc_lo, v36, v8
	v_add_co_ci_u32_e32 v41, vcc_lo, v37, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v48, v0
	v_add_co_ci_u32_e32 v37, vcc_lo, v49, v1, vcc_lo
	v_add_co_u32 v48, vcc_lo, s18, v22
	v_add_co_ci_u32_e32 v49, vcc_lo, s19, v23, vcc_lo
	global_load_b64 v[66:67], v[34:35], off
	v_add_co_u32 v34, vcc_lo, v36, v8
	v_add_co_ci_u32_e32 v35, vcc_lo, v37, v9, vcc_lo
	v_add_co_u32 v36, vcc_lo, s16, v70
	v_add_co_ci_u32_e32 v37, vcc_lo, s17, v71, vcc_lo
	v_add_co_u32 v48, vcc_lo, v48, v0
	v_add_co_ci_u32_e32 v49, vcc_lo, v49, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v62, vcc_lo, v36, v0
	v_add_co_ci_u32_e32 v63, vcc_lo, v37, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, v48, v8
	v_add_co_ci_u32_e32 v37, vcc_lo, v49, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v62, v8
	v_add_co_ci_u32_e32 v49, vcc_lo, v63, v9, vcc_lo
	v_add_co_u32 v86, vcc_lo, s18, v70
	v_add_co_ci_u32_e32 v87, vcc_lo, s19, v71, vcc_lo
	s_clause 0x1
	global_load_b64 v[76:77], v[48:49], off
	global_load_b64 v[34:35], v[34:35], off
	v_add_co_u32 v48, vcc_lo, s16, v60
	v_add_co_ci_u32_e32 v49, vcc_lo, s17, v61, vcc_lo
	global_load_b64 v[36:37], v[36:37], off
	v_add_co_u32 v48, vcc_lo, v48, v0
	v_add_co_ci_u32_e32 v49, vcc_lo, v49, v1, vcc_lo
	v_add_co_u32 v62, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v63, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v48, v8
	v_add_co_ci_u32_e32 v49, vcc_lo, v49, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v84, vcc_lo, v62, v0
	v_add_co_ci_u32_e32 v85, vcc_lo, v63, v1, vcc_lo
	global_load_b64 v[62:63], v[40:41], off
	global_load_b64 v[64:65], v[48:49], off
	v_add_co_u32 v48, vcc_lo, s16, v52
	v_add_co_ci_u32_e32 v49, vcc_lo, s17, v53, vcc_lo
	v_add_co_u32 v40, vcc_lo, s18, v52
	v_add_co_ci_u32_e32 v41, vcc_lo, s19, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v48, v0
	v_add_co_ci_u32_e32 v49, vcc_lo, v49, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v68, vcc_lo, v40, v0
	v_add_co_ci_u32_e32 v69, vcc_lo, v41, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v40, vcc_lo, v48, v8
	v_add_co_ci_u32_e32 v41, vcc_lo, v49, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v68, v8
	v_add_co_ci_u32_e32 v49, vcc_lo, v69, v9, vcc_lo
	v_add_co_u32 v96, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v97, vcc_lo, s19, v3, vcc_lo
	global_load_b64 v[72:73], v[40:41], off
	global_load_b64 v[68:69], v[48:49], off
	v_add_co_u32 v40, vcc_lo, v96, v0
	v_add_co_ci_u32_e32 v41, vcc_lo, v97, v1, vcc_lo
	v_add_co_u32 v84, vcc_lo, v84, v8
	v_add_co_ci_u32_e32 v85, vcc_lo, v85, v9, vcc_lo
	v_add_co_u32 v48, vcc_lo, v86, v0
	v_add_co_ci_u32_e32 v49, vcc_lo, v87, v1, vcc_lo
	v_add_co_u32 v86, vcc_lo, v40, v8
	v_add_co_ci_u32_e32 v87, vcc_lo, v41, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v96, vcc_lo, v48, v8
	v_add_co_ci_u32_e32 v97, vcc_lo, v49, v9, vcc_lo
	v_add_co_u32 v104, vcc_lo, s18, v74
	v_add_co_ci_u32_e32 v105, vcc_lo, s19, v75, vcc_lo
	global_load_b64 v[40:41], v[84:85], off
	s_clause 0x1
	global_load_b64 v[48:49], v[86:87], off
	global_load_b64 v[102:103], v[96:97], off
	v_add_co_u32 v96, vcc_lo, v104, v0
	v_add_co_ci_u32_e32 v97, vcc_lo, v105, v1, vcc_lo
	global_load_b64 v[82:83], v[82:83], off
	v_add_co_u32 v96, vcc_lo, v96, v8
	v_add_co_ci_u32_e32 v97, vcc_lo, v97, v9, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x457000, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v84, vcc_lo, 0x457000, v84
	v_add_co_ci_u32_e32 v85, vcc_lo, 0, v85, vcc_lo
	v_add_co_u32 v104, vcc_lo, s18, v60
	v_add_co_ci_u32_e32 v105, vcc_lo, s19, v61, vcc_lo
	global_load_b64 v[84:85], v[84:85], off offset:2816
	v_add_co_u32 v104, vcc_lo, v104, v0
	v_add_co_ci_u32_e32 v105, vcc_lo, v105, v1, vcc_lo
	v_add_co_u32 v106, vcc_lo, s12, v94
	v_add_co_ci_u32_e32 v107, vcc_lo, s13, v95, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v104, vcc_lo, v104, v8
	v_add_co_ci_u32_e32 v105, vcc_lo, v105, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v106, vcc_lo, v106, v0
	v_add_co_ci_u32_e32 v107, vcc_lo, v107, v1, vcc_lo
	v_add_co_u32 v108, vcc_lo, 0x457000, v86
	v_add_co_ci_u32_e32 v109, vcc_lo, 0, v87, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v110, vcc_lo, v106, v8
	v_add_co_ci_u32_e32 v111, vcc_lo, v107, v9, vcc_lo
	v_add_co_u32 v114, vcc_lo, s12, v100
	v_add_co_ci_u32_e32 v115, vcc_lo, s13, v101, vcc_lo
	global_load_b64 v[42:43], v[42:43], off offset:2816
	s_clause 0x2
	global_load_b64 v[106:107], v[96:97], off
	global_load_b64 v[86:87], v[104:105], off
	global_load_b64 v[104:105], v[108:109], off offset:2816
	global_load_b64 v[108:109], v[110:111], off
	v_add_co_u32 v96, vcc_lo, s12, v70
	v_add_co_ci_u32_e32 v97, vcc_lo, s13, v71, vcc_lo
	v_add_co_u32 v110, vcc_lo, s12, v52
	v_add_co_ci_u32_e32 v111, vcc_lo, s13, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v116, vcc_lo, v96, v0
	v_add_co_ci_u32_e32 v117, vcc_lo, v97, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v120, vcc_lo, v110, v0
	v_add_co_ci_u32_e32 v121, vcc_lo, v111, v1, vcc_lo
	v_add_co_u32 v96, vcc_lo, s12, v50
	v_add_co_ci_u32_e32 v97, vcc_lo, s13, v51, vcc_lo
	v_add_co_u32 v110, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v111, vcc_lo, s13, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v96, vcc_lo, v96, v0
	v_add_co_ci_u32_e32 v97, vcc_lo, v97, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v110, vcc_lo, v110, v0
	v_add_co_ci_u32_e32 v111, vcc_lo, v111, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v96, vcc_lo, v96, v8
	v_add_co_ci_u32_e32 v97, vcc_lo, v97, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v118, vcc_lo, v110, v8
	v_add_co_ci_u32_e32 v119, vcc_lo, v111, v9, vcc_lo
	global_load_b64 v[112:113], v[96:97], off
	v_add_co_u32 v122, vcc_lo, s12, v60
	v_add_co_ci_u32_e32 v123, vcc_lo, s13, v61, vcc_lo
	v_add_co_u32 v110, vcc_lo, v116, v8
	v_add_co_ci_u32_e32 v111, vcc_lo, v117, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v122, vcc_lo, v122, v0
	v_add_co_ci_u32_e32 v123, vcc_lo, v123, v1, vcc_lo
	v_add_co_u32 v116, vcc_lo, v120, v8
	v_add_co_ci_u32_e32 v117, vcc_lo, v121, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v120, vcc_lo, v122, v8
	v_add_co_ci_u32_e32 v121, vcc_lo, v123, v9, vcc_lo
	v_add_co_u32 v122, vcc_lo, v114, v0
	v_add_co_ci_u32_e32 v123, vcc_lo, v115, v1, vcc_lo
	s_clause 0x3
	global_load_b64 v[96:97], v[118:119], off
	global_load_b64 v[114:115], v[110:111], off
	global_load_b64 v[116:117], v[116:117], off
	global_load_b64 v[110:111], v[120:121], off
	v_add_co_u32 v120, vcc_lo, s12, v22
	v_add_co_ci_u32_e32 v121, vcc_lo, s13, v23, vcc_lo
	v_add_co_u32 v118, vcc_lo, 0x457000, v118
	v_add_co_ci_u32_e32 v119, vcc_lo, 0, v119, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v120, vcc_lo, v120, v0
	v_add_co_ci_u32_e32 v121, vcc_lo, v121, v1, vcc_lo
	global_load_b64 v[124:125], v[118:119], off offset:2816
	v_add_co_u32 v118, vcc_lo, v120, v8
	v_add_co_ci_u32_e32 v119, vcc_lo, v121, v9, vcc_lo
	v_add_co_u32 v120, vcc_lo, v122, v8
	v_add_co_ci_u32_e32 v121, vcc_lo, v123, v9, vcc_lo
	s_clause 0x1
	global_load_b64 v[118:119], v[118:119], off
	global_load_b64 v[126:127], v[120:121], off
	v_add_co_u32 v120, vcc_lo, s12, v74
	v_add_co_ci_u32_e32 v121, vcc_lo, s13, v75, vcc_lo
	v_add_co_u32 v122, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v123, vcc_lo, s7, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v120, vcc_lo, v120, v0
	v_add_co_ci_u32_e32 v121, vcc_lo, v121, v1, vcc_lo
	v_add_co_u32 v128, vcc_lo, s14, v94
	v_add_co_ci_u32_e32 v129, vcc_lo, s15, v95, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v94, vcc_lo, v120, v8
	v_add_co_ci_u32_e32 v95, vcc_lo, v121, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v120, vcc_lo, v128, v0
	v_add_co_ci_u32_e32 v121, vcc_lo, v129, v1, vcc_lo
	global_load_b64 v[128:129], v[94:95], off
	v_add_co_u32 v94, vcc_lo, v120, v8
	v_add_co_ci_u32_e32 v95, vcc_lo, v121, v9, vcc_lo
	v_add_co_u32 v120, vcc_lo, v122, v0
	v_add_co_ci_u32_e32 v121, vcc_lo, v123, v1, vcc_lo
	global_load_b64 v[130:131], v[94:95], off
	v_add_co_u32 v94, vcc_lo, v120, v8
	v_add_co_ci_u32_e32 v95, vcc_lo, v121, v9, vcc_lo
	v_add_co_u32 v120, vcc_lo, s14, v22
	v_add_co_ci_u32_e32 v121, vcc_lo, s15, v23, vcc_lo
	v_add_co_u32 v100, vcc_lo, s14, v100
	v_add_co_ci_u32_e32 v101, vcc_lo, s15, v101, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v120, vcc_lo, v120, v0
	global_load_b64 v[132:133], v[94:95], off
	v_add_co_ci_u32_e32 v121, vcc_lo, v121, v1, vcc_lo
	v_add_co_u32 v122, vcc_lo, v100, v0
	v_add_co_ci_u32_e32 v123, vcc_lo, v101, v1, vcc_lo
	v_add_co_u32 v100, vcc_lo, v120, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v101, vcc_lo, v121, v9, vcc_lo
	v_add_co_u32 v120, vcc_lo, v122, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v121, vcc_lo, v123, v9, vcc_lo
	s_clause 0x1
	global_load_b64 v[122:123], v[100:101], off
	global_load_b64 v[134:135], v[120:121], off
	s_load_b64 s[0:1], s[0:1], 0x68
	s_mov_b32 s3, 0xbfe99999
	s_mov_b32 s2, 0x9999999a
	s_waitcnt vmcnt(47)
	v_add_f64 v[138:139], v[38:39], -v[12:13]
	s_waitcnt vmcnt(30)
	v_mul_f64 v[136:137], v[46:47], v[66:67]
	v_add_f64 v[140:141], v[44:45], -v[12:13]
	v_add_f64 v[148:149], v[46:47], -v[30:31]
	v_add_f64 v[142:143], v[44:45], -v[38:39]
	v_add_f64 v[152:153], v[46:47], -v[32:33]
	v_fma_f64 v[154:155], v[56:57], -v[12:13], -v[54:55]
	v_fma_f64 v[98:99], v[80:81], -v[58:59], -v[98:99]
	v_add_f64 v[58:59], v[46:47], -v[58:59]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[100:101], s[0:1], s[2:3]
	s_mov_b32 s3, 0x3fc99999
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_f64 v[120:121], s[0:1], s[2:3]
	s_mov_b32 s2, 0x6a7ef9db
	s_mov_b32 s3, 0x3fa374bc
	s_waitcnt vmcnt(27)
	v_fma_f64 v[144:145], v[30:31], v[34:35], v[36:37]
	v_fma_f64 v[146:147], -v[32:33], v[76:77], v[136:137]
	v_fma_f64 v[136:137], -v[30:31], v[34:35], v[136:137]
	v_fma_f64 v[98:99], v[46:47], v[66:67], v[98:99]
	s_waitcnt vmcnt(25)
	v_mul_f64 v[150:151], v[28:29], v[64:65]
	v_fma_f64 v[138:139], v[100:101], v[138:139], v[78:79]
	v_mul_f64 v[78:79], s[0:1], s[2:3]
	v_fma_f64 v[148:149], v[100:101], v[148:149], v[88:89]
	v_fma_f64 v[92:93], v[120:121], v[140:141], v[92:93]
	v_add_f64 v[140:141], v[44:45], -v[16:17]
	v_fma_f64 v[142:143], v[100:101], v[142:143], v[90:91]
	s_mov_b32 s2, 0x3126e979
	s_mov_b32 s3, 0x3f6cac08
	v_add_co_u32 v90, vcc_lo, s16, v18
	v_add_co_ci_u32_e32 v91, vcc_lo, s17, v19, vcc_lo
	v_add_co_u32 v156, vcc_lo, s18, v18
	v_add_co_ci_u32_e32 v157, vcc_lo, s19, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v90, vcc_lo, v90, v0
	v_fma_f64 v[158:159], -v[32:33], v[76:77], v[144:145]
	v_add_co_ci_u32_e32 v91, vcc_lo, v91, v1, vcc_lo
	v_add_co_u32 v156, vcc_lo, v156, v0
	v_add_f64 v[146:147], v[62:63], v[146:147]
	v_add_co_ci_u32_e32 v157, vcc_lo, v157, v1, vcc_lo
	v_add_co_u32 v90, vcc_lo, v90, v8
	s_waitcnt vmcnt(23)
	v_fma_f64 v[160:161], v[72:73], -v[16:17], -v[68:69]
	v_add_f64 v[98:99], v[62:63], v[98:99]
	v_add_co_ci_u32_e32 v91, vcc_lo, v91, v9, vcc_lo
	v_add_co_u32 v156, vcc_lo, v156, v8
	v_add_co_ci_u32_e32 v157, vcc_lo, v157, v9, vcc_lo
	v_fma_f64 v[88:89], -v[12:13], v[56:57], v[150:151]
	global_load_b64 v[90:91], v[90:91], off
	global_load_b64 v[156:157], v[156:157], off
	v_fma_f64 v[92:93], -v[78:79], v[152:153], v[92:93]
	v_fma_f64 v[138:139], -v[78:79], v[140:141], v[138:139]
	v_add_f64 v[140:141], v[46:47], -v[24:25]
	v_add_f64 v[152:153], v[28:29], -v[38:39]
	v_fma_f64 v[46:47], v[46:47], v[66:67], v[62:63]
	v_add_f64 v[62:63], v[62:63], v[136:137]
	s_waitcnt vmcnt(23)
	v_fma_f64 v[150:151], v[40:41], -v[24:25], -v[48:49]
	s_waitcnt vmcnt(22)
	v_fma_f64 v[162:163], v[76:77], -v[32:33], -v[102:103]
	v_add_f64 v[158:159], v[158:159], -v[102:103]
	v_add_f64 v[102:103], v[146:147], -v[102:103]
	s_waitcnt vmcnt(21)
	v_fma_f64 v[146:147], v[26:27], v[82:83], v[154:155]
	v_fma_f64 v[160:161], v[28:29], v[64:65], v[160:161]
	v_add_f64 v[164:165], v[88:89], -v[54:55]
	v_mul_f64 v[88:89], s[0:1], s[2:3]
	v_fma_f64 v[140:141], v[120:121], v[140:141], v[142:143]
	v_fma_f64 v[142:143], v[120:121], v[152:153], v[148:149]
	v_fma_f64 v[46:47], -v[24:25], v[40:41], v[46:47]
	v_add_f64 v[36:37], v[62:63], -v[36:37]
	v_mul_f64 v[102:103], v[78:79], v[102:103]
	s_waitcnt vmcnt(18)
	v_add_f64 v[106:107], v[106:107], v[146:147]
	v_mul_f64 v[146:147], v[120:121], v[158:159]
	v_fma_f64 v[150:151], v[42:43], v[84:85], v[150:151]
	v_fma_f64 v[162:163], v[42:43], v[84:85], v[162:163]
	s_waitcnt vmcnt(17)
	v_add_f64 v[148:149], v[86:87], v[160:161]
	s_waitcnt vmcnt(15)
	v_mul_f64 v[108:109], v[66:67], v[108:109]
	v_add_co_u32 v158, vcc_lo, s12, v20
	v_add_co_ci_u32_e32 v159, vcc_lo, s13, v21, vcc_lo
	v_add_f64 v[152:153], v[86:87], v[164:165]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v158, vcc_lo, v158, v0
	v_add_co_ci_u32_e32 v159, vcc_lo, v159, v1, vcc_lo
	v_add_co_u32 v160, vcc_lo, s12, v18
	v_add_co_ci_u32_e32 v161, vcc_lo, s13, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v158, vcc_lo, v158, v8
	v_add_co_ci_u32_e32 v159, vcc_lo, v159, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v160, vcc_lo, v160, v0
	v_add_co_ci_u32_e32 v161, vcc_lo, v161, v1, vcc_lo
	global_load_b64 v[158:159], v[158:159], off
	v_add_co_u32 v160, vcc_lo, v160, v8
	v_add_co_ci_u32_e32 v161, vcc_lo, v161, v9, vcc_lo
	v_add_f64 v[46:47], v[46:47], -v[48:49]
	v_fma_f64 v[58:59], v[88:89], v[58:59], v[138:139]
	global_load_b64 v[160:161], v[160:161], off
	v_fma_f64 v[98:99], v[88:89], v[98:99], v[146:147]
	v_add_f64 v[150:151], v[104:105], v[150:151]
	v_add_f64 v[104:105], v[104:105], v[162:163]
	v_fma_f64 v[102:103], v[88:89], v[148:149], -v[102:103]
	s_waitcnt vmcnt(16)
	v_mul_f64 v[112:113], v[56:57], v[112:113]
	v_mul_f64 v[152:153], v[78:79], v[152:153]
	s_waitcnt vmcnt(14)
	v_fma_f64 v[146:147], -v[76:77], v[114:115], v[108:109]
	v_mul_f64 v[162:163], v[40:41], v[96:97]
	v_mul_f64 v[114:115], v[76:77], v[114:115]
	s_waitcnt vmcnt(13)
	v_mul_f64 v[116:117], v[72:73], v[116:117]
	v_mul_f64 v[150:151], v[78:79], v[150:151]
	s_waitcnt vmcnt(12)
	v_fma_f64 v[148:149], v[64:65], v[110:111], -v[112:113]
	v_fma_f64 v[104:105], v[88:89], v[104:105], -v[152:153]
	v_add_co_u32 v152, vcc_lo, s14, v70
	v_add_co_ci_u32_e32 v153, vcc_lo, s15, v71, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v152, vcc_lo, v152, v0
	s_waitcnt vmcnt(9)
	v_fma_f64 v[70:71], -v[80:81], v[126:127], v[108:109]
	v_add_co_ci_u32_e32 v153, vcc_lo, v153, v1, vcc_lo
	v_mul_f64 v[126:127], v[78:79], v[146:147]
	v_fma_f64 v[162:163], v[84:85], v[124:125], -v[162:163]
	v_fma_f64 v[124:125], v[84:85], v[124:125], -v[114:115]
	v_add_co_u32 v146, vcc_lo, v152, v8
	v_add_co_ci_u32_e32 v147, vcc_lo, v153, v9, vcc_lo
	v_fma_f64 v[152:153], v[64:65], v[110:111], -v[116:117]
	v_fma_f64 v[106:107], v[88:89], v[106:107], -v[150:151]
	global_load_b64 v[146:147], v[146:147], off
	s_waitcnt vmcnt(9)
	v_fma_f64 v[128:129], v[82:83], v[128:129], -v[112:113]
	v_mul_f64 v[148:149], v[78:79], v[148:149]
	v_fma_f64 v[46:47], v[120:121], v[46:47], v[104:105]
	s_waitcnt vmcnt(8)
	v_mul_f64 v[130:131], v[66:67], v[130:131]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[70:71], v[88:89], v[70:71], v[132:133]
	v_add_co_u32 v132, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v133, vcc_lo, s9, v3, vcc_lo
	v_mul_f64 v[162:163], v[78:79], v[162:163]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v132, vcc_lo, v132, v0
	v_add_co_ci_u32_e32 v133, vcc_lo, v133, v1, vcc_lo
	v_fma_f64 v[126:127], v[88:89], v[152:153], -v[126:127]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v132, vcc_lo, v132, v8
	v_add_co_ci_u32_e32 v133, vcc_lo, v133, v9, vcc_lo
	v_fma_f64 v[124:125], v[88:89], v[124:125], -v[148:149]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[80:81], -v[80:81], v[134:135], v[130:131]
	v_add_co_u32 v134, vcc_lo, s14, v50
	v_add_co_ci_u32_e32 v135, vcc_lo, s15, v51, vcc_lo
	global_load_b64 v[50:51], v[132:133], off
	v_add_co_u32 v134, vcc_lo, v134, v0
	v_add_co_ci_u32_e32 v135, vcc_lo, v135, v1, vcc_lo
	v_add_co_u32 v148, vcc_lo, s14, v74
	v_add_co_ci_u32_e32 v149, vcc_lo, s15, v75, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v74, vcc_lo, v134, v8
	v_add_co_ci_u32_e32 v75, vcc_lo, v135, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v134, vcc_lo, v148, v0
	v_add_co_ci_u32_e32 v135, vcc_lo, v149, v1, vcc_lo
	v_add_co_u32 v148, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v149, vcc_lo, s15, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v134, vcc_lo, v134, v8
	v_add_co_ci_u32_e32 v135, vcc_lo, v135, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v148, vcc_lo, v148, v0
	v_add_co_ci_u32_e32 v149, vcc_lo, v149, v1, vcc_lo
	global_load_b64 v[74:75], v[74:75], off
	v_add_co_u32 v148, vcc_lo, v148, v8
	v_add_co_ci_u32_e32 v149, vcc_lo, v149, v9, vcc_lo
	v_add_co_u32 v52, vcc_lo, s14, v52
	v_add_co_ci_u32_e32 v53, vcc_lo, s15, v53, vcc_lo
	v_add_co_u32 v60, vcc_lo, s14, v60
	v_add_co_ci_u32_e32 v61, vcc_lo, s15, v61, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v52, vcc_lo, v52, v0
	v_add_co_ci_u32_e32 v53, vcc_lo, v53, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v60, vcc_lo, v60, v0
	v_add_co_ci_u32_e32 v61, vcc_lo, v61, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v52, vcc_lo, v52, v8
	v_add_co_ci_u32_e32 v53, vcc_lo, v53, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v60, vcc_lo, v60, v8
	v_add_co_ci_u32_e32 v61, vcc_lo, v61, v9, vcc_lo
	v_add_co_u32 v150, vcc_lo, s14, v20
	v_add_co_ci_u32_e32 v151, vcc_lo, s15, v21, vcc_lo
	v_add_co_u32 v152, vcc_lo, s14, v18
	v_add_co_ci_u32_e32 v153, vcc_lo, s15, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v150, vcc_lo, v150, v0
	v_add_co_ci_u32_e32 v151, vcc_lo, v151, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v152, vcc_lo, v152, v0
	v_add_co_ci_u32_e32 v153, vcc_lo, v153, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v150, vcc_lo, v150, v8
	v_add_co_ci_u32_e32 v151, vcc_lo, v151, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v152, vcc_lo, v152, v8
	v_add_co_ci_u32_e32 v153, vcc_lo, v153, v9, vcc_lo
	v_fma_f64 v[128:129], v[88:89], v[128:129], -v[162:163]
	v_add_co_u32 v162, vcc_lo, 0x457000, v148
	v_add_co_ci_u32_e32 v163, vcc_lo, 0, v149, vcc_lo
	s_clause 0x6
	global_load_b64 v[148:149], v[148:149], off
	global_load_b64 v[52:53], v[52:53], off
	global_load_b64 v[162:163], v[162:163], off offset:2816
	global_load_b64 v[134:135], v[134:135], off
	global_load_b64 v[60:61], v[60:61], off
	global_load_b64 v[150:151], v[150:151], off
	global_load_b64 v[152:153], v[152:153], off
	s_waitcnt vmcnt(13)
	v_mul_f64 v[44:45], v[44:45], v[90:91]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[50:51], v[88:89], v[80:81], v[50:51]
	v_mul_f64 v[80:81], v[76:77], v[146:147]
	v_fma_f64 v[76:77], -v[76:77], v[146:147], v[130:131]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[74:75], v[56:57], v[74:75]
	v_fma_f64 v[56:57], -v[12:13], v[56:57], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[76:77], v[78:79], v[76:77]
	v_add_f64 v[56:57], v[56:57], v[156:157]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[146:147], v[40:41], v[148:149]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[52:53], v[72:73], v[52:53]
	v_fma_f64 v[72:73], -v[16:17], v[72:73], v[44:45]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[82:83], v[82:83], v[134:135], -v[74:75]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[134:135], v[64:65], v[60:61], -v[74:75]
	v_fma_f64 v[62:63], -v[40:41], v[148:149], v[130:131]
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	v_add_f64 v[54:55], v[56:57], -v[54:55]
	v_fma_f64 v[146:147], v[84:85], v[162:163], -v[146:147]
	v_fma_f64 v[84:85], v[84:85], v[162:163], -v[80:81]
	v_fma_f64 v[162:163], v[64:65], v[60:61], -v[52:53]
	v_fma_f64 v[80:81], v[34:35], v[122:123], -v[80:81]
	v_mul_f64 v[134:135], v[78:79], v[134:135]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[52:53], v[90:91], v[152:153], -v[52:53]
	v_fma_f64 v[16:17], v[88:89], v[16:17], v[92:93]
	v_fma_f64 v[54:55], v[120:121], v[54:55], v[102:103]
	v_mul_f64 v[146:147], v[78:79], v[146:147]
	v_fma_f64 v[76:77], v[88:89], v[162:163], -v[76:77]
	v_add_co_u32 v162, vcc_lo, s16, v20
	v_add_co_ci_u32_e32 v163, vcc_lo, s17, v21, vcc_lo
	v_fma_f64 v[84:85], v[88:89], v[84:85], -v[134:135]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v162, vcc_lo, v162, v0
	v_add_co_ci_u32_e32 v163, vcc_lo, v163, v1, vcc_lo
	v_fma_f64 v[50:51], v[120:121], v[80:81], v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v134, vcc_lo, v162, v8
	v_add_co_ci_u32_e32 v135, vcc_lo, v163, v9, vcc_lo
	v_add_co_u32 v162, vcc_lo, s18, v20
	v_add_co_ci_u32_e32 v163, vcc_lo, s19, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v162, vcc_lo, v162, v0
	v_add_co_ci_u32_e32 v163, vcc_lo, v163, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v162, vcc_lo, v162, v8
	v_add_co_ci_u32_e32 v163, vcc_lo, v163, v9, vcc_lo
	global_load_b64 v[134:135], v[134:135], off
	global_load_b64 v[162:163], v[162:163], off
	v_fma_f64 v[82:83], v[88:89], v[82:83], -v[146:147]
	v_fma_f64 v[146:147], -v[40:41], v[96:97], v[108:109]
	v_fma_f64 v[62:63], v[120:121], v[62:63], v[84:85]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[102:103], v[120:121], v[146:147], v[124:125]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[56:57], v[134:135], v[158:159]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[66:67], v[134:135], -v[38:39], -v[162:163]
	v_fma_f64 v[154:155], v[38:39], v[134:135], v[154:155]
	v_fma_f64 v[38:39], -v[38:39], v[134:135], v[44:45]
	v_mul_f64 v[44:45], v[134:135], v[150:151]
	v_fma_f64 v[104:105], v[134:135], v[158:159], -v[112:113]
	v_fma_f64 v[80:81], v[134:135], v[150:151], -v[74:75]
	v_fma_f64 v[74:75], v[90:91], v[152:153], -v[74:75]
	v_fma_f64 v[110:111], v[64:65], v[110:111], -v[56:57]
	v_fma_f64 v[66:67], v[28:29], v[64:65], v[66:67]
	v_add_f64 v[154:155], v[162:163], v[154:155]
	v_add_f64 v[38:39], v[38:39], v[156:157]
	v_fma_f64 v[60:61], v[64:65], v[60:61], -v[44:45]
	v_add_f64 v[64:65], v[72:73], -v[68:69]
	v_add_co_u32 v68, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v69, vcc_lo, s11, v3, vcc_lo
	v_fma_f64 v[2:3], -v[24:25], v[40:41], v[144:145]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v68, vcc_lo, v68, v0
	v_add_co_ci_u32_e32 v69, vcc_lo, v69, v1, vcc_lo
	v_add_co_u32 v72, vcc_lo, s10, v20
	v_add_co_ci_u32_e32 v73, vcc_lo, s11, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v68, vcc_lo, v68, v8
	v_add_co_ci_u32_e32 v69, vcc_lo, v69, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v72, vcc_lo, v72, v0
	v_add_co_ci_u32_e32 v73, vcc_lo, v73, v1, vcc_lo
	v_add_f64 v[28:29], v[28:29], -v[12:13]
	v_fma_f64 v[74:75], v[120:121], v[74:75], v[76:77]
	v_fma_f64 v[56:57], v[90:91], v[160:161], -v[56:57]
	v_fma_f64 v[44:45], v[90:91], v[152:153], -v[44:45]
	v_add_f64 v[12:13], v[26:27], -v[12:13]
	v_add_f64 v[26:27], v[42:43], -v[32:33]
	v_add_f64 v[32:33], v[30:31], -v[32:33]
	v_fma_f64 v[50:51], v[100:101], v[80:81], v[50:51]
	v_add_f64 v[66:67], v[86:87], v[66:67]
	v_fma_f64 v[86:87], v[34:35], v[118:119], -v[114:115]
	v_fma_f64 v[114:115], v[90:91], v[160:161], -v[112:113]
	v_add_f64 v[38:39], v[38:39], -v[162:163]
	v_mul_f64 v[162:163], v[34:35], v[118:119]
	v_add_f64 v[64:65], v[156:157], v[64:65]
	v_mul_f64 v[156:157], v[34:35], v[122:123]
	v_fma_f64 v[98:99], v[100:101], v[154:155], v[98:99]
	v_add_f64 v[154:155], v[42:43], -v[24:25]
	v_add_f64 v[2:3], v[2:3], -v[48:49]
	v_fma_f64 v[60:61], v[120:121], v[60:61], v[82:83]
	v_add_f64 v[24:25], v[30:31], -v[24:25]
	v_fma_f64 v[28:29], -v[78:79], v[28:29], v[140:141]
	v_fma_f64 v[56:57], v[100:101], v[56:57], v[102:103]
	v_fma_f64 v[44:45], v[100:101], v[44:45], v[62:63]
	v_fma_f64 v[32:33], v[120:121], v[32:33], v[58:59]
	v_fma_f64 v[66:67], v[120:121], v[66:67], v[106:107]
	v_fma_f64 v[106:107], v[120:121], v[110:111], v[128:129]
	v_add_co_u32 v110, vcc_lo, s10, v22
	v_add_co_ci_u32_e32 v111, vcc_lo, s11, v23, vcc_lo
	v_add_co_u32 v72, vcc_lo, v72, v8
	v_add_co_ci_u32_e32 v73, vcc_lo, v73, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v110, vcc_lo, v110, v0
	v_add_co_ci_u32_e32 v111, vcc_lo, v111, v1, vcc_lo
	v_add_co_u32 v112, vcc_lo, s10, v18
	v_add_co_ci_u32_e32 v113, vcc_lo, s11, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v110, vcc_lo, v110, v8
	v_add_co_ci_u32_e32 v111, vcc_lo, v111, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v112, vcc_lo, v112, v0
	v_add_co_ci_u32_e32 v113, vcc_lo, v113, v1, vcc_lo
	v_fma_f64 v[70:71], v[120:121], v[86:87], v[70:71]
	v_fma_f64 v[86:87], v[120:121], v[114:115], v[126:127]
	v_add_co_u32 v114, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v115, vcc_lo, s7, v21, vcc_lo
	v_add_co_u32 v112, vcc_lo, v112, v8
	v_add_co_ci_u32_e32 v113, vcc_lo, v113, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v114, vcc_lo, v114, v0
	v_add_co_ci_u32_e32 v115, vcc_lo, v115, v1, vcc_lo
	v_add_co_u32 v124, vcc_lo, s6, v22
	v_add_co_ci_u32_e32 v125, vcc_lo, s7, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v114, vcc_lo, v114, v8
	v_add_co_ci_u32_e32 v115, vcc_lo, v115, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v124, vcc_lo, v124, v0
	v_add_co_ci_u32_e32 v125, vcc_lo, v125, v1, vcc_lo
	v_add_co_u32 v126, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v127, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v124, vcc_lo, v124, v8
	v_add_co_ci_u32_e32 v125, vcc_lo, v125, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v126, vcc_lo, v126, v0
	v_add_co_ci_u32_e32 v127, vcc_lo, v127, v1, vcc_lo
	v_add_co_u32 v128, vcc_lo, s8, v20
	v_add_co_ci_u32_e32 v129, vcc_lo, s9, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, v126, v8
	v_add_co_ci_u32_e32 v21, vcc_lo, v127, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v128, vcc_lo, v128, v0
	v_add_co_ci_u32_e32 v129, vcc_lo, v129, v1, vcc_lo
	global_load_b64 v[126:127], v[68:69], off
	v_add_co_u32 v128, vcc_lo, v128, v8
	v_add_co_ci_u32_e32 v129, vcc_lo, v129, v9, vcc_lo
	v_add_co_u32 v22, vcc_lo, s8, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s9, v23, vcc_lo
	v_add_co_u32 v18, vcc_lo, s8, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, v22, v0
	v_add_co_ci_u32_e32 v23, vcc_lo, v23, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, v18, v0
	v_add_co_ci_u32_e32 v19, vcc_lo, v19, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v22, v8
	s_clause 0x2
	global_load_b64 v[134:135], v[72:73], off
	global_load_b64 v[136:137], v[110:111], off
	global_load_b64 v[144:145], v[112:113], off
	v_add_co_ci_u32_e32 v1, vcc_lo, v23, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, v18, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, v19, v9, vcc_lo
	s_clause 0x2
	global_load_b64 v[18:19], v[114:115], off
	global_load_b64 v[22:23], v[124:125], off
	global_load_b64 v[146:147], v[20:21], off
	s_clause 0x2
	global_load_b64 v[48:49], v[128:129], off
	global_load_b64 v[150:151], v[0:1], off
	global_load_b64 v[158:159], v[8:9], off
	v_fma_f64 v[76:77], -v[40:41], v[96:97], v[162:163]
	v_fma_f64 v[96:97], -v[34:35], v[118:119], v[108:109]
	v_fma_f64 v[40:41], -v[40:41], v[148:149], v[156:157]
	v_fma_f64 v[34:35], -v[34:35], v[122:123], v[130:131]
	v_fma_f64 v[82:83], -v[78:79], v[154:155], v[142:143]
	v_fma_f64 v[30:31], v[100:101], v[38:39], v[46:47]
	v_fma_f64 v[38:39], -v[78:79], v[64:65], v[98:99]
	v_fma_f64 v[2:3], v[100:101], v[2:3], v[54:55]
	v_fma_f64 v[36:37], v[100:101], v[36:37], v[66:67]
	v_fma_f64 v[42:43], v[100:101], v[104:105], v[70:71]
	v_fma_f64 v[46:47], v[90:91], v[160:161], -v[116:117]
	v_fma_f64 v[16:17], v[100:101], v[24:25], v[16:17]
	v_fma_f64 v[24:25], v[88:89], v[26:27], v[28:29]
	v_fma_f64 v[54:55], v[100:101], v[76:77], v[86:87]
	v_fma_f64 v[64:65], v[100:101], v[96:97], v[106:107]
	v_fma_f64 v[40:41], v[100:101], v[40:41], v[74:75]
	v_fma_f64 v[34:35], v[100:101], v[34:35], v[60:61]
	v_fma_f64 v[12:13], v[88:89], v[12:13], v[82:83]
	s_waitcnt vmcnt(9)
	v_add_f64 v[26:27], v[126:127], v[38:39]
	s_waitcnt vmcnt(8)
	v_add_f64 v[2:3], v[134:135], v[2:3]
	s_waitcnt vmcnt(7)
	v_add_f64 v[28:29], v[136:137], v[30:31]
	s_waitcnt vmcnt(6)
	v_add_f64 v[30:31], v[144:145], v[36:37]
	v_fma_f64 v[36:37], -v[78:79], v[46:47], v[42:43]
	v_fma_f64 v[42:43], -v[78:79], v[52:53], v[50:51]
	s_waitcnt vmcnt(5)
	v_add_f64 v[18:19], v[18:19], v[54:55]
	s_waitcnt vmcnt(4)
	v_add_f64 v[22:23], v[22:23], v[56:57]
	s_waitcnt vmcnt(3)
	v_add_f64 v[38:39], v[146:147], v[64:65]
	s_waitcnt vmcnt(2)
	v_add_f64 v[40:41], v[48:49], v[40:41]
	s_waitcnt vmcnt(1)
	v_add_f64 v[44:45], v[150:151], v[44:45]
	s_waitcnt vmcnt(0)
	v_add_f64 v[34:35], v[158:159], v[34:35]
	s_clause 0x3
	global_store_b64 v[4:5], v[32:33], off
	global_store_b64 v[6:7], v[16:17], off
	global_store_b64 v[10:11], v[24:25], off
	global_store_b64 v[14:15], v[12:13], off
	s_clause 0x3
	global_store_b64 v[68:69], v[26:27], off
	global_store_b64 v[72:73], v[2:3], off
	global_store_b64 v[110:111], v[28:29], off
	global_store_b64 v[112:113], v[30:31], off
	s_clause 0x3
	global_store_b64 v[94:95], v[36:37], off
	global_store_b64 v[114:115], v[18:19], off
	global_store_b64 v[124:125], v[22:23], off
	global_store_b64 v[20:21], v[38:39], off
	s_clause 0x3
	global_store_b64 v[132:133], v[42:43], off
	global_store_b64 v[128:129], v[40:41], off
	global_store_b64 v[0:1], v[44:45], off
	global_store_b64 v[8:9], v[34:35], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 166
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii, .Lfunc_end1-_Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6040
; NumSgprs: 22
; NumVgprs: 166
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 20
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 166
; Occupancy: 9
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9hypterm_2PdS_S_S_S_S_dddiii ; -- Begin function _Z9hypterm_2PdS_S_S_S_S_dddiii
	.globl	_Z9hypterm_2PdS_S_S_S_S_dddiii
	.p2align	8
	.type	_Z9hypterm_2PdS_S_S_S_S_dddiii,@function
_Z9hypterm_2PdS_S_S_S_S_dddiii:         ; @_Z9hypterm_2PdS_S_S_S_S_dddiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x64
	s_load_b32 s4, s[0:1], 0x50
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_and_b32 s5, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s13, s13, s5
	s_mul_i32 s15, s15, s3
	s_mul_i32 s14, s14, s2
	s_max_i32 s2, s13, 0
	s_lshl_b32 s5, s15, 1
	s_max_i32 s3, s14, 0
	v_add_nc_u32_e32 v12, s2, v1
	s_max_i32 s2, s5, 0
	v_add_nc_u32_e32 v79, s3, v2
	v_lshl_add_u32 v78, v0, 1, s2
	s_add_i32 s4, s4, -5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min3_u32 v0, v12, v79, v78
	v_max3_i32 v1, v12, v79, v78
	v_cmp_lt_u32_e32 vcc_lo, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s4, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_or_b32_e32 v0, 1, v78
	v_mad_u64_u32 v[50:51], null, 0x9a0, v79, 0
	s_load_b256 s[12:19], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v13, v1
	v_mad_u64_u32 v[52:53], null, 0xb9480, v0, 0
	v_mad_u64_u32 v[54:55], null, 0xb9480, v78, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[48:49], 3, v[12:13]
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fc99999
	s_load_b64 s[0:1], s[0:1], 0x40
	v_add_co_u32 v0, vcc_lo, v48, -8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v49, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v84, vcc_lo, s6, v52
	v_add_co_ci_u32_e32 v85, vcc_lo, s7, v53, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v52
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v80, vcc_lo, v84, v50
	v_add_co_ci_u32_e32 v81, vcc_lo, v85, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, v2, v50
	v_add_co_ci_u32_e32 v14, vcc_lo, v3, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, v80, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, v81, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, v13, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, v14, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, v48, -16
	v_add_co_ci_u32_e32 v18, vcc_lo, -1, v49, vcc_lo
	v_add_co_u32 v86, vcc_lo, s14, v52
	v_add_co_ci_u32_e32 v87, vcc_lo, s15, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v80, v11
	v_add_co_ci_u32_e32 v7, vcc_lo, v81, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v82, vcc_lo, v86, v50
	v_add_co_ci_u32_e32 v83, vcc_lo, v87, v51, vcc_lo
	v_add_co_u32 v8, vcc_lo, v13, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v14, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, v82, v0
	v_add_co_ci_u32_e32 v16, vcc_lo, v83, v10, vcc_lo
	v_add_co_u32 v17, vcc_lo, v82, v11
	v_add_co_ci_u32_e32 v18, vcc_lo, v83, v18, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[10:11], v[6:7], off
	global_load_b64 v[6:7], v[8:9], off
	s_clause 0x1
	global_load_b64 v[8:9], v[15:16], off
	global_load_b64 v[28:29], v[17:18], off
	v_add_nc_u32_e32 v0, 1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v15, vcc_lo, v80, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, v81, v1, vcc_lo
	v_add_co_u32 v17, vcc_lo, v13, v0
	v_add_co_ci_u32_e32 v18, vcc_lo, v14, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v82, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v83, v1, vcc_lo
	global_load_b128 v[60:63], v[15:16], off
	global_load_b128 v[66:69], v[17:18], off
	global_load_b128 v[70:73], v[0:1], off
	v_add_co_u32 v25, vcc_lo, 0xffffffe8, v48
	v_add_co_ci_u32_e32 v26, vcc_lo, -1, v49, vcc_lo
	v_add_co_u32 v27, vcc_lo, 0xffffffe0, v48
	v_add_co_ci_u32_e32 v31, vcc_lo, -1, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, v80, v25
	v_add_co_ci_u32_e32 v20, vcc_lo, v81, v26, vcc_lo
	v_add_co_u32 v21, vcc_lo, v13, v25
	v_add_co_ci_u32_e32 v22, vcc_lo, v14, v26, vcc_lo
	v_add_co_u32 v23, vcc_lo, v80, v27
	v_add_co_ci_u32_e32 v24, vcc_lo, v81, v31, vcc_lo
	v_add_co_u32 v12, vcc_lo, v13, v27
	v_add_co_ci_u32_e32 v13, vcc_lo, v14, v31, vcc_lo
	v_add_co_u32 v25, vcc_lo, v82, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, v83, v26, vcc_lo
	v_add_co_u32 v30, vcc_lo, v82, v27
	v_add_co_ci_u32_e32 v31, vcc_lo, v83, v31, vcc_lo
	global_load_b64 v[74:75], v[19:20], off
	global_load_b64 v[88:89], v[21:22], off
	global_load_b64 v[76:77], v[23:24], off
	global_load_b64 v[90:91], v[12:13], off
	s_clause 0x1
	global_load_b64 v[92:93], v[25:26], off
	global_load_b64 v[94:95], v[30:31], off
	v_add_co_u32 v12, vcc_lo, s6, v54
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v55, vcc_lo
	v_add_co_u32 v14, vcc_lo, s8, v54
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v55, vcc_lo
	v_add_co_u32 v20, vcc_lo, s14, v54
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v55, vcc_lo
	v_add_co_u32 v12, vcc_lo, v12, v50
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v51, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v50
	v_add_co_ci_u32_e32 v24, vcc_lo, v19, v51, vcc_lo
	v_add_co_u32 v19, vcc_lo, v20, v50
	v_add_co_ci_u32_e32 v20, vcc_lo, v21, v51, vcc_lo
	v_add_co_u32 v58, vcc_lo, v12, v48
	v_add_co_ci_u32_e32 v59, vcc_lo, v13, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v56, vcc_lo, v19, v48
	v_add_co_ci_u32_e32 v57, vcc_lo, v20, v49, vcc_lo
	v_add_co_u32 v96, vcc_lo, v14, v48
	v_add_co_ci_u32_e32 v97, vcc_lo, v24, v49, vcc_lo
	global_load_b128 v[20:23], v[15:16], off offset:16
	global_load_b128 v[16:19], v[17:18], off offset:16
	global_load_b128 v[24:27], v[0:1], off offset:16
	global_load_b128 v[12:15], v[58:59], off offset:-16
	global_load_b128 v[40:43], v[56:57], off offset:-16
	s_mov_b32 s7, 0x3fe99999
	global_load_b128 v[44:47], v[96:97], off offset:-16
	s_mov_b32 s6, s2
	s_mov_b32 s8, 0x6a7ef9db
	s_mov_b32 s9, 0x3fa374bc
	s_waitcnt vmcnt(19)
	v_mul_f64 v[0:1], v[2:3], v[4:5]
	s_waitcnt vmcnt(17)
	v_mul_f64 v[2:3], v[10:11], v[6:7]
	s_waitcnt vmcnt(16)
	v_mul_f64 v[8:9], v[4:5], v[8:9]
	s_waitcnt vmcnt(15)
	v_mul_f64 v[10:11], v[6:7], v[28:29]
	global_load_b128 v[32:35], v[58:59], off offset:-32
	global_load_b128 v[28:31], v[96:97], off offset:-32
	global_load_b128 v[36:39], v[56:57], off offset:-32
	global_load_b128 v[4:7], v[58:59], off offset:16
	s_waitcnt vmcnt(17)
	v_fma_f64 v[60:61], v[60:61], v[66:67], -v[0:1]
	v_fma_f64 v[64:65], v[62:63], v[68:69], -v[2:3]
	s_waitcnt vmcnt(16)
	v_fma_f64 v[62:63], v[66:67], v[70:71], -v[8:9]
	v_add_nc_u32_e32 v70, -1, v79
	v_fma_f64 v[66:67], v[68:69], v[72:73], -v[10:11]
	s_clause 0x1
	global_load_b128 v[0:3], v[96:97], off offset:8
	global_load_b128 v[8:11], v[96:97], off offset:24
	s_waitcnt vmcnt(16)
	v_mul_f64 v[68:69], v[74:75], v[88:89]
	s_waitcnt vmcnt(14)
	v_mul_f64 v[76:77], v[76:77], v[90:91]
	s_waitcnt vmcnt(13)
	v_mul_f64 v[72:73], v[88:89], v[92:93]
	s_waitcnt vmcnt(12)
	v_mul_f64 v[74:75], v[90:91], v[94:95]
	global_load_b64 v[90:91], v[58:59], off offset:32
	v_add_co_u32 v92, vcc_lo, s10, v54
	v_mad_i64_i32 v[88:89], null, 0x9a0, v70, 0
	v_add_co_ci_u32_e32 v93, vcc_lo, s11, v55, vcc_lo
	v_add_co_u32 v94, vcc_lo, s10, v52
	v_add_co_ci_u32_e32 v95, vcc_lo, s11, v53, vcc_lo
	v_add_f64 v[60:61], v[60:61], v[62:63]
	s_waitcnt vmcnt(10)
	v_fma_f64 v[72:73], v[16:17], v[24:25], -v[72:73]
	v_fma_f64 v[24:25], v[18:19], v[26:27], -v[74:75]
	v_fma_f64 v[70:71], v[20:21], v[16:17], -v[68:69]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[12:13], v[12:13], v[44:45]
	v_mul_f64 v[40:41], v[44:45], v[40:41]
	v_add_co_u32 v44, vcc_lo, v92, v50
	v_add_co_ci_u32_e32 v45, vcc_lo, v93, v51, vcc_lo
	v_mul_f64 v[14:15], v[14:15], v[46:47]
	v_mul_f64 v[42:43], v[46:47], v[42:43]
	v_fma_f64 v[68:69], v[22:23], v[18:19], -v[76:77]
	s_clause 0x1
	global_load_b64 v[76:77], v[58:59], off offset:-2464
	global_load_b128 v[20:23], v[58:59], off
	global_load_b128 v[16:19], v[56:57], off
	s_waitcnt vmcnt(8)
	v_mul_f64 v[26:27], v[34:35], v[30:31]
	v_mul_f64 v[32:33], v[32:33], v[28:29]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[36:37], v[28:29], v[36:37]
	v_add_co_u32 v28, vcc_lo, v84, v88
	v_add_co_ci_u32_e32 v29, vcc_lo, v85, v89, vcc_lo
	v_add_co_u32 v46, vcc_lo, v94, v88
	v_add_co_ci_u32_e32 v47, vcc_lo, v95, v89, vcc_lo
	v_add_co_u32 v92, vcc_lo, v86, v88
	v_add_co_ci_u32_e32 v93, vcc_lo, v87, v89, vcc_lo
	v_mul_f64 v[30:31], v[30:31], v[38:39]
	v_add_co_u32 v38, vcc_lo, v44, v48
	v_add_co_ci_u32_e32 v39, vcc_lo, v45, v49, vcc_lo
	v_add_co_u32 v44, vcc_lo, v28, v48
	global_load_b64 v[34:35], v[56:57], off offset:-2464
	v_add_co_ci_u32_e32 v45, vcc_lo, v29, v49, vcc_lo
	global_load_b64 v[88:89], v[56:57], off offset:32
	v_add_co_u32 v46, vcc_lo, v46, v48
	v_add_co_ci_u32_e32 v47, vcc_lo, v47, v49, vcc_lo
	s_waitcnt vmcnt(7)
	v_fma_f64 v[74:75], v[4:5], v[2:3], -v[12:13]
	s_waitcnt vmcnt(6)
	v_fma_f64 v[12:13], v[6:7], v[8:9], -v[26:27]
	global_load_b128 v[26:29], v[56:57], off offset:16
	s_waitcnt vmcnt(6)
	v_fma_f64 v[4:5], v[90:91], v[10:11], -v[32:33]
	global_load_b64 v[32:33], v[38:39], off offset:-2464
	s_waitcnt vmcnt(5)
	v_fma_f64 v[14:15], v[22:23], v[0:1], -v[14:15]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[18:19], v[0:1], v[18:19], -v[42:43]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], v[18:19]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[6:7], v[10:11], v[88:89], -v[36:37]
	global_load_b64 v[10:11], v[38:39], off offset:2464
	v_add_nc_u32_e32 v88, -2, v79
	s_waitcnt vmcnt(2)
	v_fma_f64 v[8:9], v[8:9], v[28:29], -v[30:31]
	global_load_b64 v[28:29], v[58:59], off offset:2464
	v_add_co_u32 v30, vcc_lo, v92, v48
	v_add_co_ci_u32_e32 v31, vcc_lo, v93, v49, vcc_lo
	global_load_b64 v[36:37], v[56:57], off offset:2464
	global_load_b64 v[44:45], v[44:45], off
	global_load_b64 v[46:47], v[46:47], off
	global_load_b64 v[30:31], v[30:31], off
	v_fma_f64 v[2:3], v[2:3], v[26:27], -v[40:41]
	v_add_nc_u32_e32 v40, 2, v79
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, 0x9a0, v40, 0
	s_waitcnt vmcnt(6)
	v_mul_f64 v[76:77], v[76:77], v[32:33]
	v_mul_f64 v[32:33], v[32:33], v[34:35]
	v_add_nc_u32_e32 v34, 1, v79
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[26:27], null, 0x9a0, v34, 0
	v_mad_i64_i32 v[34:35], null, 0x9a0, v88, 0
	v_add_co_u32 v41, vcc_lo, v84, v26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v42, vcc_lo, v85, v27, vcc_lo
	v_add_co_u32 v43, vcc_lo, v94, v26
	v_add_co_ci_u32_e32 v88, vcc_lo, v95, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, v86, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, v87, v27, vcc_lo
	v_add_co_u32 v40, vcc_lo, v84, v34
	v_add_f64 v[2:3], v[74:75], v[2:3]
	v_add_f64 v[8:9], v[12:13], v[8:9]
	v_add_f64 v[12:13], v[70:71], v[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], s[2:3]
	v_fma_f64 v[2:3], v[14:15], s[6:7], -v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[8:9], s[8:9], v[2:3]
	v_add_f64 v[8:9], v[68:69], v[24:25]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[22:23], v[28:29], v[10:11], -v[76:77]
	v_add_co_ci_u32_e32 v76, vcc_lo, v85, v35, vcc_lo
	s_waitcnt vmcnt(3)
	v_fma_f64 v[10:11], v[10:11], v[36:37], -v[32:33]
	v_add_co_u32 v36, vcc_lo, v94, v34
	v_add_co_ci_u32_e32 v37, vcc_lo, v95, v35, vcc_lo
	v_add_co_u32 v77, vcc_lo, v86, v34
	v_add_co_ci_u32_e32 v89, vcc_lo, v87, v35, vcc_lo
	v_add_co_u32 v26, vcc_lo, v26, v48
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v49, vcc_lo
	v_add_co_u32 v90, vcc_lo, v84, v0
	v_add_co_ci_u32_e32 v91, vcc_lo, v85, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mul_f64 v[28:29], v[44:45], v[46:47]
	v_add_co_u32 v44, vcc_lo, v94, v0
	v_add_co_ci_u32_e32 v45, vcc_lo, v95, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[30:31], v[46:47], v[30:31]
	v_add_co_u32 v46, vcc_lo, v86, v0
	v_add_co_ci_u32_e32 v47, vcc_lo, v87, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v41, v48
	v_add_co_ci_u32_e32 v1, vcc_lo, v42, v49, vcc_lo
	v_add_co_u32 v32, vcc_lo, v43, v48
	v_add_co_ci_u32_e32 v33, vcc_lo, v88, v49, vcc_lo
	v_add_co_u32 v34, vcc_lo, v40, v48
	v_add_co_ci_u32_e32 v35, vcc_lo, v76, v49, vcc_lo
	v_add_co_u32 v36, vcc_lo, v36, v48
	v_add_co_ci_u32_e32 v37, vcc_lo, v37, v49, vcc_lo
	v_add_co_u32 v40, vcc_lo, v77, v48
	v_add_co_ci_u32_e32 v41, vcc_lo, v89, v49, vcc_lo
	v_add_co_u32 v42, vcc_lo, v90, v48
	v_add_co_ci_u32_e32 v43, vcc_lo, v91, v49, vcc_lo
	v_add_co_u32 v44, vcc_lo, v44, v48
	v_add_co_ci_u32_e32 v45, vcc_lo, v45, v49, vcc_lo
	v_add_co_u32 v46, vcc_lo, v46, v48
	v_add_co_ci_u32_e32 v47, vcc_lo, v47, v49, vcc_lo
	global_load_b64 v[26:27], v[26:27], off
	global_load_b64 v[34:35], v[34:35], off
	global_load_b64 v[36:37], v[36:37], off
	global_load_b64 v[40:41], v[40:41], off
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[32:33], v[32:33], off
	global_load_b64 v[42:43], v[42:43], off
	global_load_b64 v[44:45], v[44:45], off
	global_load_b64 v[46:47], v[46:47], off
	v_add_f64 v[10:11], v[22:23], v[10:11]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[34:35], v[34:35], v[36:37]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[36:37], v[36:37], v[40:41]
	v_add_co_u32 v40, vcc_lo, 0xfffff000, v58
	v_add_co_ci_u32_e32 v41, vcc_lo, -1, v59, vcc_lo
	s_waitcnt vmcnt(3)
	v_fma_f64 v[28:29], v[0:1], v[32:33], -v[28:29]
	v_add_co_u32 v0, vcc_lo, 0xfffff000, v38
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v39, vcc_lo
	v_fma_f64 v[26:27], v[32:33], v[26:27], -v[30:31]
	v_add_co_u32 v30, vcc_lo, 0xfffff000, v56
	v_add_co_ci_u32_e32 v31, vcc_lo, -1, v57, vcc_lo
	global_load_b64 v[32:33], v[40:41], off offset:-832
	s_waitcnt vmcnt(2)
	v_fma_f64 v[34:35], v[42:43], v[44:45], -v[34:35]
	global_load_b64 v[42:43], v[0:1], off offset:-832
	s_waitcnt vmcnt(2)
	v_fma_f64 v[36:37], v[44:45], v[46:47], -v[36:37]
	global_load_b64 v[44:45], v[30:31], off offset:-832
	v_add_co_u32 v46, vcc_lo, 0x1000, v58
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v59, vcc_lo
	global_load_b64 v[40:41], v[40:41], off offset:-3296
	global_load_b64 v[0:1], v[0:1], off offset:-3296
	global_load_b64 v[30:31], v[30:31], off offset:-3296
	v_add_f64 v[26:27], v[28:29], v[26:27]
	v_add_f64 v[34:35], v[34:35], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[34:35], v[34:35], s[2:3]
	v_fma_f64 v[26:27], v[26:27], s[6:7], -v[34:35]
	s_waitcnt vmcnt(4)
	v_mul_f64 v[32:33], v[32:33], v[42:43]
	s_waitcnt vmcnt(3)
	v_mul_f64 v[42:43], v[42:43], v[44:45]
	v_add_co_u32 v44, vcc_lo, 0x1000, v38
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v39, vcc_lo
	s_clause 0x1
	global_load_b64 v[76:77], v[46:47], off offset:832
	global_load_b64 v[46:47], v[46:47], off offset:3296
	s_clause 0x1
	global_load_b64 v[88:89], v[44:45], off offset:832
	global_load_b64 v[44:45], v[44:45], off offset:3296
	s_waitcnt vmcnt(5)
	v_mul_f64 v[40:41], v[40:41], v[0:1]
	s_waitcnt vmcnt(4)
	v_mul_f64 v[0:1], v[0:1], v[30:31]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[32:33], v[76:77], v[88:89], -v[32:33]
	v_add_co_u32 v76, vcc_lo, 0x1000, v56
	v_add_co_ci_u32_e32 v77, vcc_lo, 0, v57, vcc_lo
	s_clause 0x1
	global_load_b64 v[90:91], v[76:77], off offset:832
	global_load_b64 v[76:77], v[76:77], off offset:3296
	s_waitcnt vmcnt(2)
	v_fma_f64 v[30:31], v[46:47], v[44:45], -v[40:41]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[42:43], v[88:89], v[90:91], -v[42:43]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[40:41], v[44:45], v[76:77], -v[0:1]
	v_add_co_u32 v0, vcc_lo, 0x2000, v38
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v39, vcc_lo
	v_add_co_u32 v38, vcc_lo, 0xffffe000, v38
	v_add_co_ci_u32_e32 v39, vcc_lo, -1, v39, vcc_lo
	v_add_co_u32 v44, vcc_lo, 0xffffe000, v58
	v_add_co_ci_u32_e32 v45, vcc_lo, -1, v59, vcc_lo
	v_add_co_u32 v46, vcc_lo, 0xffffe000, v56
	v_add_co_ci_u32_e32 v47, vcc_lo, -1, v57, vcc_lo
	global_load_b64 v[44:45], v[44:45], off offset:-1664
	global_load_b64 v[38:39], v[38:39], off offset:-1664
	global_load_b64 v[46:47], v[46:47], off offset:-1664
	v_add_co_u32 v76, vcc_lo, 0x2000, v56
	v_add_co_ci_u32_e32 v77, vcc_lo, 0, v57, vcc_lo
	v_add_nc_u32_e32 v91, -4, v78
	global_load_b64 v[76:77], v[76:77], off offset:1664
	v_add_f64 v[32:33], v[32:33], v[42:43]
	v_add_f64 v[30:31], v[30:31], v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[32:33], s[2:3]
	v_fma_f64 v[10:11], v[10:11], s[6:7], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[10:11], v[30:31], s[8:9], v[10:11]
	s_waitcnt vmcnt(2)
	v_mul_f64 v[44:45], v[44:45], v[38:39]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[38:39], v[38:39], v[46:47]
	v_add_co_u32 v46, vcc_lo, 0x2000, v58
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v59, vcc_lo
	global_load_b64 v[46:47], v[46:47], off offset:1664
	global_load_b64 v[88:89], v[0:1], off offset:1664
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[46:47], v[88:89], -v[44:45]
	v_add_nc_u32_e32 v44, -3, v79
	v_fma_f64 v[38:39], v[88:89], v[76:77], -v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_i64_i32 v[42:43], null, 0x9a0, v44, 0
	v_add_f64 v[44:45], v[64:65], v[66:67]
	v_add_nc_u32_e32 v66, 3, v79
	v_add_co_u32 v18, vcc_lo, v84, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v19, vcc_lo, v85, v43, vcc_lo
	v_add_co_u32 v46, vcc_lo, v94, v42
	v_add_co_ci_u32_e32 v47, vcc_lo, v95, v43, vcc_lo
	v_add_co_u32 v18, vcc_lo, v18, v48
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v19, vcc_lo, v19, v49, vcc_lo
	v_add_co_u32 v64, vcc_lo, v86, v42
	v_add_co_ci_u32_e32 v65, vcc_lo, v87, v43, vcc_lo
	v_add_co_u32 v42, vcc_lo, v46, v48
	v_add_co_ci_u32_e32 v43, vcc_lo, v47, v49, vcc_lo
	v_mad_u64_u32 v[46:47], null, 0x9a0, v66, 0
	v_add_co_u32 v32, vcc_lo, v64, v48
	v_add_co_ci_u32_e32 v33, vcc_lo, v65, v49, vcc_lo
	v_add_nc_u32_e32 v66, -4, v79
	v_add_f64 v[0:1], v[0:1], v[38:39]
	v_add_co_u32 v62, vcc_lo, v84, v46
	v_add_co_ci_u32_e32 v63, vcc_lo, v85, v47, vcc_lo
	v_add_co_u32 v64, vcc_lo, v94, v46
	v_add_co_ci_u32_e32 v65, vcc_lo, v95, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v62, vcc_lo, v62, v48
	v_add_co_ci_u32_e32 v63, vcc_lo, v63, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v64, vcc_lo, v64, v48
	v_add_co_ci_u32_e32 v65, vcc_lo, v65, v49, vcc_lo
	v_add_co_u32 v67, vcc_lo, v86, v46
	v_add_co_ci_u32_e32 v74, vcc_lo, v87, v47, vcc_lo
	v_mad_i64_i32 v[46:47], null, 0x9a0, v66, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v66, vcc_lo, v67, v48
	v_add_co_ci_u32_e32 v67, vcc_lo, v74, v49, vcc_lo
	v_mul_f64 v[44:45], v[44:45], s[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v74, vcc_lo, v84, v46
	v_add_co_ci_u32_e32 v75, vcc_lo, v85, v47, vcc_lo
	v_add_co_u32 v22, vcc_lo, v74, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v23, vcc_lo, v75, v49, vcc_lo
	v_add_co_u32 v74, vcc_lo, v94, v46
	v_add_co_ci_u32_e32 v75, vcc_lo, v95, v47, vcc_lo
	v_add_co_u32 v76, vcc_lo, v86, v46
	v_add_co_ci_u32_e32 v77, vcc_lo, v87, v47, vcc_lo
	v_add_co_u32 v46, vcc_lo, v74, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v47, vcc_lo, v75, v49, vcc_lo
	v_add_co_u32 v74, vcc_lo, v76, v48
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v75, vcc_lo, v77, v49, vcc_lo
	global_load_b64 v[18:19], v[18:19], off
	global_load_b64 v[42:43], v[42:43], off
	global_load_b64 v[32:33], v[32:33], off
	global_load_b64 v[62:63], v[62:63], off
	global_load_b64 v[64:65], v[64:65], off
	global_load_b64 v[66:67], v[66:67], off
	global_load_b64 v[22:23], v[22:23], off
	global_load_b64 v[46:47], v[46:47], off
	global_load_b64 v[74:75], v[74:75], off
	v_add_nc_u32_e32 v76, 4, v79
	v_fma_f64 v[14:15], v[60:61], s[6:7], -v[44:45]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[6:7], v[12:13], s[8:9], v[14:15]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[18:19], v[18:19], v[42:43]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[32:33], v[42:43], v[32:33]
	v_mad_u64_u32 v[42:43], null, 0x9a0, v76, 0
	s_waitcnt vmcnt(1)
	v_mul_f64 v[22:23], v[22:23], v[46:47]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[46:47], v[46:47], v[74:75]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v76, vcc_lo, v84, v42
	v_add_co_ci_u32_e32 v77, vcc_lo, v85, v43, vcc_lo
	v_add_co_u32 v79, vcc_lo, v94, v42
	v_add_co_ci_u32_e32 v85, vcc_lo, v95, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v76, vcc_lo, v76, v48
	v_add_co_ci_u32_e32 v77, vcc_lo, v77, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v84, vcc_lo, v79, v48
	v_add_co_ci_u32_e32 v85, vcc_lo, v85, v49, vcc_lo
	v_add_co_u32 v86, vcc_lo, v86, v42
	v_add_co_ci_u32_e32 v87, vcc_lo, v87, v43, vcc_lo
	global_load_b64 v[42:43], v[84:85], off
	v_add_co_u32 v84, vcc_lo, v86, v48
	v_add_co_ci_u32_e32 v85, vcc_lo, v87, v49, vcc_lo
	global_load_b64 v[76:77], v[76:77], off
	v_add_nc_u32_e32 v79, -1, v78
	global_load_b64 v[84:85], v[84:85], off
	v_fma_f64 v[18:19], v[62:63], v[64:65], -v[18:19]
	v_fma_f64 v[32:33], v[64:65], v[66:67], -v[32:33]
	v_mad_i64_i32 v[86:87], null, 0xb9480, v79, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v79, vcc_lo, v86, v50
	v_add_co_ci_u32_e32 v87, vcc_lo, v87, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v86, vcc_lo, v79, v48
	v_add_nc_u32_e32 v79, -2, v78
	v_add_co_ci_u32_e32 v87, vcc_lo, v87, v49, vcc_lo
	v_add_co_u32 v62, vcc_lo, 0xfff47000, v58
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_i64_i32 v[64:65], null, 0xb9480, v79, s[12:13]
	v_add_co_ci_u32_e32 v63, vcc_lo, -1, v59, vcc_lo
	v_add_co_u32 v66, vcc_lo, 0xfff47000, v56
	v_add_co_ci_u32_e32 v67, vcc_lo, -1, v57, vcc_lo
	global_load_b64 v[28:29], v[62:63], off offset:-1152
	global_load_b64 v[62:63], v[86:87], off
	global_load_b64 v[66:67], v[66:67], off offset:-1152
	v_add_co_u32 v79, vcc_lo, v64, v50
	v_add_co_ci_u32_e32 v87, vcc_lo, v65, v51, vcc_lo
	v_add_co_u32 v64, vcc_lo, 0xffe8e000, v58
	v_add_co_ci_u32_e32 v65, vcc_lo, -1, v59, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v86, vcc_lo, v79, v48
	v_add_co_ci_u32_e32 v87, vcc_lo, v87, v49, vcc_lo
	v_add_co_u32 v74, vcc_lo, 0xffe8e000, v56
	v_add_co_ci_u32_e32 v75, vcc_lo, -1, v57, vcc_lo
	global_load_b64 v[64:65], v[64:65], off offset:-2304
	global_load_b64 v[86:87], v[86:87], off
	global_load_b64 v[74:75], v[74:75], off offset:-2304
	v_add_nc_u32_e32 v79, 2, v78
	v_add_f64 v[18:19], v[18:19], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[36:37], null, 0xb9480, v79, s[12:13]
	v_add_co_u32 v79, vcc_lo, v36, v50
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v88, vcc_lo, v37, v51, vcc_lo
	v_add_co_u32 v36, vcc_lo, 0x172000, v58
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v59, vcc_lo
	v_fma_f64 v[18:19], v[18:19], s[8:9], v[26:27]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[22:23], v[76:77], v[42:43], -v[22:23]
	v_add_co_u32 v76, vcc_lo, s12, v52
	v_add_co_ci_u32_e32 v77, vcc_lo, s13, v53, vcc_lo
	s_waitcnt vmcnt(6)
	v_fma_f64 v[42:43], v[42:43], v[84:85], -v[46:47]
	v_add_co_u32 v46, vcc_lo, v79, v48
	v_add_co_ci_u32_e32 v47, vcc_lo, v88, v49, vcc_lo
	global_load_b64 v[36:37], v[36:37], off offset:2304
	global_load_b64 v[46:47], v[46:47], off
	v_add_co_u32 v79, vcc_lo, v76, v50
	v_add_co_ci_u32_e32 v84, vcc_lo, v77, v51, vcc_lo
	v_add_co_u32 v76, vcc_lo, v80, v48
	v_add_co_ci_u32_e32 v77, vcc_lo, v81, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v79, vcc_lo, v79, v48
	v_add_co_ci_u32_e32 v80, vcc_lo, v84, v49, vcc_lo
	v_add_co_u32 v81, vcc_lo, v82, v48
	v_add_co_ci_u32_e32 v82, vcc_lo, v83, v49, vcc_lo
	v_add_co_u32 v83, vcc_lo, s12, v54
	v_add_co_ci_u32_e32 v84, vcc_lo, s13, v55, vcc_lo
	global_load_b64 v[81:82], v[81:82], off
	s_waitcnt vmcnt(7)
	v_mul_f64 v[28:29], v[28:29], v[62:63]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[62:63], v[62:63], v[66:67]
	v_add_co_u32 v66, vcc_lo, 0x172000, v56
	v_add_co_ci_u32_e32 v67, vcc_lo, 0, v57, vcc_lo
	v_add_co_u32 v83, vcc_lo, v83, v50
	v_add_co_ci_u32_e32 v84, vcc_lo, v84, v51, vcc_lo
	global_load_b64 v[66:67], v[66:67], off offset:2304
	global_load_b64 v[76:77], v[76:77], off
	global_load_b64 v[79:80], v[79:80], off
	v_add_co_u32 v83, vcc_lo, v83, v48
	v_add_co_ci_u32_e32 v84, vcc_lo, v84, v49, vcc_lo
	v_add_f64 v[22:23], v[22:23], v[42:43]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[64:65], v[64:65], v[86:87]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[74:75], v[86:87], v[74:75]
	global_load_b64 v[85:86], v[83:84], off
	v_add_nc_u32_e32 v87, 3, v78
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, 0xb9480, v87, s[12:13]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[40:41], v[36:37], v[46:47]
	v_fma_f64 v[36:37], v[36:37], v[46:47], -v[64:65]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[32:33], v[46:47], v[66:67], -v[74:75]
	v_mul_f64 v[46:47], v[46:47], v[66:67]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[76:77], v[76:77], v[79:80], -v[28:29]
	v_fma_f64 v[79:80], v[79:80], v[81:82], -v[62:63]
	v_add_co_u32 v82, vcc_lo, v34, v50
	v_add_nc_u32_e32 v81, -3, v78
	v_add_co_ci_u32_e32 v87, vcc_lo, v35, v51, vcc_lo
	v_add_nc_u32_e32 v78, 4, v78
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_i64_i32 v[34:35], null, 0xb9480, v81, s[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[20:21], -v[20:21], v[85:86], v[40:41]
	v_add_co_u32 v40, vcc_lo, 0x22b000, v58
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v59, vcc_lo
	v_add_co_u32 v81, vcc_lo, v82, v48
	v_add_co_ci_u32_e32 v82, vcc_lo, v87, v49, vcc_lo
	v_add_co_u32 v87, vcc_lo, 0x22b000, v56
	v_add_co_ci_u32_e32 v88, vcc_lo, 0, v57, vcc_lo
	global_load_b64 v[40:41], v[40:41], off offset:3456
	global_load_b64 v[66:67], v[81:82], off
	global_load_b64 v[81:82], v[87:88], off offset:3456
	v_add_co_u32 v87, vcc_lo, v34, v50
	v_add_co_ci_u32_e32 v88, vcc_lo, v35, v51, vcc_lo
	v_add_co_u32 v34, vcc_lo, 0xffdd5000, v58
	v_add_co_ci_u32_e32 v35, vcc_lo, -1, v59, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v87, vcc_lo, v87, v48
	v_add_co_ci_u32_e32 v88, vcc_lo, v88, v49, vcc_lo
	v_add_f64 v[32:33], v[36:37], v[32:33]
	v_add_co_u32 v36, vcc_lo, 0xffdd5000, v56
	v_add_co_ci_u32_e32 v37, vcc_lo, -1, v57, vcc_lo
	global_load_b64 v[34:35], v[34:35], off offset:-3456
	global_load_b64 v[87:88], v[87:88], off
	global_load_b64 v[36:37], v[36:37], off offset:-3456
	v_fma_f64 v[16:17], -v[85:86], v[16:17], v[46:47]
	v_add_f64 v[26:27], v[76:77], v[79:80]
	v_mul_f64 v[30:31], v[32:33], s[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[20:21], v[16:17]
	v_fma_f64 v[12:13], v[26:27], s[6:7], -v[30:31]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[28:29], v[40:41], v[66:67], -v[28:29]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[62:63], v[66:67], v[81:82], -v[62:63]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[34:35], v[34:35], v[87:88]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[36:37], v[87:88], v[36:37]
	v_add_co_u32 v87, vcc_lo, 0x2e5000, v58
	v_add_co_ci_u32_e32 v88, vcc_lo, 0, v59, vcc_lo
	v_add_co_u32 v46, vcc_lo, 0xffd1b000, v58
	v_add_co_ci_u32_e32 v47, vcc_lo, -1, v59, vcc_lo
	v_add_co_u32 v85, vcc_lo, 0x2e5000, v56
	v_add_co_ci_u32_e32 v86, vcc_lo, 0, v57, vcc_lo
	v_add_co_u32 v89, vcc_lo, 0xffd1b000, v56
	v_add_co_ci_u32_e32 v90, vcc_lo, -1, v57, vcc_lo
	v_add_co_u32 v58, vcc_lo, 0x39e000, v58
	v_add_co_ci_u32_e32 v59, vcc_lo, 0, v59, vcc_lo
	v_add_f64 v[28:29], v[28:29], v[62:63]
	v_add_co_u32 v62, vcc_lo, 0x39e000, v83
	v_add_co_ci_u32_e32 v63, vcc_lo, 0, v84, vcc_lo
	v_mad_i64_i32 v[83:84], null, 0xb9480, v91, s[12:13]
	v_add_co_u32 v56, vcc_lo, 0x39e000, v56
	v_add_co_ci_u32_e32 v57, vcc_lo, 0, v57, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v91, vcc_lo, v83, v50
	v_add_co_ci_u32_e32 v92, vcc_lo, v84, v51, vcc_lo
	v_mad_u64_u32 v[83:84], null, 0xb9480, v78, s[12:13]
	v_fma_f64 v[32:33], v[40:41], v[66:67], -v[34:35]
	v_fma_f64 v[38:39], v[66:67], v[81:82], -v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v78, vcc_lo, v83, v50
	v_add_co_ci_u32_e32 v93, vcc_lo, v84, v51, vcc_lo
	v_add_co_u32 v83, vcc_lo, v91, v48
	v_add_co_ci_u32_e32 v84, vcc_lo, v92, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v91, vcc_lo, v78, v48
	v_add_co_ci_u32_e32 v92, vcc_lo, v93, v49, vcc_lo
	global_load_b64 v[46:47], v[46:47], off offset:-512
	global_load_b64 v[83:84], v[83:84], off
	global_load_b64 v[89:90], v[89:90], off offset:-512
	global_load_b64 v[87:88], v[87:88], off offset:512
	global_load_b64 v[91:92], v[91:92], off
	global_load_b64 v[85:86], v[85:86], off offset:512
	global_load_b64 v[58:59], v[58:59], off offset:1664
	global_load_b64 v[62:63], v[62:63], off offset:1664
	global_load_b64 v[56:57], v[56:57], off offset:1664
	v_mul_f64 v[20:21], v[28:29], s[2:3]
	s_mov_b32 s2, 0x3126e979
	s_mov_b32 s3, 0xbf6cac08
	s_delay_alu instid0(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[2:3], v[10:11]
	v_fma_f64 v[10:11], v[22:23], s[2:3], v[18:19]
	v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
	v_fma_f64 v[4:5], v[8:9], s[2:3], v[6:7]
	v_add_f64 v[14:15], v[32:33], v[38:39]
	v_fma_f64 v[16:17], v[16:17], s[6:7], -v[20:21]
	v_mul_f64 v[0:1], v[0:1], s[18:19]
	v_mul_f64 v[6:7], v[10:11], s[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[14:15], s[8:9], v[12:13]
	v_fma_f64 v[0:1], v[2:3], s[16:17], -v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[2:3], v[4:5], s[16:17], -v[6:7]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[40:41], v[46:47], v[83:84]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[42:43], v[83:84], v[89:90]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[28:29], v[87:88], v[91:92], -v[64:65]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[44:45], v[91:92], v[85:86], -v[74:75]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[24:25], v[58:59], v[62:63], -v[34:35]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[26:27], v[62:63], v[56:57], -v[36:37]
	v_fma_f64 v[18:19], v[87:88], v[91:92], -v[40:41]
	v_fma_f64 v[22:23], v[91:92], v[85:86], -v[42:43]
	v_add_f64 v[20:21], v[28:29], v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[24:25], v[26:27]
	v_add_f64 v[10:11], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[20:21], s[8:9], v[16:17]
	v_fma_f64 v[4:5], v[10:11], s[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[14:15], s[2:3], v[12:13]
	v_fma_f64 v[0:1], -v[4:5], s[0:1], v[0:1]
	v_add_co_u32 v4, vcc_lo, s4, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f64 v[2:3], -v[6:7], s[0:1], v[2:3]
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v55, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v52
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v53, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v50
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v50
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, v4, v48
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v48
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v49, vcc_lo
	s_clause 0x1
	global_store_b64 v[4:5], v[0:1], off
	global_store_b64 v[6:7], v[2:3], off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9hypterm_2PdS_S_S_S_S_dddiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 98
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9hypterm_2PdS_S_S_S_S_dddiii, .Lfunc_end2-_Z9hypterm_2PdS_S_S_S_S_dddiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4988
; NumSgprs: 22
; NumVgprs: 98
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 98
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  write_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9hypterm_0PdS_S_S_S_S_S_S_S_S_S_dddiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     103
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z9hypterm_1PdS_S_S_S_S_S_S_S_S_S_dddiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     166
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  write_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9hypterm_2PdS_S_S_S_S_dddiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z9hypterm_2PdS_S_S_S_S_dddiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     98
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
