#include<stdio.h>
#include<stdlib.h>
#include<time.h>

# define FILL_PERCENT 10
# define SIZE 250
# define BLOCK_SIZE 32


__global__ void spmvNormal( int *M, int *V, int *res){
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int temp,i;
    if (idx < SIZE) {
    	temp = 0;
        //dot product for one row
        for (i = 0; i < SIZE; i++){
            temp += M[idx * SIZE + i] * V[i];
        }
         res[idx] = temp;
    } 
}

__global__ void spmvCSR(int *ro, int *ci, int *val, int *V, int *res_csr){
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i;
	int start, end;
	int dot;
	if(idx < SIZE){
		dot = 0;
		start = ro[idx];
		end = ro[idx + 1];
		for(i = start; i < end; i++){
			dot+= val[i] * V[ci[i]];
		}
	}
	res_csr[idx] = dot;
}



__global__ void spmvECSR(int *ro, int *dd,int *val, int *V, int* res_ecsr){
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i,j;
	int start, end;
	int dot;
	if(idx < SIZE){
		start = ro[idx];
		end = ro[idx + 1];
		j=0;
		for(i = 0;i<=start;i++)
			j += dd[i];
		dot = val[start] * V[j];
		for(i = start+1; i < end; i++){
			dot += val[i] * V[j+dd[i]];
		}
	}
	res_ecsr[idx] = dot;
}


__global__ void spmvECSR_mod(int *ro, int *dd, int *val, int *V, int *res_ecsr){
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i,j;
	int start, end;
	int dot;
	if(idx < SIZE){
		start = ro[idx];
		end = ro[idx + 1];
		j = dd[start];
		dot = val[start] * V[j];
		for(i = start+1; i < end; i++){
			dot+= val[i] * V[j+dd[i]];
		}
	}
	res_ecsr[idx] = dot;
}

int **M,*V;
int *ro,*ci,*val,*dd;
int *ro_gpu,*ci_gpu,*val_gpu,*dd_gpu,*V_gpu,*M_gpu;
int *res_csr,*res_ecsr,*res,*res_ecsr_mod;
int *res_csr_gpu, *res_ecsr_gpu,*res_gpu,*res_ecsr_mod_gpu;

int main(){
	//cudaDeviceSetCacheConfig(cudaFuncCachePreferL1);

	//variable declarations
	int i,j;
	cudaEvent_t start,stop,start_csr,stop_csr,start_ecsr,stop_ecsr,start_ecsr_mod,stop_ecsr_mod;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventCreate(&start_csr);
	cudaEventCreate(&stop_csr);
	cudaEventCreate(&start_ecsr);
	cudaEventCreate(&stop_ecsr);
	cudaEventCreate(&start_ecsr_mod);
	cudaEventCreate(&stop_ecsr_mod);
	
	float time_csr=0,time_ecsr=0,time_normal=0,time_ecsr_mod=0;

	// Define CudaError
	cudaError_t err;
	
	//initiallizing result vectors
	res = (int *)malloc(SIZE*sizeof(int));
	res_csr = (int * )malloc(SIZE * sizeof(int));
	res_ecsr = (int *)malloc(SIZE * sizeof(int));
	res_ecsr_mod = (int *)malloc(SIZE * sizeof(int));

	//allocating SpMV
	printf("Generating Sparse Matrix ...");
	M = (int **)malloc(SIZE * sizeof(int *));
	for(i=0;i<SIZE;i++)
		M[i] = (int *)malloc(SIZE * sizeof(int));

	for(i=0;i<SIZE;i++)
		for(j=0;j<SIZE;j++)
			M[i][j] = 0;

	int non_zero_ct = (int)(FILL_PERCENT * SIZE/100);
	// printf("%d\n",non_zero_ct);
	// int non_zero_ct = 2;
	for(i=0;i<non_zero_ct;i++){
		long long n = (long long)((rand() % 100) * SIZE* SIZE)/100;
		long c = n % SIZE;
		long r = (int)(n / SIZE);
		M[r][c] = (rand() % 100) + 1;
	}

	printf("Done\n");

	printf("Generating Dense Vector...");
	V = (int *)malloc(SIZE * sizeof(int));
	for(i=0;i<SIZE;i++)
		V[i] = (rand() % 100) + 1;

	printf("Done\n");


	//Building CSR and ECSR rep of SpM
	printf("Building CSR vectors and Distance Difference vector...");
	int cct = 0;
	int prev = 0;
	ro = (int *)malloc((SIZE + 1)*sizeof(int));
	ci = (int *)malloc(non_zero_ct *2* sizeof(int));
	val = (int *)malloc(non_zero_ct *2* sizeof(int));
	ro[0] = 0;



	dd = (int *)malloc(non_zero_ct * 2 * sizeof(int)/2);

	/*for(i=0;i<SIZE;i++)
		for(j=0;j<SIZE;j++)
			printf("%d ",M[i][j]);
		printf("\n");*/
	for(i=0;i<SIZE;i++){
		int flag = 0;
		for(j=0;j<SIZE;j++){
			//printf("%d ",M[i][j]);
			if(M[i][j]!=0){					
				while(j-prev>255){
					printf("abc ");
					ci[cct] = prev + 255;
					val[cct] = 0;
					dd[cct] = 255;
					prev = prev + 255;
					cct++;
				}

				ci[cct] = j;
				val[cct] = M[i][j];
				if(flag==0){
					dd[cct] = j;
					flag++;
				}
				else
					dd[cct] = j - prev;
				prev = j;
				cct++;

			}
		}
		//printf("\n");
		ro[i+1] = cct;
	}
	printf("Done\n");

	// for(i=0;i<ro[SIZE];i++){
	// 	printf("%d %d\n",ci[i],val[i]);
	// }
	//Setup memory on GPU
	cudaMalloc((void **)&M_gpu,(SIZE * sizeof(int))*(SIZE));
	cudaMalloc((void **)&ro_gpu, (SIZE + 1)*sizeof(int));
	cudaMalloc((void **)&ci_gpu, (non_zero_ct * 2 * sizeof(int)));
	cudaMalloc((void **)&val_gpu, (non_zero_ct * 2 * sizeof(int)));
	cudaMalloc((void **)&dd_gpu, (non_zero_ct * 2 * sizeof(int))/2);
	cudaMalloc((void **)&V_gpu, (SIZE * sizeof(int)));
	cudaMalloc((void **)&res_gpu, (SIZE * sizeof(int)));
	cudaMalloc((void **)&res_csr_gpu, (SIZE * sizeof(int)));
	cudaMalloc((void **)&res_ecsr_gpu, (SIZE * sizeof(int)));
	cudaMalloc((void **)&res_ecsr_mod_gpu, (SIZE * sizeof(int)));

	//printf("Done cuda malloc\n");

	//transfer to device
	cudaMemcpy(M_gpu, M, (SIZE * SIZE * sizeof(int)), cudaMemcpyHostToDevice);
	cudaMemcpy(ro_gpu, ro, (SIZE +1)*sizeof(int),cudaMemcpyHostToDevice);
	cudaMemcpy(ci_gpu, ci , (non_zero_ct * 2 * sizeof(int)), cudaMemcpyHostToDevice);
	cudaMemcpy(val_gpu, val, (non_zero_ct * 2 * sizeof(int)),cudaMemcpyHostToDevice);
	cudaMemcpy(dd_gpu, dd, (non_zero_ct * 2 * sizeof(int)/2), cudaMemcpyHostToDevice);
	cudaMemcpy(V_gpu, V, (SIZE * sizeof(int)), cudaMemcpyHostToDevice);

	//printf("Done transferring to device\n");

	//setting CUDA parameters
	int nb = ceil(SIZE/BLOCK_SIZE);
	int nt = BLOCK_SIZE;
	// dim3 GridDim,BlockDim;
	// BlockDim.x = nb;
	// BlockDim.y=1;
	// GridDim.x = BLOCK_SIZE;
	// GridDim.y = BLOCK_SIZE;

	//Starting Normal Multiplication
	printf("\n\nStarting Normal Multiplication...");
	//clock_t start,end;
	//start = clock();

	cudaEventRecord(start);
	spmvNormal<<< nb,nt >>>(M_gpu,V_gpu,res_gpu);
	cudaEventRecord(stop);
	cudaEventSynchronize(stop);
	//end = clock();
	//time_normal += end - start;
	cudaEventElapsedTime(&time_normal, start, stop);

	//Checking for CUDA errors
	err = cudaGetLastError();
	if(err!=cudaSuccess){
		printf("ERROR: %s\n",cudaGetErrorString(err));
	}
	printf("Done\n");

	//Transfer result back to memory
	cudaMemcpy(res, res_gpu, (SIZE * sizeof(int)), cudaMemcpyDeviceToHost);
		



	//Starting CSR Multiplication
	printf("\n\nStarting CSR Multiplication...");
	// clock_t start_csr,end_csr;
	// start_csr = clock();

	cudaEventRecord(start_csr);
	spmvCSR<<< nb,nt>>>(ro_gpu,dd_gpu,val_gpu,V_gpu,res_csr_gpu);
	cudaEventRecord(stop_csr);
	cudaEventSynchronize(stop_csr);
	cudaEventElapsedTime(&time_csr,start_csr,stop_csr);
	//end_csr = clock();
	// time_csr += end_csr - start_csr;

	//Checking for CUDA errors
	err = cudaGetLastError();
	if(err!=cudaSuccess){
		printf("ERROR: %s\n",cudaGetErrorString(err));
		exit(0);
	}
	printf("Done\n");

	//Transfer result back to memory
	cudaMemcpy(res_csr, res_csr_gpu, (SIZE * sizeof(int)), cudaMemcpyDeviceToHost);





	//Starting ECSR Multiplication
	printf("\n\nStarting ECSR Multiplication...");
	// clock_t start_ecsr,end_ecsr;
	// start_ecsr = clock();

	cudaEventRecord(start_ecsr);
	spmvECSR<<< nb,nt>>>(ro_gpu,dd_gpu,val_gpu,V_gpu,res_ecsr_gpu);
	cudaEventRecord(stop_ecsr);
	cudaEventSynchronize(stop_ecsr);
	cudaEventElapsedTime(&time_ecsr, start_ecsr,stop_ecsr);
	// end_ecsr = clock();
	// time_ecsr += end_ecsr - start_ecsr;

	//Checking for CUDA errors
	err = cudaGetLastError();
	if(err!=cudaSuccess){
		printf("ERROR: %s\n",cudaGetErrorString(err));
		exit(0);
	}
	printf("Done\n");

	//Transfer result back to memory
	cudaMemcpy(res_ecsr, res_ecsr_gpu, (SIZE * sizeof(int)), cudaMemcpyDeviceToHost);		



	printf("\n\nStarting ECSR(modified) Multiplication...");
	// clock_t start_ecsr,end_ecsr;
	// start_ecsr = clock();

	cudaEventRecord(start_ecsr_mod);
	spmvECSR_mod<<< nb,nt>>>(ro_gpu,dd_gpu,val_gpu,V_gpu,res_ecsr_mod_gpu);
	cudaEventRecord(stop_ecsr_mod);
	cudaEventSynchronize(stop_ecsr_mod);
	cudaEventElapsedTime(&time_ecsr_mod, start_ecsr_mod,stop_ecsr_mod);
	// end_ecsr = clock();
	// time_ecsr += end_ecsr - start_ecsr;

	//Checking for CUDA errors
	err = cudaGetLastError();
	if(err!=cudaSuccess){
		printf("ERROR: %s\n",cudaGetErrorString(err));
		exit(0);
	}
	printf("Done\n\n");

	//Transfer result back to memory
	cudaMemcpy(res_ecsr_mod, res_ecsr_mod_gpu, (SIZE * sizeof(int)), cudaMemcpyDeviceToHost);	


	//free memory
	for(i=0;i<SIZE;i++)
		free(M[i]);

	free(M);
	free(V);
	free(ro);
	free(ci);
	free(val);
	free(dd);
	free(res);
	free(res_csr);
	free(res_ecsr);
	cudaFree(ro_gpu);
	cudaFree(ci_gpu);
	cudaFree(val_gpu);	
	cudaFree(dd_gpu);
	cudaFree(M_gpu);
	cudaFree(V_gpu);
	cudaFree(res_gpu);
	cudaFree(res_csr_gpu);
	cudaFree(res_ecsr_gpu);
	printf("===============================================================================\n");

	printf("Average time taken for normal multiplication:%lf\n",time_normal);
	printf("---------------------------------------------------------------\n");
	printf("Average time taken for CSR multiplication:%lf\n",time_csr);
	printf("CSR multiplication runs %lf times faster than normal multiplication\n",time_normal/time_csr);
	printf("---------------------------------------------------------------\n");
	printf("Average time taken for ECSR multiplication:%lf\n",time_ecsr);
	printf("ECSR multiplication runs %lf times faster than normal multiplication\n",time_normal/time_ecsr);
	printf("---------------------------------------------------------------\n");
	printf("Average time taken for ECSR(modified) multiplication:%lf\n",time_ecsr_mod);
	printf("ECSR(modfied) multiplication runs %lf times faster than normal multiplication\n",time_normal/time_ecsr_mod);
	printf("---------------------------------------------------------------\n");
	printf("It is seen that time taken for ECSR multiplication is %lf times that for ECSR(modified) multiplication\n",time_ecsr/time_ecsr_mod);

	return 0;
}

	.file	"tmpxft_00287194_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_
	.type	_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_, @function
_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10spmvNormalPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_, .-_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_
	.globl	_Z10spmvNormalPiS_S_
	.type	_Z10spmvNormalPiS_S_, @function
_Z10spmvNormalPiS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_
	.cfi_endproc
.LFE2054:
	.size	_Z10spmvNormalPiS_S_, .-_Z10spmvNormalPiS_S_
	.globl	_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_
	.type	_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_, @function
_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7spmvCSRPiS_S_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_, .-_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_
	.globl	_Z7spmvCSRPiS_S_S_S_
	.type	_Z7spmvCSRPiS_S_S_S_, @function
_Z7spmvCSRPiS_S_S_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_
	.cfi_endproc
.LFE2056:
	.size	_Z7spmvCSRPiS_S_S_S_, .-_Z7spmvCSRPiS_S_S_S_
	.globl	_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_
	.type	_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_, @function
_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z8spmvECSRPiS_S_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L13:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_, .-_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_
	.globl	_Z8spmvECSRPiS_S_S_S_
	.type	_Z8spmvECSRPiS_S_S_S_, @function
_Z8spmvECSRPiS_S_S_S_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_
	.cfi_endproc
.LFE2058:
	.size	_Z8spmvECSRPiS_S_S_S_, .-_Z8spmvECSRPiS_S_S_S_
	.globl	_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_
	.type	_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_, @function
_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z12spmvECSR_modPiS_S_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L18:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_, .-_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_
	.globl	_Z12spmvECSR_modPiS_S_S_S_
	.type	_Z12spmvECSR_modPiS_S_S_S_, @function
_Z12spmvECSR_modPiS_S_S_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_
	.cfi_endproc
.LFE2060:
	.size	_Z12spmvECSR_modPiS_S_S_S_, .-_Z12spmvECSR_modPiS_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Generating Sparse Matrix ..."
.LC2:
	.string	"Done\n"
.LC3:
	.string	"Generating Dense Vector..."
.LC4:
	.string	"Building CSR vectors and Distance Difference vector..."
.LC5:
	.string	"abc "
.LC6:
	.string	"\n\nStarting Normal Multiplication..."
.LC7:
	.string	"ERROR: %s\n"
.LC8:
	.string	"\n\nStarting CSR Multiplication..."
.LC9:
	.string	"\n\nStarting ECSR Multiplication..."
.LC10:
	.string	"\n\nStarting ECSR(modified) Multiplication..."
.LC11:
	.string	"Done\n\n"
.LC12:
	.string	"===============================================================================\n"
.LC13:
	.string	"Average time taken for normal multiplication:%lf\n"
.LC14:
	.string	"---------------------------------------------------------------\n"
.LC15:
	.string	"Average time taken for CSR multiplication:%lf\n"
.LC16:
	.string	"CSR multiplication runs %lf times faster than normal multiplication\n"
.LC17:
	.string	"Average time taken for ECSR multiplication:%lf\n"
.LC18:
	.string	"ECSR multiplication runs %lf times faster than normal multiplication\n"
.LC19:
	.string	"Average time taken for ECSR(modified) multiplication:%lf\n"
.LC20:
	.string	"ECSR(modfied) multiplication runs %lf times faster than normal multiplication\n"
.LC21:
	.string	"It is seen that time taken for ECSR multiplication is %lf times that for ECSR(modified) multiplication\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	104(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$1000, %edi
	movl	$0x00000000, 32(%rsp)
	movl	$0x00000000, 36(%rsp)
	movl	$0x00000000, 40(%rsp)
	movl	$0x00000000, 44(%rsp)
	call	malloc@PLT
	movl	$1000, %edi
	movq	%rax, res(%rip)
	call	malloc@PLT
	movl	$1000, %edi
	movq	%rax, res_csr(%rip)
	call	malloc@PLT
	movl	$1000, %edi
	movq	%rax, res_ecsr(%rip)
	call	malloc@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movq	%rax, res_ecsr_mod(%rip)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$2000, %edi
	call	malloc@PLT
	movq	%rax, M(%rip)
	movq	%rax, %rbx
.L24:
	movl	$1000, %edi
	call	malloc@PLT
	movq	%rax, (%rbx,%rbp,8)
	incq	%rbp
	cmpq	$250, %rbp
	jne	.L24
	xorl	%edx, %edx
	xorl	%eax, %eax
.L25:
	movq	(%rbx,%rdx,8), %rdi
	movl	$250, %ecx
	incq	%rdx
	rep stosl
	cmpq	$250, %rdx
	jne	.L25
	movl	$25, %r12d
	movl	$100, %ebp
.L26:
	call	rand@PLT
	cltd
	idivl	%ebp
	imull	$625, %edx, %edx
	movslq	%edx, %rbx
	call	rand@PLT
	movl	$250, %esi
	movl	%eax, %ecx
	movq	%rbx, %rax
	cqto
	idivq	%rsi
	movq	%rax, %rbx
	movq	M(%rip), %rax
	movq	%rdx, %rdi
	movq	(%rax,%rbx,8), %rsi
	movl	%ecx, %eax
	cltd
	idivl	%ebp
	incl	%edx
	movl	%edx, (%rsi,%rdi,4)
	decl	%r12d
	jne	.L26
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1000, %edi
	movl	$100, %ebp
	call	malloc@PLT
	movq	%rax, V(%rip)
.L27:
	call	rand@PLT
	cltd
	idivl	%ebp
	movq	V(%rip), %rax
	incl	%edx
	movl	%edx, (%rax,%rbx)
	addq	$4, %rbx
	cmpq	$1000, %rbx
	jne	.L27
	movl	$2, %edi
	xorl	%eax, %eax
	movl	$4, %r14d
	xorl	%r15d, %r15d
	leaq	.LC2(%rip), %rsi
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1004, %edi
	call	malloc@PLT
	movl	$200, %edi
	movq	%rax, %rbx
	movq	%rax, ro(%rip)
	call	malloc@PLT
	movl	$200, %edi
	movq	%rax, ci(%rip)
	call	malloc@PLT
	xorl	%ecx, %ecx
	movl	$100, %edi
	movl	%ecx, (%rbx)
	movq	%rax, val(%rip)
	call	malloc@PLT
	xorl	%ecx, %ecx
	movq	%rax, dd(%rip)
.L28:
	leaq	(%r14,%r14), %r8
	xorl	%ebp, %ebp
	xorl	%r12d, %r12d
	leaq	-8(%r8), %r13
.L33:
	movq	M(%rip), %rax
	leaq	0(,%rbp,4), %r11
	movq	(%rax,%r13), %rax
	cmpl	$0, (%rax,%rbp,4)
	je	.L29
	movl	%ebp, 24(%rsp)
	movslq	%r15d, %rbx
	salq	$2, %rbx
.L30:
	movl	24(%rsp), %eax
	leaq	4(%rbx), %rdx
	incl	%r15d
	movq	%rdx, 8(%rsp)
	subl	%ecx, %eax
	cmpl	$255, %eax
	jle	.L58
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	%ecx, 28(%rsp)
	movq	%r11, 16(%rsp)
	call	__printf_chk@PLT
	movl	28(%rsp), %ecx
	xorl	%edx, %edx
	movq	16(%rsp), %r11
	movq	ci(%rip), %rax
	addl	$255, %ecx
	movl	%ecx, (%rax,%rbx)
	movq	val(%rip), %rax
	movl	%edx, (%rax,%rbx)
	movq	dd(%rip), %rax
	movl	$255, (%rax,%rbx)
	movq	8(%rsp), %rbx
	jmp	.L30
.L58:
	movq	ci(%rip), %rsi
	movl	%ebp, %ecx
	movl	%ebp, (%rsi,%rbx)
	movq	M(%rip), %rsi
	movq	(%rsi,%r13), %rsi
	movl	(%rsi,%r11), %edi
	movq	val(%rip), %rsi
	movl	%edi, (%rsi,%rbx)
	addq	dd(%rip), %rbx
	testl	%r12d, %r12d
	movl	$1, %r12d
	cmove	%ebp, %eax
	movl	%eax, (%rbx)
.L29:
	incq	%rbp
	cmpq	$250, %rbp
	jne	.L33
	movq	ro(%rip), %rax
	movl	%r15d, (%rax,%r14)
	addq	$4, %r14
	cmpq	$1004, %r14
	jne	.L28
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$250000, %esi
	leaq	M_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1004, %esi
	leaq	ro_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$200, %esi
	leaq	ci_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$200, %esi
	leaq	val_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$100, %esi
	leaq	dd_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1000, %esi
	leaq	V_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1000, %esi
	leaq	res_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1000, %esi
	leaq	res_csr_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1000, %esi
	leaq	res_ecsr_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1000, %esi
	leaq	res_ecsr_mod_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$250000, %edx
	movq	M(%rip), %rsi
	movq	M_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$1004, %edx
	movq	ro(%rip), %rsi
	movq	ro_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$200, %edx
	movq	ci(%rip), %rsi
	movq	ci_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$200, %edx
	movq	val(%rip), %rsi
	movq	val_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$100, %edx
	movq	dd(%rip), %rsi
	movq	dd_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$1000, %edx
	movq	V(%rip), %rsi
	movq	V_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movabsq	$4294967303, %rdi
	movl	$1, %esi
	movq	%rdx, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	res_gpu(%rip), %rdx
	movq	V_gpu(%rip), %rsi
	movq	M_gpu(%rip), %rdi
	call	_Z34__device_stub__Z10spmvNormalPiS_S_PiS_S_
.L35:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L36
	call	cudaGetErrorString@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L36:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$2, %ecx
	movl	$1000, %edx
	movq	res_gpu(%rip), %rsi
	movq	res(%rip), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movabsq	$4294967303, %rdi
	movl	$1, %esi
	movq	%rdx, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	res_csr_gpu(%rip), %r8
	movq	V_gpu(%rip), %rcx
	movq	val_gpu(%rip), %rdx
	movq	dd_gpu(%rip), %rsi
	movq	ro_gpu(%rip), %rdi
	call	_Z34__device_stub__Z7spmvCSRPiS_S_S_S_PiS_S_S_S_
.L37:
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L57
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$2, %ecx
	movl	$1000, %edx
	movq	res_csr_gpu(%rip), %rsi
	movq	res_csr(%rip), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movabsq	$4294967303, %rdi
	movl	$1, %esi
	movq	%rdx, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	res_ecsr_gpu(%rip), %r8
	movq	V_gpu(%rip), %rcx
	movq	val_gpu(%rip), %rdx
	movq	dd_gpu(%rip), %rsi
	movq	ro_gpu(%rip), %rdi
	call	_Z35__device_stub__Z8spmvECSRPiS_S_S_S_PiS_S_S_S_
.L39:
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L57
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$2, %ecx
	movl	$1000, %edx
	movq	res_ecsr_gpu(%rip), %rsi
	movq	res_ecsr(%rip), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movabsq	$4294967303, %rdi
	movl	$1, %esi
	movq	%rdx, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	movq	res_ecsr_mod_gpu(%rip), %r8
	movq	V_gpu(%rip), %rcx
	movq	val_gpu(%rip), %rdx
	movq	dd_gpu(%rip), %rsi
	movq	ro_gpu(%rip), %rdi
	call	_Z40__device_stub__Z12spmvECSR_modPiS_S_S_S_PiS_S_S_S_
.L41:
	movq	104(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	104(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	leaq	44(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L42
.L57:
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L42:
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	movl	$2, %ecx
	movl	$1000, %edx
	movq	res_ecsr_mod_gpu(%rip), %rsi
	movq	res_ecsr_mod(%rip), %rdi
	call	cudaMemcpy@PLT
.L43:
	movq	M(%rip), %rax
	movq	(%rax,%rbx), %rdi
	addq	$8, %rbx
	call	free@PLT
	cmpq	$2000, %rbx
	jne	.L43
	movq	M(%rip), %rdi
	leaq	.LC14(%rip), %rbx
	call	free@PLT
	movq	V(%rip), %rdi
	call	free@PLT
	movq	ro(%rip), %rdi
	call	free@PLT
	movq	ci(%rip), %rdi
	call	free@PLT
	movq	val(%rip), %rdi
	call	free@PLT
	movq	dd(%rip), %rdi
	call	free@PLT
	movq	res(%rip), %rdi
	call	free@PLT
	movq	res_csr(%rip), %rdi
	call	free@PLT
	movq	res_ecsr(%rip), %rdi
	call	free@PLT
	movq	ro_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	ci_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	val_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	dd_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	M_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	V_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	res_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	res_csr_gpu(%rip), %rdi
	call	cudaFree@PLT
	movq	res_ecsr_gpu(%rip), %rdi
	call	cudaFree@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	40(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	32(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC16(%rip), %rsi
	movss	40(%rsp), %xmm0
	divss	32(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC18(%rip), %rsi
	movss	40(%rsp), %xmm0
	divss	36(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	44(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC20(%rip), %rsi
	movss	40(%rsp), %xmm0
	divss	44(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC21(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	36(%rsp), %xmm0
	divss	44(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z12spmvECSR_modPiS_S_S_S_"
.LC23:
	.string	"_Z8spmvECSRPiS_S_S_S_"
.LC24:
	.string	"_Z7spmvCSRPiS_S_S_S_"
.LC25:
	.string	"_Z10spmvNormalPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12spmvECSR_modPiS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8spmvECSRPiS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7spmvCSRPiS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10spmvNormalPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	res_ecsr_mod_gpu
	.bss
	.align 8
	.type	res_ecsr_mod_gpu, @object
	.size	res_ecsr_mod_gpu, 8
res_ecsr_mod_gpu:
	.zero	8
	.globl	res_gpu
	.align 8
	.type	res_gpu, @object
	.size	res_gpu, 8
res_gpu:
	.zero	8
	.globl	res_ecsr_gpu
	.align 8
	.type	res_ecsr_gpu, @object
	.size	res_ecsr_gpu, 8
res_ecsr_gpu:
	.zero	8
	.globl	res_csr_gpu
	.align 8
	.type	res_csr_gpu, @object
	.size	res_csr_gpu, 8
res_csr_gpu:
	.zero	8
	.globl	res_ecsr_mod
	.align 8
	.type	res_ecsr_mod, @object
	.size	res_ecsr_mod, 8
res_ecsr_mod:
	.zero	8
	.globl	res
	.align 8
	.type	res, @object
	.size	res, 8
res:
	.zero	8
	.globl	res_ecsr
	.align 8
	.type	res_ecsr, @object
	.size	res_ecsr, 8
res_ecsr:
	.zero	8
	.globl	res_csr
	.align 8
	.type	res_csr, @object
	.size	res_csr, 8
res_csr:
	.zero	8
	.globl	M_gpu
	.align 8
	.type	M_gpu, @object
	.size	M_gpu, 8
M_gpu:
	.zero	8
	.globl	V_gpu
	.align 8
	.type	V_gpu, @object
	.size	V_gpu, 8
V_gpu:
	.zero	8
	.globl	dd_gpu
	.align 8
	.type	dd_gpu, @object
	.size	dd_gpu, 8
dd_gpu:
	.zero	8
	.globl	val_gpu
	.align 8
	.type	val_gpu, @object
	.size	val_gpu, 8
val_gpu:
	.zero	8
	.globl	ci_gpu
	.align 8
	.type	ci_gpu, @object
	.size	ci_gpu, 8
ci_gpu:
	.zero	8
	.globl	ro_gpu
	.align 8
	.type	ro_gpu, @object
	.size	ro_gpu, 8
ro_gpu:
	.zero	8
	.globl	dd
	.align 8
	.type	dd, @object
	.size	dd, 8
dd:
	.zero	8
	.globl	val
	.align 8
	.type	val, @object
	.size	val, 8
val:
	.zero	8
	.globl	ci
	.align 8
	.type	ci, @object
	.size	ci, 8
ci:
	.zero	8
	.globl	ro
	.align 8
	.type	ro, @object
	.size	ro, 8
ro:
	.zero	8
	.globl	V
	.align 8
	.type	V, @object
	.size	V, 8
V:
	.zero	8
	.globl	M
	.align 8
	.type	M, @object
	.size	M, 8
M:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>

# define FILL_PERCENT 10
# define SIZE 250
# define BLOCK_SIZE 32


__global__ void spmvNormal( int *M, int *V, int *res){
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int temp,i;
    if (idx < SIZE) {
    	temp = 0;
        //dot product for one row
        for (i = 0; i < SIZE; i++){
            temp += M[idx * SIZE + i] * V[i];
        }
         res[idx] = temp;
    } 
}

__global__ void spmvCSR(int *ro, int *ci, int *val, int *V, int *res_csr){
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i;
	int start, end;
	int dot;
	if(idx < SIZE){
		dot = 0;
		start = ro[idx];
		end = ro[idx + 1];
		for(i = start; i < end; i++){
			dot+= val[i] * V[ci[i]];
		}
	}
	res_csr[idx] = dot;
}



__global__ void spmvECSR(int *ro, int *dd,int *val, int *V, int* res_ecsr){
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i,j;
	int start, end;
	int dot;
	if(idx < SIZE){
		start = ro[idx];
		end = ro[idx + 1];
		j=0;
		for(i = 0;i<=start;i++)
			j += dd[i];
		dot = val[start] * V[j];
		for(i = start+1; i < end; i++){
			dot += val[i] * V[j+dd[i]];
		}
	}
	res_ecsr[idx] = dot;
}


__global__ void spmvECSR_mod(int *ro, int *dd, int *val, int *V, int *res_ecsr){
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i,j;
	int start, end;
	int dot;
	if(idx < SIZE){
		start = ro[idx];
		end = ro[idx + 1];
		j = dd[start];
		dot = val[start] * V[j];
		for(i = start+1; i < end; i++){
			dot+= val[i] * V[j+dd[i]];
		}
	}
	res_ecsr[idx] = dot;
}

int **M,*V;
int *ro,*ci,*val,*dd;
int *ro_gpu,*ci_gpu,*val_gpu,*dd_gpu,*V_gpu,*M_gpu;
int *res_csr,*res_ecsr,*res,*res_ecsr_mod;
int *res_csr_gpu, *res_ecsr_gpu,*res_gpu,*res_ecsr_mod_gpu;

int main(){
	//cudaDeviceSetCacheConfig(cudaFuncCachePreferL1);

	//variable declarations
	int i,j;
	hipEvent_t start,stop,start_csr,stop_csr,start_ecsr,stop_ecsr,start_ecsr_mod,stop_ecsr_mod;
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventCreate(&start_csr);
	hipEventCreate(&stop_csr);
	hipEventCreate(&start_ecsr);
	hipEventCreate(&stop_ecsr);
	hipEventCreate(&start_ecsr_mod);
	hipEventCreate(&stop_ecsr_mod);
	
	float time_csr=0,time_ecsr=0,time_normal=0,time_ecsr_mod=0;

	// Define CudaError
	hipError_t err;
	
	//initiallizing result vectors
	res = (int *)malloc(SIZE*sizeof(int));
	res_csr = (int * )malloc(SIZE * sizeof(int));
	res_ecsr = (int *)malloc(SIZE * sizeof(int));
	res_ecsr_mod = (int *)malloc(SIZE * sizeof(int));

	//allocating SpMV
	printf("Generating Sparse Matrix ...");
	M = (int **)malloc(SIZE * sizeof(int *));
	for(i=0;i<SIZE;i++)
		M[i] = (int *)malloc(SIZE * sizeof(int));

	for(i=0;i<SIZE;i++)
		for(j=0;j<SIZE;j++)
			M[i][j] = 0;

	int non_zero_ct = (int)(FILL_PERCENT * SIZE/100);
	// printf("%d\n",non_zero_ct);
	// int non_zero_ct = 2;
	for(i=0;i<non_zero_ct;i++){
		long long n = (long long)((rand() % 100) * SIZE* SIZE)/100;
		long c = n % SIZE;
		long r = (int)(n / SIZE);
		M[r][c] = (rand() % 100) + 1;
	}

	printf("Done\n");

	printf("Generating Dense Vector...");
	V = (int *)malloc(SIZE * sizeof(int));
	for(i=0;i<SIZE;i++)
		V[i] = (rand() % 100) + 1;

	printf("Done\n");


	//Building CSR and ECSR rep of SpM
	printf("Building CSR vectors and Distance Difference vector...");
	int cct = 0;
	int prev = 0;
	ro = (int *)malloc((SIZE + 1)*sizeof(int));
	ci = (int *)malloc(non_zero_ct *2* sizeof(int));
	val = (int *)malloc(non_zero_ct *2* sizeof(int));
	ro[0] = 0;



	dd = (int *)malloc(non_zero_ct * 2 * sizeof(int)/2);

	/*for(i=0;i<SIZE;i++)
		for(j=0;j<SIZE;j++)
			printf("%d ",M[i][j]);
		printf("\n");*/
	for(i=0;i<SIZE;i++){
		int flag = 0;
		for(j=0;j<SIZE;j++){
			//printf("%d ",M[i][j]);
			if(M[i][j]!=0){					
				while(j-prev>255){
					printf("abc ");
					ci[cct] = prev + 255;
					val[cct] = 0;
					dd[cct] = 255;
					prev = prev + 255;
					cct++;
				}

				ci[cct] = j;
				val[cct] = M[i][j];
				if(flag==0){
					dd[cct] = j;
					flag++;
				}
				else
					dd[cct] = j - prev;
				prev = j;
				cct++;

			}
		}
		//printf("\n");
		ro[i+1] = cct;
	}
	printf("Done\n");

	// for(i=0;i<ro[SIZE];i++){
	// 	printf("%d %d\n",ci[i],val[i]);
	// }
	//Setup memory on GPU
	hipMalloc((void **)&M_gpu,(SIZE * sizeof(int))*(SIZE));
	hipMalloc((void **)&ro_gpu, (SIZE + 1)*sizeof(int));
	hipMalloc((void **)&ci_gpu, (non_zero_ct * 2 * sizeof(int)));
	hipMalloc((void **)&val_gpu, (non_zero_ct * 2 * sizeof(int)));
	hipMalloc((void **)&dd_gpu, (non_zero_ct * 2 * sizeof(int))/2);
	hipMalloc((void **)&V_gpu, (SIZE * sizeof(int)));
	hipMalloc((void **)&res_gpu, (SIZE * sizeof(int)));
	hipMalloc((void **)&res_csr_gpu, (SIZE * sizeof(int)));
	hipMalloc((void **)&res_ecsr_gpu, (SIZE * sizeof(int)));
	hipMalloc((void **)&res_ecsr_mod_gpu, (SIZE * sizeof(int)));

	//printf("Done cuda malloc\n");

	//transfer to device
	hipMemcpy(M_gpu, M, (SIZE * SIZE * sizeof(int)), hipMemcpyHostToDevice);
	hipMemcpy(ro_gpu, ro, (SIZE +1)*sizeof(int),hipMemcpyHostToDevice);
	hipMemcpy(ci_gpu, ci , (non_zero_ct * 2 * sizeof(int)), hipMemcpyHostToDevice);
	hipMemcpy(val_gpu, val, (non_zero_ct * 2 * sizeof(int)),hipMemcpyHostToDevice);
	hipMemcpy(dd_gpu, dd, (non_zero_ct * 2 * sizeof(int)/2), hipMemcpyHostToDevice);
	hipMemcpy(V_gpu, V, (SIZE * sizeof(int)), hipMemcpyHostToDevice);

	//printf("Done transferring to device\n");

	//setting CUDA parameters
	int nb = ceil(SIZE/BLOCK_SIZE);
	int nt = BLOCK_SIZE;
	// dim3 GridDim,BlockDim;
	// BlockDim.x = nb;
	// BlockDim.y=1;
	// GridDim.x = BLOCK_SIZE;
	// GridDim.y = BLOCK_SIZE;

	//Starting Normal Multiplication
	printf("\n\nStarting Normal Multiplication...");
	//clock_t start,end;
	//start = clock();

	hipEventRecord(start);
	spmvNormal<<< nb,nt >>>(M_gpu,V_gpu,res_gpu);
	hipEventRecord(stop);
	hipEventSynchronize(stop);
	//end = clock();
	//time_normal += end - start;
	hipEventElapsedTime(&time_normal, start, stop);

	//Checking for CUDA errors
	err = hipGetLastError();
	if(err!=hipSuccess){
		printf("ERROR: %s\n",hipGetErrorString(err));
	}
	printf("Done\n");

	//Transfer result back to memory
	hipMemcpy(res, res_gpu, (SIZE * sizeof(int)), hipMemcpyDeviceToHost);
		



	//Starting CSR Multiplication
	printf("\n\nStarting CSR Multiplication...");
	// clock_t start_csr,end_csr;
	// start_csr = clock();

	hipEventRecord(start_csr);
	spmvCSR<<< nb,nt>>>(ro_gpu,dd_gpu,val_gpu,V_gpu,res_csr_gpu);
	hipEventRecord(stop_csr);
	hipEventSynchronize(stop_csr);
	hipEventElapsedTime(&time_csr,start_csr,stop_csr);
	//end_csr = clock();
	// time_csr += end_csr - start_csr;

	//Checking for CUDA errors
	err = hipGetLastError();
	if(err!=hipSuccess){
		printf("ERROR: %s\n",hipGetErrorString(err));
		exit(0);
	}
	printf("Done\n");

	//Transfer result back to memory
	hipMemcpy(res_csr, res_csr_gpu, (SIZE * sizeof(int)), hipMemcpyDeviceToHost);





	//Starting ECSR Multiplication
	printf("\n\nStarting ECSR Multiplication...");
	// clock_t start_ecsr,end_ecsr;
	// start_ecsr = clock();

	hipEventRecord(start_ecsr);
	spmvECSR<<< nb,nt>>>(ro_gpu,dd_gpu,val_gpu,V_gpu,res_ecsr_gpu);
	hipEventRecord(stop_ecsr);
	hipEventSynchronize(stop_ecsr);
	hipEventElapsedTime(&time_ecsr, start_ecsr,stop_ecsr);
	// end_ecsr = clock();
	// time_ecsr += end_ecsr - start_ecsr;

	//Checking for CUDA errors
	err = hipGetLastError();
	if(err!=hipSuccess){
		printf("ERROR: %s\n",hipGetErrorString(err));
		exit(0);
	}
	printf("Done\n");

	//Transfer result back to memory
	hipMemcpy(res_ecsr, res_ecsr_gpu, (SIZE * sizeof(int)), hipMemcpyDeviceToHost);		



	printf("\n\nStarting ECSR(modified) Multiplication...");
	// clock_t start_ecsr,end_ecsr;
	// start_ecsr = clock();

	hipEventRecord(start_ecsr_mod);
	spmvECSR_mod<<< nb,nt>>>(ro_gpu,dd_gpu,val_gpu,V_gpu,res_ecsr_mod_gpu);
	hipEventRecord(stop_ecsr_mod);
	hipEventSynchronize(stop_ecsr_mod);
	hipEventElapsedTime(&time_ecsr_mod, start_ecsr_mod,stop_ecsr_mod);
	// end_ecsr = clock();
	// time_ecsr += end_ecsr - start_ecsr;

	//Checking for CUDA errors
	err = hipGetLastError();
	if(err!=hipSuccess){
		printf("ERROR: %s\n",hipGetErrorString(err));
		exit(0);
	}
	printf("Done\n\n");

	//Transfer result back to memory
	hipMemcpy(res_ecsr_mod, res_ecsr_mod_gpu, (SIZE * sizeof(int)), hipMemcpyDeviceToHost);	


	//free memory
	for(i=0;i<SIZE;i++)
		free(M[i]);

	free(M);
	free(V);
	free(ro);
	free(ci);
	free(val);
	free(dd);
	free(res);
	free(res_csr);
	free(res_ecsr);
	hipFree(ro_gpu);
	hipFree(ci_gpu);
	hipFree(val_gpu);	
	hipFree(dd_gpu);
	hipFree(M_gpu);
	hipFree(V_gpu);
	hipFree(res_gpu);
	hipFree(res_csr_gpu);
	hipFree(res_ecsr_gpu);
	printf("===============================================================================\n");

	printf("Average time taken for normal multiplication:%lf\n",time_normal);
	printf("---------------------------------------------------------------\n");
	printf("Average time taken for CSR multiplication:%lf\n",time_csr);
	printf("CSR multiplication runs %lf times faster than normal multiplication\n",time_normal/time_csr);
	printf("---------------------------------------------------------------\n");
	printf("Average time taken for ECSR multiplication:%lf\n",time_ecsr);
	printf("ECSR multiplication runs %lf times faster than normal multiplication\n",time_normal/time_ecsr);
	printf("---------------------------------------------------------------\n");
	printf("Average time taken for ECSR(modified) multiplication:%lf\n",time_ecsr_mod);
	printf("ECSR(modfied) multiplication runs %lf times faster than normal multiplication\n",time_normal/time_ecsr_mod);
	printf("---------------------------------------------------------------\n");
	printf("It is seen that time taken for ECSR multiplication is %lf times that for ECSR(modified) multiplication\n",time_ecsr/time_ecsr_mod);

	return 0;
}

	.text
	.file	"main.hip"
	.globl	_Z25__device_stub__spmvNormalPiS_S_ # -- Begin function _Z25__device_stub__spmvNormalPiS_S_
	.type	_Z25__device_stub__spmvNormalPiS_S_,@function
_Z25__device_stub__spmvNormalPiS_S_:    # @_Z25__device_stub__spmvNormalPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10spmvNormalPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__spmvNormalPiS_S_, .Lfunc_end0-_Z25__device_stub__spmvNormalPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__spmvCSRPiS_S_S_S_ # -- Begin function _Z22__device_stub__spmvCSRPiS_S_S_S_
	.type	_Z22__device_stub__spmvCSRPiS_S_S_S_,@function
_Z22__device_stub__spmvCSRPiS_S_S_S_:   # @_Z22__device_stub__spmvCSRPiS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7spmvCSRPiS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__spmvCSRPiS_S_S_S_, .Lfunc_end1-_Z22__device_stub__spmvCSRPiS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__spmvECSRPiS_S_S_S_ # -- Begin function _Z23__device_stub__spmvECSRPiS_S_S_S_
	.type	_Z23__device_stub__spmvECSRPiS_S_S_S_,@function
_Z23__device_stub__spmvECSRPiS_S_S_S_:  # @_Z23__device_stub__spmvECSRPiS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8spmvECSRPiS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__spmvECSRPiS_S_S_S_, .Lfunc_end2-_Z23__device_stub__spmvECSRPiS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__spmvECSR_modPiS_S_S_S_ # -- Begin function _Z27__device_stub__spmvECSR_modPiS_S_S_S_
	.type	_Z27__device_stub__spmvECSR_modPiS_S_S_S_,@function
_Z27__device_stub__spmvECSR_modPiS_S_S_S_: # @_Z27__device_stub__spmvECSR_modPiS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12spmvECSR_modPiS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z27__device_stub__spmvECSR_modPiS_S_S_S_, .Lfunc_end3-_Z27__device_stub__spmvECSR_modPiS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	80(%rsp), %rdi
	callq	hipEventCreate
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	72(%rsp), %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	64(%rsp), %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	56(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	xorl	%ebx, %ebx
	movl	%ebx, 12(%rsp)
	movl	%ebx, 8(%rsp)
	movl	%ebx, (%rsp)
	movl	%ebx, 4(%rsp)
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	%rax, res(%rip)
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	%rax, res_csr(%rip)
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	%rax, res_ecsr(%rip)
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	%rax, res_ecsr_mod(%rip)
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$2000, %edi                     # imm = 0x7D0
	callq	malloc
	movq	%rax, M(%rip)
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	M(%rip), %rcx
	movq	%rax, (%rcx,%rbx,8)
	incq	%rbx
	cmpq	$250, %rbx
	jne	.LBB4_1
# %bb.2:                                # %.preheader154
	movq	M(%rip), %rbx
	xorl	%r14d, %r14d
.LBB4_3:                                # %.preheader153
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rbx,%r14,8), %rdi
	movl	$1000, %edx                     # imm = 0x3E8
	xorl	%esi, %esi
	callq	memset@PLT
	incq	%r14
	cmpq	$250, %r14
	jne	.LBB4_3
# %bb.4:                                # %.preheader152.preheader
	movl	$25, %ebx
.LBB4_5:                                # %.preheader152
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	imull	$625, %eax, %eax                # imm = 0x271
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$36, %rcx
	addl	%edx, %ecx
	imull	$250, %ecx, %edx
	subl	%edx, %eax
	movslq	%eax, %r14
	movslq	%ecx, %r15
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movq	M(%rip), %rcx
	movq	(%rcx,%r15,8), %rcx
	movl	%eax, (%rcx,%r14,4)
	decl	%ebx
	jne	.LBB4_5
# %bb.6:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	%rax, V(%rip)
.LBB4_7:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movq	V(%rip), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	cmpq	$250, %rbx
	jne	.LBB4_7
# %bb.8:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1004, %edi                     # imm = 0x3EC
	callq	malloc
	movq	%rax, %r15
	movq	%rax, ro(%rip)
	movl	$200, %edi
	callq	malloc
	movq	%rax, %rbx
	movq	%rax, ci(%rip)
	movl	$200, %edi
	callq	malloc
	movq	%rax, %r14
	movq	%rax, val(%rip)
	movl	$0, (%r15)
	movl	$100, %edi
	callq	malloc
	movq	%rax, dd(%rip)
	movq	M(%rip), %rcx
	movl	$255, %ebp
	movq	%rax, %rdx
	xorl	%edi, %edi
	xorl	%r12d, %r12d
	xorl	%r15d, %r15d
.LBB4_9:                                # %.preheader151
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_10 Depth 2
                                        #       Child Loop BB4_13 Depth 3
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	movq	%rdi, 88(%rsp)                  # 8-byte Spill
.LBB4_10:                               #   Parent Loop BB4_9 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_13 Depth 3
	movq	(%rcx,%rdi,8), %rsi
	cmpl	$0, (%rsi,%r8,4)
	je	.LBB4_16
# %bb.11:                               # %.preheader
                                        #   in Loop: Header=BB4_10 Depth=2
	movl	%r8d, %r13d
	subl	%r15d, %r13d
	cmpl	$256, %r13d                     # imm = 0x100
	jl	.LBB4_15
# %bb.12:                               # %.lr.ph.preheader
                                        #   in Loop: Header=BB4_10 Depth=2
	movl	%r9d, 52(%rsp)                  # 4-byte Spill
	movslq	%r12d, %r12
	movq	%r8, 96(%rsp)                   # 8-byte Spill
	movl	%r8d, %r13d
	subl	%r15d, %r13d
	addl	$255, %r15d
.LBB4_13:                               # %.lr.ph
                                        #   Parent Loop BB4_9 Depth=1
                                        #     Parent Loop BB4_10 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movq	ci(%rip), %rbx
	movl	%r15d, (%rbx,%r12,4)
	movq	val(%rip), %r14
	movl	$0, (%r14,%r12,4)
	movq	dd(%rip), %rax
	movl	%ebp, (%rax,%r12,4)
	incq	%r12
	addl	$-255, %r13d
	addl	%ebp, %r15d
	cmpl	%ebp, %r13d
	jg	.LBB4_13
# %bb.14:                               # %._crit_edge.loopexit
                                        #   in Loop: Header=BB4_10 Depth=2
	movq	M(%rip), %rcx
	movq	%rax, %rdx
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movq	96(%rsp), %r8                   # 8-byte Reload
	movl	52(%rsp), %r9d                  # 4-byte Reload
.LBB4_15:                               # %._crit_edge
                                        #   in Loop: Header=BB4_10 Depth=2
	movslq	%r12d, %r12
	movl	%r8d, (%rbx,%r12,4)
	movq	(%rcx,%rdi,8), %rsi
	movl	(%rsi,%r8,4), %esi
	movl	%esi, (%r14,%r12,4)
	testl	%r9d, %r9d
	cmoveq	%rax, %rdx
	cmovel	%r8d, %r13d
	movl	%r13d, (%rdx,%r12,4)
	incl	%r12d
	movl	$1, %r9d
	movl	%r8d, %r15d
.LBB4_16:                               #   in Loop: Header=BB4_10 Depth=2
	incq	%r8
	cmpq	$250, %r8
	jne	.LBB4_10
# %bb.17:                               #   in Loop: Header=BB4_9 Depth=1
	movq	ro(%rip), %rsi
	movl	%r12d, 4(%rsi,%rdi,4)
	incq	%rdi
	cmpq	$250, %rdi
	jne	.LBB4_9
# %bb.18:
	movabsq	$4294967303, %rbx               # imm = 0x100000007
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$M_gpu, %edi
	movl	$250000, %esi                   # imm = 0x3D090
	callq	hipMalloc
	movl	$ro_gpu, %edi
	movl	$1004, %esi                     # imm = 0x3EC
	callq	hipMalloc
	movl	$ci_gpu, %edi
	movl	$200, %esi
	callq	hipMalloc
	movl	$val_gpu, %edi
	movl	$200, %esi
	callq	hipMalloc
	movl	$dd_gpu, %edi
	movl	$100, %esi
	callq	hipMalloc
	movl	$V_gpu, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	callq	hipMalloc
	movl	$res_gpu, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	callq	hipMalloc
	movl	$res_csr_gpu, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	callq	hipMalloc
	movl	$res_ecsr_gpu, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	callq	hipMalloc
	movl	$res_ecsr_mod_gpu, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	callq	hipMalloc
	movq	M_gpu(%rip), %rdi
	movq	M(%rip), %rsi
	movl	$250000, %edx                   # imm = 0x3D090
	movl	$1, %ecx
	callq	hipMemcpy
	movq	ro_gpu(%rip), %rdi
	movq	ro(%rip), %rsi
	movl	$1004, %edx                     # imm = 0x3EC
	movl	$1, %ecx
	callq	hipMemcpy
	movq	ci_gpu(%rip), %rdi
	movq	ci(%rip), %rsi
	movl	$200, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	val_gpu(%rip), %rdi
	movq	val(%rip), %rsi
	movl	$200, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	dd_gpu(%rip), %rdi
	movq	dd(%rip), %rsi
	movl	$100, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	V_gpu(%rip), %rdi
	movq	V(%rip), %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	25(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.19:
	movq	M_gpu(%rip), %rdi
	movq	V_gpu(%rip), %rsi
	movq	res_gpu(%rip), %rdx
	callq	_Z25__device_stub__spmvNormalPiS_S_
.LBB4_20:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	40(%rsp), %rdi
	callq	hipEventSynchronize
	movq	80(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	%rsp, %rdi
	callq	hipEventElapsedTime
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB4_22
# %bb.21:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB4_22:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movq	res(%rip), %rdi
	movq	res_gpu(%rip), %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_24
# %bb.23:
	movq	ro_gpu(%rip), %rdi
	movq	dd_gpu(%rip), %rsi
	movq	val_gpu(%rip), %rdx
	movq	V_gpu(%rip), %rcx
	movq	res_csr_gpu(%rip), %r8
	callq	_Z22__device_stub__spmvCSRPiS_S_S_S_
.LBB4_24:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rdi
	callq	hipEventSynchronize
	movq	72(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	12(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB4_34
# %bb.25:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movq	res_csr(%rip), %rdi
	movq	res_csr_gpu(%rip), %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %edi
	xorl	%eax, %eax
	callq	printf
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_27
# %bb.26:
	movq	ro_gpu(%rip), %rdi
	movq	dd_gpu(%rip), %rsi
	movq	val_gpu(%rip), %rdx
	movq	V_gpu(%rip), %rcx
	movq	res_ecsr_gpu(%rip), %r8
	callq	_Z23__device_stub__spmvECSRPiS_S_S_S_
.LBB4_27:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	64(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	8(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB4_34
# %bb.28:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movq	res_ecsr(%rip), %rdi
	movq	res_ecsr_gpu(%rip), %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.9, %edi
	xorl	%eax, %eax
	callq	printf
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_30
# %bb.29:
	movq	ro_gpu(%rip), %rdi
	movq	dd_gpu(%rip), %rsi
	movq	val_gpu(%rip), %rdx
	movq	V_gpu(%rip), %rcx
	movq	res_ecsr_mod_gpu(%rip), %r8
	callq	_Z27__device_stub__spmvECSR_modPiS_S_S_S_
.LBB4_30:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	4(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB4_34
# %bb.31:
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movq	res_ecsr_mod(%rip), %rdi
	movq	res_ecsr_mod_gpu(%rip), %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB4_32:                               # =>This Inner Loop Header: Depth=1
	movq	M(%rip), %rax
	movq	(%rax,%rbx,8), %rdi
	callq	free
	incq	%rbx
	cmpq	$250, %rbx
	jne	.LBB4_32
# %bb.33:
	movq	M(%rip), %rdi
	callq	free
	movq	V(%rip), %rdi
	callq	free
	movq	ro(%rip), %rdi
	callq	free
	movq	ci(%rip), %rdi
	callq	free
	movq	val(%rip), %rdi
	callq	free
	movq	dd(%rip), %rdi
	callq	free
	movq	res(%rip), %rdi
	callq	free
	movq	res_csr(%rip), %rdi
	callq	free
	movq	res_ecsr(%rip), %rdi
	callq	free
	movq	ro_gpu(%rip), %rdi
	callq	hipFree
	movq	ci_gpu(%rip), %rdi
	callq	hipFree
	movq	val_gpu(%rip), %rdi
	callq	hipFree
	movq	dd_gpu(%rip), %rdi
	callq	hipFree
	movq	M_gpu(%rip), %rdi
	callq	hipFree
	movq	V_gpu(%rip), %rdi
	callq	hipFree
	movq	res_gpu(%rip), %rdi
	callq	hipFree
	movq	res_csr_gpu(%rip), %rdi
	callq	hipFree
	movq	res_ecsr_gpu(%rip), %rdi
	callq	hipFree
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	cvtss2sd	(%rsp), %xmm0
	movl	$.L.str.12, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.11, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0
	movl	$.L.str.14, %edi
	movb	$1, %al
	callq	printf
	movss	(%rsp), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	12(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.15, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.11, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0
	movl	$.L.str.16, %edi
	movb	$1, %al
	callq	printf
	movss	(%rsp), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	8(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.17, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.11, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0
	movl	$.L.str.18, %edi
	movb	$1, %al
	callq	printf
	movss	(%rsp), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	4(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.19, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.11, %edi
	callq	puts@PLT
	movss	8(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	divss	4(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.20, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_34:
	.cfi_def_cfa_offset 160
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	xorl	%edi, %edi
	callq	exit
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10spmvNormalPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7spmvCSRPiS_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8spmvECSRPiS_S_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12spmvECSR_modPiS_S_S_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10spmvNormalPiS_S_,@object    # @_Z10spmvNormalPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10spmvNormalPiS_S_
	.p2align	3, 0x0
_Z10spmvNormalPiS_S_:
	.quad	_Z25__device_stub__spmvNormalPiS_S_
	.size	_Z10spmvNormalPiS_S_, 8

	.type	_Z7spmvCSRPiS_S_S_S_,@object    # @_Z7spmvCSRPiS_S_S_S_
	.globl	_Z7spmvCSRPiS_S_S_S_
	.p2align	3, 0x0
_Z7spmvCSRPiS_S_S_S_:
	.quad	_Z22__device_stub__spmvCSRPiS_S_S_S_
	.size	_Z7spmvCSRPiS_S_S_S_, 8

	.type	_Z8spmvECSRPiS_S_S_S_,@object   # @_Z8spmvECSRPiS_S_S_S_
	.globl	_Z8spmvECSRPiS_S_S_S_
	.p2align	3, 0x0
_Z8spmvECSRPiS_S_S_S_:
	.quad	_Z23__device_stub__spmvECSRPiS_S_S_S_
	.size	_Z8spmvECSRPiS_S_S_S_, 8

	.type	_Z12spmvECSR_modPiS_S_S_S_,@object # @_Z12spmvECSR_modPiS_S_S_S_
	.globl	_Z12spmvECSR_modPiS_S_S_S_
	.p2align	3, 0x0
_Z12spmvECSR_modPiS_S_S_S_:
	.quad	_Z27__device_stub__spmvECSR_modPiS_S_S_S_
	.size	_Z12spmvECSR_modPiS_S_S_S_, 8

	.type	M,@object                       # @M
	.bss
	.globl	M
	.p2align	3, 0x0
M:
	.quad	0
	.size	M, 8

	.type	V,@object                       # @V
	.globl	V
	.p2align	3, 0x0
V:
	.quad	0
	.size	V, 8

	.type	ro,@object                      # @ro
	.globl	ro
	.p2align	3, 0x0
ro:
	.quad	0
	.size	ro, 8

	.type	ci,@object                      # @ci
	.globl	ci
	.p2align	3, 0x0
ci:
	.quad	0
	.size	ci, 8

	.type	val,@object                     # @val
	.globl	val
	.p2align	3, 0x0
val:
	.quad	0
	.size	val, 8

	.type	dd,@object                      # @dd
	.globl	dd
	.p2align	3, 0x0
dd:
	.quad	0
	.size	dd, 8

	.type	ro_gpu,@object                  # @ro_gpu
	.globl	ro_gpu
	.p2align	3, 0x0
ro_gpu:
	.quad	0
	.size	ro_gpu, 8

	.type	ci_gpu,@object                  # @ci_gpu
	.globl	ci_gpu
	.p2align	3, 0x0
ci_gpu:
	.quad	0
	.size	ci_gpu, 8

	.type	val_gpu,@object                 # @val_gpu
	.globl	val_gpu
	.p2align	3, 0x0
val_gpu:
	.quad	0
	.size	val_gpu, 8

	.type	dd_gpu,@object                  # @dd_gpu
	.globl	dd_gpu
	.p2align	3, 0x0
dd_gpu:
	.quad	0
	.size	dd_gpu, 8

	.type	V_gpu,@object                   # @V_gpu
	.globl	V_gpu
	.p2align	3, 0x0
V_gpu:
	.quad	0
	.size	V_gpu, 8

	.type	M_gpu,@object                   # @M_gpu
	.globl	M_gpu
	.p2align	3, 0x0
M_gpu:
	.quad	0
	.size	M_gpu, 8

	.type	res_csr,@object                 # @res_csr
	.globl	res_csr
	.p2align	3, 0x0
res_csr:
	.quad	0
	.size	res_csr, 8

	.type	res_ecsr,@object                # @res_ecsr
	.globl	res_ecsr
	.p2align	3, 0x0
res_ecsr:
	.quad	0
	.size	res_ecsr, 8

	.type	res,@object                     # @res
	.globl	res
	.p2align	3, 0x0
res:
	.quad	0
	.size	res, 8

	.type	res_ecsr_mod,@object            # @res_ecsr_mod
	.globl	res_ecsr_mod
	.p2align	3, 0x0
res_ecsr_mod:
	.quad	0
	.size	res_ecsr_mod, 8

	.type	res_csr_gpu,@object             # @res_csr_gpu
	.globl	res_csr_gpu
	.p2align	3, 0x0
res_csr_gpu:
	.quad	0
	.size	res_csr_gpu, 8

	.type	res_ecsr_gpu,@object            # @res_ecsr_gpu
	.globl	res_ecsr_gpu
	.p2align	3, 0x0
res_ecsr_gpu:
	.quad	0
	.size	res_ecsr_gpu, 8

	.type	res_gpu,@object                 # @res_gpu
	.globl	res_gpu
	.p2align	3, 0x0
res_gpu:
	.quad	0
	.size	res_gpu, 8

	.type	res_ecsr_mod_gpu,@object        # @res_ecsr_mod_gpu
	.globl	res_ecsr_mod_gpu
	.p2align	3, 0x0
res_ecsr_mod_gpu:
	.quad	0
	.size	res_ecsr_mod_gpu, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Generating Sparse Matrix ..."
	.size	.L.str, 29

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Generating Dense Vector..."
	.size	.L.str.2, 27

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Building CSR vectors and Distance Difference vector..."
	.size	.L.str.3, 55

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"abc "
	.size	.L.str.4, 5

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"\n\nStarting Normal Multiplication..."
	.size	.L.str.5, 36

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"ERROR: %s\n"
	.size	.L.str.6, 11

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\n\nStarting CSR Multiplication..."
	.size	.L.str.7, 33

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\n\nStarting ECSR Multiplication..."
	.size	.L.str.8, 34

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"\n\nStarting ECSR(modified) Multiplication..."
	.size	.L.str.9, 44

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Average time taken for normal multiplication:%lf\n"
	.size	.L.str.12, 50

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"Average time taken for CSR multiplication:%lf\n"
	.size	.L.str.14, 47

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"CSR multiplication runs %lf times faster than normal multiplication\n"
	.size	.L.str.15, 69

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Average time taken for ECSR multiplication:%lf\n"
	.size	.L.str.16, 48

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"ECSR multiplication runs %lf times faster than normal multiplication\n"
	.size	.L.str.17, 70

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Average time taken for ECSR(modified) multiplication:%lf\n"
	.size	.L.str.18, 58

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"ECSR(modfied) multiplication runs %lf times faster than normal multiplication\n"
	.size	.L.str.19, 79

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"It is seen that time taken for ECSR multiplication is %lf times that for ECSR(modified) multiplication\n"
	.size	.L.str.20, 104

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10spmvNormalPiS_S_"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7spmvCSRPiS_S_S_S_"
	.size	.L__unnamed_2, 21

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8spmvECSRPiS_S_S_S_"
	.size	.L__unnamed_3, 22

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z12spmvECSR_modPiS_S_S_S_"
	.size	.L__unnamed_4, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr.5,@object                 # @str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr.5:
	.asciz	"Done"
	.size	.Lstr.5, 5

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Done\n"
	.size	.Lstr.6, 6

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"==============================================================================="
	.size	.Lstr.7, 80

	.type	.Lstr.11,@object                # @str.11
.Lstr.11:
	.asciz	"---------------------------------------------------------------"
	.size	.Lstr.11, 64

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__spmvNormalPiS_S_
	.addrsig_sym _Z22__device_stub__spmvCSRPiS_S_S_S_
	.addrsig_sym _Z23__device_stub__spmvECSRPiS_S_S_S_
	.addrsig_sym _Z27__device_stub__spmvECSR_modPiS_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10spmvNormalPiS_S_
	.addrsig_sym _Z7spmvCSRPiS_S_S_S_
	.addrsig_sym _Z8spmvECSRPiS_S_S_S_
	.addrsig_sym _Z12spmvECSR_modPiS_S_S_S_
	.addrsig_sym ro_gpu
	.addrsig_sym ci_gpu
	.addrsig_sym val_gpu
	.addrsig_sym dd_gpu
	.addrsig_sym V_gpu
	.addrsig_sym M_gpu
	.addrsig_sym res_csr_gpu
	.addrsig_sym res_ecsr_gpu
	.addrsig_sym res_gpu
	.addrsig_sym res_ecsr_mod_gpu
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10spmvNormalPiS_S_    ; -- Begin function _Z10spmvNormalPiS_S_
	.globl	_Z10spmvNormalPiS_S_
	.p2align	8
	.type	_Z10spmvNormalPiS_S_,@function
_Z10spmvNormalPiS_S_:                   ; @_Z10spmvNormalPiS_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0xfa, v1
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v2, 0xfa, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
	s_add_u32 s4, s6, s2
	s_addc_u32 s5, s7, s3
	s_add_u32 s2, s2, 4
	global_load_b32 v6, v[3:4], off
	s_load_b32 s4, s[4:5], 0x0
	s_addc_u32 s3, s3, 0
	s_cmpk_lg_i32 s2, 0x3e8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, s4, v6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v0, v3
	s_cbranch_scc1 .LBB0_2
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10spmvNormalPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10spmvNormalPiS_S_, .Lfunc_end0-_Z10spmvNormalPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7spmvCSRPiS_S_S_S_    ; -- Begin function _Z7spmvCSRPiS_S_S_S_
	.globl	_Z7spmvCSRPiS_S_S_S_
	.p2align	8
	.type	_Z7spmvCSRPiS_S_S_S_,@function
_Z7spmvCSRPiS_S_S_S_:                   ; @_Z7spmvCSRPiS_S_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s10, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 0xf9, v1
	s_xor_b32 s10, exec_lo, s10
; %bb.1:                                ; %..loopexit_crit_edge
	v_mov_b32_e32 v2, 0
; %bb.2:                                ; %Flow45
	s_or_saveexec_b32 s10, s10
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 exec_lo, exec_lo, s10
	s_cbranch_execz .LBB1_8
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_mov_b32 s1, exec_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v3, v4
	s_cbranch_execz .LBB1_7
; %bb.4:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v6, 31, v3
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_mov_b32 s2, 0
.LBB1_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[7:8], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v11, v[5:6], off
	global_load_b32 v12, v[9:10], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v12, v11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v9 :: v_dual_add_nc_u32 v3, 1, v3
	v_cmp_ge_i32_e64 s0, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_5
; %bb.6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_7:                                ; %Flow44
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_8:                                ; %.loopexit
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7spmvCSRPiS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7spmvCSRPiS_S_S_S_, .Lfunc_end1-_Z7spmvCSRPiS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8spmvECSRPiS_S_S_S_   ; -- Begin function _Z8spmvECSRPiS_S_S_S_
	.globl	_Z8spmvECSRPiS_S_S_S_
	.p2align	8
	.type	_Z8spmvECSRPiS_S_S_S_,@function
_Z8spmvECSRPiS_S_S_S_:                  ; @_Z8spmvECSRPiS_S_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s10, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 0xf9, v1
	s_xor_b32 s10, exec_lo, s10
; %bb.1:                                ; %..loopexit_crit_edge
	v_mov_b32_e32 v2, 0
; %bb.2:                                ; %Flow78
	s_or_saveexec_b32 s10, s10
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 exec_lo, exec_lo, s10
	s_cbranch_execz .LBB2_12
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, 1, v3
	v_cmpx_lt_i32_e32 -1, v3
	s_cbranch_execz .LBB2_7
; %bb.4:                                ; %.lr.ph.preheader
	v_add_nc_u32_e32 v0, 1, v3
	s_mov_b32 s0, s2
	s_mov_b32 s1, s3
	s_mov_b32 s12, 0
	s_mov_b32 s13, 0
.LBB2_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s14, s[0:1], 0x0
	v_add_nc_u32_e32 v0, -1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s13, s14, s13
	s_add_u32 s0, s0, 4
	v_mov_b32_e32 v6, s13
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB2_5
; %bb.6:                                ; %Flow76
	s_or_b32 exec_lo, exec_lo, s12
.LBB2_7:                                ; %Flow77
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s11
	v_ashrrev_i32_e32 v9, 31, v3
	v_mov_b32_e32 v8, v3
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s1, exec_lo
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	v_add_co_u32 v12, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v0, v[12:13], off
	global_load_b32 v3, v[7:8], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v0, v3, v0
	v_cmpx_lt_i32_e64 v5, v4
	s_cbranch_execz .LBB2_11
; %bb.8:                                ; %.lr.ph45.preheader
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	v_add_co_u32 v9, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v11, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	s_mov_b32 s2, 0
.LBB2_9:                                ; %.lr.ph45
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v13, v[11:12], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, v7, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, v8, v14, vcc_lo
	global_load_b32 v3, v[9:10], off
	global_load_b32 v6, v[13:14], off
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, v11, 4
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[13:14], null, v6, v3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v13 :: v_dual_add_nc_u32 v5, 1, v5
	v_cmp_ge_i32_e64 s0, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_9
; %bb.10:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_11:                               ; %Flow75
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_12:                               ; %Flow79
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8spmvECSRPiS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8spmvECSRPiS_S_S_S_, .Lfunc_end2-_Z8spmvECSRPiS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 592
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12spmvECSR_modPiS_S_S_S_ ; -- Begin function _Z12spmvECSR_modPiS_S_S_S_
	.globl	_Z12spmvECSR_modPiS_S_S_S_
	.p2align	8
	.type	_Z12spmvECSR_modPiS_S_S_S_,@function
_Z12spmvECSR_modPiS_S_S_S_:             ; @_Z12spmvECSR_modPiS_S_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s10, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 0xf9, v1
	s_xor_b32 s10, exec_lo, s10
; %bb.1:                                ; %..loopexit_crit_edge
	v_mov_b32_e32 v2, 0
; %bb.2:                                ; %Flow53
	s_or_saveexec_b32 s10, s10
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 exec_lo, exec_lo, s10
	s_cbranch_execz .LBB3_8
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_mov_b32 s1, exec_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v3
	v_mov_b32_e32 v5, v3
	v_add_nc_u32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v0, v[9:10], off
	global_load_b32 v9, v[5:6], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v0, v9, v0
	v_cmpx_lt_i32_e64 v3, v4
	s_cbranch_execz .LBB3_7
; %bb.4:                                ; %.lr.ph.preheader
	v_add_co_u32 v9, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	s_mov_b32 s2, 0
.LBB3_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v11, v[9:10], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, v5, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v6, v12, vcc_lo
	global_load_b32 v13, v[7:8], off
	global_load_b32 v14, v[11:12], off
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v14, v13, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v11 :: v_dual_add_nc_u32 v3, 1, v3
	v_cmp_ge_i32_e64 s0, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_5
; %bb.6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_7:                                ; %Flow52
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_8:                                ; %.loopexit
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12spmvECSR_modPiS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z12spmvECSR_modPiS_S_S_S_, .Lfunc_end3-_Z12spmvECSR_modPiS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10spmvNormalPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10spmvNormalPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7spmvCSRPiS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7spmvCSRPiS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8spmvECSRPiS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8spmvECSRPiS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12spmvECSR_modPiS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12spmvECSR_modPiS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
