/* File:     mat_add.cu
 * Purpose:  Implement matrix addition on a gpu using cuda
 *
 * Output:   Result of matrix addition.  
 *
 * Notes:
 * 1.  There are m blocks with n threads each.
 */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include "cuPrintf.cuh"
//#include "cuPrintf.cu"
 //#include "utils/cuPrintf.cu"


/*---------------------------------------------------------------------
 * Kernel:   Mat_add
 * Purpose:  Implement matrix addition
 * In args:  A, B, m, n
 * Out arg:  C
 */

__global__ void rotMatFunc(float matIn[], 
                           float matOut[], 
                           int dimX, 
                           int dimY, 
                           float rotMat[]) {
//    int y = blockIdx.y;
///    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    if ( x >= dimX || y >= dimY) 
         return;
    //printf("x,y = %d %d, blockIdx.x,y= %d %d,  blockDim.x,y = %d %d, threadIdx.x,y= %d %d\n",
    //        x,y,      blockIdx.x,blockIdx.y,      blockDim.x,blockDim.y,     threadIdx.x,threadIdx.y);

   float xOut,yOut;
   float xIn, yIn;
   int iIn, jIn;
   float dimXf=(float)dimX, dimYf=(float)dimY;
   int  x0=dimX/2, y0=dimY/2;

//           xOut = (float)(x - x0)/dimXf;
//           yOut = (float)(y - y0)/dimYf;
           xOut = (float)(x - x0);
           yOut = (float)(y - y0);
           
           xIn = rotMat[0] * xOut + rotMat[1] * yOut;
           yIn = rotMat[2] * xOut + rotMat[3] * yOut;
           
//           iIn = int(xIn * dimXf + x0);
//           jIn = int(yIn * dimYf + y0);
           iIn = int(xIn + x0);
           jIn = int(yIn + y0);

           if ( iIn >= 0 && 
                iIn < dimX && 
                jIn >= 0 && 
                jIn < dimY) 
                {
                printf("x=%d y=%d iIn=%d jIn=%d in=%d, out=%d\n",x, y, iIn, jIn, iIn*dimY+jIn,x*dimY+y);
                matOut[x*dimY+y] = matIn[iIn*dimY+jIn];
                }

/*
    int indexOfMatrixOut = y + x * dimY;
    int  x0=dimX/2, y0=dimY/2;//this may be passed

   float xOut,yOut;
   float xIn, yIn;
   int iIn, jIn;
   float dimXf=(float)dimX, dimYf=(float)dimY;
   xOut = (float)(x - x0)/dimXf;
   yOut = (float)(y - y0)/dimYf;
   //printf("x=%d y=%d x0=%d dimXf=%f xOut=%f yOut=%f\n",x, y, x0, dimXf, xOut, yOut);
   xIn = rotMat[0] * xOut + rotMat[1] * yOut;
   yIn = rotMat[2] * xOut + rotMat[3] * yOut;
   //printf("x =%d y=%d xIn=%f yIn=%f\n",x, y, xIn, yIn);
   iIn = int(xIn * dimXf + x0);
   jIn = int(yIn * dimYf + y0);
   int indexOfMatrixIn = jIn + iIn * dimY;

   if ( iIn >= 0 && 
        iIn < dimX && 
        jIn >= 0 && 
        jIn < dimY) 
        {
            matOut[indexOfMatrixOut] = matIn[indexOfMatrixIn];
         printf("x=%d y=%d in=%d, out=%d vI=%f vO=%f\n",x, y, indexOfMatrixIn,indexOfMatrixOut, 
                 matIn[indexOfMatrixIn], matOut[indexOfMatrixOut]);
         }
*/   
}  /* Mat_add */


/*---------------------------------------------------------------------
 * Function:  Fill_matrix
 * Purpose:   Fill an m x n matrix with random values
 * In args:   m, n
 * Out arg:   A
 */
void Fill_matrix(float A[], int dimX, int dimY) {
   int i, j;
//numVec, dimVec
   for (i = 0; i < dimX; i++)
      for (j = 0; j < dimY; j++)
          if(i==j )//or (i+j)==(dimX+1))
            A[i*dimY+j]=1.0f;
          else
            A[i*dimY+j]=0.0f;
}  /* Read_matrix */


/*---------------------------------------------------------------------
 * Function:  Print_matrix
 * Purpose:   Print an m x n matrix to stdout
 * In args:   title, A, m, n
 */
void Print_matrix(const char title[], float A[], int numVec, int dimVec, int m, int n) {
   int i, j;
   //numVec, dimVec
   printf("%s\n", title);
   for (i = 0; i < m; i++) {
      for (j = 0; j < n; j++)
         printf("%.2f ", A[i*dimVec+j]);
      printf("\n");
   }  
}  /* Print_matrix */

void checkError(cudaError_t error, const char function[])
{

        if(error != cudaSuccess)
        {
                printf("\"%s\" has a problem with error code %d and desc: %s\n", function, error, cudaGetErrorString(error));
                exit(-1);
        }
}

bool checkIfMatricesEqual(float * mat1, float * mat2, float matSize)
{
    int i = 0;
    for( ; i < matSize; i++)
       if(mat1[i] != mat2[i]){
           printf("values different for i: %d\n", i);
		   printf("mat1[i] = %d, mat2[i] = %d\n", mat1[i], mat2[i]);		   
		   return false;
	   }

    return true;
}
void rotateCPU(float matIn[], 
               float matOut[], int dimX, int dimY,
               float rotMat[])
{
   //float fX0,fY0;
   int  x0=dimX/2, y0=dimY/2;

   //fX0 = (float)iX0;
   //fY0 = (float)iY0;
   float xOut,yOut;
   float xIn, yIn;
   int iIn, jIn;
   float dimXf=(float)dimX, dimYf=(float)dimY;
   for(int x = 0 ; x < dimX; ++x)
       for(int y = 0 ; y < dimY; ++y){
           xOut = (float)(x - x0)/dimXf;
           yOut = (float)(y - y0)/dimYf;
           
           xIn = rotMat[0] * xOut + rotMat[1] * yOut;
           yIn = rotMat[2] * xOut + rotMat[3] * yOut;
           
           iIn = int(xIn * dimXf + x0);
           jIn = int(yIn * dimYf + y0);

           if ( iIn >= 0 && 
                iIn < dimX && 
                jIn >= 0 && 
                jIn < dimY) 

                matOut[x*dimY+y] = matIn[iIn*dimY+jIn];
           }

}
/* Host code */
int main(int argc, char* argv[]) {
   size_t dimX = 900;//mat size
   size_t dimY = 900;
   size_t gridX = 9;//mat size
   size_t gridY = 9;

   // variables for threads per block, number of blocks.
   int threadsPerBlock = 32;//, blocksInGrid = 0;
   //threadsPerBlock = min(_dimY, _dimY);
   //create cuda event variables
   cudaEvent_t hostStart, hostStop, deviceStart, deviceStop;
   float timeDifferenceOnHost, timeDifferenceOnDevice;
   //initialize cuda timing variables
   cudaEventCreate(&hostStart);
   cudaEventCreate(&hostStop);
   cudaEventCreate(&deviceStart);
   cudaEventCreate(&deviceStop);

   float *h_A, *h_B, *h_B2, *h_rotMat;//PC
   float *d_A, *d_B, *d_rotMat;//GPU
   size_t size, matrixSize;

   /* Get size of matrices */

   matrixSize = dimX*dimY;
   size = matrixSize*sizeof(float);

   h_A = (float*) calloc(size,1);
   h_B = (float*) calloc(size,1);
   h_B2 = (float*) calloc(size,1);
   h_rotMat = (float*) calloc(4*sizeof(float),1);

   Fill_matrix(h_A, dimX, dimY);

   //init rot Matrix
   h_rotMat[0] = 0.f;
   h_rotMat[1] = -1.f;
   //h_rotMat[0] = 0.936f;
   //h_rotMat[1] = 0.352f;
   h_rotMat[2] = -h_rotMat[1];
   h_rotMat[3] =  h_rotMat[0];

   Print_matrix("A =", h_A, dimX, dimY, 9, 9);
   printf("Rotating matrices on CPU...\n");
   cudaEventRecord(hostStart, 0);
   //rotate matrix using CPU
   rotateCPU(h_A ,h_B2, dimX, dimY, h_rotMat);
   //////////
   cudaEventRecord(hostStop, 0);
   cudaEventElapsedTime(&timeDifferenceOnHost, hostStart, hostStop);
   printf("Matrix rotation over. Time taken on CPU: %5.5f\n",     
          timeDifferenceOnHost);
   Print_matrix("B2(CPU) =", h_B2, dimX, dimY, 9, 9);

   /* Allocate matrices in device memory */
   cudaMalloc(&d_A, size);
   cudaMalloc(&d_B, size);
   cudaMalloc(&d_rotMat, 4*sizeof(float));

   /* Copy matrices from host memory to device memory */
   cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
   cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
   cudaMemcpy(d_rotMat, h_rotMat, 4*sizeof(float), cudaMemcpyHostToDevice);

   //create a proper grid block using dim3

   /* Invoke kernel using dimX * dimY thread blocks, each of    */
   /* which contains threadsPerBlock threads                        */
   
   dim3 block(threadsPerBlock, threadsPerBlock);
   dim3 grid( (gridX+threadsPerBlock-1)/threadsPerBlock, 
              (gridY+threadsPerBlock-1)/threadsPerBlock );
   cudaEventRecord(deviceStart, 0);
   rotMatFunc<<<grid, block>>>(d_A, d_B, dimX, dimY, d_rotMat);

   cudaError_t code=cudaGetLastError();
   if (code)
       printf("error=%s",cudaGetErrorString(code));
   else
       printf("code=%d",code);
   cudaDeviceSynchronize();  
   cudaEventRecord(deviceStop, 0);

   /* Wait for the kernel to complete */
   cudaThreadSynchronize();
   cudaEventElapsedTime(&timeDifferenceOnDevice, deviceStart, deviceStop);

   /* Copy result from device memory to host memory */
   checkError(cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost), "Matrix B Copy from device to Host");
	
   if(checkIfMatricesEqual(h_B, h_B2, matrixSize))
      printf("Kernels correct!\n");
   else
      printf("Kernel logic wrong!\n");
	
   printf("Finished addition on GPU. Time taken: %5.5f\n", timeDifferenceOnDevice);   
   printf("Speedup: %5.5f\n", (float)timeDifferenceOnHost/timeDifferenceOnDevice);

   Print_matrix("The rotated image(CPU) is: ", h_B2, dimX, dimY, 9, 9);
   Print_matrix("The rotated image(GPU) is: ", h_B, dimX, dimY, 9, 9);

   /* Free device memory */
   cudaFree(d_A);
   cudaFree(d_B);

   /* Free host memory */
   free(h_A);
   free(h_B);
   free(h_B2);

   return 0;
}  /* main */

	.file	"tmpxft_003a1675_00000000-6_matAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11Fill_matrixPfii
	.type	_Z11Fill_matrixPfii, @function
_Z11Fill_matrixPfii:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
.L3:
	cmpl	%esi, %ecx
	jge	.L2
	movslq	%r8d, %rax
	leaq	(%rdi,%rax,4), %r9
	xorl	%eax, %eax
.L7:
	cmpl	%edx, %eax
	jge	.L10
	movss	.LC0(%rip), %xmm0
	cmpl	%ecx, %eax
	je	.L4
	xorps	%xmm0, %xmm0
.L4:
	movss	%xmm0, (%r9,%rax,4)
	incq	%rax
	jmp	.L7
.L10:
	incl	%ecx
	addl	%edx, %r8d
	jmp	.L3
.L2:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11Fill_matrixPfii, .-_Z11Fill_matrixPfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%s\n"
.LC3:
	.string	"%.2f "
.LC4:
	.string	"\n"
	.text
	.globl	_Z12Print_matrixPKcPfiiii
	.type	_Z12Print_matrixPKcPfiiii, @function
_Z12Print_matrixPKcPfiiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %rdx
	xorl	%eax, %eax
	movl	$2, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	leaq	.LC2(%rip), %rsi
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movl	%r9d, 4(%rsp)
	call	__printf_chk@PLT
.L12:
	cmpl	%r14d, %r12d
	jge	.L11
	movslq	%ebp, %rax
	xorl	%r15d, %r15d
	leaq	(%rbx,%rax,4), %rcx
.L15:
	cmpl	%r15d, 4(%rsp)
	jle	.L17
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rcx,%r15,4), %xmm0
	movq	%rcx, 8(%rsp)
	incq	%r15
	call	__printf_chk@PLT
	movq	8(%rsp), %rcx
	jmp	.L15
.L17:
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	incl	%r12d
	addl	%r13d, %ebp
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L12
.L11:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z12Print_matrixPKcPfiiii, .-_Z12Print_matrixPKcPfiiii
	.section	.rodata.str1.1
.LC5:
	.string	"\"%s\" has a problem with error code %d and desc: %s\n"
	.text
	.globl	_Z10checkError9cudaErrorPKc
	.type	_Z10checkError9cudaErrorPKc, @function
_Z10checkError9cudaErrorPKc:
.LFB2029:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L18
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movl	%ebx, %ecx
	movq	%rbp, %rdx
	movq	%rax, %r8
	leaq	.LC5(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L18:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z10checkError9cudaErrorPKc, .-_Z10checkError9cudaErrorPKc
	.section	.rodata.str1.1
.LC6:
	.string	"values different for i: %d\n"
.LC7:
	.string	"mat1[i] = %d, mat2[i] = %d\n"
	.text
	.globl	_Z20checkIfMatricesEqualPfS_f
	.type	_Z20checkIfMatricesEqualPfS_f, @function
_Z20checkIfMatricesEqualPfS_f:
.LFB2030:
	.cfi_startproc
	endbr64
	xorl	%edx, %edx
	cvtsi2ssl	%edx, %xmm1
	comiss	%xmm1, %xmm0
	ja	.L34
	movb	$1, %al
	ret
.L34:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rax
	.cfi_def_cfa_offset 32
.L28:
	movq	%rdi, %rbp
	movq	%rsi, %rbx
	addq	$4, %rdi
	addq	$4, %rsi
	movss	0(%rbp), %xmm1
	ucomiss	(%rbx), %xmm1
	jp	.L29
	je	.L25
.L29:
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$2, %al
	leaq	.LC7(%rip), %rsi
	cvtss2sd	0(%rbp), %xmm0
	cvtss2sd	(%rbx), %xmm1
	call	__printf_chk@PLT
	xorl	%eax, %eax
	jmp	.L23
.L25:
	incl	%edx
	cvtsi2ssl	%edx, %xmm1
	comiss	%xmm1, %xmm0
	ja	.L28
	movb	$1, %al
.L23:
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z20checkIfMatricesEqualPfS_f, .-_Z20checkIfMatricesEqualPfS_f
	.globl	_Z9rotateCPUPfS_iiS_
	.type	_Z9rotateCPUPfS_iiS_, @function
_Z9rotateCPUPfS_iiS_:
.LFB2031:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	movq	%rdi, %r9
	movq	%rsi, %r10
	movl	$2, %edi
	movl	%edx, %esi
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	cvtsi2ssl	%ecx, %xmm4
	cltd
	idivl	%edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	cvtsi2ssl	%esi, %xmm3
	xorl	%ebp, %ebp
	movl	%eax, %ebx
	movl	%ecx, %eax
	cltd
	movl	%ebx, %r11d
	idivl	%edi
	negl	%r11d
.L36:
	leal	(%rbx,%r11), %edx
	cmpl	%edx, %esi
	jle	.L48
	xorl	%edi, %edi
.L39:
	cmpl	%ecx, %edi
	jge	.L49
	movl	%edi, %edx
	cvtsi2ssl	%r11d, %xmm0
	movss	(%r8), %xmm1
	movss	4(%r8), %xmm5
	subl	%eax, %edx
	cvtsi2ssl	%edx, %xmm2
	divss	%xmm3, %xmm0
	divss	%xmm4, %xmm2
	mulss	%xmm0, %xmm1
	mulss	%xmm2, %xmm5
	addss	%xmm5, %xmm1
	cvtsi2ssl	%ebx, %xmm5
	mulss	%xmm3, %xmm1
	addss	%xmm5, %xmm1
	cvttss2sil	%xmm1, %edx
	testl	%edx, %edx
	js	.L37
	cmpl	%edx, %esi
	jle	.L37
	mulss	8(%r8), %xmm0
	cvtsi2ssl	%eax, %xmm1
	mulss	12(%r8), %xmm2
	addss	%xmm2, %xmm0
	mulss	%xmm4, %xmm0
	addss	%xmm1, %xmm0
	cvttss2sil	%xmm0, %r12d
	testl	%r12d, %r12d
	js	.L37
	cmpl	%r12d, %ecx
	jle	.L37
	imull	%ecx, %edx
	addl	%r12d, %edx
	movslq	%edx, %rdx
	movss	(%r9,%rdx,4), %xmm0
	leal	(%rdi,%rbp), %edx
	movslq	%edx, %rdx
	movss	%xmm0, (%r10,%rdx,4)
.L37:
	incl	%edi
	jmp	.L39
.L49:
	addl	%ecx, %ebp
	incl	%r11d
	jmp	.L36
.L48:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z9rotateCPUPfS_iiS_, .-_Z9rotateCPUPfS_iiS_
	.globl	_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_
	.type	_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_, @function
_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10rotMatFuncPfS_iiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L50:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_, .-_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_
	.globl	_Z10rotMatFuncPfS_iiS_
	.type	_Z10rotMatFuncPfS_iiS_, @function
_Z10rotMatFuncPfS_iiS_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_
	.cfi_endproc
.LFE2058:
	.size	_Z10rotMatFuncPfS_iiS_, .-_Z10rotMatFuncPfS_iiS_
	.section	.rodata.str1.1
.LC8:
	.string	"A ="
.LC9:
	.string	"Rotating matrices on CPU...\n"
.LC10:
	.string	"Matrix rotation over. Time taken on CPU: %5.5f\n"
.LC11:
	.string	"B2(CPU) ="
.LC12:
	.string	"error=%s"
.LC13:
	.string	"code=%d"
.LC14:
	.string	"Matrix B Copy from device to Host"
.LC16:
	.string	"Kernels correct!\n"
.LC17:
	.string	"Kernel logic wrong!\n"
.LC18:
	.string	"Finished addition on GPU. Time taken: %5.5f\n"
.LC19:
	.string	"Speedup: %5.5f\n"
.LC20:
	.string	"The rotated image(CPU) is: "
.LC21:
	.string	"The rotated image(GPU) is: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$104, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$1, %esi
	movl	$3240000, %edi
	call	calloc@PLT
	movl	$1, %esi
	movl	$3240000, %edi
	movq	%rax, %r12
	call	calloc@PLT
	movl	$1, %esi
	movl	$3240000, %edi
	movq	%rax, %rbp
	call	calloc@PLT
	movl	$1, %esi
	movl	$16, %edi
	movq	%rax, %rbx
	call	calloc@PLT
	movl	$900, %edx
	movl	$900, %esi
	movq	%r12, %rdi
	movq	%rax, %r13
	call	_Z11Fill_matrixPfii
	movl	$383, %eax
	movl	$900, %ecx
	movq	$1065353216, 8(%r13)
	salq	$55, %rax
	movl	$9, %r9d
	movl	$9, %r8d
	movq	%r12, %rsi
	movq	%rax, 0(%r13)
	leaq	.LC8(%rip), %rdi
	call	_Z12Print_matrixPKcPfiiii
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	%r13, %r8
	movl	$900, %ecx
	movq	%rbx, %rsi
	movl	$900, %edx
	movq	%r12, %rdi
	call	_Z9rotateCPUPfS_iiS_
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	%rsp, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$9, %r9d
	movl	$9, %r8d
	movl	$900, %ecx
	movl	$900, %edx
	movq	%rbx, %rsi
	leaq	.LC11(%rip), %rdi
	call	_Z12Print_matrixPKcPfiiii
	leaq	40(%rsp), %rdi
	movl	$3240000, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$3240000, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$16, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$3240000, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$3240000, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$16, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$137438953504, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	movq	56(%rsp), %r8
	movq	48(%rsp), %rsi
	movl	$900, %ecx
	movl	$900, %edx
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z10rotMatFuncPfS_iiS_PfS_iiS_
.L56:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L57
	call	cudaGetErrorString@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L58
.L57:
	xorl	%edx, %edx
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L58:
	call	cudaDeviceSynchronize@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	call	cudaThreadSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$3240000, %edx
	call	cudaMemcpy@PLT
	leaq	.LC14(%rip), %rsi
	movl	%eax, %edi
	call	_Z10checkError9cudaErrorPKc
	movss	.LC15(%rip), %xmm0
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	call	_Z20checkIfMatricesEqualPfS_f
	leaq	.LC16(%rip), %rsi
	testb	%al, %al
	jne	.L63
	leaq	.LC17(%rip), %rsi
.L63:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC19(%rip), %rsi
	movb	$1, %al
	movss	(%rsp), %xmm0
	divss	4(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	$9, %r9d
	movl	$9, %r8d
	movq	%rbx, %rsi
	movl	$900, %ecx
	movl	$900, %edx
	leaq	.LC20(%rip), %rdi
	call	_Z12Print_matrixPKcPfiiii
	movl	$9, %r9d
	movl	$9, %r8d
	movq	%rbp, %rsi
	movl	$900, %ecx
	movl	$900, %edx
	leaq	.LC21(%rip), %rdi
	call	_Z12Print_matrixPKcPfiiii
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$104, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z10rotMatFuncPfS_iiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10rotMatFuncPfS_iiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC15:
	.long	1229308160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* File:     mat_add.cu
 * Purpose:  Implement matrix addition on a gpu using cuda
 *
 * Output:   Result of matrix addition.  
 *
 * Notes:
 * 1.  There are m blocks with n threads each.
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include "cuPrintf.cuh"
//#include "cuPrintf.cu"
 //#include "utils/cuPrintf.cu"


/*---------------------------------------------------------------------
 * Kernel:   Mat_add
 * Purpose:  Implement matrix addition
 * In args:  A, B, m, n
 * Out arg:  C
 */

__global__ void rotMatFunc(float matIn[], 
                           float matOut[], 
                           int dimX, 
                           int dimY, 
                           float rotMat[]) {
//    int y = blockIdx.y;
///    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    if ( x >= dimX || y >= dimY) 
         return;
    //printf("x,y = %d %d, blockIdx.x,y= %d %d,  blockDim.x,y = %d %d, threadIdx.x,y= %d %d\n",
    //        x,y,      blockIdx.x,blockIdx.y,      blockDim.x,blockDim.y,     threadIdx.x,threadIdx.y);

   float xOut,yOut;
   float xIn, yIn;
   int iIn, jIn;
   float dimXf=(float)dimX, dimYf=(float)dimY;
   int  x0=dimX/2, y0=dimY/2;

//           xOut = (float)(x - x0)/dimXf;
//           yOut = (float)(y - y0)/dimYf;
           xOut = (float)(x - x0);
           yOut = (float)(y - y0);
           
           xIn = rotMat[0] * xOut + rotMat[1] * yOut;
           yIn = rotMat[2] * xOut + rotMat[3] * yOut;
           
//           iIn = int(xIn * dimXf + x0);
//           jIn = int(yIn * dimYf + y0);
           iIn = int(xIn + x0);
           jIn = int(yIn + y0);

           if ( iIn >= 0 && 
                iIn < dimX && 
                jIn >= 0 && 
                jIn < dimY) 
                {
                printf("x=%d y=%d iIn=%d jIn=%d in=%d, out=%d\n",x, y, iIn, jIn, iIn*dimY+jIn,x*dimY+y);
                matOut[x*dimY+y] = matIn[iIn*dimY+jIn];
                }

/*
    int indexOfMatrixOut = y + x * dimY;
    int  x0=dimX/2, y0=dimY/2;//this may be passed

   float xOut,yOut;
   float xIn, yIn;
   int iIn, jIn;
   float dimXf=(float)dimX, dimYf=(float)dimY;
   xOut = (float)(x - x0)/dimXf;
   yOut = (float)(y - y0)/dimYf;
   //printf("x=%d y=%d x0=%d dimXf=%f xOut=%f yOut=%f\n",x, y, x0, dimXf, xOut, yOut);
   xIn = rotMat[0] * xOut + rotMat[1] * yOut;
   yIn = rotMat[2] * xOut + rotMat[3] * yOut;
   //printf("x =%d y=%d xIn=%f yIn=%f\n",x, y, xIn, yIn);
   iIn = int(xIn * dimXf + x0);
   jIn = int(yIn * dimYf + y0);
   int indexOfMatrixIn = jIn + iIn * dimY;

   if ( iIn >= 0 && 
        iIn < dimX && 
        jIn >= 0 && 
        jIn < dimY) 
        {
            matOut[indexOfMatrixOut] = matIn[indexOfMatrixIn];
         printf("x=%d y=%d in=%d, out=%d vI=%f vO=%f\n",x, y, indexOfMatrixIn,indexOfMatrixOut, 
                 matIn[indexOfMatrixIn], matOut[indexOfMatrixOut]);
         }
*/   
}  /* Mat_add */


/*---------------------------------------------------------------------
 * Function:  Fill_matrix
 * Purpose:   Fill an m x n matrix with random values
 * In args:   m, n
 * Out arg:   A
 */
void Fill_matrix(float A[], int dimX, int dimY) {
   int i, j;
//numVec, dimVec
   for (i = 0; i < dimX; i++)
      for (j = 0; j < dimY; j++)
          if(i==j )//or (i+j)==(dimX+1))
            A[i*dimY+j]=1.0f;
          else
            A[i*dimY+j]=0.0f;
}  /* Read_matrix */


/*---------------------------------------------------------------------
 * Function:  Print_matrix
 * Purpose:   Print an m x n matrix to stdout
 * In args:   title, A, m, n
 */
void Print_matrix(const char title[], float A[], int numVec, int dimVec, int m, int n) {
   int i, j;
   //numVec, dimVec
   printf("%s\n", title);
   for (i = 0; i < m; i++) {
      for (j = 0; j < n; j++)
         printf("%.2f ", A[i*dimVec+j]);
      printf("\n");
   }  
}  /* Print_matrix */

void checkError(hipError_t error, const char function[])
{

        if(error != hipSuccess)
        {
                printf("\"%s\" has a problem with error code %d and desc: %s\n", function, error, hipGetErrorString(error));
                exit(-1);
        }
}

bool checkIfMatricesEqual(float * mat1, float * mat2, float matSize)
{
    int i = 0;
    for( ; i < matSize; i++)
       if(mat1[i] != mat2[i]){
           printf("values different for i: %d\n", i);
		   printf("mat1[i] = %d, mat2[i] = %d\n", mat1[i], mat2[i]);		   
		   return false;
	   }

    return true;
}
void rotateCPU(float matIn[], 
               float matOut[], int dimX, int dimY,
               float rotMat[])
{
   //float fX0,fY0;
   int  x0=dimX/2, y0=dimY/2;

   //fX0 = (float)iX0;
   //fY0 = (float)iY0;
   float xOut,yOut;
   float xIn, yIn;
   int iIn, jIn;
   float dimXf=(float)dimX, dimYf=(float)dimY;
   for(int x = 0 ; x < dimX; ++x)
       for(int y = 0 ; y < dimY; ++y){
           xOut = (float)(x - x0)/dimXf;
           yOut = (float)(y - y0)/dimYf;
           
           xIn = rotMat[0] * xOut + rotMat[1] * yOut;
           yIn = rotMat[2] * xOut + rotMat[3] * yOut;
           
           iIn = int(xIn * dimXf + x0);
           jIn = int(yIn * dimYf + y0);

           if ( iIn >= 0 && 
                iIn < dimX && 
                jIn >= 0 && 
                jIn < dimY) 

                matOut[x*dimY+y] = matIn[iIn*dimY+jIn];
           }

}
/* Host code */
int main(int argc, char* argv[]) {
   size_t dimX = 900;//mat size
   size_t dimY = 900;
   size_t gridX = 9;//mat size
   size_t gridY = 9;

   // variables for threads per block, number of blocks.
   int threadsPerBlock = 32;//, blocksInGrid = 0;
   //threadsPerBlock = min(_dimY, _dimY);
   //create cuda event variables
   hipEvent_t hostStart, hostStop, deviceStart, deviceStop;
   float timeDifferenceOnHost, timeDifferenceOnDevice;
   //initialize cuda timing variables
   hipEventCreate(&hostStart);
   hipEventCreate(&hostStop);
   hipEventCreate(&deviceStart);
   hipEventCreate(&deviceStop);

   float *h_A, *h_B, *h_B2, *h_rotMat;//PC
   float *d_A, *d_B, *d_rotMat;//GPU
   size_t size, matrixSize;

   /* Get size of matrices */

   matrixSize = dimX*dimY;
   size = matrixSize*sizeof(float);

   h_A = (float*) calloc(size,1);
   h_B = (float*) calloc(size,1);
   h_B2 = (float*) calloc(size,1);
   h_rotMat = (float*) calloc(4*sizeof(float),1);

   Fill_matrix(h_A, dimX, dimY);

   //init rot Matrix
   h_rotMat[0] = 0.f;
   h_rotMat[1] = -1.f;
   //h_rotMat[0] = 0.936f;
   //h_rotMat[1] = 0.352f;
   h_rotMat[2] = -h_rotMat[1];
   h_rotMat[3] =  h_rotMat[0];

   Print_matrix("A =", h_A, dimX, dimY, 9, 9);
   printf("Rotating matrices on CPU...\n");
   hipEventRecord(hostStart, 0);
   //rotate matrix using CPU
   rotateCPU(h_A ,h_B2, dimX, dimY, h_rotMat);
   //////////
   hipEventRecord(hostStop, 0);
   hipEventElapsedTime(&timeDifferenceOnHost, hostStart, hostStop);
   printf("Matrix rotation over. Time taken on CPU: %5.5f\n",     
          timeDifferenceOnHost);
   Print_matrix("B2(CPU) =", h_B2, dimX, dimY, 9, 9);

   /* Allocate matrices in device memory */
   hipMalloc(&d_A, size);
   hipMalloc(&d_B, size);
   hipMalloc(&d_rotMat, 4*sizeof(float));

   /* Copy matrices from host memory to device memory */
   hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
   hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
   hipMemcpy(d_rotMat, h_rotMat, 4*sizeof(float), hipMemcpyHostToDevice);

   //create a proper grid block using dim3

   /* Invoke kernel using dimX * dimY thread blocks, each of    */
   /* which contains threadsPerBlock threads                        */
   
   dim3 block(threadsPerBlock, threadsPerBlock);
   dim3 grid( (gridX+threadsPerBlock-1)/threadsPerBlock, 
              (gridY+threadsPerBlock-1)/threadsPerBlock );
   hipEventRecord(deviceStart, 0);
   rotMatFunc<<<grid, block>>>(d_A, d_B, dimX, dimY, d_rotMat);

   hipError_t code=hipGetLastError();
   if (code)
       printf("error=%s",hipGetErrorString(code));
   else
       printf("code=%d",code);
   hipDeviceSynchronize();  
   hipEventRecord(deviceStop, 0);

   /* Wait for the kernel to complete */
   hipDeviceSynchronize();
   hipEventElapsedTime(&timeDifferenceOnDevice, deviceStart, deviceStop);

   /* Copy result from device memory to host memory */
   checkError(hipMemcpy(h_B, d_B, size, hipMemcpyDeviceToHost), "Matrix B Copy from device to Host");
	
   if(checkIfMatricesEqual(h_B, h_B2, matrixSize))
      printf("Kernels correct!\n");
   else
      printf("Kernel logic wrong!\n");
	
   printf("Finished addition on GPU. Time taken: %5.5f\n", timeDifferenceOnDevice);   
   printf("Speedup: %5.5f\n", (float)timeDifferenceOnHost/timeDifferenceOnDevice);

   Print_matrix("The rotated image(CPU) is: ", h_B2, dimX, dimY, 9, 9);
   Print_matrix("The rotated image(GPU) is: ", h_B, dimX, dimY, 9, 9);

   /* Free device memory */
   hipFree(d_A);
   hipFree(d_B);

   /* Free host memory */
   free(h_A);
   free(h_B);
   free(h_B2);

   return 0;
}  /* main */

	.text
	.file	"matAdd.hip"
	.globl	_Z25__device_stub__rotMatFuncPfS_iiS_ # -- Begin function _Z25__device_stub__rotMatFuncPfS_iiS_
	.type	_Z25__device_stub__rotMatFuncPfS_iiS_,@function
_Z25__device_stub__rotMatFuncPfS_iiS_:  # @_Z25__device_stub__rotMatFuncPfS_iiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10rotMatFuncPfS_iiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__rotMatFuncPfS_iiS_, .Lfunc_end0-_Z25__device_stub__rotMatFuncPfS_iiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11Fill_matrixPfii             # -- Begin function _Z11Fill_matrixPfii
	.type	_Z11Fill_matrixPfii,@function
_Z11Fill_matrixPfii:                    # @_Z11Fill_matrixPfii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_10
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%esi, %eax
	movl	%edx, %ecx
	xorl	%esi, %esi
	xorl	%r8d, %r8d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%edx, %edx
	jle	.LBB1_8
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%esi, %r9d
	leaq	(%rdi,%r9,4), %r9
	movl	%r8d, %r10d
	imull	%edx, %r10d
	leaq	(%rdi,%r8,4), %r11
	xorl	%ebx, %ebx
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%rbx, %r8
	jne	.LBB1_6
# %bb.5:                                #   in Loop: Header=BB1_4 Depth=2
	movl	$1065353216, (%r11,%r10,4)      # imm = 0x3F800000
	jmp	.LBB1_7
.LBB1_6:                                #   in Loop: Header=BB1_4 Depth=2
	movl	$0, (%r9,%rbx,4)
.LBB1_7:                                #   in Loop: Header=BB1_4 Depth=2
	incq	%rbx
	cmpq	%rbx, %rcx
	jne	.LBB1_4
.LBB1_8:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r8
	addl	%edx, %esi
	cmpq	%rax, %r8
	jne	.LBB1_2
# %bb.9:
	popq	%rbx
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
.LBB1_10:                               # %._crit_edge19
	retq
.Lfunc_end1:
	.size	_Z11Fill_matrixPfii, .Lfunc_end1-_Z11Fill_matrixPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z12Print_matrixPKcPfiiii       # -- Begin function _Z12Print_matrixPKcPfiiii
	.type	_Z12Print_matrixPKcPfiiii,@function
_Z12Print_matrixPKcPfiiii:              # @_Z12Print_matrixPKcPfiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 4(%rsp)                   # 4-byte Spill
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movq	%rsi, %r14
	callq	puts@PLT
	testl	%ebp, %ebp
	jle	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	movslq	%r15d, %r15
	movl	%ebp, %r12d
	movl	4(%rsp), %r13d                  # 4-byte Reload
	shlq	$2, %r15
	xorl	%ebp, %ebp
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	cmpl	$0, 4(%rsp)                     # 4-byte Folded Reload
	jle	.LBB2_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	xorl	%ebx, %ebx
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%rbx,4), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	%rbx, %r13
	jne	.LBB2_4
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%rbp
	addq	%r15, %r14
	cmpq	%r12, %rbp
	jne	.LBB2_2
.LBB2_6:                                # %._crit_edge13
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z12Print_matrixPKcPfiiii, .Lfunc_end2-_Z12Print_matrixPKcPfiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10checkError10hipError_tPKc   # -- Begin function _Z10checkError10hipError_tPKc
	.type	_Z10checkError10hipError_tPKc,@function
_Z10checkError10hipError_tPKc:          # @_Z10checkError10hipError_tPKc
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB3_2
# %bb.1:
	retq
.LBB3_2:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	callq	hipGetErrorString
	movl	$.L.str.3, %edi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end3:
	.size	_Z10checkError10hipError_tPKc, .Lfunc_end3-_Z10checkError10hipError_tPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z20checkIfMatricesEqualPfS_f   # -- Begin function _Z20checkIfMatricesEqualPfS_f
	.type	_Z20checkIfMatricesEqualPfS_f,@function
_Z20checkIfMatricesEqualPfS_f:          # @_Z20checkIfMatricesEqualPfS_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	$1, %bl
	xorps	%xmm1, %xmm1
	ucomiss	%xmm1, %xmm0
	jbe	.LBB4_5
# %bb.1:                                # %.lr.ph.preheader
	movq	%rsi, %r14
	movq	%rdi, %r15
	xorl	%r12d, %r12d
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r15,%r12,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	ucomiss	(%r14,%r12,4), %xmm1
	jne	.LBB4_3
	jp	.LBB4_3
# %bb.4:                                #   in Loop: Header=BB4_2 Depth=1
	incq	%r12
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r12d, %xmm1
	ucomiss	%xmm1, %xmm0
	ja	.LBB4_2
	jmp	.LBB4_5
.LBB4_3:
	xorl	%ebx, %ebx
	movl	$.L.str.4, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r12,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%r14,%r12,4), %xmm1
	movl	$.L.str.5, %edi
	movb	$2, %al
	callq	printf
.LBB4_5:                                # %.loopexit
	movl	%ebx, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z20checkIfMatricesEqualPfS_f, .Lfunc_end4-_Z20checkIfMatricesEqualPfS_f
	.cfi_endproc
                                        # -- End function
	.globl	_Z9rotateCPUPfS_iiS_            # -- Begin function _Z9rotateCPUPfS_iiS_
	.type	_Z9rotateCPUPfS_iiS_,@function
_Z9rotateCPUPfS_iiS_:                   # @_Z9rotateCPUPfS_iiS_
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB5_12
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cvtsi2ss	%edx, %xmm0
	cvtsi2ss	%ecx, %xmm1
	movl	%ecx, %eax
	movl	%ecx, %r9d
	shrl	$31, %r9d
	addl	%ecx, %r9d
	movl	%edx, %r10d
	shrl	%r10d
	cvtsi2ss	%r10d, %xmm2
	sarl	%r9d
	cvtsi2ss	%r9d, %xmm3
	negl	%r9d
	movl	%edx, %r11d
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB5_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_4 Depth 2
	testl	%ecx, %ecx
	jle	.LBB5_10
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB5_2 Depth=1
	movl	%r14d, %ebp
	subl	%r10d, %ebp
	xorps	%xmm4, %xmm4
	cvtsi2ss	%ebp, %xmm4
	movl	%ebx, %r15d
	leaq	(%rsi,%r15,4), %r15
	divss	%xmm0, %xmm4
	xorl	%r12d, %r12d
.LBB5_4:                                #   Parent Loop BB5_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%r9,%r12), %ebp
	xorps	%xmm5, %xmm5
	cvtsi2ss	%ebp, %xmm5
	divss	%xmm1, %xmm5
	movss	(%r8), %xmm6                    # xmm6 = mem[0],zero,zero,zero
	mulss	%xmm4, %xmm6
	movss	4(%r8), %xmm7                   # xmm7 = mem[0],zero,zero,zero
	mulss	%xmm5, %xmm7
	addss	%xmm6, %xmm7
	mulss	%xmm0, %xmm7
	addss	%xmm2, %xmm7
	cvttss2si	%xmm7, %ebp
	testl	%ebp, %ebp
	js	.LBB5_9
# %bb.5:                                #   in Loop: Header=BB5_4 Depth=2
	cmpl	%edx, %ebp
	jge	.LBB5_9
# %bb.6:                                #   in Loop: Header=BB5_4 Depth=2
	movss	8(%r8), %xmm6                   # xmm6 = mem[0],zero,zero,zero
	mulss	%xmm4, %xmm6
	mulss	12(%r8), %xmm5
	addss	%xmm6, %xmm5
	mulss	%xmm1, %xmm5
	addss	%xmm3, %xmm5
	cvttss2si	%xmm5, %r13d
	testl	%r13d, %r13d
	js	.LBB5_9
# %bb.7:                                #   in Loop: Header=BB5_4 Depth=2
	cmpl	%eax, %r13d
	jge	.LBB5_9
# %bb.8:                                #   in Loop: Header=BB5_4 Depth=2
	imull	%ecx, %ebp
	addl	%r13d, %ebp
	movslq	%ebp, %r13
	movss	(%rdi,%r13,4), %xmm5            # xmm5 = mem[0],zero,zero,zero
	movss	%xmm5, (%r15,%r12,4)
.LBB5_9:                                #   in Loop: Header=BB5_4 Depth=2
	incq	%r12
	cmpq	%r12, %rax
	jne	.LBB5_4
.LBB5_10:                               # %._crit_edge
                                        #   in Loop: Header=BB5_2 Depth=1
	incq	%r14
	addl	%ecx, %ebx
	cmpq	%r11, %r14
	jne	.LBB5_2
# %bb.11:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB5_12:                               # %._crit_edge52
	retq
.Lfunc_end5:
	.size	_Z9rotateCPUPfS_iiS_, .Lfunc_end5-_Z9rotateCPUPfS_iiS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI6_0:
	.long	0x4945c100                      # float 8.1E+5
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	56(%rsp), %rdi
	callq	hipEventCreate
	leaq	48(%rsp), %rdi
	callq	hipEventCreate
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	movl	$3240000, %edi                  # imm = 0x317040
	movl	$1, %esi
	callq	calloc
	movq	%rax, %rbx
	movl	$3240000, %edi                  # imm = 0x317040
	movl	$1, %esi
	callq	calloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$3240000, %edi                  # imm = 0x317040
	movl	$1, %esi
	callq	calloc
	movq	%rax, %r15
	movl	$16, %edi
	movl	$1, %esi
	callq	calloc
	movq	%rax, %r12
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB6_1:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_2 Depth 2
	imulq	$900, %rax, %rdx                # imm = 0x384
	leaq	(%rbx,%rax,4), %rsi
	xorl	%edi, %edi
.LBB6_2:                                #   Parent Loop BB6_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%rdi, %rax
	jne	.LBB6_4
# %bb.3:                                #   in Loop: Header=BB6_2 Depth=2
	movl	$1065353216, (%rsi,%rdx,4)      # imm = 0x3F800000
	jmp	.LBB6_5
.LBB6_4:                                #   in Loop: Header=BB6_2 Depth=2
	movl	$0, (%rcx,%rdi,4)
.LBB6_5:                                #   in Loop: Header=BB6_2 Depth=2
	incq	%rdi
	cmpq	$900, %rdi                      # imm = 0x384
	jne	.LBB6_2
# %bb.6:                                # %._crit_edge.i
                                        #   in Loop: Header=BB6_1 Depth=1
	incq	%rax
	addq	$3600, %rcx                     # imm = 0xE10
	cmpq	$900, %rax                      # imm = 0x384
	jne	.LBB6_1
# %bb.7:                                # %_Z11Fill_matrixPfii.exit
	movabsq	$4575657224621260800, %rax      # imm = 0x3F800000BF800000
	movq	%rax, 4(%r12)
	movl	$.L.str.6, %edi
	movq	%rbx, %rsi
	movl	$900, %ecx                      # imm = 0x384
	movl	$9, %r8d
	movl	$9, %r9d
	callq	_Z12Print_matrixPKcPfiiii
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	$900, %edx                      # imm = 0x384
	movl	$900, %ecx                      # imm = 0x384
	movq	%r12, %r8
	callq	_Z9rotateCPUPfS_iiS_
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdx
	leaq	20(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r13), %xmm0
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.9, %edi
	movq	%r15, %rsi
	movl	$900, %ecx                      # imm = 0x384
	movl	$9, %r8d
	movl	$9, %r9d
	callq	_Z12Print_matrixPKcPfiiii
	leaq	24(%rsp), %r13
	movl	$3240000, %esi                  # imm = 0x317040
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$3240000, %esi                  # imm = 0x317040
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	72(%rsp), %r14
	movl	$16, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$3240000, %edx                  # imm = 0x317040
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$3240000, %edx                  # imm = 0x317040
	movq	64(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movl	$16, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_9
# %bb.8:
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	72(%rsp), %r8
	movl	$900, %edx                      # imm = 0x384
	movl	$900, %ecx                      # imm = 0x384
	callq	_Z25__device_stub__rotMatFuncPfS_iiS_
.LBB6_9:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB6_11
# %bb.10:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB6_12
.LBB6_11:
	movl	$.L.str.11, %edi
	xorl	%esi, %esi
	xorl	%eax, %eax
	callq	printf
.LBB6_12:
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	callq	hipDeviceSynchronize
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	84(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movq	8(%rsp), %rsi
	movl	$3240000, %edx                  # imm = 0x317040
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.12, %esi
	movl	%eax, %edi
	callq	_Z10checkError10hipError_tPKc
	movss	.LCPI6_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	_Z20checkIfMatricesEqualPfS_f
	movl	$.Lstr.2, %ecx
	movl	$.Lstr.1, %edi
	testb	%al, %al
	cmovneq	%rcx, %rdi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.15, %edi
	movb	$1, %al
	callq	printf
	movss	20(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	(%r12), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.16, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.17, %edi
	movq	%r15, %rsi
	movl	$900, %ecx                      # imm = 0x384
	movl	$9, %r8d
	movl	$9, %r9d
	callq	_Z12Print_matrixPKcPfiiii
	movl	$.L.str.18, %edi
	movq	%r13, %rsi
	movl	$900, %ecx                      # imm = 0x384
	movl	$9, %r8d
	movl	$9, %r9d
	callq	_Z12Print_matrixPKcPfiiii
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10rotMatFuncPfS_iiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10rotMatFuncPfS_iiS_,@object  # @_Z10rotMatFuncPfS_iiS_
	.section	.rodata,"a",@progbits
	.globl	_Z10rotMatFuncPfS_iiS_
	.p2align	3, 0x0
_Z10rotMatFuncPfS_iiS_:
	.quad	_Z25__device_stub__rotMatFuncPfS_iiS_
	.size	_Z10rotMatFuncPfS_iiS_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%.2f "
	.size	.L.str.1, 6

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\"%s\" has a problem with error code %d and desc: %s\n"
	.size	.L.str.3, 52

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"values different for i: %d\n"
	.size	.L.str.4, 28

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"mat1[i] = %d, mat2[i] = %d\n"
	.size	.L.str.5, 28

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"A ="
	.size	.L.str.6, 4

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Matrix rotation over. Time taken on CPU: %5.5f\n"
	.size	.L.str.8, 48

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"B2(CPU) ="
	.size	.L.str.9, 10

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"error=%s"
	.size	.L.str.10, 9

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"code=%d"
	.size	.L.str.11, 8

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Matrix B Copy from device to Host"
	.size	.L.str.12, 34

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"Finished addition on GPU. Time taken: %5.5f\n"
	.size	.L.str.15, 45

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Speedup: %5.5f\n"
	.size	.L.str.16, 16

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"The rotated image(CPU) is: "
	.size	.L.str.17, 28

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"The rotated image(GPU) is: "
	.size	.L.str.18, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10rotMatFuncPfS_iiS_"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Rotating matrices on CPU..."
	.size	.Lstr, 28

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Kernel logic wrong!"
	.size	.Lstr.1, 20

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Kernels correct!"
	.size	.Lstr.2, 17

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__rotMatFuncPfS_iiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10rotMatFuncPfS_iiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10rotMatFuncPfS_iiS_  ; -- Begin function _Z10rotMatFuncPfS_iiS_
	.globl	_Z10rotMatFuncPfS_iiS_
	.p2align	8
	.type	_Z10rotMatFuncPfS_iiS_,@function
_Z10rotMatFuncPfS_iiS_:                 ; @_Z10rotMatFuncPfS_iiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_add_u32 s10, s0, 32
	s_addc_u32 s11, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[37:38], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s8, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s9, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_309
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[4:7], s[2:3], 0x0
	s_lshr_b32 s2, s9, 31
	s_lshr_b32 s3, s8, 31
	s_add_i32 s2, s9, s2
	s_add_i32 s3, s8, s3
	s_ashr_i32 s2, s2, 1
	s_ashr_i32 s3, s3, 1
	v_subrev_nc_u32_e32 v0, s2, v2
	v_subrev_nc_u32_e32 v3, s3, v37
	v_cvt_f32_i32_e32 v4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v1, v0
	v_cvt_f32_i32_e32 v0, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, s5, v1
	v_fmac_f32_e32 v3, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	v_cvt_i32_f32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_309
; %bb.2:
	v_mul_f32_e32 v1, s7, v1
	v_cmp_gt_i32_e32 vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s6, v0
	v_cvt_f32_i32_e32 v0, s2
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v8, v0
	v_cmp_gt_i32_e64 s2, s9, v8
	v_cmp_lt_i32_e64 s3, -1, v8
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_309
; %bb.3:
	s_load_b64 s[4:5], s[10:11], 0x50
	v_mbcnt_lo_u32_b32 v38, -1, 0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v38
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v13
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_9
; %bb.4:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[11:12], v3, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[6:7], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v11
	v_and_b32_e32 v1, v1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[9:10], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[11:12]
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB0_6:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[4:5] offset:40
	global_load_b64 v[9:10], v3, s[4:5]
	v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v11, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[9:10]
	v_and_b32_e32 v4, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[9:10], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %Flow634
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_8:                                ; %Flow636
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_9:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v14, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[3:4], v14, s[4:5] offset:40
	global_load_b128 v[9:12], v14, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v16, v14
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v9, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v10, vcc_lo
	v_dual_mov_b32 v17, 2 :: v_dual_mov_b32 v18, 1
	global_store_b128 v[0:1], v[15:18], off offset:8
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[13:14]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v12, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s19, s16
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v13, 33 :: v_dual_mov_b32 v16, v14
	v_dual_mov_b32 v15, v14 :: v_dual_mov_b32 v20, s19
	v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v18, s17
	v_mov_b32_e32 v17, s16
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[17:20], off offset:32
	global_store_b128 v[0:1], v[17:20], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_19
; %bb.12:
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v14, s7
	s_mov_b32 s11, exec_lo
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v6, s[4:5] offset:40
	v_mov_b32_e32 v13, s6
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s6, v3
	v_and_b32_e32 v4, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_15
; %bb.13:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s13, 0
.LBB0_14:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_14
.LBB0_15:                               ; %Flow632
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v7, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v6, s13, 0
	global_load_b64 v[3:4], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_17
; %bb.16:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_19
; %bb.18:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_19:                               ; %Flow633
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v3, vcc_lo, v9, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_20:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_22:                               ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_25
.LBB0_24:                               ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s3, -1
.LBB0_25:                               ; %Flow627
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_20
; %bb.26:
	global_load_b64 v[9:10], v[0:1], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_30
; %bb.27:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[6:7], v3, s[4:5] offset:24 glc
	global_load_b64 v[13:14], v3, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v4, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v4
	v_and_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v11, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v13, v0
	v_mov_b32_e32 v13, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v7
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_30
; %bb.28:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s2, 0
.LBB0_29:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[13:14]
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v13, v6
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_29
.LBB0_30:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_116
; %bb.31:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v12, v10 :: v_dual_and_b32 v39, 2, v9
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v16, 1
	v_and_b32_e32 v11, -3, v9
	v_mov_b32_e32 v15, 2
	s_mov_b64 s[10:11], 39
.LBB0_32:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_35 Depth 2
                                        ;     Child Loop BB0_42 Depth 2
                                        ;     Child Loop BB0_50 Depth 2
                                        ;     Child Loop BB0_58 Depth 2
                                        ;     Child Loop BB0_66 Depth 2
                                        ;     Child Loop BB0_74 Depth 2
                                        ;     Child Loop BB0_82 Depth 2
                                        ;     Child Loop BB0_90 Depth 2
                                        ;     Child Loop BB0_98 Depth 2
                                        ;     Child Loop BB0_104 Depth 2
                                        ;     Child Loop BB0_113 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s2, s[10:11], 56
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr18
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s12, s10, 56
	s_cselect_b32 s13, s11, 0
	s_cmp_gt_u32 s12, 7
	s_mov_b32 s2, -1
	s_cbranch_scc1 .LBB0_37
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc1 .LBB0_36
; %bb.34:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_lshl_b64 s[2:3], s[12:13], 3
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[6:7]
.LBB0_35:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v1, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s2, s14
	v_or_b32_e32 v19, v3, v19
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB0_35
.LBB0_36:                               ; %Flow603
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s18, 0
.LBB0_37:                               ; %Flow605
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b64 s[2:3], s[6:7]
	s_cbranch_vccnz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[19:20], v1, s[6:7]
	s_add_i32 s18, s12, -8
	s_add_u32 s2, s6, 8
	s_addc_u32 s3, s7, 0
.LBB0_39:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_44
; %bb.40:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_43
; %bb.41:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_42:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB0_42
.LBB0_43:                               ; %Flow598
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s8, 0
	s_branch .LBB0_45
.LBB0_44:                               ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr8
.LBB0_45:                               ; %Flow600
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_47
; %bb.46:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[21:22], v1, s[2:3]
	s_add_i32 s8, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_47:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_cmp_gt_u32 s8, 7
	s_cbranch_scc1 .LBB0_52
; %bb.48:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_51
; %bb.49:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_50:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s2, s16
	s_addc_u32 s19, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[18:19]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s8, s16
	v_or_b32_e32 v23, v3, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB0_50
.LBB0_51:                               ; %Flow593
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_53
.LBB0_52:                               ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr18
.LBB0_53:                               ; %Flow595
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[23:24], v1, s[2:3]
	s_add_i32 s18, s8, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_55:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_60
; %bb.56:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_59
; %bb.57:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_58:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v25, v3, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v4, v26
	s_cbranch_scc1 .LBB0_58
.LBB0_59:                               ; %Flow588
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s8, 0
	s_branch .LBB0_61
.LBB0_60:                               ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr8
.LBB0_61:                               ; %Flow590
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_63
; %bb.62:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[25:26], v1, s[2:3]
	s_add_i32 s8, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_63:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_cmp_gt_u32 s8, 7
	s_cbranch_scc1 .LBB0_68
; %bb.64:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_67
; %bb.65:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_66:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s2, s16
	s_addc_u32 s19, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[18:19]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s8, s16
	v_or_b32_e32 v27, v3, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v28, v4, v28
	s_cbranch_scc1 .LBB0_66
.LBB0_67:                               ; %Flow583
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_69
.LBB0_68:                               ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr18
.LBB0_69:                               ; %Flow585
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[27:28], v1, s[2:3]
	s_add_i32 s18, s8, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_71:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_76
; %bb.72:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v29, 0
	v_mov_b32_e32 v30, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_75
; %bb.73:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_74:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v29, v3, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v30, v4, v30
	s_cbranch_scc1 .LBB0_74
.LBB0_75:                               ; %Flow578
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s8, 0
	s_branch .LBB0_77
.LBB0_76:                               ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr29_vgpr30
                                        ; implicit-def: $sgpr8
.LBB0_77:                               ; %Flow580
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[29:30], v1, s[2:3]
	s_add_i32 s8, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_79:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_cmp_gt_u32 s8, 7
	s_cbranch_scc1 .LBB0_84
; %bb.80:                               ;   in Loop: Header=BB0_32 Depth=1
	v_mov_b32_e32 v31, 0
	v_mov_b32_e32 v32, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_83
; %bb.81:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[2:3]
.LBB0_82:                               ; %.preheader.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v1, s[16:17]
	s_add_i32 s8, s8, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[0:1]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s8, 0
	v_or_b32_e32 v31, v3, v31
	v_or_b32_e32 v32, v4, v32
	s_cbranch_scc1 .LBB0_82
.LBB0_83:                               ; %Flow573
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s8, 0
	s_branch .LBB0_85
.LBB0_84:                               ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s8, -1
.LBB0_85:                               ; %Flow575
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[31:32], v1, s[2:3]
.LBB0_87:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	v_dual_mov_b32 v0, v38 :: v_dual_mov_b32 v3, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v0
	v_mov_b32_e32 v4, 0
	v_cmp_eq_u32_e64 s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_93
; %bb.88:                               ;   in Loop: Header=BB0_32 Depth=1
	global_load_b64 v[35:36], v1, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v1, s[4:5] offset:40
	global_load_b64 v[6:7], v1, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v36
	v_and_b32_e32 v3, v3, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	global_load_b64 v[33:34], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[33:36], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[35:36]
	s_cbranch_execz .LBB0_92
; %bb.89:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s14, 0
.LBB0_90:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v1, s[4:5] offset:40
	global_load_b64 v[13:14], v1, s[4:5]
	v_dual_mov_b32 v36, v4 :: v_dual_mov_b32 v35, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v35
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v6, 24, v[13:14]
	v_and_b32_e32 v13, v7, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v6
	global_load_b64 v[33:34], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[33:36], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[35:36]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_90
; %bb.91:                               ; %Flow568
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_92:                               ; %Flow570
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_93:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	global_load_b64 v[6:7], v1, s[4:5] offset:40
	global_load_b128 v[33:36], v1, s[4:5]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s19, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v6
	v_readfirstlane_b32 s17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[14:15], s[16:17]
	s_mul_i32 s3, s17, 24
	s_mul_hi_u32 s8, s16, 24
	s_mul_i32 s18, s16, 24
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB0_95
; %bb.94:                               ;   in Loop: Header=BB0_32 Depth=1
	v_dual_mov_b32 v13, s19 :: v_dual_mov_b32 v14, v1
	s_add_i32 s19, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v33, s18
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v34, vcc_lo
	global_store_b128 v[3:4], v[13:16], off offset:8
.LBB0_95:                               ;   in Loop: Header=BB0_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_cmp_gt_u64_e64 vcc_lo, s[10:11], 56
	v_or_b32_e32 v3, 0, v12
	v_or_b32_e32 v4, v11, v39
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s19, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s19, s19, 28
	v_cndmask_b32_e32 v18, v3, v12, vcc_lo
	v_cndmask_b32_e32 v6, v4, v11, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v35, s16
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v36, vcc_lo
	s_and_b32 s19, s19, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v0, v3
	v_and_or_b32 v17, 0xffffff1f, v6, s19
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[17:20], off
	global_store_b128 v[3:4], v[21:24], off offset:16
	global_store_b128 v[3:4], v[25:28], off offset:32
	global_store_b128 v[3:4], v[29:32], off offset:48
	s_and_saveexec_b32 s16, s2
	s_cbranch_execz .LBB0_103
; %bb.96:                               ;   in Loop: Header=BB0_32 Depth=1
	s_clause 0x1
	global_load_b64 v[19:20], v1, s[4:5] offset:32 glc
	global_load_b64 v[6:7], v1, s[4:5] offset:40
	v_dual_mov_b32 v17, s14 :: v_dual_mov_b32 v18, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v6
	v_readfirstlane_b32 s21, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[14:15]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s19, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s19, s19, s17
	v_add_co_u32 v6, vcc_lo, v33, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v34, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[6:7], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v1, v[17:20], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_99
; %bb.97:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s19, 0
.LBB0_98:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15
	s_sleep 1
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v1, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s19, vcc_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_98
.LBB0_99:                               ; %Flow566
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[6:7], v1, s[4:5] offset:16
	s_mov_b32 s19, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v0, s19, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_101
; %bb.100:                              ;   in Loop: Header=BB0_32 Depth=1
	s_bcnt1_i32_b32 s19, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s19
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[6:7], v[0:1], off offset:8
.LBB0_101:                              ;   in Loop: Header=BB0_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_32 Depth=1
	global_load_b32 v0, v[6:7], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[0:1], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_103:                              ; %Flow567
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s8, s8, s3
	v_add_co_u32 v0, vcc_lo, v33, s18
	v_add_co_ci_u32_e32 v7, vcc_lo, s8, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB0_104:                              ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_104 Depth=2
	global_load_b32 v0, v[6:7], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_106:                              ;   in Loop: Header=BB0_104 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v0
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_104 Depth=2
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_109
.LBB0_108:                              ;   in Loop: Header=BB0_104 Depth=2
	s_mov_b32 s3, -1
.LBB0_109:                              ; %Flow561
                                        ;   in Loop: Header=BB0_104 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_104
; %bb.110:                              ;   in Loop: Header=BB0_32 Depth=1
	global_load_b128 v[11:14], v[3:4], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_114
; %bb.111:                              ;   in Loop: Header=BB0_32 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v1, s[4:5] offset:40
	global_load_b64 v[6:7], v1, s[4:5] offset:24 glc
	global_load_b64 v[13:14], v1, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v20, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v0, s14
	v_add_co_ci_u32_e32 v18, vcc_lo, s15, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[17:18]
	v_dual_cndmask_b32 v18, v18, v19 :: v_dual_cndmask_b32 v17, v17, v0
	v_mov_b32_e32 v19, v6
	v_and_b32_e32 v0, v18, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v17, v3
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v0, vcc_lo
	global_store_b64 v[3:4], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[19:20], v1, v[17:20], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[19:20], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_114
; %bb.112:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_mov_b32 s2, 0
.LBB0_113:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_32 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v1, v[17:20], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[19:20]
	v_dual_mov_b32 v20, v7 :: v_dual_mov_b32 v19, v6
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_113
.LBB0_114:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_sub_u32 s10, s10, s12
	s_subb_u32 s11, s11, s13
	s_add_u32 s6, s6, s12
	s_addc_u32 s7, s7, s13
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_32
; %bb.115:                              ; %Flow606
	s_mov_b32 s2, 0
	s_branch .LBB0_117
.LBB0_116:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_117:                              ; %Flow621
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_146
; %bb.118:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v11, v38 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v11
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s2, s2, v11
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_124
; %bb.119:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[14:15], v3, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[6:7], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v14
	v_and_b32_e32 v1, v1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[12:13], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[14:15]
	s_cbranch_execz .LBB0_123
; %bb.120:                              ; %.preheader3.i.i.i65.preheader
	s_mov_b32 s7, 0
.LBB0_121:                              ; %.preheader3.i.i.i65
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[4:5] offset:40
	global_load_b64 v[12:13], v3, s[4:5]
	v_dual_mov_b32 v15, v1 :: v_dual_mov_b32 v14, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[12:13]
	v_and_b32_e32 v4, v7, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[12:13], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[14:15]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_121
; %bb.122:                              ; %Flow618
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_123:                              ; %Flow620
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_124:                              ; %.loopexit4.i.i.i60
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v12, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[3:4], v12, s[4:5] offset:40
	global_load_b128 v[13:16], v12, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_126
; %bb.125:
	v_dual_mov_b32 v17, s13 :: v_dual_mov_b32 v18, v12
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v13, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v14, vcc_lo
	v_dual_mov_b32 v19, 2 :: v_dual_mov_b32 v20, 1
	global_store_b128 v[0:1], v[17:20], off offset:8
.LBB0_126:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[11:12]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v9, 0xffffff1f, v9, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_mov_b32_e32 v11, v12
	v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v18, s19
	v_dual_mov_b32 v16, s17 :: v_dual_mov_b32 v17, s18
	s_clause 0x3
	global_store_b128 v[0:1], v[9:12], off
	global_store_b128 v[0:1], v[15:18], off offset:16
	global_store_b128 v[0:1], v[15:18], off offset:32
	global_store_b128 v[0:1], v[15:18], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_134
; %bb.127:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v15, s6
	v_mov_b32_e32 v16, s7
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v6, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v3, vcc_lo, v13, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v14, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[15:18], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_130
; %bb.128:                              ; %.preheader1.i.i.i63.preheader
	s_mov_b32 s13, 0
.LBB0_129:                              ; %.preheader1.i.i.i63
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v9, s6 :: v_dual_mov_b32 v10, s7
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v6, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_129
.LBB0_130:                              ; %Flow616
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v7, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v6, s13, 0
	global_load_b64 v[3:4], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_132
; %bb.131:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_132:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_134
; %bb.133:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_134:                              ; %Flow617
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v3, vcc_lo, v13, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_135:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_137
; %bb.136:                              ;   in Loop: Header=BB0_135 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_137:                              ;   in Loop: Header=BB0_135 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_139
; %bb.138:                              ;   in Loop: Header=BB0_135 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_140
.LBB0_139:                              ;   in Loop: Header=BB0_135 Depth=1
	s_mov_b32 s3, -1
.LBB0_140:                              ; %Flow611
                                        ;   in Loop: Header=BB0_135 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_135
; %bb.141:
	global_load_b128 v[11:14], v[0:1], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_145
; %bb.142:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[6:7], v3, s[4:5] offset:24 glc
	global_load_b64 v[9:10], v3, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, v4, s6
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v15 :: v_dual_cndmask_b32 v13, v13, v4
	v_mov_b32_e32 v15, v6
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v13, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[13:16], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_145
; %bb.143:                              ; %.preheader.i.i.i62.preheader
	s_mov_b32 s2, 0
.LBB0_144:                              ; %.preheader.i.i.i62
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[13:16], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[15:16]
	v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v15, v6
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_144
.LBB0_145:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_146:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v13, v38 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v13
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s2, s2, v13
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_152
; %bb.147:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[16:17], v3, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[6:7], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v16
	v_and_b32_e32 v1, v1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[14:15], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[16:17]
	s_cbranch_execz .LBB0_151
; %bb.148:                              ; %.preheader3.i.i.i72.preheader
	s_mov_b32 s7, 0
.LBB0_149:                              ; %.preheader3.i.i.i72
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[4:5] offset:40
	global_load_b64 v[9:10], v3, s[4:5]
	v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v16
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[9:10]
	v_and_b32_e32 v4, v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[14:15], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[16:17]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_149
; %bb.150:                              ; %Flow554
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_151:                              ; %Flow556
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_152:                              ; %.loopexit4.i.i.i66
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v14, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[3:4], v14, s[4:5] offset:40
	global_load_b128 v[15:18], v14, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_154
; %bb.153:
	v_dual_mov_b32 v19, s13 :: v_dual_mov_b32 v20, v14
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v16, vcc_lo
	v_dual_mov_b32 v21, 2 :: v_dual_mov_b32 v22, 1
	global_store_b128 v[0:1], v[19:22], off offset:8
.LBB0_154:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[13:14]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v18, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s19, s16
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	v_and_or_b32 v11, 0xffffff1f, v11, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v13, v37 :: v_dual_mov_b32 v20, s19
	v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v18, s17
	v_mov_b32_e32 v17, s16
	s_clause 0x3
	global_store_b128 v[0:1], v[11:14], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[17:20], off offset:32
	global_store_b128 v[0:1], v[17:20], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_162
; %bb.155:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v11, s6
	v_mov_b32_e32 v12, s7
	s_clause 0x1
	global_load_b64 v[13:14], v6, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v6, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v3, vcc_lo, v15, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v16, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[13:14]
	s_cbranch_execz .LBB0_158
; %bb.156:                              ; %.preheader1.i.i.i70.preheader
	s_mov_b32 s13, 0
.LBB0_157:                              ; %.preheader1.i.i.i70
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v9, s6 :: v_dual_mov_b32 v10, s7
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v6, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_157
.LBB0_158:                              ; %Flow552
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v7, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v6, s13, 0
	global_load_b64 v[3:4], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_160
; %bb.159:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_160:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_162
; %bb.161:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_162:                              ; %Flow553
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v3, vcc_lo, v15, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_163:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_165
; %bb.164:                              ;   in Loop: Header=BB0_163 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_165:                              ;   in Loop: Header=BB0_163 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_167
; %bb.166:                              ;   in Loop: Header=BB0_163 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_168
.LBB0_167:                              ;   in Loop: Header=BB0_163 Depth=1
	s_mov_b32 s3, -1
.LBB0_168:                              ; %Flow547
                                        ;   in Loop: Header=BB0_163 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_163
; %bb.169:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_173
; %bb.170:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[3:4], v6, s[4:5] offset:40
	global_load_b64 v[13:14], v6, s[4:5] offset:24 glc
	global_load_b64 v[11:12], v6, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v7, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_cndmask_b32_e32 v10, v10, v15, vcc_lo
	v_and_b32_e32 v3, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_dual_mov_b32 v11, v13 :: v_dual_and_b32 v4, v10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_173
; %bb.171:                              ; %.preheader.i.i.i69.preheader
	s_mov_b32 s2, 0
.LBB0_172:                              ; %.preheader.i.i.i69
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_172
.LBB0_173:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v3
	v_mov_b32_e32 v7, 0
	v_cmp_eq_u32_e64 s2, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_179
; %bb.174:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[11:12], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[6:7], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v7, v7, v12
	v_and_b32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, 24
	v_mul_hi_u32 v13, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v13, v7
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v9, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v10, v7, vcc_lo
	global_load_b64 v[9:10], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[11:12]
	s_cbranch_execz .LBB0_178
; %bb.175:                              ; %.preheader3.i.i.i79.preheader
	s_mov_b32 s7, 0
.LBB0_176:                              ; %.preheader3.i.i.i79
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v4, s[4:5] offset:40
	global_load_b64 v[13:14], v4, s[4:5]
	v_dual_mov_b32 v12, v7 :: v_dual_mov_b32 v11, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[7:8]
	v_mov_b32_e32 v7, v9
	global_load_b64 v[9:10], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_176
; %bb.177:                              ; %Flow540
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_178:                              ; %Flow542
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_179:                              ; %.loopexit4.i.i.i73
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v6
	v_readfirstlane_b32 s7, v7
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v4, s[4:5] offset:40
	global_load_b128 v[9:12], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v13
	v_readfirstlane_b32 s11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_181
; %bb.180:
	v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v14, v4
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v9, s12
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v10, vcc_lo
	v_dual_mov_b32 v15, 2 :: v_dual_mov_b32 v16, 1
	global_store_b128 v[6:7], v[13:16], off offset:8
.LBB0_181:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[6:7], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v12, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v3, v6
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo
	v_mov_b32_e32 v3, v4
	v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v14, s19
	v_dual_mov_b32 v12, s17 :: v_dual_mov_b32 v13, s18
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[11:14], off offset:16
	global_store_b128 v[6:7], v[11:14], off offset:32
	global_store_b128 v[6:7], v[11:14], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_189
; %bb.182:
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, s7
	v_mov_b32_e32 v13, s6
	s_clause 0x1
	global_load_b64 v[15:16], v3, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v0
	v_readfirstlane_b32 s15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v0, vcc_lo, v9, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v10, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_185
; %bb.183:                              ; %.preheader1.i.i.i77.preheader
	s_mov_b32 s13, 0
.LBB0_184:                              ; %.preheader1.i.i.i77
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_184
.LBB0_185:                              ; %Flow538
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v4, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v3, s13, 0
	global_load_b64 v[0:1], v4, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_187
; %bb.186:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[3:4], off offset:8
.LBB0_187:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB0_189
; %bb.188:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[0:1], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_189:                              ; %Flow539
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v0, vcc_lo, v9, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_190:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_192
; %bb.191:                              ;   in Loop: Header=BB0_190 Depth=1
	global_load_b32 v3, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_192:                              ;   in Loop: Header=BB0_190 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_194
; %bb.193:                              ;   in Loop: Header=BB0_190 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_195
.LBB0_194:                              ;   in Loop: Header=BB0_190 Depth=1
	s_mov_b32 s3, -1
.LBB0_195:                              ; %Flow533
                                        ;   in Loop: Header=BB0_190 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_190
; %bb.196:
	global_load_b64 v[3:4], v[6:7], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_200
; %bb.197:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[4:5] offset:40
	global_load_b64 v[13:14], v6, s[4:5] offset:24 glc
	global_load_b64 v[11:12], v6, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v7, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_and_b32_e32 v0, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v0, 24
	v_cndmask_b32_e32 v10, v10, v15, vcc_lo
	v_mul_lo_u32 v0, v0, 24
	v_and_b32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, v0
	v_mul_lo_u32 v1, v1, 24
	v_mov_b32_e32 v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v7, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_200
; %bb.198:                              ; %.preheader.i.i.i76.preheader
	s_mov_b32 s2, 0
.LBB0_199:                              ; %.preheader.i.i.i76
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_199
.LBB0_200:                              ; %__ockl_printf_append_args.exit80
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v6, v38
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v6
	v_cmp_eq_u32_e64 s2, s2, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_206
; %bb.201:
	v_mov_b32_e32 v7, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[11:12], v7, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v7, s[4:5] offset:40
	global_load_b64 v[9:10], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v11
	v_and_b32_e32 v1, v1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v9, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	global_load_b64 v[9:10], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v7, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[11:12]
	s_cbranch_execz .LBB0_205
; %bb.202:                              ; %.preheader3.i.i.i87.preheader
	s_mov_b32 s7, 0
.LBB0_203:                              ; %.preheader3.i.i.i87
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v7, s[4:5] offset:40
	global_load_b64 v[13:14], v7, s[4:5]
	v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v11, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v9
	global_load_b64 v[9:10], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v7, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_203
; %bb.204:                              ; %Flow526
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_205:                              ; %Flow528
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_206:                              ; %.loopexit4.i.i.i81
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v7, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v7, s[4:5] offset:40
	global_load_b128 v[9:12], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v13
	v_readfirstlane_b32 s11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_208
; %bb.207:
	v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v14, v7
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v9, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v10, vcc_lo
	v_dual_mov_b32 v15, 2 :: v_dual_mov_b32 v16, 1
	global_store_b128 v[0:1], v[13:16], off offset:8
.LBB0_208:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v12, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v3, 0xffffff1f, v3, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v11, s16
	v_dual_mov_b32 v12, s17 :: v_dual_mov_b32 v13, s18
	v_mov_b32_e32 v14, s19
	s_clause 0x3
	global_store_b128 v[0:1], v[3:6], off
	global_store_b128 v[0:1], v[11:14], off offset:16
	global_store_b128 v[0:1], v[11:14], off offset:32
	global_store_b128 v[0:1], v[11:14], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_216
; %bb.209:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v13, s6
	v_mov_b32_e32 v14, s7
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v6, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v3, vcc_lo, v9, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v10, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_212
; %bb.210:                              ; %.preheader1.i.i.i85.preheader
	s_mov_b32 s13, 0
.LBB0_211:                              ; %.preheader1.i.i.i85
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_211
.LBB0_212:                              ; %Flow524
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v7, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v6, s13, 0
	global_load_b64 v[3:4], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_214
; %bb.213:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_214:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_216
; %bb.215:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_216:                              ; %Flow525
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v3, vcc_lo, v9, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_217:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_219
; %bb.218:                              ;   in Loop: Header=BB0_217 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_219:                              ;   in Loop: Header=BB0_217 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_221
; %bb.220:                              ;   in Loop: Header=BB0_217 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_222
.LBB0_221:                              ;   in Loop: Header=BB0_217 Depth=1
	s_mov_b32 s3, -1
.LBB0_222:                              ; %Flow519
                                        ;   in Loop: Header=BB0_217 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_217
; %bb.223:
	global_load_b64 v[6:7], v[0:1], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_227
; %bb.224:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[13:14], v3, s[4:5] offset:24 glc
	global_load_b64 v[11:12], v3, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v4, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v4
	v_and_b32_e32 v1, v10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v9, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v11, v0
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v1, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_227
; %bb.225:                              ; %.preheader.i.i.i84.preheader
	s_mov_b32 s2, 0
.LBB0_226:                              ; %.preheader.i.i.i84
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_226
.LBB0_227:                              ; %__ockl_printf_append_args.exit88
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v3
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s2, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_233
; %bb.228:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[11:12], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v12
	v_and_b32_e32 v0, v0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v9, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	global_load_b64 v[9:10], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[11:12]
	s_cbranch_execz .LBB0_232
; %bb.229:                              ; %.preheader3.i.i.i95.preheader
	s_mov_b32 s7, 0
.LBB0_230:                              ; %.preheader3.i.i.i95
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v4, s[4:5] offset:40
	global_load_b64 v[13:14], v4, s[4:5]
	v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v11, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v9
	global_load_b64 v[9:10], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_230
; %bb.231:                              ; %Flow512
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_232:                              ; %Flow514
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_233:                              ; %.loopexit4.i.i.i89
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v4, s[4:5] offset:40
	global_load_b128 v[10:13], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v14
	v_readfirstlane_b32 s11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_235
; %bb.234:
	v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v15, v4
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v11, vcc_lo
	v_dual_mov_b32 v16, 2 :: v_dual_mov_b32 v17, 1
	global_store_b128 v[0:1], v[14:17], off offset:8
.LBB0_235:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v12, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v6, 0xffffff1f, v6, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v12, s16
	v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
	v_mov_b32_e32 v15, s19
	s_clause 0x3
	global_store_b128 v[0:1], v[6:9], off
	global_store_b128 v[0:1], v[12:15], off offset:16
	global_store_b128 v[0:1], v[12:15], off offset:32
	global_store_b128 v[0:1], v[12:15], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_243
; %bb.236:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v15, s7
	v_mov_b32_e32 v14, s6
	s_clause 0x1
	global_load_b64 v[16:17], v6, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v6, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v3, vcc_lo, v10, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v11, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v6, v[14:17], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB0_239
; %bb.237:                              ; %.preheader1.i.i.i93.preheader
	s_mov_b32 s13, 0
.LBB0_238:                              ; %.preheader1.i.i.i93
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v6, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_238
.LBB0_239:                              ; %Flow510
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v7, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v6, s13, 0
	global_load_b64 v[3:4], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_241
; %bb.240:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_241:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_243
; %bb.242:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_243:                              ; %Flow511
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v3, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_244:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_246
; %bb.245:                              ;   in Loop: Header=BB0_244 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_246:                              ;   in Loop: Header=BB0_244 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_248
; %bb.247:                              ;   in Loop: Header=BB0_244 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_249
.LBB0_248:                              ;   in Loop: Header=BB0_244 Depth=1
	s_mov_b32 s3, -1
.LBB0_249:                              ; %Flow505
                                        ;   in Loop: Header=BB0_244 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_244
; %bb.250:
	global_load_b64 v[9:10], v[0:1], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_254
; %bb.251:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[4:5] offset:40
	global_load_b64 v[6:7], v3, s[4:5] offset:24 glc
	global_load_b64 v[13:14], v3, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v4, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v4
	v_and_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v11, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v13, v0
	v_mov_b32_e32 v13, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v7
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_254
; %bb.252:                              ; %.preheader.i.i.i92.preheader
	s_mov_b32 s2, 0
.LBB0_253:                              ; %.preheader.i.i.i92
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[13:14]
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v13, v6
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_253
.LBB0_254:                              ; %__ockl_printf_append_args.exit96
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v3
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s2, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_260
; %bb.255:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[13:14], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v4, s[4:5] offset:40
	global_load_b64 v[6:7], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v14
	v_and_b32_e32 v0, v0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[13:14]
	s_cbranch_execz .LBB0_259
; %bb.256:                              ; %.preheader3.i.i.i103.preheader
	s_mov_b32 s7, 0
.LBB0_257:                              ; %.preheader3.i.i.i103
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v4, s[4:5] offset:40
	global_load_b64 v[11:12], v4, s[4:5]
	v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[11:12]
	v_and_b32_e32 v11, v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[13:14]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_257
; %bb.258:                              ; %Flow498
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_259:                              ; %Flow500
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_260:                              ; %.loopexit4.i.i.i97
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[6:7], v4, s[4:5] offset:40
	global_load_b128 v[13:16], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v6
	v_readfirstlane_b32 s11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_262
; %bb.261:
	v_dual_mov_b32 v17, s13 :: v_dual_mov_b32 v18, v4
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v13, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v14, vcc_lo
	v_dual_mov_b32 v19, 2 :: v_dual_mov_b32 v20, 1
	global_store_b128 v[0:1], v[17:20], off offset:8
.LBB0_262:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v16, vcc_lo
	v_mad_u64_u32 v[11:12], null, v5, s9, v[8:9]
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v9, 0xffffff1f, v9, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v3, s16
	v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v5, s18
	v_mov_b32_e32 v6, s19
	s_clause 0x3
	global_store_b128 v[0:1], v[9:12], off
	global_store_b128 v[0:1], v[3:6], off offset:16
	global_store_b128 v[0:1], v[3:6], off offset:32
	global_store_b128 v[0:1], v[3:6], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_270
; %bb.263:
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v16, s7
	v_mov_b32_e32 v15, s6
	s_clause 0x1
	global_load_b64 v[17:18], v9, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v9, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v7, vcc_lo, v13, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v14, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[15:18], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[17:18]
	s_cbranch_execz .LBB0_266
; %bb.264:                              ; %.preheader1.i.i.i101.preheader
	s_mov_b32 s13, 0
.LBB0_265:                              ; %.preheader1.i.i.i101
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v9, v[3:6], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_265
.LBB0_266:                              ; %Flow496
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v6, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v5, s13, 0
	global_load_b64 v[3:4], v6, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_268
; %bb.267:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_268:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_270
; %bb.269:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_270:                              ; %Flow497
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, s3
	v_add_co_u32 v3, vcc_lo, v13, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_271:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_273
; %bb.272:                              ;   in Loop: Header=BB0_271 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_273:                              ;   in Loop: Header=BB0_271 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v5
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_275
; %bb.274:                              ;   in Loop: Header=BB0_271 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_276
.LBB0_275:                              ;   in Loop: Header=BB0_271 Depth=1
	s_mov_b32 s3, -1
.LBB0_276:                              ; %Flow491
                                        ;   in Loop: Header=BB0_271 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_271
; %bb.277:
	global_load_b64 v[3:4], v[0:1], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_281
; %bb.278:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[0:1], v9, s[4:5] offset:40
	global_load_b64 v[12:13], v9, s[4:5] offset:24 glc
	global_load_b64 v[7:8], v9, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	v_cndmask_b32_e32 v6, v6, v14, vcc_lo
	v_cndmask_b32_e32 v5, v5, v10, vcc_lo
	v_and_b32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v5, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v7, v0
	v_mov_b32_e32 v7, v12
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	v_mov_b32_e32 v8, v13
	global_store_b64 v[0:1], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v9, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[7:8], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_281
; %bb.279:                              ; %.preheader.i.i.i100.preheader
	s_mov_b32 s2, 0
.LBB0_280:                              ; %.preheader.i.i.i100
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v9, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[7:8]
	v_dual_mov_b32 v7, v12 :: v_dual_mov_b32 v8, v13
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_280
.LBB0_281:                              ; %__ockl_printf_append_args.exit104
	s_or_b32 exec_lo, exec_lo, s3
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v38
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v38
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_287
; %bb.282:
	v_mov_b32_e32 v5, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[8:9], v5, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v5, s[4:5] offset:40
	global_load_b64 v[6:7], v5, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v8
	v_and_b32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[8:9]
	s_cbranch_execz .LBB0_286
; %bb.283:                              ; %.preheader3.i.i.i111.preheader
	s_mov_b32 s7, 0
.LBB0_284:                              ; %.preheader3.i.i.i111
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v5, s[4:5] offset:40
	global_load_b64 v[12:13], v5, s[4:5]
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v6, v8
	v_and_b32_e32 v10, v7, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[12:13]
	v_mad_u64_u32 v[6:7], null, v10, 24, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v6
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_284
; %bb.285:                              ; %Flow484
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_286:                              ; %Flow486
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_287:                              ; %.loopexit4.i.i.i105
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v39, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[5:6], v39, s[4:5] offset:40
	global_load_b128 v[7:10], v39, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v5
	v_readfirstlane_b32 s11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s8, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_289
; %bb.288:
	v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, v39
	s_add_i32 s13, s8, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v8, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[0:1], v[12:15], off offset:8
.LBB0_289:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[38:39]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	v_mad_u64_u32 v[5:6], null, v37, s9, v[2:3]
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v9, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v3, 0xffffff1d, v3, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v6, v39
	v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, s19
	v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
	s_clause 0x3
	global_store_b128 v[0:1], v[3:6], off
	global_store_b128 v[0:1], v[12:15], off offset:16
	global_store_b128 v[0:1], v[12:15], off offset:32
	global_store_b128 v[0:1], v[12:15], off offset:48
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB0_297
; %bb.290:
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v13, s7
	v_mov_b32_e32 v12, s6
	s_clause 0x1
	global_load_b64 v[14:15], v4, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v4, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[6:7]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s13, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v9, vcc_lo, v7, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v8, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v4, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[14:15]
	s_cbranch_execz .LBB0_293
; %bb.291:                              ; %.preheader1.i.i.i109.preheader
	s_mov_b32 s11, 0
.LBB0_292:                              ; %.preheader1.i.i.i109
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
	s_sleep 1
	global_store_b64 v[9:10], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_292
.LBB0_293:                              ; %Flow482
	s_or_b32 exec_lo, exec_lo, s10
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_295
; %bb.294:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_295:
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_297
; %bb.296:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_297:                              ; %Flow483
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s8, s8, s3
	v_add_co_u32 v0, vcc_lo, v7, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_298:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_300
; %bb.299:                              ;   in Loop: Header=BB0_298 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_300:                              ;   in Loop: Header=BB0_298 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v2
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_302
; %bb.301:                              ;   in Loop: Header=BB0_298 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_303
.LBB0_302:                              ;   in Loop: Header=BB0_298 Depth=1
	s_mov_b32 s3, -1
.LBB0_303:                              ; %Flow477
                                        ;   in Loop: Header=BB0_298 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_298
; %bb.304:
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_308
; %bb.305:
	v_mov_b32_e32 v4, 0
	s_clause 0x2
	global_load_b64 v[2:3], v4, s[4:5] offset:40
	global_load_b64 v[8:9], v4, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v4, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v12 :: v_dual_cndmask_b32 v0, v0, v10
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v10, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v2
	v_mov_b32_e32 v2, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v3, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v4, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_308
; %bb.306:                              ; %.preheader.i.i.i108.preheader
	s_mov_b32 s2, 0
.LBB0_307:                              ; %.preheader.i.i.i108
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v4, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[2:3]
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_307
.LBB0_308:                              ; %__ockl_printf_append_args.exit112
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v12, 31, v11
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[11:12]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_309:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10rotMatFuncPfS_iiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10rotMatFuncPfS_iiS_, .Lfunc_end0-_Z10rotMatFuncPfS_iiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13856
; NumSgprs: 24
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"x=%d y=%d iIn=%d jIn=%d in=%d, out=%d\n"
	.size	.str, 39

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10rotMatFuncPfS_iiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z10rotMatFuncPfS_iiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
