#include <stdio.h>
#include <stdlib.h>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <iostream> 
#include <cuda_runtime.h>
#include <chrono> 

using namespace std;

const int INF = ((1 << 30) - 1);
// const int V = 50010;
void input(char* inFileName);
void output(char* outFileName);

void block_FW(int B);
int ceil(int a, int b);
// void cal(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);

int n, m;
// static int Dist[V][V];
static __align__(32) int *dist, *Result;

__global__ void PHASE_ONE(int Round, int B, int* distance, int V){
    // calculate target pivot
    extern __shared__ __align__(32) int shared_distance[];
    int x = threadIdx.x;
    int y = threadIdx.y;
    int p_x = Round * B + x; 
    int p_y = Round * B + y; 

    if(p_y < V && p_x < V){
        shared_distance[y * B + x] = distance[p_y * V + p_x];
    }else{
        shared_distance[y * B + x] = INF;
    }
    __syncthreads();

    #pragma unroll 
    for(int k = 0; k < B; k++){
        if(shared_distance[y * B + x] > shared_distance[y * B + k] + shared_distance[k * B + x]){
            shared_distance[y * B + x] = shared_distance[y * B + k] + shared_distance[k * B + x];
        }
        __syncthreads();
    }
    
    if(p_y < V && p_x < V){
        distance[p_y * V + p_x] = shared_distance[y * B + x];
    }

}
__global__ void PHASE_TWO(int Round, int B, int* distance, int V){
    // grid size (Round * 2)
    if(blockIdx.x == Round){
        return;
    }
    extern __shared__ __align__(32) int shared[];
    // first block stores pivot block
    // rest of spaces store distance col/row's block
    int* shared_p_distacne = shared; 
    int* shared_distance = shared + B*B;

    int x = threadIdx.x;
    int y = threadIdx.y;
    int p_x = Round * B + x;
    int p_y = Round * B + y;
    int idx_y, idx_x;

    // fill present distance
    if(p_y < V && p_x < V){
        shared_p_distacne[y * B + x] = distance[p_y * V + p_x];
    }else{
        shared_p_distacne[y * B + x] = INF;
    } 
    __syncthreads();

    if(blockIdx.x == Round) {
        return;
    }
  
    if(blockIdx.y == 0){
        // pivot row                    
        idx_x = blockIdx.x * B + x; 
        idx_y = p_y;
    }else{   
        // pivot col
        idx_x = p_x;
        idx_y = blockIdx.x * B + y;
    }

    if(idx_y >= V || idx_x >= V) {
        return;
    }

    if(idx_y < V && idx_x < V){
        shared_distance[y * B + x] = distance[idx_y * V + idx_x];
    }else{
        shared_distance[y * B + x] = INF;
    } 
    __syncthreads();

    // calculate for each row/col
    if(blockIdx.y == 0){        
        // #pragma unroll 
        for(int k = 0; k < B; k++){
            int temp = shared_p_distacne[y * B + k] + shared_distance[k * B + x];
            if(shared_distance[y * B + x] > temp){
                shared_distance[y * B + x] = temp;
            }  
            __syncthreads();
        }
    }else{            
        // #pragma unroll 
        for(int k = 0;  k < B; k++){
            int temp = shared_distance[y * B + k] + shared_p_distacne[k * B + x];
            if(shared_distance[y * B + x] > temp){
                shared_distance[y * B + x] = temp;
            }        
            __syncthreads();
        }     
    }

    if(idx_y < V && idx_x < V){
        distance[idx_y * V + idx_x] = shared_distance[y * B + x];
    }
    

}

__global__ void PHASE_THREE(int Round, int B, int* distance, int V){
    // grid size (Round*Round)
    if(blockIdx.x == Round || blockIdx.y == Round){
        return;
    }

    extern __shared__ __align__(32) int shared[];
    int* shared_row = shared;
    int* shared_col = shared + B*B;
    int x = threadIdx.x;
    int y = threadIdx.y;
    int idx_x = blockIdx.x * B + x;
    int idx_y = blockIdx.y * B + y;
    int row_i = Round * B + y;
    int row_j = idx_x;
    int col_i = idx_y;
    int col_j = Round * B + x;

    if(row_i < V && row_j < V){
        shared_row[y * B + x] = distance[row_i * V + row_j];
    }else{
        shared_row[y * B + x] = INF;
    } 
    if(col_i < V && col_j < V){
        shared_col[y * B + x] = distance[col_i * V + col_j];
    }else{
        shared_col[y * B + x] = INF;
    }
    __syncthreads();

    if(idx_y >= V || idx_x >= V) {
        return;
    }

    int temp = distance[idx_y * V + idx_x];      
    // #pragma unroll 
    // #pragma GCC ivdep
    for(int k = 0; k < B; k++){
      if(temp > shared_col[y * B + k] + shared_row[k * B + x]){
        temp = shared_col[y * B + k] + shared_row[k * B + x];
      }
    }
    distance[idx_y * V + idx_x] = temp;
}

int main(int argc, char* argv[]) {
    input(argv[1]);
    int B = 32;
    block_FW(B);
    output(argv[2]);
    return 0;
}

void input(char* infile) {
    FILE* file = fopen(infile, "rb");
    fread(&n, sizeof(int), 1, file);
    fread(&m, sizeof(int), 1, file);

    dist = (int*)malloc(n * n * sizeof(int));
    Result = (int*)malloc(n * n * sizeof(int));

    for (int i = 0; i < n; ++i) {
        for (int j = 0; j < n; ++j) {
            if (i == j) {
                dist[i * n + j] = 0;
            } else {
                dist[i * n + j] = INF;
            }
        }
    }

    int pair[3];
    for (int i = 0; i < m; ++i) {
        fread(pair, sizeof(int), 3, file);
        dist[pair[0] * n + pair[1]] = pair[2];
    }
    fclose(file);
}

void output(char* outFileName) {
    FILE* outfile = fopen(outFileName, "w");
    for (int i = 0; i < n; ++i) {
        for (int j = 0; j < n; ++j) {
            if(Result[i * n + j] >= INF){ 
                Result[i * n + j] = INF;
              }
        }
        fwrite(&Result[i * n], sizeof(int), n, outfile);
    }
    fclose(outfile);
}

int ceil(int a, int b) { return (a + b - 1) / b; }

void block_FW(int B) {

    int round = ceil(n, B);
    int *device_distance;
    int deviceID;
    cudaDeviceProp prop;
    dim3 grid_p1(1, 1);
    dim3 grid_p2(round, 2);
    dim3 grid_p3(round, round);
    dim3 blk(B, B);

    cudaGetDevice(&deviceID);
    cudaGetDeviceProperties(&prop, deviceID);
    
    if (!prop.deviceOverlap){
		printf("!prop.deviceOverlap\n");
  	}
    
    cudaSetDevice(0);
    cudaMalloc(&device_distance, n * n * sizeof(int));
    cudaMemcpy(device_distance, dist, n * n * sizeof(int), cudaMemcpyHostToDevice);
    
    for (int i = 0; i < round; i++) {
        PHASE_ONE<<<grid_p1, blk, B * B * sizeof(int)>>>(i, B, device_distance, n);
  
        PHASE_TWO<<<grid_p2, blk, B * B * sizeof(int) * 2>>>(i, B, device_distance, n);
  
        PHASE_THREE<<<grid_p3, blk, B * B * sizeof(int) * 2>>>(i, B, device_distance, n);
    }

    cudaMemcpy(Result, device_distance, n * n * sizeof(int), cudaMemcpyDeviceToHost);
    cudaFree(device_distance);

}

// void cal(
//     int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height) {
//     int block_end_x = block_start_x + block_height;
//     int block_end_y = block_start_y + block_width;

//     for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
//         for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
//             // To calculate B*B elements in the block (b_i, b_j)
//             // For each block, it need to compute B times
//             for (int k = Round * B; k < (Round + 1) * B && k < n; ++k) {
//                 // To calculate original index of elements in the block (b_i, b_j)
//                 // For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
//                 int block_internal_start_x = b_i * B;
//                 int block_internal_end_x = (b_i + 1) * B;
//                 int block_internal_start_y = b_j * B;
//                 int block_internal_end_y = (b_j + 1) * B;

//                 if (block_internal_end_x > n) block_internal_end_x = n;
//                 if (block_internal_end_y > n) block_internal_end_y = n;

//                 for (int i = block_internal_start_x; i < block_internal_end_x; ++i) {
//                     for (int j = block_internal_start_y; j < block_internal_end_y; ++j) {
//                         if (Dist[i][k] + Dist[k][j] < Dist[i][j]) {
//                             Dist[i][j] = Dist[i][k] + Dist[k][j];
//                         }
//                     }
//                 }
//             }
//         }
//     }
// }
	.file	"tmpxft_002d0d7b_00000000-6_hw4-1.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3872:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3872:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"rb"
	.text
	.globl	_Z5inputPc
	.type	_Z5inputPc, @function
_Z5inputPc:
.LFB3866:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movl	$4, %esi
	movq	%rax, %rbx
	movq	%rax, %r8
	leaq	n(%rip), %rdi
	call	__fread_chk@PLT
	movl	$1, %ecx
	movl	$4, %esi
	movq	%rbx, %r8
	movl	$4, %edx
	leaq	m(%rip), %rdi
	call	__fread_chk@PLT
	movl	n(%rip), %r12d
	movl	%r12d, %ebp
	imull	%r12d, %ebp
	movslq	%ebp, %rbp
	salq	$2, %rbp
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, _ZL4dist(%rip)
	movq	%rax, %r13
	call	malloc@PLT
	xorl	%ecx, %ecx
	xorl	%esi, %esi
	movl	$1073741823, %edi
	movq	%rax, _ZL6Result(%rip)
	xorl	%eax, %eax
.L3:
	cmpl	%ecx, %r12d
	jle	.L14
	movslq	%eax, %rdx
	leaq	0(%r13,%rdx,4), %r8
	xorl	%edx, %edx
.L5:
	cmpl	%edx, %ecx
	movl	%edi, %r9d
	cmove	%esi, %r9d
	movl	%r9d, (%r8,%rdx,4)
	incq	%rdx
	cmpl	%edx, %r12d
	jg	.L5
	incl	%ecx
	addl	%r12d, %eax
	jmp	.L3
.L14:
	xorl	%r12d, %r12d
	leaq	12(%rsp), %rbp
.L7:
	cmpl	%r12d, m(%rip)
	jle	.L15
	movl	$3, %ecx
	movl	$4, %edx
	movq	%rbx, %r8
	movq	%rbp, %rdi
	movl	$12, %esi
	incl	%r12d
	call	__fread_chk@PLT
	movl	12(%rsp), %eax
	movl	20(%rsp), %ecx
	imull	n(%rip), %eax
	movq	_ZL4dist(%rip), %rdx
	addl	16(%rsp), %eax
	cltq
	movl	%ecx, (%rdx,%rax,4)
	jmp	.L7
.L15:
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3866:
	.size	_Z5inputPc, .-_Z5inputPc
	.section	.rodata.str1.1
.LC1:
	.string	"w"
	.text
	.globl	_Z6outputPc
	.type	_Z6outputPc, @function
_Z6outputPc:
.LFB3867:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC1(%rip), %rsi
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	fopen@PLT
	movq	%rax, %rbx
.L17:
	cmpl	%ebp, n(%rip)
	jle	.L20
	movq	_ZL6Result(%rip), %rsi
	xorl	%ecx, %ecx
.L21:
	movslq	n(%rip), %rdx
	movl	%edx, %eax
	imull	%ebp, %eax
	cmpl	%ecx, %edx
	jle	.L23
	addl	%ecx, %eax
	cltq
	leaq	(%rsi,%rax,4), %rax
	cmpl	$1073741822, (%rax)
	jle	.L18
	movl	$1073741823, (%rax)
.L18:
	incl	%ecx
	jmp	.L21
.L23:
	cltq
	movq	%rbx, %rcx
	incl	%ebp
	leaq	(%rsi,%rax,4), %rdi
	movl	$4, %esi
	call	fwrite@PLT
	jmp	.L17
.L20:
	popq	%rax
	.cfi_def_cfa_offset 24
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3867:
	.size	_Z6outputPc, .-_Z6outputPc
	.globl	_Z4ceilii
	.type	_Z4ceilii, @function
_Z4ceilii:
.LFB3868:
	.cfi_startproc
	endbr64
	leal	-1(%rsi,%rdi), %eax
	cltd
	idivl	%esi
	ret
	.cfi_endproc
.LFE3868:
	.size	_Z4ceilii, .-_Z4ceilii
	.globl	_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii
	.type	_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii, @function
_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii:
.LFB3894:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9PHASE_ONEiiPii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L25:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3894:
	.size	_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii, .-_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii
	.globl	_Z9PHASE_ONEiiPii
	.type	_Z9PHASE_ONEiiPii, @function
_Z9PHASE_ONEiiPii:
.LFB3895:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii
	.cfi_endproc
.LFE3895:
	.size	_Z9PHASE_ONEiiPii, .-_Z9PHASE_ONEiiPii
	.globl	_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii
	.type	_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii, @function
_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii:
.LFB3896:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9PHASE_TWOiiPii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L30:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3896:
	.size	_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii, .-_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii
	.globl	_Z9PHASE_TWOiiPii
	.type	_Z9PHASE_TWOiiPii, @function
_Z9PHASE_TWOiiPii:
.LFB3897:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii
	.cfi_endproc
.LFE3897:
	.size	_Z9PHASE_TWOiiPii, .-_Z9PHASE_TWOiiPii
	.globl	_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii
	.type	_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii, @function
_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii:
.LFB3898:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11PHASE_THREEiiPii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L35:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3898:
	.size	_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii, .-_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii
	.globl	_Z11PHASE_THREEiiPii
	.type	_Z11PHASE_THREEiiPii, @function
_Z11PHASE_THREEiiPii:
.LFB3899:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii
	.cfi_endproc
.LFE3899:
	.size	_Z11PHASE_THREEiiPii, .-_Z11PHASE_THREEiiPii
	.section	.rodata.str1.1
.LC2:
	.string	"!prop.deviceOverlap\n"
	.text
	.globl	_Z8block_FWi
	.type	_Z8block_FWi, @function
_Z8block_FWi:
.LFB3869:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edi, %ebx
	subq	$1104, %rsp
	.cfi_def_cfa_offset 1152
	movq	%fs:40, %rax
	movq	%rax, 1096(%rsp)
	movl	%edi, %eax
	movl	%edi, 52(%rsp)
	movl	%edi, 56(%rsp)
	addl	n(%rip), %eax
	movl	$1, 24(%rsp)
	decl	%eax
	movl	$1, 48(%rsp)
	cltd
	movl	$1, 60(%rsp)
	idivl	%edi
	leaq	4(%rsp), %rdi
	movl	%eax, %ebp
	movabsq	$4294967297, %rax
	movq	%rax, 16(%rsp)
	incq	%rax
	movl	%ebp, 28(%rsp)
	movq	%rax, 32(%rsp)
	movl	%ebp, 40(%rsp)
	movl	%ebp, 44(%rsp)
	call	cudaGetDevice@PLT
	movl	4(%rsp), %esi
	leaq	64(%rsp), %rdi
	call	cudaGetDeviceProperties_v2@PLT
	cmpl	$0, 448(%rsp)
	jne	.L41
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L41:
	xorl	%edi, %edi
	movl	%ebx, %r12d
	xorl	%r13d, %r13d
	call	cudaSetDevice@PLT
	movl	n(%rip), %esi
	leaq	8(%rsp), %rdi
	imull	%ebx, %r12d
	imull	%esi, %esi
	movslq	%r12d, %r12
	movslq	%esi, %rsi
	leaq	0(,%r12,4), %r14
	salq	$3, %r12
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	n(%rip), %edx
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	_ZL4dist(%rip), %rsi
	imull	%edx, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
.L42:
	cmpl	%ebp, %r13d
	jge	.L49
	movl	60(%rsp), %ecx
	movq	52(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	%r14, %r8
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movl	n(%rip), %ecx
	movq	8(%rsp), %rdx
	movl	%ebx, %esi
	movl	%r13d, %edi
	call	_Z31__device_stub__Z9PHASE_ONEiiPiiiiPii
.L43:
	movl	60(%rsp), %ecx
	movq	52(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	%r12, %r8
	movq	28(%rsp), %rdi
	movl	36(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movl	n(%rip), %ecx
	movq	8(%rsp), %rdx
	movl	%ebx, %esi
	movl	%r13d, %edi
	call	_Z31__device_stub__Z9PHASE_TWOiiPiiiiPii
.L44:
	movl	60(%rsp), %ecx
	movq	52(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	%r12, %r8
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	movl	n(%rip), %ecx
	movq	8(%rsp), %rdx
	movl	%ebx, %esi
	movl	%r13d, %edi
	call	_Z34__device_stub__Z11PHASE_THREEiiPiiiiPii
.L45:
	incl	%r13d
	jmp	.L42
.L49:
	movl	n(%rip), %edx
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	_ZL6Result(%rip), %rdi
	imull	%edx, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$1104, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3869:
	.size	_Z8block_FWi, .-_Z8block_FWi
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3865:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	_Z5inputPc
	movl	$32, %edi
	call	_Z8block_FWi
	movq	16(%rbx), %rdi
	call	_Z6outputPc
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3865:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z11PHASE_THREEiiPii"
.LC4:
	.string	"_Z9PHASE_TWOiiPii"
.LC5:
	.string	"_Z9PHASE_ONEiiPii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3901:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11PHASE_THREEiiPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9PHASE_TWOiiPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9PHASE_ONEiiPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3901:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL6Result
	.comm	_ZL6Result,8,32
	.local	_ZL4dist
	.comm	_ZL4dist,8,32
	.globl	m
	.bss
	.align 4
	.type	m, @object
	.size	m, 4
m:
	.zero	4
	.globl	n
	.align 4
	.type	n, @object
	.size	n, 4
n:
	.zero	4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <iostream> 
#include <hip/hip_runtime.h>
#include <chrono> 

using namespace std;

const int INF = ((1 << 30) - 1);
// const int V = 50010;
void input(char* inFileName);
void output(char* outFileName);

void block_FW(int B);
int ceil(int a, int b);
// void cal(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);

int n, m;
// static int Dist[V][V];
static __align__(32) int *dist, *Result;

__global__ void PHASE_ONE(int Round, int B, int* distance, int V){
    // calculate target pivot
    extern __shared__ __align__(32) int shared_distance[];
    int x = threadIdx.x;
    int y = threadIdx.y;
    int p_x = Round * B + x; 
    int p_y = Round * B + y; 

    if(p_y < V && p_x < V){
        shared_distance[y * B + x] = distance[p_y * V + p_x];
    }else{
        shared_distance[y * B + x] = INF;
    }
    __syncthreads();

    #pragma unroll 
    for(int k = 0; k < B; k++){
        if(shared_distance[y * B + x] > shared_distance[y * B + k] + shared_distance[k * B + x]){
            shared_distance[y * B + x] = shared_distance[y * B + k] + shared_distance[k * B + x];
        }
        __syncthreads();
    }
    
    if(p_y < V && p_x < V){
        distance[p_y * V + p_x] = shared_distance[y * B + x];
    }

}
__global__ void PHASE_TWO(int Round, int B, int* distance, int V){
    // grid size (Round * 2)
    if(blockIdx.x == Round){
        return;
    }
    extern __shared__ __align__(32) int shared[];
    // first block stores pivot block
    // rest of spaces store distance col/row's block
    int* shared_p_distacne = shared; 
    int* shared_distance = shared + B*B;

    int x = threadIdx.x;
    int y = threadIdx.y;
    int p_x = Round * B + x;
    int p_y = Round * B + y;
    int idx_y, idx_x;

    // fill present distance
    if(p_y < V && p_x < V){
        shared_p_distacne[y * B + x] = distance[p_y * V + p_x];
    }else{
        shared_p_distacne[y * B + x] = INF;
    } 
    __syncthreads();

    if(blockIdx.x == Round) {
        return;
    }
  
    if(blockIdx.y == 0){
        // pivot row                    
        idx_x = blockIdx.x * B + x; 
        idx_y = p_y;
    }else{   
        // pivot col
        idx_x = p_x;
        idx_y = blockIdx.x * B + y;
    }

    if(idx_y >= V || idx_x >= V) {
        return;
    }

    if(idx_y < V && idx_x < V){
        shared_distance[y * B + x] = distance[idx_y * V + idx_x];
    }else{
        shared_distance[y * B + x] = INF;
    } 
    __syncthreads();

    // calculate for each row/col
    if(blockIdx.y == 0){        
        // #pragma unroll 
        for(int k = 0; k < B; k++){
            int temp = shared_p_distacne[y * B + k] + shared_distance[k * B + x];
            if(shared_distance[y * B + x] > temp){
                shared_distance[y * B + x] = temp;
            }  
            __syncthreads();
        }
    }else{            
        // #pragma unroll 
        for(int k = 0;  k < B; k++){
            int temp = shared_distance[y * B + k] + shared_p_distacne[k * B + x];
            if(shared_distance[y * B + x] > temp){
                shared_distance[y * B + x] = temp;
            }        
            __syncthreads();
        }     
    }

    if(idx_y < V && idx_x < V){
        distance[idx_y * V + idx_x] = shared_distance[y * B + x];
    }
    

}

__global__ void PHASE_THREE(int Round, int B, int* distance, int V){
    // grid size (Round*Round)
    if(blockIdx.x == Round || blockIdx.y == Round){
        return;
    }

    extern __shared__ __align__(32) int shared[];
    int* shared_row = shared;
    int* shared_col = shared + B*B;
    int x = threadIdx.x;
    int y = threadIdx.y;
    int idx_x = blockIdx.x * B + x;
    int idx_y = blockIdx.y * B + y;
    int row_i = Round * B + y;
    int row_j = idx_x;
    int col_i = idx_y;
    int col_j = Round * B + x;

    if(row_i < V && row_j < V){
        shared_row[y * B + x] = distance[row_i * V + row_j];
    }else{
        shared_row[y * B + x] = INF;
    } 
    if(col_i < V && col_j < V){
        shared_col[y * B + x] = distance[col_i * V + col_j];
    }else{
        shared_col[y * B + x] = INF;
    }
    __syncthreads();

    if(idx_y >= V || idx_x >= V) {
        return;
    }

    int temp = distance[idx_y * V + idx_x];      
    // #pragma unroll 
    // #pragma GCC ivdep
    for(int k = 0; k < B; k++){
      if(temp > shared_col[y * B + k] + shared_row[k * B + x]){
        temp = shared_col[y * B + k] + shared_row[k * B + x];
      }
    }
    distance[idx_y * V + idx_x] = temp;
}

int main(int argc, char* argv[]) {
    input(argv[1]);
    int B = 32;
    block_FW(B);
    output(argv[2]);
    return 0;
}

void input(char* infile) {
    FILE* file = fopen(infile, "rb");
    fread(&n, sizeof(int), 1, file);
    fread(&m, sizeof(int), 1, file);

    dist = (int*)malloc(n * n * sizeof(int));
    Result = (int*)malloc(n * n * sizeof(int));

    for (int i = 0; i < n; ++i) {
        for (int j = 0; j < n; ++j) {
            if (i == j) {
                dist[i * n + j] = 0;
            } else {
                dist[i * n + j] = INF;
            }
        }
    }

    int pair[3];
    for (int i = 0; i < m; ++i) {
        fread(pair, sizeof(int), 3, file);
        dist[pair[0] * n + pair[1]] = pair[2];
    }
    fclose(file);
}

void output(char* outFileName) {
    FILE* outfile = fopen(outFileName, "w");
    for (int i = 0; i < n; ++i) {
        for (int j = 0; j < n; ++j) {
            if(Result[i * n + j] >= INF){ 
                Result[i * n + j] = INF;
              }
        }
        fwrite(&Result[i * n], sizeof(int), n, outfile);
    }
    fclose(outfile);
}

int ceil(int a, int b) { return (a + b - 1) / b; }

void block_FW(int B) {

    int round = ceil(n, B);
    int *device_distance;
    int deviceID;
    hipDeviceProp_t prop;
    dim3 grid_p1(1, 1);
    dim3 grid_p2(round, 2);
    dim3 grid_p3(round, round);
    dim3 blk(B, B);

    hipGetDevice(&deviceID);
    hipGetDeviceProperties(&prop, deviceID);
    
    if (!prop.deviceOverlap){
		printf("!prop.deviceOverlap\n");
  	}
    
    hipSetDevice(0);
    hipMalloc(&device_distance, n * n * sizeof(int));
    hipMemcpy(device_distance, dist, n * n * sizeof(int), hipMemcpyHostToDevice);
    
    for (int i = 0; i < round; i++) {
        PHASE_ONE<<<grid_p1, blk, B * B * sizeof(int)>>>(i, B, device_distance, n);
  
        PHASE_TWO<<<grid_p2, blk, B * B * sizeof(int) * 2>>>(i, B, device_distance, n);
  
        PHASE_THREE<<<grid_p3, blk, B * B * sizeof(int) * 2>>>(i, B, device_distance, n);
    }

    hipMemcpy(Result, device_distance, n * n * sizeof(int), hipMemcpyDeviceToHost);
    hipFree(device_distance);

}

// void cal(
//     int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height) {
//     int block_end_x = block_start_x + block_height;
//     int block_end_y = block_start_y + block_width;

//     for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
//         for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
//             // To calculate B*B elements in the block (b_i, b_j)
//             // For each block, it need to compute B times
//             for (int k = Round * B; k < (Round + 1) * B && k < n; ++k) {
//                 // To calculate original index of elements in the block (b_i, b_j)
//                 // For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
//                 int block_internal_start_x = b_i * B;
//                 int block_internal_end_x = (b_i + 1) * B;
//                 int block_internal_start_y = b_j * B;
//                 int block_internal_end_y = (b_j + 1) * B;

//                 if (block_internal_end_x > n) block_internal_end_x = n;
//                 if (block_internal_end_y > n) block_internal_end_y = n;

//                 for (int i = block_internal_start_x; i < block_internal_end_x; ++i) {
//                     for (int j = block_internal_start_y; j < block_internal_end_y; ++j) {
//                         if (Dist[i][k] + Dist[k][j] < Dist[i][j]) {
//                             Dist[i][j] = Dist[i][k] + Dist[k][j];
//                         }
//                     }
//                 }
//             }
//         }
//     }
// }
	.text
	.file	"hw4-1.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__PHASE_ONEiiPii # -- Begin function _Z24__device_stub__PHASE_ONEiiPii
	.type	_Z24__device_stub__PHASE_ONEiiPii,@function
_Z24__device_stub__PHASE_ONEiiPii:      # @_Z24__device_stub__PHASE_ONEiiPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9PHASE_ONEiiPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__PHASE_ONEiiPii, .Lfunc_end0-_Z24__device_stub__PHASE_ONEiiPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__PHASE_TWOiiPii # -- Begin function _Z24__device_stub__PHASE_TWOiiPii
	.type	_Z24__device_stub__PHASE_TWOiiPii,@function
_Z24__device_stub__PHASE_TWOiiPii:      # @_Z24__device_stub__PHASE_TWOiiPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9PHASE_TWOiiPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__PHASE_TWOiiPii, .Lfunc_end1-_Z24__device_stub__PHASE_TWOiiPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__PHASE_THREEiiPii # -- Begin function _Z26__device_stub__PHASE_THREEiiPii
	.type	_Z26__device_stub__PHASE_THREEiiPii,@function
_Z26__device_stub__PHASE_THREEiiPii:    # @_Z26__device_stub__PHASE_THREEiiPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11PHASE_THREEiiPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__PHASE_THREEiiPii, .Lfunc_end2-_Z26__device_stub__PHASE_THREEiiPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	_Z5inputPc
	movl	$32, %edi
	callq	_Z8block_FWi
	movq	16(%rbx), %rdi
	callq	_Z6outputPc
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z5inputPc                      # -- Begin function _Z5inputPc
	.type	_Z5inputPc,@function
_Z5inputPc:                             # @_Z5inputPc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$n, %edi
	movl	$4, %esi
	movl	$1, %edx
	movq	%rax, %rcx
	callq	fread
	movl	$m, %edi
	movl	$4, %esi
	movl	$1, %edx
	movq	%rbx, %rcx
	callq	fread
	movl	n(%rip), %r12d
	movl	%r12d, %r15d
	imull	%r15d, %r15d
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%rax, _ZL4dist(%rip)
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, _ZL6Result(%rip)
	testl	%r12d, %r12d
	jle	.LBB4_5
# %bb.1:                                # %.preheader.lr.ph
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB4_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_3 Depth 2
	movl	%eax, %edx
	leaq	(%r14,%rdx,4), %rdx
	movl	%r12d, %esi
	imull	%ecx, %esi
	leaq	(%r14,%rcx,4), %rdi
	xorl	%r8d, %r8d
.LBB4_3:                                #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%r8, %rcx
	jne	.LBB4_9
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=2
	movl	$0, (%rdi,%rsi,4)
	jmp	.LBB4_10
.LBB4_9:                                #   in Loop: Header=BB4_3 Depth=2
	movl	$1073741823, (%rdx,%r8,4)       # imm = 0x3FFFFFFF
.LBB4_10:                               #   in Loop: Header=BB4_3 Depth=2
	incq	%r8
	cmpq	%r8, %r12
	jne	.LBB4_3
# %bb.11:                               # %._crit_edge
                                        #   in Loop: Header=BB4_2 Depth=1
	incq	%rcx
	addl	%r12d, %eax
	cmpq	%r12, %rcx
	jne	.LBB4_2
.LBB4_5:                                # %._crit_edge21
	cmpl	$0, m(%rip)
	jle	.LBB4_8
# %bb.6:                                # %.lr.ph24
	xorl	%ebp, %ebp
	leaq	4(%rsp), %r14
.LBB4_7:                                # =>This Inner Loop Header: Depth=1
	movl	$4, %esi
	movl	$3, %edx
	movq	%r14, %rdi
	movq	%rbx, %rcx
	callq	fread
	movl	12(%rsp), %eax
	movq	_ZL4dist(%rip), %rcx
	movslq	4(%rsp), %rdx
	movslq	n(%rip), %rsi
	imulq	%rdx, %rsi
	movslq	8(%rsp), %rdx
	addq	%rsi, %rdx
	movl	%eax, (%rcx,%rdx,4)
	incl	%ebp
	cmpl	m(%rip), %ebp
	jl	.LBB4_7
.LBB4_8:                                # %._crit_edge25
	movq	%rbx, %rdi
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end4:
	.size	_Z5inputPc, .Lfunc_end4-_Z5inputPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z8block_FWi                    # -- Begin function _Z8block_FWi
	.type	_Z8block_FWi,@function
_Z8block_FWi:                           # @_Z8block_FWi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1512, %rsp                     # imm = 0x5E8
	.cfi_def_cfa_offset 1568
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $edi killed $edi def $rdi
	movl	n(%rip), %eax
	addl	%edi, %eax
	decl	%eax
	cltd
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	idivl	%edi
	movl	%eax, %r14d
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDevice
	movl	(%rbx), %esi
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDevicePropertiesR0600
	cmpl	$0, 384(%rbx)
	jne	.LBB5_2
# %bb.1:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB5_2:
	xorl	%r15d, %r15d
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	n(%rip), %esi
	imull	%esi, %esi
	shlq	$2, %rsi
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	_ZL4dist(%rip), %rsi
	movl	n(%rip), %edx
	imull	%edx, %edx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%r14d, %r14d
	jle	.LBB5_11
# %bb.3:                                # %.lr.ph
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movl	%ebx, %eax
	movq	%r14, %r12
	shlq	$32, %r12
	movq	%rax, %r13
	shlq	$32, %r13
	movq	%r14, %rcx
	btsq	$33, %rcx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	orq	%r14, %r12
	orq	%rax, %r13
                                        # kill: def $ebx killed $ebx killed $rbx def $rbx
	imull	%ebx, %ebx
	leaq	(,%rbx,4), %rbp
	shlq	$3, %rbx
.LBB5_4:                                # =>This Inner Loop Header: Depth=1
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbp, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:                                #   in Loop: Header=BB5_4 Depth=1
	movq	8(%rsp), %rdx
	movl	n(%rip), %ecx
	movl	%r15d, %edi
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_Z24__device_stub__PHASE_ONEiiPii
.LBB5_6:                                #   in Loop: Header=BB5_4 Depth=1
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbx, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.7:                                #   in Loop: Header=BB5_4 Depth=1
	movq	8(%rsp), %rdx
	movl	n(%rip), %ecx
	movl	%r15d, %edi
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_Z24__device_stub__PHASE_TWOiiPii
.LBB5_8:                                #   in Loop: Header=BB5_4 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbx, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.9:                                #   in Loop: Header=BB5_4 Depth=1
	movq	8(%rsp), %rdx
	movl	n(%rip), %ecx
	movl	%r15d, %edi
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_Z26__device_stub__PHASE_THREEiiPii
.LBB5_10:                               #   in Loop: Header=BB5_4 Depth=1
	incl	%r15d
	cmpl	%r15d, %r14d
	jne	.LBB5_4
.LBB5_11:                               # %._crit_edge
	movq	_ZL6Result(%rip), %rdi
	movq	8(%rsp), %rsi
	movl	n(%rip), %edx
	imull	%edx, %edx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$1512, %rsp                     # imm = 0x5E8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z8block_FWi, .Lfunc_end5-_Z8block_FWi
	.cfi_endproc
                                        # -- End function
	.globl	_Z6outputPc                     # -- Begin function _Z6outputPc
	.type	_Z6outputPc,@function
_Z6outputPc:                            # @_Z6outputPc
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	n(%rip), %eax
	testl	%eax, %eax
	jle	.LBB6_8
# %bb.1:                                # %.preheader.preheader
	xorl	%r14d, %r14d
.LBB6_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_4 Depth 2
	movq	_ZL6Result(%rip), %rcx
	testl	%eax, %eax
	jle	.LBB6_7
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB6_2 Depth=1
	xorl	%edx, %edx
.LBB6_4:                                # %.lr.ph
                                        #   Parent Loop BB6_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r14d, %esi
	imull	%eax, %esi
	movslq	%esi, %rsi
	addq	%rdx, %rsi
	cmpl	$1073741823, (%rcx,%rsi,4)      # imm = 0x3FFFFFFF
	jl	.LBB6_6
# %bb.5:                                #   in Loop: Header=BB6_4 Depth=2
	movl	$1073741823, (%rcx,%rsi,4)      # imm = 0x3FFFFFFF
	movl	n(%rip), %eax
.LBB6_6:                                #   in Loop: Header=BB6_4 Depth=2
	incq	%rdx
	cmpl	%eax, %edx
	jl	.LBB6_4
.LBB6_7:                                # %._crit_edge
                                        #   in Loop: Header=BB6_2 Depth=1
	movslq	%eax, %rdx
	imull	%r14d, %eax
	cltq
	leaq	(%rcx,%rax,4), %rdi
	movl	$4, %esi
	movq	%rbx, %rcx
	callq	fwrite
	incl	%r14d
	movl	n(%rip), %eax
	cmpl	%eax, %r14d
	jl	.LBB6_2
.LBB6_8:                                # %._crit_edge15
	movq	%rbx, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end6:
	.size	_Z6outputPc, .Lfunc_end6-_Z6outputPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z4ceilii                       # -- Begin function _Z4ceilii
	.type	_Z4ceilii,@function
_Z4ceilii:                              # @_Z4ceilii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
	retq
.Lfunc_end7:
	.size	_Z4ceilii, .Lfunc_end7-_Z4ceilii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9PHASE_ONEiiPii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9PHASE_TWOiiPii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11PHASE_THREEiiPii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	n,@object                       # @n
	.bss
	.globl	n
	.p2align	2, 0x0
n:
	.long	0                               # 0x0
	.size	n, 4

	.type	m,@object                       # @m
	.globl	m
	.p2align	2, 0x0
m:
	.long	0                               # 0x0
	.size	m, 4

	.type	_Z9PHASE_ONEiiPii,@object       # @_Z9PHASE_ONEiiPii
	.section	.rodata,"a",@progbits
	.globl	_Z9PHASE_ONEiiPii
	.p2align	3, 0x0
_Z9PHASE_ONEiiPii:
	.quad	_Z24__device_stub__PHASE_ONEiiPii
	.size	_Z9PHASE_ONEiiPii, 8

	.type	_Z9PHASE_TWOiiPii,@object       # @_Z9PHASE_TWOiiPii
	.globl	_Z9PHASE_TWOiiPii
	.p2align	3, 0x0
_Z9PHASE_TWOiiPii:
	.quad	_Z24__device_stub__PHASE_TWOiiPii
	.size	_Z9PHASE_TWOiiPii, 8

	.type	_Z11PHASE_THREEiiPii,@object    # @_Z11PHASE_THREEiiPii
	.globl	_Z11PHASE_THREEiiPii
	.p2align	3, 0x0
_Z11PHASE_THREEiiPii:
	.quad	_Z26__device_stub__PHASE_THREEiiPii
	.size	_Z11PHASE_THREEiiPii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"rb"
	.size	.L.str, 3

	.type	_ZL4dist,@object                # @_ZL4dist
	.local	_ZL4dist
	.comm	_ZL4dist,8,32
	.type	_ZL6Result,@object              # @_ZL6Result
	.local	_ZL6Result
	.comm	_ZL6Result,8,32
	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w"
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9PHASE_ONEiiPii"
	.size	.L__unnamed_1, 18

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9PHASE_TWOiiPii"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11PHASE_THREEiiPii"
	.size	.L__unnamed_3, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"!prop.deviceOverlap"
	.size	.Lstr, 20

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__PHASE_ONEiiPii
	.addrsig_sym _Z24__device_stub__PHASE_TWOiiPii
	.addrsig_sym _Z26__device_stub__PHASE_THREEiiPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym n
	.addrsig_sym m
	.addrsig_sym _Z9PHASE_ONEiiPii
	.addrsig_sym _Z9PHASE_TWOiiPii
	.addrsig_sym _Z11PHASE_THREEiiPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9PHASE_ONEiiPii       ; -- Begin function _Z9PHASE_ONEiiPii
	.globl	_Z9PHASE_ONEiiPii
	.p2align	8
	.type	_Z9PHASE_ONEiiPii,@function
_Z9PHASE_ONEiiPii:                      ; @_Z9PHASE_ONEiiPii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s1, s[0:1], 0x10
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s5, s4
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v0, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v2
	v_max_i32_e32 v4, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s1, v4
	v_bfrev_b32_e32 v4, -4
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mad_u64_u32 v[4:5], null, v1, s1, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s6, v4
	v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
	global_load_b32 v4, v[4:5], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_lo_u32 v5, v2, s5
	s_cmp_lt_i32 s5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v5, v3
	v_lshl_add_u32 v2, v2, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_7
; %bb.3:                                ; %.lr.ph
	v_lshl_add_u32 v3, v3, 2, 0
	v_lshl_add_u32 v4, v5, 2, 0
	s_lshl_b32 s2, s5, 2
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v4
	ds_load_b32 v6, v3
	ds_load_b32 v7, v2
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v5, v6, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 v7, v5
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	ds_store_b32 v2, v5
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v3, s2, v3
	v_add_nc_u32_e32 v4, 4, v4
	s_add_i32 s5, s5, -1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s5, 0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_7:                                ; %._crit_edge
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mad_u64_u32 v[3:4], null, v1, s1, v[0:1]
	ds_load_b32 v2, v2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9PHASE_ONEiiPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9PHASE_ONEiiPii, .Lfunc_end0-_Z9PHASE_ONEiiPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 10
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9PHASE_TWOiiPii       ; -- Begin function _Z9PHASE_TWOiiPii
	.globl	_Z9PHASE_TWOiiPii
	.p2align	8
	.type	_Z9PHASE_TWOiiPii,@function
_Z9PHASE_TWOiiPii:                      ; @_Z9PHASE_TWOiiPii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s14, s2
	s_cbranch_scc1 .LBB1_18
; %bb.1:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	s_mul_i32 s2, s3, s2
	v_bfrev_b32_e32 v5, -4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, s2, v2
	v_add_nc_u32_e32 v3, s2, v1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_max_i32_e32 v4, v3, v0
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v4
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mad_u64_u32 v[4:5], null, v3, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_lo_u32 v4, v1, s3
	s_mul_i32 s14, s14, s3
	s_cmp_eq_u32 s15, 0
	s_mov_b32 s2, exec_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_add_nc_u32_e32 v1, s14, v1
	v_add_nc_u32_e32 v6, s14, v2
	s_cmp_lg_u32 s15, 0
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v6
	v_lshl_add_u32 v3, v4, 2, 0
	v_max_i32_e32 v6, v1, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v7, v2, 2, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s4, v6
	s_cbranch_execz .LBB1_18
; %bb.4:
	v_mad_u64_u32 v[5:6], null, v1, s4, v[0:1]
	s_mov_b32 s4, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mul_i32 s0, s3, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	global_load_b32 v6, v[0:1], off
	s_add_i32 s1, s0, 0
	s_cmp_gt_i32 s3, 0
	v_lshl_add_u32 v5, v4, 2, s1
	s_cselect_b32 s2, -1, 0
	s_and_not1_b32 vcc_lo, exec_lo, s5
	v_cndmask_b32_e64 v7, 0, 1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v4, v2, 2, v5
	v_cmp_ne_u32_e64 s0, 1, v7
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_11
; %bb.5:                                ; %.preheader119
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_10
; %bb.6:                                ; %.lr.ph.preheader
	v_lshl_add_u32 v6, v2, 2, 0
	s_lshl_b32 s0, s3, 2
	s_mov_b32 s4, s3
.LBB1_7:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v7, v5
	ds_load_b32 v8, v6
	ds_load_b32 v9, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v7, v8, v7
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 v9, v7
	s_cbranch_execz .LBB1_9
; %bb.8:                                ;   in Loop: Header=BB1_7 Depth=1
	ds_store_b32 v4, v7
.LBB1_9:                                ;   in Loop: Header=BB1_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v6, s0, v6
	v_add_nc_u32_e32 v5, 4, v5
	s_add_i32 s4, s4, -1
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s4, 0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_7
.LBB1_10:                               ; %Flow152
	s_mov_b32 s4, 0
.LBB1_11:                               ; %Flow155
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_17
; %bb.12:                               ; %.preheader
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_17
; %bb.13:                               ; %.lr.ph125
	v_lshl_add_u32 v2, v2, 2, s1
	s_lshl_b32 s0, s3, 2
.LBB1_14:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v3
	ds_load_b32 v6, v2
	ds_load_b32 v7, v4
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v5, v6, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 v7, v5
	s_cbranch_execz .LBB1_16
; %bb.15:                               ;   in Loop: Header=BB1_14 Depth=1
	ds_store_b32 v4, v5
.LBB1_16:                               ;   in Loop: Header=BB1_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v2, s0, v2
	v_add_nc_u32_e32 v3, 4, v3
	s_add_i32 s3, s3, -1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s3, 0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_14
.LBB1_17:                               ; %.loopexit
	ds_load_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9PHASE_TWOiiPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9PHASE_TWOiiPii, .Lfunc_end1-_Z9PHASE_TWOiiPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 720
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11PHASE_THREEiiPii    ; -- Begin function _Z11PHASE_THREEiiPii
	.globl	_Z11PHASE_THREEiiPii
	.p2align	8
	.type	_Z11PHASE_THREEiiPii,@function
_Z11PHASE_THREEiiPii:                   ; @_Z11PHASE_THREEiiPii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s14, s2
	s_cbranch_scc1 .LBB2_11
; %bb.1:
	s_cmp_eq_u32 s15, s2
	s_cbranch_scc1 .LBB2_11
; %bb.2:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x10
	s_load_b64 s[4:5], s[0:1], 0x8
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mul_i32 s1, s3, s2
	v_bfrev_b32_e32 v5, -4
	v_bfrev_b32_e32 v6, -4
	v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
	v_add_nc_u32_e32 v3, s1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s0, s6, v3
	v_cmp_gt_i32_e32 vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_mad_u64_u32 v[6:7], null, v3, s6, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[3:4], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s0, s4, v3
	v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
	global_load_b32 v6, v[3:4], off
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_lo_u32 v7, v0, s3
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	v_add_nc_u32_e32 v0, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e64 s1, s6, v0
	v_lshlrev_b32_e32 v4, 2, v7
	v_lshlrev_b32_e32 v7, 2, v1
	v_cmp_gt_i32_e64 s0, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v7, 0, v4, v7
	s_and_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB2_6
; %bb.5:
	v_mad_u64_u32 v[5:6], null, v3, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s4, v5
	v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
	global_load_b32 v5, v[5:6], off
.LBB2_6:
	s_or_b32 exec_lo, exec_lo, s2
	s_mul_i32 s1, s3, s3
	s_and_b32 s0, s0, vcc_lo
	s_lshl_b32 s1, s1, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, 0, s1, v4
	v_lshl_add_u32 v4, v1, 2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_11
; %bb.7:
	v_mad_u64_u32 v[4:5], null, v3, s6, v[2:3]
	s_cmp_lt_i32 s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_cbranch_scc1 .LBB2_10
; %bb.8:                                ; %.lr.ph
	v_lshl_add_u32 v1, v1, 2, 0
	s_lshl_b32 s0, s3, 2
.LBB2_9:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v0
	ds_load_b32 v6, v1
	v_add_nc_u32_e32 v1, s0, v1
	v_add_nc_u32_e32 v0, 4, v0
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v4, v4, v5
	s_cbranch_scc0 .LBB2_9
.LBB2_10:                               ; %Flow116
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v4, off
.LBB2_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11PHASE_THREEiiPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11PHASE_THREEiiPii, .Lfunc_end2-_Z11PHASE_THREEiiPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9PHASE_ONEiiPii
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z9PHASE_ONEiiPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9PHASE_TWOiiPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9PHASE_TWOiiPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11PHASE_THREEiiPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11PHASE_THREEiiPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
