// Author: Ayush Kumar
// Roll No: 170195
// Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2

#include <algorithm>
#include <cuda.h>
#include <iostream>
#include <sys/time.h>
#include <atomic>

#define THRESHOLD (0.000001)
#define BLOCKSIZE 128
#define CPT 4096
#define FAC 8

using std::cerr;
using std::cout;
using std::endl;

__host__ void host_excl_prefix_sum(float* h_A, float* h_O, int N) {
  h_O[0] = 0;
  for (int i = 1; i < N; i++) {
    h_O[i] = h_O[i - 1] + h_A[i - 1];
  }
} 

__global__ void kernel_excl_prefix_sum_init(float* d_in, float* d_out) {
  int j1 = (blockIdx.x * BLOCKSIZE + threadIdx.x) * CPT;
  float tmp = d_out[j1];
  int unroll = 4;
  int j;
  for (j = j1+1; j+unroll-1 < j1+CPT; j += unroll) {
    tmp = d_in[j-1] + tmp;
    d_out[j] = tmp;
    tmp = d_in[j] + tmp;
    d_out[j+1] = tmp;
    tmp = d_in[j+1] + tmp;
    d_out[j+2] = tmp;
    tmp = d_in[j+2] + tmp;
    d_out[j+3] = tmp;
  }
  for(int j2 = j; j2 < j1+CPT; j2++){
    tmp = d_in[j2-1] + tmp;
    d_out[j2] = tmp;
  }

}

__global__ void kernel_excl_prefix_sum(float* d_in, float* d_out, int N, uint64_t block_coverage) {
  // TODO: Fill in
  int thread_j = (blockIdx.x * BLOCKSIZE + threadIdx.x);
  // every 2*block_coverage cells have block_coverage/8 threads working on them
  int j = (FAC*thread_j/block_coverage)*2*block_coverage + block_coverage + (thread_j % (block_coverage/FAC)) * FAC;
  int base = d_out[j - j%block_coverage-1] + d_in[j-j%block_coverage -1];

  d_out[j] += base;
  d_out[j+1] += base;
  d_out[j+2] += base;
  d_out[j+3] += base;
  d_out[j+4] += base;
  d_out[j+5] += base;
  d_out[j+6] += base;
  d_out[j+7] += base;
}

__host__ void check_result(float* w_ref, float* w_opt, int N) {
  double maxdiff = 0.0, this_diff = 0.0;
  int numdiffs = 0;

  for (int i = 0; i < N; i++) {
    this_diff = w_ref[i] - w_opt[i];
    if (fabs(this_diff) > THRESHOLD) {
      numdiffs++;
      if (this_diff > maxdiff)
        maxdiff = this_diff;
    }
  }

  if (numdiffs > 0) {
    cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
         << endl;
  } else {
    cout << "No differences found between base and test versions\n";
  }
}

__host__ double rtclock() { // Seconds
  struct timezone Tzp;
  struct timeval Tp;
  int stat;
  stat = gettimeofday(&Tp, &Tzp);
  if (stat != 0) {
    cout << "Error return from gettimeofday: " << stat << "\n";
  }
  return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}

int main() {
  const int N = (1 << 24);
  size_t size = N * sizeof(float);

  float* h_in = (float*)malloc(size);
  std::fill_n(h_in, N, 1);

  float* h_excl_sum_out = (float*)malloc(size);
  std::fill_n(h_excl_sum_out, N, 0);

  double clkbegin = rtclock();
  host_excl_prefix_sum(h_in, h_excl_sum_out, N);
  double clkend = rtclock();
  double time = clkend - clkbegin; // seconds
  cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;

  float* h_dev_result = (float*)malloc(size);
  std::fill_n(h_dev_result, N, 0);
  float* d_in;
  float* d_out;
  cudaError_t status;
  cudaEvent_t start, end;
  float k_time; // milliseconds
  // TODO: Fill in
  cudaMalloc(&d_in, size);
  cudaMalloc(&d_out, size);
  dim3 threads_in_block(BLOCKSIZE);
  dim3 blocks_in_grid(N/(BLOCKSIZE*CPT));
  cudaEventCreate(&start);
  cudaEventCreate(&end);
  cudaEventRecord(start, 0);
  /************** CUDA **************/
  cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
  cudaMemset(d_out, 0, size);
  kernel_excl_prefix_sum_init<<<blocks_in_grid, threads_in_block>>>(d_in, d_out);
  uint64_t block_coverage = CPT;
  while(block_coverage < N) {
    blocks_in_grid = (N/(BLOCKSIZE*2*FAC));
    kernel_excl_prefix_sum<<<blocks_in_grid, threads_in_block>>>(d_in, d_out, N, block_coverage);
    block_coverage *= 2;
  }
  cudaMemcpy(h_dev_result, d_out, size, cudaMemcpyDeviceToHost);
  /************** CUDA **************/
  cudaEventRecord(end, 0);
  cudaEventSynchronize(end);
  cudaEventElapsedTime(&k_time, start, end);
  cudaEventDestroy(start);
  cudaEventDestroy(end);
  // for (int i = 0; i < N; i++) {
  //   cout << h_excl_sum_out[i] << ' ';
  // }
  // cout << endl;
  // for(int i = 0; i < N; i++) {
  //   cout << h_dev_result[i] << ' ';
  // }
  // cout << endl;
  check_result(h_excl_sum_out, h_dev_result, N);
  cout << "Kernel time on GPU: " << k_time << " msec" << endl;
  status = cudaGetLastError();
  if (status != cudaSuccess) {
    cerr << "CUDA Error: " << cudaGetErrorString(status) << endl;
  }

  // Free device memory
  cudaFree(d_in);
  cudaFree(d_out);

  free(h_in);
  free(h_excl_sum_out);
  free(h_dev_result);

  return EXIT_SUCCESS;
}

	.file	"tmpxft_0020471f_00000000-6_assignment5-p2.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4173:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4173:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z20host_excl_prefix_sumPfS_i
	.type	_Z20host_excl_prefix_sumPfS_i, @function
_Z20host_excl_prefix_sumPfS_i:
.LFB4167:
	.cfi_startproc
	endbr64
	movl	$0x00000000, (%rsi)
	xorl	%eax, %eax
.L3:
	incq	%rax
	cmpl	%eax, %edx
	jle	.L6
	movss	-4(%rsi,%rax,4), %xmm0
	addss	-4(%rdi,%rax,4), %xmm0
	movss	%xmm0, (%rsi,%rax,4)
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE4167:
	.size	_Z20host_excl_prefix_sumPfS_i, .-_Z20host_excl_prefix_sumPfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	" Diffs found over threshold "
.LC5:
	.string	"; Max Diff = "
.LC6:
	.string	"No differences found between base and test versions\n"
	.text
	.globl	_Z12check_resultPfS_i
	.type	_Z12check_resultPfS_i, @function
_Z12check_resultPfS_i:
.LFB4168:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, %rcx
	xorl	%eax, %eax
	xorl	%esi, %esi
	movq	.LC2(%rip), %xmm2
	movsd	.LC3(%rip), %xmm3
	xorps	%xmm1, %xmm1
.L8:
	cmpl	%eax, %edx
	jle	.L16
	movss	(%rdi,%rax,4), %xmm0
	subss	(%rcx,%rax,4), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movaps	%xmm0, %xmm4
	andps	%xmm2, %xmm4
	comisd	%xmm3, %xmm4
	jbe	.L9
	maxsd	%xmm1, %xmm0
	incl	%esi
	movaps	%xmm0, %xmm1
.L9:
	incq	%rax
	jmp	.L8
.L16:
	testl	%esi, %esi
	movsd	%xmm1, 8(%rsp)
	leaq	_ZSt4cout(%rip), %rdi
	jle	.L12
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC3(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm1
	movq	%rax, %rdi
	movaps	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	movq	%rax, %rdi
	jmp	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L12:
	.cfi_restore_state
	leaq	.LC6(%rip), %rsi
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	jmp	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	.cfi_endproc
.LFE4168:
	.size	_Z12check_resultPfS_i, .-_Z12check_resultPfS_i
	.section	.rodata.str1.1
.LC7:
	.string	"Error return from gettimeofday: "
.LC8:
	.string	"\n"
	.text
	.globl	_Z7rtclockv
	.type	_Z7rtclockv, @function
_Z7rtclockv:
.LFB4169:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rsi
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	testl	%eax, %eax
	je	.L18
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movl	%eax, %ebx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L18:
	cvtsi2sdq	16(%rsp), %xmm0
	mulsd	.LC3(%rip), %xmm0
	cvtsi2sdq	8(%rsp), %xmm1
	addsd	%xmm1, %xmm0
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4169:
	.size	_Z7rtclockv, .-_Z7rtclockv
	.globl	_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_
	.type	_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_, @function
_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_:
.LFB4195:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z27kernel_excl_prefix_sum_initPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L24:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4195:
	.size	_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_, .-_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_
	.globl	_Z27kernel_excl_prefix_sum_initPfS_
	.type	_Z27kernel_excl_prefix_sum_initPfS_, @function
_Z27kernel_excl_prefix_sum_initPfS_:
.LFB4196:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_
	.cfi_endproc
.LFE4196:
	.size	_Z27kernel_excl_prefix_sum_initPfS_, .-_Z27kernel_excl_prefix_sum_initPfS_
	.globl	_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im
	.type	_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im, @function
_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im:
.LFB4197:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22kernel_excl_prefix_sumPfS_im(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L29:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4197:
	.size	_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im, .-_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im
	.globl	_Z22kernel_excl_prefix_sumPfS_im
	.type	_Z22kernel_excl_prefix_sumPfS_im, @function
_Z22kernel_excl_prefix_sumPfS_im:
.LFB4198:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im
	.cfi_endproc
.LFE4198:
	.size	_Z22kernel_excl_prefix_sumPfS_im, .-_Z22kernel_excl_prefix_sumPfS_im
	.section	.rodata.str1.1
.LC10:
	.string	"Serial time on CPU: "
.LC12:
	.string	" msec"
.LC13:
	.string	"Kernel time on GPU: "
.LC14:
	.string	"CUDA Error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4170:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$67108864, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movss	.LC9(%rip), %xmm0
	movq	%rax, %r12
	xorl	%eax, %eax
.L35:
	movss	%xmm0, (%r12,%rax)
	addq	$4, %rax
	cmpq	$67108864, %rax
	jne	.L35
	movl	$67108864, %edi
	call	malloc@PLT
	movq	%rax, %rbp
	xorl	%eax, %eax
.L36:
	movl	$0x00000000, 0(%rbp,%rax)
	addq	$4, %rax
	cmpq	$67108864, %rax
	jne	.L36
	call	_Z7rtclockv
	movl	$16777216, %edx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	movsd	%xmm0, 8(%rsp)
	leaq	_ZSt4cout(%rip), %r15
	call	_Z20host_excl_prefix_sumPfS_i
	call	_Z7rtclockv
	subsd	8(%rsp), %xmm0
	leaq	.LC10(%rip), %rsi
	movq	%r15, %rdi
	movsd	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	mulsd	.LC11(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$67108864, %edi
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L37:
	movl	$0x00000000, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$67108864, %rax
	jne	.L37
	leaq	32(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movl	$67108864, %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$33554433, %eax
	leaq	48(%rsp), %rdi
	movl	$1, 72(%rsp)
	salq	$7, %rax
	movl	$1, 84(%rsp)
	movq	%rax, 64(%rsp)
	subq	$96, %rax
	movq	%rax, 76(%rsp)
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	movl	$67108864, %edx
	call	cudaMemset@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z49__device_stub__Z27kernel_excl_prefix_sum_initPfS_PfS_
.L38:
	movl	$12, %r14d
	movl	$4096, %r13d
.L40:
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8192, 76(%rsp)
	movl	84(%rsp), %esi
	movq	76(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	movq	%r13, %rcx
	movl	$16777216, %edx
	call	_Z46__device_stub__Z22kernel_excl_prefix_sumPfS_imPfS_im
.L39:
	addq	%r13, %r13
	decl	%r14d
	jne	.L40
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$67108864, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movl	$16777216, %edx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	call	_Z12check_resultPfS_i
	leaq	.LC13(%rip), %rsi
	movq	%r15, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	28(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	je	.L41
	leaq	.LC14(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %edi
	movq	%rax, %r14
	call	cudaGetErrorString@PLT
	movq	%r14, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L41:
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4170:
	.size	main, .-main
	.section	.rodata.str1.1
.LC15:
	.string	"_Z22kernel_excl_prefix_sumPfS_im"
.LC16:
	.string	"_Z27kernel_excl_prefix_sum_initPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4200:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22kernel_excl_prefix_sumPfS_im(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z27kernel_excl_prefix_sum_initPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4200:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	-1598689907
	.long	1051772663
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC9:
	.long	1065353216
	.section	.rodata.cst8
	.align 8
.LC11:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Author: Ayush Kumar
// Roll No: 170195
// Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2

#include <algorithm>
#include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#include <atomic>

#define THRESHOLD (0.000001)
#define BLOCKSIZE 128
#define CPT 4096
#define FAC 8

using std::cerr;
using std::cout;
using std::endl;

__host__ void host_excl_prefix_sum(float* h_A, float* h_O, int N) {
  h_O[0] = 0;
  for (int i = 1; i < N; i++) {
    h_O[i] = h_O[i - 1] + h_A[i - 1];
  }
} 

__global__ void kernel_excl_prefix_sum_init(float* d_in, float* d_out) {
  int j1 = (blockIdx.x * BLOCKSIZE + threadIdx.x) * CPT;
  float tmp = d_out[j1];
  int unroll = 4;
  int j;
  for (j = j1+1; j+unroll-1 < j1+CPT; j += unroll) {
    tmp = d_in[j-1] + tmp;
    d_out[j] = tmp;
    tmp = d_in[j] + tmp;
    d_out[j+1] = tmp;
    tmp = d_in[j+1] + tmp;
    d_out[j+2] = tmp;
    tmp = d_in[j+2] + tmp;
    d_out[j+3] = tmp;
  }
  for(int j2 = j; j2 < j1+CPT; j2++){
    tmp = d_in[j2-1] + tmp;
    d_out[j2] = tmp;
  }

}

__global__ void kernel_excl_prefix_sum(float* d_in, float* d_out, int N, uint64_t block_coverage) {
  // TODO: Fill in
  int thread_j = (blockIdx.x * BLOCKSIZE + threadIdx.x);
  // every 2*block_coverage cells have block_coverage/8 threads working on them
  int j = (FAC*thread_j/block_coverage)*2*block_coverage + block_coverage + (thread_j % (block_coverage/FAC)) * FAC;
  int base = d_out[j - j%block_coverage-1] + d_in[j-j%block_coverage -1];

  d_out[j] += base;
  d_out[j+1] += base;
  d_out[j+2] += base;
  d_out[j+3] += base;
  d_out[j+4] += base;
  d_out[j+5] += base;
  d_out[j+6] += base;
  d_out[j+7] += base;
}

__host__ void check_result(float* w_ref, float* w_opt, int N) {
  double maxdiff = 0.0, this_diff = 0.0;
  int numdiffs = 0;

  for (int i = 0; i < N; i++) {
    this_diff = w_ref[i] - w_opt[i];
    if (fabs(this_diff) > THRESHOLD) {
      numdiffs++;
      if (this_diff > maxdiff)
        maxdiff = this_diff;
    }
  }

  if (numdiffs > 0) {
    cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
         << endl;
  } else {
    cout << "No differences found between base and test versions\n";
  }
}

__host__ double rtclock() { // Seconds
  struct timezone Tzp;
  struct timeval Tp;
  int stat;
  stat = gettimeofday(&Tp, &Tzp);
  if (stat != 0) {
    cout << "Error return from gettimeofday: " << stat << "\n";
  }
  return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}

int main() {
  const int N = (1 << 24);
  size_t size = N * sizeof(float);

  float* h_in = (float*)malloc(size);
  std::fill_n(h_in, N, 1);

  float* h_excl_sum_out = (float*)malloc(size);
  std::fill_n(h_excl_sum_out, N, 0);

  double clkbegin = rtclock();
  host_excl_prefix_sum(h_in, h_excl_sum_out, N);
  double clkend = rtclock();
  double time = clkend - clkbegin; // seconds
  cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;

  float* h_dev_result = (float*)malloc(size);
  std::fill_n(h_dev_result, N, 0);
  float* d_in;
  float* d_out;
  hipError_t status;
  hipEvent_t start, end;
  float k_time; // milliseconds
  // TODO: Fill in
  hipMalloc(&d_in, size);
  hipMalloc(&d_out, size);
  dim3 threads_in_block(BLOCKSIZE);
  dim3 blocks_in_grid(N/(BLOCKSIZE*CPT));
  hipEventCreate(&start);
  hipEventCreate(&end);
  hipEventRecord(start, 0);
  /************** CUDA **************/
  hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
  hipMemset(d_out, 0, size);
  kernel_excl_prefix_sum_init<<<blocks_in_grid, threads_in_block>>>(d_in, d_out);
  uint64_t block_coverage = CPT;
  while(block_coverage < N) {
    blocks_in_grid = (N/(BLOCKSIZE*2*FAC));
    kernel_excl_prefix_sum<<<blocks_in_grid, threads_in_block>>>(d_in, d_out, N, block_coverage);
    block_coverage *= 2;
  }
  hipMemcpy(h_dev_result, d_out, size, hipMemcpyDeviceToHost);
  /************** CUDA **************/
  hipEventRecord(end, 0);
  hipEventSynchronize(end);
  hipEventElapsedTime(&k_time, start, end);
  hipEventDestroy(start);
  hipEventDestroy(end);
  // for (int i = 0; i < N; i++) {
  //   cout << h_excl_sum_out[i] << ' ';
  // }
  // cout << endl;
  // for(int i = 0; i < N; i++) {
  //   cout << h_dev_result[i] << ' ';
  // }
  // cout << endl;
  check_result(h_excl_sum_out, h_dev_result, N);
  cout << "Kernel time on GPU: " << k_time << " msec" << endl;
  status = hipGetLastError();
  if (status != hipSuccess) {
    cerr << "CUDA Error: " << hipGetErrorString(status) << endl;
  }

  // Free device memory
  hipFree(d_in);
  hipFree(d_out);

  free(h_in);
  free(h_excl_sum_out);
  free(h_dev_result);

  return EXIT_SUCCESS;
}

	.text
	.file	"assignment5-p2.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z20host_excl_prefix_sumPfS_i   # -- Begin function _Z20host_excl_prefix_sumPfS_i
	.type	_Z20host_excl_prefix_sumPfS_i,@function
_Z20host_excl_prefix_sumPfS_i:          # @_Z20host_excl_prefix_sumPfS_i
	.cfi_startproc
# %bb.0:
	movl	$0, (%rsi)
	cmpl	$2, %edx
	jl	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %eax
	decq	%rax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rdi,%rcx,4), %xmm0
	movss	%xmm0, 4(%rsi,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z20host_excl_prefix_sumPfS_i, .Lfunc_end0-_Z20host_excl_prefix_sumPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__kernel_excl_prefix_sum_initPfS_ # -- Begin function _Z42__device_stub__kernel_excl_prefix_sum_initPfS_
	.type	_Z42__device_stub__kernel_excl_prefix_sum_initPfS_,@function
_Z42__device_stub__kernel_excl_prefix_sum_initPfS_: # @_Z42__device_stub__kernel_excl_prefix_sum_initPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27kernel_excl_prefix_sum_initPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z42__device_stub__kernel_excl_prefix_sum_initPfS_, .Lfunc_end1-_Z42__device_stub__kernel_excl_prefix_sum_initPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__kernel_excl_prefix_sumPfS_im # -- Begin function _Z37__device_stub__kernel_excl_prefix_sumPfS_im
	.type	_Z37__device_stub__kernel_excl_prefix_sumPfS_im,@function
_Z37__device_stub__kernel_excl_prefix_sumPfS_im: # @_Z37__device_stub__kernel_excl_prefix_sumPfS_im
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22kernel_excl_prefix_sumPfS_im, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z37__device_stub__kernel_excl_prefix_sumPfS_im, .Lfunc_end2-_Z37__device_stub__kernel_excl_prefix_sumPfS_im
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z12check_resultPfS_i
.LCPI3_0:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI3_1:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	_Z12check_resultPfS_i
	.type	_Z12check_resultPfS_i,@function
_Z12check_resultPfS_i:                  # @_Z12check_resultPfS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB3_8
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %ecx
	xorpd	%xmm4, %xmm4
	xorl	%edx, %edx
	movaps	.LCPI3_0(%rip), %xmm0           # xmm0 = [NaN,NaN]
	movsd	.LCPI3_1(%rip), %xmm1           # xmm1 = mem[0],zero
	xorl	%eax, %eax
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rdi,%rdx,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%rsi,%rdx,4), %xmm2
	cvtss2sd	%xmm2, %xmm2
	movaps	%xmm2, %xmm3
	andps	%xmm0, %xmm3
	ucomisd	%xmm1, %xmm3
	jbe	.LBB3_5
# %bb.3:                                #   in Loop: Header=BB3_2 Depth=1
	incl	%eax
	ucomisd	%xmm4, %xmm2
	jbe	.LBB3_5
# %bb.4:                                #   in Loop: Header=BB3_2 Depth=1
	movapd	%xmm2, %xmm4
.LBB3_5:                                #   in Loop: Header=BB3_2 Depth=1
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB3_2
# %bb.6:                                # %._crit_edge
	testl	%eax, %eax
	jle	.LBB3_8
# %bb.7:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	$_ZSt4cout, %edi
	movl	%eax, %esi
	movsd	%xmm4, 8(%rsp)                  # 8-byte Spill
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str, %esi
	movl	$28, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.LBB3_8:                                # %._crit_edge.thread
	.cfi_restore %rbx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$52, %edx
	jmp	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end3:
	.size	_Z12check_resultPfS_i, .Lfunc_end3-_Z12check_resultPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7rtclockv
.LCPI4_0:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	_Z7rtclockv
	.type	_Z7rtclockv,@function
_Z7rtclockv:                            # @_Z7rtclockv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rdi
	leaq	24(%rsp), %rsi
	callq	gettimeofday
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	movl	%eax, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$32, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movl	$.L.str.4, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB4_2:
	cvtsi2sdq	8(%rsp), %xmm1
	cvtsi2sdq	16(%rsp), %xmm0
	mulsd	.LCPI4_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z7rtclockv, .Lfunc_end4-_Z7rtclockv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB5_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax)        # imm = 0x3F800000
	addq	$4, %rax
	cmpq	$67108864, %rax                 # imm = 0x4000000
	jne	.LBB5_1
# %bb.2:                                # %_ZSt6fill_nIPfiiET_S1_T0_RKT1_.exit
	movl	$1, %r15d
	movl	$1, %edi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	calloc@PLT
	movq	%rax, %r14
	callq	_Z7rtclockv
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	xorps	%xmm0, %xmm0
.LBB5_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	addss	-4(%rbx,%r15,4), %xmm0
	movss	%xmm0, (%r14,%r15,4)
	incq	%r15
	cmpq	$16777216, %r15                 # imm = 0x1000000
	jne	.LBB5_3
# %bb.4:                                # %_Z20host_excl_prefix_sumPfS_i.exit
	movabsq	$4294967424, %r12               # imm = 0x100000080
	callq	_Z7rtclockv
	subsd	8(%rsp), %xmm0                  # 8-byte Folded Reload
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	mulsd	.LCPI5_0(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.6, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$1, %edi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	calloc@PLT
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	leaq	32(%rsp), %rbp
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r13
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rbp), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	xorl	%esi, %esi
	callq	hipMemset
	leaq	-96(%r12), %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z42__device_stub__kernel_excl_prefix_sum_initPfS_
.LBB5_6:                                # %.preheader
	movl	$4096, %ebp                     # imm = 0x1000
	leaq	8064(%r12), %r13
.LBB5_7:                                # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_9
# %bb.8:                                #   in Loop: Header=BB5_7 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	movq	%rbp, %rcx
	callq	_Z37__device_stub__kernel_excl_prefix_sumPfS_im
.LBB5_9:                                #   in Loop: Header=BB5_7 Depth=1
	leaq	(,%rbp,2), %rax
	cmpq	$8388608, %rbp                  # imm = 0x800000
	movq	%rax, %rbp
	jb	.LBB5_7
# %bb.10:
	movq	24(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	8(%rsp), %r13                   # 8-byte Reload
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	52(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	%r14, %rdi
	movq	%r13, %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	callq	_Z12check_resultPfS_i
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%r15), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.6, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB5_15
# %bb.11:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.8, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB5_12
# %bb.13:
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%r12, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB5_14
.LBB5_12:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB5_14:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB5_15:
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27kernel_excl_prefix_sum_initPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22kernel_excl_prefix_sumPfS_im, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z27kernel_excl_prefix_sum_initPfS_,@object # @_Z27kernel_excl_prefix_sum_initPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z27kernel_excl_prefix_sum_initPfS_
	.p2align	3, 0x0
_Z27kernel_excl_prefix_sum_initPfS_:
	.quad	_Z42__device_stub__kernel_excl_prefix_sum_initPfS_
	.size	_Z27kernel_excl_prefix_sum_initPfS_, 8

	.type	_Z22kernel_excl_prefix_sumPfS_im,@object # @_Z22kernel_excl_prefix_sumPfS_im
	.globl	_Z22kernel_excl_prefix_sumPfS_im
	.p2align	3, 0x0
_Z22kernel_excl_prefix_sumPfS_im:
	.quad	_Z37__device_stub__kernel_excl_prefix_sumPfS_im
	.size	_Z22kernel_excl_prefix_sumPfS_im, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" Diffs found over threshold "
	.size	.L.str, 29

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"; Max Diff = "
	.size	.L.str.1, 14

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"No differences found between base and test versions\n"
	.size	.L.str.2, 53

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Error return from gettimeofday: "
	.size	.L.str.3, 33

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\n"
	.size	.L.str.4, 2

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Serial time on CPU: "
	.size	.L.str.5, 21

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	" msec"
	.size	.L.str.6, 6

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Kernel time on GPU: "
	.size	.L.str.7, 21

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"CUDA Error: "
	.size	.L.str.8, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z27kernel_excl_prefix_sum_initPfS_"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z22kernel_excl_prefix_sumPfS_im"
	.size	.L__unnamed_2, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z42__device_stub__kernel_excl_prefix_sum_initPfS_
	.addrsig_sym _Z37__device_stub__kernel_excl_prefix_sumPfS_im
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z27kernel_excl_prefix_sum_initPfS_
	.addrsig_sym _Z22kernel_excl_prefix_sumPfS_im
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z27kernel_excl_prefix_sum_initPfS_ ; -- Begin function _Z27kernel_excl_prefix_sum_initPfS_
	.globl	_Z27kernel_excl_prefix_sum_initPfS_
	.p2align	8
	.type	_Z27kernel_excl_prefix_sum_initPfS_,@function
_Z27kernel_excl_prefix_sum_initPfS_:    ; @_Z27kernel_excl_prefix_sum_initPfS_
; %bb.0:                                ; %.lr.ph.preheader
	v_lshlrev_b32_e32 v0, 12, v0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s15, 19, v0
	v_ashrrev_i32_e32 v3, 31, v2
	v_or_b32_e32 v9, 0xff9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v8, v[3:4], off
	v_add_nc_u32_e32 v3, -3, v2
.LBB0_1:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v6, v[4:5], off
	s_add_u32 s2, s2, 16
	s_addc_u32 s3, s3, 0
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	v_add_nc_u32_e32 v3, 4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v3, v9
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v8, v6
	global_store_b32 v[10:11], v6, off offset:4
	global_load_b32 v7, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	global_store_b32 v[10:11], v6, off offset:8
	global_load_b32 v7, v[4:5], off offset:8
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v8, v6, v7 :: v_dual_mov_b32 v7, s3
	v_mov_b32_e32 v6, s2
	global_store_b32 v[10:11], v8, off offset:12
	global_load_b32 v4, v[4:5], off offset:12
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v8, v8, v4 :: v_dual_mov_b32 v5, s1
	v_mov_b32_e32 v4, s0
	global_store_b32 v[10:11], v8, off offset:16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_1
; %bb.2:                                ; %.preheader
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v9, 4, v3
	v_add_nc_u32_e32 v10, 0x1000, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v9, v10
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph51.preheader
	v_add_co_u32 v2, vcc_lo, v6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v1, vcc_lo
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
.LBB0_4:                                ; %.lr.ph51
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[0:1], off
	v_add_nc_u32_e32 v9, 1, v9
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v8, v8, v4
	v_cmp_ge_i32_e32 vcc_lo, v9, v10
	global_store_b32 v[2:3], v8, off
	v_add_co_u32 v2, s0, v2, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %Flow94
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27kernel_excl_prefix_sum_initPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z27kernel_excl_prefix_sum_initPfS_, .Lfunc_end0-_Z27kernel_excl_prefix_sum_initPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 428
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22kernel_excl_prefix_sumPfS_im ; -- Begin function _Z22kernel_excl_prefix_sumPfS_im
	.globl	_Z22kernel_excl_prefix_sumPfS_im
	.p2align	8
	.type	_Z22kernel_excl_prefix_sumPfS_im,@function
_Z22kernel_excl_prefix_sumPfS_im:       ; @_Z22kernel_excl_prefix_sumPfS_im
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s8
	v_cvt_f32_u32_e32 v2, s9
	v_alignbit_b32 v7, s9, s8, 3
	s_sub_u32 s5, 0, s8
	s_subb_u32 s6, 0, s9
	s_lshr_b32 s4, s9, 3
	s_lshr_b64 s[2:3], s[8:9], 3
	v_cvt_f32_u32_e32 v3, s4
	v_cvt_f32_u32_e32 v6, v7
	v_fmac_f32_e32 v1, 0x4f800000, v2
	s_sub_u32 s2, 0, s2
	s_subb_u32 s3, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, 0x4f800000, v3
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s5, v2
	v_mul_hi_u32 v5, s5, v1
	v_mul_lo_u32 v8, s6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v5, v4
	v_rcp_f32_e32 v5, v6
	v_mul_lo_u32 v4, s5, v1
	v_mul_hi_u32 v6, v1, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x5f7ffffc, v5
	v_add_nc_u32_e32 v3, v3, v8
	v_mul_hi_u32 v10, v2, v4
	v_mul_lo_u32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v1, v3
	v_mul_hi_u32 v9, v1, v3
	v_add_co_u32 v6, vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v10, vcc_lo
	v_mul_f32_e32 v8, 0x2f800000, v5
	v_mul_hi_u32 v11, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v1, v3
	v_trunc_f32_e32 v6, v8
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
	v_lshl_add_u32 v8, s15, 7, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v0, s5, v1
	v_mul_lo_u32 v4, s6, v1
	v_mul_lo_u32 v3, s5, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 3, v8
	v_ashrrev_i32_e32 v13, 31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_lo_u32 v3, s5, v1
	v_dual_fmac_f32 v5, 0xcf800000, v6 :: v_dual_add_nc_u32 v0, v0, v4
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v18, v2, v3
	v_mul_lo_u32 v14, v1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v9, v5
	v_mul_lo_u32 v5, s2, v6
	v_mul_hi_u32 v16, v1, v0
	v_mul_hi_u32 v19, v2, v0
	v_mul_lo_u32 v0, v2, v0
	v_mul_hi_u32 v11, s2, v9
	v_mul_lo_u32 v4, s3, v9
	v_mul_lo_u32 v12, s2, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v11, v5
	v_mul_hi_u32 v11, v1, v3
	v_mul_lo_u32 v3, v2, v3
	v_mul_hi_u32 v15, v9, v12
	v_mul_hi_u32 v17, v6, v12
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v12, v6, v12
	v_add_co_u32 v11, vcc_lo, v11, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v9, v4
	v_add_co_u32 v3, vcc_lo, v11, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, v14, v18, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v19, vcc_lo
	v_mul_lo_u32 v18, v9, v4
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
	v_mul_hi_u32 v20, v6, v4
	v_add_co_u32 v11, vcc_lo, v1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, v2, v3, vcc_lo
	v_mul_lo_u32 v21, v6, v4
	v_mul_hi_u32 v19, v10, v11
	v_mad_u64_u32 v[2:3], null, v13, v11, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, v10, v14, 0
	v_mad_u64_u32 v[4:5], null, v13, v14, 0
	v_add_co_u32 v0, vcc_lo, v19, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v15, vcc_lo, v15, v18
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v0, vcc_lo, v1, v3, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, v15, v12
	v_add_co_ci_u32_e32 v2, vcc_lo, v16, v17, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo
	v_add_co_u32 v12, vcc_lo, v0, v4
	v_mul_hi_u32 v5, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s2, v3
	v_mul_lo_u32 v9, s3, v2
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v4, v5, v9
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	v_mul_lo_u32 v9, s9, v12
	v_mul_hi_u32 v15, v2, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v16, v2, v4
	v_mul_hi_u32 v17, v2, v4
	v_mul_hi_u32 v18, v3, v6
	v_mul_lo_u32 v6, v3, v6
	v_mul_hi_u32 v19, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_mad_u64_u32 v[0:1], null, s8, v12, 0
	v_add_co_u32 v15, vcc_lo, v15, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	v_mul_lo_u32 v5, s8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v15, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, v16, v18, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
	v_sub_co_u32 v10, s2, v10, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v6, v4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v15, vcc_lo
	v_ashrrev_i32_e32 v15, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v17, vcc_lo, v3, v6, vcc_lo
	v_add3_u32 v9, v1, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v19, v8, v16
	v_mad_u64_u32 v[3:4], null, v15, v16, 0
	v_mad_u64_u32 v[1:2], null, v8, v17, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v21, v13, v9
	v_mad_u64_u32 v[5:6], null, v15, v17, 0
	v_add_nc_u32_e32 v18, 2, v12
	v_add_co_u32 v1, vcc_lo, v19, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_subrev_co_ci_u32_e64 v16, vcc_lo, s9, v21, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v1, v3
	v_add_co_ci_u32_e32 v0, vcc_lo, v2, v4, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v6, vcc_lo
	v_sub_co_u32 v2, vcc_lo, v10, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, s3, v0, v5
	v_sub_co_ci_u32_e64 v5, s2, v13, v9, s2
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	v_add_co_ci_u32_e64 v4, s3, 0, v1, s3
	v_mul_lo_u32 v6, s4, v3
	v_mad_u64_u32 v[0:1], null, v7, v3, 0
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v5
	v_mul_lo_u32 v3, v7, v4
	v_cmp_le_u32_e64 s2, s8, v10
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, 0, -1, s2
	v_add3_u32 v1, v1, v3, v6
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s9, v5
	v_sub_nc_u32_e32 v5, v15, v1
	v_cndmask_b32_e32 v4, v10, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s9, v9
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	v_sub_co_u32 v0, vcc_lo, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v3, s2, s4, v5, vcc_lo
	v_sub_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
	v_sub_co_u32 v5, vcc_lo, v0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v0, v7
	v_cndmask_b32_e64 v6, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v5, v7
	v_sub_nc_u32_e32 v7, v5, v7
	v_add_nc_u32_e32 v20, 1, v12
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v9, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v2, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s4, v1
	s_load_b128 s[4:7], s[0:1], 0x0
	v_cndmask_b32_e32 v1, v10, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, v5, v7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v2, v12, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v6, v2, 1, 1
	v_dual_cndmask_b32 v1, v0, v3 :: v_dual_mov_b32 v0, 0
	v_lshlrev_b32_e32 v1, 3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, 0, v6, v[0:1]
	v_mov_b32_e32 v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s8, v6, v[0:1]
	v_ashrrev_i32_e32 v15, 31, v4
	v_mad_u64_u32 v[0:1], null, v4, v14, 0
	v_mul_hi_u32 v3, v4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, v15, v11, 0
	v_mad_u64_u32 v[7:8], null, v15, v14, 0
	v_add_co_u32 v0, vcc_lo, v3, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v0, vcc_lo, v1, v6, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v7, s9, v3
	v_mad_u64_u32 v[0:1], null, s8, v3, 0
	v_mov_b32_e32 v3, v4
	v_mul_lo_u32 v8, s8, v5
	v_add_co_u32 v5, vcc_lo, v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s2, 1, v3, vcc_lo
	v_add3_u32 v9, v1, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ashrrev_i64 v[7:8], 30, v[5:6]
	v_add_co_ci_u32_e64 v6, s0, 2, v3, vcc_lo
	v_sub_co_u32 v11, s0, v4, v0
	v_sub_nc_u32_e32 v10, v15, v9
	v_ashrrev_i64 v[1:2], 30, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v0, s1, s9, v10, s0
	v_sub_co_ci_u32_e64 v12, s0, v15, v9, s0
	v_sub_co_u32 v9, s0, v11, s8
	v_subrev_co_ci_u32_e64 v10, s1, 0, v0, s0
	v_cmp_le_u32_e64 s1, s8, v11
	v_subrev_co_ci_u32_e64 v0, s0, s9, v0, s0
	v_cmp_le_u32_e64 s0, s9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, 0, -1, s1
	v_cmp_le_u32_e64 s1, s8, v9
	v_cndmask_b32_e64 v17, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, -1, s1
	v_cmp_le_u32_e64 s1, s9, v10
	v_cndmask_b32_e64 v16, 0, -1, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v16, v14, s0
	v_sub_co_u32 v16, s0, v9, s8
	v_subrev_co_ci_u32_e64 v18, s0, 0, v0, s0
	v_cmp_eq_u32_e64 s0, s9, v12
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, s1, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s1, s7, v2, s1
	v_cndmask_b32_e64 v13, v17, v13, s0
	v_cmp_ne_u32_e64 s0, 0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, v10, v18, s0
	v_cndmask_b32_e64 v14, v9, v16, s0
	v_cmp_ne_u32_e64 s0, 0, v13
	v_ashrrev_i64 v[9:10], 30, v[5:6]
	v_add_co_ci_u32_e64 v6, s1, 3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, v11, v14, s0
	v_cndmask_b32_e64 v2, v12, v2, s0
	v_add_co_u32 v7, s0, s6, v7
	v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_not_b32_e32 v13, v13
	v_not_b32_e32 v2, v2
	v_ashrrev_i64 v[11:12], 30, v[5:6]
	v_add_co_ci_u32_e64 v6, s0, 4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s0, v4, v13
	v_add_co_ci_u32_e64 v14, s0, v15, v2, s0
	v_add_co_u32 v9, s0, s6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	v_ashrrev_i64 v[15:16], 30, v[5:6]
	v_add_co_ci_u32_e64 v6, s0, 5, v3, vcc_lo
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v11, s0, s6, v11
	v_add_co_ci_u32_e64 v12, s0, s7, v12, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i64 v[17:18], 30, v[5:6]
	v_add_co_ci_u32_e64 v6, s0, 6, v3, vcc_lo
	v_add_co_u32 v19, s0, s6, v13
	v_add_co_ci_u32_e64 v20, s0, s7, v14, s0
	v_add_co_u32 v13, s0, s4, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
	global_load_b32 v19, v[19:20], off
	global_load_b32 v20, v[13:14], off
	v_ashrrev_i64 v[21:22], 30, v[5:6]
	v_add_co_ci_u32_e32 v6, vcc_lo, 7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i64 v[4:5], 30, v[5:6]
	v_add_co_u32 v13, vcc_lo, s6, v21
	v_add_co_u32 v15, s0, s6, v15
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v22, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e64 v16, s0, s7, v16, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_clause 0x7
	global_load_b32 v6, v[0:1], off
	global_load_b32 v17, v[7:8], off
	global_load_b32 v18, v[9:10], off
	global_load_b32 v21, v[11:12], off
	global_load_b32 v22, v[15:16], off
	global_load_b32 v23, v[2:3], off
	global_load_b32 v24, v[13:14], off
	global_load_b32 v25, v[4:5], off
	s_waitcnt vmcnt(8)
	v_add_f32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v19, v19
	v_cvt_f32_i32_e32 v19, v19
	s_waitcnt vmcnt(7)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v19
	s_waitcnt vmcnt(6)
	v_add_f32_e32 v17, v17, v19
	s_waitcnt vmcnt(5)
	v_add_f32_e32 v18, v18, v19
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v20, v21, v19
	s_waitcnt vmcnt(3)
	v_add_f32_e32 v21, v22, v19
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v22, v23, v19
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v23, v24, v19
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v19, v25, v19
	s_clause 0x7
	global_store_b32 v[0:1], v6, off
	global_store_b32 v[7:8], v17, off
	global_store_b32 v[9:10], v18, off
	global_store_b32 v[11:12], v20, off
	global_store_b32 v[15:16], v21, off
	global_store_b32 v[2:3], v22, off
	global_store_b32 v[13:14], v23, off
	global_store_b32 v[4:5], v19, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22kernel_excl_prefix_sumPfS_im
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z22kernel_excl_prefix_sumPfS_im, .Lfunc_end1-_Z22kernel_excl_prefix_sumPfS_im
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2412
; NumSgprs: 18
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27kernel_excl_prefix_sum_initPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z27kernel_excl_prefix_sum_initPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22kernel_excl_prefix_sumPfS_im
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22kernel_excl_prefix_sumPfS_im.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
