#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;

#define  i_size 6//image size
#define o_size 6
#define k_size 3//kernel size
int input[i_size][i_size];
int kernel[k_size][k_size];
int output[i_size][i_size];
typedef int itype[i_size];
typedef int ktype[k_size];
void fill_image(int m[i_size][i_size]) {
	static int n = 0; int i, j;
	for (i = 0; i < i_size; i++)
		for (j = 0; j < i_size; j++)
			m[i][j] = n++;
}

void fill_kernel(int m[k_size][k_size]) {
	static int n = 0; int i, j;
	for (i = 0; i < k_size; i++)
		for (j = 0; j < k_size; j++)
			m[i][j] = n++;
}
void fill_output(int m[i_size][i_size]) {
	int i, j;

	for (i = 0; i < o_size; i++) {
		cout << "\n \t\t |";
		for (j = 0; j < o_size; j++)
			cout << "\t\t" << m[i][j];
		cout << "|";
	}

}
__global__ void add_arrays_gpu(int* a, int *b, int* c)
{
	c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
__global__ void processing(itype  *a,ktype *kernel, itype *o)
{
	
	int r = 0;
	int i = (blockIdx.y*blockDim.y + threadIdx.y)+1;
	int j = (blockIdx.x*blockDim.x + threadIdx.x)+1;
	
	
	for (int k = -1; k < 2; k++)
	{
		for (int m = -1; m < 2; m++)
		{

			r += a[i + k][j + m] * kernel[k + 1][m + 1];
			o[i][j] = r;
		}

	}
}




int main()
{fill_image(input);
fill_kernel(kernel);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);


	itype *device_a, *device_c;
	ktype *device_b;
	const int size = i_size*i_size * sizeof(int);
	
	size_t pitch;
	cudaMallocPitch((void**)&device_a, &pitch, i_size * sizeof(float), i_size);
	cudaMallocPitch((void**)&device_b, &pitch, k_size * sizeof(float), k_size);
	cudaMallocPitch((void**)&device_c, &pitch, i_size * sizeof(float), i_size);
	dim3 blockspergrid(2,2,1);
	dim3 threadperblock(2,2,1);
	cudaMemcpy(
		device_a, input,
		size,
		cudaMemcpyHostToDevice
	);

	cudaMemcpy(
		device_b, kernel,
		size,
		cudaMemcpyHostToDevice
	);
	int r = 0;
	//add_arra<< <1, count >> > (device_a, device_b, device_c);
	cudaEventRecord(start);
	//processing <<<blockspergrid, threadperblock >> > (device_a,device_b,device_c);
	for (int i = 1; i < i_size - 1; i++)
	{
		for (int j = 1; j < i_size - 1; j++)
			for (int k = -1; k < 2; k++)
			{
				for (int m = -1; m < 2; m++)
				{

					r += input[i + k][j + m] * kernel[k + 1][m + 1];
					output[i][j] = r;
				}

			}
	}




	cudaEventRecord(stop);
	
	/*cudaMemcpy(
		output, device_c,
		size,
		cudaMemcpyDeviceToHost
	);*/
	cudaEventSynchronize(stop);
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);
	cout << "\n total time to execute operation is " << milliseconds << "\n";
	fill_output(output);
	

	//getchar();

	return 0;
}
	.file	"tmpxft_003a3780_00000000-6_image_processing.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10fill_imagePA6_i
	.type	_Z10fill_imagePA6_i, @function
_Z10fill_imagePA6_i:
.LFB3635:
	.cfi_startproc
	endbr64
	movl	_ZZ10fill_imagePA6_iE1n(%rip), %edx
	leaq	144(%rdi), %rsi
	movl	%edx, %ecx
.L3:
	xorl	%eax, %eax
.L4:
	leal	(%rcx,%rax), %r8d
	movl	%r8d, (%rdi,%rax,4)
	incq	%rax
	cmpq	$6, %rax
	jne	.L4
	addq	$24, %rdi
	addl	$6, %ecx
	cmpq	%rsi, %rdi
	jne	.L3
	addl	$36, %edx
	movl	%edx, _ZZ10fill_imagePA6_iE1n(%rip)
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z10fill_imagePA6_i, .-_Z10fill_imagePA6_i
	.globl	_Z11fill_kernelPA3_i
	.type	_Z11fill_kernelPA3_i, @function
_Z11fill_kernelPA3_i:
.LFB3636:
	.cfi_startproc
	endbr64
	movl	_ZZ11fill_kernelPA3_iE1n(%rip), %eax
	leal	9(%rax), %edx
.L9:
	leal	1(%rax), %ecx
	movl	%eax, (%rdi)
	addq	$12, %rdi
	movl	%ecx, -8(%rdi)
	leal	2(%rax), %ecx
	addl	$3, %eax
	movl	%ecx, -4(%rdi)
	cmpl	%edx, %eax
	jne	.L9
	movl	%eax, _ZZ11fill_kernelPA3_iE1n(%rip)
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z11fill_kernelPA3_i, .-_Z11fill_kernelPA3_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n \t\t |"
.LC1:
	.string	"\t\t"
.LC2:
	.string	"|"
	.text
	.globl	_Z11fill_outputPA6_i
	.type	_Z11fill_outputPA6_i, @function
_Z11fill_outputPA6_i:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC0(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	144(%rdi), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 64
.L13:
	leaq	_ZSt4cout(%rip), %r12
	movq	%r14, %rsi
	xorl	%ebp, %ebp
	movq	%r12, %rdi
	leaq	.LC1(%rip), %r15
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L12:
	movq	%r15, %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	(%rbx,%rbp,4), %esi
	incq	%rbp
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	cmpq	$6, %rbp
	jne	.L12
	leaq	.LC2(%rip), %rsi
	movq	%r12, %rdi
	addq	$24, %rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	%r13, %rbx
	jne	.L13
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z11fill_outputPA6_i, .-_Z11fill_outputPA6_i
	.section	.rodata.str1.1
.LC4:
	.string	"\n total time to execute operation is "
.LC5:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	input(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%r12, %rdi
	leaq	kernel(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	48(%rsp), %rbx
	call	_Z10fill_imagePA6_i
	movq	%rbp, %rdi
	call	_Z11fill_kernelPA3_i
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	%rbx, %rsi
	leaq	24(%rsp), %rdi
	movl	$6, %ecx
	movl	$24, %edx
	call	cudaMallocPitch@PLT
	movq	%rbx, %rsi
	leaq	40(%rsp), %rdi
	movl	$3, %ecx
	movl	$12, %edx
	call	cudaMallocPitch@PLT
	movq	%rbx, %rsi
	leaq	32(%rsp), %rdi
	movl	$6, %ecx
	movl	$24, %edx
	leaq	24+kernel(%rip), %rbx
	call	cudaMallocPitch@PLT
	movq	24(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	movl	$144, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$144, %edx
	leaq	-20(%r12), %rbp
	leaq	4+output(%rip), %r12
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$6, %edi
	movl	$1, %r8d
	xorl	%r9d, %r9d
.L18:
	leaq	0(,%rdi,4), %rdx
	movl	$1, %esi
.L24:
	leaq	0(%rbp,%rdx), %r10
	leaq	-12+kernel(%rip), %rcx
.L22:
	xorl	%eax, %eax
.L19:
	movl	-4(%r10,%rax), %r11d
	imull	12(%rcx,%rax), %r11d
	addq	$4, %rax
	addl	%r11d, %r9d
	cmpq	$12, %rax
	jne	.L19
	addq	$12, %rcx
	addq	$24, %r10
	cmpq	%rbx, %rcx
	jne	.L22
	incq	%rsi
	movl	%r9d, (%r12,%rdx)
	addq	$4, %rdx
	cmpq	$5, %rsi
	jne	.L24
	incl	%r8d
	addq	$6, %rdi
	cmpl	$5, %r8d
	jne	.L18
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$0x00000000, 4(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	4(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	output(%rip), %rdi
	call	_Z11fill_outputPA6_i
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.text
	.globl	_Z38__device_stub__Z14add_arrays_gpuPiS_S_PiS_S_
	.type	_Z38__device_stub__Z14add_arrays_gpuPiS_S_PiS_S_, @function
_Z38__device_stub__Z14add_arrays_gpuPiS_S_PiS_S_:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14add_arrays_gpuPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L28:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z38__device_stub__Z14add_arrays_gpuPiS_S_PiS_S_, .-_Z38__device_stub__Z14add_arrays_gpuPiS_S_PiS_S_
	.globl	_Z14add_arrays_gpuPiS_S_
	.type	_Z14add_arrays_gpuPiS_S_, @function
_Z14add_arrays_gpuPiS_S_:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14add_arrays_gpuPiS_S_PiS_S_
	.cfi_endproc
.LFE3664:
	.size	_Z14add_arrays_gpuPiS_S_, .-_Z14add_arrays_gpuPiS_S_
	.globl	_Z41__device_stub__Z10processingPA6_iPA3_iS0_PA6_iPA3_iS0_
	.type	_Z41__device_stub__Z10processingPA6_iPA3_iS0_PA6_iPA3_iS0_, @function
_Z41__device_stub__Z10processingPA6_iPA3_iS0_PA6_iPA3_iS0_:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10processingPA6_iPA3_iS0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L33:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z41__device_stub__Z10processingPA6_iPA3_iS0_PA6_iPA3_iS0_, .-_Z41__device_stub__Z10processingPA6_iPA3_iS0_PA6_iPA3_iS0_
	.globl	_Z10processingPA6_iPA3_iS0_
	.type	_Z10processingPA6_iPA3_iS0_, @function
_Z10processingPA6_iPA3_iS0_:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z10processingPA6_iPA3_iS0_PA6_iPA3_iS0_
	.cfi_endproc
.LFE3666:
	.size	_Z10processingPA6_iPA3_iS0_, .-_Z10processingPA6_iPA3_iS0_
	.section	.rodata.str1.1
.LC6:
	.string	"_Z10processingPA6_iPA3_iS0_"
.LC7:
	.string	"_Z14add_arrays_gpuPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3668:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10processingPA6_iPA3_iS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14add_arrays_gpuPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3668:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ11fill_kernelPA3_iE1n
	.comm	_ZZ11fill_kernelPA3_iE1n,4,4
	.local	_ZZ10fill_imagePA6_iE1n
	.comm	_ZZ10fill_imagePA6_iE1n,4,4
	.globl	output
	.bss
	.align 32
	.type	output, @object
	.size	output, 144
output:
	.zero	144
	.globl	kernel
	.align 32
	.type	kernel, @object
	.size	kernel, 36
kernel:
	.zero	36
	.globl	input
	.align 32
	.type	input, @object
	.size	input, 144
input:
	.zero	144
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include <stdio.h>
#include <iostream>
using namespace std;

#define  i_size 6//image size
#define o_size 6
#define k_size 3//kernel size
int input[i_size][i_size];
int kernel[k_size][k_size];
int output[i_size][i_size];
typedef int itype[i_size];
typedef int ktype[k_size];
void fill_image(int m[i_size][i_size]) {
	static int n = 0; int i, j;
	for (i = 0; i < i_size; i++)
		for (j = 0; j < i_size; j++)
			m[i][j] = n++;
}

void fill_kernel(int m[k_size][k_size]) {
	static int n = 0; int i, j;
	for (i = 0; i < k_size; i++)
		for (j = 0; j < k_size; j++)
			m[i][j] = n++;
}
void fill_output(int m[i_size][i_size]) {
	int i, j;

	for (i = 0; i < o_size; i++) {
		cout << "\n \t\t |";
		for (j = 0; j < o_size; j++)
			cout << "\t\t" << m[i][j];
		cout << "|";
	}

}
__global__ void add_arrays_gpu(int* a, int *b, int* c)
{
	c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
__global__ void processing(itype  *a,ktype *kernel, itype *o)
{
	
	int r = 0;
	int i = (blockIdx.y*blockDim.y + threadIdx.y)+1;
	int j = (blockIdx.x*blockDim.x + threadIdx.x)+1;
	
	
	for (int k = -1; k < 2; k++)
	{
		for (int m = -1; m < 2; m++)
		{

			r += a[i + k][j + m] * kernel[k + 1][m + 1];
			o[i][j] = r;
		}

	}
}




int main()
{fill_image(input);
fill_kernel(kernel);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);


	itype *device_a, *device_c;
	ktype *device_b;
	const int size = i_size*i_size * sizeof(int);
	
	size_t pitch;
	hipMallocPitch((void**)&device_a, &pitch, i_size * sizeof(float), i_size);
	hipMallocPitch((void**)&device_b, &pitch, k_size * sizeof(float), k_size);
	hipMallocPitch((void**)&device_c, &pitch, i_size * sizeof(float), i_size);
	dim3 blockspergrid(2,2,1);
	dim3 threadperblock(2,2,1);
	hipMemcpy(
		device_a, input,
		size,
		hipMemcpyHostToDevice
	);

	hipMemcpy(
		device_b, kernel,
		size,
		hipMemcpyHostToDevice
	);
	int r = 0;
	//add_arra<< <1, count >> > (device_a, device_b, device_c);
	hipEventRecord(start);
	//processing <<<blockspergrid, threadperblock >> > (device_a,device_b,device_c);
	for (int i = 1; i < i_size - 1; i++)
	{
		for (int j = 1; j < i_size - 1; j++)
			for (int k = -1; k < 2; k++)
			{
				for (int m = -1; m < 2; m++)
				{

					r += input[i + k][j + m] * kernel[k + 1][m + 1];
					output[i][j] = r;
				}

			}
	}




	hipEventRecord(stop);
	
	/*cudaMemcpy(
		output, device_c,
		size,
		cudaMemcpyDeviceToHost
	);*/
	hipEventSynchronize(stop);
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);
	cout << "\n total time to execute operation is " << milliseconds << "\n";
	fill_output(output);
	

	//getchar();

	return 0;
}
	.text
	.file	"image_processing.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z10fill_imagePA6_i             # -- Begin function _Z10fill_imagePA6_i
	.type	_Z10fill_imagePA6_i,@function
_Z10fill_imagePA6_i:                    # @_Z10fill_imagePA6_i
	.cfi_startproc
# %bb.0:
	movl	_ZZ10fill_imagePA6_iE1n(%rip), %esi
	xorl	%eax, %eax
.LBB0_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_2 Depth 2
	movl	%esi, %ecx
	xorl	%edx, %edx
.LBB0_2:                                #   Parent Loop BB0_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rcx,%rdx), %esi
	movl	%esi, (%rdi,%rdx,4)
	incq	%rdx
	cmpq	$6, %rdx
	jne	.LBB0_2
# %bb.3:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%rax
	addq	$24, %rdi
	leal	(%rcx,%rdx), %esi
	cmpq	$6, %rax
	jne	.LBB0_1
# %bb.4:
	addl	%edx, %ecx
	movl	%ecx, _ZZ10fill_imagePA6_iE1n(%rip)
	retq
.Lfunc_end0:
	.size	_Z10fill_imagePA6_i, .Lfunc_end0-_Z10fill_imagePA6_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11fill_kernelPA3_i            # -- Begin function _Z11fill_kernelPA3_i
	.type	_Z11fill_kernelPA3_i,@function
_Z11fill_kernelPA3_i:                   # @_Z11fill_kernelPA3_i
	.cfi_startproc
# %bb.0:
	movl	_ZZ11fill_kernelPA3_iE1n(%rip), %esi
	xorl	%eax, %eax
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	movl	%esi, %ecx
	xorl	%edx, %edx
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rcx,%rdx), %esi
	movl	%esi, (%rdi,%rdx,4)
	incq	%rdx
	cmpq	$3, %rdx
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rax
	addq	$12, %rdi
	leal	(%rcx,%rdx), %esi
	cmpq	$3, %rax
	jne	.LBB1_1
# %bb.4:
	addl	%edx, %ecx
	movl	%ecx, _ZZ11fill_kernelPA3_iE1n(%rip)
	retq
.Lfunc_end1:
	.size	_Z11fill_kernelPA3_i, .Lfunc_end1-_Z11fill_kernelPA3_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11fill_outputPA6_i            # -- Begin function _Z11fill_outputPA6_i
	.type	_Z11fill_outputPA6_i,@function
_Z11fill_outputPA6_i:                   # @_Z11fill_outputPA6_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	xorl	%r14d, %r14d
.LBB2_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$6, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%r15d, %r15d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%rbx,%r15,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	incq	%r15
	cmpq	$6, %r15
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r14
	addq	$24, %rbx
	cmpq	$6, %r14
	jne	.LBB2_1
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z11fill_outputPA6_i, .Lfunc_end2-_Z11fill_outputPA6_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__add_arrays_gpuPiS_S_ # -- Begin function _Z29__device_stub__add_arrays_gpuPiS_S_
	.type	_Z29__device_stub__add_arrays_gpuPiS_S_,@function
_Z29__device_stub__add_arrays_gpuPiS_S_: # @_Z29__device_stub__add_arrays_gpuPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14add_arrays_gpuPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z29__device_stub__add_arrays_gpuPiS_S_, .Lfunc_end3-_Z29__device_stub__add_arrays_gpuPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__processingPA6_iPA3_iS0_ # -- Begin function _Z25__device_stub__processingPA6_iPA3_iS0_
	.type	_Z25__device_stub__processingPA6_iPA3_iS0_,@function
_Z25__device_stub__processingPA6_iPA3_iS0_: # @_Z25__device_stub__processingPA6_iPA3_iS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10processingPA6_iPA3_iS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__processingPA6_iPA3_iS0_, .Lfunc_end4-_Z25__device_stub__processingPA6_iPA3_iS0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$input, %eax
	movl	_ZZ10fill_imagePA6_iE1n(%rip), %edi
	xorl	%ecx, %ecx
.LBB5_1:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_2 Depth 2
	movl	%edi, %edx
	xorl	%esi, %esi
.LBB5_2:                                #   Parent Loop BB5_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rdx,%rsi), %edi
	movl	%edi, (%rax,%rsi,4)
	incq	%rsi
	cmpq	$6, %rsi
	jne	.LBB5_2
# %bb.3:                                #   in Loop: Header=BB5_1 Depth=1
	incq	%rcx
	addq	$24, %rax
	leal	(%rdx,%rsi), %edi
	cmpq	$6, %rcx
	jne	.LBB5_1
# %bb.4:                                # %_Z10fill_imagePA6_i.exit
	addl	%esi, %edx
	movl	%edx, _ZZ10fill_imagePA6_iE1n(%rip)
	movl	$kernel, %eax
	movl	_ZZ11fill_kernelPA3_iE1n(%rip), %edi
	xorl	%ecx, %ecx
.LBB5_5:                                # %.preheader.i23
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_6 Depth 2
	movl	%edi, %edx
	xorl	%esi, %esi
.LBB5_6:                                #   Parent Loop BB5_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rdx,%rsi), %edi
	movl	%edi, (%rax,%rsi,4)
	incq	%rsi
	cmpq	$3, %rsi
	jne	.LBB5_6
# %bb.7:                                #   in Loop: Header=BB5_5 Depth=1
	incq	%rcx
	addq	$12, %rax
	leal	(%rdx,%rsi), %edi
	cmpq	$3, %rcx
	jne	.LBB5_5
# %bb.8:                                # %_Z11fill_kernelPA3_i.exit
	addl	%esi, %edx
	movl	%edx, _ZZ11fill_kernelPA3_iE1n(%rip)
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	leaq	48(%rsp), %r14
	leaq	24(%rsp), %r12
	movl	$24, %edx
	movl	$6, %ecx
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMallocPitch
	leaq	32(%rsp), %r15
	movl	$12, %edx
	movl	$3, %ecx
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMallocPitch
	leaq	40(%rsp), %rdi
	movl	$24, %edx
	movl	$6, %ecx
	movq	%r12, %rsi
	callq	hipMallocPitch
	movq	(%r14), %rdi
	movl	$input, %r14d
	movl	$input, %esi
	movl	$144, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$kernel, %esi
	movl	$144, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$1, %eax
.LBB5_9:                                # %.preheader35
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_10 Depth 2
                                        #       Child Loop BB5_11 Depth 3
                                        #         Child Loop BB5_12 Depth 4
	movq	%r14, %rcx
	movl	$1, %edx
.LBB5_10:                               # %.preheader34
                                        #   Parent Loop BB5_9 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB5_11 Depth 3
                                        #         Child Loop BB5_12 Depth 4
	movq	$-1, %rsi
	movl	$kernel, %edi
	movq	%rcx, %r8
.LBB5_11:                               # %.preheader
                                        #   Parent Loop BB5_9 Depth=1
                                        #     Parent Loop BB5_10 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB5_12 Depth 4
	incq	%rsi
	xorl	%r9d, %r9d
.LBB5_12:                               #   Parent Loop BB5_9 Depth=1
                                        #     Parent Loop BB5_10 Depth=2
                                        #       Parent Loop BB5_11 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movl	(%rdi,%r9,4), %r10d
	imull	(%r8,%r9,4), %r10d
	addl	%r10d, %ebx
	incq	%r9
	cmpq	$3, %r9
	jne	.LBB5_12
# %bb.13:                               #   in Loop: Header=BB5_11 Depth=3
	addq	$24, %r8
	addq	$12, %rdi
	cmpq	$2, %rsi
	jne	.LBB5_11
# %bb.14:                               #   in Loop: Header=BB5_10 Depth=2
	leaq	(%rax,%rax,2), %rsi
	leaq	(,%rdx,4), %rdi
	movl	%ebx, output(%rdi,%rsi,8)
	incq	%rdx
	addq	$4, %rcx
	cmpq	$5, %rdx
	jne	.LBB5_10
# %bb.15:                               #   in Loop: Header=BB5_9 Depth=1
	incq	%rax
	addq	$24, %r14
	cmpq	$5, %rax
	jne	.LBB5_9
# %bb.16:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	20(%rsp), %rbx
	movl	$0, (%rbx)
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$37, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.4, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$output, %edi
	callq	_Z11fill_outputPA6_i
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14add_arrays_gpuPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10processingPA6_iPA3_iS0_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	input,@object                   # @input
	.bss
	.globl	input
	.p2align	4, 0x0
input:
	.zero	144
	.size	input, 144

	.type	kernel,@object                  # @kernel
	.globl	kernel
	.p2align	4, 0x0
kernel:
	.zero	36
	.size	kernel, 36

	.type	output,@object                  # @output
	.globl	output
	.p2align	4, 0x0
output:
	.zero	144
	.size	output, 144

	.type	_ZZ10fill_imagePA6_iE1n,@object # @_ZZ10fill_imagePA6_iE1n
	.local	_ZZ10fill_imagePA6_iE1n
	.comm	_ZZ10fill_imagePA6_iE1n,4,4
	.type	_ZZ11fill_kernelPA3_iE1n,@object # @_ZZ11fill_kernelPA3_iE1n
	.local	_ZZ11fill_kernelPA3_iE1n
	.comm	_ZZ11fill_kernelPA3_iE1n,4,4
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n \t\t |"
	.size	.L.str, 7

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\t\t"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"|"
	.size	.L.str.2, 2

	.type	_Z14add_arrays_gpuPiS_S_,@object # @_Z14add_arrays_gpuPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z14add_arrays_gpuPiS_S_
	.p2align	3, 0x0
_Z14add_arrays_gpuPiS_S_:
	.quad	_Z29__device_stub__add_arrays_gpuPiS_S_
	.size	_Z14add_arrays_gpuPiS_S_, 8

	.type	_Z10processingPA6_iPA3_iS0_,@object # @_Z10processingPA6_iPA3_iS0_
	.globl	_Z10processingPA6_iPA3_iS0_
	.p2align	3, 0x0
_Z10processingPA6_iPA3_iS0_:
	.quad	_Z25__device_stub__processingPA6_iPA3_iS0_
	.size	_Z10processingPA6_iPA3_iS0_, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"\n total time to execute operation is "
	.size	.L.str.3, 38

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\n"
	.size	.L.str.4, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14add_arrays_gpuPiS_S_"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10processingPA6_iPA3_iS0_"
	.size	.L__unnamed_2, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__add_arrays_gpuPiS_S_
	.addrsig_sym _Z25__device_stub__processingPA6_iPA3_iS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym input
	.addrsig_sym kernel
	.addrsig_sym output
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z14add_arrays_gpuPiS_S_
	.addrsig_sym _Z10processingPA6_iPA3_iS0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14add_arrays_gpuPiS_S_ ; -- Begin function _Z14add_arrays_gpuPiS_S_
	.globl	_Z14add_arrays_gpuPiS_S_
	.p2align	8
	.type	_Z14add_arrays_gpuPiS_S_,@function
_Z14add_arrays_gpuPiS_S_:               ; @_Z14add_arrays_gpuPiS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v1, v0, s[4:5]
	global_load_b32 v2, v0, s[6:7]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14add_arrays_gpuPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14add_arrays_gpuPiS_S_, .Lfunc_end0-_Z14add_arrays_gpuPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 72
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10processingPA6_iPA3_iS0_ ; -- Begin function _Z10processingPA6_iPA3_iS0_
	.globl	_Z10processingPA6_iPA3_iS0_
	.p2align	8
	.type	_Z10processingPA6_iPA3_iS0_,@function
_Z10processingPA6_iPA3_iS0_:            ; @_Z10processingPA6_iPA3_iS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s6, -1
	v_mov_b32_e32 v7, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s2
	v_add3_u32 v6, v0, s15, 1
	v_mov_b32_e32 v0, 0
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_i64_i32 v[4:5], null, v6, 24, s[4:5]
	v_add_nc_u32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
.LBB1_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
	v_add_nc_u32_e32 v8, s6, v6
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[4:5], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[4:5], null, v8, 24, s[0:1]
.LBB1_2:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v8, s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v9, vcc_lo
	global_load_b32 v10, v7, s[4:5]
	global_load_b32 v11, v[8:9], off
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s7, 3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v10, v11, v[0:1]
	v_mov_b32_e32 v0, v8
	global_store_b32 v[2:3], v8, off
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s6, s6, 1
	s_add_u32 s2, s2, 12
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s6, 2
	s_cbranch_scc0 .LBB1_1
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10processingPA6_iPA3_iS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10processingPA6_iPA3_iS0_, .Lfunc_end1-_Z10processingPA6_iPA3_iS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14add_arrays_gpuPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z14add_arrays_gpuPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10processingPA6_iPA3_iS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10processingPA6_iPA3_iS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
