#include "includes.h"
__device__ __forceinline__ int mirror(int index, int len){
int s2 = 2 * len - 2;
if(index < 0){
index = s2 * (-index / s2) + index;
return index <= 1 - len ? index + s2 : -index;
}
if(index >= len){
index -= s2 * (index / s2);
if(index >= len)
index = s2 - index;
return index;
}
if(index < 0 || index >= len) index = mirror(index, len);
return index;
}
__global__ void gussain_filter_x(float* random, float* kernel, int lw, size_t dim_z, size_t dim_y, size_t dim_x, int mode, float cval){
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t total = dim_x * dim_y * dim_z;
size_t total_xy = dim_x * dim_y;
size_t id_x = index % dim_x;
size_t id_y = (index / dim_x) % dim_y;
size_t id_z = (index / total_xy) % dim_z;
size_t id_block = index / total;
int id;
float new_pixel = 0;
int dim = 2;
if(dim_z > 1){
dim = 3;
}
if(index < total * dim){
if(mode == 0){
for(int i = -lw; i < lw + 1; i++){
id = id_x + i;
if(id < 0 || id > dim_x - 1)
new_pixel += cval * kernel[i+lw];
else new_pixel += kernel[i+lw] *
random[id_block * total + id_z * total_xy + id_y * dim_x + id];
}
__syncthreads();
random[index] = new_pixel;
__syncthreads();
}
else{
for(int i = -lw; i < lw + 1; i++){
id = id_x + i;
id = mirror(id, dim_x);
new_pixel += kernel[i+lw] *
random[id_block * total + id_z * total_xy + id_y * dim_x + id];
}
__syncthreads();
random[index] = new_pixel;
__syncthreads();
}
}
}
	.file	"tmpxft_00235e53_00000000-6_gussain_filter_x.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z44__device_stub__Z16gussain_filter_xPfS_immmifPfS_immmif
	.type	_Z44__device_stub__Z16gussain_filter_xPfS_immmifPfS_immmif, @function
_Z44__device_stub__Z16gussain_filter_xPfS_immmifPfS_immmif:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movss	%xmm0, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z16gussain_filter_xPfS_immmif(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z44__device_stub__Z16gussain_filter_xPfS_immmifPfS_immmif, .-_Z44__device_stub__Z16gussain_filter_xPfS_immmifPfS_immmif
	.globl	_Z16gussain_filter_xPfS_immmif
	.type	_Z16gussain_filter_xPfS_immmif, @function
_Z16gussain_filter_xPfS_immmif:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z16gussain_filter_xPfS_immmifPfS_immmif
	.cfi_endproc
.LFE2034:
	.size	_Z16gussain_filter_xPfS_immmif, .-_Z16gussain_filter_xPfS_immmif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16gussain_filter_xPfS_immmif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16gussain_filter_xPfS_immmif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ int mirror(int index, int len){
int s2 = 2 * len - 2;
if(index < 0){
index = s2 * (-index / s2) + index;
return index <= 1 - len ? index + s2 : -index;
}
if(index >= len){
index -= s2 * (index / s2);
if(index >= len)
index = s2 - index;
return index;
}
if(index < 0 || index >= len) index = mirror(index, len);
return index;
}
__global__ void gussain_filter_x(float* random, float* kernel, int lw, size_t dim_z, size_t dim_y, size_t dim_x, int mode, float cval){
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t total = dim_x * dim_y * dim_z;
size_t total_xy = dim_x * dim_y;
size_t id_x = index % dim_x;
size_t id_y = (index / dim_x) % dim_y;
size_t id_z = (index / total_xy) % dim_z;
size_t id_block = index / total;
int id;
float new_pixel = 0;
int dim = 2;
if(dim_z > 1){
dim = 3;
}
if(index < total * dim){
if(mode == 0){
for(int i = -lw; i < lw + 1; i++){
id = id_x + i;
if(id < 0 || id > dim_x - 1)
new_pixel += cval * kernel[i+lw];
else new_pixel += kernel[i+lw] *
random[id_block * total + id_z * total_xy + id_y * dim_x + id];
}
__syncthreads();
random[index] = new_pixel;
__syncthreads();
}
else{
for(int i = -lw; i < lw + 1; i++){
id = id_x + i;
id = mirror(id, dim_x);
new_pixel += kernel[i+lw] *
random[id_block * total + id_z * total_xy + id_y * dim_x + id];
}
__syncthreads();
random[index] = new_pixel;
__syncthreads();
}
}
}
	.text
	.file	"gussain_filter_x.hip"
	.globl	_Z31__device_stub__gussain_filter_xPfS_immmif # -- Begin function _Z31__device_stub__gussain_filter_xPfS_immmif
	.type	_Z31__device_stub__gussain_filter_xPfS_immmif,@function
_Z31__device_stub__gussain_filter_xPfS_immmif: # @_Z31__device_stub__gussain_filter_xPfS_immmif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	movq	%rsp, %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16gussain_filter_xPfS_immmif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__gussain_filter_xPfS_immmif, .Lfunc_end0-_Z31__device_stub__gussain_filter_xPfS_immmif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16gussain_filter_xPfS_immmif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16gussain_filter_xPfS_immmif,@object # @_Z16gussain_filter_xPfS_immmif
	.section	.rodata,"a",@progbits
	.globl	_Z16gussain_filter_xPfS_immmif
	.p2align	3, 0x0
_Z16gussain_filter_xPfS_immmif:
	.quad	_Z31__device_stub__gussain_filter_xPfS_immmif
	.size	_Z16gussain_filter_xPfS_immmif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16gussain_filter_xPfS_immmif"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__gussain_filter_xPfS_immmif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16gussain_filter_xPfS_immmif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16gussain_filter_xPfS_immmif ; -- Begin function _Z16gussain_filter_xPfS_immmif
	.globl	_Z16gussain_filter_xPfS_immmif
	.p2align	8
	.type	_Z16gussain_filter_xPfS_immmif,@function
_Z16gussain_filter_xPfS_immmif:         ; @_Z16gussain_filter_xPfS_immmif
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b64 s[12:13], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	v_cmp_lt_u64_e64 s10, s[4:5], 2
	s_mul_i32 s3, s12, s7
	s_mul_hi_u32 s8, s12, s6
	s_mul_i32 s9, s13, s6
	s_mul_i32 s16, s12, s6
	s_add_i32 s17, s8, s3
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s16, s5
	s_mul_hi_u32 s3, s16, s4
	s_add_i32 s17, s17, s9
	s_add_i32 s19, s3, s2
	s_mul_i32 s2, s17, s4
	s_mul_i32 s18, s16, s4
	s_add_i32 s19, s19, s2
	s_and_b32 s2, s10, exec_lo
	s_cselect_b32 s2, 2, 3
	v_mov_b32_e32 v2, 0
	s_mul_i32 s3, s19, s2
	s_mul_hi_u32 s8, s18, s2
	s_mul_i32 s2, s18, s2
	s_add_i32 s3, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_22
; %bb.1:
	v_cvt_f32_u32_e32 v0, s12
	v_cvt_f32_u32_e32 v3, s13
	v_cvt_f32_u32_e32 v4, s6
	v_cvt_f32_u32_e32 v5, s7
	v_cvt_f32_u32_e32 v6, s16
	v_cvt_f32_u32_e32 v7, s17
	v_fmac_f32_e32 v0, 0x4f800000, v3
	s_sub_u32 s2, 0, s12
	v_fmac_f32_e32 v4, 0x4f800000, v5
	s_subb_u32 s3, 0, s13
	v_fmac_f32_e32 v6, 0x4f800000, v7
	v_rcp_f32_e32 v0, v0
	s_sub_u32 s10, 0, s6
	s_subb_u32 s11, 0, s7
	s_sub_u32 s8, 0, s16
	v_rcp_f32_e32 v6, v6
	s_subb_u32 s9, 0, s17
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	v_mul_f32_e32 v6, 0x5f7ffffc, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x2f800000, v0
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, 0xcf800000, v3
	v_cvt_u32_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s2, v3
	v_mul_hi_u32 v7, s2, v0
	v_mul_lo_u32 v8, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v7, v5
	v_mul_lo_u32 v7, s2, v0
	v_add_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, v7
	v_mul_lo_u32 v11, v0, v5
	v_mul_hi_u32 v12, v0, v5
	v_mul_hi_u32 v13, v3, v7
	v_mul_lo_u32 v7, v3, v7
	v_mul_hi_u32 v14, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v10, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v7, v5
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v13, s3, v0
	v_mul_f32_e32 v9, 0x2f800000, v6
	v_mul_lo_u32 v5, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v9, v9
	v_fmac_f32_e32 v6, 0xcf800000, v9
	v_cvt_u32_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v12, v6
	v_mul_lo_u32 v6, s8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, s8, v12
	v_mul_lo_u32 v16, s9, v12
	v_mul_lo_u32 v18, s8, v12
	v_add_nc_u32_e32 v17, v17, v6
	v_rcp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x5f7ffffc, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, 0x2f800000, v4
	v_trunc_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v4, 0xcf800000, v8
	v_cvt_u32_f32_e32 v10, v8
	v_cvt_u32_f32_e32 v11, v4
	v_mul_hi_u32 v4, s2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v7, s10, v10
	v_mul_hi_u32 v14, s10, v11
	v_mul_lo_u32 v8, s11, v11
	v_mul_lo_u32 v15, s10, v11
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_lo_u32 v5, s2, v0
	v_add_nc_u32_e32 v7, v14, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v4, v4, v13
	v_mul_hi_u32 v13, v11, v15
	v_mul_hi_u32 v14, v10, v15
	v_mul_lo_u32 v15, v10, v15
	v_mul_hi_u32 v19, v0, v5
	v_mul_lo_u32 v20, v0, v4
	v_mul_hi_u32 v21, v0, v4
	v_mul_hi_u32 v6, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v22, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v19, vcc_lo, v19, v20
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v19, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v20, v6, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v22, vcc_lo
	v_mul_hi_u32 v19, v12, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	v_add_nc_u32_e32 v6, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v20, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v22, v11, v6
	v_mul_hi_u32 v23, v1, v0
	v_mul_hi_u32 v21, v11, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[3:4], null, v1, v20, 0
	v_mul_hi_u32 v24, v10, v6
	v_mul_lo_u32 v25, v10, v6
	v_mad_u64_u32 v[5:6], null, 0, v0, 0
	v_mad_u64_u32 v[7:8], null, 0, v20, 0
	v_add_co_u32 v0, vcc_lo, v23, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, v13, v22
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v0, vcc_lo, v3, v6, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s2, v0, v7
	v_add_co_ci_u32_e64 v6, s2, 0, v3, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v14, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, s13, v0
	v_mad_u64_u32 v[3:4], null, s12, v0, 0
	v_mul_lo_u32 v13, s12, v6
	v_add_co_u32 v5, vcc_lo, v5, v25
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v5, vcc_lo, v11, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v4, v13, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v10, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_nc_u32_e32 v22, 0, v4
	v_sub_co_u32 v3, vcc_lo, v1, v3
	v_add_co_u32 v11, s2, v0, 2
	v_mul_hi_u32 v15, s10, v5
	v_mul_lo_u32 v21, s10, v7
	v_add_co_ci_u32_e64 v14, s2, 0, v6, s2
	v_subrev_co_ci_u32_e64 v22, s2, s13, v22, vcc_lo
	v_sub_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v3
	v_sub_co_u32 v25, s2, v3, s12
	v_add_nc_u32_e32 v15, v15, v21
	v_mul_lo_u32 v20, s11, v5
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v21, vcc_lo, 0, v22, s2
	v_cmp_le_u32_e32 vcc_lo, s12, v25
	v_mul_lo_u32 v8, s10, v5
	v_add_nc_u32_e32 v15, v15, v20
	v_cndmask_b32_e64 v22, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_hi_u32 v23, v7, v8
	v_mul_lo_u32 v24, v7, v8
	v_cndmask_b32_e64 v20, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v21
	v_mul_hi_u32 v8, v5, v8
	v_mul_lo_u32 v26, v5, v15
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s13, v4
	v_mul_hi_u32 v4, v5, v15
	v_cndmask_b32_e32 v3, v20, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s13, v21
	v_mul_hi_u32 v20, v7, v15
	v_mul_lo_u32 v15, v7, v15
	v_cndmask_b32_e32 v21, v25, v22, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, v26
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s2, 0, v21
	v_add_co_u32 v8, vcc_lo, v8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v23, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v20, vcc_lo
	v_cndmask_b32_e64 v10, v10, v11, s2
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cvt_f32_u32_e32 v21, s19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v0, v10, vcc_lo
	v_add_co_u32 v0, s3, v4, v15
	v_add_co_ci_u32_e64 v3, s3, 0, v8, s3
	v_cndmask_b32_e64 v4, v13, v14, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s2, v5, v0
	v_add_co_ci_u32_e64 v11, s2, v7, v3, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v6, v4, vcc_lo
	v_mul_hi_u32 v14, v10, v8
	v_add_nc_u32_e32 v13, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[3:4], null, v10, v11, 0
	v_mad_u64_u32 v[5:6], null, v0, v8, 0
	v_mad_u64_u32 v[7:8], null, v0, v11, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v16, v12, v13
	v_mul_hi_u32 v15, v12, v13
	v_add_co_u32 v3, vcc_lo, v14, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_mul_hi_u32 v11, v9, v13
	v_add_co_u32 v3, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, v4, v6, vcc_lo
	v_mul_lo_u32 v3, v9, v18
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_mul_hi_u32 v4, v9, v18
	v_add_co_u32 v5, vcc_lo, v19, v16
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v15, vcc_lo
	v_mul_lo_u32 v13, v9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v6, v4, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v11, vcc_lo
	v_cvt_f32_u32_e32 v5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_cvt_f32_u32_e32 v6, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, 0x4f800000, v6
	v_mul_hi_u32 v11, s8, v3
	v_mul_lo_u32 v6, s9, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v9, s8, v4
	v_rcp_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v11, v9
	v_mul_lo_u32 v11, s8, v3
	s_sub_u32 s8, 0, s4
	s_subb_u32 s9, 0, s5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, 0x5f7ffffc, v5 :: v_dual_add_nc_u32 v6, v9, v6
	s_sub_u32 s20, 0, s18
	s_subb_u32 s21, 0, s19
	v_mul_hi_u32 v9, v3, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v12, v3, v6
	v_mul_hi_u32 v13, v3, v6
	v_mul_hi_u32 v16, v4, v11
	v_mul_lo_u32 v11, v4, v11
	v_mul_f32_e32 v15, 0x2f800000, v5
	v_add_co_u32 v9, vcc_lo, v9, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v9, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v12, v16, vcc_lo
	v_trunc_f32_e32 v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, 0xcf800000, v12
	v_mul_hi_u32 v17, v4, v6
	v_mul_lo_u32 v6, v4, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v9, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, v6
	v_cvt_u32_f32_e32 v11, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, v4, v9, vcc_lo
	v_cvt_u32_f32_e32 v9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v5, v1, v3
	v_mul_hi_u32 v12, s8, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[3:4], null, v1, v6, 0
	v_mul_lo_u32 v6, s8, v9
	v_mul_lo_u32 v13, s9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v12, v6
	v_mul_lo_u32 v5, s8, v11
	v_mad_u64_u32 v[3:4], null, s16, v15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v6, v13
	v_mul_hi_u32 v12, v11, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v18, v11, v6
	v_mul_hi_u32 v13, v9, v5
	v_mul_lo_u32 v16, v9, v5
	v_mul_hi_u32 v17, v11, v6
	v_mul_hi_u32 v19, v9, v6
	v_mul_lo_u32 v20, v9, v6
	v_mad_u64_u32 v[5:6], null, s17, v15, v[4:5]
	v_add_co_u32 v6, vcc_lo, v14, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, v12, v18
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v14, s6, v4
	v_sub_nc_u32_e32 v4, 0, v5
	v_sub_co_u32 v3, s2, v1, v3
	v_add_co_u32 v7, vcc_lo, v7, v16
	v_subrev_co_ci_u32_e64 v4, s3, s17, v4, s2
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_co_u32 v8, s3, v3, s16
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v19, vcc_lo
	v_subrev_co_ci_u32_e64 v4, s3, 0, v4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, s16, v8
	v_add_co_u32 v17, s3, v15, 2
	v_add_co_ci_u32_e64 v18, null, 0, 0, s3
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s17, v4
	v_mul_lo_u32 v12, s7, v6
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s17, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v16, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, v20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v13, vcc_lo
	v_sub_co_ci_u32_e64 v5, vcc_lo, 0, v5, s2
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, v9, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s17, v5
	v_cvt_f32_u32_e32 v20, s18
	v_add_co_u32 v9, s2, v15, 1
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v16, s8, v8
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s16, v3
	v_fmac_f32_e32 v20, 0x4f800000, v21
	v_mul_hi_u32 v19, s8, v7
	v_add_co_ci_u32_e64 v11, null, 0, 0, s2
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_mul_lo_u32 v22, s9, v7
	v_cmp_eq_u32_e64 s2, s17, v5
	v_cndmask_b32_e32 v9, v9, v17, vcc_lo
	v_rcp_f32_e32 v17, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v13, v3, s2
	v_mul_lo_u32 v13, s8, v7
	v_cndmask_b32_e32 v11, v11, v18, vcc_lo
	v_cmp_ne_u32_e64 s2, 0, v5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v17, 0x5f7ffffc, v17 :: v_dual_add_nc_u32 v4, v19, v16
	v_mul_lo_u32 v19, v8, v13
	v_cndmask_b32_e64 v9, v15, v9, s2
	v_cndmask_b32_e64 v11, 0, v11, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v16, v4, v22
	v_mad_u64_u32 v[3:4], null, s6, v6, 0
	v_mul_hi_u32 v6, v7, v13
	v_mul_hi_u32 v13, v8, v13
	v_mul_lo_u32 v5, v7, v16
	v_mul_hi_u32 v18, v7, v16
	v_mul_hi_u32 v15, v8, v16
	v_add3_u32 v12, v4, v14, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_mul_f32_e32 v6, 0x2f800000, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, v19
	v_mul_lo_u32 v5, v8, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v6, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, v18, v13, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v17, 0xcf800000, v6
	v_cvt_u32_f32_e32 v16, v6
	v_add_co_u32 v5, vcc_lo, v13, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v15, vcc_lo
	v_cvt_u32_f32_e32 v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v7, v5
	v_add_co_ci_u32_e32 v13, vcc_lo, v8, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v18, s20, v15
	v_mul_lo_u32 v19, s20, v16
	v_mul_hi_u32 v20, v9, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[5:6], null, v9, v13, 0
	v_mul_lo_u32 v14, s21, v15
	v_mad_u64_u32 v[7:8], null, v11, v17, 0
	v_add_nc_u32_e32 v17, v18, v19
	v_mul_lo_u32 v19, s20, v15
	v_add_co_u32 v18, vcc_lo, v20, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_mad_u64_u32 v[4:5], null, v11, v13, 0
	v_add_nc_u32_e32 v13, v17, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, v18, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v6, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v6, v15, v13
	v_mul_hi_u32 v8, v15, v19
	v_mul_hi_u32 v14, v15, v13
	v_mul_lo_u32 v18, v16, v19
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	v_mul_hi_u32 v19, v16, v19
	v_mul_hi_u32 v5, v16, v13
	v_mul_lo_u32 v13, v16, v13
	v_add_co_u32 v6, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v18
	v_add_co_ci_u32_e32 v6, vcc_lo, v8, v19, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_sub_nc_u32_e32 v8, v0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v13
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_sub_co_u32 v13, s2, v10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v3, vcc_lo, s7, v8, s2
	v_add_co_u32 v8, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v14, vcc_lo, v16, v5, vcc_lo
	v_sub_co_u32 v15, vcc_lo, v13, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v16, s3, 0, v3, vcc_lo
	v_mul_lo_u32 v18, s20, v14
	v_mul_hi_u32 v19, s20, v8
	s_clause 0x2
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x10
	s_load_b64 s[14:15], s[0:1], 0x30
	v_cmp_le_u32_e64 s0, s7, v16
	v_mul_lo_u32 v22, s21, v8
	v_mad_u64_u32 v[5:6], null, v10, s12, 0
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, 0, -1, s0
	v_cmp_le_u32_e64 s0, s6, v15
	v_add_nc_u32_e32 v6, v19, v18
	v_mul_lo_u32 v18, s20, v8
	v_sub_co_u32 v19, vcc_lo, v15, s6
	v_cndmask_b32_e64 v21, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s7, v16
	v_add_nc_u32_e32 v6, v6, v22
	v_mul_lo_u32 v24, v14, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v20, v21, s0
	v_subrev_co_ci_u32_e32 v20, vcc_lo, 0, v3, vcc_lo
	v_mul_lo_u32 v3, v8, v6
	v_add_co_u32 v7, vcc_lo, v7, v4
	v_mul_hi_u32 v4, v8, v18
	v_mul_hi_u32 v21, v8, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	v_mul_hi_u32 v18, v14, v18
	v_mul_hi_u32 v23, v14, v6
	v_mul_lo_u32 v6, v14, v6
	v_mul_lo_u32 v22, s5, v7
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v21, vcc_lo
	v_mul_lo_u32 v17, s4, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, v24
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v18, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v23, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s3, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v3, v6
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	v_mad_u64_u32 v[3:4], null, s4, v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v14, vcc_lo, v14, v18, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_sub_co_ci_u32_e64 v10, s0, v0, v12, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[6:7], null, v1, v14, 0
	v_mul_hi_u32 v0, v1, v8
	v_cmp_le_u32_e64 s0, s7, v10
	v_add3_u32 v12, v4, v17, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 0, -1, s0
	v_cmp_le_u32_e64 s0, s6, v13
	v_sub_nc_u32_e32 v4, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, -1, s0
	v_add_co_u32 v0, s0, v0, v6
	v_add_co_ci_u32_e64 v17, s0, 0, v7, s0
	v_sub_co_u32 v9, s0, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v18, s1, s5, v4, s0
	v_mad_u64_u32 v[3:4], null, s18, v17, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v21, s1, v9, s4
	v_subrev_co_ci_u32_e64 v22, s2, 0, v18, s1
	v_cmp_eq_u32_e64 s2, s7, v10
	v_sub_co_ci_u32_e64 v11, s0, v11, v12, s0
	v_mov_b32_e32 v0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v8, v14, s2
	v_cndmask_b32_e32 v14, v15, v19, vcc_lo
	v_cndmask_b32_e32 v6, v16, v20, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v22
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s14, 0
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v21
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_mad_u64_u32 v[7:8], null, s19, v17, v[0:1]
	v_sub_co_u32 v0, null, v1, v5
	v_cndmask_b32_e32 v5, v13, v14, vcc_lo
	v_cndmask_b32_e32 v6, v10, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s5, v22
	v_sub_nc_u32_e32 v10, 0, v7
	v_cndmask_b32_e32 v4, v15, v4, vcc_lo
	v_subrev_co_ci_u32_e64 v8, vcc_lo, s5, v18, s1
	v_sub_co_u32 v13, vcc_lo, v21, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_sub_co_u32 v3, vcc_lo, v1, v3
	v_subrev_co_ci_u32_e64 v10, s1, s19, v10, vcc_lo
	v_sub_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v12, s0, v3, s18
	v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
	v_cmp_le_u32_e64 s0, s5, v11
	v_cmp_eq_u32_e64 s1, s5, v11
	v_cmp_le_u32_e32 vcc_lo, s19, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, -1, s0
	v_cmp_le_u32_e64 s0, s4, v9
	v_cndmask_b32_e64 v15, 0, -1, s0
	v_cmp_le_u32_e64 s0, s19, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, 0, -1, s0
	v_cmp_le_u32_e64 s0, s18, v12
	v_cndmask_b32_e64 v12, 0, -1, s0
	v_cmp_ne_u32_e64 s0, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v22, v8, s0
	v_cndmask_b32_e64 v8, v14, v15, s1
	v_cmp_eq_u32_e64 s1, s19, v10
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	v_cndmask_b32_e64 v10, v16, v12, s1
	v_add_co_u32 v12, s1, v17, 2
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s19, v7
	v_add_co_ci_u32_e64 v14, null, 0, 0, s1
	v_add_co_u32 v16, s1, v17, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v18, null, 0, 0, s1
	v_cndmask_b32_e32 v3, v15, v3, vcc_lo
	v_cmp_ne_u32_e64 s1, 0, v10
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_cndmask_b32_e64 v7, v21, v13, s0
	v_cmp_ne_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v18, v14, s1
	v_cndmask_b32_e64 v3, v16, v12, s1
	v_cndmask_b32_e64 v12, 0, 1, s2
	v_dual_cndmask_b32 v8, v11, v4 :: v_dual_cndmask_b32 v7, v9, v7
	v_cndmask_b32_e64 v10, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v17, v3, s0
	v_cmp_ne_u32_e32 vcc_lo, 1, v12
	s_mov_b32 s0, -1
	s_cbranch_scc0 .LBB0_12
; %bb.2:
	v_mov_b32_e32 v11, 0
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	s_cbranch_vccnz .LBB0_11
; %bb.3:                                ; %.lr.ph
	s_lshl_b32 s4, s12, 1
	v_mul_lo_u32 v15, v10, s18
	s_add_i32 s4, s4, -2
	v_mul_lo_u32 v16, v9, s19
	s_ashr_i32 s0, s4, 31
	v_mul_lo_u32 v18, v8, s16
	s_add_i32 s1, s4, s0
	v_mul_lo_u32 v19, v7, s17
	s_xor_b32 s5, s1, s0
	v_mad_u64_u32 v[11:12], null, v7, s16, 0
	v_cvt_f32_u32_e32 v3, s5
	v_mul_lo_u32 v20, v6, s12
	v_mul_lo_u32 v21, v5, s13
	v_mad_u64_u32 v[13:14], null, v5, s12, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v17, v3
	v_mad_u64_u32 v[3:4], null, v9, s18, 0
	v_add3_u32 v12, v12, v19, v18
	s_sub_i32 s0, 0, s5
	s_lshl_b32 s1, s3, 1
	v_add3_u32 v14, v14, v21, v20
	s_sub_i32 s6, 0, s3
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v4, v4, v16, v15
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v17, 0x4f7ffffe, v17
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_sub_i32 s7, 1, s12
	s_or_b32 s14, s1, 1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_cvt_u32_f32_e32 v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_mul_lo_u32 v16, s0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, v11
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v12, vcc_lo
	v_mul_hi_u32 v16, v15, v16
	v_add_co_u32 v12, vcc_lo, v3, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, v4, v14, vcc_lo
	s_mov_b32 s0, 0
	v_add_nc_u32_e32 v14, v15, v16
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s6, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v3
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s20, exec_lo
	v_cmpx_le_i32_e64 s12, v3
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, v3, v14
	v_mul_lo_u32 v15, v15, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v15
	v_subrev_nc_u32_e32 v15, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v15, vcc_lo
	v_subrev_nc_u32_e32 v15, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v15, vcc_lo
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_sub_nc_u32_e32 v4, s4, v3
	v_cmp_gt_i32_e32 vcc_lo, s12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v4, v3, vcc_lo
.LBB0_7:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_8:                                ; %Flow116
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v4
	v_mul_hi_u32 v15, v3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, v15, s5
	v_sub_nc_u32_e32 v3, v3, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v15, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_cndmask_b32_e32 v3, v3, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v15, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_cndmask_b32_e32 v3, v3, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v4
	v_sub_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s4, v3
	v_sub_nc_u32_e32 v15, 0, v3
	v_cmp_lt_i32_e32 vcc_lo, s7, v3
	v_cndmask_b32_e32 v3, v4, v15, vcc_lo
.LBB0_10:                               ; %_Z6mirrorii.exit
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[20:21], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s20, s10, s20
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_addc_u32 s21, s11, s21
	s_add_i32 s0, s0, 1
	s_load_b32 s1, s[20:21], 0x0
	s_add_i32 s6, s6, 1
	s_cmp_eq_u32 s14, s0
	v_add_co_u32 v3, vcc_lo, v12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v13, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v11, s1, v3
	s_cbranch_scc0 .LBB0_4
.LBB0_11:                               ; %._crit_edge
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_mov_b32 s0, 0
	s_barrier
	buffer_gl0_inv
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_store_b32 v[3:4], v11, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
.LBB0_12:                               ; %Flow125
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_21
; %bb.13:
	v_mov_b32_e32 v11, 0
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_20
; %bb.14:                               ; %.lr.ph86
	v_mul_lo_u32 v10, v10, s18
	v_mul_lo_u32 v11, v9, s19
	v_mad_u64_u32 v[3:4], null, v9, s18, 0
	v_mul_lo_u32 v12, v8, s16
	v_mul_lo_u32 v13, v7, s17
	v_mad_u64_u32 v[8:9], null, v7, s16, 0
	s_sub_i32 s4, 0, s3
	s_add_u32 s0, s12, -1
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v4, v4, v11, v10
	v_mul_lo_u32 v10, v6, s12
	v_mul_lo_u32 v11, v5, s13
	v_mad_u64_u32 v[6:7], null, v5, s12, 0
	v_add3_u32 v9, v9, v13, v12
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_addc_u32 s1, s13, -1
	s_lshl_b32 s3, s3, 1
	s_mov_b32 s2, 0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v7, v7, v11, v10
	v_add_co_u32 v5, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v4, vcc_lo
	v_lshlrev_b64 v[3:4], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v9, vcc_lo
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v4, 0
	s_or_b32 s5, s3, 1
.LBB0_15:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s4, v0
	v_mov_b32_e32 v7, s15
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 -1, v3
	s_cbranch_execz .LBB0_19
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=1
	v_mov_b32_e32 v7, s15
	s_mov_b32 s6, exec_lo
	v_cmpx_ge_u64_e64 s[0:1], v[3:4]
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_15 Depth=1
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
.LBB0_18:                               ; %Flow120
                                        ;   in Loop: Header=BB0_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_19:                               ;   in Loop: Header=BB0_15 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[6:7], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s10, s6
	s_addc_u32 s7, s11, s7
	s_add_i32 s2, s2, 1
	global_load_b32 v3, v4, s[6:7]
	s_add_i32 s4, s4, 1
	s_cmp_eq_u32 s5, s2
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v11, v3, v7
	s_cbranch_scc0 .LBB0_15
.LBB0_20:                               ; %Flow123
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_barrier
	buffer_gl0_inv
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v11, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
.LBB0_21:                               ; %.sink.split
	buffer_gl0_inv
.LBB0_22:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16gussain_filter_xPfS_immmif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16gussain_filter_xPfS_immmif, .Lfunc_end0-_Z16gussain_filter_xPfS_immmif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4864
; NumSgprs: 24
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16gussain_filter_xPfS_immmif
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z16gussain_filter_xPfS_immmif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
