#include <math.h>
#include <stdlib.h>
//! Ising model evolution
/*!
  \param G      Spins on the square lattice             [n-by-n]
  \param w      Weight matrix                           [5-by-5]
  \param k      Number of iterations                    [scalar]
  \param n      Number of lattice points per dim        [scalar]

  NOTE: Both matrices G and w are stored in row-major format.
*/

__global__ void kernelCalcNewLattice(int* oldLattice, int* newLattice, double* w, int n,int dim){
    // Each thread will calculate the new magnetic moments of a block of the lattice.The top left cell of that block has coordinates (iStart,jStart).
	int iStart = blockIdx.x * dim;
	int jStart = threadIdx.x * dim;

    for(int i = iStart; i <= (iStart + (dim-1)) && ( i<n ); i++){
        for(int j = jStart; j <= (jStart + (dim-1)) && ( j<n ); j++){
            double influence = 0.0;
            for(int k=-2; k<=2; k++){
                for(int l=-2; l<=2; l++){
                    int newI = ( i+k+n )%n;             // (newI,newJ) are the coordinates of the moment that will influence the (i,j) new moment
                    int newJ = ( j+l+n )%n;
                    influence += w[ (k+2)*5 + (l+2) ] * oldLattice[ newI*n + newJ ];
                }
            }
            if( fabs(influence) < 1e-4 ){
                newLattice[i*n + j] = oldLattice[i*n + j];
            }else if( influence < 0.0 ){
                newLattice[i*n + j] = -1.0;
            }else{
                newLattice[i*n + j] =  1.0;
            }
        }
    }
}

void calcNewLattice(int* oldLattice, int* newLattice, double* w, int n, int iteration){
    if( iteration != 0 ){                   // If its not the first iteration
        for(int i=0; i<n*n; i++){
            oldLattice[i] = newLattice[i];  // oldLattice is now newLattice and we will calculate the newLattice
        }
    }

 	int* dev_oldLattice;
 	int* dev_newLattice;
 	double* dev_w;

 	cudaMallocManaged( &dev_oldLattice, n*n*sizeof(int) );
 	cudaMallocManaged( &dev_newLattice, n*n*sizeof(int) );
 	cudaMallocManaged( &dev_w, 25*sizeof(double) );

 	for(int i=0; i<n*n; i++){
 		dev_oldLattice[i] = oldLattice[i];
 		dev_newLattice[i] = newLattice[i];
 	}

 	for(int i=0; i<25; i++){
 		dev_w[i] = w[i];
 	}

    int dim = 50;                               // Every thread will calculate the moments of a dim x dim block of the lattice
    int numOfBlocks = ceil((double)n/dim);      // Number of blocks in each dimension 

    kernelCalcNewLattice<<<numOfBlocks,numOfBlocks>>>(dev_oldLattice, dev_newLattice, dev_w, n, dim);
    cudaDeviceSynchronize();

    for(int i=0; i<n*n; i++){
 		oldLattice[i] = dev_oldLattice[i];
 		newLattice[i] = dev_newLattice[i];
    }

    cudaFree( dev_oldLattice );
    cudaFree( dev_newLattice );
    cudaFree( dev_w );

}

void ising( int *G, double *w, int k, int n){
    int* oldLattice;
    int* newLattice;

  	oldLattice = (int*) malloc(n*n*sizeof(int));
    newLattice = (int*) malloc(n*n*sizeof(int));



    for(int i=0; i<n*n; i++){
        oldLattice[i] = G[i];
    }

    for(int i=0; i<k; i++){
        if( i!=0 ){             // If it is not the first iteration
            int same = 1;
            for(int j=0; j<n*n; j++){                   // Check if the lattice has changed in the last iteration
                if( oldLattice[j] != newLattice[j]){
                    same = 0;
                    break;
                }
            }

            if( same ){         // If it didnt change, break
                break;
            }
        }
        calcNewLattice(oldLattice, newLattice, w, n, i);
        cudaDeviceSynchronize();
    }

    for(int i=0; i<n*n; i++){
        G[i] = newLattice[i];
    }

    free( oldLattice );
    free( newLattice );

}


	.file	"tmpxft_00209b23_00000000-6_ising.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii
	.type	_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii, @function
_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z20kernelCalcNewLatticePiS_Pdii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii, .-_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii
	.globl	_Z20kernelCalcNewLatticePiS_Pdii
	.type	_Z20kernelCalcNewLatticePiS_Pdii, @function
_Z20kernelCalcNewLatticePiS_Pdii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii
	.cfi_endproc
.LFE2035:
	.size	_Z20kernelCalcNewLatticePiS_Pdii, .-_Z20kernelCalcNewLatticePiS_Pdii
	.globl	_Z14calcNewLatticePiS_Pdii
	.type	_Z14calcNewLatticePiS_Pdii, @function
_Z14calcNewLatticePiS_Pdii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	imull	%ecx, %r13d
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	testl	%r8d, %r8d
	jne	.L19
.L12:
	movslq	%r13d, %r14
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	salq	$2, %r14
	movq	%r14, %rsi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movq	%r14, %rsi
	call	cudaMallocManaged@PLT
	movl	$1, %edx
	leaq	24(%rsp), %rdi
	movl	$200, %esi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rcx
	xorl	%eax, %eax
	jmp	.L10
.L19:
	xorl	%eax, %eax
.L9:
	cmpl	%eax, %r13d
	jle	.L12
	movl	(%r12,%rax,4), %edx
	movl	%edx, 0(%rbp,%rax,4)
	incq	%rax
	jmp	.L9
.L10:
	cmpl	%eax, %r13d
	jle	.L22
	movl	0(%rbp,%rax,4), %esi
	movl	%esi, (%rdx,%rax,4)
	movl	(%r12,%rax,4), %esi
	movl	%esi, (%rcx,%rax,4)
	incq	%rax
	jmp	.L10
.L22:
	movq	24(%rsp), %rdx
	xorl	%eax, %eax
.L14:
	movsd	(%r15,%rax), %xmm0
	movsd	%xmm0, (%rdx,%rax)
	addq	$8, %rax
	cmpq	$200, %rax
	jne	.L14
	cvtsi2sdl	%ebx, %xmm0
	divsd	.LC0(%rip), %xmm0
	call	ceil@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	cvttsd2sil	%xmm0, %edx
	movq	%rax, 48(%rsp)
	movl	52(%rsp), %ecx
	movq	%rax, 36(%rsp)
	movl	40(%rsp), %esi
	movl	%edx, 32(%rsp)
	movq	32(%rsp), %rdi
	movl	%edx, 44(%rsp)
	movq	44(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$50, %r8d
	movl	%ebx, %ecx
	movq	8(%rsp), %rdi
	call	_Z46__device_stub__Z20kernelCalcNewLatticePiS_PdiiPiS_Pdii
.L15:
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rdx
	xorl	%eax, %eax
.L16:
	cmpl	%eax, %r13d
	jle	.L23
	movl	(%rdi,%rax,4), %ecx
	movl	%ecx, 0(%rbp,%rax,4)
	movl	(%rdx,%rax,4), %ecx
	movl	%ecx, (%r12,%rax,4)
	incq	%rax
	jmp	.L16
.L23:
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z14calcNewLatticePiS_Pdii, .-_Z14calcNewLatticePiS_Pdii
	.globl	_Z5isingPiPdii
	.type	_Z5isingPiPdii, @function
_Z5isingPiPdii:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	imull	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r13d, %rbx
	salq	$2, %rbx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%rbx, %rdi
	movq	%rsi, (%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L25:
	cmpl	%eax, %r13d
	jle	.L38
	movl	(%r15,%rax,4), %edx
	movl	%edx, 0(%rbp,%rax,4)
	incq	%rax
	jmp	.L25
.L38:
	xorl	%r8d, %r8d
.L27:
	xorl	%eax, %eax
	cmpl	%r14d, %r8d
	jge	.L31
	testl	%r8d, %r8d
	je	.L29
.L28:
	cmpl	%eax, %r13d
	jle	.L39
	movl	0(%rbp,%rax,4), %edx
	incq	%rax
	cmpl	-4(%rbx,%rax,4), %edx
	je	.L28
	jmp	.L29
.L39:
	xorl	%eax, %eax
	jmp	.L31
.L29:
	movq	(%rsp), %rdx
	movl	%r12d, %ecx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	movl	%r8d, 12(%rsp)
	call	_Z14calcNewLatticePiS_Pdii
	call	cudaDeviceSynchronize@PLT
	movl	12(%rsp), %r8d
	incl	%r8d
	jmp	.L27
.L31:
	cmpl	%eax, %r13d
	jle	.L40
	movl	(%rbx,%rax,4), %edx
	movl	%edx, (%r15,%rax,4)
	incq	%rax
	jmp	.L31
.L40:
	movq	%rbp, %rdi
	call	free@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z5isingPiPdii, .-_Z5isingPiPdii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z20kernelCalcNewLatticePiS_Pdii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20kernelCalcNewLatticePiS_Pdii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1078525952
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
//! Ising model evolution
/*!
  \param G      Spins on the square lattice             [n-by-n]
  \param w      Weight matrix                           [5-by-5]
  \param k      Number of iterations                    [scalar]
  \param n      Number of lattice points per dim        [scalar]

  NOTE: Both matrices G and w are stored in row-major format.
*/

__global__ void kernelCalcNewLattice(int* oldLattice, int* newLattice, double* w, int n,int dim){
    // Each thread will calculate the new magnetic moments of a block of the lattice.The top left cell of that block has coordinates (iStart,jStart).
	int iStart = blockIdx.x * dim;
	int jStart = threadIdx.x * dim;

    for(int i = iStart; i <= (iStart + (dim-1)) && ( i<n ); i++){
        for(int j = jStart; j <= (jStart + (dim-1)) && ( j<n ); j++){
            double influence = 0.0;
            for(int k=-2; k<=2; k++){
                for(int l=-2; l<=2; l++){
                    int newI = ( i+k+n )%n;             // (newI,newJ) are the coordinates of the moment that will influence the (i,j) new moment
                    int newJ = ( j+l+n )%n;
                    influence += w[ (k+2)*5 + (l+2) ] * oldLattice[ newI*n + newJ ];
                }
            }
            if( fabs(influence) < 1e-4 ){
                newLattice[i*n + j] = oldLattice[i*n + j];
            }else if( influence < 0.0 ){
                newLattice[i*n + j] = -1.0;
            }else{
                newLattice[i*n + j] =  1.0;
            }
        }
    }
}

void calcNewLattice(int* oldLattice, int* newLattice, double* w, int n, int iteration){
    if( iteration != 0 ){                   // If its not the first iteration
        for(int i=0; i<n*n; i++){
            oldLattice[i] = newLattice[i];  // oldLattice is now newLattice and we will calculate the newLattice
        }
    }

 	int* dev_oldLattice;
 	int* dev_newLattice;
 	double* dev_w;

 	hipMallocManaged( &dev_oldLattice, n*n*sizeof(int) );
 	hipMallocManaged( &dev_newLattice, n*n*sizeof(int) );
 	hipMallocManaged( &dev_w, 25*sizeof(double) );

 	for(int i=0; i<n*n; i++){
 		dev_oldLattice[i] = oldLattice[i];
 		dev_newLattice[i] = newLattice[i];
 	}

 	for(int i=0; i<25; i++){
 		dev_w[i] = w[i];
 	}

    int dim = 50;                               // Every thread will calculate the moments of a dim x dim block of the lattice
    int numOfBlocks = ceil((double)n/dim);      // Number of blocks in each dimension 

    kernelCalcNewLattice<<<numOfBlocks,numOfBlocks>>>(dev_oldLattice, dev_newLattice, dev_w, n, dim);
    hipDeviceSynchronize();

    for(int i=0; i<n*n; i++){
 		oldLattice[i] = dev_oldLattice[i];
 		newLattice[i] = dev_newLattice[i];
    }

    hipFree( dev_oldLattice );
    hipFree( dev_newLattice );
    hipFree( dev_w );

}

void ising( int *G, double *w, int k, int n){
    int* oldLattice;
    int* newLattice;

  	oldLattice = (int*) malloc(n*n*sizeof(int));
    newLattice = (int*) malloc(n*n*sizeof(int));



    for(int i=0; i<n*n; i++){
        oldLattice[i] = G[i];
    }

    for(int i=0; i<k; i++){
        if( i!=0 ){             // If it is not the first iteration
            int same = 1;
            for(int j=0; j<n*n; j++){                   // Check if the lattice has changed in the last iteration
                if( oldLattice[j] != newLattice[j]){
                    same = 0;
                    break;
                }
            }

            if( same ){         // If it didnt change, break
                break;
            }
        }
        calcNewLattice(oldLattice, newLattice, w, n, i);
        hipDeviceSynchronize();
    }

    for(int i=0; i<n*n; i++){
        G[i] = newLattice[i];
    }

    free( oldLattice );
    free( newLattice );

}


	.text
	.file	"ising.hip"
	.globl	_Z35__device_stub__kernelCalcNewLatticePiS_Pdii # -- Begin function _Z35__device_stub__kernelCalcNewLatticePiS_Pdii
	.type	_Z35__device_stub__kernelCalcNewLatticePiS_Pdii,@function
_Z35__device_stub__kernelCalcNewLatticePiS_Pdii: # @_Z35__device_stub__kernelCalcNewLatticePiS_Pdii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20kernelCalcNewLatticePiS_Pdii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__kernelCalcNewLatticePiS_Pdii, .Lfunc_end0-_Z35__device_stub__kernelCalcNewLatticePiS_Pdii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z14calcNewLatticePiS_Pdii
.LCPI1_0:
	.quad	0x4049000000000000              # double 50
	.text
	.globl	_Z14calcNewLatticePiS_Pdii
	.type	_Z14calcNewLatticePiS_Pdii,@function
_Z14calcNewLatticePiS_Pdii:             # @_Z14calcNewLatticePiS_Pdii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movq	%rdx, %r15
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	%ecx, %r13d
	imull	%r13d, %r13d
	testl	%r8d, %r8d
	je	.LBB1_5
# %bb.1:                                # %.preheader53
	testl	%ebp, %ebp
	je	.LBB1_2
# %bb.3:                                # %.lr.ph.preheader
	cmpl	$1, %r13d
	movl	%r13d, %eax
	adcl	$0, %eax
	xorl	%ecx, %ecx
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%rcx,4), %edx
	movl	%edx, (%r14,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_4
	jmp	.LBB1_5
.LBB1_2:
	xorl	%r13d, %r13d
.LBB1_5:                                # %.loopexit
	movl	%r13d, %r12d
	shlq	$2, %r12
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$200, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%ebp, %ebp
	je	.LBB1_8
# %bb.6:                                # %.lr.ph56
	movq	16(%rsp), %rax
	movq	(%rsp), %rcx
	cmpl	$1, %r13d
	movl	%r13d, %edx
	adcl	$0, %edx
	xorl	%esi, %esi
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rsi,4), %edi
	movl	%edi, (%rax,%rsi,4)
	movl	(%rbx,%rsi,4), %edi
	movl	%edi, (%rcx,%rsi,4)
	incq	%rsi
	cmpq	%rsi, %rdx
	jne	.LBB1_7
.LBB1_8:                                # %.preheader
	movq	8(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_9:                                # =>This Inner Loop Header: Depth=1
	movsd	(%r15,%rcx,8), %xmm0            # xmm0 = mem[0],zero
	movsd	%xmm0, (%rax,%rcx,8)
	incq	%rcx
	cmpq	$25, %rcx
	jne	.LBB1_9
# %bb.10:
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebp, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %edi
	btsq	$32, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.11:
	movq	16(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%ebp, %ecx
	movl	$50, %r8d
	callq	_Z35__device_stub__kernelCalcNewLatticePiS_Pdii
.LBB1_12:
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rdi
	testl	%ebp, %ebp
	je	.LBB1_15
# %bb.13:                               # %.lr.ph59
	movq	(%rsp), %rax
	cmpl	$1, %r13d
	adcl	$0, %r13d
	xorl	%ecx, %ecx
.LBB1_14:                               # =>This Inner Loop Header: Depth=1
	movl	(%rdi,%rcx,4), %edx
	movl	%edx, (%r14,%rcx,4)
	movl	(%rax,%rcx,4), %edx
	movl	%edx, (%rbx,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r13
	jne	.LBB1_14
.LBB1_15:                               # %._crit_edge
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z14calcNewLatticePiS_Pdii, .Lfunc_end1-_Z14calcNewLatticePiS_Pdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5isingPiPdii                  # -- Begin function _Z5isingPiPdii
	.type	_Z5isingPiPdii,@function
_Z5isingPiPdii:                         # @_Z5isingPiPdii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, 4(%rsp)                   # 4-byte Spill
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	movl	%ecx, %ebx
	imull	%ebx, %ebx
	leaq	(,%rbx,4), %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r12
	testl	%ebp, %ebp
	je	.LBB2_2
# %bb.1:                                # %.lr.ph.preheader
	cmpq	$1, %rbx
	movq	%rbx, %rdx
	adcq	$0, %rdx
	shlq	$2, %rdx
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	memcpy@PLT
.LBB2_2:                                # %.preheader48
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	cmpl	$0, 4(%rsp)                     # 4-byte Folded Reload
	jle	.LBB2_10
# %bb.3:                                # %.lr.ph54
	cmpl	$2, %ebx
	movl	$1, %r13d
	cmovael	%ebx, %r13d
	xorl	%r14d, %r14d
.LBB2_4:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_8 Depth 2
	testl	%r14d, %r14d
	je	.LBB2_9
# %bb.5:                                # %.preheader
                                        #   in Loop: Header=BB2_4 Depth=1
	testl	%ebp, %ebp
	je	.LBB2_12
# %bb.6:                                # %.lr.ph52.preheader
                                        #   in Loop: Header=BB2_4 Depth=1
	xorl	%eax, %eax
.LBB2_8:                                # %.lr.ph52
                                        #   Parent Loop BB2_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r15,%rax,4), %ecx
	cmpl	(%r12,%rax,4), %ecx
	jne	.LBB2_9
# %bb.7:                                #   in Loop: Header=BB2_8 Depth=2
	incq	%rax
	cmpq	%rax, %r13
	jne	.LBB2_8
	jmp	.LBB2_10
.LBB2_9:                                # %.loopexit
                                        #   in Loop: Header=BB2_4 Depth=1
	movq	%r15, %rdi
	movq	%r12, %rsi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	%ebp, %ecx
	movl	%r14d, %r8d
	callq	_Z14calcNewLatticePiS_Pdii
	callq	hipDeviceSynchronize
	incl	%r14d
	cmpl	4(%rsp), %r14d                  # 4-byte Folded Reload
	jne	.LBB2_4
.LBB2_10:                               # %.critedge
	testl	%ebp, %ebp
	je	.LBB2_12
# %bb.11:                               # %.lr.ph56.preheader
	cmpq	$1, %rbx
	adcq	$0, %rbx
	shlq	$2, %rbx
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	%r12, %rsi
	movq	%rbx, %rdx
	callq	memcpy@PLT
.LBB2_12:                               # %._crit_edge
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	free                            # TAILCALL
.Lfunc_end2:
	.size	_Z5isingPiPdii, .Lfunc_end2-_Z5isingPiPdii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20kernelCalcNewLatticePiS_Pdii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20kernelCalcNewLatticePiS_Pdii,@object # @_Z20kernelCalcNewLatticePiS_Pdii
	.section	.rodata,"a",@progbits
	.globl	_Z20kernelCalcNewLatticePiS_Pdii
	.p2align	3, 0x0
_Z20kernelCalcNewLatticePiS_Pdii:
	.quad	_Z35__device_stub__kernelCalcNewLatticePiS_Pdii
	.size	_Z20kernelCalcNewLatticePiS_Pdii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20kernelCalcNewLatticePiS_Pdii"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__kernelCalcNewLatticePiS_Pdii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20kernelCalcNewLatticePiS_Pdii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20kernelCalcNewLatticePiS_Pdii ; -- Begin function _Z20kernelCalcNewLatticePiS_Pdii
	.globl	_Z20kernelCalcNewLatticePiS_Pdii
	.p2align	8
	.type	_Z20kernelCalcNewLatticePiS_Pdii,@function
_Z20kernelCalcNewLatticePiS_Pdii:       ; @_Z20kernelCalcNewLatticePiS_Pdii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 1
	s_mul_i32 s16, s15, s3
	s_cselect_b32 s4, -1, 0
	s_cmp_ge_i32 s16, s2
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s4, s5
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_18
; %bb.1:                                ; %.preheader62.lr.ph
	s_ashr_i32 s4, s2, 31
	v_mul_lo_u32 v4, v0, s3
	s_add_i32 s5, s2, s4
	v_mov_b32_e32 v7, -1
	s_xor_b32 s17, s5, s4
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_cvt_f32_u32_e32 v1, s17
	s_add_i32 s1, s3, -1
	s_sub_i32 s3, 0, s17
	v_add_nc_u32_e32 v5, s1, v4
	v_cmp_gt_i32_e64 s0, s2, v4
	v_rcp_iflag_f32_e32 v1, v1
	s_mov_b32 s10, 0xeb1c432d
	s_mov_b32 s11, 0x3f1a36e2
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v6, 1 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s12
	s_mul_hi_u32 s13, s12, s3
	s_add_i32 s3, s16, s1
	s_add_i32 s18, s12, s13
.LBB0_2:                                ; %.preheader62
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;         Child Loop BB0_6 Depth 4
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_17
; %bb.3:                                ; %.preheader61.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v8, v4
	s_add_i32 s20, s16, s2
	s_mul_i32 s21, s16, s2
	s_mov_b32 s22, 0
.LBB0_4:                                ; %.preheader61
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;         Child Loop BB0_6 Depth 4
	v_mov_b32_e32 v0, 0
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, s2, v8
	s_mov_b32 s1, -2
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[12:13], s[8:9]
.LBB0_5:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_6 Depth 4
	s_add_i32 s14, s20, s1
	v_mov_b32_e32 v3, -5
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s14, s14, s15
	s_xor_b32 s14, s14, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s23, s14, s18
	s_mul_i32 s23, s23, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s14, s14, s23
	s_sub_i32 s23, s14, s17
	s_cmp_ge_u32 s14, s17
	s_cselect_b32 s14, s23, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s23, s14, s17
	s_cmp_ge_u32 s14, s17
	s_cselect_b32 s14, s23, s14
	s_xor_b32 s14, s14, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s23, s14, s15
	s_mov_b64 s[14:15], s[12:13]
	s_mul_i32 s23, s23, s2
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_5 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v2, v3, 3
	s_load_b64 s[24:25], s[14:15], 0x0
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v9, v10
	v_xor_b32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v9, s18
	v_mul_lo_u32 v11, v11, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v9, v11
	v_subrev_nc_u32_e32 v11, s17, v9
	v_cmp_le_u32_e32 vcc_lo, s17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v9, v11, vcc_lo
	v_subrev_nc_u32_e32 v11, s17, v9
	v_cmp_le_u32_e32 vcc_lo, s17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v9, v11, vcc_lo
	v_xor_b32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v9, v10
	v_add_nc_u32_e32 v9, s23, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_i32_e32 v[9:10], v9
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[24:25], v[9:10], v[0:1]
	v_add_co_u32 v3, s24, v3, 1
	s_and_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccz .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=3
	s_add_i32 s1, s1, 1
	s_add_u32 s12, s12, 40
	s_addc_u32 s13, s13, 0
	s_cmp_eq_u32 s1, 3
	s_cbranch_scc0 .LBB0_5
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v2, s21, v8
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_cmpx_nlt_f64_e64 |v[0:1]|, s[10:11]
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_14
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, s6, v0
	v_add_co_ci_u32_e64 v1, s1, s7, v1, s1
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=2
	global_store_b32 v[0:1], v6, off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_11:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=2
	global_store_b32 v[0:1], v7, off
.LBB0_13:                               ; %Flow88
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr2
.LBB0_14:                               ; %Flow89
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s1, s12
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_4 Depth=2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_16:                               ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v0, 1, v8
	v_cmp_ge_i32_e32 vcc_lo, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s1, s2, v0
	v_mov_b32_e32 v8, v0
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s22, s1, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_4
.LBB0_17:                               ; %Flow91
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_add_i32 s1, s16, 1
	s_cmp_ge_i32 s16, s3
	s_mov_b32 s16, s1
	s_cselect_b32 s12, -1, 0
	s_cmp_ge_i32 s1, s2
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s12, s12, s13
	s_and_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccz .LBB0_2
.LBB0_18:                               ; %._crit_edge69
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20kernelCalcNewLatticePiS_Pdii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20kernelCalcNewLatticePiS_Pdii, .Lfunc_end0-_Z20kernelCalcNewLatticePiS_Pdii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 828
; NumSgprs: 28
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20kernelCalcNewLatticePiS_Pdii
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z20kernelCalcNewLatticePiS_Pdii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
