/*
 * segmentation_tools.cu
 *
 *  Created on: Apr 15, 2017
 *      Author: sara
 */

#include "segmentation_tools.cuh"
#include "segmentator_cuda_kernels.cuh"

/******************************************************************************
 * compute_organ_mask_bounds: estimate left, right, front, back, top and bottom
 * lungs bounds based on extracted mask
 *
 * Arguments:
 *      meta_mask: meta mask containing organ segmentation
 *      value: value of the organ segmentation label
 *      left: left lungs bound
 *      right: right lungs bound
 *      front: front lungs bound
 *      back: back lungs bound
 *      top: top lungs bound
 *      bottom: bottom lungs bounds
 *
******************************************************************************/
void compute_organ_mask_bounds(const unsigned char *meta_mask,
                               const unsigned int *size,
                               const unsigned char value,
                               unsigned &left, unsigned &right,
                               unsigned &front, unsigned &back,
                               unsigned &bottom, unsigned &top)
{

    unsigned int n_p = size[0] * size[1] * size[2];
    unsigned int n_s = size[0] + size[1] + size[2];

    unsigned int n_p_B = n_p * sizeof(unsigned char);
    unsigned char *meta_mask_d;
    cudaMalloc((void **)&meta_mask_d, n_p_B);
    cudaMemcpy(meta_mask_d, meta_mask, n_p_B, cudaMemcpyHostToDevice);

    unsigned int n_s_B = n_s * sizeof(unsigned int);
    unsigned int *accs = new unsigned int[n_s];
    for(unsigned int i = 0; i < n_s; i++)
        accs[i] = 0;
    unsigned int *accs_d;
    cudaMalloc((void **)&accs_d, n_s_B);
    cudaMemcpy(accs_d, accs, n_s_B, cudaMemcpyHostToDevice);

    dim3 grid(size[1], size[2]);
    get_organ_mask_accs_gpu<<<grid, size[0]>>>(meta_mask_d, value, accs_d);

    cudaMemcpy(accs, accs_d, n_s_B, cudaMemcpyDeviceToHost);

    // 1. Determining left and right bounds
    for(unsigned int i = 0; i < size[0]; i++)
    {
        if(!left and accs[i])
            left = i;
        if(!right and accs[size[0] - i - 1])
            right = size[0] - i - 1;
        if(left and right)
            break;
    }

    // 2. Determining front and back bounds
    for(unsigned int i = 0; i < size[1]; i++)
    {
        if(!front and accs[size[0] + i])
            front = i;
        if(!back and accs[size[0] + size[1] - i - 1])
            back = size[1] - i - 1;
        if(front and back)
            break;
    }

    // 3. Determine bottom and top
    for(unsigned int i = 0; i < size[2]; i++)
    {
        if(!bottom and accs[size[0] + size[1] + i])
            bottom = i;
        if(!top and accs[size[0] + size[1] + size[2] - i - 1])
            top = size[2] - i - 1;
        if(bottom and top)
            break;
    }

    cudaFree(meta_mask_d);
    cudaFree(accs_d);
    delete [] accs;
}



	.file	"tmpxft_0039e2af_00000000-6_segmentation_tools.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text._Z22mean_std_normalizationPfS_S_jj,"axG",@progbits,_Z22mean_std_normalizationPfS_S_jj,comdat
	.weak	_Z22mean_std_normalizationPfS_S_jj
	.type	_Z22mean_std_normalizationPfS_S_jj, @function
_Z22mean_std_normalizationPfS_S_jj:
.LFB2052:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z22mean_std_normalizationPfS_S_jj(%rip), %rbx
	subq	$144, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, (%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movl	%r8d, 4(%rsp)
	movq	%rbx, _ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f(%rip)
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	movq	%rbx, %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$144, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z22mean_std_normalizationPfS_S_jj, .-_Z22mean_std_normalizationPfS_S_jj
	.section	.text._Z27volume_air_segmentation_gpuPKfjjjPbf,"axG",@progbits,_Z27volume_air_segmentation_gpuPKfjjjPbf,comdat
	.weak	_Z27volume_air_segmentation_gpuPKfjjjPbf
	.type	_Z27volume_air_segmentation_gpuPKfjjjPbf, @function
_Z27volume_air_segmentation_gpuPKfjjjPbf:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z27volume_air_segmentation_gpuPKfjjjPbf(%rip), %rbx
	subq	$160, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movl	%esi, 8(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 32(%rsp)
	movq	%rbx, _ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f(%rip)
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	movss	%xmm0, 20(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	movq	%rbx, %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L7:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$160, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z27volume_air_segmentation_gpuPKfjjjPbf, .-_Z27volume_air_segmentation_gpuPKfjjjPbf
	.section	.text._Z22detect_body_bounds_gpuPKbPjjjjjjj,"axG",@progbits,_Z22detect_body_bounds_gpuPKbPjjjjjjj,comdat
	.weak	_Z22detect_body_bounds_gpuPKbPjjjjjjj
	.type	_Z22detect_body_bounds_gpuPKbPjjjjjjj, @function
_Z22detect_body_bounds_gpuPKbPjjjjjjj:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z22detect_body_bounds_gpuPKbPjjjjjjj(%rip), %rbx
	subq	$176, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	movl	192(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	68(%rsp), %rsi
	movl	%eax, 16(%rsp)
	movl	200(%rsp), %eax
	movl	%edx, (%rsp)
	leaq	40(%rsp), %rdx
	movl	%eax, 20(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movl	%r8d, 8(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%rbx, _ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f(%rip)
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	movq	%rbx, %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L11:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$176, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z22detect_body_bounds_gpuPKbPjjjjjjj, .-_Z22detect_body_bounds_gpuPKbPjjjjjjj
	.section	.text._Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,"axG",@progbits,_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,comdat
	.weak	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
	.type	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j, @function
_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j(%rip), %rbx
	subq	$160, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	3(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movb	%cl, 3(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 32(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%rbx, _ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f(%rip)
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	movq	%rbx, %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L15:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$160, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j, .-_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
	.section	.text._Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,"axG",@progbits,_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,comdat
	.weak	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
	.type	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj, @function
_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj:
.LFB2044:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj(%rip), %rbx
	subq	$208, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	movl	224(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	92(%rsp), %rsi
	movl	%eax, 12(%rsp)
	movl	232(%rsp), %eax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movl	%eax, 16(%rsp)
	movl	240(%rsp), %eax
	movq	%rcx, 48(%rsp)
	leaq	72(%rsp), %rcx
	movl	%eax, 20(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 56(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%rbx, _ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f(%rip)
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	movq	%rbx, %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L19:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$208, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj, .-_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
	.section	.text._Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,"axG",@progbits,_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,comdat
	.weak	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
	.type	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj, @function
_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj:
.LFB2046:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj(%rip), %rbx
	subq	$208, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	movl	224(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	92(%rsp), %rsi
	movl	%eax, 12(%rsp)
	movl	232(%rsp), %eax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movl	%eax, 16(%rsp)
	movl	240(%rsp), %eax
	movq	%rcx, 48(%rsp)
	leaq	72(%rsp), %rcx
	movl	%eax, 20(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 56(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%rbx, _ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f(%rip)
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	movq	%rbx, %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L23:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$208, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj, .-_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
	.section	.text._Z16accumulation_gpuPfS_jj,"axG",@progbits,_Z16accumulation_gpuPfS_jj,comdat
	.weak	_Z16accumulation_gpuPfS_jj
	.type	_Z16accumulation_gpuPfS_jj, @function
_Z16accumulation_gpuPfS_jj:
.LFB2048:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z16accumulation_gpuPfS_jj(%rip), %rbx
	addq	$-128, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	%rsp, %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rbx, _ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f(%rip)
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	movq	%rbx, %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L27:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z16accumulation_gpuPfS_jj, .-_Z16accumulation_gpuPfS_jj
	.section	.text._Z24squared_accumulation_gpuPfS_S_jj,"axG",@progbits,_Z24squared_accumulation_gpuPfS_S_jj,comdat
	.weak	_Z24squared_accumulation_gpuPfS_S_jj
	.type	_Z24squared_accumulation_gpuPfS_S_jj, @function
_Z24squared_accumulation_gpuPfS_S_jj:
.LFB2050:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z24squared_accumulation_gpuPfS_S_jj(%rip), %rbx
	subq	$144, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, (%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movl	%r8d, 4(%rsp)
	movq	%rbx, _ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f(%rip)
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	movq	%rbx, %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L31:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$144, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z24squared_accumulation_gpuPfS_S_jj, .-_Z24squared_accumulation_gpuPfS_S_jj
	.section	.text._Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj,"axG",@progbits,_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj,comdat
	.weak	_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj
	.type	_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj, @function
_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_Z23get_organ_mask_accs_gpuPKhhPj(%rip), %rbx
	addq	$-128, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movb	%sil, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rbx, _ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f(%rip)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	movq	%rbx, %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L35:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj, .-_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj
	.section	.text._Z23get_organ_mask_accs_gpuPKhhPj,"axG",@progbits,_Z23get_organ_mask_accs_gpuPKhhPj,comdat
	.weak	_Z23get_organ_mask_accs_gpuPKhhPj
	.type	_Z23get_organ_mask_accs_gpuPKhhPj, @function
_Z23get_organ_mask_accs_gpuPKhhPj:
.LFB2040:
	.cfi_startproc
	endbr64
	movzbl	%sil, %esi
	jmp	_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj
	.cfi_endproc
.LFE2040:
	.size	_Z23get_organ_mask_accs_gpuPKhhPj, .-_Z23get_organ_mask_accs_gpuPKhhPj
	.text
	.globl	_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_
	.type	_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_, @function
_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movl	4(%rsi), %ecx
	movq	168(%rsp), %rax
	movq	%r9, 8(%rsp)
	leaq	48(%rsp), %rdi
	movl	%edx, 44(%rsp)
	movl	(%rsi), %edx
	movq	%rax, 16(%rsp)
	movq	176(%rsp), %rax
	leal	(%rdx,%rcx), %r14d
	movq	160(%rsp), %r15
	movq	%rax, 24(%rsp)
	imull	%ecx, %edx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movl	8(%rsi), %eax
	imull	%eax, %edx
	addl	%eax, %r14d
	movq	%rdx, %rsi
	movq	%rdx, 32(%rsp)
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%r14d, %eax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	_Znam@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L41:
	cmpl	%r14d, %eax
	jnb	.L65
	xorl	%edx, %edx
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	jmp	.L41
.L65:
	movl	32(%rsp), %r14d
	leaq	56(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdi
	movq	%r14, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	0(%rbp), %eax
	movq	4(%rbp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	%eax, 76(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movl	84(%rsp), %ecx
	movq	76(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movzbl	44(%rsp), %esi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	_Z47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPj
.L43:
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
.L44:
	cmpl	0(%rbp), %eax
	jnb	.L50
	cmpl	$0, (%r12)
	jne	.L45
	movl	%eax, %edx
	cmpl	$0, (%rbx,%rdx,4)
	je	.L45
	movl	%eax, (%r12)
.L45:
	cmpl	$0, 0(%r13)
	jne	.L46
	movl	%eax, %edx
	notl	%edx
	addl	0(%rbp), %edx
	movl	%edx, %ecx
	cmpl	$0, (%rbx,%rcx,4)
	je	.L46
	movl	%edx, 0(%r13)
.L46:
	cmpl	$0, (%r12)
	je	.L47
	cmpl	$0, 0(%r13)
	je	.L47
.L50:
	xorl	%eax, %eax
	jmp	.L48
.L47:
	incl	%eax
	jmp	.L44
.L55:
	movq	8(%rsp), %rsi
	cmpl	$0, (%rsi)
	je	.L66
.L51:
	cmpl	$0, (%r15)
	je	.L67
.L52:
	movq	8(%rsp), %rsi
	cmpl	$0, (%rsi)
	jne	.L68
.L53:
	incl	%eax
.L48:
	cmpl	4(%rbp), %eax
	jb	.L55
	jmp	.L56
.L66:
	movl	%eax, %edx
	addl	0(%rbp), %edx
	cmpl	$0, (%rbx,%rdx,4)
	je	.L51
	movl	%eax, (%rsi)
	jmp	.L51
.L67:
	movl	4(%rbp), %edx
	movl	0(%rbp), %ecx
	addl	%edx, %ecx
	decl	%ecx
	subl	%eax, %ecx
	cmpl	$0, (%rbx,%rcx,4)
	je	.L52
	decl	%edx
	subl	%eax, %edx
	movl	%edx, (%r15)
	jmp	.L52
.L68:
	cmpl	$0, (%r15)
	je	.L53
.L56:
	xorl	%eax, %eax
	jmp	.L54
.L60:
	movq	16(%rsp), %rsi
	cmpl	$0, (%rsi)
	je	.L69
.L57:
	movq	24(%rsp), %rdi
	cmpl	$0, (%rdi)
	je	.L70
.L58:
	movq	16(%rsp), %rdi
	cmpl	$0, (%rdi)
	jne	.L71
.L59:
	incl	%eax
.L54:
	cmpl	8(%rbp), %eax
	jb	.L60
	jmp	.L61
.L69:
	movl	4(%rbp), %edx
	addl	0(%rbp), %edx
	addl	%eax, %edx
	movl	%edx, %edx
	cmpl	$0, (%rbx,%rdx,4)
	je	.L57
	movl	%eax, (%rsi)
	jmp	.L57
.L70:
	movl	8(%rbp), %edx
	movl	4(%rbp), %ecx
	addl	0(%rbp), %ecx
	leal	-1(%rdx,%rcx), %ecx
	subl	%eax, %ecx
	cmpl	$0, (%rbx,%rcx,4)
	je	.L58
	decl	%edx
	subl	%eax, %edx
	movl	%edx, (%rdi)
	jmp	.L58
.L71:
	movq	24(%rsp), %rsi
	cmpl	$0, (%rsi)
	je	.L59
.L61:
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_, .-_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22mean_std_normalizationPfS_S_jj"
.LC1:
	.string	"_Z24squared_accumulation_gpuPfS_S_jj"
.LC2:
	.string	"_Z16accumulation_gpuPfS_jj"
.LC3:
	.string	"_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj"
.LC4:
	.string	"_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj"
.LC5:
	.string	"_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j"
.LC6:
	.string	"_Z23get_organ_mask_accs_gpuPKhhPj"
.LC7:
	.string	"_Z22detect_body_bounds_gpuPKbPjjjjjjj"
.LC8:
	.string	"_Z27volume_air_segmentation_gpuPKfjjjPbf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22mean_std_normalizationPfS_S_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z24squared_accumulation_gpuPfS_S_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z16accumulation_gpuPfS_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z23get_organ_mask_accs_gpuPKhhPj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z22detect_body_bounds_gpuPKbPjjjjjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z27volume_air_segmentation_gpuPKfjjjPbf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.weak	_ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f
	.section	.bss._ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f,"awG",@nobits,_ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f,comdat
	.align 8
	.type	_ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f, @gnu_unique_object
	.size	_ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f, 8
_ZZ48__device_stub__Z22mean_std_normalizationPfS_S_jjPfS_S_jjE3__f:
	.zero	8
	.weak	_ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f
	.section	.bss._ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f,"awG",@nobits,_ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f,comdat
	.align 8
	.type	_ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f, @gnu_unique_object
	.size	_ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f, 8
_ZZ50__device_stub__Z24squared_accumulation_gpuPfS_S_jjPfS_S_jjE3__f:
	.zero	8
	.weak	_ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f
	.section	.bss._ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f,"awG",@nobits,_ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f,comdat
	.align 8
	.type	_ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f, @gnu_unique_object
	.size	_ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f, 8
_ZZ40__device_stub__Z16accumulation_gpuPfS_jjPfS_jjE3__f:
	.zero	8
	.weak	_ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f
	.section	.bss._ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f,"awG",@nobits,_ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f,comdat
	.align 8
	.type	_ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f, @gnu_unique_object
	.size	_ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f, 8
_ZZ57__device_stub__Z24resize_gt_slice_and_cropPhS_PjS0_PfjjjjPhS_PjS0_PfjjjjE3__f:
	.zero	8
	.weak	_ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f
	.section	.bss._ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f,"awG",@nobits,_ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f,comdat
	.align 8
	.type	_ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f, @gnu_unique_object
	.size	_ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f, 8
_ZZ61__device_stub__Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjjPfS_PjS0_S_jjjjE3__f:
	.zero	8
	.weak	_ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f
	.section	.bss._ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f,"awG",@nobits,_ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f,comdat
	.align 8
	.type	_ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f, @gnu_unique_object
	.size	_ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f, 8
_ZZ63__device_stub__Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_jPKhPjS1_hS1_jE3__f:
	.zero	8
	.weak	_ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f
	.section	.bss._ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f,"awG",@nobits,_ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f,comdat
	.align 8
	.type	_ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f, @gnu_unique_object
	.size	_ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f, 8
_ZZ47__device_stub__Z23get_organ_mask_accs_gpuPKhhPjPKhhPjE3__f:
	.zero	8
	.weak	_ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f
	.section	.bss._ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f,"awG",@nobits,_ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f,comdat
	.align 8
	.type	_ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f, @gnu_unique_object
	.size	_ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f, 8
_ZZ51__device_stub__Z22detect_body_bounds_gpuPKbPjjjjjjjPKbPjjjjjjjE3__f:
	.zero	8
	.weak	_ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f
	.section	.bss._ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f,"awG",@nobits,_ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f,comdat
	.align 8
	.type	_ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f, @gnu_unique_object
	.size	_ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f, 8
_ZZ54__device_stub__Z27volume_air_segmentation_gpuPKfjjjPbfPKfjjjPbfE3__f:
	.zero	8
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * segmentation_tools.cu
 *
 *  Created on: Apr 15, 2017
 *      Author: sara
 */


#include <hip/hip_runtime.h>
#include "segmentation_tools.cuh"
#include "segmentator_cuda_kernels.cuh"

/******************************************************************************
 * compute_organ_mask_bounds: estimate left, right, front, back, top and bottom
 * lungs bounds based on extracted mask
 *
 * Arguments:
 *      meta_mask: meta mask containing organ segmentation
 *      value: value of the organ segmentation label
 *      left: left lungs bound
 *      right: right lungs bound
 *      front: front lungs bound
 *      back: back lungs bound
 *      top: top lungs bound
 *      bottom: bottom lungs bounds
 *
******************************************************************************/
void compute_organ_mask_bounds(const unsigned char *meta_mask,
                               const unsigned int *size,
                               const unsigned char value,
                               unsigned &left, unsigned &right,
                               unsigned &front, unsigned &back,
                               unsigned &bottom, unsigned &top)
{

    unsigned int n_p = size[0] * size[1] * size[2];
    unsigned int n_s = size[0] + size[1] + size[2];

    unsigned int n_p_B = n_p * sizeof(unsigned char);
    unsigned char *meta_mask_d;
    hipMalloc((void **)&meta_mask_d, n_p_B);
    hipMemcpy(meta_mask_d, meta_mask, n_p_B, hipMemcpyHostToDevice);

    unsigned int n_s_B = n_s * sizeof(unsigned int);
    unsigned int *accs = new unsigned int[n_s];
    for(unsigned int i = 0; i < n_s; i++)
        accs[i] = 0;
    unsigned int *accs_d;
    hipMalloc((void **)&accs_d, n_s_B);
    hipMemcpy(accs_d, accs, n_s_B, hipMemcpyHostToDevice);

    dim3 grid(size[1], size[2]);
    get_organ_mask_accs_gpu<<<grid, size[0]>>>(meta_mask_d, value, accs_d);

    hipMemcpy(accs, accs_d, n_s_B, hipMemcpyDeviceToHost);

    // 1. Determining left and right bounds
    for(unsigned int i = 0; i < size[0]; i++)
    {
        if(!left and accs[i])
            left = i;
        if(!right and accs[size[0] - i - 1])
            right = size[0] - i - 1;
        if(left and right)
            break;
    }

    // 2. Determining front and back bounds
    for(unsigned int i = 0; i < size[1]; i++)
    {
        if(!front and accs[size[0] + i])
            front = i;
        if(!back and accs[size[0] + size[1] - i - 1])
            back = size[1] - i - 1;
        if(front and back)
            break;
    }

    // 3. Determine bottom and top
    for(unsigned int i = 0; i < size[2]; i++)
    {
        if(!bottom and accs[size[0] + size[1] + i])
            bottom = i;
        if(!top and accs[size[0] + size[1] + size[2] - i - 1])
            top = size[2] - i - 1;
        if(bottom and top)
            break;
    }

    hipFree(meta_mask_d);
    hipFree(accs_d);
    delete [] accs;
}



	.text
	.file	"segmentation_tools.hip"
	.globl	_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_ # -- Begin function _Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_
	.type	_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_,@function
_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_: # @_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 72(%rsp)                   # 8-byte Spill
	movq	%r8, 64(%rsp)                   # 8-byte Spill
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movl	%edx, 28(%rsp)                  # 4-byte Spill
	movq	%rsi, %rbx
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	movl	(%rsi), %eax
	movl	4(%rsi), %r15d
	movl	%r15d, %ebp
	imull	%eax, %ebp
	movl	8(%rsi), %r13d
	imull	%r13d, %ebp
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	leal	(%r15,%rax), %r12d
	addl	%r13d, %r12d
	leaq	32(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	(,%r12,4), %ebp
	leaq	(,%r12,4), %rdi
	callq	_Znam
	movq	%rax, %r14
	testl	%r12d, %r12d
	je	.LBB0_2
# %bb.1:                                # %.lr.ph.preheader
	addl	%r13d, %r15d
	movq	40(%rsp), %rax                  # 8-byte Reload
	addl	%r15d, %eax
	decl	%eax
	leaq	4(,%rax,4), %rdx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB0_2:                                # %._crit_edge
	movl	%ebp, %ebp
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%r14, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	4(%rbx), %rdi
	movl	(%rbx), %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	32(%rsp), %rax
	movq	16(%rsp), %rcx
	leaq	104(%rsp), %rdx
	movq	%rax, (%rdx)
	leaq	15(%rsp), %rax
	movl	28(%rsp), %esi                  # 4-byte Reload
	movb	%sil, (%rax)
	leaq	96(%rsp), %rsi
	movq	%rcx, (%rsi)
	leaq	144(%rsp), %r12
	movq	%rdx, (%r12)
	movq	%rax, 8(%r12)
	movq	%rsi, 16(%r12)
	leaq	128(%rsp), %r15
	leaq	112(%rsp), %r13
	leaq	88(%rsp), %rdx
	leaq	80(%rsp), %rcx
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	__hipPopCallConfiguration
	movq	(%r15), %rsi
	movl	8(%r15), %edx
	movq	(%r13), %rcx
	movl	8(%r13), %r8d
	movl	$_Z23get_organ_mask_accs_gpuPKhhPj, %edi
	movq	%r12, %r9
	leaq	80(%rsp), %rax
	pushq	(%rax)
	.cfi_adjust_cfa_offset 8
	leaq	96(%rsp), %rax
	pushq	(%rax)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB0_4:
	movq	16(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, (%rbx)
	movq	72(%rsp), %r9                   # 8-byte Reload
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	56(%rsp), %r8                   # 8-byte Reload
	je	.LBB0_16
# %bb.5:                                # %.lr.ph114.preheader
	movl	(%r8), %edx
	movl	$-1, %eax
	xorl	%ecx, %ecx
.LBB0_7:                                # %.lr.ph114
                                        # =>This Inner Loop Header: Depth=1
	testl	%edx, %edx
	jne	.LBB0_11
# %bb.8:                                #   in Loop: Header=BB0_7 Depth=1
	cmpl	$0, (%r14,%rcx,4)
	je	.LBB0_9
# %bb.10:                               #   in Loop: Header=BB0_7 Depth=1
	movl	%ecx, (%r8)
	movl	%ecx, %edx
	jmp	.LBB0_11
.LBB0_9:                                #   in Loop: Header=BB0_7 Depth=1
	xorl	%edx, %edx
.LBB0_11:                               #   in Loop: Header=BB0_7 Depth=1
	movl	(%rdi), %esi
	testl	%esi, %esi
	jne	.LBB0_14
# %bb.12:                               #   in Loop: Header=BB0_7 Depth=1
	movl	(%rbx), %esi
	addl	%eax, %esi
	cmpl	$0, (%r14,%rsi,4)
	je	.LBB0_6
# %bb.13:                               #   in Loop: Header=BB0_7 Depth=1
	movl	%esi, (%rdi)
	movl	(%r8), %edx
.LBB0_14:                               #   in Loop: Header=BB0_7 Depth=1
	testl	%edx, %edx
	je	.LBB0_6
# %bb.15:                               #   in Loop: Header=BB0_7 Depth=1
	testl	%esi, %esi
	jne	.LBB0_16
.LBB0_6:                                # %.thread
                                        #   in Loop: Header=BB0_7 Depth=1
	incq	%rcx
	movl	(%rbx), %esi
	decl	%eax
	cmpq	%rsi, %rcx
	jb	.LBB0_7
.LBB0_16:                               # %._crit_edge115
	cmpl	$0, 4(%rbx)
	je	.LBB0_28
# %bb.17:                               # %.lr.ph119.preheader
	movq	224(%rsp), %rax
	movl	(%r9), %esi
	xorl	%ecx, %ecx
	movl	$-1, %edx
.LBB0_19:                               # %.lr.ph119
                                        # =>This Inner Loop Header: Depth=1
	testl	%esi, %esi
	jne	.LBB0_23
# %bb.20:                               #   in Loop: Header=BB0_19 Depth=1
	movl	(%rbx), %esi
	addl	%ecx, %esi
	cmpl	$0, (%r14,%rsi,4)
	je	.LBB0_21
# %bb.22:                               #   in Loop: Header=BB0_19 Depth=1
	movl	%ecx, (%r9)
	movl	%ecx, %esi
	jmp	.LBB0_23
.LBB0_21:                               #   in Loop: Header=BB0_19 Depth=1
	xorl	%esi, %esi
.LBB0_23:                               #   in Loop: Header=BB0_19 Depth=1
	movl	(%rax), %edi
	testl	%edi, %edi
	jne	.LBB0_26
# %bb.24:                               #   in Loop: Header=BB0_19 Depth=1
	movl	4(%rbx), %edi
	movl	(%rbx), %r8d
	addl	%edi, %r8d
	addl	%edx, %r8d
	cmpl	$0, (%r14,%r8,4)
	je	.LBB0_18
# %bb.25:                               #   in Loop: Header=BB0_19 Depth=1
	addl	%edx, %edi
	movl	%edi, (%rax)
	movl	(%r9), %esi
.LBB0_26:                               #   in Loop: Header=BB0_19 Depth=1
	testl	%esi, %esi
	je	.LBB0_18
# %bb.27:                               #   in Loop: Header=BB0_19 Depth=1
	testl	%edi, %edi
	jne	.LBB0_28
.LBB0_18:                               # %.thread141
                                        #   in Loop: Header=BB0_19 Depth=1
	incl	%ecx
	decl	%edx
	cmpl	4(%rbx), %ecx
	jb	.LBB0_19
.LBB0_28:                               # %._crit_edge120
	cmpl	$0, 8(%rbx)
	je	.LBB0_40
# %bb.29:                               # %.lr.ph124.preheader
	movq	240(%rsp), %rax
	movq	232(%rsp), %rcx
	movl	(%rcx), %edi
	xorl	%edx, %edx
	movl	$-1, %esi
.LBB0_31:                               # %.lr.ph124
                                        # =>This Inner Loop Header: Depth=1
	testl	%edi, %edi
	jne	.LBB0_35
# %bb.32:                               #   in Loop: Header=BB0_31 Depth=1
	movl	4(%rbx), %edi
	addl	(%rbx), %edi
	addl	%edx, %edi
	cmpl	$0, (%r14,%rdi,4)
	je	.LBB0_33
# %bb.34:                               #   in Loop: Header=BB0_31 Depth=1
	movl	%edx, (%rcx)
	movl	%edx, %edi
	jmp	.LBB0_35
.LBB0_33:                               #   in Loop: Header=BB0_31 Depth=1
	xorl	%edi, %edi
.LBB0_35:                               #   in Loop: Header=BB0_31 Depth=1
	movl	(%rax), %r8d
	testl	%r8d, %r8d
	jne	.LBB0_38
# %bb.36:                               #   in Loop: Header=BB0_31 Depth=1
	movl	8(%rbx), %r8d
	movl	4(%rbx), %r9d
	addl	%r8d, %r9d
	addl	(%rbx), %r9d
	addl	%esi, %r9d
	cmpl	$0, (%r14,%r9,4)
	je	.LBB0_30
# %bb.37:                               #   in Loop: Header=BB0_31 Depth=1
	addl	%esi, %r8d
	movl	%r8d, (%rax)
	movl	(%rcx), %edi
.LBB0_38:                               #   in Loop: Header=BB0_31 Depth=1
	testl	%edi, %edi
	je	.LBB0_30
# %bb.39:                               #   in Loop: Header=BB0_31 Depth=1
	testl	%r8d, %r8d
	jne	.LBB0_40
.LBB0_30:                               # %.thread145
                                        #   in Loop: Header=BB0_31 Depth=1
	incl	%edx
	decl	%esi
	cmpl	8(%rbx), %edx
	jb	.LBB0_31
.LBB0_40:                               # %._crit_edge125
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	_ZdaPv
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_, .Lfunc_end0-_Z25compute_organ_mask_boundsPKhPKjhRjS3_S3_S3_S3_S3_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z38__device_stub__get_organ_mask_accs_gpuPKhhPj,"axG",@progbits,_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj,comdat
	.weak	_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj # -- Begin function _Z38__device_stub__get_organ_mask_accs_gpuPKhhPj
	.type	_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj,@function
_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj: # @_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	15(%rsp), %rcx
	movb	%sil, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23get_organ_mask_accs_gpuPKhhPj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj, .Lfunc_end1-_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23get_organ_mask_accs_gpuPKhhPj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23get_organ_mask_accs_gpuPKhhPj,@object # @_Z23get_organ_mask_accs_gpuPKhhPj
	.section	.rodata._Z23get_organ_mask_accs_gpuPKhhPj,"aG",@progbits,_Z23get_organ_mask_accs_gpuPKhhPj,comdat
	.weak	_Z23get_organ_mask_accs_gpuPKhhPj
	.p2align	3, 0x0
_Z23get_organ_mask_accs_gpuPKhhPj:
	.quad	_Z38__device_stub__get_organ_mask_accs_gpuPKhhPj
	.size	_Z23get_organ_mask_accs_gpuPKhhPj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z23get_organ_mask_accs_gpuPKhhPj"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__get_organ_mask_accs_gpuPKhhPj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23get_organ_mask_accs_gpuPKhhPj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z27volume_air_segmentation_gpuPKfjjjPbf,"axG",@progbits,_Z27volume_air_segmentation_gpuPKfjjjPbf,comdat
	.protected	_Z27volume_air_segmentation_gpuPKfjjjPbf ; -- Begin function _Z27volume_air_segmentation_gpuPKfjjjPbf
	.globl	_Z27volume_air_segmentation_gpuPKfjjjPbf
	.p2align	8
	.type	_Z27volume_air_segmentation_gpuPKfjjjPbf,@function
_Z27volume_air_segmentation_gpuPKfjjjPbf: ; @_Z27volume_air_segmentation_gpuPKfjjjPbf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x28
	s_load_b32 s3, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mul_i32 s2, s5, s4
	s_mul_i32 s2, s2, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x18
	s_load_b32 s0, s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s0, v0
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	global_store_b8 v1, v0, s[4:5]
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27volume_air_segmentation_gpuPKfjjjPbf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z27volume_air_segmentation_gpuPKfjjjPbf,"axG",@progbits,_Z27volume_air_segmentation_gpuPKfjjjPbf,comdat
.Lfunc_end0:
	.size	_Z27volume_air_segmentation_gpuPKfjjjPbf, .Lfunc_end0-_Z27volume_air_segmentation_gpuPKfjjjPbf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 192
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z22detect_body_bounds_gpuPKbPjjjjjjj,"axG",@progbits,_Z22detect_body_bounds_gpuPKbPjjjjjjj,comdat
	.protected	_Z22detect_body_bounds_gpuPKbPjjjjjjj ; -- Begin function _Z22detect_body_bounds_gpuPKbPjjjjjjj
	.globl	_Z22detect_body_bounds_gpuPKbPjjjjjjj
	.p2align	8
	.type	_Z22detect_body_bounds_gpuPKbPjjjjjjj,@function
_Z22detect_body_bounds_gpuPKbPjjjjjjj:  ; @_Z22detect_body_bounds_gpuPKbPjjjjjjj
; %bb.0:
	s_mov_b32 s12, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[14:15], s[0:1], 0x20
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s13, 0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_lshl_b64 s[16:17], s[12:13], 2
	s_mov_b32 s19, s13
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, s16
	s_addc_u32 s17, s7, s17
	s_add_i32 s18, s12, s10
	s_add_i32 s3, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
	s_lshl_b64 s[20:21], s[18:19], 2
	s_add_u32 s20, s6, s20
	s_addc_u32 s21, s7, s21
	s_add_i32 s18, s18, s10
	global_store_b32 v1, v1, s[16:17]
	s_lshl_b64 s[16:17], s[18:19], 2
	global_store_b32 v1, v2, s[20:21]
	s_add_u32 s16, s6, s16
	s_addc_u32 s17, s7, s17
	s_add_i32 s18, s18, s10
	s_add_i32 s3, s9, -1
	s_lshl_b64 s[18:19], s[18:19], 2
	v_mov_b32_e32 v3, s3
	s_add_u32 s18, s6, s18
	s_addc_u32 s19, s7, s19
	s_clause 0x1
	global_store_b32 v1, v1, s[16:17]
	global_store_b32 v1, v3, s[18:19]
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v0
	s_cbranch_execz .LBB1_8
; %bb.3:
	v_mov_b32_e32 v1, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB1_7
; %bb.4:                                ; %.lr.ph.preheader
	s_mul_i32 s2, s12, s9
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s2, s8, v[0:1]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, s9
.LBB1_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_u8 v3, v1, s[4:5]
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v3, 1, v3
	v_cvt_f32_ubyte0_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v2, v2, v3 :: v_dual_add_nc_u32 v1, s8, v1
	s_cbranch_scc0 .LBB1_5
; %bb.6:                                ; %._crit_edge.loopexit
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v2
.LBB1_7:                                ; %._crit_edge
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v1
.LBB1_8:                                ; %Flow162
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s9, v0
	s_cbranch_execz .LBB1_14
; %bb.9:
	v_mov_b32_e32 v1, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB1_13
; %bb.10:                               ; %.lr.ph101
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s12, s9, v[0:1]
	s_mov_b32 s2, s8
	v_mul_lo_u32 v2, v1, s8
	v_mov_b32_e32 v1, 0
.LBB1_11:                               ; =>This Inner Loop Header: Depth=1
	global_load_u8 v3, v2, s[4:5]
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v3, 1, v3
	v_cvt_f32_ubyte0_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v1, v1, v3 :: v_dual_add_nc_u32 v2, 1, v2
	s_cbranch_scc0 .LBB1_11
; %bb.12:                               ; %._crit_edge102.loopexit
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
.LBB1_13:                               ; %._crit_edge102
	v_lshlrev_b32_e32 v0, 2, v0
	ds_store_b32 v0, v1 offset:4096
.LBB1_14:                               ; %Flow160
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_34
; %bb.15:
	s_max_u32 s22, s9, s8
	s_mov_b32 s3, 0
	s_cmp_eq_u32 s22, 0
	s_cbranch_scc1 .LBB1_34
; %bb.16:                               ; %.lr.ph106
	s_mov_b32 s13, s3
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[4:5], s[12:13], 2
	s_lshr_b32 s13, s8, 1
	s_add_u32 s4, s6, s4
	s_addc_u32 s5, s7, s5
	s_lshl_b32 s20, s10, 1
	s_lshr_b32 s23, s9, 1
	s_add_i32 s2, s20, s12
	s_mov_b32 s24, 0
	s_lshl_b64 s[16:17], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s6, s16
	s_addc_u32 s17, s7, s17
	s_add_u32 s0, s0, 40
	s_addc_u32 s1, s1, 0
	s_add_i32 s2, s12, s10
	s_mov_b32 s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s18, s6, s18
	s_addc_u32 s19, s7, s19
	s_add_i32 s2, s2, s20
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s6, s20
	s_addc_u32 s21, s7, s21
.LBB1_17:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_ge_u32 s24, s13
	s_cselect_b32 s26, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccnz .LBB1_21
; %bb.18:                               ;   in Loop: Header=BB1_17 Depth=1
	global_load_b32 v1, v0, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s24, v1
	s_cbranch_vccnz .LBB1_21
; %bb.19:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s10
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s11, v1
	s_cbranch_vccnz .LBB1_21
; %bb.20:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s24
	global_store_b32 v0, v1, s[4:5]
.LBB1_21:                               ;   in Loop: Header=BB1_17 Depth=1
	s_cmp_ge_u32 s24, s23
	s_cselect_b32 s25, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB1_25
; %bb.22:                               ;   in Loop: Header=BB1_17 Depth=1
	global_load_b32 v1, v0, s[16:17]
	s_waitcnt vmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s24, v1
	s_cbranch_vccnz .LBB1_25
; %bb.23:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s10
	ds_load_b32 v1, v1 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s14, v1
	s_cbranch_vccnz .LBB1_25
; %bb.24:                               ;   in Loop: Header=BB1_17 Depth=1
	s_load_b32 s2, s[0:1], 0x0
	v_mov_b32_e32 v1, s24
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s12
	s_lshl_b64 s[28:29], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s6, s28
	s_addc_u32 s29, s7, s29
	global_store_b32 v0, v1, s[28:29]
.LBB1_25:                               ;   in Loop: Header=BB1_17 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccnz .LBB1_29
; %bb.26:                               ;   in Loop: Header=BB1_17 Depth=1
	global_load_b32 v1, v0, s[18:19]
	s_cmp_ge_u32 s24, s8
	s_cselect_b32 s2, -1, 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s24, v1
	s_or_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_29
; %bb.27:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s10
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s11, v1
	s_cbranch_vccnz .LBB1_29
; %bb.28:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s24
	global_store_b32 v0, v1, s[18:19]
.LBB1_29:                               ;   in Loop: Header=BB1_17 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB1_33
; %bb.30:                               ;   in Loop: Header=BB1_17 Depth=1
	global_load_b32 v1, v0, s[20:21]
	s_cmp_ge_u32 s24, s9
	s_cselect_b32 s2, -1, 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s24, v1
	s_or_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_33
; %bb.31:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s10
	ds_load_b32 v1, v1 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s15, v1
	s_cbranch_vccnz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_17 Depth=1
	v_mov_b32_e32 v1, s24
	global_store_b32 v0, v1, s[20:21]
.LBB1_33:                               ;   in Loop: Header=BB1_17 Depth=1
	s_add_i32 s24, s24, 1
	s_add_i32 s10, s10, 4
	s_cmp_lg_u32 s22, s24
	s_cbranch_scc1 .LBB1_17
.LBB1_34:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22detect_body_bounds_gpuPKbPjjjjjjj
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z22detect_body_bounds_gpuPKbPjjjjjjj,"axG",@progbits,_Z22detect_body_bounds_gpuPKbPjjjjjjj,comdat
.Lfunc_end1:
	.size	_Z22detect_body_bounds_gpuPKbPjjjjjjj, .Lfunc_end1-_Z22detect_body_bounds_gpuPKbPjjjjjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 976
; NumSgprs: 32
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z23get_organ_mask_accs_gpuPKhhPj,"axG",@progbits,_Z23get_organ_mask_accs_gpuPKhhPj,comdat
	.protected	_Z23get_organ_mask_accs_gpuPKhhPj ; -- Begin function _Z23get_organ_mask_accs_gpuPKhhPj
	.globl	_Z23get_organ_mask_accs_gpuPKhhPj
	.p2align	8
	.type	_Z23get_organ_mask_accs_gpuPKhhPj,@function
_Z23get_organ_mask_accs_gpuPKhhPj:      ; @_Z23get_organ_mask_accs_gpuPKhhPj
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[6:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v3, 2, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s2, s15
	s_and_b32 s4, s4, 0xffff
	s_add_i32 s5, s5, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x10
	global_load_u8 v1, v1, s[6:7]
	s_mov_b32 s6, 0
	s_waitcnt lgkmcnt(0)
	v_and_b32_e64 v2, 0xff, s5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u16_e32 vcc_lo, v1, v2
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	global_atomic_add_u32 v3, v0, s[0:1]
.LBB2_1:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s7, v0, s5
	s_lshl_b32 s5, 1, s5
	s_and_not1_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s6, s6, s7
	s_cmp_lg_u32 s3, 0
	s_cbranch_scc1 .LBB2_1
; %bb.2:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB2_4
; %bb.3:
	s_add_i32 s8, s14, s4
	s_mov_b32 s9, 0
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
	s_lshl_b64 s[8:9], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s0, s8
	s_addc_u32 s7, s1, s9
	global_atomic_add_u32 v1, v2, s[6:7]
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
.LBB2_5:                                ; %ComputeLoop10
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s6, s3
	v_readlane_b32 s7, v0, s6
	s_lshl_b32 s6, 1, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s3, s3, s6
	s_add_i32 s5, s5, s7
	s_cmp_lg_u32 s3, 0
	s_cbranch_scc1 .LBB2_5
; %bb.6:                                ; %ComputeEnd11
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s3, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB2_8
; %bb.7:
	s_add_i32 s2, s2, s15
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
	s_add_i32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB2_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23get_organ_mask_accs_gpuPKhhPj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z23get_organ_mask_accs_gpuPKhhPj,"axG",@progbits,_Z23get_organ_mask_accs_gpuPKhhPj,comdat
.Lfunc_end2:
	.size	_Z23get_organ_mask_accs_gpuPKhhPj, .Lfunc_end2-_Z23get_organ_mask_accs_gpuPKhhPj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,"axG",@progbits,_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,comdat
	.protected	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j ; -- Begin function _Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
	.globl	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
	.p2align	8
	.type	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,@function
_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j: ; @_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x30
	s_load_b32 s3, s[0:1], 0x3c
	s_load_b32 s8, s[0:1], 0x28
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s10, s2, s15
	s_and_b32 s11, s3, 0xffff
	s_lshl_b64 s[2:3], s[8:9], 2
	s_add_i32 s10, s10, s14
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
	v_mad_u64_u32 v[1:2], null, s10, s11, v[0:1]
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_9
; %bb.1:
	global_load_u8 v0, v1, s[4:5]
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_and_b32_e64 v2, 0xff, s4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u16_e32 vcc_lo, v0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_9
; %bb.2:                                ; %.preheader
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v2, 0
	s_cmp_eq_u32 s8, 0
	s_mov_b32 s5, 0
	s_cbranch_scc1 .LBB3_8
; %bb.3:                                ; %.lr.ph.preheader
	s_add_u32 s10, s6, 4
	s_addc_u32 s11, s7, 0
	s_mov_b32 s15, 1
	s_mov_b32 s12, -1
	s_mov_b32 s14, 0
.LBB3_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s15, 1
	s_cbranch_scc1 .LBB3_6
; %bb.5:                                ;   in Loop: Header=BB3_4 Depth=1
	s_add_i32 s4, s12, -2
	s_mov_b32 s13, s5
	s_lshl_b64 s[16:17], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s16, s2, s16
	s_addc_u32 s17, s3, s17
	s_add_i32 s4, s12, -1
	s_lshl_b64 s[18:19], s[4:5], 2
	s_load_b32 s4, s[16:17], 0x0
	s_add_u32 s18, s2, s18
	s_addc_u32 s19, s3, s19
	s_lshl_b64 s[20:21], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s20
	s_addc_u32 s21, s3, s21
	s_clause 0x1
	s_load_b32 s13, s[18:19], 0x0
	s_load_b32 s16, s[20:21], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s13
	s_add_i32 s14, s4, s16
.LBB3_6:                                ;   in Loop: Header=BB3_4 Depth=1
	s_load_b32 s4, s[10:11], 0x0
	s_cmp_ge_u32 s15, s8
	v_mov_b32_e32 v0, s14
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s4, v1
	s_cselect_b32 s4, -1, 0
	s_add_i32 s13, s15, 1
	s_add_i32 s15, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s15
	s_or_b32 s4, vcc_lo, s4
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_add_i32 s12, s12, 3
	s_and_b32 s4, exec_lo, s4
	s_mov_b32 s15, s13
	s_or_b32 s9, s4, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_4
; %bb.7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s9
.LBB3_8:                                ; %._crit_edge
	v_mov_b32_e32 v3, 0
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_lshl_add_u32 v2, v2, 1, v2
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[6:7], off
	global_load_b32 v10, v[8:9], off
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(2)
	v_sub_nc_u32_e32 v13, 0, v2
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v5, v10, v2
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v10, v5
	v_sub_nc_u32_e32 v11, 0, v5
	v_rcp_iflag_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v10, v10
	v_mul_lo_u32 v11, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v10, v11
	v_add_nc_u32_e32 v4, v10, v11
	v_cvt_f32_u32_e32 v10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v1, v4
	v_rcp_iflag_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v4, v5
	v_add_nc_u32_e32 v12, 1, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	v_cvt_u32_f32_e32 v10, v10
	v_sub_nc_u32_e32 v11, v1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v13, v13, v10
	v_sub_nc_u32_e32 v14, v11, v5
	v_cmp_ge_u32_e32 vcc_lo, v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v12 :: v_dual_cndmask_b32 v11, v11, v14
	v_add_nc_u32_e32 v12, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e32 vcc_lo, v11, v5
	v_mul_hi_u32 v11, v10, v13
	v_cndmask_b32_e32 v4, v4, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_lo_u32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v5
	v_mul_hi_u32 v5, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v5, v2
	v_add_nc_u32_e32 v11, 1, v5
	v_sub_nc_u32_e32 v10, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v10, v2
	v_cmp_ge_u32_e32 vcc_lo, v10, v2
	v_dual_cndmask_b32 v5, v5, v11 :: v_dual_cndmask_b32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, 1, v5
	v_cmp_ge_u32_e32 vcc_lo, v10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v10, 1 :: v_dual_cndmask_b32 v5, v5, v11
	v_mul_lo_u32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	v_add_nc_u32_e32 v2, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_atomic_add_u32 v[1:2], v10, off
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, v5, v0, v1
	v_add_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_atomic_add_u32 v[1:2], v10, off
	s_clause 0x1
	global_load_b32 v1, v[6:7], off
	global_load_b32 v2, v[8:9], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, v0, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_atomic_add_u32 v[0:1], v10, off
.LBB3_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,"axG",@progbits,_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j,comdat
.Lfunc_end3:
	.size	_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j, .Lfunc_end3-_Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1036
; NumSgprs: 24
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,"axG",@progbits,_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,comdat
	.protected	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj ; -- Begin function _Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
	.globl	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
	.p2align	8
	.type	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,@function
_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj: ; @_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s12, s19, s18
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s12, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s2, s17
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB4_10
; %bb.1:                                ; %.preheader
	v_mov_b32_e32 v2, 0
	s_cmp_eq_u32 s16, 0
	s_mov_b32 s2, 0
	s_cbranch_scc1 .LBB4_5
; %bb.2:                                ; %.lr.ph
	s_mul_i32 s3, s12, s17
	s_mov_b32 s4, -1
	s_mov_b32 s5, s3
.LBB4_3:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s6, s4, 2
	v_cmp_gt_u32_e32 vcc_lo, s5, v1
	s_cmp_ge_u32 s6, s16
	s_cselect_b32 s6, -1, 0
	s_add_i32 s4, s4, 1
	s_or_b32 s6, vcc_lo, s6
	s_add_i32 s5, s5, s3
	v_mov_b32_e32 v2, s4
	s_and_b32 s6, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s6, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB4_3
; %bb.4:                                ; %Flow182
	s_or_b32 exec_lo, exec_lo, s2
.LBB4_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v2, s17
	s_mov_b32 s3, exec_lo
	v_add_nc_u32_e32 v6, s17, v5
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_u32_e64 v5, v6
	s_cbranch_execz .LBB4_9
; %bb.6:                                ; %.lr.ph143.preheader
	v_mad_u64_u32 v[3:4], null, s12, v5, s[12:13]
	v_add_nc_u32_e32 v0, -1, v5
	s_mov_b32 s4, 0
.LBB4_7:                                ; %.lr.ph143
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 2, v0
	v_cmp_lt_u32_e32 vcc_lo, v1, v3
	v_add_nc_u32_e32 v0, 1, v0
	v_add_nc_u32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_u32_e64 s2, v4, v6
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s4, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB4_7
; %bb.8:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_9:                                ; %Flow181
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_cvt_f32_u32_e32 v3, s12
	s_sub_i32 s2, 0, s12
	v_mul_lo_u32 v6, v5, s12
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	v_rcp_iflag_f32_e32 v3, v3
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v1, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s2, v3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v3, v15, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s12
	v_add_nc_u32_e32 v6, 1, v3
	v_sub_nc_u32_e32 v4, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s12, v4
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v16, v3, v6, vcc_lo
	v_add_lshl_u32 v11, v16, v5, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[11:12]
	v_lshlrev_b32_e32 v11, 2, v0
	v_mul_lo_u32 v16, s12, v16
	v_lshlrev_b64 v[13:14], 2, v[11:12]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	v_sub_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s0, v13
	global_load_b128 v[4:7], v[3:4], off
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v14, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
	global_load_b128 v[8:11], v[8:9], off
	v_mov_b32_e32 v3, v12
	s_sub_i32 s0, 0, s18
	s_clause 0x1
	global_load_b32 v0, v[13:14], off offset:8
	global_load_b32 v13, v[13:14], off
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	v_cvt_f32_u32_e32 v3, s18
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v14, v3
	s_waitcnt vmcnt(4)
	v_sub_nc_u32_e32 v4, v5, v4
	v_sub_nc_u32_e32 v5, v7, v6
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v14, 0x4f7ffffe, v14 :: v_dual_add_nc_u32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v14, v14
	s_waitcnt vmcnt(2)
	v_cvt_f32_u32_e32 v0, v0
	v_cvt_f32_u32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, s0, v14
	v_mul_hi_u32 v17, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v17
	v_mul_hi_u32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v14, s18
	v_sub_nc_u32_e32 v6, v15, v16
	v_cvt_f32_u32_e32 v16, s19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s18, v6
	v_div_scale_f32 v18, null, v16, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v20, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v18, v20, 1.0
	v_dual_fmac_f32 v20, v21, v20 :: v_dual_add_nc_u32 v7, 1, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v14, v7 :: v_dual_add_nc_u32 v4, 1, v4
	v_subrev_nc_u32_e32 v14, s18, v6
	v_cvt_f32_u32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v6, v6, v14 :: v_dual_add_nc_u32 v19, 1, v7
	v_div_scale_f32 v17, null, v3, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s18, v6
	v_rcp_f32_e32 v14, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v19, vcc_lo
	v_div_scale_f32 v22, vcc_lo, v4, v3, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v17, v14, 1.0
	v_fmac_f32_e32 v14, v7, v14
	v_div_scale_f32 v7, s0, v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v7, v20
	v_fma_f32 v24, -v18, v21, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, v24, v20 :: v_dual_mul_f32 v24, 0.5, v3
	v_mul_lo_u32 v19, v6, s18
	v_cvt_f32_u32_e32 v6, v6
	v_fma_f32 v7, -v18, v21, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v19
	v_cvt_f32_u32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, -0.5, v3
	v_dual_mul_f32 v19, v22, v14 :: v_dual_fmac_f32 v24, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v17, v19, v22
	v_dual_fmac_f32 v6, -0.5, v16 :: v_dual_fmac_f32 v19, v23, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v23, v6, v11
	v_fmac_f32_e32 v24, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v11, -v17, v19, v22
	v_fmac_f32_e32 v23, v15, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v11, v14, v19
	s_mov_b32 vcc_lo, s0
	v_fmac_f32_e32 v23, 0.5, v16
	v_div_fmas_f32 v7, v7, v20, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v6, v10, v3, v4
	v_div_fixup_f32 v7, v7, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v6, v24 :: v_dual_mul_f32 v3, v7, v23
	v_floor_f32_e32 v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v8, v3
	s_waitcnt vmcnt(1)
	v_cvt_f32_u32_e32 v3, v13
	v_fma_f32 v14, v6, v24, -v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v8, v0
	v_fma_f32 v8, v7, v23, -v8
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v9, v3 :: v_dual_lshlrev_b32 v0, 9, v0
	v_cvt_u32_f32_e32 v3, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v0, v2, v3
	v_mov_b32_e32 v3, v12
	v_add_nc_u32_e32 v11, 0x201, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
	v_lshlrev_b64 v[3:4], 2, v[11:12]
	v_add_nc_u32_e32 v11, 1, v2
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v10, v[3:4], off
	v_mov_b32_e32 v4, v12
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[6:7], v0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v0, v0, v8 :: v_dual_add_nc_u32 v3, 0x200, v2
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[11:12]
	v_cvt_f64_f32_e32 v[10:11], v0
	global_load_b32 v13, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
	v_cvt_f64_f32_e32 v[4:5], v8
	global_load_b32 v15, v[2:3], off
	v_cvt_f64_f32_e32 v[2:3], v14
	v_add_f64 v[8:9], -v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], -v[2:3], 1.0
	v_mul_f64 v[6:7], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[10:11]
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, v14, v13
	v_cvt_f64_f32_e32 v[13:14], v0
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[10:11], v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[8:9], v[13:14], v[6:7]
	v_mul_f64 v[2:3], v[2:3], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	v_cvt_f32_f64_e32 v3, v[2:3]
	v_mov_b32_e32 v2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB4_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,"axG",@progbits,_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj,comdat
.Lfunc_end4:
	.size	_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj, .Lfunc_end4-_Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1472
; NumSgprs: 22
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,"axG",@progbits,_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,comdat
	.protected	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj ; -- Begin function _Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
	.globl	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
	.p2align	8
	.type	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,@function
_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj: ; @_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s12, s19, s18
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s12, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s2, s17
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB5_10
; %bb.1:                                ; %.preheader
	v_mov_b32_e32 v2, 0
	s_cmp_eq_u32 s16, 0
	s_mov_b32 s2, 0
	s_cbranch_scc1 .LBB5_5
; %bb.2:                                ; %.lr.ph
	s_mul_i32 s3, s12, s17
	s_mov_b32 s4, -1
	s_mov_b32 s5, s3
.LBB5_3:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s6, s4, 2
	v_cmp_gt_u32_e32 vcc_lo, s5, v1
	s_cmp_ge_u32 s6, s16
	s_cselect_b32 s6, -1, 0
	s_add_i32 s4, s4, 1
	s_or_b32 s6, vcc_lo, s6
	s_add_i32 s5, s5, s3
	v_mov_b32_e32 v2, s4
	s_and_b32 s6, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s6, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB5_3
; %bb.4:                                ; %Flow183
	s_or_b32 exec_lo, exec_lo, s2
.LBB5_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v2, s17
	s_mov_b32 s3, exec_lo
	v_add_nc_u32_e32 v6, s17, v5
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_u32_e64 v5, v6
	s_cbranch_execz .LBB5_9
; %bb.6:                                ; %.lr.ph144.preheader
	v_mad_u64_u32 v[3:4], null, s12, v5, s[12:13]
	v_add_nc_u32_e32 v0, -1, v5
	s_mov_b32 s4, 0
.LBB5_7:                                ; %.lr.ph144
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 2, v0
	v_cmp_lt_u32_e32 vcc_lo, v1, v3
	v_add_nc_u32_e32 v0, 1, v0
	v_add_nc_u32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_u32_e64 s2, v4, v6
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s4, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB5_7
; %bb.8:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
.LBB5_9:                                ; %Flow182
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_cvt_f32_u32_e32 v3, s12
	s_sub_i32 s2, 0, s12
	v_mul_lo_u32 v6, v5, s12
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	v_rcp_iflag_f32_e32 v3, v3
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v1, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s2, v3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v3, v15, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s12
	v_add_nc_u32_e32 v6, 1, v3
	v_sub_nc_u32_e32 v4, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s12, v4
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v16, v3, v6, vcc_lo
	v_add_lshl_u32 v11, v16, v5, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[11:12]
	v_lshlrev_b32_e32 v11, 2, v0
	v_mul_lo_u32 v16, s12, v16
	v_lshlrev_b64 v[13:14], 2, v[11:12]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v13
	global_load_b128 v[4:7], v[3:4], off
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v14, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
	global_load_b128 v[8:11], v[8:9], off
	v_mov_b32_e32 v3, v12
	s_sub_i32 s0, 0, s18
	s_clause 0x1
	global_load_b32 v0, v[13:14], off offset:8
	global_load_b32 v12, v[13:14], off
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	v_cvt_f32_u32_e32 v3, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v13, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v13, 0x4f7ffffe, v13
	v_cvt_u32_f32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v14, s0, v13
	v_mul_hi_u32 v14, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, v13, v14
	v_sub_nc_u32_e32 v14, v15, v16
	v_mul_hi_u32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, v13, s18
	s_waitcnt vmcnt(4)
	v_sub_nc_u32_e32 v4, v5, v4
	v_sub_nc_u32_e32 v5, v7, v6
	v_sub_nc_u32_e32 v6, v14, v15
	v_cvt_f32_u32_e32 v15, s19
	v_add_nc_u32_e32 v7, 1, v13
	v_add_nc_u32_e32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s18, v6
	v_cvt_f32_u32_e32 v4, v4
	s_waitcnt vmcnt(2)
	v_cvt_f32_u32_e32 v0, v0
	v_cndmask_b32_e32 v7, v13, v7, vcc_lo
	v_subrev_nc_u32_e32 v13, s18, v6
	v_div_scale_f32 v16, null, v3, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v13, vcc_lo
	v_rcp_f32_e32 v13, v16
	v_add_nc_u32_e32 v18, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s18, v6
	v_dual_cndmask_b32 v6, v7, v18 :: v_dual_add_nc_u32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_u32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v16, v13, 1.0
	v_div_scale_f32 v21, vcc_lo, v4, v3, v4
	v_mul_lo_u32 v18, v6, s18
	v_div_scale_f32 v17, null, v15, v15, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v13, v7, v13
	v_div_scale_f32 v7, s0, v5, v15, v5
	v_rcp_f32_e32 v19, v17
	v_cvt_f32_u32_e32 v6, v6
	v_sub_nc_u32_e32 v14, v14, v18
	v_mul_f32_e32 v18, v21, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v6, -0.5, v15
	v_cvt_f32_u32_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fma_f32 v22, -v16, v18, v21
	v_fma_f32 v20, -v17, v19, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, -0.5, v3
	v_mul_f32_e32 v11, v6, v11
	v_fmac_f32_e32 v19, v20, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v14, v10
	v_fmac_f32_e32 v18, v22, v13
	v_mul_f32_e32 v20, v7, v19
	v_mul_f32_e32 v22, 0.5, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v11, 0.5, v15
	v_fma_f32 v16, -v16, v18, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, -v17, v20, v7
	v_fmac_f32_e32 v22, v8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v10, v16, v13, v18
	v_fmac_f32_e32 v20, v23, v19
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v22, v6, v9
	v_div_fixup_f32 v3, v10, v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v17, v20, v7
	v_mul_f32_e32 v6, v3, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v7, v7, v19, v20
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v5, v7, v15, v5
	s_waitcnt vmcnt(1)
	v_cvt_f32_u32_e32 v7, v12
	v_fma_f32 v12, v3, v22, -v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v4, v5, v11
	v_add_f32_e32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v4, v4
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v4, v0
	v_fma_f32 v9, v5, v11, -v4
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[4:5], v9
	v_lshlrev_b32_e32 v0, 9, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v2, v7
	global_load_u8 v7, v0, s[4:5]
	v_add_nc_u32_e32 v2, 0x201, v0
	global_load_u8 v8, v2, s[4:5]
	v_add_nc_u32_e32 v2, 1, v0
	v_add_nc_u32_e32 v0, 0x200, v0
	s_clause 0x1
	global_load_u8 v14, v2, s[4:5]
	global_load_u8 v0, v0, s[4:5]
	v_cvt_f64_f32_e32 v[2:3], v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], -v[2:3], 1.0
	s_waitcnt vmcnt(3)
	v_cvt_f64_u32_e32 v[6:7], v7
	s_waitcnt vmcnt(2)
	v_cvt_f32_ubyte0_e32 v8, v8
	v_mul_f32_e32 v8, v12, v8
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v8, v9
	v_add_f64 v[8:9], -v[4:5], 1.0
	v_mul_f32_e32 v0, v12, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[10:11], v10
	v_cvt_f64_f32_e32 v[12:13], v0
	v_mul_f64 v[6:7], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[10:11]
	v_cvt_f64_u32_e32 v[10:11], v14
	v_fma_f64 v[6:7], v[8:9], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[10:11]
	v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[2:3]
	v_cvt_f64_f32_e32 v[2:3], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], 0.5
	v_cvt_i32_f64_e32 v0, v[2:3]
	global_store_b8 v1, v0, s[6:7]
.LBB5_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,"axG",@progbits,_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj,comdat
.Lfunc_end5:
	.size	_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj, .Lfunc_end5-_Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1360
; NumSgprs: 22
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z16accumulation_gpuPfS_jj,"axG",@progbits,_Z16accumulation_gpuPfS_jj,comdat
	.protected	_Z16accumulation_gpuPfS_jj ; -- Begin function _Z16accumulation_gpuPfS_jj
	.globl	_Z16accumulation_gpuPfS_jj
	.p2align	8
	.type	_Z16accumulation_gpuPfS_jj,@function
_Z16accumulation_gpuPfS_jj:             ; @_Z16accumulation_gpuPfS_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB6_3
; %bb.1:
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s2, 0, s3
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s2, v0
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s3
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v2
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v3, v[0:1], off
.LBB6_2:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB6_2
.LBB6_3:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16accumulation_gpuPfS_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z16accumulation_gpuPfS_jj,"axG",@progbits,_Z16accumulation_gpuPfS_jj,comdat
.Lfunc_end6:
	.size	_Z16accumulation_gpuPfS_jj, .Lfunc_end6-_Z16accumulation_gpuPfS_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z24squared_accumulation_gpuPfS_S_jj,"axG",@progbits,_Z24squared_accumulation_gpuPfS_S_jj,comdat
	.protected	_Z24squared_accumulation_gpuPfS_S_jj ; -- Begin function _Z24squared_accumulation_gpuPfS_S_jj
	.globl	_Z24squared_accumulation_gpuPfS_S_jj
	.p2align	8
	.type	_Z24squared_accumulation_gpuPfS_S_jj,@function
_Z24squared_accumulation_gpuPfS_S_jj:   ; @_Z24squared_accumulation_gpuPfS_S_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB7_3
; %bb.1:
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s2, 0, s3
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_mul_lo_u32 v0, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v0
	v_subrev_nc_u32_e32 v2, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_subrev_nc_u32_e32 v3, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, v0, v3
	v_mov_b32_e32 v4, v2
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v0, v1
	v_frexp_mant_f32_e64 v0, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_ldexp_f32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, 1.0, v0
	v_add_f32_e32 v6, -1.0, v0
	v_rcp_f32_e32 v5, v1
	v_add_f32_e32 v8, -1.0, v1
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v0, v0, v8 :: v_dual_mul_f32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v1, v7
	v_fma_f32 v8, v7, v1, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v7, v0
	v_add_co_u32 v0, s0, s6, v2
	v_add_co_ci_u32_e64 v1, s0, s7, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v9, v8
	s_mov_b32 s0, 0x3e76c4e1
	global_load_b32 v3, v[0:1], off
	v_sub_f32_e32 v11, v6, v10
	v_sub_f32_e32 v2, v10, v9
	v_sub_f32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v2, v8
	v_sub_f32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v6
	v_add_f32_e32 v2, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v5, v2
	v_add_f32_e32 v5, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v5, v7
	v_dual_mul_f32 v7, v5, v5 :: v_dual_sub_f32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v5, v5, -v7
	v_add_f32_e32 v8, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v5, v8
	v_add_f32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmaak_f32 v9, s0, v8, 0x3e91f4c4
	v_dual_sub_f32 v7, v8, v7 :: v_dual_mul_f32 v12, v5, v8
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v4|
	v_dual_fmaak_f32 v9, v8, v9, 0x3ecccdef :: v_dual_sub_f32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v8, v5, -v12
	v_mul_f32_e32 v10, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, v8, v2
	v_fma_f32 v7, v8, v9, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v6, v9
	v_add_f32_e32 v9, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v9, v10 :: v_dual_add_f32 v11, 0x3f2aaaaa, v9
	v_dual_sub_f32 v7, v7, v10 :: v_dual_add_f32 v10, 0xbf2aaaaa, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, 0x31739010, v7
	v_sub_f32_e32 v9, v9, v10
	v_fmac_f32_e32 v13, v6, v5
	v_ldexp_f32 v5, v5, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, v7, v9
	v_add_f32_e32 v8, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v11, v7
	v_sub_f32_e32 v9, v11, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v8, v6
	v_sub_f32_e32 v11, v8, v12
	v_add_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v8, v6, -v10
	v_sub_f32_e32 v11, v13, v11
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v8, v7
	v_frexp_exp_i32_f32_e32 v7, v4
	v_fmac_f32_e32 v9, v11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	v_add_f32_e32 v7, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v6, v6
	v_mul_f32_e32 v11, 0x3f317218, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v7, v10
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3f317218, v6, -v11
	v_add_f32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v6, 0xb102e308, v10
	v_add_f32_e32 v8, v5, v7
	v_sub_f32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v7, v5
	v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v5, v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v8, v2
	v_sub_f32_e32 v11, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v5, v7
	v_sub_f32_e32 v6, v6, v11
	v_sub_f32_e32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v9, v5
	v_sub_f32_e32 v7, v7, v10
	v_sub_f32_e32 v12, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v12
	v_dual_sub_f32 v2, v2, v8 :: v_dual_add_f32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v6, v2
	v_add_f32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v8, v6 :: v_dual_add_f32 v10, v9, v5
	v_sub_f32_e32 v8, v8, v7
	v_sub_f32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v10, v9
	v_dual_sub_f32 v6, v6, v8 :: v_dual_sub_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v6
	v_add_f32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v10, v2
	v_sub_f32_e32 v6, v5, v10
	v_add_f32_e32 v7, v5, v5
	v_mul_f32_e32 v8, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, v2, v6
	v_fma_f32 v5, v5, 2.0, -v7
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 2.0, v2
	v_add_f32_e32 v2, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v2
	v_cndmask_b32_e32 v6, v5, v7, vcc_lo
	v_sub_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	v_sub_f32_e32 v2, v2, v5
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v6, v8 :: v_dual_cndmask_b32 v2, 0, v2
	v_mul_f32_e32 v10, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v8, v2
	v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v11, v9, 0x32a5705f, v11 :: v_dual_sub_f32 v10, v10, v12
	v_cvt_i32_f32_e32 v7, v12
	v_add_f32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v10, v7
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
	v_fma_f32 v2, v5, v2, v5
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v2, 0x7f800000, |v2|, s0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
.LBB7_2:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB7_2
.LBB7_3:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24squared_accumulation_gpuPfS_S_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z24squared_accumulation_gpuPfS_S_jj,"axG",@progbits,_Z24squared_accumulation_gpuPfS_S_jj,comdat
.Lfunc_end7:
	.size	_Z24squared_accumulation_gpuPfS_S_jj, .Lfunc_end7-_Z24squared_accumulation_gpuPfS_S_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1284
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z22mean_std_normalizationPfS_S_jj,"axG",@progbits,_Z22mean_std_normalizationPfS_S_jj,comdat
	.protected	_Z22mean_std_normalizationPfS_S_jj ; -- Begin function _Z22mean_std_normalizationPfS_S_jj
	.globl	_Z22mean_std_normalizationPfS_S_jj
	.p2align	8
	.type	_Z22mean_std_normalizationPfS_S_jj,@function
_Z22mean_std_normalizationPfS_S_jj:     ; @_Z22mean_std_normalizationPfS_S_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB8_2
; %bb.1:
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s2, 0, s3
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_mul_lo_u32 v0, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v0
	v_subrev_nc_u32_e32 v2, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_subrev_nc_u32_e32 v3, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, v0, v3
	v_mov_b32_e32 v4, v2
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v6, v[0:1], off
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v6, v4
	global_store_b32 v[0:1], v4, off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v3, null, v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v3, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v4, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v3, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v3, -v3, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v5, v7
	v_div_fixup_f32 v2, v3, v2, v4
	global_store_b32 v[0:1], v2, off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22mean_std_normalizationPfS_S_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z22mean_std_normalizationPfS_S_jj,"axG",@progbits,_Z22mean_std_normalizationPfS_S_jj,comdat
.Lfunc_end8:
	.size	_Z22mean_std_normalizationPfS_S_jj, .Lfunc_end8-_Z22mean_std_normalizationPfS_S_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 424
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27volume_air_segmentation_gpuPKfjjjPbf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z27volume_air_segmentation_gpuPKfjjjPbf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22detect_body_bounds_gpuPKbPjjjjjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z22detect_body_bounds_gpuPKbPjjjjjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           1
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23get_organ_mask_accs_gpuPKhhPj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23get_organ_mask_accs_gpuPKhhPj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           1
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z32get_organ_mask_accs_gpu_multiplePKhPjS1_hS1_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z28resize_volume_slice_and_cropPfS_PjS0_S_jjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z24resize_gt_slice_and_cropPhS_PjS0_Pfjjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16accumulation_gpuPfS_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16accumulation_gpuPfS_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24squared_accumulation_gpuPfS_S_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24squared_accumulation_gpuPfS_S_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22mean_std_normalizationPfS_S_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22mean_std_normalizationPfS_S_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
