/**
 * 3mm.cu: This file is part of the PolyBench/GPU 1.0 test suite.
 *
 *
 * Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
 * Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
 * Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
 */

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <cuda.h>

#define GPU_DEVICE 0

//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05

/* Problem size. */
//# define NI 512
//# define NJ 512
//# define NK 512
//# define NL 512
//# define NM 512

/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8

/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;

int NI;  
int NJ; 
int NK; 
int NL; 
int NM; 

void init_array(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* C, DATA_TYPE* D)
{
	int i, j;

	for (i = 0; i < NI; i++)
	{
		for (j = 0; j < NK; j++)
		{
			A[i*NK + j] = ((DATA_TYPE) i*j) / NI;
		}
	}
  
	for (i = 0; i < NK; i++)
	{
		for (j = 0; j < NJ; j++)
		{
			B[i*NJ + j] = ((DATA_TYPE) i*(j+1)) / NJ;
		}
	}
  
	for (i = 0; i < NJ; i++)
	{
		for (j = 0; j < NM; j++)
		{
			C[i*NM + j] = ((DATA_TYPE) i*(j+3)) / NL;
		}
	}
  
	for (i = 0; i < NM; i++)
	{
		for (j = 0; j < NL; j++)
		{
			D[i*NL + j] = ((DATA_TYPE) i*(j+2)) / NK;
		}
	}
}
	
__global__ void mm3_kernel1(DATA_TYPE *A, DATA_TYPE *B, DATA_TYPE *E,int NI, int NJ, int NK, int NL, int NM)
{
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;

	if ((i < NI) && (j < NJ))
	{
		int k;
		for(k=0; k < NK; k++)
		{
			E[i * NJ + j] += A[i * NK + k] * B[k * NJ + j];
		}
	}
}

	
__global__ void mm3_kernel2(DATA_TYPE *C, DATA_TYPE *D, DATA_TYPE *F,int NI, int NJ, int NK, int NL, int NM)
{
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;

	if ((i < NJ) && (j < NL))
	{
		int k;
		for(k=0; k < NM; k++)
		{
			F[i * NL + j] += C[i * NM + k] * D[k * NL +j];
		}
	}
}

	
__global__ void mm3_kernel3(DATA_TYPE *E, DATA_TYPE *F, DATA_TYPE *G, int NI, int NJ, int NK, int NL, int NM)
{
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;

	if ((i < NI) && (j < NL))
	{
		int k;
		for(k=0; k < NJ; k++)
		{
			G[i * NL + j] += E[i * NJ + k] * F[k * NL + j];
		}
	}
}


void mm3Cuda(DATA_TYPE* A_gpu, DATA_TYPE* B_gpu, DATA_TYPE* C_gpu, DATA_TYPE* D_gpu, DATA_TYPE* E_gpu, DATA_TYPE* F_gpu, 
		DATA_TYPE* G_gpu, int NI, int NJ, int NK, int NL, int NM)
{
	cudaEvent_t start, end;
	float time;

	
	dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
	dim3 grid1((size_t)(ceil( ((float)NJ) / ((float)DIM_THREAD_BLOCK_X) )),(size_t)(ceil((float)NI/ ((float)DIM_THREAD_BLOCK_Y) )));
	dim3 grid2((size_t)(ceil( ((float)NL) / ((float)DIM_THREAD_BLOCK_X) )),(size_t)(ceil((float)NJ/ ((float)DIM_THREAD_BLOCK_Y) )));
	dim3 grid3((size_t)(ceil( ((float)NL) / ((float)DIM_THREAD_BLOCK_X) )),(size_t)(ceil((float)NI/ ((float)DIM_THREAD_BLOCK_Y) )));

  //for(int i = 0; i < 5; i++){
    cudaEventCreate(&start);
    cudaEventCreate(&end);
    cudaEventRecord(start);

    mm3_kernel1<<<grid1,block>>>(A_gpu, B_gpu, E_gpu,NI, NJ, NK, NL, NM);
    cudaDeviceSynchronize();
    mm3_kernel2<<<grid2,block>>>(C_gpu, D_gpu, F_gpu,NI, NJ, NK, NL, NM);
    cudaDeviceSynchronize();
    mm3_kernel3<<<grid3,block>>>(E_gpu, F_gpu, G_gpu,NI, NJ, NK, NL, NM);
    cudaDeviceSynchronize();

    cudaEventRecord(end);
    cudaEventSynchronize(end);
    cudaEventElapsedTime(&time, start, end);

    fprintf(stdout, "%0.6lf\n", time);
  //}
}


int main(int argc, char** argv)
{

  if(argc < 2){
    printf("please no troll\n");
    return 1;
  }

  NI = atoi(argv[1]); 
  NJ = atoi(argv[1]);
  NK = atoi(argv[1]);
  NL = atoi(argv[1]);  
  NM = atoi(argv[1]);

	DATA_TYPE* A;
	DATA_TYPE* B;
	DATA_TYPE* C;
	DATA_TYPE* D;
	DATA_TYPE* E;
	DATA_TYPE* F;
	DATA_TYPE* G;

	cudaMallocManaged(&A, NI*NK*sizeof(DATA_TYPE));
	cudaMallocManaged(&B, NK*NJ*sizeof(DATA_TYPE));
	cudaMallocManaged(&C, NJ*NM*sizeof(DATA_TYPE));
	cudaMallocManaged(&D, NM*NL*sizeof(DATA_TYPE));
	cudaMallocManaged(&E, NI*NJ*sizeof(DATA_TYPE));
	cudaMallocManaged(&F, NJ*NL*sizeof(DATA_TYPE));
	cudaMallocManaged(&G, NI*NL*sizeof(DATA_TYPE));

	init_array(A, B, C, D);

	mm3Cuda(A, B, C, D, E, F, G, NI, NJ, NK, NL, NM); 

	cudaFree(A);
	cudaFree(B);
	cudaFree(C);
	cudaFree(D);
	cudaFree(E);
	cudaFree(F);
	cudaFree(G);

	return 0;
}


	.file	"tmpxft_0022f881_00000000-6_3mm_managed.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2045:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2045:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10init_arrayPfS_S_S_
	.type	_Z10init_arrayPfS_S_S_, @function
_Z10init_arrayPfS_S_S_:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdx, %r8
	movl	NI(%rip), %r11d
	movq	%rsi, %r9
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	NK(%rip), %edx
	movq	%rcx, %rsi
	xorl	%r10d, %r10d
	xorl	%ecx, %ecx
.L3:
	cmpl	%ecx, %r11d
	jle	.L5
	movslq	%r10d, %rax
	leaq	(%rdi,%rax,4), %rbx
	xorl	%eax, %eax
.L6:
	cmpl	%eax, %edx
	jle	.L21
	cvtsi2ssl	%eax, %xmm1
	cvtsi2ssl	%ecx, %xmm0
	mulss	%xmm1, %xmm0
	cvtsi2ssl	%r11d, %xmm1
	divss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	jmp	.L6
.L21:
	incl	%ecx
	addl	%edx, %r10d
	jmp	.L3
.L5:
	movl	NJ(%rip), %ecx
	xorl	%r11d, %r11d
	xorl	%edi, %edi
.L7:
	cmpl	%edi, %edx
	jle	.L9
	movslq	%r11d, %rax
	leaq	(%r9,%rax,4), %r10
	xorl	%eax, %eax
.L10:
	cmpl	%eax, %ecx
	jle	.L22
	incl	%eax
	cvtsi2ssl	%edi, %xmm0
	addq	$4, %r10
	cvtsi2ssl	%eax, %xmm1
	mulss	%xmm1, %xmm0
	cvtsi2ssl	%ecx, %xmm1
	divss	%xmm1, %xmm0
	movss	%xmm0, -4(%r10)
	jmp	.L10
.L22:
	incl	%edi
	addl	%ecx, %r11d
	jmp	.L7
.L9:
	movl	NM(%rip), %r10d
	movl	NL(%rip), %r9d
	xorl	%r11d, %r11d
	xorl	%edi, %edi
.L11:
	cmpl	%edi, %ecx
	jg	.L13
	xorl	%edi, %edi
	xorl	%ecx, %ecx
	jmp	.L14
.L13:
	movslq	%r11d, %rax
	leaq	(%r8,%rax,4), %rbx
	xorl	%eax, %eax
.L15:
	cmpl	%eax, %r10d
	jle	.L23
	cvtsi2ssl	%edi, %xmm1
	leal	3(%rax), %ebp
	cvtsi2ssl	%ebp, %xmm0
	mulss	%xmm1, %xmm0
	cvtsi2ssl	%r9d, %xmm1
	divss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	jmp	.L15
.L23:
	incl	%edi
	addl	%r10d, %r11d
	jmp	.L11
.L24:
	incl	%ecx
	addl	%r9d, %edi
.L14:
	cmpl	%ecx, %r10d
	jle	.L2
	movslq	%edi, %rax
	leaq	(%rsi,%rax,4), %r8
	xorl	%eax, %eax
.L18:
	cmpl	%eax, %r9d
	jle	.L24
	cvtsi2ssl	%ecx, %xmm1
	leal	2(%rax), %r11d
	cvtsi2ssl	%r11d, %xmm0
	mulss	%xmm1, %xmm0
	cvtsi2ssl	%edx, %xmm1
	divss	%xmm1, %xmm0
	movss	%xmm0, (%r8,%rax,4)
	incq	%rax
	jmp	.L18
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z10init_arrayPfS_S_S_, .-_Z10init_arrayPfS_S_S_
	.globl	_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii
	.type	_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii, @function
_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11mm3_kernel1PfS_S_iiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L25:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii, .-_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii
	.globl	_Z11mm3_kernel1PfS_S_iiiii
	.type	_Z11mm3_kernel1PfS_S_iiiii, @function
_Z11mm3_kernel1PfS_S_iiiii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii
	.cfi_endproc
.LFE2068:
	.size	_Z11mm3_kernel1PfS_S_iiiii, .-_Z11mm3_kernel1PfS_S_iiiii
	.globl	_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii
	.type	_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii, @function
_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11mm3_kernel2PfS_S_iiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L30:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii, .-_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii
	.globl	_Z11mm3_kernel2PfS_S_iiiii
	.type	_Z11mm3_kernel2PfS_S_iiiii, @function
_Z11mm3_kernel2PfS_S_iiiii:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii
	.cfi_endproc
.LFE2070:
	.size	_Z11mm3_kernel2PfS_S_iiiii, .-_Z11mm3_kernel2PfS_S_iiiii
	.globl	_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii
	.type	_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii, @function
_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11mm3_kernel3PfS_S_iiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L35:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii, .-_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii
	.globl	_Z11mm3_kernel3PfS_S_iiiii
	.type	_Z11mm3_kernel3PfS_S_iiiii, @function
_Z11mm3_kernel3PfS_S_iiiii:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii
	.cfi_endproc
.LFE2072:
	.size	_Z11mm3_kernel3PfS_S_iiiii, .-_Z11mm3_kernel3PfS_S_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"%0.6lf\n"
	.text
	.globl	_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	.type	_Z7mm3CudaPfS_S_S_S_S_S_iiiii, @function
_Z7mm3CudaPfS_S_S_S_S_S_iiiii:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdx, 24(%rsp)
	movq	%r8, 8(%rsp)
	movl	224(%rsp), %ebp
	movq	%r9, 16(%rsp)
	movl	232(%rsp), %r12d
	cvtsi2ssl	200(%rsp), %xmm0
	movq	%rax, 32(%rsp)
	mulss	.LC0(%rip), %xmm0
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	movabsq	$34359738400, %rax
	movl	$1, 80(%rsp)
	movq	%rax, 72(%rsp)
	call	ceilf@PLT
	comiss	.LC1(%rip), %xmm0
	jnb	.L41
	cvttss2siq	%xmm0, %rbx
	jmp	.L42
.L41:
	subss	.LC1(%rip), %xmm0
	cvttss2siq	%xmm0, %rbx
	btcq	$63, %rbx
.L42:
	cvtsi2ssl	208(%rsp), %xmm1
	movss	.LC2(%rip), %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm1, 44(%rsp)
	call	ceilf@PLT
	comiss	.LC1(%rip), %xmm0
	movss	44(%rsp), %xmm1
	jnb	.L43
	cvttss2siq	%xmm0, %rax
	jmp	.L44
.L43:
	subss	.LC1(%rip), %xmm0
	cvttss2siq	%xmm0, %rax
	btcq	$63, %rax
.L44:
	movss	.LC0(%rip), %xmm0
	movl	%eax, 84(%rsp)
	movl	%ebx, 88(%rsp)
	mulss	%xmm1, %xmm0
	movl	$1, 92(%rsp)
	call	ceilf@PLT
	movss	%xmm0, 44(%rsp)
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC2(%rip), %xmm0
	call	ceilf@PLT
	comiss	.LC1(%rip), %xmm0
	movss	44(%rsp), %xmm1
	jnb	.L45
	cvttss2siq	%xmm0, %rax
	jmp	.L46
.L45:
	subss	.LC1(%rip), %xmm0
	cvttss2siq	%xmm0, %rax
	btcq	$63, %rax
.L46:
	comiss	.LC1(%rip), %xmm1
	movl	%eax, 96(%rsp)
	movl	%eax, %edx
	jnb	.L47
	cvttss2siq	%xmm1, %rax
	jmp	.L48
.L47:
	subss	.LC1(%rip), %xmm1
	cvttss2siq	%xmm1, %rax
	btcq	$63, %rax
.L48:
	leaq	56(%rsp), %rdi
	movl	%edx, 108(%rsp)
	movl	%eax, 100(%rsp)
	movl	$1, 104(%rsp)
	movl	%ebx, 112(%rsp)
	movl	$1, 116(%rsp)
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	80(%rsp), %ecx
	movl	92(%rsp), %esi
	xorl	%r9d, %r9d
	movq	72(%rsp), %rdx
	movq	84(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	%r12
	.cfi_def_cfa_offset 200
	movq	%r14, %rdi
	movq	%r15, %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 208
	movl	232(%rsp), %r9d
	movl	224(%rsp), %r8d
	movl	216(%rsp), %ecx
	movq	24(%rsp), %rdx
	call	_Z40__device_stub__Z11mm3_kernel1PfS_S_iiiiiPfS_S_iiiii
	popq	%rdi
	.cfi_def_cfa_offset 200
	popq	%r8
	.cfi_def_cfa_offset 192
.L49:
	call	cudaDeviceSynchronize@PLT
	movl	80(%rsp), %ecx
	movl	104(%rsp), %esi
	xorl	%r9d, %r9d
	movq	72(%rsp), %rdx
	movq	96(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	%r12
	.cfi_def_cfa_offset 200
	movq	%r13, %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 208
	movl	232(%rsp), %r9d
	movl	224(%rsp), %r8d
	movl	216(%rsp), %ecx
	movq	32(%rsp), %rdx
	movq	40(%rsp), %rdi
	call	_Z40__device_stub__Z11mm3_kernel2PfS_S_iiiiiPfS_S_iiiii
	popq	%rcx
	.cfi_def_cfa_offset 200
	popq	%rsi
	.cfi_def_cfa_offset 192
.L50:
	call	cudaDeviceSynchronize@PLT
	movl	80(%rsp), %ecx
	movl	116(%rsp), %esi
	xorl	%r9d, %r9d
	movq	72(%rsp), %rdx
	movq	108(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	%r12
	.cfi_def_cfa_offset 200
	pushq	%rbp
	.cfi_def_cfa_offset 208
	movl	232(%rsp), %r9d
	movl	224(%rsp), %r8d
	movl	216(%rsp), %ecx
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z40__device_stub__Z11mm3_kernel3PfS_S_iiiiiPfS_S_iiiii
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L51:
	call	cudaDeviceSynchronize@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	leaq	52(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	stdout(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	movb	$1, %al
	movl	$2, %esi
	cvtss2sd	52(%rsp), %xmm0
	call	__fprintf_chk@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z7mm3CudaPfS_S_S_S_S_S_iiiii, .-_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	.section	.rodata.str1.1
.LC4:
	.string	"please no troll\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jg	.L55
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L54
.L55:
	movq	8(%rsi), %rbp
	movq	%rbp, %rdi
	call	atoi@PLT
	movq	%rbp, %rdi
	movl	%eax, %ebx
	movl	%eax, NI(%rip)
	call	atoi@PLT
	movq	%rbp, %rdi
	movl	%eax, NJ(%rip)
	call	atoi@PLT
	movq	%rbp, %rdi
	movl	%eax, %r12d
	movl	%eax, NK(%rip)
	call	atoi@PLT
	imull	%r12d, %ebx
	movq	%rbp, %rdi
	movl	%eax, NL(%rip)
	call	atoi@PLT
	movq	%rsp, %rdi
	movl	$1, %edx
	movslq	%ebx, %rsi
	movl	%eax, NM(%rip)
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	NK(%rip), %esi
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	imull	NJ(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	NJ(%rip), %esi
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	imull	NM(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	NM(%rip), %esi
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	imull	NL(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	NI(%rip), %esi
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	imull	NJ(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	NJ(%rip), %esi
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	imull	NL(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	NI(%rip), %esi
	leaq	48(%rsp), %rdi
	movl	$1, %edx
	imull	NL(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movq	24(%rsp), %r13
	movq	16(%rsp), %r12
	movq	8(%rsp), %rbp
	movq	(%rsp), %rbx
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_Z10init_arrayPfS_S_S_
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movl	NM(%rip), %eax
	movq	%rbx, %rdi
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	NL(%rip), %eax
	pushq	%rax
	.cfi_def_cfa_offset 128
	movl	NK(%rip), %eax
	pushq	%rax
	.cfi_def_cfa_offset 136
	movl	NJ(%rip), %eax
	pushq	%rax
	.cfi_def_cfa_offset 144
	movl	NI(%rip), %eax
	pushq	%rax
	.cfi_def_cfa_offset 152
	pushq	88(%rsp)
	.cfi_def_cfa_offset 160
	movq	88(%rsp), %r9
	movq	80(%rsp), %r8
	call	_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	movq	48(%rsp), %rdi
	addq	$48, %rsp
	.cfi_def_cfa_offset 112
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L54:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z11mm3_kernel3PfS_S_iiiii"
.LC6:
	.string	"_Z11mm3_kernel2PfS_S_iiiii"
.LC7:
	.string	"_Z11mm3_kernel1PfS_S_iiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2074:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11mm3_kernel3PfS_S_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11mm3_kernel2PfS_S_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11mm3_kernel1PfS_S_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2074:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	NM
	.bss
	.align 4
	.type	NM, @object
	.size	NM, 4
NM:
	.zero	4
	.globl	NL
	.align 4
	.type	NL, @object
	.size	NL, 4
NL:
	.zero	4
	.globl	NK
	.align 4
	.type	NK, @object
	.size	NK, 4
NK:
	.zero	4
	.globl	NJ
	.align 4
	.type	NJ, @object
	.size	NJ, 4
NJ:
	.zero	4
	.globl	NI
	.align 4
	.type	NI, @object
	.size	NI, 4
NI:
	.zero	4
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1040187392
	.align 4
.LC1:
	.long	1593835520
	.align 4
.LC2:
	.long	1023410176
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * 3mm.cu: This file is part of the PolyBench/GPU 1.0 test suite.
 *
 *
 * Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
 * Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
 * Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
 */

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>

#define GPU_DEVICE 0

//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05

/* Problem size. */
//# define NI 512
//# define NJ 512
//# define NK 512
//# define NL 512
//# define NM 512

/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8

/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;

int NI;  
int NJ; 
int NK; 
int NL; 
int NM; 

void init_array(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* C, DATA_TYPE* D)
{
	int i, j;

	for (i = 0; i < NI; i++)
	{
		for (j = 0; j < NK; j++)
		{
			A[i*NK + j] = ((DATA_TYPE) i*j) / NI;
		}
	}
  
	for (i = 0; i < NK; i++)
	{
		for (j = 0; j < NJ; j++)
		{
			B[i*NJ + j] = ((DATA_TYPE) i*(j+1)) / NJ;
		}
	}
  
	for (i = 0; i < NJ; i++)
	{
		for (j = 0; j < NM; j++)
		{
			C[i*NM + j] = ((DATA_TYPE) i*(j+3)) / NL;
		}
	}
  
	for (i = 0; i < NM; i++)
	{
		for (j = 0; j < NL; j++)
		{
			D[i*NL + j] = ((DATA_TYPE) i*(j+2)) / NK;
		}
	}
}
	
__global__ void mm3_kernel1(DATA_TYPE *A, DATA_TYPE *B, DATA_TYPE *E,int NI, int NJ, int NK, int NL, int NM)
{
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;

	if ((i < NI) && (j < NJ))
	{
		int k;
		for(k=0; k < NK; k++)
		{
			E[i * NJ + j] += A[i * NK + k] * B[k * NJ + j];
		}
	}
}

	
__global__ void mm3_kernel2(DATA_TYPE *C, DATA_TYPE *D, DATA_TYPE *F,int NI, int NJ, int NK, int NL, int NM)
{
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;

	if ((i < NJ) && (j < NL))
	{
		int k;
		for(k=0; k < NM; k++)
		{
			F[i * NL + j] += C[i * NM + k] * D[k * NL +j];
		}
	}
}

	
__global__ void mm3_kernel3(DATA_TYPE *E, DATA_TYPE *F, DATA_TYPE *G, int NI, int NJ, int NK, int NL, int NM)
{
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;

	if ((i < NI) && (j < NL))
	{
		int k;
		for(k=0; k < NJ; k++)
		{
			G[i * NL + j] += E[i * NJ + k] * F[k * NL + j];
		}
	}
}


void mm3Cuda(DATA_TYPE* A_gpu, DATA_TYPE* B_gpu, DATA_TYPE* C_gpu, DATA_TYPE* D_gpu, DATA_TYPE* E_gpu, DATA_TYPE* F_gpu, 
		DATA_TYPE* G_gpu, int NI, int NJ, int NK, int NL, int NM)
{
	hipEvent_t start, end;
	float time;

	
	dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
	dim3 grid1((size_t)(ceil( ((float)NJ) / ((float)DIM_THREAD_BLOCK_X) )),(size_t)(ceil((float)NI/ ((float)DIM_THREAD_BLOCK_Y) )));
	dim3 grid2((size_t)(ceil( ((float)NL) / ((float)DIM_THREAD_BLOCK_X) )),(size_t)(ceil((float)NJ/ ((float)DIM_THREAD_BLOCK_Y) )));
	dim3 grid3((size_t)(ceil( ((float)NL) / ((float)DIM_THREAD_BLOCK_X) )),(size_t)(ceil((float)NI/ ((float)DIM_THREAD_BLOCK_Y) )));

  //for(int i = 0; i < 5; i++){
    hipEventCreate(&start);
    hipEventCreate(&end);
    hipEventRecord(start);

    mm3_kernel1<<<grid1,block>>>(A_gpu, B_gpu, E_gpu,NI, NJ, NK, NL, NM);
    hipDeviceSynchronize();
    mm3_kernel2<<<grid2,block>>>(C_gpu, D_gpu, F_gpu,NI, NJ, NK, NL, NM);
    hipDeviceSynchronize();
    mm3_kernel3<<<grid3,block>>>(E_gpu, F_gpu, G_gpu,NI, NJ, NK, NL, NM);
    hipDeviceSynchronize();

    hipEventRecord(end);
    hipEventSynchronize(end);
    hipEventElapsedTime(&time, start, end);

    fprintf(stdout, "%0.6lf\n", time);
  //}
}


int main(int argc, char** argv)
{

  if(argc < 2){
    printf("please no troll\n");
    return 1;
  }

  NI = atoi(argv[1]); 
  NJ = atoi(argv[1]);
  NK = atoi(argv[1]);
  NL = atoi(argv[1]);  
  NM = atoi(argv[1]);

	DATA_TYPE* A;
	DATA_TYPE* B;
	DATA_TYPE* C;
	DATA_TYPE* D;
	DATA_TYPE* E;
	DATA_TYPE* F;
	DATA_TYPE* G;

	hipMallocManaged(&A, NI*NK*sizeof(DATA_TYPE));
	hipMallocManaged(&B, NK*NJ*sizeof(DATA_TYPE));
	hipMallocManaged(&C, NJ*NM*sizeof(DATA_TYPE));
	hipMallocManaged(&D, NM*NL*sizeof(DATA_TYPE));
	hipMallocManaged(&E, NI*NJ*sizeof(DATA_TYPE));
	hipMallocManaged(&F, NJ*NL*sizeof(DATA_TYPE));
	hipMallocManaged(&G, NI*NL*sizeof(DATA_TYPE));

	init_array(A, B, C, D);

	mm3Cuda(A, B, C, D, E, F, G, NI, NJ, NK, NL, NM); 

	hipFree(A);
	hipFree(B);
	hipFree(C);
	hipFree(D);
	hipFree(E);
	hipFree(F);
	hipFree(G);

	return 0;
}


	.text
	.file	"3mm_managed.hip"
	.globl	_Z10init_arrayPfS_S_S_          # -- Begin function _Z10init_arrayPfS_S_S_
	.type	_Z10init_arrayPfS_S_S_,@function
_Z10init_arrayPfS_S_S_:                 # @_Z10init_arrayPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	NI(%rip), %r8d
	movl	NK(%rip), %eax
	testl	%r8d, %r8d
	jle	.LBB0_6
# %bb.1:                                # %.preheader48.lr.ph
	cvtsi2ss	%r8d, %xmm0
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB0_2:                                # %.preheader48
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	testl	%eax, %eax
	jle	.LBB0_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r10d, %xmm1
	xorl	%ebx, %ebx
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm2, %xmm2
	cvtsi2ss	%ebx, %xmm2
	mulss	%xmm1, %xmm2
	divss	%xmm0, %xmm2
	movss	%xmm2, (%r11,%rbx,4)
	incq	%rbx
	cmpq	%rbx, %rax
	jne	.LBB0_4
.LBB0_5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r10
	addl	%eax, %r9d
	cmpq	%r8, %r10
	jne	.LBB0_2
.LBB0_6:                                # %.preheader47
	movl	NJ(%rip), %edi
	testl	%eax, %eax
	jle	.LBB0_12
# %bb.7:                                # %.preheader46.lr.ph
	xorps	%xmm0, %xmm0
	cvtsi2ss	%edi, %xmm0
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
.LBB0_8:                                # %.preheader46
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_10 Depth 2
	testl	%edi, %edi
	jle	.LBB0_11
# %bb.9:                                # %.lr.ph52
                                        #   in Loop: Header=BB0_8 Depth=1
	movl	%r8d, %r10d
	leaq	(%rsi,%r10,4), %r10
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r9d, %xmm1
	xorl	%r11d, %r11d
.LBB0_10:                               #   Parent Loop BB0_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	1(%r11), %rbx
	xorps	%xmm2, %xmm2
	cvtsi2ss	%ebx, %xmm2
	mulss	%xmm1, %xmm2
	divss	%xmm0, %xmm2
	movss	%xmm2, (%r10,%r11,4)
	movq	%rbx, %r11
	cmpq	%rbx, %rdi
	jne	.LBB0_10
.LBB0_11:                               # %._crit_edge53
                                        #   in Loop: Header=BB0_8 Depth=1
	incq	%r9
	addl	%edi, %r8d
	cmpq	%rax, %r9
	jne	.LBB0_8
.LBB0_12:                               # %.preheader45
	movl	NM(%rip), %esi
	testl	%edi, %edi
	jle	.LBB0_18
# %bb.13:                               # %.preheader44.lr.ph
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
	cvtsi2ssl	NL(%rip), %xmm0
	xorl	%r9d, %r9d
.LBB0_14:                               # %.preheader44
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_16 Depth 2
	testl	%esi, %esi
	jle	.LBB0_17
# %bb.15:                               # %.lr.ph56
                                        #   in Loop: Header=BB0_14 Depth=1
	movl	%r8d, %r10d
	leaq	(%rdx,%r10,4), %r10
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r9d, %xmm1
	xorl	%r11d, %r11d
.LBB0_16:                               #   Parent Loop BB0_14 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	3(%r11), %ebx
	xorps	%xmm2, %xmm2
	cvtsi2ss	%ebx, %xmm2
	mulss	%xmm1, %xmm2
	divss	%xmm0, %xmm2
	movss	%xmm2, (%r10,%r11,4)
	incq	%r11
	cmpq	%r11, %rsi
	jne	.LBB0_16
.LBB0_17:                               # %._crit_edge57
                                        #   in Loop: Header=BB0_14 Depth=1
	incq	%r9
	addl	%esi, %r8d
	cmpq	%rdi, %r9
	jne	.LBB0_14
.LBB0_18:                               # %.preheader43
	testl	%esi, %esi
	jle	.LBB0_24
# %bb.19:                               # %.preheader.lr.ph
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movl	NL(%rip), %eax
	xorl	%edx, %edx
	xorl	%edi, %edi
.LBB0_20:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_22 Depth 2
	testl	%eax, %eax
	jle	.LBB0_23
# %bb.21:                               # %.lr.ph60
                                        #   in Loop: Header=BB0_20 Depth=1
	movl	%edx, %r8d
	leaq	(%rcx,%r8,4), %r8
	xorps	%xmm1, %xmm1
	cvtsi2ss	%edi, %xmm1
	xorl	%r9d, %r9d
.LBB0_22:                               #   Parent Loop BB0_20 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	2(%r9), %r10d
	xorps	%xmm2, %xmm2
	cvtsi2ss	%r10d, %xmm2
	mulss	%xmm1, %xmm2
	divss	%xmm0, %xmm2
	movss	%xmm2, (%r8,%r9,4)
	incq	%r9
	cmpq	%r9, %rax
	jne	.LBB0_22
.LBB0_23:                               # %._crit_edge61
                                        #   in Loop: Header=BB0_20 Depth=1
	incq	%rdi
	addl	%eax, %edx
	cmpq	%rsi, %rdi
	jne	.LBB0_20
.LBB0_24:                               # %._crit_edge63
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z10init_arrayPfS_S_S_, .Lfunc_end0-_Z10init_arrayPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__mm3_kernel1PfS_S_iiiii # -- Begin function _Z26__device_stub__mm3_kernel1PfS_S_iiiii
	.type	_Z26__device_stub__mm3_kernel1PfS_S_iiiii,@function
_Z26__device_stub__mm3_kernel1PfS_S_iiiii: # @_Z26__device_stub__mm3_kernel1PfS_S_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11mm3_kernel1PfS_S_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__mm3_kernel1PfS_S_iiiii, .Lfunc_end1-_Z26__device_stub__mm3_kernel1PfS_S_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__mm3_kernel2PfS_S_iiiii # -- Begin function _Z26__device_stub__mm3_kernel2PfS_S_iiiii
	.type	_Z26__device_stub__mm3_kernel2PfS_S_iiiii,@function
_Z26__device_stub__mm3_kernel2PfS_S_iiiii: # @_Z26__device_stub__mm3_kernel2PfS_S_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11mm3_kernel2PfS_S_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__mm3_kernel2PfS_S_iiiii, .Lfunc_end2-_Z26__device_stub__mm3_kernel2PfS_S_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__mm3_kernel3PfS_S_iiiii # -- Begin function _Z26__device_stub__mm3_kernel3PfS_S_iiiii
	.type	_Z26__device_stub__mm3_kernel3PfS_S_iiiii,@function
_Z26__device_stub__mm3_kernel3PfS_S_iiiii: # @_Z26__device_stub__mm3_kernel3PfS_S_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11mm3_kernel3PfS_S_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z26__device_stub__mm3_kernel3PfS_S_iiiii, .Lfunc_end3-_Z26__device_stub__mm3_kernel3PfS_S_iiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z7mm3CudaPfS_S_S_S_S_S_iiiii
.LCPI4_0:
	.long	0x3d000000                      # float 0.03125
.LCPI4_1:
	.long	0x5f000000                      # float 9.22337203E+18
.LCPI4_2:
	.long	0x3e000000                      # float 0.125
	.text
	.globl	_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	.type	_Z7mm3CudaPfS_S_S_S_S_S_iiiii,@function
_Z7mm3CudaPfS_S_S_S_S_S_iiiii:          # @_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 32(%rsp)                   # 8-byte Spill
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	movq	%rdx, 56(%rsp)                  # 8-byte Spill
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	movl	176(%rsp), %r13d
	cvtsi2ssl	160(%rsp), %xmm0
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rbx
	movq	%rbx, %rax
	subss	.LCPI4_1(%rip), %xmm0
	cvttss2si	%xmm0, %rcx
	sarq	$63, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ssl	152(%rsp), %xmm0
	andl	%eax, %ecx
	orl	%ecx, %ebx
	mulss	.LCPI4_2(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rbp
	movq	%rbp, %rax
	sarq	$63, %rax
	subss	.LCPI4_1(%rip), %xmm0
	cvttss2si	%xmm0, %rcx
	andl	%eax, %ecx
	orl	%ecx, %ebp
	shlq	$32, %rbp
	orq	%rbp, %rbx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r13d, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r15
	movq	%r15, %rax
	subss	.LCPI4_1(%rip), %xmm0
	cvttss2si	%xmm0, %rcx
	sarq	$63, %rax
	andl	%eax, %ecx
	orl	%ecx, %r15d
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	mulss	.LCPI4_2(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r14
	movq	%r14, %rax
	sarq	$63, %rax
	subss	.LCPI4_1(%rip), %xmm0
	cvttss2si	%xmm0, %rcx
	andl	%eax, %ecx
	orl	%ecx, %r14d
	shlq	$32, %r14
	orq	%r15, %r14
	leaq	72(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	184(%rsp), %ebx
	movq	%r13, %r12
	movabsq	$34359738400, %r13              # imm = 0x800000020
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	152(%rsp), %ecx
	movl	160(%rsp), %r8d
	movl	168(%rsp), %r9d
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__mm3_kernel1PfS_S_iiiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB4_2:
	orq	%rbp, %r15
	callq	hipDeviceSynchronize
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movl	152(%rsp), %ecx
	movl	160(%rsp), %r8d
	movl	168(%rsp), %r9d
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__mm3_kernel2PfS_S_iiiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB4_4:
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	144(%rsp), %rdx
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movl	152(%rsp), %ecx
	movl	160(%rsp), %r8d
	movl	168(%rsp), %r9d
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__mm3_kernel3PfS_S_iiiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB4_6:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	72(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	84(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	stdout(%rip), %rdi
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str, %esi
	movb	$1, %al
	callq	fprintf
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z7mm3CudaPfS_S_S_S_S_S_iiiii, .Lfunc_end4-_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$1, %edi
	jg	.LBB5_2
# %bb.1:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %eax
	jmp	.LBB5_3
.LBB5_2:
	movq	8(%rsi), %rbx
	movq	%rbx, %rdi
	callq	atoi
	movl	%eax, %ebp
	movl	%eax, NI(%rip)
	movq	%rbx, %rdi
	callq	atoi
	movl	%eax, NJ(%rip)
	movq	%rbx, %rdi
	callq	atoi
	movl	%eax, %r14d
	movl	%eax, NK(%rip)
	movq	%rbx, %rdi
	callq	atoi
	movl	%eax, NL(%rip)
	movq	%rbx, %rdi
	callq	atoi
	movl	%eax, NM(%rip)
	imull	%ebp, %r14d
	movslq	%r14d, %rsi
	shlq	$2, %rsi
	movq	%rsp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	NK(%rip), %rax
	movslq	NJ(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	16(%rsp), %rdi
	movq	%rdi, %r14
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	NJ(%rip), %rax
	movslq	NM(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	48(%rsp), %r13
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	NM(%rip), %rax
	movslq	NL(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	40(%rsp), %r12
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	NI(%rip), %rax
	movslq	NJ(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	NJ(%rip), %rax
	movslq	NL(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	32(%rsp), %rbp
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	NI(%rip), %rax
	movslq	NL(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movq	(%r14), %rsi
	movq	(%r13), %rdx
	movq	(%r12), %rcx
	callq	_Z10init_arrayPfS_S_S_
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movq	(%r14), %rsi
	movq	(%r13), %rdx
	movq	(%r12), %rcx
	movq	(%rbx), %r8
	movq	(%rbp), %r9
	movl	NI(%rip), %r14d
	movl	NJ(%rip), %ebx
	movl	NK(%rip), %r11d
	movl	NL(%rip), %r10d
	movl	NM(%rip), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	_Z7mm3CudaPfS_S_S_S_S_S_iiiii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
	movq	%rsp, %rax
	movq	(%rax), %rdi
	callq	hipFree
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipFree
	movq	(%r13), %rdi
	callq	hipFree
	movq	(%r12), %rdi
	callq	hipFree
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipFree
	movq	(%rbp), %rdi
	callq	hipFree
	movq	(%r15), %rdi
	callq	hipFree
	xorl	%eax, %eax
.LBB5_3:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11mm3_kernel1PfS_S_iiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11mm3_kernel2PfS_S_iiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11mm3_kernel3PfS_S_iiiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	NI,@object                      # @NI
	.bss
	.globl	NI
	.p2align	2, 0x0
NI:
	.long	0                               # 0x0
	.size	NI, 4

	.type	NJ,@object                      # @NJ
	.globl	NJ
	.p2align	2, 0x0
NJ:
	.long	0                               # 0x0
	.size	NJ, 4

	.type	NK,@object                      # @NK
	.globl	NK
	.p2align	2, 0x0
NK:
	.long	0                               # 0x0
	.size	NK, 4

	.type	NL,@object                      # @NL
	.globl	NL
	.p2align	2, 0x0
NL:
	.long	0                               # 0x0
	.size	NL, 4

	.type	NM,@object                      # @NM
	.globl	NM
	.p2align	2, 0x0
NM:
	.long	0                               # 0x0
	.size	NM, 4

	.type	_Z11mm3_kernel1PfS_S_iiiii,@object # @_Z11mm3_kernel1PfS_S_iiiii
	.section	.rodata,"a",@progbits
	.globl	_Z11mm3_kernel1PfS_S_iiiii
	.p2align	3, 0x0
_Z11mm3_kernel1PfS_S_iiiii:
	.quad	_Z26__device_stub__mm3_kernel1PfS_S_iiiii
	.size	_Z11mm3_kernel1PfS_S_iiiii, 8

	.type	_Z11mm3_kernel2PfS_S_iiiii,@object # @_Z11mm3_kernel2PfS_S_iiiii
	.globl	_Z11mm3_kernel2PfS_S_iiiii
	.p2align	3, 0x0
_Z11mm3_kernel2PfS_S_iiiii:
	.quad	_Z26__device_stub__mm3_kernel2PfS_S_iiiii
	.size	_Z11mm3_kernel2PfS_S_iiiii, 8

	.type	_Z11mm3_kernel3PfS_S_iiiii,@object # @_Z11mm3_kernel3PfS_S_iiiii
	.globl	_Z11mm3_kernel3PfS_S_iiiii
	.p2align	3, 0x0
_Z11mm3_kernel3PfS_S_iiiii:
	.quad	_Z26__device_stub__mm3_kernel3PfS_S_iiiii
	.size	_Z11mm3_kernel3PfS_S_iiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%0.6lf\n"
	.size	.L.str, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11mm3_kernel1PfS_S_iiiii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11mm3_kernel2PfS_S_iiiii"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11mm3_kernel3PfS_S_iiiii"
	.size	.L__unnamed_3, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"please no troll"
	.size	.Lstr, 16

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__mm3_kernel1PfS_S_iiiii
	.addrsig_sym _Z26__device_stub__mm3_kernel2PfS_S_iiiii
	.addrsig_sym _Z26__device_stub__mm3_kernel3PfS_S_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11mm3_kernel1PfS_S_iiiii
	.addrsig_sym _Z11mm3_kernel2PfS_S_iiiii
	.addrsig_sym _Z11mm3_kernel3PfS_S_iiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11mm3_kernel1PfS_S_iiiii ; -- Begin function _Z11mm3_kernel1PfS_S_iiiii
	.globl	_Z11mm3_kernel1PfS_S_iiiii
	.p2align	8
	.type	_Z11mm3_kernel1PfS_S_iiiii,@function
_Z11mm3_kernel1PfS_S_iiiii:             ; @_Z11mm3_kernel1PfS_S_iiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s5, v0
	s_and_b32 s2, s2, vcc_lo
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mad_u64_u32 v[1:2], null, v4, s5, v[0:1]
	v_mul_lo_u32 v4, v4, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_load_b128 s[0:3], s[0:1], 0x0
	global_load_b32 v6, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s6, 0
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_nc_u32_e32 v0, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v1, v[4:5], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v1, v7
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11mm3_kernel1PfS_S_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11mm3_kernel1PfS_S_iiiii, .Lfunc_end0-_Z11mm3_kernel1PfS_S_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11mm3_kernel2PfS_S_iiiii ; -- Begin function _Z11mm3_kernel2PfS_S_iiiii
	.globl	_Z11mm3_kernel2PfS_S_iiiii
	.p2align	8
	.type	_Z11mm3_kernel2PfS_S_iiiii,@function
_Z11mm3_kernel2PfS_S_iiiii:             ; @_Z11mm3_kernel2PfS_S_iiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x1c
	s_load_b64 s[4:5], s[0:1], 0x24
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s6, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, s6, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_cmp_gt_i32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v0
	s_and_b32 s2, s2, vcc_lo
	s_cmp_gt_i32 s5, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mad_u64_u32 v[1:2], null, v4, s4, v[0:1]
	v_mul_lo_u32 v4, v4, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_load_b128 s[0:3], s[0:1], 0x0
	global_load_b32 v6, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s5, 0
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v1, v[4:5], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v1, v7
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB1_2
.LBB1_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11mm3_kernel2PfS_S_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11mm3_kernel2PfS_S_iiiii, .Lfunc_end1-_Z11mm3_kernel2PfS_S_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11mm3_kernel3PfS_S_iiiii ; -- Begin function _Z11mm3_kernel3PfS_S_iiiii
	.globl	_Z11mm3_kernel3PfS_S_iiiii
	.p2align	8
	.type	_Z11mm3_kernel3PfS_S_iiiii,@function
_Z11mm3_kernel3PfS_S_iiiii:             ; @_Z11mm3_kernel3PfS_S_iiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[4:5], s[0:1], 0x18
	s_load_b32 s6, s[0:1], 0x24
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s6, v0
	s_and_b32 s2, s2, vcc_lo
	s_cmp_gt_i32 s5, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mad_u64_u32 v[1:2], null, v4, s6, v[0:1]
	v_mul_lo_u32 v4, v4, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_load_b128 s[0:3], s[0:1], 0x0
	global_load_b32 v6, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s5, 0
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_nc_u32_e32 v0, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v1, v[4:5], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v1, v7
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB2_2
.LBB2_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11mm3_kernel3PfS_S_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11mm3_kernel3PfS_S_iiiii, .Lfunc_end2-_Z11mm3_kernel3PfS_S_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11mm3_kernel1PfS_S_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11mm3_kernel1PfS_S_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11mm3_kernel2PfS_S_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11mm3_kernel2PfS_S_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11mm3_kernel3PfS_S_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11mm3_kernel3PfS_S_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
