#include <stdio.h>
#include <stdint.h>
#include <math.h>
#include <cuda_runtime.h>
#define FLT_MIN 1.175494351e-38F
__device__ float FCC_KR = 0.3;
__device__ float FCC_KB = 0.11;
__device__ float SMPTE_240M_KR = 0.212;
__device__ float SMPTE_240M_KB = 0.087;
__device__ float REC_601_KR = 0.299;
__device__ float REC_601_KB = 0.114;
__device__ float REC_709_KR = 0.2126;
__device__ float REC_709_KB = 0.0722;
__device__ float REC_2020_KR = 0.2627;
__device__ float REC_2020_KB = 0.0593;

__device__ float REC709_ALPHA = 1.09929682680944f;
__device__ float REC709_BETA = 0.018053968510807f;

__device__ float ST2084_M1 = 0.1593017578125f;
__device__ float ST2084_M2 = 78.84375f;
__device__ float ST2084_C1 = 0.8359375f;
__device__ float ST2084_C2 = 18.8515625f;
__device__ float ST2084_C3 = 18.6875f;

__device__ float yuv2rgb_REC_2020_NCL[9] = {1.000000, 1.4196651e-17, 1.47459996, 1.000000, -0.164553121,  -0.571353137, 1.000000, 1.88139999, 5.67866042e-17};
__device__ float rgb2yuv_REC_709[9] = {0.212599993, 0.715200007, 0.0722000003, -0.114572108, -0.385427892, 0.500000, 0.500000, -0.454152912, -0.0458470918};
__device__ float gamutMa[9] = {1.66049099, -0.58764112, -0.0728498623, -0.124550477, 1.13289988, -0.00834942237, -0.0181507636, -0.100578897, 1.11872971};

struct FilterContext {
    unsigned filter_width;
    unsigned stride;
    float *data;
    int *left;
};

__global__ void doGPU(uint8_t *data, uint8_t *dst_data, int length) {
    int i = blockDim.x * blockIdx.x + threadIdx.x;
    if (i >= length)
        return;
    dst_data[i] = data[i];
}

__device__ void save_yuv(uint8_t *data, uint8_t *dst_data, int i) {
    for (int x = 0; x < 4; x++) {
        dst_data[x] = data[x];
    }
}

__device__ uint16_t clamp(uint16_t v, uint16_t min = 0, uint16_t max = 255) {
    if (v > max)
        return max;
    if (v < min)
        return min;
    return v;
}

__device__ float rec_709_oetf(float x){
    //[3] ToGammaLutOperationAVX2
    //if (x < 4.5f * REC709_BETA)
    //    x = x / 4.5f;
    //else
    //    x = pow((x + (REC709_ALPHA - 1.0f)) / REC709_ALPHA, 1.0f / 0.45f);
    //return x;
    //rec_1886_inverse_eotf
    return x < 0.0f ? 0.0f : pow(x, 1.0f / 2.4f);

}

__device__ float st_2084_eotf(float x){
    // [1] ToLinearLutOperationAVX2
    // Filter negative values to avoid NAN.
    if (x > 0.0f) {
        float xpow = pow(x, 1.0f / ST2084_M2);
        float num = max(xpow - ST2084_C1, 0.0f);
        float den = max(ST2084_C2 - ST2084_C3 * xpow, FLT_MIN);
        x = pow(num / den, 1.0f / ST2084_M1);
    } else {
        x = 0.0f;
    }
    return x;
}


__device__ void linear_to_gamma(float r, float g, float b, float *rr, float *rg, float *rb) {
    *rr = rec_709_oetf(r);
    *rg = rec_709_oetf(g);
    *rb = rec_709_oetf(b);
}

__device__ void gamma_to_linear(float r, float g, float b, float *rr, float *rg, float *rb) {
    *rr = 100.0*st_2084_eotf(r);
    *rg = 100.0*st_2084_eotf(g);
    *rb = 100.0*st_2084_eotf(b);
}

__device__ float int16_2floaty(uint16_t x){
    return float(x) * 0.00114155246 + -0.0730593577;
}
__device__ float int16_2float(uint16_t x){
    return float(x) * 0.00111607148 + -0.571428597;
}

__device__ uint16_t float_2int16y(float x){
    x = x * 876 + 64;
    float d = 0;
    x+=d;

    if(x<0.0f)
        x = 0.0f;
    if(x<float(1UL<<10)-1)
        return x;
    return float(1UL<<10)-1;
}

__device__ uint16_t float_2int16(float x){
    x = x * 876 + 512;
    float d = 0;
    x+=d;

    if(x<0.0f)
        x = 0.0f;
    if(x<float(1UL<<10)-1)
        return x;
    return float(1UL<<10)-1;
}

__device__ void yuv_to_rgb(uint16_t *y, uint16_t *u, uint16_t *v, uint16_t *ry, uint16_t *ru, uint16_t *rv) {
    // int to float

    float iy,iu,iv;
    iy = int16_2floaty(*y);
    iu = int16_2float(*u);
    iv = int16_2float(*v);

    float r = iy * yuv2rgb_REC_2020_NCL[0] + iu * yuv2rgb_REC_2020_NCL[1] + iv * yuv2rgb_REC_2020_NCL[2];
    float g = iy * yuv2rgb_REC_2020_NCL[3] + iu * yuv2rgb_REC_2020_NCL[4] + iv * yuv2rgb_REC_2020_NCL[5];
    float b = iy * yuv2rgb_REC_2020_NCL[6] + iu * yuv2rgb_REC_2020_NCL[7] + iv * yuv2rgb_REC_2020_NCL[8];

    float lr, lg, lb;
    gamma_to_linear(r,g,b, &lr, &lg, &lb);

    r = lr * gamutMa[0] + lg * gamutMa[1] + lb * gamutMa[2];
    g = lr * gamutMa[3] + lg * gamutMa[4] + lb * gamutMa[5];
    b = lr * gamutMa[6] + lg * gamutMa[7] + lb * gamutMa[8];

    float gr, gg, gb;
    linear_to_gamma(r,g,b, &gr, &gg, &gb);
    //gr = r; gg=g; gb=b;

    iy = gr * rgb2yuv_REC_709[0] + gg * rgb2yuv_REC_709[1] + gb * rgb2yuv_REC_709[2];
    iu = gr * rgb2yuv_REC_709[3] + gg * rgb2yuv_REC_709[4] + gb * rgb2yuv_REC_709[5];
    iv = gr * rgb2yuv_REC_709[6] + gg * rgb2yuv_REC_709[7] + gb * rgb2yuv_REC_709[8];

    // float to int
    *ry = clamp(float_2int16y(iy), 16*4, 235*4);
    *ru = clamp(float_2int16(iu), 16*4, 240*4);
    *rv = clamp(float_2int16(iv), 16*4, 240*4);

    //*ry = *y;
    //*ru = *u;
    //*rv = *v;
}


__global__ void
calc_colorspace(uint8_t *data0, uint8_t *data1, uint8_t *data2, int w, int h, int stride_y, int stride_uv,
                uint8_t *dst_data0, uint8_t *dst_data1, uint8_t *dst_data2, int colorspace) {
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    int iy = i/(w/2)*2;
    int ix = (i % (w/2)) *2;
    if (ix >= w || iy >= h)
        return;

    int ofy = iy * stride_y + ix;
    int ofuv = (iy>>1) * stride_uv + ix/2;

    uint16_t * srcy = (uint16_t *)data0;
    uint16_t * srcu = (uint16_t *)data1;
    uint16_t * srcv = (uint16_t *)data2;

    uint16_t * dsty = (uint16_t *)dst_data0;
    uint16_t * dstu = (uint16_t *)dst_data1;
    uint16_t * dstv = (uint16_t *)dst_data2;

    yuv_to_rgb(&srcy[ofy], &srcu[ofuv], &srcv[ofuv], &dsty[ofy], &dstu[ofuv], &dstv[ofuv]);
    yuv_to_rgb(&srcy[ofy + 1], &srcu[ofuv], &srcv[ofuv], &dsty[ofy + 1], &dstu[ofuv], &dstv[ofuv]);
    yuv_to_rgb(&srcy[ofy + stride_y], &srcu[ofuv], &srcv[ofuv], &dsty[ofy + stride_y], &dstu[ofuv], &dstv[ofuv]);
    yuv_to_rgb(&srcy[ofy + stride_y +1], &srcu[ofuv], &srcv[ofuv], &dsty[ofy + stride_y + 1], &dstu[ofuv], &dstv[ofuv]);
}

__global__ void colorspace(float *src0, float *src1, float *src2, float *dst0, float *dst1, float *dst2, int w, int h){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>w*h-1)
        return;
    float iy = src0[i];
    float iu = src1[i];
    float iv = src2[i];
    float r = iy * yuv2rgb_REC_2020_NCL[0] + iu * yuv2rgb_REC_2020_NCL[1] + iv * yuv2rgb_REC_2020_NCL[2];
    float g = iy * yuv2rgb_REC_2020_NCL[3] + iu * yuv2rgb_REC_2020_NCL[4] + iv * yuv2rgb_REC_2020_NCL[5];
    float b = iy * yuv2rgb_REC_2020_NCL[6] + iu * yuv2rgb_REC_2020_NCL[7] + iv * yuv2rgb_REC_2020_NCL[8];

    float lr, lg, lb;
    gamma_to_linear(r,g,b, &lr, &lg, &lb);

    r = lr * gamutMa[0] + lg * gamutMa[1] + lb * gamutMa[2];
    g = lr * gamutMa[3] + lg * gamutMa[4] + lb * gamutMa[5];
    b = lr * gamutMa[6] + lg * gamutMa[7] + lb * gamutMa[8];

    float gr, gg, gb;
    linear_to_gamma(r,g,b, &gr, &gg, &gb);
    //gr = r; gg=g; gb=b;

    dst0[i] = gr * rgb2yuv_REC_709[0] + gg * rgb2yuv_REC_709[1] + gb * rgb2yuv_REC_709[2];
    dst1[i] = gr * rgb2yuv_REC_709[3] + gg * rgb2yuv_REC_709[4] + gb * rgb2yuv_REC_709[5];
    dst2[i] = gr * rgb2yuv_REC_709[6] + gg * rgb2yuv_REC_709[7] + gb * rgb2yuv_REC_709[8];

    //yuv_to_rgb(&src0[i], &src1[i], &src2[i], &dst0[i], &dst1[i], &dst2[i]);
}

__global__ void resize_line_32_y(uint8_t *src, float *dst, int width, int height) {
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>width*height-1)
        return;
    dst[i] = int16_2floaty(src[i]);
}

__global__ void resize_line_32_uv(uint8_t *src, float *dst, int wi, int hi){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>wi*hi-1)
        return;

    int h = int(i / wi);
    int v = int(i % wi);
    int w = int(wi / 2);
    if (h == 0 || h == hi-1){
        if (v % 2 == 0 || v == wi - 1)
            dst[i] = int16_2float(src[int(h/2)*w +int(v / 2)]);
        else
            dst[i] = int16_2float(src[int(h/2) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2) * w + int(v / 2) + 1]) * 0.5;
    }
    else if (h % 2 == 0){
        if (v % 2 == 0 || v == wi - 1)
            dst[i] = int16_2float(src[int(h / 2 - 1) * w + int(v / 2)]) * 0.25 + int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.75;
        else{
            float x1 = int16_2float(src[int(h / 2 - 1) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2 - 1) * w + int(v / 2) + 1]) * 0.5;
            float x2 = int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2) * w + int(v / 2) + 1]) * 0.5;
            dst[i] = x1 * 0.25 + x2 * 0.75;
        }
    }
    else{
        if (v % 2 == 0 || v == wi - 1)
            dst[i] = int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.75 + int16_2float(src[int(h / 2 + 1) * w + int(v / 2)]) * 0.25;
        else{
            float x1 = int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2) * w + int(v / 2) + 1]) * 0.5;
            float x2 = int16_2float(src[int(h / 2 + 1) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2 + 1) * w + int(v / 2) + 1]) * 0.5;
            dst[i] = x1 * 0.75 + x2 * 0.25;
        }
    }
}

__global__ void stamp_line_32_y(float *src, uint8_t *dst, int wi, int hi){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>wi*hi-1)
        return;
    dst[i] = clamp(float_2int16y(src[i]), 16*4, 235*4);
}

__global__ void stamp_line_32_uv(float *src, uint8_t *dst, int wi, int hi){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>wi*hi-1)
        return;
    float x1,x2,x3;
    x1=x2=x3=0;
    int h = int(i / wi);
    int v = int(i % wi);
    int w = int(wi * 2);

    int sh = (h+1)/2;
    int sv = (v+1)/2;

    if (h == hi -1){
        float x1 = src[sh * w + sv] * 0.5 + src[(sh + 1) * w + sv] * 0.375 + src[(sh + 2) * w + sv] * 0.125;
        float x2 = src[sh * w + sv + 1] * 0.5 + src[(sh + 1) * w + sv + 1] * 0.375 + src[(sh + 2) * w + sv + 1] * 0.125;
        float x3 = src[sh * w + sv + 2] * 0.5 + src[(sh + 1) * w + sv + 2] * 0.375 + src[(sh + 2) * w + sv + 2] * 0.125;
    }
    else{
        float x1 = src[sh * w + sv] * 0.125 + src[(sh + 1) * w + sv] * 0.375 + src[(sh + 2) * w + sv] * 0.375 + src[(sh + 3) * w + sv] * 0.125;
        float x2 = src[sh * w + sv + 1] * 0.125 + src[(sh + 1) * w + sv + 1] * 0.375 + src[(sh + 2) * w + sv + 1] * 0.375 + src[(sh + 3) * w + sv + 1] * 0.125;
        float x3 = src[sh * w + sv + 2] * 0.125 + src[(sh + 1) * w + sv + 2] * 0.375 + src[(sh + 2) * w + sv + 2] * 0.375 + src[(sh + 3) * w + sv + 2] * 0.125;
    }
    dst[i] = clamp(float_2int16(x1 * 0.25 + x2 * 0.5 + x3 * 0.25), 16*4, 240*4);
}

extern "C" {
int
doitgpu(uint8_t *data0, uint8_t *data1, uint8_t *data2, int *linesize, int width, int height, int format, uint8_t *out0,
        uint8_t *out1, uint8_t *out2) {
    fprintf(stderr, "=====gpu====\n");
    uint8_t *cuda_data0, *cuda_data1, *cuda_data2;
    uint8_t *dst_data0, *dst_data1, *dst_data2;
    float *dst_w0, *dst_w1, *dst_w2, *dst_prt0, *dst_prt1, *dst_prt2;
    int length0 = linesize[0] * height;
    int length1 = linesize[1] * height >> 1;
    int length2 = linesize[2] * height >> 1;
    int stride_y = linesize[0]>>1;
    int stride_uv = linesize[1]>>1;

    cudaMalloc(&cuda_data0, length0);
    cudaMalloc(&cuda_data1, length1);
    cudaMalloc(&cuda_data2, length2);
    cudaMalloc(&dst_data0, length0);
    cudaMalloc(&dst_data1, length1);
    cudaMalloc(&dst_data2, length2);
    cudaMemcpy(cuda_data0, data0, length0, cudaMemcpyHostToDevice);
    cudaMemcpy(cuda_data1, data1, length1, cudaMemcpyHostToDevice);
    cudaMemcpy(cuda_data2, data2, length2, cudaMemcpyHostToDevice);

    cudaMalloc(&dst_w0, 4 * width * height);
    cudaMalloc(&dst_w1, 4 * width * height);
    cudaMalloc(&dst_w2, 4 * width * height);

    cudaMalloc(&dst_prt0, 4 * width * height);
    cudaMalloc(&dst_prt1, 4 * width * height);
    cudaMalloc(&dst_prt2, 4 * width * height);

    int blocks = (width * height +128 - 1)/128;
    int threads = 128;
    resize_line_32_y<<<blocks, threads>>>(cuda_data0, dst_w0, width, height);
    resize_line_32_uv<<<blocks, threads>>>(cuda_data1, dst_w1, width, height);
    resize_line_32_uv<<<blocks, threads>>>(cuda_data2, dst_w2, width, height);
    fprintf(stderr, "--resized\n");

    colorspace<<<blocks, threads>>>(dst_w0, dst_w1, dst_w2, dst_prt0, dst_prt1, dst_prt2, width, height);
    fprintf(stderr, "--colorspace\n");

    stamp_line_32_y<<<blocks, threads>>>(dst_prt0, dst_data0, width, height);

    blocks = (width * height / 4 + 128 - 1) / 128;
    threads = 128;
    //calc_colorspace <<<blocks, threads>>>(cuda_data0, cuda_data1, cuda_data2, width, height, stride_y, stride_uv,
    //                                      dst_data0, dst_data1, dst_data2, 0);
    stamp_line_32_uv<<<blocks, threads>>>(dst_prt1, dst_data1, width/2, height/2);
    stamp_line_32_uv<<<blocks, threads>>>(dst_prt2, dst_data2, width/2, height/2);
    fprintf(stderr, "--over\n");


    cudaMemcpy(out0, dst_data0, length0, cudaMemcpyDeviceToHost);
    cudaMemcpy(out1, dst_data1, length1, cudaMemcpyDeviceToHost);
    cudaMemcpy(out2, dst_data2, length2, cudaMemcpyDeviceToHost);
    cudaDeviceReset();

    return 0;
}

}
	.file	"tmpxft_00229ea9_00000000-6_colorhdr.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2041:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2041:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0:
.LFB2204:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2204:
	.size	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	.globl	_Z8save_yuvPhS_i
	.type	_Z8save_yuvPhS_i, @function
_Z8save_yuvPhS_i:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z8save_yuvPhS_i, .-_Z8save_yuvPhS_i
	.globl	_Z5clampttt
	.type	_Z5clampttt, @function
_Z5clampttt:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5clampttt, .-_Z5clampttt
	.globl	_Z12rec_709_oetff
	.type	_Z12rec_709_oetff, @function
_Z12rec_709_oetff:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z12rec_709_oetff, .-_Z12rec_709_oetff
	.globl	_Z12st_2084_eotff
	.type	_Z12st_2084_eotff, @function
_Z12st_2084_eotff:
.LFB2197:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z12rec_709_oetff
	.cfi_endproc
.LFE2197:
	.size	_Z12st_2084_eotff, .-_Z12st_2084_eotff
	.globl	_Z15linear_to_gammafffPfS_S_
	.type	_Z15linear_to_gammafffPfS_S_, @function
_Z15linear_to_gammafffPfS_S_:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z15linear_to_gammafffPfS_S_, .-_Z15linear_to_gammafffPfS_S_
	.globl	_Z15gamma_to_linearfffPfS_S_
	.type	_Z15gamma_to_linearfffPfS_S_, @function
_Z15gamma_to_linearfffPfS_S_:
.LFB2203:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2203:
	.size	_Z15gamma_to_linearfffPfS_S_, .-_Z15gamma_to_linearfffPfS_S_
	.globl	_Z13int16_2floatyt
	.type	_Z13int16_2floatyt, @function
_Z13int16_2floatyt:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z13int16_2floatyt, .-_Z13int16_2floatyt
	.globl	_Z12int16_2floatt
	.type	_Z12int16_2floatt, @function
_Z12int16_2floatt:
.LFB2199:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z13int16_2floatyt
	.cfi_endproc
.LFE2199:
	.size	_Z12int16_2floatt, .-_Z12int16_2floatt
	.globl	_Z13float_2int16yf
	.type	_Z13float_2int16yf, @function
_Z13float_2int16yf:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2035:
	.size	_Z13float_2int16yf, .-_Z13float_2int16yf
	.globl	_Z12float_2int16f
	.type	_Z12float_2int16f, @function
_Z12float_2int16f:
.LFB2201:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z13float_2int16yf
	.cfi_endproc
.LFE2201:
	.size	_Z12float_2int16f, .-_Z12float_2int16f
	.globl	_Z10yuv_to_rgbPtS_S_S_S_S_
	.type	_Z10yuv_to_rgbPtS_S_S_S_S_, @function
_Z10yuv_to_rgbPtS_S_S_S_S_:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2037:
	.size	_Z10yuv_to_rgbPtS_S_S_S_S_, .-_Z10yuv_to_rgbPtS_S_S_S_S_
	.globl	_Z27__device_stub__Z5doGPUPhS_iPhS_i
	.type	_Z27__device_stub__Z5doGPUPhS_iPhS_i, @function
_Z27__device_stub__Z5doGPUPhS_iPhS_i:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5doGPUPhS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L25:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z27__device_stub__Z5doGPUPhS_iPhS_i, .-_Z27__device_stub__Z5doGPUPhS_iPhS_i
	.globl	_Z5doGPUPhS_i
	.type	_Z5doGPUPhS_i, @function
_Z5doGPUPhS_i:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z5doGPUPhS_iPhS_i
	.cfi_endproc
.LFE2064:
	.size	_Z5doGPUPhS_i, .-_Z5doGPUPhS_i
	.globl	_Z50__device_stub__Z15calc_colorspacePhS_S_iiiiS_S_S_iPhS_S_iiiiS_S_S_i
	.type	_Z50__device_stub__Z15calc_colorspacePhS_S_iiiiS_S_S_iPhS_S_iiiiS_S_S_i, @function
_Z50__device_stub__Z15calc_colorspacePhS_S_iiiiS_S_S_iPhS_S_iiiiS_S_S_i:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	248(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	264(%rsp), %rax
	movl	%ecx, 36(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movl	%r9d, 28(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	%rsp, %rax
	movq	%rax, 200(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z15calc_colorspacePhS_S_iiiiS_S_S_i(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L31:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z50__device_stub__Z15calc_colorspacePhS_S_iiiiS_S_S_iPhS_S_iiiiS_S_S_i, .-_Z50__device_stub__Z15calc_colorspacePhS_S_iiiiS_S_S_iPhS_S_iiiiS_S_S_i
	.globl	_Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.type	_Z15calc_colorspacePhS_S_iiiiS_S_S_i, @function
_Z15calc_colorspacePhS_S_iiiiS_S_S_i:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z15calc_colorspacePhS_S_iiiiS_S_S_iPhS_S_iiiiS_S_S_i
	.cfi_endproc
.LFE2066:
	.size	_Z15calc_colorspacePhS_S_iiiiS_S_S_i, .-_Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.globl	_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii
	.type	_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii, @function
_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10colorspacePfS_S_S_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L36:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii, .-_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii
	.globl	_Z10colorspacePfS_S_S_S_S_ii
	.type	_Z10colorspacePfS_S_S_S_S_ii, @function
_Z10colorspacePfS_S_S_S_S_ii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii
	.cfi_endproc
.LFE2068:
	.size	_Z10colorspacePfS_S_S_S_S_ii, .-_Z10colorspacePfS_S_S_S_S_ii
	.globl	_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii
	.type	_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii, @function
_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16resize_line_32_yPhPfii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L41:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii, .-_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii
	.globl	_Z16resize_line_32_yPhPfii
	.type	_Z16resize_line_32_yPhPfii, @function
_Z16resize_line_32_yPhPfii:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii
	.cfi_endproc
.LFE2070:
	.size	_Z16resize_line_32_yPhPfii, .-_Z16resize_line_32_yPhPfii
	.globl	_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii
	.type	_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii, @function
_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17resize_line_32_uvPhPfii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L46:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii, .-_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii
	.globl	_Z17resize_line_32_uvPhPfii
	.type	_Z17resize_line_32_uvPhPfii, @function
_Z17resize_line_32_uvPhPfii:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii
	.cfi_endproc
.LFE2072:
	.size	_Z17resize_line_32_uvPhPfii, .-_Z17resize_line_32_uvPhPfii
	.globl	_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii
	.type	_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii, @function
_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15stamp_line_32_yPfPhii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L51:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii, .-_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii
	.globl	_Z15stamp_line_32_yPfPhii
	.type	_Z15stamp_line_32_yPfPhii, @function
_Z15stamp_line_32_yPfPhii:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii
	.cfi_endproc
.LFE2074:
	.size	_Z15stamp_line_32_yPfPhii, .-_Z15stamp_line_32_yPfPhii
	.globl	_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii
	.type	_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii, @function
_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16stamp_line_32_uvPfPhii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L56:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii, .-_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii
	.globl	_Z16stamp_line_32_uvPfPhii
	.type	_Z16stamp_line_32_uvPfPhii, @function
_Z16stamp_line_32_uvPfPhii:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii
	.cfi_endproc
.LFE2076:
	.size	_Z16stamp_line_32_uvPfPhii, .-_Z16stamp_line_32_uvPfPhii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"=====gpu====\n"
.LC1:
	.string	"--resized\n"
.LC2:
	.string	"--colorspace\n"
.LC3:
	.string	"--over\n"
	.text
	.globl	doitgpu
	.type	doitgpu, @function
doitgpu:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	movl	$2, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	leaq	.LC0(%rip), %rdx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	movl	%ebx, %r15d
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	248(%rsp), %rax
	movq	%rdi, 16(%rsp)
	movq	%rcx, 8(%rsp)
	movq	stderr(%rip), %rdi
	movq	%rax, 24(%rsp)
	movq	256(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	264(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	(%rcx), %eax
	movl	8(%rcx), %r14d
	imull	4(%rcx), %r15d
	imull	%ebx, %eax
	imull	%ebx, %r14d
	sarl	%r15d
	cltq
	movslq	%r15d, %r15
	movq	%rax, %rsi
	sarl	%r14d
	movq	%rax, 8(%rsp)
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movslq	%r14d, %r14
	leaq	56(%rsp), %rdi
	movq	%r15, %rsi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	leaq	64(%rsp), %rdi
	movq	%r14, %rsi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	leaq	80(%rsp), %rdi
	movq	%r15, %rsi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	leaq	88(%rsp), %rdi
	movq	%r14, %rsi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	48(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	movl	%ebx, %ebp
	movq	64(%rsp), %rdi
	imull	%r13d, %ebp
	movl	$1, %ecx
	movq	%r14, %rdx
	call	cudaMemcpy@PLT
	leaq	96(%rsp), %rdi
	leal	0(,%rbp,4), %r12d
	movslq	%r12d, %r12
	movq	%r12, %rsi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	%r12, %rsi
	leaq	104(%rsp), %rdi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	%r12, %rsi
	leaq	112(%rsp), %rdi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	%r12, %rsi
	leaq	120(%rsp), %rdi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	%r12, %rsi
	leaq	128(%rsp), %rdi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	movq	%r12, %rsi
	leaq	136(%rsp), %rdi
	call	_Z10cudaMallocIhE9cudaErrorPPT_m.isra.0
	leal	127(%rbp), %eax
	movl	$128, %esi
	xorl	%r9d, %r9d
	cltd
	movl	$33554433, %ecx
	xorl	%r8d, %r8d
	movl	$1, 164(%rsp)
	idivl	%esi
	salq	$7, %rcx
	movq	%rcx, 156(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 144(%rsp)
	movl	%eax, %r12d
	movabsq	$4294967297, %rax
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	96(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%r13d, %edx
	call	_Z40__device_stub__Z16resize_line_32_yPhPfiiPhPfii
.L62:
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$7, %rdx
	movl	%r12d, 144(%rsp)
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	movq	%rdx, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	movq	104(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%r13d, %edx
	call	_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii
.L63:
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$7, %rdx
	movl	%r12d, 144(%rsp)
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	movq	%rdx, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	movq	112(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%r13d, %edx
	call	_Z41__device_stub__Z17resize_line_32_uvPhPfiiPhPfii
.L64:
	movq	stderr(%rip), %rdi
	leaq	.LC1(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$7, %rdx
	movl	$1, %ecx
	movl	%r12d, 144(%rsp)
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	movq	%rdx, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	pushq	%rbx
	.cfi_def_cfa_offset 248
	pushq	%r13
	.cfi_def_cfa_offset 256
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z42__device_stub__Z10colorspacePfS_S_S_S_S_iiPfS_S_S_S_S_ii
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L65:
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$7, %rdx
	movl	$1, %ecx
	movl	%r12d, 144(%rsp)
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	movq	%rdx, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	movq	72(%rsp), %rsi
	movq	120(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%r13d, %edx
	call	_Z39__device_stub__Z15stamp_line_32_yPfPhiiPfPhii
.L66:
	movl	%ebp, %eax
	movl	$4, %esi
	movl	$33554433, %ecx
	xorl	%r9d, %r9d
	cltd
	salq	$7, %rcx
	xorl	%r8d, %r8d
	movl	$1, 164(%rsp)
	idivl	%esi
	movq	%rcx, 156(%rsp)
	movl	$128, %esi
	addl	$127, %eax
	cltd
	idivl	%esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 144(%rsp)
	movl	%eax, %ebp
	movabsq	$4294967297, %rax
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movl	%ebx, %eax
	movl	$2, %esi
	movq	128(%rsp), %rdi
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	%r13d, %eax
	cltd
	idivl	%esi
	movq	80(%rsp), %rsi
	movl	%eax, %edx
	call	_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii
.L67:
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$7, %rdx
	movl	%ebp, 144(%rsp)
	movq	%rax, 148(%rsp)
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	movq	%rdx, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movl	%ebx, %eax
	movl	$2, %esi
	movq	136(%rsp), %rdi
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	%r13d, %eax
	cltd
	idivl	%esi
	movq	88(%rsp), %rsi
	movl	%eax, %edx
	call	_Z40__device_stub__Z16stamp_line_32_uvPfPhiiPfPhii
.L68:
	movq	stderr(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	80(%rsp), %rsi
	movq	32(%rsp), %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rsi
	movq	40(%rsp), %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	call	cudaDeviceReset@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L69
	call	__stack_chk_fail@PLT
.L69:
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	doitgpu, .-doitgpu
	.section	.rodata.str1.1
.LC4:
	.string	"_Z16stamp_line_32_uvPfPhii"
.LC5:
	.string	"_Z15stamp_line_32_yPfPhii"
.LC6:
	.string	"_Z17resize_line_32_uvPhPfii"
.LC7:
	.string	"_Z16resize_line_32_yPhPfii"
.LC8:
	.string	"_Z10colorspacePfS_S_S_S_S_ii"
.LC9:
	.string	"_Z15calc_colorspacePhS_S_iiiiS_S_S_i"
.LC10:
	.string	"_Z5doGPUPhS_i"
.LC11:
	.string	"FCC_KR"
.LC12:
	.string	"FCC_KB"
.LC13:
	.string	"SMPTE_240M_KR"
.LC14:
	.string	"SMPTE_240M_KB"
.LC15:
	.string	"REC_601_KR"
.LC16:
	.string	"REC_601_KB"
.LC17:
	.string	"REC_709_KR"
.LC18:
	.string	"REC_709_KB"
.LC19:
	.string	"REC_2020_KR"
.LC20:
	.string	"REC_2020_KB"
.LC21:
	.string	"REC709_ALPHA"
.LC22:
	.string	"REC709_BETA"
.LC23:
	.string	"ST2084_M1"
.LC24:
	.string	"ST2084_M2"
.LC25:
	.string	"ST2084_C1"
.LC26:
	.string	"ST2084_C2"
.LC27:
	.string	"ST2084_C3"
.LC28:
	.string	"yuv2rgb_REC_2020_NCL"
.LC29:
	.string	"rgb2yuv_REC_709"
.LC30:
	.string	"gamutMa"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2078:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16stamp_line_32_uvPfPhii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15stamp_line_32_yPfPhii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17resize_line_32_uvPhPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z16resize_line_32_yPhPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10colorspacePfS_S_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15calc_colorspacePhS_S_iiiiS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5doGPUPhS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL6FCC_KR(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL6FCC_KB(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL13SMPTE_240M_KR(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL13SMPTE_240M_KB(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL10REC_601_KR(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL10REC_601_KB(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL10REC_709_KR(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL10REC_709_KB(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL11REC_2020_KR(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL11REC_2020_KB(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL12REC709_ALPHA(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL11REC709_BETA(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9ST2084_M1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9ST2084_M2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC25(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9ST2084_C1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC26(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9ST2084_C2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9ST2084_C3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL20yuv2rgb_REC_2020_NCL(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL15rgb2yuv_REC_709(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$36, %r9d
	movq	%rdx, %rcx
	leaq	_ZL7gamutMa(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2078:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7gamutMa
	.comm	_ZL7gamutMa,36,32
	.local	_ZL15rgb2yuv_REC_709
	.comm	_ZL15rgb2yuv_REC_709,36,32
	.local	_ZL20yuv2rgb_REC_2020_NCL
	.comm	_ZL20yuv2rgb_REC_2020_NCL,36,32
	.local	_ZL9ST2084_C3
	.comm	_ZL9ST2084_C3,4,4
	.local	_ZL9ST2084_C2
	.comm	_ZL9ST2084_C2,4,4
	.local	_ZL9ST2084_C1
	.comm	_ZL9ST2084_C1,4,4
	.local	_ZL9ST2084_M2
	.comm	_ZL9ST2084_M2,4,4
	.local	_ZL9ST2084_M1
	.comm	_ZL9ST2084_M1,4,4
	.local	_ZL11REC709_BETA
	.comm	_ZL11REC709_BETA,4,4
	.local	_ZL12REC709_ALPHA
	.comm	_ZL12REC709_ALPHA,4,4
	.local	_ZL11REC_2020_KB
	.comm	_ZL11REC_2020_KB,4,4
	.local	_ZL11REC_2020_KR
	.comm	_ZL11REC_2020_KR,4,4
	.local	_ZL10REC_709_KB
	.comm	_ZL10REC_709_KB,4,4
	.local	_ZL10REC_709_KR
	.comm	_ZL10REC_709_KR,4,4
	.local	_ZL10REC_601_KB
	.comm	_ZL10REC_601_KB,4,4
	.local	_ZL10REC_601_KR
	.comm	_ZL10REC_601_KR,4,4
	.local	_ZL13SMPTE_240M_KB
	.comm	_ZL13SMPTE_240M_KB,4,4
	.local	_ZL13SMPTE_240M_KR
	.comm	_ZL13SMPTE_240M_KR,4,4
	.local	_ZL6FCC_KB
	.comm	_ZL6FCC_KB,4,4
	.local	_ZL6FCC_KR
	.comm	_ZL6FCC_KR,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdint.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define FLT_MIN 1.175494351e-38F
__device__ float FCC_KR = 0.3;
__device__ float FCC_KB = 0.11;
__device__ float SMPTE_240M_KR = 0.212;
__device__ float SMPTE_240M_KB = 0.087;
__device__ float REC_601_KR = 0.299;
__device__ float REC_601_KB = 0.114;
__device__ float REC_709_KR = 0.2126;
__device__ float REC_709_KB = 0.0722;
__device__ float REC_2020_KR = 0.2627;
__device__ float REC_2020_KB = 0.0593;

__device__ float REC709_ALPHA = 1.09929682680944f;
__device__ float REC709_BETA = 0.018053968510807f;

__device__ float ST2084_M1 = 0.1593017578125f;
__device__ float ST2084_M2 = 78.84375f;
__device__ float ST2084_C1 = 0.8359375f;
__device__ float ST2084_C2 = 18.8515625f;
__device__ float ST2084_C3 = 18.6875f;

__device__ float yuv2rgb_REC_2020_NCL[9] = {1.000000, 1.4196651e-17, 1.47459996, 1.000000, -0.164553121,  -0.571353137, 1.000000, 1.88139999, 5.67866042e-17};
__device__ float rgb2yuv_REC_709[9] = {0.212599993, 0.715200007, 0.0722000003, -0.114572108, -0.385427892, 0.500000, 0.500000, -0.454152912, -0.0458470918};
__device__ float gamutMa[9] = {1.66049099, -0.58764112, -0.0728498623, -0.124550477, 1.13289988, -0.00834942237, -0.0181507636, -0.100578897, 1.11872971};

struct FilterContext {
    unsigned filter_width;
    unsigned stride;
    float *data;
    int *left;
};

__global__ void doGPU(uint8_t *data, uint8_t *dst_data, int length) {
    int i = blockDim.x * blockIdx.x + threadIdx.x;
    if (i >= length)
        return;
    dst_data[i] = data[i];
}

__device__ void save_yuv(uint8_t *data, uint8_t *dst_data, int i) {
    for (int x = 0; x < 4; x++) {
        dst_data[x] = data[x];
    }
}

__device__ uint16_t clamp(uint16_t v, uint16_t min = 0, uint16_t max = 255) {
    if (v > max)
        return max;
    if (v < min)
        return min;
    return v;
}

__device__ float rec_709_oetf(float x){
    //[3] ToGammaLutOperationAVX2
    //if (x < 4.5f * REC709_BETA)
    //    x = x / 4.5f;
    //else
    //    x = pow((x + (REC709_ALPHA - 1.0f)) / REC709_ALPHA, 1.0f / 0.45f);
    //return x;
    //rec_1886_inverse_eotf
    return x < 0.0f ? 0.0f : pow(x, 1.0f / 2.4f);

}

__device__ float st_2084_eotf(float x){
    // [1] ToLinearLutOperationAVX2
    // Filter negative values to avoid NAN.
    if (x > 0.0f) {
        float xpow = pow(x, 1.0f / ST2084_M2);
        float num = max(xpow - ST2084_C1, 0.0f);
        float den = max(ST2084_C2 - ST2084_C3 * xpow, FLT_MIN);
        x = pow(num / den, 1.0f / ST2084_M1);
    } else {
        x = 0.0f;
    }
    return x;
}


__device__ void linear_to_gamma(float r, float g, float b, float *rr, float *rg, float *rb) {
    *rr = rec_709_oetf(r);
    *rg = rec_709_oetf(g);
    *rb = rec_709_oetf(b);
}

__device__ void gamma_to_linear(float r, float g, float b, float *rr, float *rg, float *rb) {
    *rr = 100.0*st_2084_eotf(r);
    *rg = 100.0*st_2084_eotf(g);
    *rb = 100.0*st_2084_eotf(b);
}

__device__ float int16_2floaty(uint16_t x){
    return float(x) * 0.00114155246 + -0.0730593577;
}
__device__ float int16_2float(uint16_t x){
    return float(x) * 0.00111607148 + -0.571428597;
}

__device__ uint16_t float_2int16y(float x){
    x = x * 876 + 64;
    float d = 0;
    x+=d;

    if(x<0.0f)
        x = 0.0f;
    if(x<float(1UL<<10)-1)
        return x;
    return float(1UL<<10)-1;
}

__device__ uint16_t float_2int16(float x){
    x = x * 876 + 512;
    float d = 0;
    x+=d;

    if(x<0.0f)
        x = 0.0f;
    if(x<float(1UL<<10)-1)
        return x;
    return float(1UL<<10)-1;
}

__device__ void yuv_to_rgb(uint16_t *y, uint16_t *u, uint16_t *v, uint16_t *ry, uint16_t *ru, uint16_t *rv) {
    // int to float

    float iy,iu,iv;
    iy = int16_2floaty(*y);
    iu = int16_2float(*u);
    iv = int16_2float(*v);

    float r = iy * yuv2rgb_REC_2020_NCL[0] + iu * yuv2rgb_REC_2020_NCL[1] + iv * yuv2rgb_REC_2020_NCL[2];
    float g = iy * yuv2rgb_REC_2020_NCL[3] + iu * yuv2rgb_REC_2020_NCL[4] + iv * yuv2rgb_REC_2020_NCL[5];
    float b = iy * yuv2rgb_REC_2020_NCL[6] + iu * yuv2rgb_REC_2020_NCL[7] + iv * yuv2rgb_REC_2020_NCL[8];

    float lr, lg, lb;
    gamma_to_linear(r,g,b, &lr, &lg, &lb);

    r = lr * gamutMa[0] + lg * gamutMa[1] + lb * gamutMa[2];
    g = lr * gamutMa[3] + lg * gamutMa[4] + lb * gamutMa[5];
    b = lr * gamutMa[6] + lg * gamutMa[7] + lb * gamutMa[8];

    float gr, gg, gb;
    linear_to_gamma(r,g,b, &gr, &gg, &gb);
    //gr = r; gg=g; gb=b;

    iy = gr * rgb2yuv_REC_709[0] + gg * rgb2yuv_REC_709[1] + gb * rgb2yuv_REC_709[2];
    iu = gr * rgb2yuv_REC_709[3] + gg * rgb2yuv_REC_709[4] + gb * rgb2yuv_REC_709[5];
    iv = gr * rgb2yuv_REC_709[6] + gg * rgb2yuv_REC_709[7] + gb * rgb2yuv_REC_709[8];

    // float to int
    *ry = clamp(float_2int16y(iy), 16*4, 235*4);
    *ru = clamp(float_2int16(iu), 16*4, 240*4);
    *rv = clamp(float_2int16(iv), 16*4, 240*4);

    //*ry = *y;
    //*ru = *u;
    //*rv = *v;
}


__global__ void
calc_colorspace(uint8_t *data0, uint8_t *data1, uint8_t *data2, int w, int h, int stride_y, int stride_uv,
                uint8_t *dst_data0, uint8_t *dst_data1, uint8_t *dst_data2, int colorspace) {
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    int iy = i/(w/2)*2;
    int ix = (i % (w/2)) *2;
    if (ix >= w || iy >= h)
        return;

    int ofy = iy * stride_y + ix;
    int ofuv = (iy>>1) * stride_uv + ix/2;

    uint16_t * srcy = (uint16_t *)data0;
    uint16_t * srcu = (uint16_t *)data1;
    uint16_t * srcv = (uint16_t *)data2;

    uint16_t * dsty = (uint16_t *)dst_data0;
    uint16_t * dstu = (uint16_t *)dst_data1;
    uint16_t * dstv = (uint16_t *)dst_data2;

    yuv_to_rgb(&srcy[ofy], &srcu[ofuv], &srcv[ofuv], &dsty[ofy], &dstu[ofuv], &dstv[ofuv]);
    yuv_to_rgb(&srcy[ofy + 1], &srcu[ofuv], &srcv[ofuv], &dsty[ofy + 1], &dstu[ofuv], &dstv[ofuv]);
    yuv_to_rgb(&srcy[ofy + stride_y], &srcu[ofuv], &srcv[ofuv], &dsty[ofy + stride_y], &dstu[ofuv], &dstv[ofuv]);
    yuv_to_rgb(&srcy[ofy + stride_y +1], &srcu[ofuv], &srcv[ofuv], &dsty[ofy + stride_y + 1], &dstu[ofuv], &dstv[ofuv]);
}

__global__ void colorspace(float *src0, float *src1, float *src2, float *dst0, float *dst1, float *dst2, int w, int h){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>w*h-1)
        return;
    float iy = src0[i];
    float iu = src1[i];
    float iv = src2[i];
    float r = iy * yuv2rgb_REC_2020_NCL[0] + iu * yuv2rgb_REC_2020_NCL[1] + iv * yuv2rgb_REC_2020_NCL[2];
    float g = iy * yuv2rgb_REC_2020_NCL[3] + iu * yuv2rgb_REC_2020_NCL[4] + iv * yuv2rgb_REC_2020_NCL[5];
    float b = iy * yuv2rgb_REC_2020_NCL[6] + iu * yuv2rgb_REC_2020_NCL[7] + iv * yuv2rgb_REC_2020_NCL[8];

    float lr, lg, lb;
    gamma_to_linear(r,g,b, &lr, &lg, &lb);

    r = lr * gamutMa[0] + lg * gamutMa[1] + lb * gamutMa[2];
    g = lr * gamutMa[3] + lg * gamutMa[4] + lb * gamutMa[5];
    b = lr * gamutMa[6] + lg * gamutMa[7] + lb * gamutMa[8];

    float gr, gg, gb;
    linear_to_gamma(r,g,b, &gr, &gg, &gb);
    //gr = r; gg=g; gb=b;

    dst0[i] = gr * rgb2yuv_REC_709[0] + gg * rgb2yuv_REC_709[1] + gb * rgb2yuv_REC_709[2];
    dst1[i] = gr * rgb2yuv_REC_709[3] + gg * rgb2yuv_REC_709[4] + gb * rgb2yuv_REC_709[5];
    dst2[i] = gr * rgb2yuv_REC_709[6] + gg * rgb2yuv_REC_709[7] + gb * rgb2yuv_REC_709[8];

    //yuv_to_rgb(&src0[i], &src1[i], &src2[i], &dst0[i], &dst1[i], &dst2[i]);
}

__global__ void resize_line_32_y(uint8_t *src, float *dst, int width, int height) {
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>width*height-1)
        return;
    dst[i] = int16_2floaty(src[i]);
}

__global__ void resize_line_32_uv(uint8_t *src, float *dst, int wi, int hi){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>wi*hi-1)
        return;

    int h = int(i / wi);
    int v = int(i % wi);
    int w = int(wi / 2);
    if (h == 0 || h == hi-1){
        if (v % 2 == 0 || v == wi - 1)
            dst[i] = int16_2float(src[int(h/2)*w +int(v / 2)]);
        else
            dst[i] = int16_2float(src[int(h/2) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2) * w + int(v / 2) + 1]) * 0.5;
    }
    else if (h % 2 == 0){
        if (v % 2 == 0 || v == wi - 1)
            dst[i] = int16_2float(src[int(h / 2 - 1) * w + int(v / 2)]) * 0.25 + int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.75;
        else{
            float x1 = int16_2float(src[int(h / 2 - 1) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2 - 1) * w + int(v / 2) + 1]) * 0.5;
            float x2 = int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2) * w + int(v / 2) + 1]) * 0.5;
            dst[i] = x1 * 0.25 + x2 * 0.75;
        }
    }
    else{
        if (v % 2 == 0 || v == wi - 1)
            dst[i] = int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.75 + int16_2float(src[int(h / 2 + 1) * w + int(v / 2)]) * 0.25;
        else{
            float x1 = int16_2float(src[int(h / 2) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2) * w + int(v / 2) + 1]) * 0.5;
            float x2 = int16_2float(src[int(h / 2 + 1) * w + int(v / 2)]) * 0.5 + int16_2float(src[int(h / 2 + 1) * w + int(v / 2) + 1]) * 0.5;
            dst[i] = x1 * 0.75 + x2 * 0.25;
        }
    }
}

__global__ void stamp_line_32_y(float *src, uint8_t *dst, int wi, int hi){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>wi*hi-1)
        return;
    dst[i] = clamp(float_2int16y(src[i]), 16*4, 235*4);
}

__global__ void stamp_line_32_uv(float *src, uint8_t *dst, int wi, int hi){
    int i = (blockDim.x * blockIdx.x + threadIdx.x);
    if(i>wi*hi-1)
        return;
    float x1,x2,x3;
    x1=x2=x3=0;
    int h = int(i / wi);
    int v = int(i % wi);
    int w = int(wi * 2);

    int sh = (h+1)/2;
    int sv = (v+1)/2;

    if (h == hi -1){
        float x1 = src[sh * w + sv] * 0.5 + src[(sh + 1) * w + sv] * 0.375 + src[(sh + 2) * w + sv] * 0.125;
        float x2 = src[sh * w + sv + 1] * 0.5 + src[(sh + 1) * w + sv + 1] * 0.375 + src[(sh + 2) * w + sv + 1] * 0.125;
        float x3 = src[sh * w + sv + 2] * 0.5 + src[(sh + 1) * w + sv + 2] * 0.375 + src[(sh + 2) * w + sv + 2] * 0.125;
    }
    else{
        float x1 = src[sh * w + sv] * 0.125 + src[(sh + 1) * w + sv] * 0.375 + src[(sh + 2) * w + sv] * 0.375 + src[(sh + 3) * w + sv] * 0.125;
        float x2 = src[sh * w + sv + 1] * 0.125 + src[(sh + 1) * w + sv + 1] * 0.375 + src[(sh + 2) * w + sv + 1] * 0.375 + src[(sh + 3) * w + sv + 1] * 0.125;
        float x3 = src[sh * w + sv + 2] * 0.125 + src[(sh + 1) * w + sv + 2] * 0.375 + src[(sh + 2) * w + sv + 2] * 0.375 + src[(sh + 3) * w + sv + 2] * 0.125;
    }
    dst[i] = clamp(float_2int16(x1 * 0.25 + x2 * 0.5 + x3 * 0.25), 16*4, 240*4);
}

extern "C" {
int
doitgpu(uint8_t *data0, uint8_t *data1, uint8_t *data2, int *linesize, int width, int height, int format, uint8_t *out0,
        uint8_t *out1, uint8_t *out2) {
    fprintf(stderr, "=====gpu====\n");
    uint8_t *cuda_data0, *cuda_data1, *cuda_data2;
    uint8_t *dst_data0, *dst_data1, *dst_data2;
    float *dst_w0, *dst_w1, *dst_w2, *dst_prt0, *dst_prt1, *dst_prt2;
    int length0 = linesize[0] * height;
    int length1 = linesize[1] * height >> 1;
    int length2 = linesize[2] * height >> 1;
    int stride_y = linesize[0]>>1;
    int stride_uv = linesize[1]>>1;

    hipMalloc(&cuda_data0, length0);
    hipMalloc(&cuda_data1, length1);
    hipMalloc(&cuda_data2, length2);
    hipMalloc(&dst_data0, length0);
    hipMalloc(&dst_data1, length1);
    hipMalloc(&dst_data2, length2);
    hipMemcpy(cuda_data0, data0, length0, hipMemcpyHostToDevice);
    hipMemcpy(cuda_data1, data1, length1, hipMemcpyHostToDevice);
    hipMemcpy(cuda_data2, data2, length2, hipMemcpyHostToDevice);

    hipMalloc(&dst_w0, 4 * width * height);
    hipMalloc(&dst_w1, 4 * width * height);
    hipMalloc(&dst_w2, 4 * width * height);

    hipMalloc(&dst_prt0, 4 * width * height);
    hipMalloc(&dst_prt1, 4 * width * height);
    hipMalloc(&dst_prt2, 4 * width * height);

    int blocks = (width * height +128 - 1)/128;
    int threads = 128;
    resize_line_32_y<<<blocks, threads>>>(cuda_data0, dst_w0, width, height);
    resize_line_32_uv<<<blocks, threads>>>(cuda_data1, dst_w1, width, height);
    resize_line_32_uv<<<blocks, threads>>>(cuda_data2, dst_w2, width, height);
    fprintf(stderr, "--resized\n");

    colorspace<<<blocks, threads>>>(dst_w0, dst_w1, dst_w2, dst_prt0, dst_prt1, dst_prt2, width, height);
    fprintf(stderr, "--colorspace\n");

    stamp_line_32_y<<<blocks, threads>>>(dst_prt0, dst_data0, width, height);

    blocks = (width * height / 4 + 128 - 1) / 128;
    threads = 128;
    //calc_colorspace <<<blocks, threads>>>(cuda_data0, cuda_data1, cuda_data2, width, height, stride_y, stride_uv,
    //                                      dst_data0, dst_data1, dst_data2, 0);
    stamp_line_32_uv<<<blocks, threads>>>(dst_prt1, dst_data1, width/2, height/2);
    stamp_line_32_uv<<<blocks, threads>>>(dst_prt2, dst_data2, width/2, height/2);
    fprintf(stderr, "--over\n");


    hipMemcpy(out0, dst_data0, length0, hipMemcpyDeviceToHost);
    hipMemcpy(out1, dst_data1, length1, hipMemcpyDeviceToHost);
    hipMemcpy(out2, dst_data2, length2, hipMemcpyDeviceToHost);
    hipDeviceReset();

    return 0;
}

}
	.text
	.file	"colorhdr.hip"
	.globl	_Z20__device_stub__doGPUPhS_i   # -- Begin function _Z20__device_stub__doGPUPhS_i
	.type	_Z20__device_stub__doGPUPhS_i,@function
_Z20__device_stub__doGPUPhS_i:          # @_Z20__device_stub__doGPUPhS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5doGPUPhS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__doGPUPhS_i, .Lfunc_end0-_Z20__device_stub__doGPUPhS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i # -- Begin function _Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i
	.type	_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i,@function
_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i: # @_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15calc_colorspacePhS_S_iiiiS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i, .Lfunc_end1-_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__colorspacePfS_S_S_S_S_ii # -- Begin function _Z25__device_stub__colorspacePfS_S_S_S_S_ii
	.type	_Z25__device_stub__colorspacePfS_S_S_S_S_ii,@function
_Z25__device_stub__colorspacePfS_S_S_S_S_ii: # @_Z25__device_stub__colorspacePfS_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10colorspacePfS_S_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__colorspacePfS_S_S_S_S_ii, .Lfunc_end2-_Z25__device_stub__colorspacePfS_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__resize_line_32_yPhPfii # -- Begin function _Z31__device_stub__resize_line_32_yPhPfii
	.type	_Z31__device_stub__resize_line_32_yPhPfii,@function
_Z31__device_stub__resize_line_32_yPhPfii: # @_Z31__device_stub__resize_line_32_yPhPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16resize_line_32_yPhPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z31__device_stub__resize_line_32_yPhPfii, .Lfunc_end3-_Z31__device_stub__resize_line_32_yPhPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__resize_line_32_uvPhPfii # -- Begin function _Z32__device_stub__resize_line_32_uvPhPfii
	.type	_Z32__device_stub__resize_line_32_uvPhPfii,@function
_Z32__device_stub__resize_line_32_uvPhPfii: # @_Z32__device_stub__resize_line_32_uvPhPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17resize_line_32_uvPhPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z32__device_stub__resize_line_32_uvPhPfii, .Lfunc_end4-_Z32__device_stub__resize_line_32_uvPhPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__stamp_line_32_yPfPhii # -- Begin function _Z30__device_stub__stamp_line_32_yPfPhii
	.type	_Z30__device_stub__stamp_line_32_yPfPhii,@function
_Z30__device_stub__stamp_line_32_yPfPhii: # @_Z30__device_stub__stamp_line_32_yPfPhii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15stamp_line_32_yPfPhii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z30__device_stub__stamp_line_32_yPfPhii, .Lfunc_end5-_Z30__device_stub__stamp_line_32_yPfPhii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__stamp_line_32_uvPfPhii # -- Begin function _Z31__device_stub__stamp_line_32_uvPfPhii
	.type	_Z31__device_stub__stamp_line_32_uvPfPhii,@function
_Z31__device_stub__stamp_line_32_uvPfPhii: # @_Z31__device_stub__stamp_line_32_uvPfPhii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16stamp_line_32_uvPfPhii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z31__device_stub__stamp_line_32_uvPfPhii, .Lfunc_end6-_Z31__device_stub__stamp_line_32_uvPfPhii
	.cfi_endproc
                                        # -- End function
	.globl	doitgpu                         # -- Begin function doitgpu
	.type	doitgpu,@function
doitgpu:                                # @doitgpu
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
                                        # kill: def $r8d killed $r8d def $r8
	movq	%r8, 112(%rsp)                  # 8-byte Spill
	movq	%rcx, %rbx
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$13, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movslq	(%rbx), %r12
	movslq	%ebp, %r13
	imulq	%r13, %r12
	movl	4(%rbx), %r15d
	imull	%r13d, %r15d
	sarl	%r15d
	imull	8(%rbx), %r13d
	sarl	%r13d
	leaq	128(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movslq	%r15d, %rbx
	leaq	104(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movslq	%r13d, %r15
	leaq	120(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	96(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, 24(%rsp)                  # 8-byte Spill
	movq	%r12, %rdx
	movabsq	$4294967424, %r12               # imm = 0x100000080
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	104(%rsp), %rax
	movq	(%rax), %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%rbx, 8(%rsp)                   # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movq	%rbp, %r13
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, 16(%rsp)                  # 8-byte Spill
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %r14d
	movq	112(%rsp), %r15                 # 8-byte Reload
	imull	%r15d, %r14d
	leal	(,%r14,4), %eax
	movslq	%eax, %rbx
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rbx
	callq	hipMalloc
	leal	127(%r14), %eax
	leal	254(%r14), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$7, %ecx
	leaq	(%rcx,%r12), %r15
	addq	$-128, %r15
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_2
# %bb.1:
	movq	128(%rsp), %rdi
	movq	72(%rsp), %rsi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	callq	_Z31__device_stub__resize_line_32_yPhPfii
.LBB7_2:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_4
# %bb.3:
	movq	104(%rsp), %rdi
	movq	64(%rsp), %rsi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	callq	_Z32__device_stub__resize_line_32_uvPhPfii
.LBB7_4:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_6
# %bb.5:
	movq	120(%rsp), %rdi
	movq	56(%rsp), %rsi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	callq	_Z32__device_stub__resize_line_32_uvPhPfii
.LBB7_6:
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$10, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_8
# %bb.7:
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	40(%rsp), %r8
	movq	32(%rsp), %r9
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__colorspacePfS_S_S_S_S_ii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB7_8:
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
	movl	$13, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_10
# %bb.9:
	movq	48(%rsp), %rdi
	movq	96(%rsp), %rsi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	callq	_Z30__device_stub__stamp_line_32_yPfPhii
.LBB7_10:
	leal	3(%r14), %eax
	testl	%r14d, %r14d
	cmovnsl	%r14d, %eax
	sarl	$2, %eax
	leal	127(%rax), %ecx
	addl	$254, %eax
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	sarl	$7, %eax
	leaq	(%r12,%rax), %r15
	addq	$-128, %r15
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %r14
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_12
# %bb.11:
	movq	40(%rsp), %rdi
	movq	88(%rsp), %rsi
	movl	%ebx, %edx
	shrl	$31, %edx
	addl	%ebx, %edx
	sarl	%edx
	movl	%r13d, %ecx
	shrl	$31, %ecx
	addl	%r13d, %ecx
	sarl	%ecx
	callq	_Z31__device_stub__stamp_line_32_uvPfPhii
.LBB7_12:
	movq	208(%rsp), %r12
	movq	200(%rsp), %rbp
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_14
# %bb.13:
	movq	32(%rsp), %rdi
	movq	80(%rsp), %rsi
	movl	%ebx, %edx
	shrl	$31, %edx
	addl	%ebx, %edx
	sarl	%edx
	movl	%r13d, %ecx
	shrl	$31, %ecx
	addl	%r13d, %ecx
	sarl	%ecx
	callq	_Z31__device_stub__stamp_line_32_uvPfPhii
.LBB7_14:
	movq	stderr(%rip), %rcx
	movl	$.L.str.3, %edi
	movl	$7, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	96(%rsp), %rsi
	movq	%rbp, %rdi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	88(%rsp), %rsi
	movq	%r12, %rdi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rsi
	movq	216(%rsp), %rdi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	doitgpu, .Lfunc_end7-doitgpu
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5doGPUPhS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15calc_colorspacePhS_S_iiiiS_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10colorspacePfS_S_S_S_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16resize_line_32_yPhPfii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17resize_line_32_uvPhPfii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15stamp_line_32_yPfPhii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16stamp_line_32_uvPfPhii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$FCC_KR, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$FCC_KB, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$SMPTE_240M_KR, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$SMPTE_240M_KB, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC_601_KR, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC_601_KB, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC_709_KR, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC_709_KB, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC_2020_KR, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC_2020_KB, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC709_ALPHA, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$REC709_BETA, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ST2084_M1, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ST2084_M2, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ST2084_C1, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ST2084_C2, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ST2084_C3, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yuv2rgb_REC_2020_NCL, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$rgb2yuv_REC_709, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$gamutMa, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	FCC_KR,@object                  # @FCC_KR
	.local	FCC_KR
	.comm	FCC_KR,4,4
	.type	FCC_KB,@object                  # @FCC_KB
	.local	FCC_KB
	.comm	FCC_KB,4,4
	.type	SMPTE_240M_KR,@object           # @SMPTE_240M_KR
	.local	SMPTE_240M_KR
	.comm	SMPTE_240M_KR,4,4
	.type	SMPTE_240M_KB,@object           # @SMPTE_240M_KB
	.local	SMPTE_240M_KB
	.comm	SMPTE_240M_KB,4,4
	.type	REC_601_KR,@object              # @REC_601_KR
	.local	REC_601_KR
	.comm	REC_601_KR,4,4
	.type	REC_601_KB,@object              # @REC_601_KB
	.local	REC_601_KB
	.comm	REC_601_KB,4,4
	.type	REC_709_KR,@object              # @REC_709_KR
	.local	REC_709_KR
	.comm	REC_709_KR,4,4
	.type	REC_709_KB,@object              # @REC_709_KB
	.local	REC_709_KB
	.comm	REC_709_KB,4,4
	.type	REC_2020_KR,@object             # @REC_2020_KR
	.local	REC_2020_KR
	.comm	REC_2020_KR,4,4
	.type	REC_2020_KB,@object             # @REC_2020_KB
	.local	REC_2020_KB
	.comm	REC_2020_KB,4,4
	.type	REC709_ALPHA,@object            # @REC709_ALPHA
	.local	REC709_ALPHA
	.comm	REC709_ALPHA,4,4
	.type	REC709_BETA,@object             # @REC709_BETA
	.local	REC709_BETA
	.comm	REC709_BETA,4,4
	.type	ST2084_M1,@object               # @ST2084_M1
	.local	ST2084_M1
	.comm	ST2084_M1,4,4
	.type	ST2084_M2,@object               # @ST2084_M2
	.local	ST2084_M2
	.comm	ST2084_M2,4,4
	.type	ST2084_C1,@object               # @ST2084_C1
	.local	ST2084_C1
	.comm	ST2084_C1,4,4
	.type	ST2084_C2,@object               # @ST2084_C2
	.local	ST2084_C2
	.comm	ST2084_C2,4,4
	.type	ST2084_C3,@object               # @ST2084_C3
	.local	ST2084_C3
	.comm	ST2084_C3,4,4
	.type	yuv2rgb_REC_2020_NCL,@object    # @yuv2rgb_REC_2020_NCL
	.local	yuv2rgb_REC_2020_NCL
	.comm	yuv2rgb_REC_2020_NCL,36,16
	.type	rgb2yuv_REC_709,@object         # @rgb2yuv_REC_709
	.local	rgb2yuv_REC_709
	.comm	rgb2yuv_REC_709,36,16
	.type	gamutMa,@object                 # @gamutMa
	.local	gamutMa
	.comm	gamutMa,36,16
	.type	_Z5doGPUPhS_i,@object           # @_Z5doGPUPhS_i
	.section	.rodata,"a",@progbits
	.globl	_Z5doGPUPhS_i
	.p2align	3, 0x0
_Z5doGPUPhS_i:
	.quad	_Z20__device_stub__doGPUPhS_i
	.size	_Z5doGPUPhS_i, 8

	.type	_Z15calc_colorspacePhS_S_iiiiS_S_S_i,@object # @_Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.globl	_Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.p2align	3, 0x0
_Z15calc_colorspacePhS_S_iiiiS_S_S_i:
	.quad	_Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i
	.size	_Z15calc_colorspacePhS_S_iiiiS_S_S_i, 8

	.type	_Z10colorspacePfS_S_S_S_S_ii,@object # @_Z10colorspacePfS_S_S_S_S_ii
	.globl	_Z10colorspacePfS_S_S_S_S_ii
	.p2align	3, 0x0
_Z10colorspacePfS_S_S_S_S_ii:
	.quad	_Z25__device_stub__colorspacePfS_S_S_S_S_ii
	.size	_Z10colorspacePfS_S_S_S_S_ii, 8

	.type	_Z16resize_line_32_yPhPfii,@object # @_Z16resize_line_32_yPhPfii
	.globl	_Z16resize_line_32_yPhPfii
	.p2align	3, 0x0
_Z16resize_line_32_yPhPfii:
	.quad	_Z31__device_stub__resize_line_32_yPhPfii
	.size	_Z16resize_line_32_yPhPfii, 8

	.type	_Z17resize_line_32_uvPhPfii,@object # @_Z17resize_line_32_uvPhPfii
	.globl	_Z17resize_line_32_uvPhPfii
	.p2align	3, 0x0
_Z17resize_line_32_uvPhPfii:
	.quad	_Z32__device_stub__resize_line_32_uvPhPfii
	.size	_Z17resize_line_32_uvPhPfii, 8

	.type	_Z15stamp_line_32_yPfPhii,@object # @_Z15stamp_line_32_yPfPhii
	.globl	_Z15stamp_line_32_yPfPhii
	.p2align	3, 0x0
_Z15stamp_line_32_yPfPhii:
	.quad	_Z30__device_stub__stamp_line_32_yPfPhii
	.size	_Z15stamp_line_32_yPfPhii, 8

	.type	_Z16stamp_line_32_uvPfPhii,@object # @_Z16stamp_line_32_uvPfPhii
	.globl	_Z16stamp_line_32_uvPfPhii
	.p2align	3, 0x0
_Z16stamp_line_32_uvPfPhii:
	.quad	_Z31__device_stub__stamp_line_32_uvPfPhii
	.size	_Z16stamp_line_32_uvPfPhii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"=====gpu====\n"
	.size	.L.str, 14

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"--resized\n"
	.size	.L.str.1, 11

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"--colorspace\n"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"--over\n"
	.size	.L.str.3, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5doGPUPhS_i"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15calc_colorspacePhS_S_iiiiS_S_S_i"
	.size	.L__unnamed_2, 37

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10colorspacePfS_S_S_S_S_ii"
	.size	.L__unnamed_3, 29

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z16resize_line_32_yPhPfii"
	.size	.L__unnamed_4, 27

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z17resize_line_32_uvPhPfii"
	.size	.L__unnamed_5, 28

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z15stamp_line_32_yPfPhii"
	.size	.L__unnamed_6, 26

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z16stamp_line_32_uvPfPhii"
	.size	.L__unnamed_7, 27

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"FCC_KR"
	.size	.L__unnamed_8, 7

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"FCC_KB"
	.size	.L__unnamed_9, 7

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"SMPTE_240M_KR"
	.size	.L__unnamed_10, 14

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"SMPTE_240M_KB"
	.size	.L__unnamed_11, 14

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"REC_601_KR"
	.size	.L__unnamed_12, 11

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"REC_601_KB"
	.size	.L__unnamed_13, 11

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"REC_709_KR"
	.size	.L__unnamed_14, 11

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"REC_709_KB"
	.size	.L__unnamed_15, 11

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"REC_2020_KR"
	.size	.L__unnamed_16, 12

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"REC_2020_KB"
	.size	.L__unnamed_17, 12

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"REC709_ALPHA"
	.size	.L__unnamed_18, 13

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"REC709_BETA"
	.size	.L__unnamed_19, 12

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"ST2084_M1"
	.size	.L__unnamed_20, 10

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"ST2084_M2"
	.size	.L__unnamed_21, 10

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"ST2084_C1"
	.size	.L__unnamed_22, 10

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"ST2084_C2"
	.size	.L__unnamed_23, 10

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"ST2084_C3"
	.size	.L__unnamed_24, 10

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"yuv2rgb_REC_2020_NCL"
	.size	.L__unnamed_25, 21

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"rgb2yuv_REC_709"
	.size	.L__unnamed_26, 16

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"gamutMa"
	.size	.L__unnamed_27, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__doGPUPhS_i
	.addrsig_sym _Z30__device_stub__calc_colorspacePhS_S_iiiiS_S_S_i
	.addrsig_sym _Z25__device_stub__colorspacePfS_S_S_S_S_ii
	.addrsig_sym _Z31__device_stub__resize_line_32_yPhPfii
	.addrsig_sym _Z32__device_stub__resize_line_32_uvPhPfii
	.addrsig_sym _Z30__device_stub__stamp_line_32_yPfPhii
	.addrsig_sym _Z31__device_stub__stamp_line_32_uvPfPhii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym FCC_KR
	.addrsig_sym FCC_KB
	.addrsig_sym SMPTE_240M_KR
	.addrsig_sym SMPTE_240M_KB
	.addrsig_sym REC_601_KR
	.addrsig_sym REC_601_KB
	.addrsig_sym REC_709_KR
	.addrsig_sym REC_709_KB
	.addrsig_sym REC_2020_KR
	.addrsig_sym REC_2020_KB
	.addrsig_sym REC709_ALPHA
	.addrsig_sym REC709_BETA
	.addrsig_sym ST2084_M1
	.addrsig_sym ST2084_M2
	.addrsig_sym ST2084_C1
	.addrsig_sym ST2084_C2
	.addrsig_sym ST2084_C3
	.addrsig_sym yuv2rgb_REC_2020_NCL
	.addrsig_sym rgb2yuv_REC_709
	.addrsig_sym gamutMa
	.addrsig_sym _Z5doGPUPhS_i
	.addrsig_sym _Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.addrsig_sym _Z10colorspacePfS_S_S_S_S_ii
	.addrsig_sym _Z16resize_line_32_yPhPfii
	.addrsig_sym _Z17resize_line_32_uvPhPfii
	.addrsig_sym _Z15stamp_line_32_yPfPhii
	.addrsig_sym _Z16stamp_line_32_uvPfPhii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5doGPUPhS_i           ; -- Begin function _Z5doGPUPhS_i
	.globl	_Z5doGPUPhS_i
	.p2align	8
	.type	_Z5doGPUPhS_i,@function
_Z5doGPUPhS_i:                          ; @_Z5doGPUPhS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v4, 31, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5doGPUPhS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5doGPUPhS_i, .Lfunc_end0-_Z5doGPUPhS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 136
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function _Z12st_2084_eotff
	.type	_Z12st_2084_eotff,@function
_Z12st_2084_eotff:                      ; @_Z12st_2084_eotff
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_f32_e32 0, v0
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mov_b32_e32 v1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ST2084_M2@rel32@lo+4
	s_addc_u32 s1, s1, ST2084_M2@rel32@hi+12
	global_load_b32 v2, v1, s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ST2084_C1@rel32@lo+4
	s_addc_u32 s1, s1, ST2084_C1@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, ST2084_C2@rel32@lo+4
	s_addc_u32 s5, s5, ST2084_C2@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, ST2084_C3@rel32@lo+4
	s_addc_u32 s7, s7, ST2084_C3@rel32@hi+12
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, ST2084_M1@rel32@lo+4
	s_addc_u32 s9, s9, ST2084_M1@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v6, null, v2, v2, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v2, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	v_fmac_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v7
	s_clause 0x3
	global_load_b32 v3, v1, s[0:1]
	global_load_b32 v4, v1, s[4:5]
	global_load_b32 v5, v1, s[6:7]
	global_load_b32 v1, v1, s[8:9]
	s_mov_b32 s4, 0x3e76c4e1
	v_fma_f32 v10, -v6, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v7
	v_fma_f32 v6, -v6, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v7, v8
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v0
	v_div_fixup_f32 v2, v6, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 1.0, v2, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_cmp_neq_f32_e64 s5, v2, |v2|
	v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v6, |v0|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v6
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v6, v6, v7
	v_add_f32_e32 v9, -1.0, v6
	v_add_f32_e32 v7, 1.0, v6
	v_cmp_lt_f32_e64 s6, |v0|, 1.0
	v_cmp_eq_f32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v8, v7
	s_xor_b32 s5, s5, s6
	v_add_f32_e32 v11, -1.0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, v9, v8
	v_mul_f32_e32 v12, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v10, v7, -v12
	v_fmac_f32_e32 v7, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v12, v7
	v_sub_f32_e32 v11, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v9, v11 :: v_dual_sub_f32 v12, v6, v12
	v_dual_sub_f32 v6, v9, v6 :: v_dual_sub_f32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v6
	v_add_f32_e32 v6, v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v8, v6
	v_add_f32_e32 v7, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v7, v10
	v_dual_mul_f32 v9, v7, v7 :: v_dual_sub_f32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v7, v7, -v9
	v_add_f32_e32 v10, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v7, v10
	v_add_f32_e32 v10, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v11, s4, v10, 0x3e91f4c4
	v_sub_f32_e32 v9, v10, v9
	v_dual_fmaak_f32 v11, v10, v11, 0x3ecccdef :: v_dual_sub_f32 v8, v8, v9
	v_mul_f32_e32 v14, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, v10, v11
	v_fma_f32 v15, v10, v7, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v10, v11, -v12
	v_fmac_f32_e32 v9, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v12, v9
	v_dual_add_f32 v13, 0x3f2aaaaa, v11 :: v_dual_sub_f32 v12, v11, v12
	v_fmac_f32_e32 v15, v10, v6
	v_ldexp_f32 v6, v6, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v9, v9, v12 :: v_dual_add_f32 v12, 0xbf2aaaaa, v13
	v_fmac_f32_e32 v15, v8, v7
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v9, 0x31739010, v9
	v_sub_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v9, v11
	v_add_f32_e32 v10, v14, v15
	v_add_f32_e32 v8, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v13, v8
	v_sub_f32_e32 v13, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v9, v11
	v_dual_sub_f32 v13, v15, v13 :: v_dual_mul_f32 v12, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v10, v8, -v12
	v_fmac_f32_e32 v11, v10, v9
	v_frexp_exp_i32_f32_e32 v9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v13, v8
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v8, v8
	v_add_f32_e32 v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v9, v12
	v_sub_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v13, 0x3f317218, v8 :: v_dual_add_f32 v6, v6, v11
	v_fma_f32 v12, 0x3f317218, v8, -v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0xb102e308, v8
	v_add_f32_e32 v10, v7, v9
	v_sub_f32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v9, v7
	v_add_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v6
	v_dual_sub_f32 v10, v8, v10 :: v_dual_add_f32 v7, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v6, v10 :: v_dual_add_f32 v9, v7, v8
	v_sub_f32_e32 v13, v7, v13
	v_dual_sub_f32 v12, v12, v13 :: v_dual_sub_f32 v11, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v12, v6
	v_sub_f32_e32 v8, v8, v11
	v_sub_f32_e32 v14, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v14
	v_dual_add_f32 v7, v8, v7 :: v_dual_sub_f32 v8, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v10, v7
	v_sub_f32_e32 v10, v10, v8
	v_sub_f32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v12, v10 :: v_dual_add_f32 v11, v9, v7
	v_dual_add_f32 v6, v6, v8 :: v_dual_sub_f32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v9
	v_add_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v11, v6
	v_sub_f32_e32 v8, v7, v11
	v_mul_f32_e32 v9, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_fma_f32 v7, v2, v7, -v9
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v2, v6
	v_add_f32_e32 v6, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, v6, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8
	v_cndmask_b32_e64 v10, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v8, v10
	v_trunc_f32_e32 v8, v2
	v_mul_f32_e32 v12, 0x3fb8aa3b, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v13, 0x3fb8aa3b, v11, -v12
	v_rndne_f32_e32 v14, v12
	v_dual_sub_f32 v12, v12, v14 :: v_dual_fmac_f32 v13, 0x32a5705f, v11
	v_sub_f32_e32 v6, v6, v9
	v_cvt_i32_f32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v7, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
	v_add_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v10, v6
	v_exp_f32_e32 v12, v12
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v12, v9
	v_mul_f32_e32 v9, 0.5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
	v_trunc_f32_e32 v12, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v8, v2
	v_cmp_neq_f32_e64 s0, v12, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v7, v6, v7
	v_cmp_eq_f32_e64 s1, 0x7f800000, v7
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 1.0, v0, s0
	v_cndmask_b32_e64 v10, 0, v0, s0
	v_cndmask_b32_e64 v6, v6, v7, s1
	v_cmp_gt_f32_e64 s1, 0, v2
	v_cndmask_b32_e64 v7, |v2|, 0, s5
	v_cmp_class_f32_e64 s0, v0, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v6, 0x7fffffff, v6, v8
	s_xor_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 0x7f800000, 0, s1
	v_cmp_eq_f32_e64 s1, |v0|, 1.0
	v_cndmask_b32_e32 v9, 0x7fc00000, v6, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v8, 0x7fffffff, v8, v10
	v_cndmask_b32_e64 v7, v7, |v0|, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x204
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_or_b32 vcc_lo, s2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v2
	v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v2, v0, v3
	s_waitcnt vmcnt(1)
	v_fma_f32 v0, -v5, v0, v4
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v1, v1, 1.0
	v_max_f32_e32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_f32_e32 v0, 0x800000, v0
	v_rcp_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v0, v0, v2
	v_div_scale_f32 v9, vcc_lo, v2, v0, v2
	v_rcp_f32_e32 v5, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v6
	v_fma_f32 v7, -v3, v5, 1.0
	v_fmac_f32_e32 v5, v7, v5
	v_div_scale_f32 v7, s0, 1.0, v1, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, v9, v5
	v_mul_f32_e32 v10, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, -v3, v8, v9
	v_fma_f32 v12, -v4, v10, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v11, v5
	v_fmac_f32_e32 v10, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v8, v9
	v_fma_f32 v4, -v4, v10, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v5, v8
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v4, v4, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v0, v3, v0, v2
	v_div_fixup_f32 v1, v4, v1, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v0
	v_cndmask_b32_e32 v1, 1.0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
	v_frexp_mant_f32_e64 v2, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	v_ldexp_f32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, 1.0, v2
	v_add_f32_e32 v5, -1.0, v2
	v_rcp_f32_e32 v4, v3
	v_add_f32_e32 v7, -1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, v5, v4
	v_mul_f32_e32 v8, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, v6, v3, -v8
	v_fmac_f32_e32 v3, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v8, v3
	v_dual_sub_f32 v7, v5, v2 :: v_dual_sub_f32 v8, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v7
	v_dual_sub_f32 v3, v8, v3 :: v_dual_sub_f32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v2
	v_add_f32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v4, v2
	v_add_f32_e32 v3, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v3, v6
	v_dual_mul_f32 v5, v3, v3 :: v_dual_sub_f32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v3, v3, -v5
	v_add_f32_e32 v6, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v3, v6
	v_add_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v7, s4, v6, 0x3e91f4c4
	v_dual_sub_f32 v5, v6, v5 :: v_dual_mul_f32 v10, v3, v6
	v_cmp_neq_f32_e64 s4, v1, |v1|
	v_fmaak_f32 v7, v6, v7, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v11, v6, v3, -v10
	v_sub_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, v6, v7
	v_fmac_f32_e32 v11, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v6, v7, -v8
	v_fmac_f32_e32 v11, v4, v3
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, v4, v7
	v_cmp_lt_f32_e64 s5, |v0|, 1.0
	v_add_f32_e32 v6, v10, v11
	v_cmp_eq_f32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v7, v8, v5
	s_xor_b32 s4, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v7, v8 :: v_dual_add_f32 v9, 0x3f2aaaaa, v7
	v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, 0xbf2aaaaa, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, 0x31739010, v5
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v7
	v_add_f32_e32 v4, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v9, v4
	v_mul_f32_e32 v8, v6, v4
	v_sub_f32_e32 v9, v6, v10
	v_add_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v6, v4, -v8
	v_sub_f32_e32 v9, v11, v9
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v6, v5
	v_frexp_exp_i32_f32_e32 v5, v0
	v_fmac_f32_e32 v7, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	v_add_f32_e32 v5, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v4, v4
	v_add_f32_e32 v6, v3, v5
	v_sub_f32_e32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v9, 0x3f317218, v4
	v_sub_f32_e32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v7, v8
	v_fma_f32 v8, 0x3f317218, v4, -v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v5, v3
	v_add_f32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0xb102e308, v4
	v_dual_add_f32 v2, v2, v3 :: v_dual_add_f32 v3, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, v6, v2 :: v_dual_sub_f32 v9, v3, v9
	v_dual_add_f32 v5, v3, v4 :: v_dual_sub_f32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v7, v5, v3
	v_sub_f32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v5, v7
	v_sub_f32_e32 v4, v4, v7
	v_add_f32_e32 v6, v8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v10
	v_dual_add_f32 v3, v4, v3 :: v_dual_sub_f32 v4, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v6, v3
	v_sub_f32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v2, v2, v4 :: v_dual_add_f32 v7, v5, v3
	v_dual_sub_f32 v4, v8, v6 :: v_dual_sub_f32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v2, v4 :: v_dual_sub_f32 v3, v3, v5
	v_add_f32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v7, v2
	v_sub_f32_e32 v4, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v5, v1, v3 :: v_dual_sub_f32 v2, v2, v4
	v_fma_f32 v3, v1, v3, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v1, v2
	v_add_f32_e32 v2, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v2, v5, vcc_lo
	v_sub_f32_e32 v2, v2, v5
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v3, v2
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_sub_f32_e32 v7, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_trunc_f32_e32 v4, v1
	v_mul_f32_e32 v8, 0x3fb8aa3b, v7
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v6, v2
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v10
	v_cvt_i32_f32_e32 v5, v10
	v_add_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v3, v8, v5
	v_mul_f32_e32 v5, 0.5, v1
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v8, v5
	v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v8, v5
	v_fma_f32 v2, v3, v2, v3
	v_cmp_eq_f32_e64 s1, 0x7f800000, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v4, 1.0, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, v3, s1
	v_cmp_gt_f32_e64 s1, 0, v1
	v_cndmask_b32_e64 v3, |v1|, 0, s4
	v_bfi_b32 v2, 0x7fffffff, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s1, s1, s2
	v_cndmask_b32_e64 v5, 0x7f800000, 0, s1
	v_cmp_eq_f32_e64 s1, |v0|, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0x7fc00000, v2, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v3, v3, |v0|, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cndmask_b32_e64 v4, 0, v0, s0
	v_cmp_class_f32_e64 vcc_lo, v1, 0x204
	v_cmp_class_f32_e64 s0, v0, 0x204
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v3, 0x7fffffff, v5, v4
	s_or_b32 vcc_lo, s2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v1
	v_cndmask_b32_e32 v1, 0x7fc00000, v2, vcc_lo
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v0, v1
	s_setpc_b64 s[30:31]
.Lfunc_end1:
	.size	_Z12st_2084_eotff, .Lfunc_end1-_Z12st_2084_eotff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2784
; NumSgprs: 34
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z12rec_709_oetff
	.type	_Z12rec_709_oetff,@function
_Z12rec_709_oetff:                      ; @_Z12rec_709_oetff
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f32_e32 0, v0
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_frexp_mant_f32_e64 v1, |v0|
	s_mov_b32 s0, 0x3e76c4e1
	v_cmp_eq_f32_e64 s1, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_ldexp_f32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, -1.0, v1
	v_add_f32_e32 v2, 1.0, v1
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, v4, v3 :: v_dual_add_f32 v6, -1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v2, v5
	v_sub_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v5, v2, -v7
	v_fmac_f32_e32 v2, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v7, v2
	v_dual_sub_f32 v6, v4, v1 :: v_dual_sub_f32 v7, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v7, v2
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v4, v1
	v_add_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v6, v1
	v_mul_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v5, v1
	v_mul_f32_e32 v4, v2, v2
	v_sub_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v1, v3
	v_fma_f32 v3, v2, v2, -v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v1, v1
	v_fmac_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v4, v3
	v_fmaak_f32 v6, s0, v5, 0x3e91f4c4
	v_sub_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	v_mul_f32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v5, v6, -v7
	v_dual_fmac_f32 v4, v3, v6 :: v_dual_mul_f32 v9, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v7, v4
	v_fma_f32 v10, v5, v2, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v7, v6, v7 :: v_dual_fmac_f32 v10, v5, v1
	v_add_f32_e32 v8, 0x3f2aaaaa, v6
	v_ldexp_f32 v1, v1, 1
	v_sub_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v3, v2
	v_ldexp_f32 v2, v2, 1
	v_add_f32_e32 v4, 0x31739010, v4
	v_add_f32_e32 v7, 0xbf2aaaaa, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v7
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v4
	v_dual_add_f32 v5, v9, v10 :: v_dual_sub_f32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v8, v5, v9
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v5, v3, -v7
	v_sub_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, v0
	v_fmac_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_add_f32_e32 v4, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_sub_f32_e32 v7, v4, v7
	v_add_f32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v7
	v_dual_mul_f32 v8, 0x3f317218, v3 :: v_dual_add_f32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, 0x3f317218, v3, -v8
	v_dual_fmamk_f32 v3, v3, 0xb102e308, v7 :: v_dual_sub_f32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v4, v2
	v_dual_add_f32 v1, v1, v2 :: v_dual_add_f32 v2, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v5, v1
	v_sub_f32_e32 v8, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v8
	v_add_f32_e32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v6, v2
	v_sub_f32_e32 v5, v4, v5
	v_sub_f32_e32 v9, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v4, v4, v7
	v_sub_f32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v3, v1 :: v_dual_add_f32 v2, v4, v2
	v_sub_f32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v5, v2
	v_sub_f32_e32 v5, v5, v4
	v_sub_f32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v3, v3, v5
	v_add_f32_e32 v7, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v7, v6
	v_cndmask_b32_e64 v3, 0x3ed55555, 1.0, vcc_lo
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v2, v7 :: v_dual_mul_f32 v5, v3, v2
	v_sub_f32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v3, v2, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fmac_f32_e32 v2, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v5, v2
	v_cndmask_b32_e32 v4, v1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_sub_f32_e32 v7, v4, v6
	v_trunc_f32_e32 v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v8, 0x3fb8aa3b, v7 :: v_dual_sub_f32 v1, v1, v5
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v2, v1
	v_dual_fmamk_f32 v9, v7, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10
	v_cvt_i32_f32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v8, v9
	v_exp_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v8, v5
	v_mul_f32_e32 v5, 0.5, v3
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v8, v5
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	v_add_f32_e32 v1, v6, v1
	v_cmp_neq_f32_e64 s0, v8, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	v_cndmask_b32_e64 v3, 0x7f800000, 0, s1
	v_fma_f32 v1, v2, v1, v2
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cmp_eq_f32_e64 s0, 0x7f800000, v2
	v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s0
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_cmp_class_f32_e64 s0, v0, 0x204
	v_bfi_b32 v1, 0x7fffffff, v1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v3, v2
	s_or_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v0, v1
	s_setpc_b64 s[30:31]
.Lfunc_end2:
	.size	_Z12rec_709_oetff, .Lfunc_end2-_Z12rec_709_oetff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 1056
; NumSgprs: 34
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z15calc_colorspacePhS_S_iiiiS_S_S_i ; -- Begin function _Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.globl	_Z15calc_colorspacePhS_S_iiiiS_S_S_i
	.p2align	8
	.type	_Z15calc_colorspacePhS_S_iiiiS_S_S_i,@function
_Z15calc_colorspacePhS_S_iiiiS_S_S_i:   ; @_Z15calc_colorspacePhS_S_iiiiS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b128 s[44:47], s[0:1], 0x18
	s_load_b32 s2, s[0:1], 0x54
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s44, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s3, s44, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s4, s3, 1
	s_ashr_i32 s3, s3, 31
	s_add_i32 s5, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s3
	v_cvt_f32_u32_e32 v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s5
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	v_lshlrev_b32_e32 v3, 1, v2
	v_mul_lo_u32 v0, v2, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s2, s45, v3
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 1, v0
	v_cmp_gt_i32_e32 vcc_lo, s44, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mad_u64_u32 v[4:5], null, v2, s47, v[0:1]
	v_mad_u64_u32 v[6:7], null, v3, s46, v[1:2]
	s_mov_b32 s10, 0xa003a73b
	s_mov_b32 s28, 0xa06c1b5a
	s_mov_b32 s11, 0xbfe24924
	s_mov_b32 s29, 0x3f524924
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s44, 0x9ffcfefc
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s48, 0x9edf1f7e
	s_mov_b32 s45, 0xbfb2b404
	v_lshlrev_b64 v[1:2], 1, v[4:5]
	s_mov_b32 s49, 0x3f52b404
	v_lshlrev_b64 v[3:4], 1, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v23, vcc_lo, s7, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v27, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v4, vcc_lo
	global_load_u16 v0, v[22:23], off
	global_load_u16 v7, v[27:28], off
	v_add_co_u32 v24, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v2, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yuv2rgb_REC_2020_NCL@rel32@lo+4
	s_addc_u32 s3, s3, yuv2rgb_REC_2020_NCL@rel32@hi+12
	s_getpc_b64 s[34:35]
	s_add_u32 s34, s34, _Z12st_2084_eotff@rel32@lo+4
	s_addc_u32 s35, s35, _Z12st_2084_eotff@rel32@hi+12
	global_load_u16 v9, v[24:25], off
	s_load_b128 s[4:7], s[0:1], 0x28
	s_load_b256 s[12:19], s[2:3], 0x0
	s_load_b64 s[0:1], s[0:1], 0x38
	s_load_b32 s33, s[2:3], 0x20
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v29, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v20, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v21, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[5:6], v0
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[7:8], v7
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[9:10], v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[5:6], v[5:6], s[28:29], s[10:11]
	v_fma_f64 v[7:8], v[7:8], s[48:49], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[9:10], s[28:29], s[10:11]
	v_cvt_f32_f64_e32 v5, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v6, v[7:8]
	v_cvt_f32_f64_e32 v7, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, s19, v5
	v_dual_mul_f32 v0, s13, v5 :: v_dual_fmac_f32 v17, s18, v6
	v_mul_f32_e32 v16, s16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v0, s12, v6 :: v_dual_fmac_f32 v17, s33, v7
	v_fmac_f32_e32 v16, s15, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, s14, v7
	v_fmac_f32_e32 v16, s17, v7
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, 0x42c80000, v0
	v_mov_b32_e32 v0, v16
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v16, 0x42c80000, v0
	v_mov_b32_e32 v0, v17
	s_swappc_b64 s[30:31], s[34:35]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, gamutMa@rel32@lo+4
	s_addc_u32 s1, s1, gamutMa@rel32@hi+12
	s_getpc_b64 s[50:51]
	s_add_u32 s50, s50, _Z12rec_709_oetff@rel32@lo+4
	s_addc_u32 s51, s51, _Z12rec_709_oetff@rel32@hi+12
	s_clause 0x1
	s_load_b256 s[20:27], s[0:1], 0x0
	s_load_b32 s52, s[0:1], 0x20
	v_mul_f32_e32 v0, 0x42c80000, v0
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v12, s27, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v1, s21, v16 :: v_dual_fmac_f32 v12, s26, v26
	v_fmac_f32_e32 v1, s20, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s22, v0
	v_mul_f32_e32 v11, s24, v16
	v_dual_fmac_f32 v11, s23, v26 :: v_dual_fmac_f32 v12, s52, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, s25, v0 :: v_dual_mov_b32 v0, v1
	s_swappc_b64 s[30:31], s[50:51]
	v_dual_mov_b32 v13, v0 :: v_dual_mov_b32 v0, v11
	s_swappc_b64 s[30:31], s[50:51]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v0, v12
	s_swappc_b64 s[30:31], s[50:51]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, rgb2yuv_REC_709@rel32@lo+4
	s_addc_u32 s1, s1, rgb2yuv_REC_709@rel32@hi+12
	v_bfrev_b32_e32 v26, 34
	s_clause 0x1
	s_load_b256 s[36:43], s[0:1], 0x0
	s_load_b32 s53, s[0:1], 0x20
	s_mov_b32 s54, 0x445b0000
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v2, s40, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, s37, v11 :: v_dual_fmac_f32 v2, s39, v13
	v_mul_f32_e32 v3, s43, v11
	v_dual_fmac_f32 v1, s36, v13 :: v_dual_fmac_f32 v2, s41, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, s42, v13
	v_fmac_f32_e32 v3, s53, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s38, v0
	v_fmaak_f32 v0, s54, v1, 0x42800000
	v_fmamk_f32 v1, v2, 0x445b0000, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmamk_f32 v2, v3, 0x445b0000, v26
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	v_dual_min_f32 v0, 0x447fc000, v0 :: v_dual_cndmask_b32 v1, 0, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v0, v0
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_min_f32 v1, 0x447fc000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_med3_u16 v0, v0, 64, 0x3ac
	v_min_f32_e32 v2, 0x447fc000, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_med3_u16 v1, v1, 64, 0x3c0
	v_med3_u16 v2, v2, 64, 0x3c0
	global_store_b16 v[29:30], v0, off
	global_store_b16 v[18:19], v1, off
	global_store_b16 v[20:21], v2, off
	global_load_u16 v0, v[22:23], off
	global_load_u16 v2, v[27:28], off offset:2
	global_load_u16 v4, v[24:25], off
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[0:1], v0
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[2:3], v2
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[28:29], s[10:11]
	v_fma_f64 v[2:3], v[2:3], s[48:49], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[4:5], s[28:29], s[10:11]
	v_cvt_f32_f64_e32 v1, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v2, v[2:3]
	v_cvt_f32_f64_e32 v3, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, s19, v1
	v_dual_mul_f32 v0, s13, v1 :: v_dual_fmac_f32 v17, s18, v2
	v_mul_f32_e32 v16, s16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v0, s12, v2 :: v_dual_fmac_f32 v17, s33, v3
	v_fmac_f32_e32 v16, s15, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, s14, v3
	v_fmac_f32_e32 v16, s17, v3
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v31, 0x42c80000, v0 :: v_dual_mov_b32 v0, v16
	s_swappc_b64 s[30:31], s[34:35]
	v_mul_f32_e32 v16, 0x42c80000, v0
	v_mov_b32_e32 v0, v17
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, s27, v16
	v_mul_f32_e32 v1, s21, v16
	v_mul_f32_e32 v0, 0x42c80000, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, s26, v31
	v_fmac_f32_e32 v1, s20, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s22, v0
	v_mul_f32_e32 v11, s24, v16
	v_dual_fmac_f32 v11, s23, v31 :: v_dual_fmac_f32 v12, s52, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, s25, v0 :: v_dual_mov_b32 v0, v1
	s_swappc_b64 s[30:31], s[50:51]
	v_dual_mov_b32 v13, v0 :: v_dual_mov_b32 v0, v11
	s_swappc_b64 s[30:31], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v0, v12
	s_swappc_b64 s[30:31], s[50:51]
	v_mul_f32_e32 v2, s40, v11
	v_mul_f32_e32 v1, s37, v11
	s_ashr_i32 s47, s46, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[0:1], s[46:47], 1
	v_dual_fmac_f32 v2, s39, v13 :: v_dual_mul_f32 v3, s43, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v1, s36, v13 :: v_dual_fmac_f32 v2, s41, v0
	v_fmac_f32_e32 v3, s42, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v3, s53, v0
	v_fmac_f32_e32 v1, s38, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v0, s54, v1, 0x42800000
	v_fmamk_f32 v1, v2, 0x445b0000, v26
	v_fmamk_f32 v2, v3, 0x445b0000, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_min_f32 v0, 0x447fc000, v0 :: v_dual_cndmask_b32 v1, 0, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0, v2
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_min_f32 v1, 0x447fc000, v1
	v_add_co_u32 v27, vcc_lo, v27, s0
	v_med3_u16 v0, v0, 64, 0x3ac
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min_f32_e32 v2, 0x447fc000, v2
	v_cvt_u32_f32_e32 v1, v1
	v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v2, v2
	v_med3_u16 v1, v1, 64, 0x3c0
	s_delay_alu instid0(VALU_DEP_2)
	v_med3_u16 v2, v2, 64, 0x3c0
	global_store_b16 v[29:30], v0, off offset:2
	global_store_b16 v[18:19], v1, off
	global_store_b16 v[20:21], v2, off
	global_load_u16 v0, v[22:23], off
	global_load_u16 v2, v[27:28], off
	global_load_u16 v4, v[24:25], off
	v_add_co_u32 v29, vcc_lo, v29, s0
	v_add_co_ci_u32_e32 v30, vcc_lo, s1, v30, vcc_lo
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[0:1], v0
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[2:3], v2
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[28:29], s[10:11]
	v_fma_f64 v[2:3], v[2:3], s[48:49], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[4:5], s[28:29], s[10:11]
	v_cvt_f32_f64_e32 v1, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v2, v[2:3]
	v_cvt_f32_f64_e32 v3, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, s19, v1
	v_dual_mul_f32 v0, s13, v1 :: v_dual_fmac_f32 v17, s18, v2
	v_mul_f32_e32 v16, s16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v0, s12, v2 :: v_dual_fmac_f32 v17, s33, v3
	v_fmac_f32_e32 v16, s15, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, s14, v3
	v_fmac_f32_e32 v16, s17, v3
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v31, 0x42c80000, v0 :: v_dual_mov_b32 v0, v16
	s_swappc_b64 s[30:31], s[34:35]
	v_mul_f32_e32 v16, 0x42c80000, v0
	v_mov_b32_e32 v0, v17
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, s27, v16
	v_mul_f32_e32 v1, s21, v16
	v_mul_f32_e32 v0, 0x42c80000, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, s26, v31
	v_fmac_f32_e32 v1, s20, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s22, v0
	v_mul_f32_e32 v11, s24, v16
	v_dual_fmac_f32 v11, s23, v31 :: v_dual_fmac_f32 v12, s52, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, s25, v0 :: v_dual_mov_b32 v0, v1
	s_swappc_b64 s[30:31], s[50:51]
	v_dual_mov_b32 v13, v0 :: v_dual_mov_b32 v0, v11
	s_swappc_b64 s[30:31], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v0, v12
	s_swappc_b64 s[30:31], s[50:51]
	v_mul_f32_e32 v2, s40, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, s37, v11 :: v_dual_fmac_f32 v2, s39, v13
	v_mul_f32_e32 v3, s43, v11
	v_dual_fmac_f32 v1, s36, v13 :: v_dual_fmac_f32 v2, s41, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, s42, v13
	v_fmac_f32_e32 v3, s53, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s38, v0
	v_fmaak_f32 v0, s54, v1, 0x42800000
	v_fmamk_f32 v1, v2, 0x445b0000, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmamk_f32 v2, v3, 0x445b0000, v26
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	v_dual_min_f32 v0, 0x447fc000, v0 :: v_dual_cndmask_b32 v1, 0, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v0, v0
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_min_f32 v1, 0x447fc000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_med3_u16 v0, v0, 64, 0x3ac
	v_min_f32_e32 v2, 0x447fc000, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_med3_u16 v1, v1, 64, 0x3c0
	v_med3_u16 v2, v2, 64, 0x3c0
	global_store_b16 v[29:30], v0, off
	global_store_b16 v[18:19], v1, off
	global_store_b16 v[20:21], v2, off
	global_load_u16 v0, v[22:23], off
	global_load_u16 v2, v[27:28], off offset:2
	global_load_u16 v4, v[24:25], off
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[0:1], v0
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[2:3], v2
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[28:29], s[10:11]
	v_fma_f64 v[2:3], v[2:3], s[48:49], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[4:5], s[28:29], s[10:11]
	v_cvt_f32_f64_e32 v1, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v2, v[2:3]
	v_cvt_f32_f64_e32 v3, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, s19, v1
	v_dual_mul_f32 v0, s13, v1 :: v_dual_fmac_f32 v17, s18, v2
	v_mul_f32_e32 v16, s16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v0, s12, v2 :: v_dual_fmac_f32 v17, s33, v3
	v_fmac_f32_e32 v16, s15, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, s14, v3
	v_fmac_f32_e32 v16, s17, v3
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, 0x42c80000, v0
	v_mov_b32_e32 v0, v16
	s_swappc_b64 s[30:31], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x42c80000, v0
	v_mov_b32_e32 v0, v17
	s_swappc_b64 s[30:31], s[34:35]
	v_mul_f32_e32 v12, s27, v16
	v_mul_f32_e32 v1, s21, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v0, 0x42c80000, v0
	v_fmac_f32_e32 v12, s26, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, s20, v22
	v_fmac_f32_e32 v1, s22, v0
	v_mul_f32_e32 v11, s24, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, s23, v22 :: v_dual_fmac_f32 v12, s52, v0
	v_dual_fmac_f32 v11, s25, v0 :: v_dual_mov_b32 v0, v1
	s_swappc_b64 s[30:31], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v13, v0 :: v_dual_mov_b32 v0, v11
	s_swappc_b64 s[30:31], s[50:51]
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v0, v12
	s_swappc_b64 s[30:31], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, s40, v11
	v_dual_mul_f32 v1, s37, v11 :: v_dual_fmac_f32 v2, s39, v13
	v_mul_f32_e32 v3, s43, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v1, s36, v13 :: v_dual_fmac_f32 v2, s41, v0
	v_fmac_f32_e32 v3, s42, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v3, s53, v0
	v_fmac_f32_e32 v1, s38, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v0, s54, v1, 0x42800000
	v_fmamk_f32 v1, v2, 0x445b0000, v26
	v_fmac_f32_e32 v26, 0x445b0000, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_min_f32 v0, 0x447fc000, v0 :: v_dual_cndmask_b32 v1, 0, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0, v26
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v2, 0, v26 :: v_dual_min_f32 v1, 0x447fc000, v1
	v_med3_u16 v0, v0, 64, 0x3ac
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_f32_e32 v2, 0x447fc000, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v2, v2
	v_med3_u16 v1, v1, 64, 0x3c0
	s_delay_alu instid0(VALU_DEP_2)
	v_med3_u16 v2, v2, 64, 0x3c0
	global_store_b16 v[29:30], v0, off offset:2
	global_store_b16 v[18:19], v1, off
	global_store_b16 v[20:21], v2, off
.LBB3_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15calc_colorspacePhS_S_iiiiS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 55
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15calc_colorspacePhS_S_iiiiS_S_S_i, .Lfunc_end3-_Z15calc_colorspacePhS_S_iiiiS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2732
; NumSgprs: 57
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 57
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10colorspacePfS_S_S_S_S_ii ; -- Begin function _Z10colorspacePfS_S_S_S_S_ii
	.globl	_Z10colorspacePfS_S_S_S_S_ii
	.p2align	8
	.type	_Z10colorspacePfS_S_S_S_S_ii,@function
_Z10colorspacePfS_S_S_S_S_ii:           ; @_Z10colorspacePfS_S_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b64 s[2:3], s[0:1], 0x30
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s2, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yuv2rgb_REC_2020_NCL@rel32@lo+4
	s_addc_u32 s3, s3, yuv2rgb_REC_2020_NCL@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s14, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v19, vcc_lo
	v_add_co_u32 v2, vcc_lo, s12, v18
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v19, vcc_lo
	global_load_b32 v4, v[0:1], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, s16, v18
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v19, vcc_lo
	global_load_b32 v1, v[0:1], off
	s_clause 0x1
	s_load_b256 s[4:11], s[2:3], 0x0
	s_load_b32 s2, s[2:3], 0x20
	s_load_b128 s[12:15], s[0:1], 0x20
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_mul_f32_e32 v17, s11, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v0, s5, v4 :: v_dual_fmac_f32 v17, s10, v2
	v_mul_f32_e32 v16, s8, v4
	v_fmac_f32_e32 v0, s4, v2
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, _Z12st_2084_eotff@rel32@lo+4
	s_addc_u32 s11, s11, _Z12st_2084_eotff@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v17, s2, v1 :: v_dual_fmac_f32 v16, s7, v2
	v_fmac_f32_e32 v0, s6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, s9, v1
	s_swappc_b64 s[30:31], s[10:11]
	v_mul_f32_e32 v20, 0x42c80000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v16
	s_swappc_b64 s[30:31], s[10:11]
	v_mul_f32_e32 v16, 0x42c80000, v0
	v_mov_b32_e32 v0, v17
	s_swappc_b64 s[30:31], s[10:11]
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, gamutMa@rel32@lo+4
	s_addc_u32 s9, s9, gamutMa@rel32@hi+12
	v_mul_f32_e32 v0, 0x42c80000, v0
	s_clause 0x1
	s_load_b256 s[0:7], s[8:9], 0x0
	s_load_b32 s8, s[8:9], 0x20
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v1, s1, v16
	v_mul_f32_e32 v12, s7, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, s0, v20
	v_fmac_f32_e32 v12, s6, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v1, s2, v0
	v_mul_f32_e32 v11, s4, v16
	v_fmac_f32_e32 v12, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, s3, v20
	v_dual_fmac_f32 v11, s5, v0 :: v_dual_mov_b32 v0, v1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, _Z12rec_709_oetff@rel32@lo+4
	s_addc_u32 s5, s5, _Z12rec_709_oetff@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[4:5]
	v_dual_mov_b32 v13, v0 :: v_dual_mov_b32 v0, v11
	s_swappc_b64 s[30:31], s[4:5]
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v0, v12
	s_swappc_b64 s[30:31], s[4:5]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, rgb2yuv_REC_709@rel32@lo+4
	s_addc_u32 s1, s1, rgb2yuv_REC_709@rel32@hi+12
	v_add_co_u32 v1, vcc_lo, s18, v18
	s_load_b128 s[0:3], s[0:1], 0x0
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v19, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v4, 0 :: v_dual_mul_f32 v3, s1, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, s0, v13
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, rgb2yuv_REC_709@rel32@lo+16
	s_addc_u32 s1, s1, rgb2yuv_REC_709@rel32@hi+24
	v_fmac_f32_e32 v3, s2, v0
	global_store_b32 v[1:2], v3, off
	global_load_b96 v[1:3], v4, s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, rgb2yuv_REC_709@rel32@lo+28
	s_addc_u32 s1, s1, rgb2yuv_REC_709@rel32@hi+36
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, v13, v1
	v_add_co_u32 v1, vcc_lo, s12, v18
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v19, vcc_lo
	v_fmac_f32_e32 v5, v0, v3
	global_store_b32 v[1:2], v5, off
	global_load_b96 v[1:3], v4, s[0:1]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v13, v1
	v_fmac_f32_e32 v2, v0, v3
	v_add_co_u32 v0, vcc_lo, s14, v18
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v19, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB4_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10colorspacePfS_S_S_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z10colorspacePfS_S_S_S_S_ii, .Lfunc_end4-_Z10colorspacePfS_S_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 688
; NumSgprs: 35
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16resize_line_32_yPhPfii ; -- Begin function _Z16resize_line_32_yPhPfii
	.globl	_Z16resize_line_32_yPhPfii
	.p2align	8
	.type	_Z16resize_line_32_yPhPfii,@function
_Z16resize_line_32_yPhPfii:             ; @_Z16resize_line_32_yPhPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s2, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s4, 0x9edf1f7e
	s_mov_b32 s5, 0x3f52b404
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
	s_mov_b32 s0, 0x9ffcfefc
	s_mov_b32 s1, 0xbfb2b404
	global_load_u8 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[3:4], v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[3:4], s[4:5], s[0:1]
	v_cvt_f32_f64_e32 v3, v[3:4]
	global_store_b32 v[0:1], v3, off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16resize_line_32_yPhPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z16resize_line_32_yPhPfii, .Lfunc_end5-_Z16resize_line_32_yPhPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17resize_line_32_uvPhPfii ; -- Begin function _Z17resize_line_32_uvPhPfii
	.globl	_Z17resize_line_32_uvPhPfii
	.p2align	8
	.type	_Z17resize_line_32_uvPhPfii,@function
_Z17resize_line_32_uvPhPfii:            ; @_Z17resize_line_32_uvPhPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mul_i32 s4, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB6_20
; %bb.1:
	s_ashr_i32 s4, s2, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s5, s2, s4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s5, s5, s4
	v_add_nc_u32_e32 v4, v1, v2
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s6, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v2
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s4, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s0, s3, -1
	s_lshr_b32 s1, s2, 31
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_add_i32 s1, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s3, s1, 1
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v5
	v_mul_lo_u32 v0, v3, s2
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cmp_ne_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_and_b32_e32 v5, 1, v0
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s10, exec_lo, s1
	s_cbranch_execz .LBB6_15
; %bb.2:
	s_add_i32 s0, s2, -1
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	v_cmp_ne_u32_e64 s0, s0, v0
	v_and_b32_e32 v4, 1, v3
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 s11, vcc_lo, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 1, v4
	s_xor_b32 s12, exec_lo, s0
	s_cbranch_execz .LBB6_8
; %bb.3:
	v_lshrrev_b32_e32 v4, 31, v3
	v_lshrrev_b32_e32 v5, 31, v0
	s_mov_b32 s0, 0xa003a73b
	s_mov_b32 s8, 0xa06c1b5a
	s_mov_b32 s1, 0xbfe24924
	v_add_nc_u32_e32 v3, v3, v4
	v_add_nc_u32_e32 v0, v0, v5
	s_mov_b32 s9, 0x3f524924
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 1, v3
	v_ashrrev_i32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, s3, v[0:1]
	v_ashrrev_i32_e32 v0, 31, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v0, vcc_lo
	global_load_u8 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[3:4], v0
	v_fma_f64 v[3:4], v[3:4], s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[3:4]
	v_cvt_f64_f32_e32 v[3:4], v0
	v_add_nc_u32_e32 v0, s3, v7
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v8, 31, v0
	s_and_saveexec_b32 s13, s11
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB6_5
; %bb.4:
	v_add_co_u32 v7, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_clause 0x1
	global_load_u16 v0, v[7:8], off
	global_load_u8 v7, v[5:6], off offset:1
	s_waitcnt vmcnt(1)
	v_lshrrev_b16 v5, 8, v0
	v_and_b32_e32 v0, 0xff, v0
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v5, 0xffff, v5
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_u32_e32 v[5:6], v5
	v_cvt_f64_u32_e32 v[9:10], v0
	v_fma_f64 v[7:8], v[7:8], s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[5:6], v[5:6], s[8:9], s[0:1]
	v_fma_f64 v[9:10], v[9:10], s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v7, v[7:8]
	v_cvt_f32_f64_e32 v0, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v9, v[9:10]
	v_cvt_f64_f32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_cvt_f64_f32_e32 v[9:10], v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[7:8], v[7:8], 0.5
	v_mul_f64 v[5:6], v[5:6], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], v[3:4], 0.5, v[7:8]
                                        ; implicit-def: $vgpr8
	v_fma_f64 v[5:6], v[9:10], 0.5, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v0, v[5:6]
	v_cvt_f32_f64_e32 v5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[3:4], v0
	v_cvt_f64_f32_e32 v[5:6], v5
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[3:4], v[3:4], -2
	v_fma_f64 v[3:4], 0x3fe80000, v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v7, v[3:4]
                                        ; implicit-def: $vgpr3_vgpr4
.LBB6_5:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s13
	s_cbranch_execz .LBB6_7
; %bb.6:
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
	s_mov_b32 s8, 0xa003a73b
	s_mov_b32 s14, 0xa06c1b5a
	s_mov_b32 s9, 0xbfe24924
	global_load_u8 v0, v[5:6], off
	s_mov_b32 s15, 0x3f524924
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[5:6], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[14:15], s[8:9]
	v_cvt_f32_f64_e32 v0, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_ldexp_f64 v[5:6], v[5:6], -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], 0x3fe80000, v[3:4], v[5:6]
	v_cvt_f32_f64_e32 v7, v[3:4]
.LBB6_7:                                ; %Flow236
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr0
.LBB6_8:                                ; %Flow239
	s_and_not1_saveexec_b32 s12, s12
	s_cbranch_execz .LBB6_14
; %bb.9:
	v_lshrrev_b32_e32 v4, 31, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 1, v3
	s_mov_b32 s0, 0xa003a73b
	s_mov_b32 s8, 0xa06c1b5a
	s_mov_b32 s1, 0xbfe24924
	v_add_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v5, -1, v8
	s_mov_b32 s9, 0x3f524924
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 1, v0
	v_mad_u64_u32 v[3:4], null, v5, s3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	global_load_u8 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[3:4], v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[3:4], s[8:9], s[0:1]
	v_cvt_f32_f64_e32 v3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cvt_f64_f32_e32 v[3:4], v3
	s_and_saveexec_b32 s13, s11
	s_xor_b32 s11, exec_lo, s13
	s_cbranch_execz .LBB6_11
; %bb.10:
	v_mad_u64_u32 v[9:10], null, v8, s3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v9
	v_add_co_u32 v7, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v0, vcc_lo
	s_clause 0x1
	global_load_u16 v0, v[7:8], off
	global_load_u8 v7, v[5:6], off offset:1
	s_waitcnt vmcnt(1)
	v_lshrrev_b16 v5, 8, v0
	v_and_b32_e32 v0, 0xff, v0
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v5, 0xffff, v5
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_u32_e32 v[5:6], v5
	v_cvt_f64_u32_e32 v[9:10], v0
	v_fma_f64 v[7:8], v[7:8], s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[5:6], v[5:6], s[8:9], s[0:1]
	v_fma_f64 v[9:10], v[9:10], s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v7, v[7:8]
	v_cvt_f32_f64_e32 v0, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v9, v[9:10]
	v_cvt_f64_f32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_cvt_f64_f32_e32 v[9:10], v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[7:8], v[7:8], 0.5
	v_mul_f64 v[5:6], v[5:6], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], v[3:4], 0.5, v[7:8]
                                        ; implicit-def: $vgpr8
	v_fma_f64 v[5:6], v[9:10], 0.5, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v0, v[5:6]
	v_cvt_f32_f64_e32 v5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[3:4], v0
	v_cvt_f64_f32_e32 v[5:6], v5
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], 0x3fe80000, v[3:4]
	v_fma_f64 v[3:4], 0x3fd00000, v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v7, v[3:4]
                                        ; implicit-def: $vgpr3_vgpr4
.LBB6_11:                               ; %Flow237
	s_and_not1_saveexec_b32 s0, s11
	s_cbranch_execz .LBB6_13
; %bb.12:
	v_mad_u64_u32 v[5:6], null, v8, s3, v[0:1]
	s_mov_b32 s8, 0xa003a73b
	s_mov_b32 s14, 0xa06c1b5a
	s_mov_b32 s9, 0xbfe24924
	s_mov_b32 s15, 0x3f524924
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v5
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v0, vcc_lo
	global_load_u8 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[5:6], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[14:15], s[8:9]
	v_cvt_f32_f64_e32 v0, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_mul_f64 v[5:6], 0x3fe80000, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], 0x3fd00000, v[3:4], v[5:6]
	v_cvt_f32_f64_e32 v7, v[3:4]
.LBB6_13:                               ; %Flow238
	s_or_b32 exec_lo, exec_lo, s0
.LBB6_14:                               ; %Flow240
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr3
.LBB6_15:                               ; %Flow242
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB6_19
; %bb.16:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v4, 31, v3
	v_lshrrev_b32_e32 v6, 31, v0
	s_mov_b32 s8, 0xa06c1b5a
	s_mov_b32 s9, 0x3f524924
	s_add_i32 s0, s2, -1
	v_add_nc_u32_e32 v3, v3, v4
	v_add_nc_u32_e32 v4, v0, v6
	v_cmp_ne_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v8, 1, v3
	v_ashrrev_i32_e32 v3, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, s3, v[3:4]
	v_ashrrev_i32_e32 v4, 31, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s4, 0xa003a73b
	s_mov_b32 s5, 0xbfe24924
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	global_load_u8 v6, v[3:4], off
	s_and_b32 s2, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], s[8:9], s[4:5]
	v_cvt_f32_f64_e32 v7, v[6:7]
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB6_18
; %bb.17:
	global_load_u8 v0, v[3:4], off offset:1
	v_cvt_f64_f32_e32 v[5:6], v7
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[3:4], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[3:4], s[8:9], s[4:5]
	v_cvt_f32_f64_e32 v0, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[3:4], v0
	v_mul_f64 v[3:4], v[3:4], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[5:6], 0.5, v[3:4]
	v_cvt_f32_f64_e32 v7, v[3:4]
.LBB6_18:                               ; %Flow241
	s_or_b32 exec_lo, exec_lo, s0
.LBB6_19:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v7, off
.LBB6_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17resize_line_32_uvPhPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z17resize_line_32_uvPhPfii, .Lfunc_end6-_Z17resize_line_32_uvPhPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1764
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15stamp_line_32_yPfPhii ; -- Begin function _Z15stamp_line_32_yPfPhii
	.globl	_Z15stamp_line_32_yPfPhii
	.p2align	8
	.type	_Z15stamp_line_32_yPfPhii,@function
_Z15stamp_line_32_yPfPhii:              ; @_Z15stamp_line_32_yPfPhii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s2, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_mov_b32 s0, 0x445b0000
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_fmaak_f32 v0, s0, v0, 0x42800000
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f32_e32 v0, 0x447fc000, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_med3_u16 v3, v0, 64, 0x3ac
	v_add_co_u32 v0, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
	global_store_b8 v[0:1], v3, off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15stamp_line_32_yPfPhii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z15stamp_line_32_yPfPhii, .Lfunc_end7-_Z15stamp_line_32_yPfPhii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16stamp_line_32_uvPfPhii ; -- Begin function _Z16stamp_line_32_uvPfPhii
	.globl	_Z16stamp_line_32_uvPfPhii
	.p2align	8
	.type	_Z16stamp_line_32_uvPfPhii,@function
_Z16stamp_line_32_uvPfPhii:             ; @_Z16stamp_line_32_uvPfPhii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s2, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b8 v[0:1], v2, off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16stamp_line_32_uvPfPhii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z16stamp_line_32_uvPfPhii, .Lfunc_end8-_Z16stamp_line_32_uvPfPhii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 116
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	FCC_KR                  ; @FCC_KR
	.type	FCC_KR,@object
	.data
	.globl	FCC_KR
	.p2align	2, 0x0
FCC_KR:
	.long	0x3e99999a                      ; float 0.300000012
	.size	FCC_KR, 4

	.protected	FCC_KB                  ; @FCC_KB
	.type	FCC_KB,@object
	.globl	FCC_KB
	.p2align	2, 0x0
FCC_KB:
	.long	0x3de147ae                      ; float 0.109999999
	.size	FCC_KB, 4

	.protected	SMPTE_240M_KR           ; @SMPTE_240M_KR
	.type	SMPTE_240M_KR,@object
	.globl	SMPTE_240M_KR
	.p2align	2, 0x0
SMPTE_240M_KR:
	.long	0x3e591687                      ; float 0.211999997
	.size	SMPTE_240M_KR, 4

	.protected	SMPTE_240M_KB           ; @SMPTE_240M_KB
	.type	SMPTE_240M_KB,@object
	.globl	SMPTE_240M_KB
	.p2align	2, 0x0
SMPTE_240M_KB:
	.long	0x3db22d0e                      ; float 0.0869999975
	.size	SMPTE_240M_KB, 4

	.protected	REC_601_KR              ; @REC_601_KR
	.type	REC_601_KR,@object
	.globl	REC_601_KR
	.p2align	2, 0x0
REC_601_KR:
	.long	0x3e991687                      ; float 0.298999995
	.size	REC_601_KR, 4

	.protected	REC_601_KB              ; @REC_601_KB
	.type	REC_601_KB,@object
	.globl	REC_601_KB
	.p2align	2, 0x0
REC_601_KB:
	.long	0x3de978d5                      ; float 0.114
	.size	REC_601_KB, 4

	.protected	REC_709_KR              ; @REC_709_KR
	.type	REC_709_KR,@object
	.globl	REC_709_KR
	.p2align	2, 0x0
REC_709_KR:
	.long	0x3e59b3d0                      ; float 0.212599993
	.size	REC_709_KR, 4

	.protected	REC_709_KB              ; @REC_709_KB
	.type	REC_709_KB,@object
	.globl	REC_709_KB
	.p2align	2, 0x0
REC_709_KB:
	.long	0x3d93dd98                      ; float 0.0722000003
	.size	REC_709_KB, 4

	.protected	REC_2020_KR             ; @REC_2020_KR
	.type	REC_2020_KR,@object
	.globl	REC_2020_KR
	.p2align	2, 0x0
REC_2020_KR:
	.long	0x3e86809d                      ; float 0.262699991
	.size	REC_2020_KR, 4

	.protected	REC_2020_KB             ; @REC_2020_KB
	.type	REC_2020_KB,@object
	.globl	REC_2020_KB
	.p2align	2, 0x0
REC_2020_KB:
	.long	0x3d72e48f                      ; float 0.0593000017
	.size	REC_2020_KB, 4

	.protected	REC709_ALPHA            ; @REC709_ALPHA
	.type	REC709_ALPHA,@object
	.globl	REC709_ALPHA
	.p2align	2, 0x0
REC709_ALPHA:
	.long	0x3f8cb5c2                      ; float 1.09929681
	.size	REC709_ALPHA, 4

	.protected	REC709_BETA             ; @REC709_BETA
	.type	REC709_BETA,@object
	.globl	REC709_BETA
	.p2align	2, 0x0
REC709_BETA:
	.long	0x3c93e5eb                      ; float 0.0180539694
	.size	REC709_BETA, 4

	.protected	ST2084_M1               ; @ST2084_M1
	.type	ST2084_M1,@object
	.globl	ST2084_M1
	.p2align	2, 0x0
ST2084_M1:
	.long	0x3e232000                      ; float 0.159301758
	.size	ST2084_M1, 4

	.protected	ST2084_M2               ; @ST2084_M2
	.type	ST2084_M2,@object
	.globl	ST2084_M2
	.p2align	2, 0x0
ST2084_M2:
	.long	0x429db000                      ; float 78.84375
	.size	ST2084_M2, 4

	.protected	ST2084_C1               ; @ST2084_C1
	.type	ST2084_C1,@object
	.globl	ST2084_C1
	.p2align	2, 0x0
ST2084_C1:
	.long	0x3f560000                      ; float 0.8359375
	.size	ST2084_C1, 4

	.protected	ST2084_C2               ; @ST2084_C2
	.type	ST2084_C2,@object
	.globl	ST2084_C2
	.p2align	2, 0x0
ST2084_C2:
	.long	0x4196d000                      ; float 18.8515625
	.size	ST2084_C2, 4

	.protected	ST2084_C3               ; @ST2084_C3
	.type	ST2084_C3,@object
	.globl	ST2084_C3
	.p2align	2, 0x0
ST2084_C3:
	.long	0x41958000                      ; float 18.6875
	.size	ST2084_C3, 4

	.protected	yuv2rgb_REC_2020_NCL    ; @yuv2rgb_REC_2020_NCL
	.type	yuv2rgb_REC_2020_NCL,@object
	.globl	yuv2rgb_REC_2020_NCL
	.p2align	4, 0x0
yuv2rgb_REC_2020_NCL:
	.long	0x3f800000                      ; float 1
	.long	0x2382f0e5                      ; float 1.4196651E-17
	.long	0x3fbcbfb1                      ; float 1.47459996
	.long	0x3f800000                      ; float 1
	.long	0xbe28809d                      ; float -0.164553121
	.long	0xbf124433                      ; float -0.571353137
	.long	0x3f800000                      ; float 1
	.long	0x3ff0d1b7                      ; float 1.88139999
	.long	0x2482f0e5                      ; float 5.67866042E-17
	.size	yuv2rgb_REC_2020_NCL, 36

	.protected	rgb2yuv_REC_709         ; @rgb2yuv_REC_709
	.type	rgb2yuv_REC_709,@object
	.globl	rgb2yuv_REC_709
	.p2align	4, 0x0
rgb2yuv_REC_709:
	.long	0x3e59b3d0                      ; float 0.212599993
	.long	0x3f371759                      ; float 0.715200006
	.long	0x3d93dd98                      ; float 0.0722000003
	.long	0xbdeaa4c8                      ; float -0.114572108
	.long	0xbec556ce                      ; float -0.385427892
	.long	0x3f000000                      ; float 0.5
	.long	0x3f000000                      ; float 0.5
	.long	0xbee886bb                      ; float -0.454152912
	.long	0xbd3bca29                      ; float -0.0458470918
	.size	rgb2yuv_REC_709, 36

	.protected	gamutMa                 ; @gamutMa
	.type	gamutMa,@object
	.globl	gamutMa
	.p2align	4, 0x0
gamutMa:
	.long	0x3fd48af8                      ; float 1.66049099
	.long	0xbf166fa6                      ; float -0.58764112
	.long	0xbd95324f                      ; float -0.0728498623
	.long	0xbdff1452                      ; float -0.124550477
	.long	0x3f9102dd                      ; float 1.13289988
	.long	0xbc08cc04                      ; float -0.00834942236
	.long	0xbc94b0e9                      ; float -0.0181507636
	.long	0xbdcdfc4f                      ; float -0.100578897
	.long	0x3f8f3289                      ; float 1.11872971
	.size	gamutMa, 36

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym ST2084_M1
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	.addrsig_sym ST2084_C1
	.addrsig_sym ST2084_C2
	.addrsig_sym ST2084_C3
	.addrsig_sym yuv2rgb_REC_2020_NCL
	.addrsig_sym rgb2yuv_REC_709
	.addrsig_sym gamutMa
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
