

/*This mixed-precision matrix-vector multiplication algorithm is based on cublasSgemv NVIDIA's CUBLAS 1.1.
*/

#define LOG_THREAD_COUNT    (7)
#define THREAD_COUNT        (1 << LOG_THREAD_COUNT)
#define CTAS                (64)
#define IDXA(row,col)       (lda*(col)+(row))
#define IDXX(i)             (startx + ((i) * incx))
#define IDXY(i)             (starty + ((i) * incy))
#define TILEW_LOG           (5)
#define TILEW               (1 << TILEW_LOG)
#define TILEH_LOG           (5)
#define TILEH               (1 << TILEH_LOG)
#define X_ELEMS_PER_THREAD  (4)
#define IINC                (CTAS * THREAD_COUNT)
#define JINC                (THREAD_COUNT * X_ELEMS_PER_THREAD)
#define XINC                (THREAD_COUNT)


__shared__ float XX[TILEH];
__shared__ float AA[(TILEH+1)*TILEW];


__global__ void sgemvn_mixedprecis(const float *A, const float *x,float *y, int m, int n, int lda, int   incx,   int   incy)
{
    __shared__ float XX[JINC];
    int i, ii, j, jj, idx, incr, tid;
    double sdot;
    int startx;
    int starty;


    tid = threadIdx.x;
    startx = (incx >= 0) ? 0 : ((1 - n) * incx);
    starty = (incy >= 0) ? 0 : ((1 - m) * incy);

    for (i = 0; i < m; i += IINC) {

        ii = i + blockIdx.x * THREAD_COUNT;
        if (ii >= m) break;
        ii += tid;
        sdot = 0.0f;

        for (j = 0; j < n; j += JINC) {
            int jjLimit = min (j + JINC, n);
            incr = XINC * incx;
            jj = j + tid;
            __syncthreads ();
            idx = IDXX(jj);

            if (jj < (jjLimit - 3 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
                XX[tid+1*XINC] = x[idx + 1 * incr];
                XX[tid+2*XINC] = x[idx + 2 * incr];
                XX[tid+3*XINC] = x[idx + 3 * incr];
            }
            else if (jj < (jjLimit - 2 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
                XX[tid+1*XINC] = x[idx + 1 * incr];
                XX[tid+2*XINC] = x[idx + 2 * incr];
            }
            else if (jj < (jjLimit - 1 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
                XX[tid+1*XINC] = x[idx + 1 * incr];
            }
            else if (jj < (jjLimit - 0 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
            }

            __syncthreads ();

            if (ii < m) { /* if this row is active, accumulate dp */
                idx = IDXA(ii, j);
                incr = lda;
                jjLimit = jjLimit - j;
                jj = 0;
                while (jj < (jjLimit - 5)) {
                    sdot += A[idx + 0*incr] * XX[jj+ 0];
                    sdot += A[idx + 1*incr] * XX[jj+ 1];
                    sdot += A[idx + 2*incr] * XX[jj+ 2];
                    sdot += A[idx + 3*incr] * XX[jj+ 3];
                    sdot += A[idx + 4*incr] * XX[jj+ 4];
                    sdot += A[idx + 5*incr] * XX[jj+ 5];
                    jj   += 6;
                    idx  += 6 * incr;
                }
                while (jj < jjLimit) {
                    sdot += A[idx + 0*incr] * XX[jj+ 0];
                    jj   += 1;
                    idx  += 1 * incr;
                }
            }
        }
        if (ii < m) {
            idx = IDXY(ii);

           y[idx] = sdot;
        }
    }
}

	.file	"tmpxft_002e6f73_00000000-6_sgemv_mixedprecision.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z18sgemvn_mixedprecisPKfS0_PfiiiiiPKfS0_Pfiiiii
	.type	_Z49__device_stub__Z18sgemvn_mixedprecisPKfS0_PfiiiiiPKfS0_Pfiiiii, @function
_Z49__device_stub__Z18sgemvn_mixedprecisPKfS0_PfiiiiiPKfS0_Pfiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z49__device_stub__Z18sgemvn_mixedprecisPKfS0_PfiiiiiPKfS0_Pfiiiii, .-_Z49__device_stub__Z18sgemvn_mixedprecisPKfS0_PfiiiiiPKfS0_Pfiiiii
	.globl	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.type	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii, @function
_Z18sgemvn_mixedprecisPKfS0_Pfiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z18sgemvn_mixedprecisPKfS0_PfiiiiiPKfS0_Pfiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii, .-_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18sgemvn_mixedprecisPKfS0_Pfiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>


/*This mixed-precision matrix-vector multiplication algorithm is based on cublasSgemv NVIDIA's CUBLAS 1.1.
*/

#define LOG_THREAD_COUNT    (7)
#define THREAD_COUNT        (1 << LOG_THREAD_COUNT)
#define CTAS                (64)
#define IDXA(row,col)       (lda*(col)+(row))
#define IDXX(i)             (startx + ((i) * incx))
#define IDXY(i)             (starty + ((i) * incy))
#define TILEW_LOG           (5)
#define TILEW               (1 << TILEW_LOG)
#define TILEH_LOG           (5)
#define TILEH               (1 << TILEH_LOG)
#define X_ELEMS_PER_THREAD  (4)
#define IINC                (CTAS * THREAD_COUNT)
#define JINC                (THREAD_COUNT * X_ELEMS_PER_THREAD)
#define XINC                (THREAD_COUNT)


__shared__ float XX[TILEH];
__shared__ float AA[(TILEH+1)*TILEW];


__global__ void sgemvn_mixedprecis(const float *A, const float *x,float *y, int m, int n, int lda, int   incx,   int   incy)
{
    __shared__ float XX[JINC];
    int i, ii, j, jj, idx, incr, tid;
    double sdot;
    int startx;
    int starty;


    tid = threadIdx.x;
    startx = (incx >= 0) ? 0 : ((1 - n) * incx);
    starty = (incy >= 0) ? 0 : ((1 - m) * incy);

    for (i = 0; i < m; i += IINC) {

        ii = i + blockIdx.x * THREAD_COUNT;
        if (ii >= m) break;
        ii += tid;
        sdot = 0.0f;

        for (j = 0; j < n; j += JINC) {
            int jjLimit = min (j + JINC, n);
            incr = XINC * incx;
            jj = j + tid;
            __syncthreads ();
            idx = IDXX(jj);

            if (jj < (jjLimit - 3 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
                XX[tid+1*XINC] = x[idx + 1 * incr];
                XX[tid+2*XINC] = x[idx + 2 * incr];
                XX[tid+3*XINC] = x[idx + 3 * incr];
            }
            else if (jj < (jjLimit - 2 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
                XX[tid+1*XINC] = x[idx + 1 * incr];
                XX[tid+2*XINC] = x[idx + 2 * incr];
            }
            else if (jj < (jjLimit - 1 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
                XX[tid+1*XINC] = x[idx + 1 * incr];
            }
            else if (jj < (jjLimit - 0 * XINC)) {
                XX[tid+0*XINC] = x[idx + 0 * incr];
            }

            __syncthreads ();

            if (ii < m) { /* if this row is active, accumulate dp */
                idx = IDXA(ii, j);
                incr = lda;
                jjLimit = jjLimit - j;
                jj = 0;
                while (jj < (jjLimit - 5)) {
                    sdot += A[idx + 0*incr] * XX[jj+ 0];
                    sdot += A[idx + 1*incr] * XX[jj+ 1];
                    sdot += A[idx + 2*incr] * XX[jj+ 2];
                    sdot += A[idx + 3*incr] * XX[jj+ 3];
                    sdot += A[idx + 4*incr] * XX[jj+ 4];
                    sdot += A[idx + 5*incr] * XX[jj+ 5];
                    jj   += 6;
                    idx  += 6 * incr;
                }
                while (jj < jjLimit) {
                    sdot += A[idx + 0*incr] * XX[jj+ 0];
                    jj   += 1;
                    idx  += 1 * incr;
                }
            }
        }
        if (ii < m) {
            idx = IDXY(ii);

           y[idx] = sdot;
        }
    }
}

	.text
	.file	"sgemv_mixedprecision.hip"
	.globl	_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii # -- Begin function _Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii
	.type	_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii,@function
_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii: # @_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18sgemvn_mixedprecisPKfS0_Pfiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii, .Lfunc_end0-_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18sgemvn_mixedprecisPKfS0_Pfiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii,@object # @_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.p2align	3, 0x0
_Z18sgemvn_mixedprecisPKfS0_Pfiiiii:
	.quad	_Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii
	.size	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18sgemvn_mixedprecisPKfS0_Pfiiiii"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__sgemvn_mixedprecisPKfS0_Pfiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii ; -- Begin function _Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.globl	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
	.p2align	8
	.type	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii,@function
_Z18sgemvn_mixedprecisPKfS0_Pfiiiii:    ; @_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_35
; %bb.1:                                ; %.lr.ph167
	s_clause 0x2
	s_load_b32 s13, s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_lshl_b32 s1, s15, 7
	s_sub_i32 s0, 1, s5
	v_add_nc_u32_e32 v1, s1, v0
	s_ashr_i32 s12, s7, 31
	s_sub_i32 s14, 1, s4
	s_mul_i32 s0, s0, s7
	v_lshlrev_b32_e32 v11, 2, v0
	v_mad_u64_u32 v[2:3], null, s6, 3, v[1:2]
	s_and_b32 s12, s12, s0
	v_lshl_add_u32 v15, s6, 1, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v12, 0x200, v11
	v_add_nc_u32_e32 v13, 0x400, v11
	v_add_nc_u32_e32 v14, 0x600, v11
	v_lshl_add_u32 v16, s6, 2, v1
	v_mad_u64_u32 v[3:4], null, s6, 5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s14, s13
	s_ashr_i32 s0, s13, 31
	s_mov_b32 s16, s6
	s_and_b32 s14, s0, s14
	s_cmp_gt_i32 s5, 0
	s_mov_b32 s15, 0
	s_cselect_b32 s19, -1, 0
	s_ashr_i32 s17, s6, 31
	s_mul_i32 s18, s7, 0x180
	s_lshl_b32 s20, s7, 7
	s_lshl_b32 s21, s7, 8
	s_lshl_b32 s22, s6, 9
	s_mul_i32 s23, s6, 6
	s_lshl_b64 s[16:17], s[16:17], 2
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_22 Depth 3
                                        ;       Child Loop BB0_27 Depth 3
	s_add_i32 s0, s15, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s0, s4
	s_cbranch_scc1 .LBB0_30
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s0, v0
	v_mov_b32_e32 v6, 0
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s4, v4
	s_cbranch_vccnz .LBB0_31
; %bb.4:                                ; %.lr.ph163
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v18, v3
	v_dual_mov_b32 v19, v16 :: v_dual_mov_b32 v20, v2
	v_mov_b32_e32 v21, v15
	s_mov_b32 s25, 0
.LBB0_5:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_22 Depth 3
                                        ;       Child Loop BB0_27 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v27, s25, v0
	s_add_i32 s24, s25, 0x200
	s_mov_b32 s30, 0
	s_min_i32 s26, s24, s5
	s_mov_b32 s28, 0
	v_mad_u64_u32 v[7:8], null, v27, s7, s[12:13]
	s_add_i32 s27, s26, 0xfffffe80
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s27, v27
	s_mov_b32 s27, 0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s29, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s29, exec_lo, s29
	s_cbranch_execz .LBB0_11
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s27, s26, 0xffffff00
	s_mov_b32 s30, -1
	v_cmp_le_i32_e32 vcc_lo, s27, v27
	s_mov_b32 s27, 0
	s_and_saveexec_b32 s31, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s27, s26, 0xffffff80
	s_mov_b32 s28, -1
	v_cmp_le_i32_e32 vcc_lo, s27, v27
	s_mov_b32 s27, 0
	s_and_saveexec_b32 s30, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s30, exec_lo, s30
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_gt_i32_e32 vcc_lo, s26, v27
	s_xor_b32 s28, exec_lo, -1
	s_and_b32 s27, vcc_lo, exec_lo
; %bb.9:                                ; %Flow274
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s27, s27, exec_lo
	s_and_b32 s28, s28, exec_lo
	s_xor_b32 s30, exec_lo, -1
.LBB0_10:                               ; %Flow273
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	v_dual_mov_b32 v10, v11 :: v_dual_mov_b32 v25, v12
	v_dual_mov_b32 v22, v12 :: v_dual_mov_b32 v23, v11
	v_mov_b32_e32 v8, v7
	v_dual_mov_b32 v24, v13 :: v_dual_mov_b32 v9, v7
	v_mov_b32_e32 v26, v11
	s_and_b32 s27, s27, exec_lo
	s_and_b32 s28, s28, exec_lo
	s_and_b32 s30, s30, exec_lo
.LBB0_11:                               ; %Flow272
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_saveexec_b32 s29, s29
	v_dual_mov_b32 v27, s21 :: v_dual_mov_b32 v28, s20
	s_xor_b32 exec_lo, exec_lo, s29
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_5 Depth=2
	v_ashrrev_i32_e32 v8, 31, v7
	v_dual_mov_b32 v27, s18 :: v_dual_mov_b32 v24, v14
	v_dual_mov_b32 v25, v13 :: v_dual_mov_b32 v26, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[7:8]
	s_or_b32 s30, s30, exec_lo
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
	v_mov_b32_e32 v28, s21
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	v_add_nc_u32_e32 v9, s20, v7
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v8
                                        ; implicit-def: $vgpr8
.LBB0_13:                               ; %Flow275
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
	v_mov_b32_e32 v29, s20
	s_and_saveexec_b32 s29, s30
	s_cbranch_execz .LBB0_15
; %bb.14:                               ; %.sink.split.sink.split.sink.split
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_ashrrev_i32_e32 v10, 31, v9
	v_dual_mov_b32 v22, v24 :: v_dual_mov_b32 v29, v27
	s_or_b32 s28, s28, exec_lo
	v_mov_b32_e32 v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[9:10]
                                        ; implicit-def: $vgpr10
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	global_load_b32 v9, v[8:9], off
	v_add_nc_u32_e32 v8, v7, v28
	s_waitcnt vmcnt(0)
	ds_store_b32 v26, v9
.LBB0_15:                               ; %Flow276
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
	s_and_saveexec_b32 s29, s28
	s_cbranch_execz .LBB0_17
; %bb.16:                               ; %.sink.split.sink.split
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_ashrrev_i32_e32 v9, 31, v8
	v_dual_mov_b32 v10, v22 :: v_dual_add_nc_u32 v7, v7, v29
	s_or_b32 s27, s27, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v23, v8
.LBB0_17:                               ; %Flow277
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
	s_and_saveexec_b32 s28, s27
	s_cbranch_execz .LBB0_19
; %bb.18:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v7
.LBB0_19:                               ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s27, s0
	s_cbranch_execz .LBB0_28
; %bb.20:                               ;   in Loop: Header=BB0_5 Depth=2
	s_sub_i32 s26, s26, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s26, 6
	s_cbranch_scc1 .LBB0_24
; %bb.21:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s28, s26, -5
	s_mov_b32 s30, 0
	s_mov_b32 s29, 0
	s_mov_b32 s25, 0
.LBB0_22:                               ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v22, s30 :: v_dual_add_nc_u32 v7, s29, v17
	s_add_i32 s25, s25, 6
	s_add_i32 s30, s30, 24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v24, v[7:8], off
	v_add_co_u32 v7, vcc_lo, v7, s16
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	global_load_b32 v26, v[7:8], off
	v_add_nc_u32_e32 v7, s29, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v27, v[7:8], off
	v_add_nc_u32_e32 v7, s29, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v28, v[7:8], off
	v_add_nc_u32_e32 v7, s29, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v29, v[7:8], off
	v_add_nc_u32_e32 v7, s29, v18
	s_add_i32 s29, s29, s23
	s_cmp_ge_i32 s25, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v30, v[7:8], off
	ds_load_2addr_b64 v[7:10], v22 offset1:1
	ds_load_b64 v[22:23], v22 offset:16
	s_waitcnt vmcnt(5) lgkmcnt(1)
	v_mul_f32_e32 v7, v24, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[24:25], v7
	s_waitcnt vmcnt(4)
	v_mul_f32_e32 v7, v26, v8
	v_cvt_f64_f32_e32 v[7:8], v7
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v9, v27, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[24:25]
	v_cvt_f64_f32_e32 v[24:25], v9
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f32_e32 v9, v29, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_mul_f32_e32 v7, v28, v10
	v_cvt_f64_f32_e32 v[9:10], v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_f32_e32 v[7:8], v7
	v_add_f64 v[5:6], v[5:6], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v30, v23
	v_cvt_f64_f32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[9:10]
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_cbranch_scc0 .LBB0_22
; %bb.23:                               ; %Flow266
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v7, s29, v17
	s_branch .LBB0_25
.LBB0_24:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mad_u64_u32 v[7:8], null, s25, s6, v[4:5]
	s_mov_b32 s25, 0
.LBB0_25:                               ; %.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s25, s26
	s_cbranch_scc1 .LBB0_28
; %bb.26:                               ; %.lr.ph159.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	s_lshl_b32 s28, s25, 2
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.LBB0_27:                               ; %.lr.ph159
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v9, v[7:8], off
	v_mov_b32_e32 v10, s28
	v_add_co_u32 v7, vcc_lo, v7, s16
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	ds_load_b32 v10, v10
	s_add_i32 s25, s25, 1
	s_add_i32 s28, s28, 4
	s_cmp_lt_i32 s25, s26
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[9:10], v9
	v_add_f64 v[5:6], v[5:6], v[9:10]
	s_cbranch_scc1 .LBB0_27
.LBB0_28:                               ; %Flow268
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v21, s22, v21
	v_add_nc_u32_e32 v20, s22, v20
	v_add_nc_u32_e32 v19, s22, v19
	v_add_nc_u32_e32 v18, s22, v18
	v_add_nc_u32_e32 v17, s22, v17
	s_cmp_lt_i32 s24, s5
	s_cbranch_scc0 .LBB0_31
; %bb.29:                               ;   in Loop: Header=BB0_5 Depth=2
	s_mov_b32 s25, s24
	s_branch .LBB0_5
.LBB0_30:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr1
	s_branch .LBB0_34
.LBB0_31:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s4, v4
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f32_f64_e32 v7, v[5:6]
	v_mad_u64_u32 v[5:6], null, v4, s13, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_store_b32 v[4:5], v7, off
.LBB0_33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_addk_i32 s15, 0x2000
	v_add_nc_u32_e32 v15, 0x2000, v15
	v_add_nc_u32_e32 v2, 0x2000, v2
	v_add_nc_u32_e32 v16, 0x2000, v16
	v_add_nc_u32_e32 v3, 0x2000, v3
	v_add_nc_u32_e32 v1, 0x2000, v1
	s_cmp_ge_i32 s15, s4
	s_cselect_b32 s0, -1, 0
.LBB0_34:                               ; %Flow282
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_2
.LBB0_35:                               ; %._crit_edge168
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18sgemvn_mixedprecisPKfS0_Pfiiiii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18sgemvn_mixedprecisPKfS0_Pfiiiii, .Lfunc_end0-_Z18sgemvn_mixedprecisPKfS0_Pfiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1648
; NumSgprs: 34
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18sgemvn_mixedprecisPKfS0_Pfiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z18sgemvn_mixedprecisPKfS0_Pfiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
