

#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <cuda_runtime.h>

#define PI 3.14159265358979323846

#define N 100000
#define BLOCK_SIZE 1024

__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
	float r = sqrtf(-2*logf(u1));
	float theta = 2*PI*(u2);
	*n1 = r*sinf(theta);
	*n2 = r*cosf(theta);
}

__global__ void norm_transform(float *dev_u1, float *dev_u2, 
		float *dev_n1, float *dev_n2, int size)
{
	int tid = threadIdx.x + blockIdx.x*blockDim.x;
	if (tid < size)
	{
		float res1;
		float res2;
		BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
		dev_n1[tid] = res1;
		dev_n2[tid] = res2;
	}
	
}


int main()
{
	int dev_count;
	cudaGetDeviceCount(&dev_count);
	printf("Number of CUDA-capable devices: %d.\n", dev_count);
	cudaDeviceProp dev_prop;
	for (int j=0; j<dev_count; j++)
	{
		cudaGetDeviceProperties(&dev_prop, j);
		printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
		printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
	}
	int i;
	
	
	curandGenerator_t gen1, gen2;
	float *dev_u1, *dev_u2, *host_u1, *host_u2;
	float *dev_n1, *dev_n2, *host_n1, *host_n2;

	// allocate memory on the host
	//host_u1 = (float*)calloc(N, sizeof(float));
	//host_u2 = (float*)calloc(N, sizeof(float));
	
	float elapsedTime;
	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventRecord(start, 0);
	
	host_n1 = (float*)calloc(N, sizeof(float));
	host_n2 = (float*)calloc(N, sizeof(float));
		

	// allocate memory on the device
	cudaMalloc((void**)&dev_u1, N * sizeof(float));
	cudaMalloc((void**)&dev_u2, N * sizeof(float));
	
	cudaMalloc((void**)&dev_n1, N * sizeof(float));
	cudaMalloc((void**)&dev_n2, N * sizeof(float));
	
	
	// create a mersenne twister
	curandCreateGenerator(&gen1, CURAND_RNG_PSEUDO_MTGP32);
	curandCreateGenerator(&gen2, CURAND_RNG_PSEUDO_MTGP32);

	// set seed
	curandGenerateUniform(gen1, dev_u1, N);
	curandGenerateUniform(gen2, dev_u2, N);
	
	int numBlocks = ceil(float(N) / BLOCK_SIZE);
	
	// box muller transform
	norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
	

	// copy device memory to host
	cudaMemcpy(host_n1, dev_n1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(host_n2, dev_n2, N * sizeof(float), cudaMemcpyDeviceToHost);
	
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsedTime, start, stop);
	cudaEventDestroy(start);
	cudaEventDestroy(stop);
	
	printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n",  N, elapsedTime/1000.0);

	printf("Random normal draws: \n");
	for (i = 0; i < 10; i++)
	{
		printf(" %1.4f  %1.4f\n", host_n1[i], host_n2[i]);
	}
	printf("\n");
	curandDestroyGenerator(gen1);
	curandDestroyGenerator(gen2);
	cudaDeviceReset();
	free(host_n1);
	free(host_n2);
	
	return 0;
}

	.file	"tmpxft_00342e95_00000000-6_monte_carlo.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9BoxMullerffPfS_
	.type	_Z9BoxMullerffPfS_, @function
_Z9BoxMullerffPfS_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z9BoxMullerffPfS_, .-_Z9BoxMullerffPfS_
	.globl	_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
	.type	_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i, @function
_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z14norm_transformPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L4:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i, .-_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
	.globl	_Z14norm_transformPfS_S_S_i
	.type	_Z14norm_transformPfS_S_S_i, @function
_Z14norm_transformPfS_S_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z14norm_transformPfS_S_S_i, .-_Z14norm_transformPfS_S_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Number of CUDA-capable devices: %d.\n"
.LC1:
	.string	"Device number %d has max %d threads per block.\n"
.LC2:
	.string	"Device number %d has %d multiprocessors.\n"
.LC4:
	.string	"Time elapsed to generate 2 x %d normal variables: %f seconds.\n"
.LC5:
	.string	"Random normal draws: \n"
.LC6:
	.string	" %1.4f  %1.4f\n"
.LC7:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	leaq	.LC1(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	subq	$1144, %rsp
	.cfi_def_cfa_offset 1184
	movq	%fs:40, %rax
	movq	%rax, 1128(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
	movl	4(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC0(%rip), %rsi
	call	__printf_chk@PLT
.L11:
	cmpl	%ebx, 4(%rsp)
	jle	.L18
	movl	%ebx, %esi
	leaq	96(%rsp), %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	416(%rsp), %ecx
	movl	%ebx, %edx
	xorl	%eax, %eax
	movq	%rbp, %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	484(%rsp), %ecx
	movl	%ebx, %edx
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	incl	%ebx
	call	__printf_chk@PLT
	jmp	.L11
.L18:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4, %esi
	movl	$100000, %edi
	call	calloc@PLT
	movl	$4, %esi
	movl	$100000, %edi
	movq	%rax, %rbp
	call	calloc@PLT
	leaq	24(%rsp), %rdi
	movl	$400000, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$400000, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$400000, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$400000, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$141, %esi
	call	curandCreateGenerator@PLT
	leaq	16(%rsp), %rdi
	movl	$141, %esi
	call	curandCreateGenerator@PLT
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$100000, %edx
	call	curandGenerateUniform@PLT
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$100000, %edx
	call	curandGenerateUniform@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2147483697, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	addq	%rdi, %rdi
	movq	%rdx, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movl	$100000, %r8d
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
.L13:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%r12d, %r12d
	movl	$400000, %edx
	leaq	.LC6(%rip), %r13
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	leaq	84(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	64(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movl	$100000, %edx
	leaq	.LC4(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	84(%rsp), %xmm0
	divsd	.LC3(%rip), %xmm0
	call	__printf_chk@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L14:
	cvtss2sd	(%rbx,%r12), %xmm1
	movq	%r13, %rsi
	cvtss2sd	0(%rbp,%r12), %xmm0
	movl	$2, %edi
	movb	$2, %al
	addq	$4, %r12
	call	__printf_chk@PLT
	cmpq	$40, %r12
	jne	.L14
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	curandDestroyGenerator@PLT
	movq	16(%rsp), %rdi
	call	curandDestroyGenerator@PLT
	call	cudaDeviceReset@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	1128(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$1144, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z14norm_transformPfS_S_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14norm_transformPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:



#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>


#define PI 3.14159265358979323846

#define N 100000
#define BLOCK_SIZE 1024

__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
	float r = sqrtf(-2*logf(u1));
	float theta = 2*PI*(u2);
	*n1 = r*sinf(theta);
	*n2 = r*cosf(theta);
}

__global__ void norm_transform(float *dev_u1, float *dev_u2, 
		float *dev_n1, float *dev_n2, int size)
{
	int tid = threadIdx.x + blockIdx.x*blockDim.x;
	if (tid < size)
	{
		float res1;
		float res2;
		BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
		dev_n1[tid] = res1;
		dev_n2[tid] = res2;
	}
	
}


int main()
{
	int dev_count;
	hipGetDeviceCount(&dev_count);
	printf("Number of CUDA-capable devices: %d.\n", dev_count);
	hipDeviceProp_t dev_prop;
	for (int j=0; j<dev_count; j++)
	{
		hipGetDeviceProperties(&dev_prop, j);
		printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
		printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
	}
	int i;
	
	
	hiprandGenerator_t gen1, gen2;
	float *dev_u1, *dev_u2, *host_u1, *host_u2;
	float *dev_n1, *dev_n2, *host_n1, *host_n2;

	// allocate memory on the host
	//host_u1 = (float*)calloc(N, sizeof(float));
	//host_u2 = (float*)calloc(N, sizeof(float));
	
	float elapsedTime;
	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventRecord(start, 0);
	
	host_n1 = (float*)calloc(N, sizeof(float));
	host_n2 = (float*)calloc(N, sizeof(float));
		

	// allocate memory on the device
	hipMalloc((void**)&dev_u1, N * sizeof(float));
	hipMalloc((void**)&dev_u2, N * sizeof(float));
	
	hipMalloc((void**)&dev_n1, N * sizeof(float));
	hipMalloc((void**)&dev_n2, N * sizeof(float));
	
	
	// create a mersenne twister
	hiprandCreateGenerator(&gen1, HIPRAND_RNG_PSEUDO_MTGP32);
	hiprandCreateGenerator(&gen2, HIPRAND_RNG_PSEUDO_MTGP32);

	// set seed
	hiprandGenerateUniform(gen1, dev_u1, N);
	hiprandGenerateUniform(gen2, dev_u2, N);
	
	int numBlocks = ceil(float(N) / BLOCK_SIZE);
	
	// box muller transform
	norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
	

	// copy device memory to host
	hipMemcpy(host_n1, dev_n1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(host_n2, dev_n2, N * sizeof(float), hipMemcpyDeviceToHost);
	
	hipEventRecord(stop, 0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsedTime, start, stop);
	hipEventDestroy(start);
	hipEventDestroy(stop);
	
	printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n",  N, elapsedTime/1000.0);

	printf("Random normal draws: \n");
	for (i = 0; i < 10; i++)
	{
		printf(" %1.4f  %1.4f\n", host_n1[i], host_n2[i]);
	}
	printf("\n");
	hiprandDestroyGenerator(gen1);
	hiprandDestroyGenerator(gen2);
	hipDeviceReset();
	free(host_n1);
	free(host_n2);
	
	return 0;
}

	.text
	.file	"monte_carlo.hip"
	.globl	_Z29__device_stub__norm_transformPfS_S_S_i # -- Begin function _Z29__device_stub__norm_transformPfS_S_S_i
	.type	_Z29__device_stub__norm_transformPfS_S_S_i,@function
_Z29__device_stub__norm_transformPfS_S_S_i: # @_Z29__device_stub__norm_transformPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14norm_transformPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__norm_transformPfS_S_S_i, .Lfunc_end0-_Z29__device_stub__norm_transformPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1560, %rsp                     # imm = 0x618
	.cfi_def_cfa_offset 1616
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	20(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	movl	(%rbx), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	cmpl	$0, (%rbx)
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph
	leaq	88(%rsp), %rbx
	xorl	%ebp, %ebp
.LBB1_2:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	%ebp, %esi
	callq	hipGetDevicePropertiesR0600
	movl	408(%rsp), %edx
	movl	$.L.str.1, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movl	476(%rsp), %edx
	movl	$.L.str.2, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	incl	%ebp
	cmpl	20(%rsp), %ebp
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$100000, %edi                   # imm = 0x186A0
	movl	$4, %esi
	callq	calloc
	movq	%rax, %rbx
	movl	$100000, %edi                   # imm = 0x186A0
	movl	$4, %esi
	callq	calloc
	movq	%rax, %r14
	leaq	56(%rsp), %r12
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	48(%rsp), %r15
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	callq	hipMalloc
	leaq	72(%rsp), %r13
	movq	%r13, %rdi
	movl	$403, %esi                      # imm = 0x193
	callq	hiprandCreateGenerator
	leaq	64(%rsp), %rbp
	movq	%rbp, %rdi
	movl	$403, %esi                      # imm = 0x193
	callq	hiprandCreateGenerator
	movq	(%r13), %rdi
	movq	(%r12), %rsi
	movl	$100000, %edx                   # imm = 0x186A0
	callq	hiprandGenerateUniform
	movq	(%rbp), %rdi
	movq	(%r15), %rsi
	movl	$100000, %edx                   # imm = 0x186A0
	callq	hiprandGenerateUniform
	movabsq	$4294967394, %rdi               # imm = 0x100000062
	leaq	926(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rcx
	movl	$100000, %r8d                   # imm = 0x186A0
	callq	_Z29__device_stub__norm_transformPfS_S_S_i
.LBB1_5:
	movq	40(%rsp), %rsi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	84(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	cvtss2sd	(%r15), %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movl	$.L.str.3, %edi
	movl	$100000, %esi                   # imm = 0x186A0
	movb	$1, %al
	callq	printf
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB1_6:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r12,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%r14,%r12,4), %xmm1
	movl	$.L.str.5, %edi
	movb	$2, %al
	callq	printf
	incq	%r12
	cmpq	$10, %r12
	jne	.LBB1_6
# %bb.7:
	movl	$10, %edi
	callq	putchar@PLT
	movq	72(%rsp), %rdi
	callq	hiprandDestroyGenerator
	movq	64(%rsp), %rdi
	callq	hiprandDestroyGenerator
	callq	hipDeviceReset
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$1560, %rsp                     # imm = 0x618
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14norm_transformPfS_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14norm_transformPfS_S_S_i,@object # @_Z14norm_transformPfS_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z14norm_transformPfS_S_S_i
	.p2align	3, 0x0
_Z14norm_transformPfS_S_S_i:
	.quad	_Z29__device_stub__norm_transformPfS_S_S_i
	.size	_Z14norm_transformPfS_S_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Number of CUDA-capable devices: %d.\n"
	.size	.L.str, 37

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Device number %d has max %d threads per block.\n"
	.size	.L.str.1, 48

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Device number %d has %d multiprocessors.\n"
	.size	.L.str.2, 42

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Time elapsed to generate 2 x %d normal variables: %f seconds.\n"
	.size	.L.str.3, 63

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" %1.4f  %1.4f\n"
	.size	.L.str.5, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14norm_transformPfS_S_S_i"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Random normal draws: "
	.size	.Lstr, 22

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__norm_transformPfS_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14norm_transformPfS_S_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14norm_transformPfS_S_S_i ; -- Begin function _Z14norm_transformPfS_S_S_i
	.globl	_Z14norm_transformPfS_S_S_i
	.p2align	8
	.type	_Z14norm_transformPfS_S_S_i,@function
_Z14norm_transformPfS_S_S_i:            ; @_Z14norm_transformPfS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, 0x54442d18
	s_mov_b32 s1, 0x401921fb
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[2:3], v5
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], s[0:1]
	v_cvt_f32_f64_e32 v2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, 0x7fffffff, v2
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v2|
	v_lshrrev_b32_e32 v7, 23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s2
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v17, v3, s0, 0x800000
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, v6
	v_add_nc_u32_e32 v6, 0xffffff88, v7
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v17, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v6
	v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v15, v6
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v17, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v6
	v_mov_b32_e32 v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
	v_cndmask_b32_e32 v5, v11, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v17, v[8:9]
	v_add_nc_u32_e32 v6, v16, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v6
	v_mov_b32_e32 v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v17, v[8:9]
	v_mov_b32_e32 v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0x4e441529, v17, v[8:9]
	v_mov_b32_e32 v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0xa2f9836e, v17, v[8:9]
	v_cndmask_b32_e64 v8, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v9, v14, v12 :: v_dual_add_nc_u32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
	v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v8, v12, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v15, v9, s0
	v_cndmask_b32_e64 v12, v14, v15, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v9, v13, s0
	v_sub_nc_u32_e32 v14, 32, v6
	v_cndmask_b32_e64 v13, v13, v8, s0
	v_cndmask_b32_e64 v5, v8, v5, s0
	v_cndmask_b32_e64 v12, v12, v10, s1
	v_cndmask_b32_e64 v10, v10, v9, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v9, v13, s1
	v_cndmask_b32_e64 v5, v13, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v12, v10, v14
	v_alignbit_b32 v11, v10, v9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v9, v5, v14
	v_cndmask_b32_e32 v6, v15, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v11, v10 :: v_dual_cndmask_b32 v9, v13, v9
	v_bfe_u32 v10, v6, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v6, v8, 30
	v_alignbit_b32 v8, v8, v9, 30
	v_alignbit_b32 v5, v9, v5, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, 0, v10
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v12
	v_xor_b32_e32 v5, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v13, v11
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	v_alignbit_b32 v11, v11, v8, v9
	v_alignbit_b32 v5, v8, v5, v9
	v_lshrrev_b32_e32 v9, 29, v6
	v_lshrrev_b32_e32 v6, 30, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v11, v5, 9
	v_lshlrev_b32_e32 v9, 31, v9
	v_lshrrev_b32_e32 v11, 9, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v6, v10, v6
	v_clz_i32_u32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v9
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v8, v5, v16
	v_or_b32_e32 v8, v11, v14
	v_add_lshl_u32 v11, v12, v13, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v5, 9, v5
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v11
	v_fma_f32 v11, 0x3fc90fda, v8, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 0x33000000, v5
	v_fmamk_f32 v8, v8, 0x33a22168, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v5, v9
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, v12, v8
.LBB0_3:                                ; %Flow32
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v10, 0x3f22f983, |v2|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v10
	v_fma_f32 v5, 0xbfc90fda, v6, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v6, 0xb3a22168, v5
	v_fmamk_f32 v5, v6, 0xa7c234c4, v5
	v_cvt_i32_f32_e32 v6, v6
; %bb.5:                                ; %_ZL4sinff.exit.i
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v18, v3, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v18, 0
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v12
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_mov_b32_e32 v9, v13
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	v_cndmask_b32_e32 v8, v12, v8, vcc_lo
	v_add_nc_u32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v14
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v17, v7
	v_mov_b32_e32 v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v16
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v9, v13, v11
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v16, v10, s0
	v_cndmask_b32_e64 v13, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_sub_nc_u32_e32 v15, 32, v7
	v_cndmask_b32_e64 v14, v14, v9, s0
	v_cndmask_b32_e64 v8, v9, v8, s0
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v11, v11, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s1
	v_cndmask_b32_e64 v8, v14, v8, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v13, v11, v15
	v_alignbit_b32 v12, v11, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v10, v8, v15
	v_cndmask_b32_e32 v7, v16, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v10, v14, v10
	v_bfe_u32 v11, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v7, v9, 30
	v_alignbit_b32 v9, v9, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 0, v11
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_xor_b32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v12
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v12, v12, v9, v10
	v_alignbit_b32 v8, v9, v8, v10
	v_lshrrev_b32_e32 v10, 29, v7
	v_lshrrev_b32_e32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v12, v8, 9
	v_lshlrev_b32_e32 v10, 31, v10
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v13, v9
	v_or_b32_e32 v15, 0.5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v13, 32, v13
	v_sub_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, 31, v13
	v_alignbit_b32 v8, v9, v8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v9, v12, v15
	v_add_lshl_u32 v12, v13, v14, 23
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, 0x3fc90fda, v9
	v_sub_nc_u32_e32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v9, -v13
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v9, v9, 0x33a22168, v12
	v_or_b32_e32 v8, v8, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	v_dual_add_f32 v8, v13, v9 :: v_dual_add_nc_u32 v9, v11, v7
.LBB0_7:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.8:
	v_rndne_f32_e32 v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0xbfc90fda, v7, |v2|
	v_cvt_i32_f32_e32 v9, v7
	v_fmamk_f32 v8, v7, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v8, v7, 0xa7c234c4, v8
; %bb.9:                                ; %_Z9BoxMullerffPfS_.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
	s_mov_b32 s1, 0x37d75334
	v_and_b32_e32 v12, 1, v9
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v3, v3, v2
	v_cndmask_b32_e64 v7, 1.0, 0x4f800000, vcc_lo
	v_and_b32_e32 v11, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v4, v7 :: v_dual_lshlrev_b32 v9, 30, v9
	v_and_b32_e32 v9, 0x80000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v4
	v_fma_f32 v10, 0x3f317217, v4, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v10, v4, 0x3377d1cf, v10
	v_add_f32_e32 v7, v7, v10
	v_cndmask_b32_e64 v10, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_mul_f32 v7, v5, v5
	v_lshlrev_b32_e32 v6, 30, v6
	v_dual_sub_f32 v4, v4, v10 :: v_dual_fmaak_f32 v15, s1, v7, 0xbab64f3b
	v_fmaak_f32 v14, s0, v7, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v4, -2.0, v4 :: v_dual_fmaak_f32 v15, v7, v15, 0x3d2aabf7
	v_fmaak_f32 v14, v7, v14, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_mul_f32_e32 v14, v7, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v15, v7, v15, 0xbf000004 :: v_dual_cndmask_b32 v4, v4, v10
	v_dual_mul_f32 v10, v8, v8 :: v_dual_fmac_f32 v5, v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v7, v15, 1.0
	v_sqrt_f32_e32 v13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v17, s1, v10, 0xbab64f3b
	v_fmaak_f32 v16, s0, v10, 0x3c0881c4
	v_fmaak_f32 v17, v10, v17, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fmaak_f32 v16, v10, v16, 0xbe2aaa9d
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v18, -1, v13
	v_dual_mul_f32 v16, v10, v16 :: v_dual_add_nc_u32 v19, 1, v13
	v_fmaak_f32 v17, v10, v17, 0xbf000004
	v_fma_f32 v20, -v18, v13, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, -v19, v13, v4
	v_fmac_f32_e32 v8, v8, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v10, v10, v17, 1.0
	v_cmp_ge_f32_e64 s0, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, v13, v18, s0
	v_cmp_lt_f32_e64 s0, 0, v14
	v_cndmask_b32_e64 v13, v13, v19, s0
	v_cmp_eq_u32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v7, v5, s0
	v_cmp_eq_u32_e64 s0, 0, v12
	v_cndmask_b32_e64 v7, -v8, v10, s0
	v_mul_f32_e32 v8, 0x37800000, v13
	v_and_b32_e32 v6, 0x80000000, v6
	v_cmp_class_f32_e64 s0, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_2)
	v_xor3_b32 v5, v3, v6, v5
	v_xor_b32_e32 v6, v9, v7
	v_cndmask_b32_e32 v7, v13, v8, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	v_cndmask_b32_e64 v5, 0x7fc00000, v5, s0
	v_cndmask_b32_e64 v6, 0x7fc00000, v6, s0
	v_cndmask_b32_e32 v4, v7, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v5, v4, v5
	v_mul_f32_e32 v4, v4, v6
	global_store_b32 v[2:3], v5, off
	global_store_b32 v[0:1], v4, off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14norm_transformPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14norm_transformPfS_S_S_i, .Lfunc_end0-_Z14norm_transformPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2308
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14norm_transformPfS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14norm_transformPfS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
