//put C:/Users/molly/Desktop/289Q/project/main.cu
//nvcc -std=c++11 main.cu

// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <fstream>
#include <cooperative_groups.h>
#include <cooperative_groups.h>
// includes, project
#include <cuda.h>
#include <cuda_runtime.h>

using namespace cooperative_groups;
namespace cg = cooperative_groups;

// #define FILESIZE_CHAR 1048576
#define FILESIZE_CHAR 1048576
#define FILESIZE_INT FILESIZE_CHAR/4


__host__
void makeLUT(int N, int* LUT){
	int M = N;
	int even = 0;
	int odd = 1;
	int LUTsize = N*(log2((double)N)*2 - 2);
	for (int i =0; i < LUTsize/2; i+=N){
		for (int j=0; j<N; j+=M){
			for (int k =0; k<M/2; k++){
				LUT[i+j+k] = even;
				even+=2;
			}
			for (int k =M/2; k<M; k++){
				LUT[i+j+k] = odd;
				odd+=2;
			}
		} even=0; odd=1; M = M/2;
	}
	for (int x=LUTsize-N, i=LUTsize/2; i<LUTsize;i+=N, x-=N){
		for(int j=0; j<N; j++){
			int newIndex = LUT[x+j-LUTsize/2];
			LUT[newIndex + i] = j;
		}
	}
	return;
}

int createMask(int n)
{
   int r = 0;
   for (int i=0; i<n; i++)
       r |= 1 << i;

   return r;
}


__global__
void benes(int N, int block, char* network, int* LUT, volatile int* valid, int mask, int* data, char* output){
	int idx = threadIdx.x;
	int in1, in2, in1_index, in2_index;
	int readOffset=0;
	int fileSize = FILESIZE_INT/2;
	int readOffsetSecondNet=fileSize;
	thread_group g = tiled_partition(this_thread_block(), 2); //stops working after 32?
		if(blockIdx.x == 0){
			while(readOffset < fileSize){
				in1 = data[idx*2 + readOffset];
				in2 = data[idx*2+1 + readOffset];
				readOffset+=N;
				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
				network[idx*2 + (blockIdx.x+1)*N] = in1;  
				network[idx*2 + (blockIdx.x+1)*N + 1] = in2;
				
				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;  
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;
				}
				g.sync();
				// __syncthreads();
				valid[idx + (blockIdx.x+1)*(N/2)]=1;// valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
				
			}
		}
		
		else if ( blockIdx.x < block) {
			while(readOffset < fileSize){
				while((valid[idx + (blockIdx.x)*(N/2)])==0);
				in1_index = LUT[idx*2 + (blockIdx.x-1)*N];
				in2_index = LUT[idx*2 + (blockIdx.x-1)*N + 1];
				in1 = network[in1_index+(blockIdx.x)*N];
				in2 = network[in2_index+(blockIdx.x)*N];
				valid[idx + (blockIdx.x)*(N/2)] = 0;// valid[idx*2 + 1 + (blockIdx.x)*N] = 0;
			

				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
				network[idx*2 + (blockIdx.x+1)*N] = in1;
				network[idx*2 + (blockIdx.x+1)*N + 1] = in2;

				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;  
				}
				
				if (blockIdx.x != gridDim.x - 1 && blockIdx.x != block-1){
					valid[idx + (blockIdx.x+1)*(N/2)]=1;// valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
					g.sync();
					// __syncthreads();
				}
				else {
					output[idx*2 + readOffset] = network[idx*2 + (blockIdx.x+1)*N];
					output[idx*2+1 + readOffset] = network[idx*2 + (blockIdx.x+1)*N + 1];
				}
				readOffset += N;
			}
		} 



		else if(blockIdx.x == block){
			while(readOffsetSecondNet < FILESIZE_INT){
				in1 = data[idx*2 + readOffsetSecondNet];
				in2 = data[idx*2+1 + readOffsetSecondNet];
				readOffsetSecondNet+=N;
				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
					network[idx*2 + (blockIdx.x+1)*N] = in1;  
					network[idx*2 + (blockIdx.x+1)*N + 1] = in2;
				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;  
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;
				}

				
				valid[idx + (blockIdx.x+1)*(N/2)]=1;// valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
				// __syncthreads();
				g.sync();
			}
		}
		
		else{
			while(readOffsetSecondNet < FILESIZE_INT){
				// printf("waiting for previous block %d to produce\n", blockIdx.x - 1);
				while((valid[idx + (blockIdx.x)*(N/2)])==0);
				
				// printf("waiting for previous block %d to produce\n", blockIdx.x - 1);
				in1_index = LUT[idx*2 + ((blockIdx.x%block)-1)*N];
				in2_index = LUT[idx*2 + ((blockIdx.x%block)-1)*N + 1];
				in1 = network[in1_index+(blockIdx.x)*N];
				in2 = network[in2_index+(blockIdx.x)*N];
				
				// printf("Block %d thread %d consumed %d %d\n", blockIdx.x,threadIdx.x, in1, in2);
				valid[idx + (blockIdx.x)*(N/2)] = 0; //valid[idx*2 + 1 + (blockIdx.x)*N] = 0;
			
				//printf("waiting for next block %d to consume\n", blockIdx.x + 1);
				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
					network[idx*2 + (blockIdx.x+1)*N] = in1;
					network[idx*2 + (blockIdx.x+1)*N + 1] = in2;
					// printf("Block %d produced %d %d\n", blockIdx.x, in1, in2);
				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;  
				}
				//printf("Block %d produced %d %d\n", blockIdx.x, in1, in2);
				if (blockIdx.x != gridDim.x - 1){
					valid[idx + (blockIdx.x+1)*(N/2)]=1; //valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
					// __syncthreads();
					g.sync();
					//printf("valid:%d index:%d\n",valid[idx + (blockIdx.x+1)*N],idx + (blockIdx.x+1)*N);
				}
				else {
					output[idx*2 + readOffsetSecondNet] = network[idx*2 + (blockIdx.x+1)*N];
					output[idx*2+1 + readOffsetSecondNet] = network[idx*2 + (blockIdx.x+1)*N + 1];
				}
				readOffsetSecondNet += N;
			}
		}
}



int main(int argc, char *argv[]){
	
	if (argc != 3){
		printf("Usage: %s <input.txt> <size>\n", argv[0]);
		return 1;
	}
	
	std::ifstream file(argv[1], std::ios::binary);
	if (!file) {
        printf("Could not open input file\n");
        return 1;
    }

	
	int N = atoi(argv[2]);
	if (FILESIZE_INT<N)
		N = FILESIZE_INT;
	int blockSize = N/2; 
	int blocks = 2*log2((double)N)-1; 
	int b = 2*log2((double)N)-1;
	int LUTsize = N*(log2((double)N)*2 - 2);
	int numBlocks;

	if (FILESIZE_INT <= N)
		numBlocks = blocks;
	else
		numBlocks = 2*blocks;

	char* network;
	cudaMallocManaged(&network,N*(numBlocks+1)*sizeof(char));
	memset(network,0,N*(numBlocks+1)*sizeof(char));

	
	int* LUT;
	cudaMallocManaged(&LUT,LUTsize*sizeof(int));
	makeLUT(N,LUT);
	int mask = createMask(log2((double)N));
  
    int *valid;
	cudaMallocManaged(&valid,(N/2)*(numBlocks)*sizeof(int));
	memset(valid,0,(N/2)*(numBlocks+1)*sizeof(int)); 
	for(int i = 0; i < N/2; i++)
		valid[i] = 1;
	
	char* data;
	cudaMallocManaged(&data,FILESIZE_CHAR*sizeof(char));
	memset(data,0,FILESIZE_CHAR*sizeof(char));
	file.read(data, FILESIZE_CHAR*sizeof(char));
	file.close();
	
	int* idata;
	cudaMallocManaged(&idata,FILESIZE_CHAR*sizeof(char));
	memcpy(idata, data, FILESIZE_CHAR*sizeof(char));
	
	char* output;
	cudaMallocManaged(&output,FILESIZE_CHAR*sizeof(char));
	memset(output,0,FILESIZE_CHAR*sizeof(char));
	
	benes<<<numBlocks,blockSize>>>(N, blocks, network, LUT, valid, mask, idata, output);
	cudaDeviceSynchronize();

	// printf("The input is:");
	// for (int i = 0; i < FILESIZE_INT; i++){
		// if (i%N == 0) printf("\n");
		// printf("%d ", idata[i]);
	// }
	// printf("\n\n");

  
	for (int i = 0; i < FILESIZE_INT-1; i++){
		if ((i%N != N-1) && (output[i+1]!=0)) {
				if((mask & output[i+1]) < (mask & output[i])){
						printf("ERROR in routing at output %d %d %d\n",i ,mask & output[i+1],mask &output[i] );
						return 1;
				}
		}
}
printf("Routing was successful!\n");
   
	cudaFree(valid);
	cudaFree(LUT);
	cudaFree(network);
	cudaFree(data);
	cudaFree(idata);
	cudaFree(output);
}
 
 

	.file	"tmpxft_00282c88_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6968:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6968:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7makeLUTiPi
	.type	_Z7makeLUTiPi, @function
_Z7makeLUTiPi:
.LFB6963:
	.cfi_startproc
	endbr64
	cvtsi2sdl	%edi, %xmm1
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movaps	%xmm1, %xmm0
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movsd	%xmm1, (%rsp)
	call	log2@PLT
	movl	$2, %ecx
	xorl	%r11d, %r11d
	addsd	%xmm0, %xmm0
	subsd	.LC0(%rip), %xmm0
	mulsd	(%rsp), %xmm0
	cvttsd2sil	%xmm0, %edi
	movl	%edi, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %ecx
	movl	%eax, (%rsp)
	movl	%eax, %r8d
	movslq	%ebx, %rax
	movq	%rax, 24(%rsp)
.L3:
	cmpl	%r12d, (%rsp)
	jle	.L8
	movl	%ecx, %eax
	movl	$2, %esi
	leaq	0(%rbp,%r11,4), %r9
	movl	$1, %r13d
	cltd
	idivl	%esi
	movslq	%ecx, %rdx
	leaq	0(,%rdx,4), %rsi
	xorl	%edx, %edx
	movq	%rsi, 16(%rsp)
	testl	%eax, %eax
	cmovns	%eax, %edx
	leal	(%rdx,%rdx), %esi
	movl	%ecx, %edx
	subl	%eax, %edx
	movl	%esi, 12(%rsp)
	xorl	%esi, %esi
	addl	%edx, %edx
	cmpl	%ecx, %eax
	cmovle	%edx, %esi
	xorl	%r14d, %r14d
	xorl	%r10d, %r10d
.L9:
	cmpl	%ebx, %r14d
	jge	.L17
	xorl	%edx, %edx
.L7:
	leal	(%r10,%rdx,2), %r15d
	cmpl	%edx, %eax
	jle	.L18
	movl	%r15d, (%r9,%rdx,4)
	incq	%rdx
	jmp	.L7
.L18:
	movl	12(%rsp), %edx
	movl	%r13d, %r15d
	addl	%edx, %r10d
	movslq	%eax, %rdx
.L5:
	cmpl	%edx, %ecx
	jle	.L19
	movl	%r15d, (%r9,%rdx,4)
	addl	$2, %r15d
	incq	%rdx
	jmp	.L5
.L19:
	movq	16(%rsp), %rdx
	addl	%esi, %r13d
	addl	%ecx, %r14d
	addq	%rdx, %r9
	jmp	.L9
.L17:
	movq	24(%rsp), %rcx
	addl	%ebx, %r12d
	addq	%rcx, %r11
	movl	%eax, %ecx
	jmp	.L3
.L8:
	movl	%edi, %edx
	movslq	(%rsp), %rsi
	movl	%ebx, %eax
	subl	%ebx, %edx
	negl	%eax
	movslq	%edx, %rdx
	cltq
	subq	%rsi, %rdx
	salq	$2, %rax
	leaq	0(%rbp,%rdx,4), %rcx
.L10:
	cmpl	%edi, %r8d
	jge	.L20
	movq	%rcx, %rsi
	xorl	%edx, %edx
.L12:
	cmpl	%ebx, %edx
	jge	.L21
	movl	(%rsi), %r9d
	addq	$4, %rsi
	addl	%r8d, %r9d
	movslq	%r9d, %r9
	movl	%edx, 0(%rbp,%r9,4)
	incl	%edx
	jmp	.L12
.L21:
	addl	%ebx, %r8d
	addq	%rax, %rcx
	jmp	.L10
.L20:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6963:
	.size	_Z7makeLUTiPi, .-_Z7makeLUTiPi
	.globl	_Z10createMaski
	.type	_Z10createMaski, @function
_Z10createMaski:
.LFB6964:
	.cfi_startproc
	endbr64
	xorl	%ecx, %ecx
	xorl	%eax, %eax
	movl	$1, %edx
.L23:
	cmpl	%edi, %ecx
	jge	.L25
	movl	%edx, %esi
	sall	%cl, %esi
	incl	%ecx
	orl	%esi, %eax
	jmp	.L23
.L25:
	ret
	.cfi_endproc
.LFE6964:
	.size	_Z10createMaski, .-_Z10createMaski
	.globl	_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_
	.type	_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_, @function
_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_:
.LFB6990:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movl	%r9d, 28(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z5benesiiPcPiPViiS0_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L26:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6990:
	.size	_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_, .-_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_
	.globl	_Z5benesiiPcPiPViiS0_S_
	.type	_Z5benesiiPcPiPViiS0_S_, @function
_Z5benesiiPcPiPViiS0_S_:
.LFB6991:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_
	.cfi_endproc
.LFE6991:
	.size	_Z5benesiiPcPiPViiS0_S_, .-_Z5benesiiPcPiPViiS0_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z5benesiiPcPiPViiS0_S_"
.LC2:
	.string	"_ZN37_INTERNAL_9a227ec7_7_main_cu_c848ebe24cuda3std3__419piecewise_constructE"
.LC3:
	.string	"_ZN37_INTERNAL_9a227ec7_7_main_cu_c848ebe24cuda3std6ranges3__45__cpo4swapE"
.LC4:
	.string	"_ZN37_INTERNAL_9a227ec7_7_main_cu_c848ebe24cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6993:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5benesiiPcPiPViiS0_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6993:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata.str1.1
.LC5:
	.string	"Usage: %s <input.txt> <size>\n"
.LC6:
	.string	"Could not open input file\n"
.LC8:
	.string	"ERROR in routing at output %d %d %d\n"
.LC9:
	.string	"Routing was successful!\n"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB6965:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA6965
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$648, %rsp
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	cmpl	$3, %edi
	je	.L34
	movq	(%rsi), %rdx
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
.LEHB0:
	call	__printf_chk@PLT
	movl	$1, -668(%rbp)
	jmp	.L33
.L34:
	leaq	-576(%rbp), %rax
	movq	8(%rsi), %rsi
	movl	$4, %edx
	movq	%rax, %rdi
	movq	%rax, -664(%rbp)
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
	movl	-288(%rbp), %eax
	andl	$5, %eax
	movl	%eax, -668(%rbp)
	je	.L36
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
.LEHB1:
	call	__printf_chk@PLT
.L45:
	movl	$1, -668(%rbp)
	jmp	.L37
.L36:
	movq	16(%rbx), %rdi
	movl	$262144, %ebx
	call	atoi@PLT
	movl	$2, %esi
	cmpl	%ebx, %eax
	movl	%eax, %r12d
	cmovle	%eax, %ebx
	movl	%ebx, %eax
	cvtsi2sdl	%ebx, %xmm1
	cltd
	idivl	%esi
	movsd	%xmm1, -680(%rbp)
	movaps	%xmm1, %xmm0
	movl	%eax, %r14d
	call	log2@PLT
	addsd	%xmm0, %xmm0
	subsd	.LC7(%rip), %xmm0
	cvttsd2sil	%xmm0, %r15d
	cvtsi2sdl	%ebx, %xmm0
	movl	%r15d, %r13d
	call	log2@PLT
	cvtsi2sdl	%ebx, %xmm0
	call	log2@PLT
	addsd	%xmm0, %xmm0
	subsd	.LC0(%rip), %xmm0
	mulsd	-680(%rbp), %xmm0
	cvttsd2sil	%xmm0, %eax
	movl	%eax, -680(%rbp)
	cmpl	$262143, %r12d
	jg	.L38
	leal	(%r15,%r15), %r13d
.L38:
	leal	1(%r13), %eax
	leaq	-648(%rbp), %rdi
	movl	$1, %edx
	imull	%ebx, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, %r12
	call	cudaMallocManaged@PLT
	movq	-648(%rbp), %rdi
	xorl	%eax, %eax
	movq	%r12, %rcx
	movslq	-680(%rbp), %rsi
	movl	$1, %edx
	rep stosb
	salq	$2, %rsi
	leaq	-640(%rbp), %rdi
	call	cudaMallocManaged@PLT
	movq	-640(%rbp), %rsi
	movl	%ebx, %edi
	call	_Z7makeLUTiPi
	cvtsi2sdl	%ebx, %xmm0
	call	log2@PLT
	cvttsd2sil	%xmm0, %edi
	call	_Z10createMaski
	leaq	-632(%rbp), %rdi
	movl	$1, %edx
	movl	%eax, %r12d
	movl	%r13d, %eax
	imull	%r14d, %eax
	movslq	%eax, %rsi
	movl	%eax, -680(%rbp)
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	-680(%rbp), %ecx
	movq	-632(%rbp), %rdi
	xorl	%eax, %eax
	addl	%r14d, %ecx
	movslq	%ecx, %rcx
	salq	$2, %rcx
	rep stosb
	xorl	%eax, %eax
	movq	-632(%rbp), %rdx
.L39:
	cmpl	%eax, %r14d
	jle	.L59
	movl	$1, (%rdx,%rax,4)
	incq	%rax
	jmp	.L39
.L59:
	leaq	-624(%rbp), %rdi
	movl	$1, %edx
	movl	$1048576, %esi
	call	cudaMallocManaged@PLT
	movq	-624(%rbp), %rsi
	movl	$262144, %ecx
	xorl	%eax, %eax
	movl	$1048576, %edx
	movq	%rsi, %rdi
	rep stosl
	movq	-664(%rbp), %rdi
	call	_ZNSi4readEPcl@PLT
	movq	-664(%rbp), %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
	leaq	-616(%rbp), %rdi
	movl	$1, %edx
	movl	$1048576, %esi
	call	cudaMallocManaged@PLT
	movq	-624(%rbp), %rsi
	movl	$262144, %ecx
	movl	$1, %edx
	movq	-616(%rbp), %rdi
	rep movsl
	leaq	-608(%rbp), %rdi
	movl	$1048576, %esi
	call	cudaMallocManaged@PLT
	movq	-608(%rbp), %rdi
	xorl	%eax, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$262144, %ecx
	movl	%r14d, -588(%rbp)
	rep stosl
	movl	%r13d, -600(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -584(%rbp)
	movl	-580(%rbp), %ecx
	movq	%rax, -596(%rbp)
	movq	-588(%rbp), %rdx
	movq	-600(%rbp), %rdi
	movl	-592(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L41
.L43:
	call	cudaDeviceSynchronize@PLT
	movq	-608(%rbp), %r9
	xorl	%esi, %esi
	leal	-1(%rbx), %r10d
	jmp	.L46
.L41:
	pushq	-608(%rbp)
	movl	%r12d, %r9d
	movl	%r15d, %esi
	movl	%ebx, %edi
	movq	-648(%rbp), %rdx
	pushq	-616(%rbp)
	movq	-632(%rbp), %r8
	movq	-640(%rbp), %rcx
	.cfi_escape 0x2e,0x10
	call	_Z37__device_stub__Z5benesiiPcPiPViiS0_S_iiPcPiPViiS0_S_
	popq	%rax
	popq	%rdx
	jmp	.L43
.L62:
	movsbl	1(%r9,%rsi), %ecx
	testb	%cl, %cl
	jne	.L60
.L44:
	incq	%rsi
	cmpq	$262143, %rsi
	je	.L61
.L46:
	movl	%esi, %eax
	cltd
	idivl	%ebx
	cmpl	%r10d, %edx
	jne	.L62
	jmp	.L44
.L60:
	movsbl	(%r9,%rsi), %r8d
	andl	%r12d, %ecx
	andl	%r12d, %r8d
	cmpl	%r8d, %ecx
	jge	.L44
	movl	%esi, %edx
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	xorl	%eax, %eax
	.cfi_escape 0x2e,0
	call	__printf_chk@PLT
	jmp	.L45
.L61:
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	-632(%rbp), %rdi
	call	cudaFree@PLT
	movq	-640(%rbp), %rdi
	call	cudaFree@PLT
	movq	-648(%rbp), %rdi
	call	cudaFree@PLT
	movq	-624(%rbp), %rdi
	call	cudaFree@PLT
	movq	-616(%rbp), %rdi
	call	cudaFree@PLT
	movq	-608(%rbp), %rdi
	call	cudaFree@PLT
.LEHE1:
.L37:
	movq	-664(%rbp), %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
	jmp	.L33
.L51:
	endbr64
	movq	%rax, %rbx
.L47:
	movq	-664(%rbp), %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	jne	.L58
	movq	%rbx, %rdi
.LEHB2:
	call	_Unwind_Resume@PLT
.LEHE2:
.L33:
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L49
.L58:
	call	__stack_chk_fail@PLT
.L49:
	movl	-668(%rbp), %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6965:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA6965:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE6965-.LLSDACSB6965
.LLSDACSB6965:
	.uleb128 .LEHB0-.LFB6965
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB6965
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L51-.LFB6965
	.uleb128 0
	.uleb128 .LEHB2-.LFB6965
	.uleb128 .LEHE2-.LEHB2
	.uleb128 0
	.uleb128 0
.LLSDACSE6965:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1073741824
	.align 8
.LC7:
	.long	0
	.long	1072693248
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//put C:/Users/molly/Desktop/289Q/project/main.cu
//nvcc -std=c++11 main.cu

// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <fstream>
#include <hip/hip_cooperative_groups.h>
#include <hip/hip_cooperative_groups.h>
// includes, project
#include <hip/hip_runtime.h>


using namespace cooperative_groups;
namespace cg = cooperative_groups;

// #define FILESIZE_CHAR 1048576
#define FILESIZE_CHAR 1048576
#define FILESIZE_INT FILESIZE_CHAR/4


__host__
void makeLUT(int N, int* LUT){
	int M = N;
	int even = 0;
	int odd = 1;
	int LUTsize = N*(log2((double)N)*2 - 2);
	for (int i =0; i < LUTsize/2; i+=N){
		for (int j=0; j<N; j+=M){
			for (int k =0; k<M/2; k++){
				LUT[i+j+k] = even;
				even+=2;
			}
			for (int k =M/2; k<M; k++){
				LUT[i+j+k] = odd;
				odd+=2;
			}
		} even=0; odd=1; M = M/2;
	}
	for (int x=LUTsize-N, i=LUTsize/2; i<LUTsize;i+=N, x-=N){
		for(int j=0; j<N; j++){
			int newIndex = LUT[x+j-LUTsize/2];
			LUT[newIndex + i] = j;
		}
	}
	return;
}

int createMask(int n)
{
   int r = 0;
   for (int i=0; i<n; i++)
       r |= 1 << i;

   return r;
}


__global__
void benes(int N, int block, char* network, int* LUT, volatile int* valid, int mask, int* data, char* output){
	int idx = threadIdx.x;
	int in1, in2, in1_index, in2_index;
	int readOffset=0;
	int fileSize = FILESIZE_INT/2;
	int readOffsetSecondNet=fileSize;
	thread_group g = tiled_partition(this_thread_block(), 2); //stops working after 32?
		if(blockIdx.x == 0){
			while(readOffset < fileSize){
				in1 = data[idx*2 + readOffset];
				in2 = data[idx*2+1 + readOffset];
				readOffset+=N;
				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
				network[idx*2 + (blockIdx.x+1)*N] = in1;  
				network[idx*2 + (blockIdx.x+1)*N + 1] = in2;
				
				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;  
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;
				}
				g.sync();
				// __syncthreads();
				valid[idx + (blockIdx.x+1)*(N/2)]=1;// valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
				
			}
		}
		
		else if ( blockIdx.x < block) {
			while(readOffset < fileSize){
				while((valid[idx + (blockIdx.x)*(N/2)])==0);
				in1_index = LUT[idx*2 + (blockIdx.x-1)*N];
				in2_index = LUT[idx*2 + (blockIdx.x-1)*N + 1];
				in1 = network[in1_index+(blockIdx.x)*N];
				in2 = network[in2_index+(blockIdx.x)*N];
				valid[idx + (blockIdx.x)*(N/2)] = 0;// valid[idx*2 + 1 + (blockIdx.x)*N] = 0;
			

				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
				network[idx*2 + (blockIdx.x+1)*N] = in1;
				network[idx*2 + (blockIdx.x+1)*N + 1] = in2;

				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;  
				}
				
				if (blockIdx.x != gridDim.x - 1 && blockIdx.x != block-1){
					valid[idx + (blockIdx.x+1)*(N/2)]=1;// valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
					g.sync();
					// __syncthreads();
				}
				else {
					output[idx*2 + readOffset] = network[idx*2 + (blockIdx.x+1)*N];
					output[idx*2+1 + readOffset] = network[idx*2 + (blockIdx.x+1)*N + 1];
				}
				readOffset += N;
			}
		} 



		else if(blockIdx.x == block){
			while(readOffsetSecondNet < FILESIZE_INT){
				in1 = data[idx*2 + readOffsetSecondNet];
				in2 = data[idx*2+1 + readOffsetSecondNet];
				readOffsetSecondNet+=N;
				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
					network[idx*2 + (blockIdx.x+1)*N] = in1;  
					network[idx*2 + (blockIdx.x+1)*N + 1] = in2;
				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;  
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;
				}

				
				valid[idx + (blockIdx.x+1)*(N/2)]=1;// valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
				// __syncthreads();
				g.sync();
			}
		}
		
		else{
			while(readOffsetSecondNet < FILESIZE_INT){
				// printf("waiting for previous block %d to produce\n", blockIdx.x - 1);
				while((valid[idx + (blockIdx.x)*(N/2)])==0);
				
				// printf("waiting for previous block %d to produce\n", blockIdx.x - 1);
				in1_index = LUT[idx*2 + ((blockIdx.x%block)-1)*N];
				in2_index = LUT[idx*2 + ((blockIdx.x%block)-1)*N + 1];
				in1 = network[in1_index+(blockIdx.x)*N];
				in2 = network[in2_index+(blockIdx.x)*N];
				
				// printf("Block %d thread %d consumed %d %d\n", blockIdx.x,threadIdx.x, in1, in2);
				valid[idx + (blockIdx.x)*(N/2)] = 0; //valid[idx*2 + 1 + (blockIdx.x)*N] = 0;
			
				//printf("waiting for next block %d to consume\n", blockIdx.x + 1);
				while((valid[idx + (blockIdx.x+1)*(N/2)])==1);
				if ((in1 & mask) < (in2 & mask)){
					network[idx*2 + (blockIdx.x+1)*N] = in1;
					network[idx*2 + (blockIdx.x+1)*N + 1] = in2;
					// printf("Block %d produced %d %d\n", blockIdx.x, in1, in2);
				}
				else{
					network[idx*2 + (blockIdx.x+1)*N] = in2;
					network[idx*2 + (blockIdx.x+1)*N + 1] = in1;  
				}
				//printf("Block %d produced %d %d\n", blockIdx.x, in1, in2);
				if (blockIdx.x != gridDim.x - 1){
					valid[idx + (blockIdx.x+1)*(N/2)]=1; //valid[idx*2 + 1 + (blockIdx.x+1)*N]=1;
					// __syncthreads();
					g.sync();
					//printf("valid:%d index:%d\n",valid[idx + (blockIdx.x+1)*N],idx + (blockIdx.x+1)*N);
				}
				else {
					output[idx*2 + readOffsetSecondNet] = network[idx*2 + (blockIdx.x+1)*N];
					output[idx*2+1 + readOffsetSecondNet] = network[idx*2 + (blockIdx.x+1)*N + 1];
				}
				readOffsetSecondNet += N;
			}
		}
}



int main(int argc, char *argv[]){
	
	if (argc != 3){
		printf("Usage: %s <input.txt> <size>\n", argv[0]);
		return 1;
	}
	
	std::ifstream file(argv[1], std::ios::binary);
	if (!file) {
        printf("Could not open input file\n");
        return 1;
    }

	
	int N = atoi(argv[2]);
	if (FILESIZE_INT<N)
		N = FILESIZE_INT;
	int blockSize = N/2; 
	int blocks = 2*log2((double)N)-1; 
	int b = 2*log2((double)N)-1;
	int LUTsize = N*(log2((double)N)*2 - 2);
	int numBlocks;

	if (FILESIZE_INT <= N)
		numBlocks = blocks;
	else
		numBlocks = 2*blocks;

	char* network;
	hipMallocManaged(&network,N*(numBlocks+1)*sizeof(char));
	memset(network,0,N*(numBlocks+1)*sizeof(char));

	
	int* LUT;
	hipMallocManaged(&LUT,LUTsize*sizeof(int));
	makeLUT(N,LUT);
	int mask = createMask(log2((double)N));
  
    int *valid;
	hipMallocManaged(&valid,(N/2)*(numBlocks)*sizeof(int));
	memset(valid,0,(N/2)*(numBlocks+1)*sizeof(int)); 
	for(int i = 0; i < N/2; i++)
		valid[i] = 1;
	
	char* data;
	hipMallocManaged(&data,FILESIZE_CHAR*sizeof(char));
	memset(data,0,FILESIZE_CHAR*sizeof(char));
	file.read(data, FILESIZE_CHAR*sizeof(char));
	file.close();
	
	int* idata;
	hipMallocManaged(&idata,FILESIZE_CHAR*sizeof(char));
	memcpy(idata, data, FILESIZE_CHAR*sizeof(char));
	
	char* output;
	hipMallocManaged(&output,FILESIZE_CHAR*sizeof(char));
	memset(output,0,FILESIZE_CHAR*sizeof(char));
	
	benes<<<numBlocks,blockSize>>>(N, blocks, network, LUT, valid, mask, idata, output);
	hipDeviceSynchronize();

	// printf("The input is:");
	// for (int i = 0; i < FILESIZE_INT; i++){
		// if (i%N == 0) printf("\n");
		// printf("%d ", idata[i]);
	// }
	// printf("\n\n");

  
	for (int i = 0; i < FILESIZE_INT-1; i++){
		if ((i%N != N-1) && (output[i+1]!=0)) {
				if((mask & output[i+1]) < (mask & output[i])){
						printf("ERROR in routing at output %d %d %d\n",i ,mask & output[i+1],mask &output[i] );
						return 1;
				}
		}
}
printf("Routing was successful!\n");
   
	hipFree(valid);
	hipFree(LUT);
	hipFree(network);
	hipFree(data);
	hipFree(idata);
	hipFree(output);
}
 
 

	.text
	.file	"main.hip"
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7makeLUTiPi
.LCPI0_0:
	.quad	0xc000000000000000              # double -2
	.text
	.globl	_Z7makeLUTiPi
	.type	_Z7makeLUTiPi,@function
_Z7makeLUTiPi:                          # @_Z7makeLUTiPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
	cvtsi2sd	%edi, %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	callq	log2
	addsd	%xmm0, %xmm0
	addsd	.LCPI0_0(%rip), %xmm0
	mulsd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	cvttsd2si	%xmm0, %eax
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	sarl	%ecx
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movl	%eax, 24(%rsp)                  # 4-byte Spill
	cmpl	$2, %eax
	jl	.LBB0_10
# %bb.1:                                # %.preheader68.lr.ph
	movslq	%ebp, %rdx
	movl	12(%rsp), %eax                  # 4-byte Reload
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leaq	(,%rdx,4), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movl	%ebp, %r11d
	movl	%ebp, %r10d
	movl	%ebp, 28(%rsp)                  # 4-byte Spill
.LBB0_2:                                # %.preheader68
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_6 Depth 3
                                        #       Child Loop BB0_17 Depth 3
	shrl	$31, %r10d
	addl	%r11d, %r10d
	sarl	%r10d
	testl	%ebp, %ebp
	jle	.LBB0_9
# %bb.3:                                # %.preheader67.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movslq	%r10d, %r14
	movslq	%r11d, %r15
	movl	%r14d, %r12d
	leaq	(,%r15,4), %r13
	movl	$1, %eax
	xorl	%esi, %esi
	movq	%rdi, %r9
	xorl	%ebp, %ebp
.LBB0_4:                                # %.preheader67
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_6 Depth 3
                                        #       Child Loop BB0_17 Depth 3
	cmpl	$2, %r11d
	jl	.LBB0_7
# %bb.5:                                # %.lr.ph
                                        #   in Loop: Header=BB0_4 Depth=2
	xorl	%ecx, %ecx
.LBB0_6:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%ebp, (%r9,%rcx,4)
	addl	$2, %ebp
	incq	%rcx
	cmpq	%rcx, %r12
	jne	.LBB0_6
.LBB0_7:                                # %.preheader66
                                        #   in Loop: Header=BB0_4 Depth=2
	movq	%r14, %rcx
	cmpl	%r11d, %r10d
	jge	.LBB0_8
.LBB0_17:                               #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%eax, (%r9,%rcx,4)
	addl	$2, %eax
	incq	%rcx
	cmpq	%rcx, %r15
	jne	.LBB0_17
.LBB0_8:                                # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=2
	addq	%r15, %rsi
	addq	%r13, %r9
	cmpq	%rdx, %rsi
	jl	.LBB0_4
.LBB0_9:                                # %._crit_edge80
                                        #   in Loop: Header=BB0_2 Depth=1
	addq	%rdx, %r8
	addq	32(%rsp), %rdi                  # 8-byte Folded Reload
	movl	%r10d, %r11d
	cmpq	16(%rsp), %r8                   # 8-byte Folded Reload
	movl	28(%rsp), %ebp                  # 4-byte Reload
	jl	.LBB0_2
.LBB0_10:                               # %.preheader65
	movl	24(%rsp), %r9d                  # 4-byte Reload
	movl	%r9d, %eax
	movl	12(%rsp), %r10d                 # 4-byte Reload
	subl	%r10d, %eax
	jle	.LBB0_16
# %bb.11:                               # %.preheader.lr.ph
	movl	%ebp, %edx
	subl	%ebp, %eax
	movl	%ebp, %esi
	negl	%esi
.LBB0_12:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_14 Depth 2
	testl	%ebp, %ebp
	jle	.LBB0_15
# %bb.13:                               # %.lr.ph85
                                        #   in Loop: Header=BB0_12 Depth=1
	movslq	%r10d, %rdi
	xorl	%r8d, %r8d
.LBB0_14:                               #   Parent Loop BB0_12 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rax,%r8), %ecx
	movslq	%ecx, %rcx
	movslq	(%rbx,%rcx,4), %rcx
	addq	%rdi, %rcx
	movl	%r8d, (%rbx,%rcx,4)
	incq	%r8
	cmpq	%r8, %rdx
	jne	.LBB0_14
.LBB0_15:                               # %._crit_edge86
                                        #   in Loop: Header=BB0_12 Depth=1
	addl	%ebp, %r10d
	addq	%rsi, %rax
	cmpl	%r9d, %r10d
	jl	.LBB0_12
.LBB0_16:                               # %._crit_edge90
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7makeLUTiPi, .Lfunc_end0-_Z7makeLUTiPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z10createMaski                 # -- Begin function _Z10createMaski
	.type	_Z10createMaski,@function
_Z10createMaski:                        # @_Z10createMaski
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jle	.LBB1_1
# %bb.3:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
	xorl	%eax, %eax
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	btsl	%ecx, %eax
	incl	%ecx
	cmpl	%ecx, %edi
	jne	.LBB1_4
# %bb.2:                                # %._crit_edge
	retq
.LBB1_1:
	xorl	%eax, %eax
	retq
.Lfunc_end1:
	.size	_Z10createMaski, .Lfunc_end1-_Z10createMaski
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__benesiiPcPiPViiS0_S_ # -- Begin function _Z20__device_stub__benesiiPcPiPViiS0_S_
	.type	_Z20__device_stub__benesiiPcPiPViiS0_S_,@function
_Z20__device_stub__benesiiPcPiPViiS0_S_: # @_Z20__device_stub__benesiiPcPiPViiS0_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5benesiiPcPiPViiS0_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__benesiiPcPiPViiS0_S_, .Lfunc_end2-_Z20__device_stub__benesiiPcPiPViiS0_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0xbff0000000000000              # double -1
.LCPI3_1:
	.quad	0xc000000000000000              # double -2
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$600, %rsp                      # imm = 0x258
	.cfi_def_cfa_offset 656
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	cmpl	$3, %edi
	jne	.LBB3_1
# %bb.2:
	movq	8(%rbx), %rsi
	.cfi_escape 0x2e, 0x00
	leaq	80(%rsp), %r14
	movq	%r14, %rdi
	movl	$4, %edx
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
	movq	(%r14), %rax
	movq	-24(%rax), %rax
	testb	$5, 112(%rsp,%rax)
	je	.LBB3_4
# %bb.3:
	.cfi_escape 0x2e, 0x00
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB3_39:
	movl	$1, %ebx
	jmp	.LBB3_40
.LBB3_1:
	movq	(%rbx), %rsi
	.cfi_escape 0x2e, 0x00
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %ebx
	jmp	.LBB3_41
.LBB3_4:
	movq	16(%rbx), %rdi
	.cfi_escape 0x2e, 0x00
	callq	atoi
	movl	%eax, %r15d
	movl	$262144, %ebx                   # imm = 0x40000
	cmpl	%ebx, %eax
	cmovll	%eax, %ebx
	setl	%bpl
	cvtsi2sd	%ebx, %xmm0
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	.cfi_escape 0x2e, 0x00
	callq	log2
	addsd	%xmm0, %xmm0
	addsd	.LCPI3_0(%rip), %xmm0
	cvttsd2si	%xmm0, %r14d
	.cfi_escape 0x2e, 0x00
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	log2
	.cfi_escape 0x2e, 0x00
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	log2
	movsd	%xmm0, 72(%rsp)                 # 8-byte Spill
	movl	%r14d, 60(%rsp)                 # 4-byte Spill
	movl	%r14d, %eax
	movl	%ebp, %ecx
	shll	%cl, %eax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	leal	1(%rax), %r14d
	movl	%r14d, %eax
	imull	%ebx, %eax
	movslq	%eax, %r12
.Ltmp0:
	.cfi_escape 0x2e, 0x00
	leaq	48(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
.Ltmp1:
# %bb.5:                                # %_ZL16hipMallocManagedIcE10hipError_tPPT_mj.exit
	movsd	72(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	addsd	.LCPI3_1(%rip), %xmm0
	mulsd	(%rsp), %xmm0                   # 8-byte Folded Reload
	cvttsd2si	%xmm0, %r13d
	movq	48(%rsp), %rdi
	.cfi_escape 0x2e, 0x00
	xorl	%ebp, %ebp
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	memset@PLT
	movslq	%r13d, %rsi
	shlq	$2, %rsi
.Ltmp3:
	.cfi_escape 0x2e, 0x00
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
.Ltmp4:
# %bb.6:                                # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit
	movl	%ebx, %r12d
	shrl	$31, %r12d
	addl	%ebx, %r12d
	sarl	%r12d
	movq	40(%rsp), %rsi
	.cfi_escape 0x2e, 0x00
	movl	%ebx, %edi
	callq	_Z7makeLUTiPi
	.cfi_escape 0x2e, 0x00
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	log2
	cvttsd2si	%xmm0, %eax
	testl	%eax, %eax
	movq	64(%rsp), %r13                  # 8-byte Reload
	jle	.LBB3_9
# %bb.7:                                # %.lr.ph.i.preheader
	xorl	%ecx, %ecx
	xorl	%ebp, %ebp
.LBB3_8:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	btsl	%ecx, %ebp
	incl	%ecx
	cmpl	%ecx, %eax
	jne	.LBB3_8
.LBB3_9:                                # %_Z10createMaski.exit
	movl	%r13d, %eax
	imull	%r12d, %eax
	movslq	%eax, %rsi
	shlq	$2, %rsi
.Ltmp6:
	.cfi_escape 0x2e, 0x00
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
.Ltmp7:
# %bb.10:                               # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit80
	movq	16(%rsp), %rdi
	imull	%r12d, %r14d
	movslq	%r14d, %rdx
	shlq	$2, %rdx
	.cfi_escape 0x2e, 0x00
	xorl	%esi, %esi
	callq	memset@PLT
	cmpl	$2, %r15d
	jl	.LBB3_13
# %bb.11:                               # %.lr.ph
	movq	16(%rsp), %rax
	cmpl	$2, %r12d
	movl	$1, %ecx
	cmovgel	%r12d, %ecx
	xorl	%edx, %edx
.LBB3_12:                               # =>This Inner Loop Header: Depth=1
	movl	$1, (%rax,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB3_12
.LBB3_13:                               # %._crit_edge
.Ltmp9:
	.cfi_escape 0x2e, 0x00
	leaq	32(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	movl	$1, %edx
	callq	hipMallocManaged
.Ltmp10:
# %bb.14:                               # %_ZL16hipMallocManagedIcE10hipError_tPPT_mj.exit81
	movq	32(%rsp), %r15
	.cfi_escape 0x2e, 0x00
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp11:
	.cfi_escape 0x2e, 0x00
	leaq	80(%rsp), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r15, %rsi
	callq	_ZNSi4readEPcl
.Ltmp12:
# %bb.15:
.Ltmp13:
	.cfi_escape 0x2e, 0x00
	leaq	80(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv
.Ltmp14:
# %bb.16:
.Ltmp16:
	.cfi_escape 0x2e, 0x00
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	movl	$1, %edx
	callq	hipMallocManaged
.Ltmp17:
# %bb.17:                               # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit82
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	.cfi_escape 0x2e, 0x00
	movl	$1048576, %edx                  # imm = 0x100000
	callq	memcpy@PLT
.Ltmp19:
	.cfi_escape 0x2e, 0x00
	leaq	8(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	movl	$1, %edx
	callq	hipMallocManaged
.Ltmp20:
# %bb.18:                               # %_ZL16hipMallocManagedIcE10hipError_tPPT_mj.exit83
	movq	8(%rsp), %rdi
	.cfi_escape 0x2e, 0x00
	movl	$1048576, %edx                  # imm = 0x100000
	xorl	%esi, %esi
	callq	memset@PLT
	movl	%r13d, %edi
	btsq	$32, %rdi
	movl	%r12d, %edx
	btsq	$32, %rdx
.Ltmp21:
	.cfi_escape 0x2e, 0x00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp22:
# %bb.19:
	testl	%eax, %eax
	jne	.LBB3_21
# %bb.20:
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	16(%rsp), %r8
.Ltmp23:
	.cfi_escape 0x2e, 0x10
	movl	%ebx, %edi
	movl	60(%rsp), %esi                  # 4-byte Reload
	movl	%ebp, %r9d
	pushq	8(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z20__device_stub__benesiiPcPiPViiS0_S_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.Ltmp24:
.LBB3_21:
.Ltmp25:
	.cfi_escape 0x2e, 0x00
	callq	hipDeviceSynchronize
.Ltmp26:
# %bb.22:                               # %.preheader
	leal	-1(%rbx), %edi
	movq	8(%rsp), %r8
	xorl	%esi, %esi
.LBB3_23:                               # =>This Inner Loop Header: Depth=1
	movl	%esi, %eax
	cltd
	idivl	%ebx
	cmpl	%edi, %edx
	je	.LBB3_26
# %bb.24:                               #   in Loop: Header=BB3_23 Depth=1
	movsbl	1(%r8,%rsi), %edx
	testl	%edx, %edx
	je	.LBB3_26
# %bb.25:                               #   in Loop: Header=BB3_23 Depth=1
	andl	%ebp, %edx
	movsbl	(%r8,%rsi), %ecx
	andl	%ebp, %ecx
	cmpl	%ecx, %edx
	jl	.LBB3_38
.LBB3_26:                               #   in Loop: Header=BB3_23 Depth=1
	incq	%rsi
	cmpq	$262143, %rsi                   # imm = 0x3FFFF
	jne	.LBB3_23
# %bb.27:
	.cfi_escape 0x2e, 0x00
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	16(%rsp), %rdi
.Ltmp27:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp28:
# %bb.28:
	movq	40(%rsp), %rdi
.Ltmp29:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp30:
# %bb.29:
	movq	48(%rsp), %rdi
.Ltmp31:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp32:
# %bb.30:
	movq	32(%rsp), %rdi
.Ltmp33:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp34:
# %bb.31:
	movq	24(%rsp), %rdi
.Ltmp35:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp36:
# %bb.32:
	xorl	%ebx, %ebx
	movq	8(%rsp), %rdi
.Ltmp37:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp38:
.LBB3_40:
	.cfi_escape 0x2e, 0x00
	leaq	80(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.LBB3_41:
	movl	%ebx, %eax
	addq	$600, %rsp                      # imm = 0x258
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_38:
	.cfi_def_cfa_offset 656
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.2, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB3_39
.LBB3_42:
.Ltmp18:
	jmp	.LBB3_43
.LBB3_35:
.Ltmp8:
	jmp	.LBB3_43
.LBB3_34:
.Ltmp5:
	jmp	.LBB3_43
.LBB3_33:
.Ltmp2:
	jmp	.LBB3_43
.LBB3_36:
.Ltmp15:
	jmp	.LBB3_43
.LBB3_37:
.Ltmp39:
.LBB3_43:
	movq	%rax, %rbx
	.cfi_escape 0x2e, 0x00
	leaq	80(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
	.cfi_escape 0x2e, 0x00
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table3:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp1-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp1                  #   Call between .Ltmp1 and .Ltmp3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp7-.Lfunc_begin0           # >> Call Site 6 <<
	.uleb128 .Ltmp9-.Ltmp7                  #   Call between .Ltmp7 and .Ltmp9
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 7 <<
	.uleb128 .Ltmp10-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp10
	.uleb128 .Ltmp15-.Lfunc_begin0          #     jumps to .Ltmp15
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp10-.Lfunc_begin0          # >> Call Site 8 <<
	.uleb128 .Ltmp11-.Ltmp10                #   Call between .Ltmp10 and .Ltmp11
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp11-.Lfunc_begin0          # >> Call Site 9 <<
	.uleb128 .Ltmp14-.Ltmp11                #   Call between .Ltmp11 and .Ltmp14
	.uleb128 .Ltmp15-.Lfunc_begin0          #     jumps to .Ltmp15
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp16-.Lfunc_begin0          # >> Call Site 10 <<
	.uleb128 .Ltmp17-.Ltmp16                #   Call between .Ltmp16 and .Ltmp17
	.uleb128 .Ltmp18-.Lfunc_begin0          #     jumps to .Ltmp18
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp17-.Lfunc_begin0          # >> Call Site 11 <<
	.uleb128 .Ltmp19-.Ltmp17                #   Call between .Ltmp17 and .Ltmp19
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp19-.Lfunc_begin0          # >> Call Site 12 <<
	.uleb128 .Ltmp20-.Ltmp19                #   Call between .Ltmp19 and .Ltmp20
	.uleb128 .Ltmp39-.Lfunc_begin0          #     jumps to .Ltmp39
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp20-.Lfunc_begin0          # >> Call Site 13 <<
	.uleb128 .Ltmp21-.Ltmp20                #   Call between .Ltmp20 and .Ltmp21
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp21-.Lfunc_begin0          # >> Call Site 14 <<
	.uleb128 .Ltmp38-.Ltmp21                #   Call between .Ltmp21 and .Ltmp38
	.uleb128 .Ltmp39-.Lfunc_begin0          #     jumps to .Ltmp39
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp38-.Lfunc_begin0          # >> Call Site 15 <<
	.uleb128 .Lfunc_end3-.Ltmp38            #   Call between .Ltmp38 and .Lfunc_end3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5benesiiPcPiPViiS0_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5benesiiPcPiPViiS0_S_,@object # @_Z5benesiiPcPiPViiS0_S_
	.section	.rodata,"a",@progbits
	.globl	_Z5benesiiPcPiPViiS0_S_
	.p2align	3, 0x0
_Z5benesiiPcPiPViiS0_S_:
	.quad	_Z20__device_stub__benesiiPcPiPViiS0_S_
	.size	_Z5benesiiPcPiPViiS0_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Usage: %s <input.txt> <size>\n"
	.size	.L.str, 30

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"ERROR in routing at output %d %d %d\n"
	.size	.L.str.2, 37

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5benesiiPcPiPViiS0_S_"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Routing was successful!"
	.size	.Lstr, 24

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Could not open input file"
	.size	.Lstr.1, 26

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__benesiiPcPiPViiS0_S_
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z5benesiiPcPiPViiS0_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5benesiiPcPiPViiS0_S_ ; -- Begin function _Z5benesiiPcPiPViiS0_S_
	.globl	_Z5benesiiPcPiPViiS0_S_
	.p2align	8
	.type	_Z5benesiiPcPiPViiS0_S_,@function
_Z5benesiiPcPiPViiS0_S_:                ; @_Z5benesiiPcPiPViiS0_S_
; %bb.0:
	s_clause 0x4
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b128 s[8:11], s[0:1], 0x8
	s_load_b64 s[12:13], s[0:1], 0x18
	s_load_b32 s14, s[0:1], 0x20
	s_load_b128 s[4:7], s[0:1], 0x28
	s_cmp_lg_u32 s15, 0
	s_cbranch_scc0 .LBB0_32
; %bb.1:
	s_load_b32 s0, s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s3
	s_mov_b32 s1, -1
	s_cbranch_scc0 .LBB0_20
; %bb.2:
	s_cmp_eq_u32 s15, s3
	s_cbranch_scc1 .LBB0_14
; %bb.3:                                ; %.preheader254
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s17, 0, s3
	s_lshr_b32 s1, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s18, s2, s1
	v_rcp_iflag_f32_e32 v1, v1
	s_mul_i32 s1, s15, s2
	s_ashr_i32 s18, s18, 1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v2, v1
	v_lshlrev_b32_e32 v1, 1, v0
	v_readfirstlane_b32 s16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add3_u32 v6, s1, s2, v1
	v_mad_u64_u32 v[2:3], null, s18, s15, v[0:1]
	v_mov_b32_e32 v3, 0
	s_mul_i32 s17, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s17, s16, s17
	s_add_i32 s16, s16, s17
	v_add_co_u32 v4, s17, s8, v6
	s_mul_hi_u32 s16, s15, s16
	v_add_co_ci_u32_e64 v5, null, s9, 0, s17
	s_mul_i32 s16, s16, s3
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_nc_u32_e32 v2, s18, v2
	s_sub_i32 s16, s15, s16
	v_add_nc_u32_e32 v6, 1, v6
	s_sub_i32 s17, s16, s3
	s_cmp_ge_u32 s16, s3
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	s_cselect_b32 s16, s17, s16
	v_add_co_u32 v8, vcc_lo, s12, v8
	s_sub_i32 s17, s16, s3
	s_cmp_ge_u32 s16, s3
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
	s_cselect_b32 s16, s17, s16
	v_add_co_u32 v10, vcc_lo, s12, v10
	s_add_i32 s16, s16, -1
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	v_mad_u64_u32 v[14:15], null, s16, s2, v[1:2]
	v_mov_b32_e32 v15, v3
	v_mov_b32_e32 v13, v3
	v_add_co_u32 v6, s18, s8, v6
	s_add_i32 s16, s0, -1
	v_add_co_ci_u32_e64 v7, null, s9, 0, s18
	v_add_nc_u32_e32 v12, 1, v14
	v_lshlrev_b64 v[15:16], 2, v[14:15]
	v_mov_b32_e32 v2, 1
	s_cmp_lg_u32 s15, s16
	s_mov_b32 s17, 0x20000
	v_lshlrev_b64 v[17:18], 2, v[12:13]
	s_cselect_b32 s16, -1, 0
	v_add_co_u32 v12, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s10, v17
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v18, vcc_lo
.LBB0_4:                                ; %.preheader253
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
	s_mov_b32 s18, 0
.LBB0_5:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_b32 v16, v[8:9] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v16
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_clause 0x1
	global_load_b32 v16, v[12:13], off
	global_load_b32 v17, v[14:15], off
	s_mov_b32 s18, 0
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v16, s1, v16
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, s1, v17
	s_clause 0x1
	global_load_u8 v16, v16, s[8:9]
	global_load_u8 v17, v17, s[8:9]
	flat_store_b32 v[8:9], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_7:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_b32 v18, v[10:11] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 1, v18
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	v_bfe_i32 v18, v16, 0, 8
	v_bfe_i32 v19, v17, 0, 8
	s_mov_b32 s18, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, s14, v18
	v_and_b32_e32 v19, s14, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v18, v19
	v_cndmask_b32_e32 v18, v16, v17, vcc_lo
	v_cndmask_b32_e32 v16, v17, v16, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_clause 0x1
	global_store_b8 v[4:5], v16, off
	global_store_b8 v[6:7], v18, off
	s_cbranch_vccnz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s18, 0
	flat_store_b32 v[10:11], v2 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v17, s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_store_b8 v[17:18], v16, off
	global_load_u8 v16, v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[17:18], v16, off offset:1
.LBB0_12:                               ; %_ZNK18cooperative_groups12thread_group4syncEv.exit237
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_add_i32 s17, s17, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s17, 0x40000
	s_cbranch_scc1 .LBB0_4
; %bb.13:                               ; %Flow366
	s_mov_b32 s1, 0
.LBB0_14:                               ; %Flow368
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_19
; %bb.15:                               ; %.preheader251
	s_lshr_b32 s1, s2, 31
	v_dual_mov_b32 v10, 1 :: v_dual_lshlrev_b32 v1, 1, v0
	s_add_i32 s1, s2, s1
	s_add_i32 s16, s3, 1
	s_ashr_i32 s1, s1, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s1, s16, v[0:1]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s16, s2, v[1:2]
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 1, v4
	v_add_co_u32 v2, s1, s8, v4
	v_add_co_u32 v4, vcc_lo, s12, v5
	v_add_co_ci_u32_e64 v3, null, s9, 0, s1
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v6, vcc_lo
	v_add_co_u32 v6, s1, s8, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, null, s9, 0, s1
	s_mov_b32 s1, 0x20000
.LBB0_16:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_17 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, s1, v1
	s_mov_b32 s16, 0
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
.LBB0_17:                               ;   Parent Loop BB0_16 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_b32 v11, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 1, v11
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %_ZNK18cooperative_groups12thread_group4syncEv.exit226
                                        ;   in Loop: Header=BB0_16 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_and_b32_e32 v11, s14, v8
	v_and_b32_e32 v12, s14, v9
	s_add_i32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_gt_i32 s1, 0x3ffff
	v_cmp_lt_i32_e32 vcc_lo, v11, v12
	v_dual_cndmask_b32 v11, v9, v8 :: v_dual_cndmask_b32 v8, v8, v9
	s_clause 0x1
	global_store_b8 v[2:3], v11, off
	global_store_b8 v[6:7], v8, off
	flat_store_b32 v[4:5], v10 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_16
.LBB0_19:                               ; %Flow369
	s_mov_b32 s1, 0
.LBB0_20:                               ; %Flow372
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_31
; %bb.21:                               ; %.preheader249
	s_lshr_b32 s1, s2, 31
	v_lshlrev_b32_e32 v1, 1, v0
	s_add_i32 s1, s2, s1
	s_add_i32 s16, s15, -1
	s_ashr_i32 s1, s1, 1
	s_add_i32 s0, s0, -1
	v_mad_u64_u32 v[2:3], null, s1, s15, v[0:1]
	s_cmp_lg_u32 s15, s0
	s_cselect_b32 s0, -1, 0
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s15, s3
	v_mad_u64_u32 v[4:5], null, s16, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v6, 1, v4
	v_mov_b32_e32 v5, v3
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v2, s1, v2
	s_mul_i32 s1, s15, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s12, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v9, vcc_lo
	v_lshlrev_b64 v[12:13], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v11, vcc_lo
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_add3_u32 v2, s1, s2, v1
	v_add_co_u32 v8, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v14, 1, v2
	v_add_co_u32 v10, vcc_lo, s12, v10
	v_add_co_u32 v12, s3, s8, v2
	v_add_co_u32 v14, s10, s8, v14
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	v_add_co_ci_u32_e64 v13, null, s9, 0, s3
	v_add_co_ci_u32_e64 v15, null, s9, 0, s10
	v_mov_b32_e32 v2, 1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, s3
	s_mov_b32 s3, 0
.LBB0_22:                               ; %.preheader248
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_23 Depth 2
                                        ;     Child Loop BB0_25 Depth 2
	s_mov_b32 s10, 0
.LBB0_23:                               ;   Parent Loop BB0_22 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_b32 v16, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v16
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_23
; %bb.24:                               ;   in Loop: Header=BB0_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_clause 0x1
	global_load_b32 v16, v[6:7], off
	global_load_b32 v17, v[8:9], off
	s_mov_b32 s10, 0
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v16, s1, v16
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, s1, v17
	s_clause 0x1
	global_load_u8 v16, v16, s[8:9]
	global_load_u8 v17, v17, s[8:9]
	flat_store_b32 v[4:5], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_25:                               ;   Parent Loop BB0_22 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_b32 v18, v[10:11] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 1, v18
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_25
; %bb.26:                               ;   in Loop: Header=BB0_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_bfe_i32 v18, v16, 0, 8
	v_bfe_i32 v19, v17, 0, 8
	s_mov_b32 s10, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, s14, v18
	v_and_b32_e32 v19, s14, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v18, v19
	v_cndmask_b32_e32 v18, v16, v17, vcc_lo
	v_cndmask_b32_e32 v16, v17, v16, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_clause 0x1
	global_store_b8 v[12:13], v16, off
	global_store_b8 v[14:15], v18, off
	s_cbranch_vccnz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_22 Depth=1
	s_mov_b32 s10, 0
	flat_store_b32 v[10:11], v2 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
.LBB0_28:                               ; %Flow370
                                        ;   in Loop: Header=BB0_22 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_22 Depth=1
	v_add_nc_u32_e32 v17, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_store_b8 v[17:18], v16, off
	global_load_u8 v16, v[14:15], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[17:18], v16, off offset:1
.LBB0_30:                               ; %_ZNK18cooperative_groups12thread_group4syncEv.exit217
                                        ;   in Loop: Header=BB0_22 Depth=1
	s_add_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s3, 0x1ffff
	s_cbranch_scc0 .LBB0_22
.LBB0_31:                               ; %Flow373
	s_mov_b32 s0, 0
	s_branch .LBB0_33
.LBB0_32:
	s_mov_b32 s0, -1
.LBB0_33:                               ; %Flow375
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_38
; %bb.34:                               ; %.preheader
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 31
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v8, 1, v0
	s_add_i32 s0, s2, s0
	v_mov_b32_e32 v9, 1
	s_ashr_i32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, s2, v8
	v_add_nc_u32_e32 v0, s0, v0
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, s0, s8, v4
	v_add_nc_u32_e32 v4, 1, v4
	v_add_co_ci_u32_e64 v1, null, s9, 0, s0
	v_add_co_u32 v2, vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v4, s0, s8, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
	v_add_co_ci_u32_e64 v5, null, s9, 0, s0
	s_mov_b32 s0, 0
.LBB0_35:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_36 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s0, v8
	s_mov_b32 s1, 0
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
.LBB0_36:                               ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_b32 v10, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 1, v10
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_36
; %bb.37:                               ; %_ZNK18cooperative_groups12thread_group4syncEv.exit
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_and_b32_e32 v10, s14, v6
	v_and_b32_e32 v11, s14, v7
	s_add_i32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_gt_i32 s0, 0x1ffff
	v_cmp_lt_i32_e32 vcc_lo, v10, v11
	v_cndmask_b32_e32 v10, v7, v6, vcc_lo
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_clause 0x1
	global_store_b8 v[0:1], v10, off
	global_store_b8 v[4:5], v6, off
	s_waitcnt_vscnt null, 0x0
	buffer_gl1_inv
	buffer_gl0_inv
	flat_store_b32 v[2:3], v9 dlc
	s_waitcnt_vscnt null, 0x0
	s_cbranch_scc0 .LBB0_35
.LBB0_38:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5benesiiPcPiPViiS0_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5benesiiPcPiPViiS0_S_, .Lfunc_end0-_Z5benesiiPcPiPViiS0_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1968
; NumSgprs: 21
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5benesiiPcPiPViiS0_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z5benesiiPcPiPViiS0_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
