#include <stdio.h>

#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory

// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);

/**
 * @brief Performs an optimized version of a matrix transposition.
 * @param a The input matrix.
 * @param b The transposed matrix in output.
 * @param size The size of the matrix side.
 *
 * By exploiting GPU shared memory we may decompose the transposition in
 * multiple submatrices transpositions, minimizing global memory accesses
 * by doing them simultaneously for same-tile threads.
 */
__global__ void transposeOptimized(double *a, double *b, int size) 
{
    __shared__ double tile[TILE][TILE];
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    tile[threadIdx.x][threadIdx.y] = a[row * size + col];
    __syncthreads();
    b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}

/**
 * @brief Performs a naive version of a matrix transposition on GPU.
 * @param a The input matrix.
 * @param b The transposed matrix in output.
 * @param size The size of the matrix side.
 */
__global__ void transposeNaive(double *a, double *b, int size) 
{
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    int col = blockIdx.y * blockDim.y + threadIdx.y;
    b[col * size + row] = a[row * size + col];
}

/**
 * @brief Performs a serial version of a matrix transposition on CPU.
 * @param a The input matrix.
 * @param b The transposed matrix in output.
 * @param size The size of the matrix side.
 */
void transposeCpu(double *a, double *b, int size) 
{
    for (int i = 0; i < size; ++i)
      for (int j = 0; j < size; ++j)
        b[j * size + i] = a[i * size + j];
}

/**
 * @brief Validates the equality of two matrices in input.
 * @param a Matrix a.
 * @param b Matrix b.
 * @param size The size of the matrix side.
 */
int isCorrect(double * a, double * b, int size)
{
    for(int i = 0; i < size; ++i)
        for(int j = 0; j < size; ++j)
            if(b[i * size + j] != a[i * size + j])
                return 0;
    return 1;
}

/**
 * @brief Tests execution time and bandwidth of a transposition kernel on a GPU. 
 * @param kernel The kernel to be tested.
 * @param kernelName The name of the kernel to be tested.
 * @param block_x The x-dimension of the block used to perform blocking for cache.
 * @param block_y The y-dimension of the block used to perform blocking for cache.
 *
 * The transposition is performed as specified by the kernel function and then is
 * validated against a correctly-transposed matrix. GPU time and bandwidth are
 * provided as outputs of the function.
 */
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
    double * h_in, * h_out;
    double * dev_in, * dev_out;
    double * cpu;

    dim3 block(block_x, block_y);
    dim3 grid(N / block.x, N / block.y);

    h_in = (double *)malloc(MEMSIZE);
    h_out = (double *)malloc(MEMSIZE);
    cpu = (double *)malloc(MEMSIZE);
    cudaMalloc((void **)&dev_in, MEMSIZE);
    cudaMalloc((void **)&dev_out, MEMSIZE);
    
    // Fill input matrix with some indices (for validating transposition).
    for(int i = 0; i < MATSIZE; ++i)
        h_in[i] = i;
    
    // Initial setup of input matrix and timing events.
    cudaMemcpy(dev_in, h_in, MEMSIZE, cudaMemcpyHostToDevice);    
    cudaEvent_t start, stop;
    float exec_time = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    // Print some informations about the current task.
    printf("\nTransposing matrix on CPU for validation...\n");
    transposeCpu(h_in, cpu, N);
    printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
    printf("\nKernel: %s\n\n", kernelName);

    // Time kernel execution.
    cudaEventRecord(start);
    kernel<<<grid, block>>>(dev_in, dev_out, N);
    cudaEventRecord(stop);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&exec_time, start, stop);
    cudaMemcpy(h_out, dev_out, MEMSIZE, cudaMemcpyDeviceToHost);
    printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
    printf("GPU Time: %f\n", exec_time);

    // Bandwidth given by reading and writing a matrix during exec_time,
    // converted to GB/s for readability.
    printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
    printf("-------------------------------\n");

    // Cleanup
    free(h_in);
    free(h_out);
    free(cpu);
    cudaFree(dev_in);
    cudaFree(dev_out);
    cudaEventDestroy(start);
    cudaEventDestroy(stop);
    return 0;
}

int main(int argc, char *argv[]) 
{
    testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
    
    int a[5] = {2, 4, 8, 16, 32};

    for(int i = 0; i < 5; ++i)
        for(int j = 0; j < 5; ++j)
            testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);

    return 0;
}
	.file	"tmpxft_00271e4d_00000000-6_ex6.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12transposeCpuPdS_i
	.type	_Z12transposeCpuPdS_i, @function
_Z12transposeCpuPdS_i:
.LFB2027:
	.cfi_startproc
	endbr64
	movslq	%edx, %rax
	xorl	%r8d, %r8d
	salq	$3, %rax
.L3:
	cmpl	%edx, %r8d
	jge	.L8
	movq	%rsi, %r9
	xorl	%ecx, %ecx
.L4:
	movsd	(%rdi,%rcx,8), %xmm0
	incq	%rcx
	movsd	%xmm0, (%r9)
	addq	%rax, %r9
	cmpl	%ecx, %edx
	jg	.L4
	incl	%r8d
	addq	$8, %rsi
	addq	%rax, %rdi
	jmp	.L3
.L8:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z12transposeCpuPdS_i, .-_Z12transposeCpuPdS_i
	.globl	_Z9isCorrectPdS_i
	.type	_Z9isCorrectPdS_i, @function
_Z9isCorrectPdS_i:
.LFB2028:
	.cfi_startproc
	endbr64
	movslq	%edx, %r8
	xorl	%r9d, %r9d
	xorl	%ecx, %ecx
	salq	$3, %r8
.L10:
	cmpl	%edx, %ecx
	jge	.L18
	movq	%r9, %rax
	xorl	%r10d, %r10d
.L13:
	movsd	(%rsi,%rax), %xmm0
	ucomisd	(%rdi,%rax), %xmm0
	jp	.L14
	jne	.L14
	incl	%r10d
	addq	$8, %rax
	cmpl	%r10d, %edx
	jne	.L13
	incl	%ecx
	addq	%r8, %r9
	jmp	.L10
.L18:
	movl	$1, %eax
	ret
.L14:
	xorl	%eax, %eax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9isCorrectPdS_i, .-_Z9isCorrectPdS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CORRECT"
.LC1:
	.string	"FAIL"
.LC3:
	.string	"\nTransposing matrix on CPU for validation...\n"
.LC4:
	.string	"\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n"
.LC5:
	.string	"\nKernel: %s\n\n"
.LC6:
	.string	"%s: %s\n"
.LC7:
	.string	"GPU Time: %f\n"
.LC10:
	.string	"Bandwidth (GB/s): %f\n"
.LC11:
	.string	"-------------------------------\n"
	.text
	.globl	_Z17testCudaBandwidthPFvPdS_iEPKcii
	.type	_Z17testCudaBandwidthPFvPdS_iEPKcii, @function
_Z17testCudaBandwidthPFvPdS_iEPKcii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	movl	$536870912, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	xorl	%edx, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	movl	$8192, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movl	%ecx, %eax
	movl	$1, 72(%rsp)
	divl	%r12d
	movl	$1, 84(%rsp)
	xorl	%edx, %edx
	movl	%eax, 76(%rsp)
	movl	%ecx, %eax
	divl	%ebp
	movl	%eax, 80(%rsp)
	call	malloc@PLT
	movl	$536870912, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$536870912, %edi
	movq	%rax, %r13
	call	malloc@PLT
	leaq	32(%rsp), %rdi
	movl	$536870912, %esi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$536870912, %esi
	call	cudaMalloc@PLT
	xorl	%eax, %eax
.L20:
	cvtsi2sdl	%eax, %xmm0
	movsd	%xmm0, (%rbx,%rax,8)
	incq	%rax
	cmpq	$67108864, %rax
	jne	.L20
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$536870912, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	leaq	48(%rsp), %rdi
	movl	$0x00000000, 28(%rsp)
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	movl	$8192, %edx
	movq	%rbx, %rdi
	call	_Z12transposeCpuPdS_i
	pushq	%rbp
	.cfi_def_cfa_offset 168
	movl	$32, %r9d
	xorl	%eax, %eax
	pushq	%r12
	.cfi_def_cfa_offset 176
	movl	$32, %r8d
	movl	$8192, %ecx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	movl	$2, %edi
	popq	%rdx
	.cfi_def_cfa_offset 160
	leaq	.LC5(%rip), %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r12d, 64(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	movl	%ebp, 68(%rsp)
	movl	84(%rsp), %esi
	movq	64(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$8192, %edx
	call	*%r15
.L21:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	movl	$536870912, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movl	$8192, %edx
	movq	%r13, %rdi
	call	_Z9isCorrectPdS_i
	leaq	.LC1(%rip), %rcx
	movq	%r14, %rdx
	leaq	.LC6(%rip), %rsi
	testl	%eax, %eax
	leaq	.LC0(%rip), %rax
	movl	$2, %edi
	cmovne	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	28(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC10(%rip), %rsi
	movss	.LC8(%rip), %xmm0
	divss	28(%rsp), %xmm0
	divss	.LC9(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC11(%rip), %rsi
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z17testCudaBandwidthPFvPdS_iEPKcii, .-_Z17testCudaBandwidthPFvPdS_iEPKcii
	.section	.rodata.str1.1
.LC12:
	.string	"Naive Transpose"
.LC13:
	.string	"Optimized Transpose"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$32, %ecx
	movl	$32, %edx
	leaq	.LC12(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	leaq	_Z14transposeNaivePdS_i(%rip), %rdi
	xorl	%ebp, %ebp
	leaq	.LC13(%rip), %r12
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	_Z17testCudaBandwidthPFvPdS_iEPKcii
	movl	$32, 20(%rsp)
	movabsq	$17179869186, %rax
	movq	%rax, 4(%rsp)
	movabsq	$68719476744, %rax
	movq	%rax, 12(%rsp)
.L28:
	xorl	%ebx, %ebx
.L29:
	leaq	4(%rsp), %rax
	movq	%r12, %rsi
	leaq	_Z18transposeOptimizedPdS_i(%rip), %rdi
	movl	(%rax,%rbx,4), %ecx
	movl	(%rax,%rbp,4), %edx
	incq	%rbx
	call	_Z17testCudaBandwidthPFvPdS_iEPKcii
	cmpq	$5, %rbx
	jne	.L29
	incq	%rbp
	cmpq	$5, %rbp
	jne	.L28
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.text
	.globl	_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
	.type	_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i, @function
_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18transposeOptimizedPdS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L34:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i, .-_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
	.globl	_Z18transposeOptimizedPdS_i
	.type	_Z18transposeOptimizedPdS_i, @function
_Z18transposeOptimizedPdS_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
	.cfi_endproc
.LFE2056:
	.size	_Z18transposeOptimizedPdS_i, .-_Z18transposeOptimizedPdS_i
	.globl	_Z37__device_stub__Z14transposeNaivePdS_iPdS_i
	.type	_Z37__device_stub__Z14transposeNaivePdS_iPdS_i, @function
_Z37__device_stub__Z14transposeNaivePdS_iPdS_i:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14transposeNaivePdS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L39:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z37__device_stub__Z14transposeNaivePdS_iPdS_i, .-_Z37__device_stub__Z14transposeNaivePdS_iPdS_i
	.globl	_Z14transposeNaivePdS_i
	.type	_Z14transposeNaivePdS_i, @function
_Z14transposeNaivePdS_i:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z14transposeNaivePdS_iPdS_i
	.cfi_endproc
.LFE2058:
	.size	_Z14transposeNaivePdS_i, .-_Z14transposeNaivePdS_i
	.section	.rodata.str1.1
.LC14:
	.string	"_Z14transposeNaivePdS_i"
.LC15:
	.string	"_Z18transposeOptimizedPdS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14transposeNaivePdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18transposeOptimizedPdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC8:
	.long	1317011456
	.align 4
.LC9:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory

// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);

/**
 * @brief Performs an optimized version of a matrix transposition.
 * @param a The input matrix.
 * @param b The transposed matrix in output.
 * @param size The size of the matrix side.
 *
 * By exploiting GPU shared memory we may decompose the transposition in
 * multiple submatrices transpositions, minimizing global memory accesses
 * by doing them simultaneously for same-tile threads.
 */
__global__ void transposeOptimized(double *a, double *b, int size) 
{
    __shared__ double tile[TILE][TILE];
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    tile[threadIdx.x][threadIdx.y] = a[row * size + col];
    __syncthreads();
    b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}

/**
 * @brief Performs a naive version of a matrix transposition on GPU.
 * @param a The input matrix.
 * @param b The transposed matrix in output.
 * @param size The size of the matrix side.
 */
__global__ void transposeNaive(double *a, double *b, int size) 
{
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    int col = blockIdx.y * blockDim.y + threadIdx.y;
    b[col * size + row] = a[row * size + col];
}

/**
 * @brief Performs a serial version of a matrix transposition on CPU.
 * @param a The input matrix.
 * @param b The transposed matrix in output.
 * @param size The size of the matrix side.
 */
void transposeCpu(double *a, double *b, int size) 
{
    for (int i = 0; i < size; ++i)
      for (int j = 0; j < size; ++j)
        b[j * size + i] = a[i * size + j];
}

/**
 * @brief Validates the equality of two matrices in input.
 * @param a Matrix a.
 * @param b Matrix b.
 * @param size The size of the matrix side.
 */
int isCorrect(double * a, double * b, int size)
{
    for(int i = 0; i < size; ++i)
        for(int j = 0; j < size; ++j)
            if(b[i * size + j] != a[i * size + j])
                return 0;
    return 1;
}

/**
 * @brief Tests execution time and bandwidth of a transposition kernel on a GPU. 
 * @param kernel The kernel to be tested.
 * @param kernelName The name of the kernel to be tested.
 * @param block_x The x-dimension of the block used to perform blocking for cache.
 * @param block_y The y-dimension of the block used to perform blocking for cache.
 *
 * The transposition is performed as specified by the kernel function and then is
 * validated against a correctly-transposed matrix. GPU time and bandwidth are
 * provided as outputs of the function.
 */
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
    double * h_in, * h_out;
    double * dev_in, * dev_out;
    double * cpu;

    dim3 block(block_x, block_y);
    dim3 grid(N / block.x, N / block.y);

    h_in = (double *)malloc(MEMSIZE);
    h_out = (double *)malloc(MEMSIZE);
    cpu = (double *)malloc(MEMSIZE);
    hipMalloc((void **)&dev_in, MEMSIZE);
    hipMalloc((void **)&dev_out, MEMSIZE);
    
    // Fill input matrix with some indices (for validating transposition).
    for(int i = 0; i < MATSIZE; ++i)
        h_in[i] = i;
    
    // Initial setup of input matrix and timing events.
    hipMemcpy(dev_in, h_in, MEMSIZE, hipMemcpyHostToDevice);    
    hipEvent_t start, stop;
    float exec_time = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    // Print some informations about the current task.
    printf("\nTransposing matrix on CPU for validation...\n");
    transposeCpu(h_in, cpu, N);
    printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
    printf("\nKernel: %s\n\n", kernelName);

    // Time kernel execution.
    hipEventRecord(start);
    kernel<<<grid, block>>>(dev_in, dev_out, N);
    hipEventRecord(stop);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&exec_time, start, stop);
    hipMemcpy(h_out, dev_out, MEMSIZE, hipMemcpyDeviceToHost);
    printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
    printf("GPU Time: %f\n", exec_time);

    // Bandwidth given by reading and writing a matrix during exec_time,
    // converted to GB/s for readability.
    printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
    printf("-------------------------------\n");

    // Cleanup
    free(h_in);
    free(h_out);
    free(cpu);
    hipFree(dev_in);
    hipFree(dev_out);
    hipEventDestroy(start);
    hipEventDestroy(stop);
    return 0;
}

int main(int argc, char *argv[]) 
{
    testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
    
    int a[5] = {2, 4, 8, 16, 32};

    for(int i = 0; i < 5; ++i)
        for(int j = 0; j < 5; ++j)
            testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);

    return 0;
}
	.text
	.file	"ex6.hip"
	.globl	_Z33__device_stub__transposeOptimizedPdS_i # -- Begin function _Z33__device_stub__transposeOptimizedPdS_i
	.type	_Z33__device_stub__transposeOptimizedPdS_i,@function
_Z33__device_stub__transposeOptimizedPdS_i: # @_Z33__device_stub__transposeOptimizedPdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18transposeOptimizedPdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__transposeOptimizedPdS_i, .Lfunc_end0-_Z33__device_stub__transposeOptimizedPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__transposeNaivePdS_i # -- Begin function _Z29__device_stub__transposeNaivePdS_i
	.type	_Z29__device_stub__transposeNaivePdS_i,@function
_Z29__device_stub__transposeNaivePdS_i: # @_Z29__device_stub__transposeNaivePdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14transposeNaivePdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__transposeNaivePdS_i, .Lfunc_end1-_Z29__device_stub__transposeNaivePdS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12transposeCpuPdS_i           # -- Begin function _Z12transposeCpuPdS_i
	.type	_Z12transposeCpuPdS_i,@function
_Z12transposeCpuPdS_i:                  # @_Z12transposeCpuPdS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%edx, %eax
	leaq	(,%rax,8), %rcx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
.LBB2_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_3 Depth 2
	movl	%r8d, %r10d
	leaq	(%rdi,%r10,8), %r10
	movq	%rsi, %r11
	xorl	%ebx, %ebx
.LBB2_3:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%r10,%rbx,8), %xmm0            # xmm0 = mem[0],zero
	movsd	%xmm0, (%r11)
	incq	%rbx
	addq	%rcx, %r11
	cmpq	%rbx, %rax
	jne	.LBB2_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%r9
	addl	%edx, %r8d
	addq	$8, %rsi
	cmpq	%rax, %r9
	jne	.LBB2_2
# %bb.5:
	popq	%rbx
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
.LBB2_6:                                # %._crit_edge17
	retq
.Lfunc_end2:
	.size	_Z12transposeCpuPdS_i, .Lfunc_end2-_Z12transposeCpuPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z9isCorrectPdS_i               # -- Begin function _Z9isCorrectPdS_i
	.type	_Z9isCorrectPdS_i,@function
_Z9isCorrectPdS_i:                      # @_Z9isCorrectPdS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB3_1
# %bb.3:                                # %.preheader.lr.ph
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%edx, %eax
	xorl	%ecx, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
.LBB3_4:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
	movl	%ecx, %r11d
	leaq	(%rdi,%r11,8), %r10
	leaq	(%rsi,%r11,8), %r11
	xorl	%ebx, %ebx
.LBB3_6:                                #   Parent Loop BB3_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%r11,%rbx,8), %xmm0            # xmm0 = mem[0],zero
	ucomisd	(%r10,%rbx,8), %xmm0
	jne	.LBB3_8
	jp	.LBB3_8
# %bb.5:                                #   in Loop: Header=BB3_6 Depth=2
	incq	%rbx
	cmpq	%rbx, %rax
	jne	.LBB3_6
# %bb.7:                                # %._crit_edge
                                        #   in Loop: Header=BB3_4 Depth=1
	incq	%r9
	cmpq	%rax, %r9
	setae	%r8b
	addl	%edx, %ecx
	cmpq	%rax, %r9
	jne	.LBB3_4
.LBB3_8:
	popq	%rbx
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	jmp	.LBB3_2
.LBB3_1:
	movb	$1, %r8b
.LBB3_2:                                # %.thread
	movzbl	%r8b, %eax
	andl	$1, %eax
	retq
.Lfunc_end3:
	.size	_Z9isCorrectPdS_i, .Lfunc_end3-_Z9isCorrectPdS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z17testCudaBandwidthPFvPdS_iEPKcii
.LCPI4_0:
	.long	0x4e800000                      # float 1.07374182E+9
.LCPI4_1:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z17testCudaBandwidthPFvPdS_iEPKcii
	.type	_Z17testCudaBandwidthPFvPdS_iEPKcii,@function
_Z17testCudaBandwidthPFvPdS_iEPKcii:    # @_Z17testCudaBandwidthPFvPdS_iEPKcii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 56(%rsp)                  # 8-byte Spill
	movl	%edx, %eax
	movq	%r14, %rbp
	shlq	$32, %rbp
	orq	%rax, %rbp
	xorl	%r15d, %r15d
	movl	$8192, %eax                     # imm = 0x2000
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %r13d
	shlq	$32, %r13
	movl	$536870912, %edi                # imm = 0x20000000
	callq	malloc
	movq	%rax, %rbx
	movl	$536870912, %edi                # imm = 0x20000000
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$536870912, %edi                # imm = 0x20000000
	callq	malloc
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	leaq	48(%rsp), %rdi
	movl	$536870912, %esi                # imm = 0x20000000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$536870912, %esi                # imm = 0x20000000
	callq	hipMalloc
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r15d, %xmm0
	movsd	%xmm0, (%rbx,%r15,8)
	incq	%r15
	cmpq	$67108864, %r15                 # imm = 0x4000000
	jne	.LBB4_1
# %bb.2:
	xorl	%r15d, %r15d
	movl	$8192, %eax                     # imm = 0x2000
	xorl	%edx, %edx
	divl	%r12d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	48(%rsp), %rdi
	movl	$536870912, %edx                # imm = 0x20000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$0, 12(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	%rbx, %rax
	movq	24(%rsp), %rcx                  # 8-byte Reload
.LBB4_3:                                # %.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_4 Depth 2
	movq	%rcx, %rdx
	xorl	%esi, %esi
.LBB4_4:                                #   Parent Loop BB4_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rax,%rsi,8), %xmm0            # xmm0 = mem[0],zero
	movsd	%xmm0, (%rdx)
	incq	%rsi
	addq	$65536, %rdx                    # imm = 0x10000
	cmpq	$8192, %rsi                     # imm = 0x2000
	jne	.LBB4_4
# %bb.5:                                # %._crit_edge.i
                                        #   in Loop: Header=BB4_3 Depth=1
	incq	%r15
	addq	$8, %rcx
	addq	$65536, %rax                    # imm = 0x10000
	cmpq	$8192, %r15                     # imm = 0x2000
	jne	.LBB4_3
# %bb.6:                                # %_Z12transposeCpuPdS_i.exit
	orq	64(%rsp), %r13                  # 8-byte Folded Reload
	movl	%r14d, (%rsp)
	movl	$.L.str.1, %edi
	movl	$8192, %esi                     # imm = 0x2000
	movl	$8192, %edx                     # imm = 0x2000
	movl	$32, %ecx
	movl	$32, %r8d
	movl	%r12d, %r9d
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	movq	72(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movl	$8192, %edx                     # imm = 0x2000
	movq	56(%rsp), %rax                  # 8-byte Reload
	callq	*(%rax)
.LBB4_8:
	movq	16(%rsp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	12(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	40(%rsp), %rsi
	movl	$536870912, %edx                # imm = 0x20000000
	movq	80(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$65536, %eax                    # imm = 0x10000
	movq	24(%rsp), %rcx                  # 8-byte Reload
	movq	%r15, %rdx
	xorl	%esi, %esi
.LBB4_9:                                # %.lr.ph.i28
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_11 Depth 2
	xorl	%edi, %edi
.LBB4_11:                               #   Parent Loop BB4_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rcx,%rdi,8), %xmm0            # xmm0 = mem[0],zero
	ucomisd	(%rdx,%rdi,8), %xmm0
	jne	.LBB4_13
	jp	.LBB4_13
# %bb.10:                               #   in Loop: Header=BB4_11 Depth=2
	incq	%rdi
	cmpq	$8192, %rdi                     # imm = 0x2000
	jne	.LBB4_11
# %bb.12:                               # %._crit_edge.i32
                                        #   in Loop: Header=BB4_9 Depth=1
	cmpq	$8191, %r14                     # imm = 0x1FFF
	leaq	1(%r14), %rdi
	setae	%sil
	addq	%rax, %rdx
	addq	%rax, %rcx
	movq	%rdi, %r14
	cmpq	$8192, %rdi                     # imm = 0x2000
	jne	.LBB4_9
.LBB4_13:                               # %_Z9isCorrectPdS_i.exit
	movl	$.L.str.4, %eax
	movl	$.L.str.5, %edx
	testb	$1, %sil
	cmovneq	%rax, %rdx
	movl	$.L.str.3, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	divss	12(%rsp), %xmm0
	divss	.LCPI4_1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	%rbx, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z17testCudaBandwidthPFvPdS_iEPKcii, .Lfunc_end4-_Z17testCudaBandwidthPFvPdS_iEPKcii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI5_0:
	.long	2                               # 0x2
	.long	4                               # 0x4
	.long	8                               # 0x8
	.long	16                              # 0x10
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$_Z14transposeNaivePdS_i, %edi
	movl	$.L.str.9, %esi
	movl	$32, %edx
	movl	$32, %ecx
	callq	_Z17testCudaBandwidthPFvPdS_iEPKcii
	movaps	.LCPI5_0(%rip), %xmm0           # xmm0 = [2,4,8,16]
	movaps	%xmm0, (%rsp)
	movl	$32, 16(%rsp)
	xorl	%r14d, %r14d
.LBB5_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_2 Depth 2
	movl	(%rsp,%r14,4), %ebx
	xorl	%r15d, %r15d
.LBB5_2:                                #   Parent Loop BB5_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rsp,%r15,4), %ecx
	movl	$_Z18transposeOptimizedPdS_i, %edi
	movl	$.L.str.10, %esi
	movl	%ebx, %edx
	callq	_Z17testCudaBandwidthPFvPdS_iEPKcii
	incq	%r15
	cmpq	$5, %r15
	jne	.LBB5_2
# %bb.3:                                #   in Loop: Header=BB5_1 Depth=1
	incq	%r14
	cmpq	$5, %r14
	jne	.LBB5_1
# %bb.4:
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18transposeOptimizedPdS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14transposeNaivePdS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18transposeOptimizedPdS_i,@object # @_Z18transposeOptimizedPdS_i
	.section	.rodata,"a",@progbits
	.globl	_Z18transposeOptimizedPdS_i
	.p2align	3, 0x0
_Z18transposeOptimizedPdS_i:
	.quad	_Z33__device_stub__transposeOptimizedPdS_i
	.size	_Z18transposeOptimizedPdS_i, 8

	.type	_Z14transposeNaivePdS_i,@object # @_Z14transposeNaivePdS_i
	.globl	_Z14transposeNaivePdS_i
	.p2align	3, 0x0
_Z14transposeNaivePdS_i:
	.quad	_Z29__device_stub__transposeNaivePdS_i
	.size	_Z14transposeNaivePdS_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n"
	.size	.L.str.1, 48

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\nKernel: %s\n\n"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%s: %s\n"
	.size	.L.str.3, 8

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"CORRECT"
	.size	.L.str.4, 8

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"FAIL"
	.size	.L.str.5, 5

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"GPU Time: %f\n"
	.size	.L.str.6, 14

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Bandwidth (GB/s): %f\n"
	.size	.L.str.7, 22

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Naive Transpose"
	.size	.L.str.9, 16

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Optimized Transpose"
	.size	.L.str.10, 20

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18transposeOptimizedPdS_i"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14transposeNaivePdS_i"
	.size	.L__unnamed_2, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\nTransposing matrix on CPU for validation..."
	.size	.Lstr, 45

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"-------------------------------"
	.size	.Lstr.1, 32

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__transposeOptimizedPdS_i
	.addrsig_sym _Z29__device_stub__transposeNaivePdS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18transposeOptimizedPdS_i
	.addrsig_sym _Z14transposeNaivePdS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18transposeOptimizedPdS_i ; -- Begin function _Z18transposeOptimizedPdS_i
	.globl	_Z18transposeOptimizedPdS_i
	.p2align	8
	.type	_Z18transposeOptimizedPdS_i,@function
_Z18transposeOptimizedPdS_i:            ; @_Z18transposeOptimizedPdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 3, v0
	v_lshl_add_u32 v6, v1, 8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
	ds_store_b64 v6, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[2:3], v6
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18transposeOptimizedPdS_i
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18transposeOptimizedPdS_i, .Lfunc_end0-_Z18transposeOptimizedPdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z14transposeNaivePdS_i ; -- Begin function _Z14transposeNaivePdS_i
	.globl	_Z14transposeNaivePdS_i
	.p2align	8
	.type	_Z14transposeNaivePdS_i,@function
_Z14transposeNaivePdS_i:                ; @_Z14transposeNaivePdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
	v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14transposeNaivePdS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14transposeNaivePdS_i, .Lfunc_end1-_Z14transposeNaivePdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18transposeOptimizedPdS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18transposeOptimizedPdS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14transposeNaivePdS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14transposeNaivePdS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
