
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#define PI  3.1415926535897932
#define MAXEQNS    10       // maximum number of differential equations in the system
 
const int itermax10 = 2;    // number of iterations to use for rk10
const int itermax12 = 1;    // number of additional iterations to use for rk12
const int neqns = 2;        // number of differential equations in the system
const double tol = 1.0e-10; // the error tolerance
const double tol10 = tol / 10;
const bool sho = true;      // set sho to true if you want the simple harmonic oscillator results
// set sho to false, if you want the predator - prey results
 
// the following constants are the 10th order method's coefficients
const double  a0 = 0;
__constant__ double  a1 = 0.11747233803526765;
__constant__ double  a2 = 0.35738424175967745;
__constant__ double  a3 = 0.64261575824032255;
__constant__ double  a4 = 0.88252766196473235;
const double  a5 = 1.0000000000000000;
 
__constant__ double  b10 = 0.047323231137709573;
__constant__ double  b11 = 0.077952072407795078;
__constant__ double  b12 = -0.010133421269900587;
__constant__ double  b13 = 0.0028864915990617097;
__constant__ double  b14 = -0.00055603583939812082;
__constant__ double  b20 = 0.021779075831486075;
__constant__ double  b21 = 0.22367959757928498;
__constant__ double  b22 = 0.12204792759220492;
__constant__ double  b23 = -0.012091266674498959;
__constant__ double  b24 = 0.0019689074312004371;
__constant__ double  b30 = 0.044887590835180592;
__constant__ double  b31 = 0.15973856856089786;
__constant__ double  b32 = 0.32285378852557547;
__constant__ double  b33 = 0.12204792759220492;
__constant__ double  b34 = -0.0069121172735362915;
__constant__ double  b40 = 0.019343435528957094;
__constant__ double  b41 = 0.22312684732165494;
__constant__ double  b42 = 0.23418268877986459;
__constant__ double  b43 = 0.32792261792646064;
__constant__ double  b44 = 0.077952072407795078;
const double  b50 = 0.066666666666666667;
const double  b51 = 0.10981508874708385;
const double  b52 = 0.37359383699761912;
const double  b53 = 0.18126454003786724;
const double  b54 = 0.26865986755076313;
 
const double  c0 = 0.033333333333333333;
const double  c1 = 0.18923747814892349;
const double  c2 = 0.27742918851774318;
const double  c3 = 0.27742918851774318;
const double  c4 = 0.18923747814892349;
const double  c5 = 0.033333333333333333;
 
// the following coefficients allow us to get rk12 internal xk values from rk10 fk values
__constant__ double  g10 = 0.043407276098971173;
__constant__ double  g11 = 0.049891561330903419;
__constant__ double  g12 = -0.012483721919363355;
__constant__ double  g13 = 0.0064848904066894701;
__constant__ double  g14 = -0.0038158693974615597;
__constant__ double  g15 = 0.0014039153409773882;
__constant__ double  g20 = 0.030385164419638569;
__constant__ double  g21 = 0.19605322645426044;
__constant__ double  g22 = 0.047860687574395354;
__constant__ double  g23 = -0.012887249003100515;
__constant__ double  g24 = 0.0064058521980400821;
__constant__ double  g25 = -0.0022420783785910372;
__constant__ double  g30 = 0.032291666666666667;
__constant__ double  g31 = 0.19311806292811784;
__constant__ double  g32 = 0.25797759963091718;
__constant__ double  g33 = 0.019451588886825999;
__constant__ double  g34 = -0.0038805847791943522;
__constant__ double  g35 = 0.0010416666666666667;
__constant__ double  g40 = 0.035575411711924371;
__constant__ double  g41 = 0.18283162595088341;
__constant__ double  g42 = 0.29031643752084369;
__constant__ double  g43 = 0.22956850094334782;
__constant__ double  g44 = -0.0068157483053369507;
__constant__ double  g45 = 0.0029481689136947641;
__constant__ double  g50 = 0.031929417992355945;
__constant__ double  g51 = 0.19305334754638505;
__constant__ double  g52 = 0.27094429811105371;
__constant__ double  g53 = 0.28991291043710653;
__constant__ double  g54 = 0.13934591681802007;
__constant__ double  g55 = -0.010073942765637839;
const double  g60 = 0.033333333333333333;
const double  g61 = 0.18923747814892349;
const double  g62 = 0.27742918851774318;
const double  g63 = 0.27742918851774318;
const double  g64 = 0.18923747814892349;
const double  g65 = 0.033333333333333333;
 
// the following constants are the 12th order method's coefficients
const double  ah0 = 0.0;
const double  ah1 = 0.084888051860716535;
const double  ah2 = 0.26557560326464289;
const double  ah3 = 0.50000000000000000;
const double  ah4 = 0.73442439673535711;
const double  ah5 = 0.91511194813928346;
const double  ah6 = 1.0000000000000000;
 
__constant__ double  bh10 = 0.033684534770907752;
__constant__ double  bh11 = 0.057301749935629582;
__constant__ double  bh12 = -0.0082444880936983822;
__constant__ double  bh13 = 0.0029151263642014432;
__constant__ double  bh14 = -0.00096482361331657787;
__constant__ double  bh15 = 0.00019595249699271744;
__constant__ double  bh20 = 0.015902242088596380;
__constant__ double  bh21 = 0.16276437062291593;
__constant__ double  bh22 = 0.096031583397703751;
__constant__ double  bh23 = -0.011758319711158930;
__constant__ double  bh24 = 0.0032543514515832418;
__constant__ double  bh25 = -0.00061862458499748489;
__constant__ double  bh30 = 0.031250000000000000;
__constant__ double  bh31 = 0.11881843285766042;
__constant__ double  bh32 = 0.24868761828096535;
__constant__ double  bh33 = 0.11000000000000000;
__constant__ double  bh34 = -0.010410996557394222;
__constant__ double  bh35 = 0.0016549454187684515;
__constant__ double  bh40 = 0.015902242088596380;
__constant__ double  bh41 = 0.15809680304274781;
__constant__ double  bh42 = 0.18880881534382426;
__constant__ double  bh43 = 0.28087114502765051;
__constant__ double  bh44 = 0.096031583397703751;
__constant__ double  bh45 = -0.0052861921651656089;
__constant__ double  bh50 = 0.033684534770907752;
__constant__ double  bh51 = 0.11440754737426645;
__constant__ double  bh52 = 0.24657204460460206;
__constant__ double  bh53 = 0.20929436236889375;
__constant__ double  bh54 = 0.25385170908498387;
__constant__ double  bh55 = 0.057301749935629582;
const double  bh60 = 0;
const double  bh61 = 0.19581988897471611;
const double  bh62 = 0.14418011102528389;
const double  bh63 = 0.32000000000000000;
const double  bh64 = 0.14418011102528389;
const double  bh65 = 0.19581988897471611;
 
const double  ch0 = 0.023809523809523810;
const double  ch1 = 0.13841302368078297;
const double  ch2 = 0.21587269060493131;
const double  ch3 = 0.24380952380952381;
const double  ch4 = 0.21587269060493131;
const double  ch5 = 0.13841302368078297;
const double  ch6 = 0.023809523809523810;

#define cudaErrorCheck(call) { cudaAssert(call,__FILE__,__LINE__); }

void cudaAssert(const cudaError err, const char *file, const int line)
{ 
    if( cudaSuccess != err) {                                                
        fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",        
                file, line, cudaGetErrorString(err) );
		getchar();
        exit(1);
    } 
}

//****************************************************************************

//Derivative kernel: takes pointers to x[], and f[] allocated on the device
__global__ void derKernel(double* device_x, double* device_f)
{
	//2 elements in device_x represent 2 elements from individual arrays X1-X4;
	//ie if thread id is 0 then the array number is 0x2 and work on elements tx*2 and tx*2 +1
	int tx = threadIdx.x;
	int xArrayNumber = tx *2;
	
		
			device_f[xArrayNumber] = device_x[xArrayNumber+1];
			__syncthreads();
			device_f[xArrayNumber+1] = -device_x[xArrayNumber];
			__syncthreads();
		
		
	
}
__global__ void guessKernel(double*device_X_Total, double* device_X_Not,double* device_F_Not, double h){

	device_X_Total[threadIdx.x] = device_X_Not[threadIdx.x] + a1 * h * device_F_Not[threadIdx.x];
	device_X_Total[threadIdx.x +2] = device_X_Not[threadIdx.x] + a2 * h * device_F_Not[threadIdx.x];
	device_X_Total[threadIdx.x +4] = device_X_Not[threadIdx.x] + a3 * h * device_F_Not[threadIdx.x];
	device_X_Total[threadIdx.x +6] = device_X_Not[threadIdx.x] + a4 * h * device_F_Not[threadIdx.x];
}
__global__ void order10Kernel(double*device_X_Total, double* device_X_Not, double *device_F_Not, double h, double *device_f)
{
	int tx = threadIdx.x;
	device_X_Total[tx]=device_X_Not[tx] + h*((b10 * device_F_Not[tx]) + (b11 * device_f[tx]) + (b12 * device_f[tx+2]) + (b13 * device_f[tx +4]) + (b14 * device_f[tx +6]));
	__syncthreads();
	device_X_Total[tx+2]=device_X_Not[tx] + h*((b20 * device_F_Not[tx]) + (b21 * device_f[tx]) + (b22 * device_f[tx+2]) + (b23 * device_f[tx +4]) + (b24 * device_f[tx +6]));
	__syncthreads();
	device_X_Total[tx+4]=device_X_Not[tx] + h*((b30 * device_F_Not[tx]) +( b31 * device_f[tx]) + (b32 * device_f[tx+2]) + (b33 * device_f[tx +4]) + (b34 * device_f[tx +6]));
	__syncthreads();
	device_X_Total[tx+6]=device_X_Not[tx] + h*((b40 * device_F_Not[tx]) + (b41 * device_f[tx]) +( b42 * device_f[tx+2]) + (b43 * device_f[tx +4]) +( b44 * device_f[tx +6]));
	__syncthreads();
	
}
__global__ void Order10FkKernel(double*device_X_Total, double* device_X_Not, double* device_F_Not, double h, double*device_f)
{

	int tx = threadIdx.x;
	device_X_Total[tx] = device_X_Not[tx] + h*((g10*device_F_Not[tx])+ (g11 * device_f[tx]) + (g12 * device_f[tx+2])+ (g13 * device_f[tx + 4]) + (g14 * device_f[tx+ 6])+ (g15 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+2] = device_X_Not[tx] + h*((g20*device_F_Not[tx])+ (g21 * device_f[tx]) + (g22 * device_f[tx+2])+ (g23 * device_f[tx + 4]) + (g24 * device_f[tx+ 6])+ (g25 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+4] = device_X_Not[tx] + h*((g30*device_F_Not[tx])+ (g31 * device_f[tx]) + (g32 * device_f[tx+2])+ (g33 * device_f[tx + 4]) + (g34 * device_f[tx+ 6])+ (g35 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+6] = device_X_Not[tx] + h*((g40*device_F_Not[tx])+ (g41 * device_f[tx]) + (g42 * device_f[tx+2])+ (g43 * device_f[tx + 4]) + (g44 * device_f[tx+ 6])+ (g45 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+8] = device_X_Not[tx] + h*((g50*device_F_Not[tx])+ (g51 * device_f[tx]) + (g52 * device_f[tx+2])+ (g53 * device_f[tx + 4]) + (g54 * device_f[tx+ 6])+ (g55 *device_f[tx+8]));
	__syncthreads();
}
__global__ void Order12Kernel(double*device_X_Total, double* device_X_Not, double* device_F_Not, double h, double*device_f){
	
	int tx =  threadIdx.x;
	device_X_Total[tx] = device_X_Not[tx] + h*((bh10*device_F_Not[tx])+ (bh11 * device_f[tx]) + (bh12 * device_f[tx+2])+ (bh13 * device_f[tx + 4]) + (bh14 * device_f[tx+ 6])+ (bh15 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+2] = device_X_Not[tx] + h*((bh20*device_F_Not[tx])+ (bh21 * device_f[tx]) + (bh22 * device_f[tx+2])+ (bh23 * device_f[tx + 4]) + (bh24 * device_f[tx+ 6])+ (bh25 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+4] = device_X_Not[tx] + h*((bh30*device_F_Not[tx])+ (bh31 * device_f[tx]) + (bh32 * device_f[tx+2])+ (bh33 * device_f[tx + 4]) + (bh34 * device_f[tx+ 6])+ (bh35 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+6] = device_X_Not[tx] + h*((bh40*device_F_Not[tx])+ (bh41 * device_f[tx]) + (bh42 * device_f[tx+2])+ (bh43 * device_f[tx + 4]) + (bh44 * device_f[tx+ 6])+ (bh45 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+8] = device_X_Not[tx] + h*((bh50*device_F_Not[tx])+ (bh51 * device_f[tx]) + (bh52 * device_f[tx+2])+ (bh53 * device_f[tx + 4]) + (bh54 * device_f[tx+ 6])+ (bh55 *device_f[tx+8]));
	__syncthreads();
}
//****************************************************************************
// the following function describes the ordinary differential equations
//** The function is still live for the non parallel function calls to der
//** still active in the program. 
void der(double t, double x[], double f[]) {
       if (sho) {
              f[0] = x[1];
              f[1] = -x[0];
       }
       else {
              f[0] = x[0] * (2.0 - x[1]);
              f[1] = x[1] * (x[0] - 1.0);
       }
}
 
void rk1210() {
       // Implicit Runge-Kutta of orders 12 and 10
       double  x0[MAXEQNS], x1[MAXEQNS], x2[MAXEQNS], x3[MAXEQNS], x4[MAXEQNS];
       double  x5[MAXEQNS], x6[MAXEQNS], xn10[MAXEQNS], xn12[MAXEQNS];
       double  t0, tf, h, hnew, est, esti, f0[MAXEQNS], f1[MAXEQNS], f2[MAXEQNS];
       double  f3[MAXEQNS], f4[MAXEQNS], f5[MAXEQNS], f6[MAXEQNS];
       int     iter;
       bool    finished = false;  // becomes true when we have reached tf
 
       if (sho) {
              h = PI / 4.0;       // initial guess for stepsize to use
              x0[0] = 0.0;      // initial value of first  component
              x0[1] = 1.0;      // initial value of second component
              t0 = 0.0;         // initial t value, t0
              tf = 2 * PI;        // final t value, tf
       }
       else {
              h = 1.0 / 2.0;      // initial guess for stepsize to use
              x0[0] = 2.0;      // initial value of first  component
              x0[1] = 2.0;      // initial value of second component
              t0 = 0.0;         // initial t value, t0
              tf = 4.0;         // final t value, tf
       }
       printf("Initial conditions are  t0 = %8.5lf, x0[0] = %18.15lf, x0[1] = %18.15lf\n", t0, x0[0], x0[1]);
	   const int arraySize = 10;  //there will be 8 elements being written from x1-x4 (Remaining 2 for when X5 is included);
			  int numOfXArrays =4;
			  double x_total[arraySize]; 
			  double f_total[arraySize];
       while (!finished) {                  // keep going until we reach tf successfully
              der(t0, x0, f0);                    // first, we will get 10th order results
              ////////////////////   THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //for (int i = 0; i<neqns; i++) {
              //       x1[i] = x0[i] + a1*h*f0[i];  // just guess that solution is a straight line initially
              //       x2[i] = x0[i] + a2*h*f0[i];  // at the four internal points within the step
              //       x3[i] = x0[i] + a3*h*f0[i];
              //       x4[i] = x0[i] + a4*h*f0[i];
              //}
			  //*************************************************************************************
			  double* device_x_total; double* device_x_not; double* device_f_not; //creating variables for the device
			  //allocating memory for device variables
			  cudaMalloc((void**) &device_x_total, arraySize * sizeof(double));
			  cudaMalloc((void**) &device_x_not, arraySize * sizeof(double));
			  cudaMalloc((void**) &device_f_not, arraySize * sizeof(double));
			  //copying contents of x0 and f0 to the device variables
			  cudaMemcpy(device_x_not, x0, arraySize*sizeof(double), cudaMemcpyHostToDevice);
			  cudaMemcpy(device_f_not, f0, arraySize *sizeof(double), cudaMemcpyHostToDevice);
			  guessKernel<<<1, neqns>>>(device_x_total, device_x_not, device_f_not, h);

			  cudaMemcpy(x_total, device_x_total, arraySize*sizeof(double), cudaMemcpyDeviceToHost);

			  //************************************************************************************
              ////////////////////   AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //der(t0 + a1*h, x1, f1);          // now, evaluate the derivatives at these four points
              //der(t0 + a2*h, x2, f2);
              //der(t0 + a3*h, x3, f3);
              //der(t0 + a4*h, x4, f4);
			  //****************************************************************************************
			  
			  double* device_f;  //creating variables for device;
			  //allocating memory for x[], and f[]
			  cudaMalloc((void**) &device_x_total, arraySize* sizeof(double));
			  cudaMalloc((void**) &device_f, arraySize * sizeof(double));

			  //copying over t and x[]
			  cudaMemcpy(device_x_total, x_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
			  //*******Creating timers to test 4 arrays *********
			  /*cudaEvent_t start, stop;
			  cudaEventCreate(&start);
			  cudaEventCreate(&stop);
			  cudaEventRecord(start);*/
			  //kernel call
			  derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
			  
			 /* cudaEventRecord(stop);*/
			  //copying data from device to host
		      cudaMemcpy(f_total, device_f, arraySize*sizeof(double), cudaMemcpyDeviceToHost);
			  /*cudaEventSynchronize(stop);
			  float milliseconds =0;
			  cudaEventElapsedTime(&milliseconds, start, stop);
			  printf("Kernel took: %f milliseconds\n", milliseconds);
			  getchar();*/
			  
			  
			  //****************************************************************************************
			  cudaMalloc((void**) &device_x_total, arraySize* sizeof(double));
			  cudaMalloc((void**) &device_x_not, arraySize*sizeof(double));
			  cudaMalloc((void**) &device_f_not, arraySize*sizeof(double));
			  cudaMalloc((void**) &device_f, arraySize*sizeof(double));
              for (iter = 0; iter<itermax10; iter++) {  // now, we perform itermax10 iterations for the 10th order method
                     printf("iter = %d\n", iter);
                     //////////////////   AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
						/*for (int i = 0; i<neqns; i++) x1[i] = x0[i] + h*(b10*f0[i] + b11*f1[i] + b12*f2[i] + b13*f3[i] + b14*f4[i]);
						for (int i = 0; i<neqns; i++) x2[i] = x0[i] + h*(b20*f0[i] + b21*f1[i] + b22*f2[i] + b23*f3[i] + b24*f4[i]);
						for (int i = 0; i<neqns; i++) x3[i] = x0[i] + h*(b30*f0[i] + b31*f1[i] + b32*f2[i] + b33*f3[i] + b34*f4[i]);
						for (int i = 0; i<neqns; i++) x4[i] = x0[i] + h*(b40*f0[i] + b41*f1[i] + b42*f2[i] + b43*f3[i] + b44*f4[i]);*/
					 
						
					    //*************Copying over f_total f0 and x0*******************************
						cudaMemcpy(device_f, f_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
						cudaMemcpy(device_f_not, f0, arraySize*sizeof(double), cudaMemcpyHostToDevice);
						cudaMemcpy(device_x_not, x0, arraySize*sizeof(double), cudaMemcpyHostToDevice);
						order10Kernel<<<1,neqns>>>(device_x_total,device_x_not,device_f_not, h,device_f);
					    cudaMemcpy(x_total, device_x_total, arraySize*sizeof(double), cudaMemcpyDeviceToHost);
						
						

					 //**********************************************************************************************************************
                     ////////////////////   AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
                     //der(t0 + a1*h, x1, f1);          // now, evaluate the derivatives at these four points
                     //der(t0 + a2*h, x2, f2);
                     //der(t0 + a3*h, x3, f3);
                     //der(t0 + a4*h, x4, f4);
					 //************************************************************************************
			  
					 
					  cudaMalloc((void**) &device_x_total, arraySize* sizeof(double));
					  cudaMalloc((void**) &device_f, arraySize * sizeof(double));

					  //copying over t and x[]
					  cudaMemcpy(device_x_total, x_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
						
					  //kernel call
					   derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
					  //writeback
					  cudaMemcpy(f_total, device_f, arraySize*sizeof(double), cudaMemcpyDeviceToHost);
					 
					 //*****************************************************************************************
                     ////////////////////   END OF PARALLEL SECTION OF CODE  ///////////////////////
              }
			  cudaFree(device_x_total);
			  cudaFree(device_x_not);
			  cudaFree(device_f_not);
			  cudaFree(device_f);

			   
			   memcpy(x1,x_total, 2*sizeof(double));
			   memcpy(x2,x_total +2, 2*sizeof(double));
			   memcpy(x3,x_total +4, 2 *sizeof(double));
		       memcpy(x4, x_total +6, 2*sizeof(double));
			   memcpy(f1,f_total, 2*sizeof(double));
			   memcpy(f2,f_total +2, 2*sizeof(double));
			   memcpy(f3,f_total +4, 2 *sizeof(double));
			   memcpy(f4, f_total +6, 2*sizeof(double));
						
              for (int i = 0; i<neqns; i++) x5[i] = x0[i] + h*(b50*f0[i] + b51*f1[i] + b52*f2[i] + b53*f3[i] + b54*f4[i]);  // now get x5
              der(t0 + a5*h, x5, f5);  // and get the derivative there, f5
              for (int i = 0; i<neqns; i++) {
                     xn10[i] = x0[i] + h*(c0*f0[i] + c1*f1[i] + c2*f2[i] + c3*f3[i] + c4*f4[i] + c5*f5[i]);  // now compute final 10th order answer
              }
              if (sho) {
                     printf("10th order iterations = %d, t = %8.5lf, xn10[0] = %18.15lf, xn10[1] = %18.15lf, error[0] = %e, error[1] = %e\n",
                           itermax10, t0 + h, xn10[0], xn10[1], xn10[0] - sin(t0 + h), xn10[1] - cos(t0 + h));
              }
              else {
                     printf("10th order iterations = %d, t = %8.5lf, xn10[0] = %18.15lf, xn10[1] = %18.15lf\n",
                           itermax10, t0 + h, xn10[0], xn10[1]);
              }
              ////////////////////   THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //for (int i = 0; i<neqns; i++) {
              //       x1[i] = x0[i] + h*(g10*f0[i] + g11*f1[i] + g12*f2[i] + g13*f3[i] + g14*f4[i] + g15*f5[i]); // these fk's are from 10th order method,
              //       x2[i] = x0[i] + h*(g20*f0[i] + g21*f1[i] + g22*f2[i] + g23*f3[i] + g24*f4[i] + g25*f5[i]); // and note that they are being
              //       x3[i] = x0[i] + h*(g30*f0[i] + g31*f1[i] + g32*f2[i] + g33*f3[i] + g34*f4[i] + g35*f5[i]); // used to build the five internal values
              //       x4[i] = x0[i] + h*(g40*f0[i] + g41*f1[i] + g42*f2[i] + g43*f3[i] + g44*f4[i] + g45*f5[i]); // used to construct the 12th order xk's,
              //       x5[i] = x0[i] + h*(g50*f0[i] + g51*f1[i] + g52*f2[i] + g53*f3[i] + g54*f4[i] + g55*f5[i]); // so these xk's are for the 12th order method
              //}
			  //***************************************************************************************************************************************************
			  
			  //copying f arrays to a single array f_total
			   memcpy(f_total,f1, 2*sizeof(double));
			   memcpy(f_total+2,f2, 2*sizeof(double));
			   memcpy(f_total+4,f3, 2 *sizeof(double));
			   memcpy(f_total+6, f4, 2*sizeof(double));
			   memcpy(f_total+8, f5, 2*sizeof(double));
			   //allocating memory
			   cudaMalloc((void**) &device_x_total, arraySize*sizeof(double));
			   cudaMalloc((void**) &device_f, arraySize*sizeof(double));
			   cudaMalloc((void**) &device_x_not, arraySize*sizeof(double));
			   cudaMalloc((void**) &device_f_not, arraySize*sizeof(double));

			   //copying over f0, x0, and f_total
			   cudaMemcpy(device_f,f_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
			   cudaMemcpy(device_x_not, x0, arraySize*sizeof(double), cudaMemcpyHostToDevice);
			   cudaMemcpy(device_f_not, f0, arraySize*sizeof(double), cudaMemcpyHostToDevice);

			   //calling order10 kernel
			   Order10FkKernel<<<1, neqns>>>(device_x_total, device_x_not, device_f_not, h, device_f);

			   //WriteBack of x_total 
			   cudaMemcpy(x_total, device_x_total, arraySize*sizeof(double), cudaMemcpyDeviceToHost);
			   
			  //***************************************************************************************************************************************************
              ////////////////////    AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //der(t0 + a1*h, x1, f1);
              //der(t0 + a2*h, x2, f2);    //  now we get the fk's to be used in the 12th order method
              //der(t0 + a3*h, x3, f3);
              //der(t0 + a4*h, x4, f4);    // i.e., obtain derivatives at the five internal points needed for 12th order method
              //der(t0 + a5*h, x5, f5);
			  //********************************************************************************************************************
			  numOfXArrays=5;  //because we are passing in X1-X5
			  
			  cudaMemcpy(device_x_total, x_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
			  //kernel call
			  derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
			  //copying data from device to host
			  cudaMemcpy(f_total, device_f, arraySize*sizeof(double), cudaMemcpyDeviceToHost);
			  
			  //****************************************************************************************************************************

              ////////////////////   END OF PARALLEL SECTION OF CODE  ///////////////////////
              for (iter = 0; iter<itermax12; iter++) {  // now we can iterate to improve the values at the five internal points
                     ////////////////////   THIS CAN BE DONE IN PARALLEL   ///////////////////////
                     //for (int i = 0; i<neqns; i++) {  // each time, we recompute the internal xk values used in the 12th order method
                     //      x1[i] = x0[i] + h*(bh10*f0[i] + bh11*f1[i] + bh12*f2[i] + bh13*f3[i] + bh14*f4[i] + bh15*f5[i]);
                     //      x2[i] = x0[i] + h*(bh20*f0[i] + bh21*f1[i] + bh22*f2[i] + bh23*f3[i] + bh24*f4[i] + bh25*f5[i]);
                     //      x3[i] = x0[i] + h*(bh30*f0[i] + bh31*f1[i] + bh32*f2[i] + bh33*f3[i] + bh34*f4[i] + bh35*f5[i]);
                     //      x4[i] = x0[i] + h*(bh40*f0[i] + bh41*f1[i] + bh42*f2[i] + bh43*f3[i] + bh44*f4[i] + bh45*f5[i]);
                     //      x5[i] = x0[i] + h*(bh50*f0[i] + bh51*f1[i] + bh52*f2[i] + bh53*f3[i] + bh54*f4[i] + bh55*f5[i]);
                     //}
				  cudaMemcpy(device_f, f_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
				  cudaMemcpy(device_x_not, x0, arraySize*sizeof(double), cudaMemcpyHostToDevice);
				  cudaMemcpy(device_f_not, f0, arraySize*sizeof(double), cudaMemcpyHostToDevice);
				  Order12Kernel<<<1,neqns>>>(device_x_total, device_x_not, device_f_not, h, device_f);
			      cudaMemcpy(x_total, device_x_total, arraySize*sizeof(double), cudaMemcpyDeviceToHost);

                     ////////////////////  AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
                     //der(t0 + a1*h, x1, f1);  // once again, obtain derivatives at the five internal points of the 12th order method
                     //der(t0 + a2*h, x2, f2);
                     //der(t0 + a3*h, x3, f3);
                     //der(t0 + a4*h, x4, f4);
                     //der(t0 + a5*h, x5, f5);
                     ////////////////////   END OF PARALLEL SECTION OF CODE  ///////////////////////
					 //*******************************************************************************************************************
						
						cudaMemcpy(device_x_total, x_total, arraySize*sizeof(double), cudaMemcpyHostToDevice);
						//kernel call
						derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
						//copying data from device to host
						cudaMemcpy(f_total, device_f, arraySize*sizeof(double), cudaMemcpyDeviceToHost);
						
			  }

			   cudaFree(device_x_total);
			  cudaFree(device_f);
			  cudaFree(device_x_not);
			  cudaFree(device_f_not);
			  memcpy(f1,f_total, 2*sizeof(double));
			  memcpy(f2,f_total +2, 2*sizeof(double));
			  memcpy(f3,f_total +4, 2 *sizeof(double));
			  memcpy(f4, f_total +6, 2*sizeof(double));
			  memcpy(f5, f_total +8, 2*sizeof(double));
			  memcpy(x1,x_total, 2*sizeof(double));
			  memcpy(x2,x_total +2, 2*sizeof(double));
			  memcpy(x3,x_total +4, 2 *sizeof(double));
			  memcpy(x4, x_total +6, 2*sizeof(double));
			  memcpy(x5, x_total +8, 2*sizeof(double));
              for (int i = 0; i<neqns; i++) {  // iteration complete, so now compute final base value for 12th order method
                     x6[i] = x0[i] + h*(bh60*f0[i] + bh61*f1[i] + bh62*f2[i] + bh63*f3[i] + bh64*f4[i] + bh65*f5[i]);
              }
              der(t0 + ah6*h, x6, f6);  // and get the derivative there
              for (int i = 0; i<neqns; i++) {  // now, compute the final 12th order approximation to the solution at the end of the step
                     xn12[i] = x0[i] + h*(ch0*f0[i] + ch1*f1[i] + ch2*f2[i] + ch3*f3[i] + ch4*f4[i] + ch5*f5[i] + ch6*f6[i]);  // now compute final 12th order answer
              }
              printf("      The estimates of the errors in the 10-th order method by differencing with 12-th order method results are %e      and    %e\n", xn10[0] - xn12[0], xn10[1] - xn12[1]);
              if (sho) {
                     printf("12th order iterations = %d, t = %8.5lf, xn12[0] = %18.15lf, xn12[1] = %18.15lf, error[0] = %e, error[1] = %e\n",
                           iter, t0 + h, xn12[0], xn12[1], xn12[0] - sin(t0 + h), xn12[1] - cos(t0 + h));
              }
              else {
                     printf("12th order iterations = %d, t = %8.5lf, xn12[0] = %18.15lf, xn12[1] = %18.15lf\n",
                           iter, t0 + h, xn12[0], xn12[1]);
              }
              est = 1.0e-30;
              for (int i = 0; i<neqns; i++) {  // now, just update the solution to prepare for the next step
                     esti = xn10[i] - xn12[i];
                     est = est + esti*esti;
              }
              est = sqrt(est);  // sqrt of the sum of the squares of the errors in each component of the solution at t0 + h
              hnew = h * pow(tol10 / est, 0.1);
              if (est < tol) {  // if error estimate is less than the error tolerance, then the step succeeded
                     printf("The step succeeded since est = %e was less than tol = %e\n\n", est, tol);
                     for (int i = 0; i<neqns; i++) {  // now, just update the solution to prepare for the next step
                           x0[i] = xn12[i];
                     }
                     t0 = t0 + h;  // and update the independent variable
                     if (t0 / tf >= 0.99999999999999) finished = true;  // and if we have reached the final value, tf, set finished to true
              }
              else {
                     printf("The step failed since est = %e was not less than tol = %e\n\n", est, tol);
              }
              h = hnew;  // in any event, if not finished, we set the stepsize, h, to the new value, hnew
              if ((t0 + h) > tf) h = tf - t0;  // if new step takes us past final value, tf, reduce it to tf-t0
       }
}
 
int main(int argc, char* argv[])
{
	  cudaEvent_t start, stop;
	  cudaEventCreate(&start);
	  cudaEventCreate(&stop);
	  cudaEventRecord(start);
       printf("Testing Implicit RK1210 ");
       if (sho) {
              printf(" for simple harmonic oscillator example problem \n\n");
       }
       else {
              printf(" for predator - prey example problem \n\n");
       }
       rk1210();
	   cudaEventRecord(stop);
	   cudaEventSynchronize(stop);
	   float milliseconds =0;
	   cudaEventElapsedTime(&milliseconds, start, stop);
	   printf("Code took: %f milliseconds\n", milliseconds);
			  
	   getchar();
       return 0;
}

	.file	"tmpxft_00312ba2_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Cuda error in file '%s' in line %i : %s.\n"
	.text
	.globl	_Z10cudaAssert9cudaErrorPKci
	.type	_Z10cudaAssert9cudaErrorPKci, @function
_Z10cudaAssert9cudaErrorPKci:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movl	%edx, 12(%rsp)
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	movl	12(%rsp), %r8d
	movq	%rax, %r9
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	call	getchar@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z10cudaAssert9cudaErrorPKci, .-_Z10cudaAssert9cudaErrorPKci
	.globl	_Z3derdPdS_
	.type	_Z3derdPdS_, @function
_Z3derdPdS_:
.LFB2028:
	.cfi_startproc
	endbr64
	movsd	8(%rdi), %xmm0
	movsd	%xmm0, (%rsi)
	movsd	(%rdi), %xmm0
	xorps	.LC1(%rip), %xmm0
	movsd	%xmm0, 8(%rsi)
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z3derdPdS_, .-_Z3derdPdS_
	.globl	_Z30__device_stub__Z9derKernelPdS_PdS_
	.type	_Z30__device_stub__Z9derKernelPdS_PdS_, @function
_Z30__device_stub__Z9derKernelPdS_PdS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9derKernelPdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L9:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z30__device_stub__Z9derKernelPdS_PdS_, .-_Z30__device_stub__Z9derKernelPdS_PdS_
	.globl	_Z9derKernelPdS_
	.type	_Z9derKernelPdS_, @function
_Z9derKernelPdS_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z9derKernelPdS_PdS_
	.cfi_endproc
.LFE2056:
	.size	_Z9derKernelPdS_, .-_Z9derKernelPdS_
	.globl	_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d
	.type	_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d, @function
_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movsd	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11guessKernelPdS_S_d(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L14:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d, .-_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d
	.globl	_Z11guessKernelPdS_S_d
	.type	_Z11guessKernelPdS_S_d, @function
_Z11guessKernelPdS_S_d:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d
	.cfi_endproc
.LFE2058:
	.size	_Z11guessKernelPdS_S_d, .-_Z11guessKernelPdS_S_d
	.globl	_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_
	.type	_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_, @function
_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z13order10KernelPdS_S_dS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L19:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_, .-_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_
	.globl	_Z13order10KernelPdS_S_dS_
	.type	_Z13order10KernelPdS_S_dS_, @function
_Z13order10KernelPdS_S_dS_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_
	.cfi_endproc
.LFE2060:
	.size	_Z13order10KernelPdS_S_dS_, .-_Z13order10KernelPdS_S_dS_
	.globl	_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_
	.type	_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_, @function
_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z15Order10FkKernelPdS_S_dS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L24:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_, .-_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_
	.globl	_Z15Order10FkKernelPdS_S_dS_
	.type	_Z15Order10FkKernelPdS_S_dS_, @function
_Z15Order10FkKernelPdS_S_dS_:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_
	.cfi_endproc
.LFE2062:
	.size	_Z15Order10FkKernelPdS_S_dS_, .-_Z15Order10FkKernelPdS_S_dS_
	.globl	_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_
	.type	_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_, @function
_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z13Order12KernelPdS_S_dS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L29:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_, .-_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_
	.globl	_Z13Order12KernelPdS_S_dS_
	.type	_Z13Order12KernelPdS_S_dS_, @function
_Z13Order12KernelPdS_S_dS_:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_
	.cfi_endproc
.LFE2064:
	.size	_Z13Order12KernelPdS_S_dS_, .-_Z13Order12KernelPdS_S_dS_
	.section	.rodata.str1.1
.LC5:
	.string	"Initial conditions are  t0 = %8.5lf, x0[0] = %18.15lf, x0[1] = %18.15lf\n"
.LC6:
	.string	"iter = %d\n"
.LC15:
	.string	"10th order iterations = %d, t = %8.5lf, xn10[0] = %18.15lf, xn10[1] = %18.15lf, error[0] = %e, error[1] = %e\n"
.LC23:
	.string	"      The estimates of the errors in the 10-th order method by differencing with 12-th order method results are %e      and    %e\n"
.LC24:
	.string	"12th order iterations = %d, t = %8.5lf, xn12[0] = %18.15lf, xn12[1] = %18.15lf, error[0] = %e, error[1] = %e\n"
.LC29:
	.string	"The step succeeded since est = %e was less than tol = %e\n\n"
.LC32:
	.string	"The step failed since est = %e was not less than tol = %e\n\n"
	.text
	.globl	_Z6rk1210v
	.type	_Z6rk1210v, @function
_Z6rk1210v:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorps	%xmm1, %xmm1
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movaps	%xmm1, %xmm0
	movl	$4, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	$2147483649, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	addq	%rbp, %rbp
	movabsq	$4294967297, %rbx
	subq	$1336, %rsp
	.cfi_def_cfa_offset 1392
	movsd	.LC4(%rip), %xmm2
	movq	%fs:40, %rax
	movq	%rax, 1320(%rsp)
	xorl	%eax, %eax
	movb	$3, %al
	movq	$0x000000000, 200(%rsp)
	movsd	%xmm2, 208(%rsp)
	call	__printf_chk@PLT
	movsd	.LC3(%rip), %xmm7
	movq	$0x000000000, 48(%rsp)
	movsd	%xmm7, 8(%rsp)
.L53:
	movsd	208(%rsp), %xmm0
	leaq	144(%rsp), %rax
	movl	$80, %esi
	leaq	152(%rsp), %r15
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	leaq	200(%rsp), %r13
	leaq	600(%rsp), %r12
	movsd	%xmm0, 600(%rsp)
	movsd	200(%rsp), %xmm0
	xorps	.LC1(%rip), %xmm0
	movsd	%xmm0, 608(%rsp)
	call	cudaMalloc@PLT
	movl	$80, %esi
	movq	%r15, %rdi
	call	cudaMalloc@PLT
	leaq	160(%rsp), %rax
	movl	$80, %esi
	movq	%rax, %rdi
	movq	%rax, 64(%rsp)
	call	cudaMalloc@PLT
	movq	152(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	160(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, 188(%rsp)
	movl	$1, 196(%rsp)
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movsd	8(%rsp), %xmm0
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z36__device_stub__Z11guessKernelPdS_S_dPdS_S_d
.L35:
	leaq	1160(%rsp), %rax
	movl	$2, %ecx
	movl	$80, %edx
	movq	144(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	leaq	168(%rsp), %rax
	movl	$80, %esi
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rbx, 192(%rsp)
	movl	196(%rsp), %ecx
	movl	$1, %esi
	movl	%r14d, 188(%rsp)
	movq	188(%rsp), %rdx
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	168(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z30__device_stub__Z9derKernelPdS_PdS_
.L36:
	leaq	1240(%rsp), %rax
	movl	$2, %ecx
	movl	$80, %edx
	movq	168(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rax, 56(%rsp)
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	movq	%r15, %rdi
	movl	$80, %esi
	xorl	%r15d, %r15d
	call	cudaMalloc@PLT
	movq	64(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
.L39:
	movl	%r15d, %edx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	168(%rsp), %rdi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	160(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	152(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, 188(%rsp)
	movl	$1, 196(%rsp)
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	168(%rsp), %rcx
	movsd	8(%rsp), %xmm0
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z40__device_stub__Z13order10KernelPdS_S_dS_PdS_S_dS_
.L37:
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$80, %edx
	movq	144(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rbx, 192(%rsp)
	movl	196(%rsp), %ecx
	movl	$1, %esi
	movl	%r14d, 188(%rsp)
	movq	188(%rsp), %rdx
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	168(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z30__device_stub__Z9derKernelPdS_PdS_
.L38:
	movq	56(%rsp), %rdi
	movl	$2, %ecx
	movl	$80, %edx
	movq	168(%rsp), %rsi
	call	cudaMemcpy@PLT
	testl	%r15d, %r15d
	jne	.L66
	movl	$1, %r15d
	jmp	.L39
.L66:
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movups	1256(%rsp), %xmm7
	xorl	%eax, %eax
	movups	1240(%rsp), %xmm8
	movups	1272(%rsp), %xmm6
	movups	1288(%rsp), %xmm5
	movsd	.LC8(%rip), %xmm4
	movsd	.LC9(%rip), %xmm3
	movups	%xmm8, 680(%rsp)
	movsd	.LC10(%rip), %xmm2
	movsd	.LC11(%rip), %xmm1
	movups	%xmm7, 760(%rsp)
	movsd	.LC7(%rip), %xmm9
	movups	%xmm6, 840(%rsp)
	movups	%xmm5, 920(%rsp)
.L40:
	movsd	680(%rsp,%rax), %xmm10
	movsd	(%r12,%rax), %xmm0
	mulsd	%xmm4, %xmm10
	mulsd	%xmm9, %xmm0
	addsd	%xmm10, %xmm0
	movsd	760(%rsp,%rax), %xmm10
	mulsd	%xmm3, %xmm10
	addsd	%xmm10, %xmm0
	movsd	840(%rsp,%rax), %xmm10
	mulsd	%xmm2, %xmm10
	addsd	%xmm10, %xmm0
	movsd	920(%rsp,%rax), %xmm10
	mulsd	%xmm1, %xmm10
	addsd	%xmm10, %xmm0
	mulsd	8(%rsp), %xmm0
	addsd	0(%r13,%rax), %xmm0
	movsd	%xmm0, 280(%rsp,%rax)
	addq	$8, %rax
	cmpq	$16, %rax
	jne	.L40
	movsd	288(%rsp), %xmm0
	movsd	.LC12(%rip), %xmm1
	xorl	%eax, %eax
	movsd	.LC13(%rip), %xmm2
	movsd	.LC14(%rip), %xmm3
	movsd	%xmm0, 1000(%rsp)
	movsd	280(%rsp), %xmm0
	xorps	.LC1(%rip), %xmm0
	movsd	%xmm0, 1008(%rsp)
.L41:
	movsd	680(%rsp,%rax), %xmm4
	movsd	(%r12,%rax), %xmm0
	mulsd	%xmm2, %xmm4
	mulsd	%xmm1, %xmm0
	addsd	%xmm4, %xmm0
	movsd	760(%rsp,%rax), %xmm4
	mulsd	%xmm3, %xmm4
	addsd	%xmm4, %xmm0
	movsd	840(%rsp,%rax), %xmm4
	mulsd	%xmm3, %xmm4
	addsd	%xmm4, %xmm0
	movsd	920(%rsp,%rax), %xmm4
	mulsd	%xmm2, %xmm4
	addsd	%xmm4, %xmm0
	movsd	1000(%rsp,%rax), %xmm4
	mulsd	%xmm1, %xmm4
	addsd	%xmm4, %xmm0
	mulsd	8(%rsp), %xmm0
	addsd	0(%r13,%rax), %xmm0
	movsd	%xmm0, 440(%rsp,%rax)
	addq	$8, %rax
	cmpq	$16, %rax
	jne	.L41
	movaps	%xmm7, 80(%rsp)
	leaq	136(%rsp), %rdi
	movsd	448(%rsp), %xmm7
	leaq	128(%rsp), %rsi
	movaps	%xmm8, 112(%rsp)
	leaq	1240(%rsp), %r14
	movsd	%xmm7, 40(%rsp)
	movsd	8(%rsp), %xmm7
	addsd	48(%rsp), %xmm7
	movaps	%xmm5, 16(%rsp)
	movaps	%xmm6, 96(%rsp)
	movaps	%xmm7, %xmm0
	movsd	%xmm7, 32(%rsp)
	call	sincos@PLT
	movsd	40(%rsp), %xmm4
	movsd	40(%rsp), %xmm2
	movl	$2, %edx
	movsd	128(%rsp), %xmm7
	movsd	32(%rsp), %xmm0
	movl	$2, %edi
	movb	$5, %al
	movsd	440(%rsp), %xmm6
	leaq	.LC15(%rip), %rsi
	movsd	%xmm7, 64(%rsp)
	subsd	64(%rsp), %xmm4
	movsd	136(%rsp), %xmm7
	movaps	%xmm6, %xmm3
	movaps	%xmm6, %xmm1
	movsd	%xmm6, 56(%rsp)
	subsd	%xmm7, %xmm3
	movsd	%xmm7, 72(%rsp)
	call	__printf_chk@PLT
	movaps	96(%rsp), %xmm6
	movaps	112(%rsp), %xmm8
	leaq	144(%rsp), %rdi
	movaps	80(%rsp), %xmm7
	movaps	16(%rsp), %xmm5
	movl	$80, %esi
	movups	%xmm6, 1272(%rsp)
	movups	1000(%rsp), %xmm6
	movups	%xmm8, 1240(%rsp)
	movups	%xmm7, 1256(%rsp)
	movups	%xmm5, 1288(%rsp)
	movups	%xmm6, 1304(%rsp)
	call	cudaMalloc@PLT
	leaq	168(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	leaq	152(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	leaq	160(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	movq	168(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	152(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	160(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, 188(%rsp)
	movl	$1, 196(%rsp)
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	168(%rsp), %rcx
	movsd	8(%rsp), %xmm0
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z42__device_stub__Z15Order10FkKernelPdS_S_dS_PdS_S_dS_
.L42:
	movq	144(%rsp), %rsi
	movl	$2, %ecx
	movl	$80, %edx
	leaq	1160(%rsp), %r12
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	144(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movabsq	$4294967301, %rax
	movl	$1, 196(%rsp)
	movq	%rax, %rdx
	movq	%rax, 188(%rsp)
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	168(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z30__device_stub__Z9derKernelPdS_PdS_
.L43:
	movq	168(%rsp), %rsi
	movl	$2, %ecx
	movl	$80, %edx
	movq	%r14, %rdi
	leaq	200(%rsp), %r13
	leaq	600(%rsp), %r15
	call	cudaMemcpy@PLT
	movq	168(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	152(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	160(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, 188(%rsp)
	movl	$1, 196(%rsp)
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movq	168(%rsp), %rcx
	movsd	8(%rsp), %xmm0
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z40__device_stub__Z13Order12KernelPdS_S_dS_PdS_S_dS_
.L44:
	movq	144(%rsp), %rsi
	movl	$2, %ecx
	movl	$80, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	144(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movabsq	$4294967301, %rax
	movl	$1, 196(%rsp)
	movq	%rax, %rdx
	movq	%rax, 188(%rsp)
	movq	%rbx, 176(%rsp)
	movl	$1, 184(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	movq	168(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z30__device_stub__Z9derKernelPdS_PdS_
.L45:
	movq	168(%rsp), %rsi
	movl	$2, %ecx
	movl	$80, %edx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movups	1240(%rsp), %xmm7
	xorl	%r8d, %r8d
	movups	1256(%rsp), %xmm5
	movups	1272(%rsp), %xmm6
	movups	1304(%rsp), %xmm1
	leaq	680(%rsp), %rdi
	leaq	760(%rsp), %rsi
	movups	%xmm7, 680(%rsp)
	movups	1288(%rsp), %xmm7
	leaq	840(%rsp), %rcx
	leaq	920(%rsp), %rdx
	movups	%xmm5, 760(%rsp)
	movups	1224(%rsp), %xmm5
	leaq	1000(%rsp), %rax
	movups	%xmm6, 840(%rsp)
	movups	%xmm7, 920(%rsp)
	movups	%xmm1, 1000(%rsp)
	movups	%xmm5, 280(%rsp)
.L46:
	movsd	(%rdi,%r8), %xmm2
	xorps	%xmm0, %xmm0
	movsd	.LC16(%rip), %xmm1
	mulsd	(%r15,%r8), %xmm0
	movsd	(%rsi,%r8), %xmm3
	mulsd	%xmm1, %xmm2
	mulsd	(%rax,%r8), %xmm1
	addsd	%xmm2, %xmm0
	movsd	.LC17(%rip), %xmm2
	mulsd	%xmm2, %xmm3
	mulsd	(%rdx,%r8), %xmm2
	addsd	%xmm3, %xmm0
	movsd	.LC18(%rip), %xmm3
	mulsd	(%rcx,%r8), %xmm3
	addsd	%xmm3, %xmm0
	addsd	%xmm2, %xmm0
	addsd	%xmm1, %xmm0
	mulsd	8(%rsp), %xmm0
	addsd	0(%r13,%r8), %xmm0
	movsd	%xmm0, 360(%rsp,%r8)
	addq	$8, %r8
	cmpq	$16, %r8
	jne	.L46
	movsd	368(%rsp), %xmm0
	movsd	.LC19(%rip), %xmm1
	xorl	%r8d, %r8d
	movsd	.LC20(%rip), %xmm2
	movsd	.LC21(%rip), %xmm3
	movsd	%xmm0, 1080(%rsp)
	movsd	.LC22(%rip), %xmm5
	movsd	360(%rsp), %xmm0
	xorps	.LC1(%rip), %xmm0
	movsd	%xmm0, 1088(%rsp)
.L47:
	movsd	(%r15,%r8), %xmm0
	movsd	(%rdi,%r8), %xmm4
	mulsd	%xmm1, %xmm0
	mulsd	%xmm2, %xmm4
	addsd	%xmm4, %xmm0
	movsd	(%rsi,%r8), %xmm4
	mulsd	%xmm3, %xmm4
	addsd	%xmm4, %xmm0
	movsd	(%rcx,%r8), %xmm4
	mulsd	%xmm5, %xmm4
	addsd	%xmm4, %xmm0
	movsd	(%rdx,%r8), %xmm4
	mulsd	%xmm3, %xmm4
	addsd	%xmm4, %xmm0
	movsd	(%rax,%r8), %xmm4
	mulsd	%xmm2, %xmm4
	addsd	%xmm4, %xmm0
	movsd	1080(%rsp,%r8), %xmm4
	mulsd	%xmm1, %xmm4
	addsd	%xmm4, %xmm0
	mulsd	8(%rsp), %xmm0
	addsd	0(%r13,%r8), %xmm0
	movsd	%xmm0, 520(%rsp,%r8)
	addq	$8, %r8
	cmpq	$16, %r8
	jne	.L47
	movsd	528(%rsp), %xmm7
	movsd	40(%rsp), %xmm5
	movl	$2, %edi
	movb	$2, %al
	movsd	520(%rsp), %xmm3
	movsd	56(%rsp), %xmm6
	leaq	.LC23(%rip), %rsi
	subsd	%xmm7, %xmm5
	movsd	%xmm7, 16(%rsp)
	subsd	%xmm3, %xmm6
	movsd	%xmm3, 40(%rsp)
	movaps	%xmm5, %xmm1
	movsd	%xmm5, 80(%rsp)
	movaps	%xmm6, %xmm0
	movsd	%xmm6, 56(%rsp)
	call	__printf_chk@PLT
	movsd	16(%rsp), %xmm4
	movl	$1, %edx
	movb	$5, %al
	subsd	64(%rsp), %xmm4
	movsd	40(%rsp), %xmm3
	leaq	.LC24(%rip), %rsi
	movl	$2, %edi
	subsd	72(%rsp), %xmm3
	movsd	16(%rsp), %xmm2
	movsd	40(%rsp), %xmm1
	movsd	32(%rsp), %xmm0
	call	__printf_chk@PLT
	movsd	80(%rsp), %xmm5
	movsd	56(%rsp), %xmm6
	mulsd	%xmm5, %xmm5
	mulsd	%xmm6, %xmm6
	addsd	.LC25(%rip), %xmm6
	addsd	%xmm6, %xmm5
	movaps	%xmm5, %xmm0
	call	sqrt@PLT
	movsd	.LC26(%rip), %xmm1
	movaps	%xmm0, %xmm2
	movsd	.LC27(%rip), %xmm0
	movsd	%xmm2, 56(%rsp)
	divsd	%xmm2, %xmm0
	call	pow@PLT
	movsd	56(%rsp), %xmm2
	mulsd	8(%rsp), %xmm0
	movsd	.LC28(%rip), %xmm1
	comisd	%xmm2, %xmm1
	movsd	%xmm0, 8(%rsp)
	movaps	%xmm2, %xmm0
	jbe	.L64
	leaq	.LC29(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	call	__printf_chk@PLT
	movsd	32(%rsp), %xmm0
	divsd	.LC30(%rip), %xmm0
	comisd	.LC31(%rip), %xmm0
	movsd	40(%rsp), %xmm5
	movsd	16(%rsp), %xmm3
	movsd	32(%rsp), %xmm6
	movsd	%xmm5, 200(%rsp)
	setnb	%al
	movsd	%xmm3, 208(%rsp)
	movsd	%xmm6, 48(%rsp)
	jmp	.L50
.L64:
	leaq	.LC32(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L50:
	movsd	48(%rsp), %xmm0
	addsd	8(%rsp), %xmm0
	comisd	.LC30(%rip), %xmm0
	jbe	.L51
	movsd	.LC30(%rip), %xmm7
	subsd	48(%rsp), %xmm7
	movsd	%xmm7, 8(%rsp)
.L51:
	movl	$5, %r14d
	testb	%al, %al
	je	.L53
	movq	1320(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$1336, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z6rk1210v, .-_Z6rk1210v
	.section	.rodata.str1.1
.LC33:
	.string	"Testing Implicit RK1210 "
.LC34:
	.string	" for simple harmonic oscillator example problem \n\n"
.LC36:
	.string	"Code took: %f milliseconds\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	.LC33(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC34(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	_Z6rk1210v
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$0x00000000, 4(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC36(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	call	getchar@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L68
	call	__stack_chk_fail@PLT
.L68:
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC37:
	.string	"_Z13Order12KernelPdS_S_dS_"
.LC38:
	.string	"_Z15Order10FkKernelPdS_S_dS_"
.LC39:
	.string	"_Z13order10KernelPdS_S_dS_"
.LC40:
	.string	"_Z11guessKernelPdS_S_d"
.LC41:
	.string	"_Z9derKernelPdS_"
.LC42:
	.string	"a1"
.LC43:
	.string	"a2"
.LC44:
	.string	"a3"
.LC45:
	.string	"a4"
.LC46:
	.string	"b10"
.LC47:
	.string	"b11"
.LC48:
	.string	"b12"
.LC49:
	.string	"b13"
.LC50:
	.string	"b14"
.LC51:
	.string	"b20"
.LC52:
	.string	"b21"
.LC53:
	.string	"b22"
.LC54:
	.string	"b23"
.LC55:
	.string	"b24"
.LC56:
	.string	"b30"
.LC57:
	.string	"b31"
.LC58:
	.string	"b32"
.LC59:
	.string	"b33"
.LC60:
	.string	"b34"
.LC61:
	.string	"b40"
.LC62:
	.string	"b41"
.LC63:
	.string	"b42"
.LC64:
	.string	"b43"
.LC65:
	.string	"b44"
.LC66:
	.string	"g10"
.LC67:
	.string	"g11"
.LC68:
	.string	"g12"
.LC69:
	.string	"g13"
.LC70:
	.string	"g14"
.LC71:
	.string	"g15"
.LC72:
	.string	"g20"
.LC73:
	.string	"g21"
.LC74:
	.string	"g22"
.LC75:
	.string	"g23"
.LC76:
	.string	"g24"
.LC77:
	.string	"g25"
.LC78:
	.string	"g30"
.LC79:
	.string	"g31"
.LC80:
	.string	"g32"
.LC81:
	.string	"g33"
.LC82:
	.string	"g34"
.LC83:
	.string	"g35"
.LC84:
	.string	"g40"
.LC85:
	.string	"g41"
.LC86:
	.string	"g42"
.LC87:
	.string	"g43"
.LC88:
	.string	"g44"
.LC89:
	.string	"g45"
.LC90:
	.string	"g50"
.LC91:
	.string	"g51"
.LC92:
	.string	"g52"
.LC93:
	.string	"g53"
.LC94:
	.string	"g54"
.LC95:
	.string	"g55"
.LC96:
	.string	"bh10"
.LC97:
	.string	"bh11"
.LC98:
	.string	"bh12"
.LC99:
	.string	"bh13"
.LC100:
	.string	"bh14"
.LC101:
	.string	"bh15"
.LC102:
	.string	"bh20"
.LC103:
	.string	"bh21"
.LC104:
	.string	"bh22"
.LC105:
	.string	"bh23"
.LC106:
	.string	"bh24"
.LC107:
	.string	"bh25"
.LC108:
	.string	"bh30"
.LC109:
	.string	"bh31"
.LC110:
	.string	"bh32"
.LC111:
	.string	"bh33"
.LC112:
	.string	"bh34"
.LC113:
	.string	"bh35"
.LC114:
	.string	"bh40"
.LC115:
	.string	"bh41"
.LC116:
	.string	"bh42"
.LC117:
	.string	"bh43"
.LC118:
	.string	"bh44"
.LC119:
	.string	"bh45"
.LC120:
	.string	"bh50"
.LC121:
	.string	"bh51"
.LC122:
	.string	"bh52"
.LC123:
	.string	"bh53"
.LC124:
	.string	"bh54"
.LC125:
	.string	"bh55"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13Order12KernelPdS_S_dS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15Order10FkKernelPdS_S_dS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13order10KernelPdS_S_dS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC40(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11guessKernelPdS_S_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9derKernelPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	movl	$8, %r9d
	leaq	_ZL2a1(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL2a2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC44(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL2a3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC45(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL2a4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC46(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b10(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b11(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC48(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b12(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC49(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b13(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC50(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b14(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC51(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b20(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC52(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b21(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC53(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b22(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC54(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b23(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b24(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b30(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b31(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b32(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b33(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b34(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b40(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b41(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC63(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b42(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC64(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b43(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC65(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3b44(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC66(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g10(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC67(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g11(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC68(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g12(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC69(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g13(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC70(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g14(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC71(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g15(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC72(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g20(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC73(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g21(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC74(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g22(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC75(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g23(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC76(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g24(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC77(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g25(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC78(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g30(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC79(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g31(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC80(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g32(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC81(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g33(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC82(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g34(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC83(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g35(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC84(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g40(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC85(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g41(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC86(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g42(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC87(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g43(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC88(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g44(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC89(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g45(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC90(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g50(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC91(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g51(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC92(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g52(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC93(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g53(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC94(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g54(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC95(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3g55(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC96(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh10(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC97(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh11(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC98(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh12(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC99(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh13(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC100(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh14(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC101(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh15(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC102(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh20(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC103(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh21(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC104(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh22(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC105(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh23(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC106(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh24(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC107(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh25(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC108(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh30(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC109(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh31(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC110(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh32(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC111(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh33(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC112(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh34(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC113(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh35(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC114(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh40(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC115(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh41(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC116(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh42(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC117(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh43(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC118(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh44(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC119(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh45(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC120(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh50(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC121(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh51(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC122(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh52(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC123(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh53(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC124(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4bh54(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC125(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$8, %r9d
	movq	%rdx, %rcx
	leaq	_ZL4bh55(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2066:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL4bh55
	.comm	_ZL4bh55,8,8
	.local	_ZL4bh54
	.comm	_ZL4bh54,8,8
	.local	_ZL4bh53
	.comm	_ZL4bh53,8,8
	.local	_ZL4bh52
	.comm	_ZL4bh52,8,8
	.local	_ZL4bh51
	.comm	_ZL4bh51,8,8
	.local	_ZL4bh50
	.comm	_ZL4bh50,8,8
	.local	_ZL4bh45
	.comm	_ZL4bh45,8,8
	.local	_ZL4bh44
	.comm	_ZL4bh44,8,8
	.local	_ZL4bh43
	.comm	_ZL4bh43,8,8
	.local	_ZL4bh42
	.comm	_ZL4bh42,8,8
	.local	_ZL4bh41
	.comm	_ZL4bh41,8,8
	.local	_ZL4bh40
	.comm	_ZL4bh40,8,8
	.local	_ZL4bh35
	.comm	_ZL4bh35,8,8
	.local	_ZL4bh34
	.comm	_ZL4bh34,8,8
	.local	_ZL4bh33
	.comm	_ZL4bh33,8,8
	.local	_ZL4bh32
	.comm	_ZL4bh32,8,8
	.local	_ZL4bh31
	.comm	_ZL4bh31,8,8
	.local	_ZL4bh30
	.comm	_ZL4bh30,8,8
	.local	_ZL4bh25
	.comm	_ZL4bh25,8,8
	.local	_ZL4bh24
	.comm	_ZL4bh24,8,8
	.local	_ZL4bh23
	.comm	_ZL4bh23,8,8
	.local	_ZL4bh22
	.comm	_ZL4bh22,8,8
	.local	_ZL4bh21
	.comm	_ZL4bh21,8,8
	.local	_ZL4bh20
	.comm	_ZL4bh20,8,8
	.local	_ZL4bh15
	.comm	_ZL4bh15,8,8
	.local	_ZL4bh14
	.comm	_ZL4bh14,8,8
	.local	_ZL4bh13
	.comm	_ZL4bh13,8,8
	.local	_ZL4bh12
	.comm	_ZL4bh12,8,8
	.local	_ZL4bh11
	.comm	_ZL4bh11,8,8
	.local	_ZL4bh10
	.comm	_ZL4bh10,8,8
	.local	_ZL3g55
	.comm	_ZL3g55,8,8
	.local	_ZL3g54
	.comm	_ZL3g54,8,8
	.local	_ZL3g53
	.comm	_ZL3g53,8,8
	.local	_ZL3g52
	.comm	_ZL3g52,8,8
	.local	_ZL3g51
	.comm	_ZL3g51,8,8
	.local	_ZL3g50
	.comm	_ZL3g50,8,8
	.local	_ZL3g45
	.comm	_ZL3g45,8,8
	.local	_ZL3g44
	.comm	_ZL3g44,8,8
	.local	_ZL3g43
	.comm	_ZL3g43,8,8
	.local	_ZL3g42
	.comm	_ZL3g42,8,8
	.local	_ZL3g41
	.comm	_ZL3g41,8,8
	.local	_ZL3g40
	.comm	_ZL3g40,8,8
	.local	_ZL3g35
	.comm	_ZL3g35,8,8
	.local	_ZL3g34
	.comm	_ZL3g34,8,8
	.local	_ZL3g33
	.comm	_ZL3g33,8,8
	.local	_ZL3g32
	.comm	_ZL3g32,8,8
	.local	_ZL3g31
	.comm	_ZL3g31,8,8
	.local	_ZL3g30
	.comm	_ZL3g30,8,8
	.local	_ZL3g25
	.comm	_ZL3g25,8,8
	.local	_ZL3g24
	.comm	_ZL3g24,8,8
	.local	_ZL3g23
	.comm	_ZL3g23,8,8
	.local	_ZL3g22
	.comm	_ZL3g22,8,8
	.local	_ZL3g21
	.comm	_ZL3g21,8,8
	.local	_ZL3g20
	.comm	_ZL3g20,8,8
	.local	_ZL3g15
	.comm	_ZL3g15,8,8
	.local	_ZL3g14
	.comm	_ZL3g14,8,8
	.local	_ZL3g13
	.comm	_ZL3g13,8,8
	.local	_ZL3g12
	.comm	_ZL3g12,8,8
	.local	_ZL3g11
	.comm	_ZL3g11,8,8
	.local	_ZL3g10
	.comm	_ZL3g10,8,8
	.local	_ZL3b44
	.comm	_ZL3b44,8,8
	.local	_ZL3b43
	.comm	_ZL3b43,8,8
	.local	_ZL3b42
	.comm	_ZL3b42,8,8
	.local	_ZL3b41
	.comm	_ZL3b41,8,8
	.local	_ZL3b40
	.comm	_ZL3b40,8,8
	.local	_ZL3b34
	.comm	_ZL3b34,8,8
	.local	_ZL3b33
	.comm	_ZL3b33,8,8
	.local	_ZL3b32
	.comm	_ZL3b32,8,8
	.local	_ZL3b31
	.comm	_ZL3b31,8,8
	.local	_ZL3b30
	.comm	_ZL3b30,8,8
	.local	_ZL3b24
	.comm	_ZL3b24,8,8
	.local	_ZL3b23
	.comm	_ZL3b23,8,8
	.local	_ZL3b22
	.comm	_ZL3b22,8,8
	.local	_ZL3b21
	.comm	_ZL3b21,8,8
	.local	_ZL3b20
	.comm	_ZL3b20,8,8
	.local	_ZL3b14
	.comm	_ZL3b14,8,8
	.local	_ZL3b13
	.comm	_ZL3b13,8,8
	.local	_ZL3b12
	.comm	_ZL3b12,8,8
	.local	_ZL3b11
	.comm	_ZL3b11,8,8
	.local	_ZL3b10
	.comm	_ZL3b10,8,8
	.local	_ZL2a4
	.comm	_ZL2a4,8,8
	.local	_ZL2a3
	.comm	_ZL2a3,8,8
	.local	_ZL2a2
	.comm	_ZL2a2,8,8
	.local	_ZL2a1
	.comm	_ZL2a1,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	0
	.long	-2147483648
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	1413754136
	.long	1072243195
	.align 8
.LC4:
	.long	0
	.long	1072693248
	.align 8
.LC7:
	.long	286331153
	.long	1068568849
	.align 8
.LC8:
	.long	1992731660
	.long	1069292759
	.align 8
.LC9:
	.long	536417629
	.long	1071114486
	.align 8
.LC10:
	.long	733056314
	.long	1070019501
	.align 8
.LC11:
	.long	674772159
	.long	1070674361
	.align 8
.LC12:
	.long	286331153
	.long	1067520273
	.align 8
.LC13:
	.long	99213250
	.long	1070086383
	.align 8
.LC14:
	.long	1525214717
	.long	1070711142
	.align 8
.LC16:
	.long	1233567931
	.long	1070141600
	.align 8
.LC17:
	.long	1858808522
	.long	1069708414
	.align 8
.LC18:
	.long	1202590843
	.long	1070889697
	.align 8
.LC19:
	.long	409044505
	.long	1066951046
	.align 8
.LC20:
	.long	-1727638545
	.long	1069660036
	.align 8
.LC21:
	.long	1629467864
	.long	1070309815
	.align 8
.LC22:
	.long	-2053403412
	.long	1070544166
	.align 8
.LC25:
	.long	-18103648
	.long	968116299
	.align 8
.LC26:
	.long	-1717986918
	.long	1069128089
	.align 8
.LC27:
	.long	-512138090
	.long	1034288511
	.align 8
.LC28:
	.long	-640172613
	.long	1037794527
	.align 8
.LC30:
	.long	1413754136
	.long	1075388923
	.align 8
.LC31:
	.long	-90
	.long	1072693247
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"

#include <hip/device_functions.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#define PI  3.1415926535897932
#define MAXEQNS    10       // maximum number of differential equations in the system
 
const int itermax10 = 2;    // number of iterations to use for rk10
const int itermax12 = 1;    // number of additional iterations to use for rk12
const int neqns = 2;        // number of differential equations in the system
const double tol = 1.0e-10; // the error tolerance
const double tol10 = tol / 10;
const bool sho = true;      // set sho to true if you want the simple harmonic oscillator results
// set sho to false, if you want the predator - prey results
 
// the following constants are the 10th order method's coefficients
const double  a0 = 0;
__constant__ double  a1 = 0.11747233803526765;
__constant__ double  a2 = 0.35738424175967745;
__constant__ double  a3 = 0.64261575824032255;
__constant__ double  a4 = 0.88252766196473235;
const double  a5 = 1.0000000000000000;
 
__constant__ double  b10 = 0.047323231137709573;
__constant__ double  b11 = 0.077952072407795078;
__constant__ double  b12 = -0.010133421269900587;
__constant__ double  b13 = 0.0028864915990617097;
__constant__ double  b14 = -0.00055603583939812082;
__constant__ double  b20 = 0.021779075831486075;
__constant__ double  b21 = 0.22367959757928498;
__constant__ double  b22 = 0.12204792759220492;
__constant__ double  b23 = -0.012091266674498959;
__constant__ double  b24 = 0.0019689074312004371;
__constant__ double  b30 = 0.044887590835180592;
__constant__ double  b31 = 0.15973856856089786;
__constant__ double  b32 = 0.32285378852557547;
__constant__ double  b33 = 0.12204792759220492;
__constant__ double  b34 = -0.0069121172735362915;
__constant__ double  b40 = 0.019343435528957094;
__constant__ double  b41 = 0.22312684732165494;
__constant__ double  b42 = 0.23418268877986459;
__constant__ double  b43 = 0.32792261792646064;
__constant__ double  b44 = 0.077952072407795078;
const double  b50 = 0.066666666666666667;
const double  b51 = 0.10981508874708385;
const double  b52 = 0.37359383699761912;
const double  b53 = 0.18126454003786724;
const double  b54 = 0.26865986755076313;
 
const double  c0 = 0.033333333333333333;
const double  c1 = 0.18923747814892349;
const double  c2 = 0.27742918851774318;
const double  c3 = 0.27742918851774318;
const double  c4 = 0.18923747814892349;
const double  c5 = 0.033333333333333333;
 
// the following coefficients allow us to get rk12 internal xk values from rk10 fk values
__constant__ double  g10 = 0.043407276098971173;
__constant__ double  g11 = 0.049891561330903419;
__constant__ double  g12 = -0.012483721919363355;
__constant__ double  g13 = 0.0064848904066894701;
__constant__ double  g14 = -0.0038158693974615597;
__constant__ double  g15 = 0.0014039153409773882;
__constant__ double  g20 = 0.030385164419638569;
__constant__ double  g21 = 0.19605322645426044;
__constant__ double  g22 = 0.047860687574395354;
__constant__ double  g23 = -0.012887249003100515;
__constant__ double  g24 = 0.0064058521980400821;
__constant__ double  g25 = -0.0022420783785910372;
__constant__ double  g30 = 0.032291666666666667;
__constant__ double  g31 = 0.19311806292811784;
__constant__ double  g32 = 0.25797759963091718;
__constant__ double  g33 = 0.019451588886825999;
__constant__ double  g34 = -0.0038805847791943522;
__constant__ double  g35 = 0.0010416666666666667;
__constant__ double  g40 = 0.035575411711924371;
__constant__ double  g41 = 0.18283162595088341;
__constant__ double  g42 = 0.29031643752084369;
__constant__ double  g43 = 0.22956850094334782;
__constant__ double  g44 = -0.0068157483053369507;
__constant__ double  g45 = 0.0029481689136947641;
__constant__ double  g50 = 0.031929417992355945;
__constant__ double  g51 = 0.19305334754638505;
__constant__ double  g52 = 0.27094429811105371;
__constant__ double  g53 = 0.28991291043710653;
__constant__ double  g54 = 0.13934591681802007;
__constant__ double  g55 = -0.010073942765637839;
const double  g60 = 0.033333333333333333;
const double  g61 = 0.18923747814892349;
const double  g62 = 0.27742918851774318;
const double  g63 = 0.27742918851774318;
const double  g64 = 0.18923747814892349;
const double  g65 = 0.033333333333333333;
 
// the following constants are the 12th order method's coefficients
const double  ah0 = 0.0;
const double  ah1 = 0.084888051860716535;
const double  ah2 = 0.26557560326464289;
const double  ah3 = 0.50000000000000000;
const double  ah4 = 0.73442439673535711;
const double  ah5 = 0.91511194813928346;
const double  ah6 = 1.0000000000000000;
 
__constant__ double  bh10 = 0.033684534770907752;
__constant__ double  bh11 = 0.057301749935629582;
__constant__ double  bh12 = -0.0082444880936983822;
__constant__ double  bh13 = 0.0029151263642014432;
__constant__ double  bh14 = -0.00096482361331657787;
__constant__ double  bh15 = 0.00019595249699271744;
__constant__ double  bh20 = 0.015902242088596380;
__constant__ double  bh21 = 0.16276437062291593;
__constant__ double  bh22 = 0.096031583397703751;
__constant__ double  bh23 = -0.011758319711158930;
__constant__ double  bh24 = 0.0032543514515832418;
__constant__ double  bh25 = -0.00061862458499748489;
__constant__ double  bh30 = 0.031250000000000000;
__constant__ double  bh31 = 0.11881843285766042;
__constant__ double  bh32 = 0.24868761828096535;
__constant__ double  bh33 = 0.11000000000000000;
__constant__ double  bh34 = -0.010410996557394222;
__constant__ double  bh35 = 0.0016549454187684515;
__constant__ double  bh40 = 0.015902242088596380;
__constant__ double  bh41 = 0.15809680304274781;
__constant__ double  bh42 = 0.18880881534382426;
__constant__ double  bh43 = 0.28087114502765051;
__constant__ double  bh44 = 0.096031583397703751;
__constant__ double  bh45 = -0.0052861921651656089;
__constant__ double  bh50 = 0.033684534770907752;
__constant__ double  bh51 = 0.11440754737426645;
__constant__ double  bh52 = 0.24657204460460206;
__constant__ double  bh53 = 0.20929436236889375;
__constant__ double  bh54 = 0.25385170908498387;
__constant__ double  bh55 = 0.057301749935629582;
const double  bh60 = 0;
const double  bh61 = 0.19581988897471611;
const double  bh62 = 0.14418011102528389;
const double  bh63 = 0.32000000000000000;
const double  bh64 = 0.14418011102528389;
const double  bh65 = 0.19581988897471611;
 
const double  ch0 = 0.023809523809523810;
const double  ch1 = 0.13841302368078297;
const double  ch2 = 0.21587269060493131;
const double  ch3 = 0.24380952380952381;
const double  ch4 = 0.21587269060493131;
const double  ch5 = 0.13841302368078297;
const double  ch6 = 0.023809523809523810;

#define cudaErrorCheck(call) { cudaAssert(call,__FILE__,__LINE__); }

void cudaAssert(const hipError_t err, const char *file, const int line)
{ 
    if( hipSuccess != err) {                                                
        fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",        
                file, line, hipGetErrorString(err) );
		getchar();
        exit(1);
    } 
}

//****************************************************************************

//Derivative kernel: takes pointers to x[], and f[] allocated on the device
__global__ void derKernel(double* device_x, double* device_f)
{
	//2 elements in device_x represent 2 elements from individual arrays X1-X4;
	//ie if thread id is 0 then the array number is 0x2 and work on elements tx*2 and tx*2 +1
	int tx = threadIdx.x;
	int xArrayNumber = tx *2;
	
		
			device_f[xArrayNumber] = device_x[xArrayNumber+1];
			__syncthreads();
			device_f[xArrayNumber+1] = -device_x[xArrayNumber];
			__syncthreads();
		
		
	
}
__global__ void guessKernel(double*device_X_Total, double* device_X_Not,double* device_F_Not, double h){

	device_X_Total[threadIdx.x] = device_X_Not[threadIdx.x] + a1 * h * device_F_Not[threadIdx.x];
	device_X_Total[threadIdx.x +2] = device_X_Not[threadIdx.x] + a2 * h * device_F_Not[threadIdx.x];
	device_X_Total[threadIdx.x +4] = device_X_Not[threadIdx.x] + a3 * h * device_F_Not[threadIdx.x];
	device_X_Total[threadIdx.x +6] = device_X_Not[threadIdx.x] + a4 * h * device_F_Not[threadIdx.x];
}
__global__ void order10Kernel(double*device_X_Total, double* device_X_Not, double *device_F_Not, double h, double *device_f)
{
	int tx = threadIdx.x;
	device_X_Total[tx]=device_X_Not[tx] + h*((b10 * device_F_Not[tx]) + (b11 * device_f[tx]) + (b12 * device_f[tx+2]) + (b13 * device_f[tx +4]) + (b14 * device_f[tx +6]));
	__syncthreads();
	device_X_Total[tx+2]=device_X_Not[tx] + h*((b20 * device_F_Not[tx]) + (b21 * device_f[tx]) + (b22 * device_f[tx+2]) + (b23 * device_f[tx +4]) + (b24 * device_f[tx +6]));
	__syncthreads();
	device_X_Total[tx+4]=device_X_Not[tx] + h*((b30 * device_F_Not[tx]) +( b31 * device_f[tx]) + (b32 * device_f[tx+2]) + (b33 * device_f[tx +4]) + (b34 * device_f[tx +6]));
	__syncthreads();
	device_X_Total[tx+6]=device_X_Not[tx] + h*((b40 * device_F_Not[tx]) + (b41 * device_f[tx]) +( b42 * device_f[tx+2]) + (b43 * device_f[tx +4]) +( b44 * device_f[tx +6]));
	__syncthreads();
	
}
__global__ void Order10FkKernel(double*device_X_Total, double* device_X_Not, double* device_F_Not, double h, double*device_f)
{

	int tx = threadIdx.x;
	device_X_Total[tx] = device_X_Not[tx] + h*((g10*device_F_Not[tx])+ (g11 * device_f[tx]) + (g12 * device_f[tx+2])+ (g13 * device_f[tx + 4]) + (g14 * device_f[tx+ 6])+ (g15 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+2] = device_X_Not[tx] + h*((g20*device_F_Not[tx])+ (g21 * device_f[tx]) + (g22 * device_f[tx+2])+ (g23 * device_f[tx + 4]) + (g24 * device_f[tx+ 6])+ (g25 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+4] = device_X_Not[tx] + h*((g30*device_F_Not[tx])+ (g31 * device_f[tx]) + (g32 * device_f[tx+2])+ (g33 * device_f[tx + 4]) + (g34 * device_f[tx+ 6])+ (g35 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+6] = device_X_Not[tx] + h*((g40*device_F_Not[tx])+ (g41 * device_f[tx]) + (g42 * device_f[tx+2])+ (g43 * device_f[tx + 4]) + (g44 * device_f[tx+ 6])+ (g45 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+8] = device_X_Not[tx] + h*((g50*device_F_Not[tx])+ (g51 * device_f[tx]) + (g52 * device_f[tx+2])+ (g53 * device_f[tx + 4]) + (g54 * device_f[tx+ 6])+ (g55 *device_f[tx+8]));
	__syncthreads();
}
__global__ void Order12Kernel(double*device_X_Total, double* device_X_Not, double* device_F_Not, double h, double*device_f){
	
	int tx =  threadIdx.x;
	device_X_Total[tx] = device_X_Not[tx] + h*((bh10*device_F_Not[tx])+ (bh11 * device_f[tx]) + (bh12 * device_f[tx+2])+ (bh13 * device_f[tx + 4]) + (bh14 * device_f[tx+ 6])+ (bh15 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+2] = device_X_Not[tx] + h*((bh20*device_F_Not[tx])+ (bh21 * device_f[tx]) + (bh22 * device_f[tx+2])+ (bh23 * device_f[tx + 4]) + (bh24 * device_f[tx+ 6])+ (bh25 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+4] = device_X_Not[tx] + h*((bh30*device_F_Not[tx])+ (bh31 * device_f[tx]) + (bh32 * device_f[tx+2])+ (bh33 * device_f[tx + 4]) + (bh34 * device_f[tx+ 6])+ (bh35 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+6] = device_X_Not[tx] + h*((bh40*device_F_Not[tx])+ (bh41 * device_f[tx]) + (bh42 * device_f[tx+2])+ (bh43 * device_f[tx + 4]) + (bh44 * device_f[tx+ 6])+ (bh45 *device_f[tx+8]));
	__syncthreads();
	device_X_Total[tx+8] = device_X_Not[tx] + h*((bh50*device_F_Not[tx])+ (bh51 * device_f[tx]) + (bh52 * device_f[tx+2])+ (bh53 * device_f[tx + 4]) + (bh54 * device_f[tx+ 6])+ (bh55 *device_f[tx+8]));
	__syncthreads();
}
//****************************************************************************
// the following function describes the ordinary differential equations
//** The function is still live for the non parallel function calls to der
//** still active in the program. 
void der(double t, double x[], double f[]) {
       if (sho) {
              f[0] = x[1];
              f[1] = -x[0];
       }
       else {
              f[0] = x[0] * (2.0 - x[1]);
              f[1] = x[1] * (x[0] - 1.0);
       }
}
 
void rk1210() {
       // Implicit Runge-Kutta of orders 12 and 10
       double  x0[MAXEQNS], x1[MAXEQNS], x2[MAXEQNS], x3[MAXEQNS], x4[MAXEQNS];
       double  x5[MAXEQNS], x6[MAXEQNS], xn10[MAXEQNS], xn12[MAXEQNS];
       double  t0, tf, h, hnew, est, esti, f0[MAXEQNS], f1[MAXEQNS], f2[MAXEQNS];
       double  f3[MAXEQNS], f4[MAXEQNS], f5[MAXEQNS], f6[MAXEQNS];
       int     iter;
       bool    finished = false;  // becomes true when we have reached tf
 
       if (sho) {
              h = PI / 4.0;       // initial guess for stepsize to use
              x0[0] = 0.0;      // initial value of first  component
              x0[1] = 1.0;      // initial value of second component
              t0 = 0.0;         // initial t value, t0
              tf = 2 * PI;        // final t value, tf
       }
       else {
              h = 1.0 / 2.0;      // initial guess for stepsize to use
              x0[0] = 2.0;      // initial value of first  component
              x0[1] = 2.0;      // initial value of second component
              t0 = 0.0;         // initial t value, t0
              tf = 4.0;         // final t value, tf
       }
       printf("Initial conditions are  t0 = %8.5lf, x0[0] = %18.15lf, x0[1] = %18.15lf\n", t0, x0[0], x0[1]);
	   const int arraySize = 10;  //there will be 8 elements being written from x1-x4 (Remaining 2 for when X5 is included);
			  int numOfXArrays =4;
			  double x_total[arraySize]; 
			  double f_total[arraySize];
       while (!finished) {                  // keep going until we reach tf successfully
              der(t0, x0, f0);                    // first, we will get 10th order results
              ////////////////////   THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //for (int i = 0; i<neqns; i++) {
              //       x1[i] = x0[i] + a1*h*f0[i];  // just guess that solution is a straight line initially
              //       x2[i] = x0[i] + a2*h*f0[i];  // at the four internal points within the step
              //       x3[i] = x0[i] + a3*h*f0[i];
              //       x4[i] = x0[i] + a4*h*f0[i];
              //}
			  //*************************************************************************************
			  double* device_x_total; double* device_x_not; double* device_f_not; //creating variables for the device
			  //allocating memory for device variables
			  hipMalloc((void**) &device_x_total, arraySize * sizeof(double));
			  hipMalloc((void**) &device_x_not, arraySize * sizeof(double));
			  hipMalloc((void**) &device_f_not, arraySize * sizeof(double));
			  //copying contents of x0 and f0 to the device variables
			  hipMemcpy(device_x_not, x0, arraySize*sizeof(double), hipMemcpyHostToDevice);
			  hipMemcpy(device_f_not, f0, arraySize *sizeof(double), hipMemcpyHostToDevice);
			  guessKernel<<<1, neqns>>>(device_x_total, device_x_not, device_f_not, h);

			  hipMemcpy(x_total, device_x_total, arraySize*sizeof(double), hipMemcpyDeviceToHost);

			  //************************************************************************************
              ////////////////////   AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //der(t0 + a1*h, x1, f1);          // now, evaluate the derivatives at these four points
              //der(t0 + a2*h, x2, f2);
              //der(t0 + a3*h, x3, f3);
              //der(t0 + a4*h, x4, f4);
			  //****************************************************************************************
			  
			  double* device_f;  //creating variables for device;
			  //allocating memory for x[], and f[]
			  hipMalloc((void**) &device_x_total, arraySize* sizeof(double));
			  hipMalloc((void**) &device_f, arraySize * sizeof(double));

			  //copying over t and x[]
			  hipMemcpy(device_x_total, x_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
			  //*******Creating timers to test 4 arrays *********
			  /*cudaEvent_t start, stop;
			  cudaEventCreate(&start);
			  cudaEventCreate(&stop);
			  cudaEventRecord(start);*/
			  //kernel call
			  derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
			  
			 /* cudaEventRecord(stop);*/
			  //copying data from device to host
		      hipMemcpy(f_total, device_f, arraySize*sizeof(double), hipMemcpyDeviceToHost);
			  /*cudaEventSynchronize(stop);
			  float milliseconds =0;
			  cudaEventElapsedTime(&milliseconds, start, stop);
			  printf("Kernel took: %f milliseconds\n", milliseconds);
			  getchar();*/
			  
			  
			  //****************************************************************************************
			  hipMalloc((void**) &device_x_total, arraySize* sizeof(double));
			  hipMalloc((void**) &device_x_not, arraySize*sizeof(double));
			  hipMalloc((void**) &device_f_not, arraySize*sizeof(double));
			  hipMalloc((void**) &device_f, arraySize*sizeof(double));
              for (iter = 0; iter<itermax10; iter++) {  // now, we perform itermax10 iterations for the 10th order method
                     printf("iter = %d\n", iter);
                     //////////////////   AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
						/*for (int i = 0; i<neqns; i++) x1[i] = x0[i] + h*(b10*f0[i] + b11*f1[i] + b12*f2[i] + b13*f3[i] + b14*f4[i]);
						for (int i = 0; i<neqns; i++) x2[i] = x0[i] + h*(b20*f0[i] + b21*f1[i] + b22*f2[i] + b23*f3[i] + b24*f4[i]);
						for (int i = 0; i<neqns; i++) x3[i] = x0[i] + h*(b30*f0[i] + b31*f1[i] + b32*f2[i] + b33*f3[i] + b34*f4[i]);
						for (int i = 0; i<neqns; i++) x4[i] = x0[i] + h*(b40*f0[i] + b41*f1[i] + b42*f2[i] + b43*f3[i] + b44*f4[i]);*/
					 
						
					    //*************Copying over f_total f0 and x0*******************************
						hipMemcpy(device_f, f_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
						hipMemcpy(device_f_not, f0, arraySize*sizeof(double), hipMemcpyHostToDevice);
						hipMemcpy(device_x_not, x0, arraySize*sizeof(double), hipMemcpyHostToDevice);
						order10Kernel<<<1,neqns>>>(device_x_total,device_x_not,device_f_not, h,device_f);
					    hipMemcpy(x_total, device_x_total, arraySize*sizeof(double), hipMemcpyDeviceToHost);
						
						

					 //**********************************************************************************************************************
                     ////////////////////   AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
                     //der(t0 + a1*h, x1, f1);          // now, evaluate the derivatives at these four points
                     //der(t0 + a2*h, x2, f2);
                     //der(t0 + a3*h, x3, f3);
                     //der(t0 + a4*h, x4, f4);
					 //************************************************************************************
			  
					 
					  hipMalloc((void**) &device_x_total, arraySize* sizeof(double));
					  hipMalloc((void**) &device_f, arraySize * sizeof(double));

					  //copying over t and x[]
					  hipMemcpy(device_x_total, x_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
						
					  //kernel call
					   derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
					  //writeback
					  hipMemcpy(f_total, device_f, arraySize*sizeof(double), hipMemcpyDeviceToHost);
					 
					 //*****************************************************************************************
                     ////////////////////   END OF PARALLEL SECTION OF CODE  ///////////////////////
              }
			  hipFree(device_x_total);
			  hipFree(device_x_not);
			  hipFree(device_f_not);
			  hipFree(device_f);

			   
			   memcpy(x1,x_total, 2*sizeof(double));
			   memcpy(x2,x_total +2, 2*sizeof(double));
			   memcpy(x3,x_total +4, 2 *sizeof(double));
		       memcpy(x4, x_total +6, 2*sizeof(double));
			   memcpy(f1,f_total, 2*sizeof(double));
			   memcpy(f2,f_total +2, 2*sizeof(double));
			   memcpy(f3,f_total +4, 2 *sizeof(double));
			   memcpy(f4, f_total +6, 2*sizeof(double));
						
              for (int i = 0; i<neqns; i++) x5[i] = x0[i] + h*(b50*f0[i] + b51*f1[i] + b52*f2[i] + b53*f3[i] + b54*f4[i]);  // now get x5
              der(t0 + a5*h, x5, f5);  // and get the derivative there, f5
              for (int i = 0; i<neqns; i++) {
                     xn10[i] = x0[i] + h*(c0*f0[i] + c1*f1[i] + c2*f2[i] + c3*f3[i] + c4*f4[i] + c5*f5[i]);  // now compute final 10th order answer
              }
              if (sho) {
                     printf("10th order iterations = %d, t = %8.5lf, xn10[0] = %18.15lf, xn10[1] = %18.15lf, error[0] = %e, error[1] = %e\n",
                           itermax10, t0 + h, xn10[0], xn10[1], xn10[0] - sin(t0 + h), xn10[1] - cos(t0 + h));
              }
              else {
                     printf("10th order iterations = %d, t = %8.5lf, xn10[0] = %18.15lf, xn10[1] = %18.15lf\n",
                           itermax10, t0 + h, xn10[0], xn10[1]);
              }
              ////////////////////   THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //for (int i = 0; i<neqns; i++) {
              //       x1[i] = x0[i] + h*(g10*f0[i] + g11*f1[i] + g12*f2[i] + g13*f3[i] + g14*f4[i] + g15*f5[i]); // these fk's are from 10th order method,
              //       x2[i] = x0[i] + h*(g20*f0[i] + g21*f1[i] + g22*f2[i] + g23*f3[i] + g24*f4[i] + g25*f5[i]); // and note that they are being
              //       x3[i] = x0[i] + h*(g30*f0[i] + g31*f1[i] + g32*f2[i] + g33*f3[i] + g34*f4[i] + g35*f5[i]); // used to build the five internal values
              //       x4[i] = x0[i] + h*(g40*f0[i] + g41*f1[i] + g42*f2[i] + g43*f3[i] + g44*f4[i] + g45*f5[i]); // used to construct the 12th order xk's,
              //       x5[i] = x0[i] + h*(g50*f0[i] + g51*f1[i] + g52*f2[i] + g53*f3[i] + g54*f4[i] + g55*f5[i]); // so these xk's are for the 12th order method
              //}
			  //***************************************************************************************************************************************************
			  
			  //copying f arrays to a single array f_total
			   memcpy(f_total,f1, 2*sizeof(double));
			   memcpy(f_total+2,f2, 2*sizeof(double));
			   memcpy(f_total+4,f3, 2 *sizeof(double));
			   memcpy(f_total+6, f4, 2*sizeof(double));
			   memcpy(f_total+8, f5, 2*sizeof(double));
			   //allocating memory
			   hipMalloc((void**) &device_x_total, arraySize*sizeof(double));
			   hipMalloc((void**) &device_f, arraySize*sizeof(double));
			   hipMalloc((void**) &device_x_not, arraySize*sizeof(double));
			   hipMalloc((void**) &device_f_not, arraySize*sizeof(double));

			   //copying over f0, x0, and f_total
			   hipMemcpy(device_f,f_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
			   hipMemcpy(device_x_not, x0, arraySize*sizeof(double), hipMemcpyHostToDevice);
			   hipMemcpy(device_f_not, f0, arraySize*sizeof(double), hipMemcpyHostToDevice);

			   //calling order10 kernel
			   Order10FkKernel<<<1, neqns>>>(device_x_total, device_x_not, device_f_not, h, device_f);

			   //WriteBack of x_total 
			   hipMemcpy(x_total, device_x_total, arraySize*sizeof(double), hipMemcpyDeviceToHost);
			   
			  //***************************************************************************************************************************************************
              ////////////////////    AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
              //der(t0 + a1*h, x1, f1);
              //der(t0 + a2*h, x2, f2);    //  now we get the fk's to be used in the 12th order method
              //der(t0 + a3*h, x3, f3);
              //der(t0 + a4*h, x4, f4);    // i.e., obtain derivatives at the five internal points needed for 12th order method
              //der(t0 + a5*h, x5, f5);
			  //********************************************************************************************************************
			  numOfXArrays=5;  //because we are passing in X1-X5
			  
			  hipMemcpy(device_x_total, x_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
			  //kernel call
			  derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
			  //copying data from device to host
			  hipMemcpy(f_total, device_f, arraySize*sizeof(double), hipMemcpyDeviceToHost);
			  
			  //****************************************************************************************************************************

              ////////////////////   END OF PARALLEL SECTION OF CODE  ///////////////////////
              for (iter = 0; iter<itermax12; iter++) {  // now we can iterate to improve the values at the five internal points
                     ////////////////////   THIS CAN BE DONE IN PARALLEL   ///////////////////////
                     //for (int i = 0; i<neqns; i++) {  // each time, we recompute the internal xk values used in the 12th order method
                     //      x1[i] = x0[i] + h*(bh10*f0[i] + bh11*f1[i] + bh12*f2[i] + bh13*f3[i] + bh14*f4[i] + bh15*f5[i]);
                     //      x2[i] = x0[i] + h*(bh20*f0[i] + bh21*f1[i] + bh22*f2[i] + bh23*f3[i] + bh24*f4[i] + bh25*f5[i]);
                     //      x3[i] = x0[i] + h*(bh30*f0[i] + bh31*f1[i] + bh32*f2[i] + bh33*f3[i] + bh34*f4[i] + bh35*f5[i]);
                     //      x4[i] = x0[i] + h*(bh40*f0[i] + bh41*f1[i] + bh42*f2[i] + bh43*f3[i] + bh44*f4[i] + bh45*f5[i]);
                     //      x5[i] = x0[i] + h*(bh50*f0[i] + bh51*f1[i] + bh52*f2[i] + bh53*f3[i] + bh54*f4[i] + bh55*f5[i]);
                     //}
				  hipMemcpy(device_f, f_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
				  hipMemcpy(device_x_not, x0, arraySize*sizeof(double), hipMemcpyHostToDevice);
				  hipMemcpy(device_f_not, f0, arraySize*sizeof(double), hipMemcpyHostToDevice);
				  Order12Kernel<<<1,neqns>>>(device_x_total, device_x_not, device_f_not, h, device_f);
			      hipMemcpy(x_total, device_x_total, arraySize*sizeof(double), hipMemcpyDeviceToHost);

                     ////////////////////  AND THIS CAN BE DONE IN PARALLEL   ///////////////////////
                     //der(t0 + a1*h, x1, f1);  // once again, obtain derivatives at the five internal points of the 12th order method
                     //der(t0 + a2*h, x2, f2);
                     //der(t0 + a3*h, x3, f3);
                     //der(t0 + a4*h, x4, f4);
                     //der(t0 + a5*h, x5, f5);
                     ////////////////////   END OF PARALLEL SECTION OF CODE  ///////////////////////
					 //*******************************************************************************************************************
						
						hipMemcpy(device_x_total, x_total, arraySize*sizeof(double), hipMemcpyHostToDevice);
						//kernel call
						derKernel<<<1,numOfXArrays>>>(device_x_total, device_f);
						//copying data from device to host
						hipMemcpy(f_total, device_f, arraySize*sizeof(double), hipMemcpyDeviceToHost);
						
			  }

			   hipFree(device_x_total);
			  hipFree(device_f);
			  hipFree(device_x_not);
			  hipFree(device_f_not);
			  memcpy(f1,f_total, 2*sizeof(double));
			  memcpy(f2,f_total +2, 2*sizeof(double));
			  memcpy(f3,f_total +4, 2 *sizeof(double));
			  memcpy(f4, f_total +6, 2*sizeof(double));
			  memcpy(f5, f_total +8, 2*sizeof(double));
			  memcpy(x1,x_total, 2*sizeof(double));
			  memcpy(x2,x_total +2, 2*sizeof(double));
			  memcpy(x3,x_total +4, 2 *sizeof(double));
			  memcpy(x4, x_total +6, 2*sizeof(double));
			  memcpy(x5, x_total +8, 2*sizeof(double));
              for (int i = 0; i<neqns; i++) {  // iteration complete, so now compute final base value for 12th order method
                     x6[i] = x0[i] + h*(bh60*f0[i] + bh61*f1[i] + bh62*f2[i] + bh63*f3[i] + bh64*f4[i] + bh65*f5[i]);
              }
              der(t0 + ah6*h, x6, f6);  // and get the derivative there
              for (int i = 0; i<neqns; i++) {  // now, compute the final 12th order approximation to the solution at the end of the step
                     xn12[i] = x0[i] + h*(ch0*f0[i] + ch1*f1[i] + ch2*f2[i] + ch3*f3[i] + ch4*f4[i] + ch5*f5[i] + ch6*f6[i]);  // now compute final 12th order answer
              }
              printf("      The estimates of the errors in the 10-th order method by differencing with 12-th order method results are %e      and    %e\n", xn10[0] - xn12[0], xn10[1] - xn12[1]);
              if (sho) {
                     printf("12th order iterations = %d, t = %8.5lf, xn12[0] = %18.15lf, xn12[1] = %18.15lf, error[0] = %e, error[1] = %e\n",
                           iter, t0 + h, xn12[0], xn12[1], xn12[0] - sin(t0 + h), xn12[1] - cos(t0 + h));
              }
              else {
                     printf("12th order iterations = %d, t = %8.5lf, xn12[0] = %18.15lf, xn12[1] = %18.15lf\n",
                           iter, t0 + h, xn12[0], xn12[1]);
              }
              est = 1.0e-30;
              for (int i = 0; i<neqns; i++) {  // now, just update the solution to prepare for the next step
                     esti = xn10[i] - xn12[i];
                     est = est + esti*esti;
              }
              est = sqrt(est);  // sqrt of the sum of the squares of the errors in each component of the solution at t0 + h
              hnew = h * pow(tol10 / est, 0.1);
              if (est < tol) {  // if error estimate is less than the error tolerance, then the step succeeded
                     printf("The step succeeded since est = %e was less than tol = %e\n\n", est, tol);
                     for (int i = 0; i<neqns; i++) {  // now, just update the solution to prepare for the next step
                           x0[i] = xn12[i];
                     }
                     t0 = t0 + h;  // and update the independent variable
                     if (t0 / tf >= 0.99999999999999) finished = true;  // and if we have reached the final value, tf, set finished to true
              }
              else {
                     printf("The step failed since est = %e was not less than tol = %e\n\n", est, tol);
              }
              h = hnew;  // in any event, if not finished, we set the stepsize, h, to the new value, hnew
              if ((t0 + h) > tf) h = tf - t0;  // if new step takes us past final value, tf, reduce it to tf-t0
       }
}
 
int main(int argc, char* argv[])
{
	  hipEvent_t start, stop;
	  hipEventCreate(&start);
	  hipEventCreate(&stop);
	  hipEventRecord(start);
       printf("Testing Implicit RK1210 ");
       if (sho) {
              printf(" for simple harmonic oscillator example problem \n\n");
       }
       else {
              printf(" for predator - prey example problem \n\n");
       }
       rk1210();
	   hipEventRecord(stop);
	   hipEventSynchronize(stop);
	   float milliseconds =0;
	   hipEventElapsedTime(&milliseconds, start, stop);
	   printf("Code took: %f milliseconds\n", milliseconds);
			  
	   getchar();
       return 0;
}

	.text
	.file	"kernel.hip"
	.globl	_Z10cudaAssert10hipError_tPKci  # -- Begin function _Z10cudaAssert10hipError_tPKci
	.type	_Z10cudaAssert10hipError_tPKci,@function
_Z10cudaAssert10hipError_tPKci:         # @_Z10cudaAssert10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB0_2
# %bb.1:
	retq
.LBB0_2:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	movq	stderr(%rip), %r15
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	callq	getchar
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z10cudaAssert10hipError_tPKci, .Lfunc_end0-_Z10cudaAssert10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__derKernelPdS_ # -- Begin function _Z24__device_stub__derKernelPdS_
	.type	_Z24__device_stub__derKernelPdS_,@function
_Z24__device_stub__derKernelPdS_:       # @_Z24__device_stub__derKernelPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9derKernelPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__derKernelPdS_, .Lfunc_end1-_Z24__device_stub__derKernelPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__guessKernelPdS_S_d # -- Begin function _Z26__device_stub__guessKernelPdS_S_d
	.type	_Z26__device_stub__guessKernelPdS_S_d,@function
_Z26__device_stub__guessKernelPdS_S_d:  # @_Z26__device_stub__guessKernelPdS_S_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11guessKernelPdS_S_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__guessKernelPdS_S_d, .Lfunc_end2-_Z26__device_stub__guessKernelPdS_S_d
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__order10KernelPdS_S_dS_ # -- Begin function _Z28__device_stub__order10KernelPdS_S_dS_
	.type	_Z28__device_stub__order10KernelPdS_S_dS_,@function
_Z28__device_stub__order10KernelPdS_S_dS_: # @_Z28__device_stub__order10KernelPdS_S_dS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	24(%rsp), %r8
	movq	%rcx, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13order10KernelPdS_S_dS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__order10KernelPdS_S_dS_, .Lfunc_end3-_Z28__device_stub__order10KernelPdS_S_dS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__Order10FkKernelPdS_S_dS_ # -- Begin function _Z30__device_stub__Order10FkKernelPdS_S_dS_
	.type	_Z30__device_stub__Order10FkKernelPdS_S_dS_,@function
_Z30__device_stub__Order10FkKernelPdS_S_dS_: # @_Z30__device_stub__Order10FkKernelPdS_S_dS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	24(%rsp), %r8
	movq	%rcx, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15Order10FkKernelPdS_S_dS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z30__device_stub__Order10FkKernelPdS_S_dS_, .Lfunc_end4-_Z30__device_stub__Order10FkKernelPdS_S_dS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__Order12KernelPdS_S_dS_ # -- Begin function _Z28__device_stub__Order12KernelPdS_S_dS_
	.type	_Z28__device_stub__Order12KernelPdS_S_dS_,@function
_Z28__device_stub__Order12KernelPdS_S_dS_: # @_Z28__device_stub__Order12KernelPdS_S_dS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	24(%rsp), %r8
	movq	%rcx, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13Order12KernelPdS_S_dS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z28__device_stub__Order12KernelPdS_S_dS_, .Lfunc_end5-_Z28__device_stub__Order12KernelPdS_S_dS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z3derdPdS_
.LCPI6_0:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.text
	.globl	_Z3derdPdS_
	.type	_Z3derdPdS_,@function
_Z3derdPdS_:                            # @_Z3derdPdS_
	.cfi_startproc
# %bb.0:
	movsd	8(%rdi), %xmm0                  # xmm0 = mem[0],zero
	movsd	%xmm0, (%rsi)
	movsd	(%rdi), %xmm0                   # xmm0 = mem[0],zero
	xorps	.LCPI6_0(%rip), %xmm0
	movlps	%xmm0, 8(%rsi)
	retq
.Lfunc_end6:
	.size	_Z3derdPdS_, .Lfunc_end6-_Z3derdPdS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z6rk1210v
.LCPI7_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI7_1:
	.quad	0x3fe921fb54442d18              # double 0.78539816339744828
.LCPI7_3:
	.quad	0x3fb1111111111111              # double 0.066666666666666666
.LCPI7_4:
	.quad	0x3fbc1cd776c6ac0c              # double 0.10981508874708384
.LCPI7_5:
	.quad	0x3fd7e8f61ff9155d              # double 0.37359383699761911
.LCPI7_6:
	.quad	0x3fc733ad2bb18d3a              # double 0.18126454003786724
.LCPI7_7:
	.quad	0x3fd131b9283834bf              # double 0.26865986755076315
.LCPI7_8:
	.quad	0x3fa1111111111111              # double 0.033333333333333333
.LCPI7_9:
	.quad	0x3fc838ef05e9dfc2              # double 0.1892374781489235
.LCPI7_10:
	.quad	0x3fd1c1665ae8edfd              # double 0.27742918851774317
.LCPI7_11:
	.quad	0x3fc910a04986c0bb              # double 0.19581988897471611
.LCPI7_12:
	.quad	0x3fc2747e6ecb2aca              # double 0.14418011102528389
.LCPI7_13:
	.quad	0x3fd47ae147ae147b              # double 0.32000000000000001
.LCPI7_14:
	.quad	0x3f98618618618619              # double 0.023809523809523812
.LCPI7_15:
	.quad	0x3fc1b784990653ef              # double 0.13841302368078298
.LCPI7_16:
	.quad	0x3fcba1b7611fb4d8              # double 0.21587269060493131
.LCPI7_17:
	.quad	0x3fcf3526859b8cec              # double 0.24380952380952381
.LCPI7_18:
	.quad	0x39b4484bfeebc2a0              # double 1.0000000000000001E-30
.LCPI7_19:
	.quad	0x3da5fd7fe1796496              # double 1.0000000000000001E-11
.LCPI7_20:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
.LCPI7_21:
	.quad	0x3ddb7cdfd9d7bdbb              # double 1.0E-10
.LCPI7_22:
	.quad	0x401921fb54442d18              # double 6.2831853071795862
.LCPI7_23:
	.quad	0x3fefffffffffffa6              # double 0.99999999999999001
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI7_2:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.text
	.globl	_Z6rk1210v
	.type	_Z6rk1210v,@function
_Z6rk1210v:                             # @_Z6rk1210v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1240, %rsp                     # imm = 0x4D8
	.cfi_def_cfa_offset 1296
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	leaq	112(%rsp), %rcx
	movq	$0, (%rcx)
	movabsq	$4607182418800017408, %rax      # imm = 0x3FF0000000000000
	movq	%rax, 8(%rcx)
	movsd	.LCPI7_0(%rip), %xmm2           # xmm2 = mem[0],zero
	movl	$.L.str.1, %edi
	xorps	%xmm0, %xmm0
	xorpd	%xmm1, %xmm1
	movb	$3, %al
	callq	printf
	leaq	3(%rbx), %r14
	movsd	.LCPI7_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movapd	%xmm0, 80(%rsp)                 # 16-byte Spill
	leaq	16(%rsp), %r15
	leaq	1(%rbx), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	leaq	8(%rsp), %rbp
	leaq	672(%rsp), %r13
	xorpd	%xmm0, %xmm0
	movsd	%xmm0, 96(%rsp)                 # 8-byte Spill
.LBB7_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_6 Depth 2
                                        #     Child Loop BB7_12 Depth 2
                                        #     Child Loop BB7_14 Depth 2
                                        #     Child Loop BB7_24 Depth 2
                                        #     Child Loop BB7_26 Depth 2
                                        #     Child Loop BB7_28 Depth 2
	movsd	120(%rsp), %xmm0                # xmm0 = mem[0],zero
	movsd	%xmm0, 192(%rsp)
	movsd	112(%rsp), %xmm0                # xmm0 = mem[0],zero
	xorpd	.LCPI7_2(%rip), %xmm0
	movlpd	%xmm0, 200(%rsp)
	movl	$80, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movq	32(%rsp), %rdi
	movl	$80, %edx
	leaq	112(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$80, %edx
	leaq	192(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_3
# %bb.2:                                #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movapd	80(%rsp), %xmm0                 # 16-byte Reload
	callq	_Z26__device_stub__guessKernelPdS_S_d
.LBB7_3:                                #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rsi
	movl	$80, %edx
	leaq	752(%rsp), %r12
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$80, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$80, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	16(%rsp), %rdi
	movl	$80, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_5
# %bb.4:                                #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z24__device_stub__derKernelPdS_
.LBB7_5:                                #   in Loop: Header=BB7_1 Depth=1
	movq	8(%rsp), %rsi
	movl	$80, %edx
	movq	%r13, %r12
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$80, %esi
	movq	%r15, %rbx
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movl	$80, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	xorl	%esi, %esi
	movb	$1, %r15b
.LBB7_6:                                #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movq	8(%rsp), %rdi
	movl	$80, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$80, %edx
	leaq	192(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$80, %edx
	leaq	112(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rbp               # imm = 0x100000001
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_8
# %bb.7:                                #   in Loop: Header=BB7_6 Depth=2
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rcx
	movapd	80(%rsp), %xmm0                 # 16-byte Reload
	callq	_Z28__device_stub__order10KernelPdS_S_dS_
.LBB7_8:                                #   in Loop: Header=BB7_6 Depth=2
	movq	16(%rsp), %rsi
	movl	$80, %edx
	leaq	752(%rsp), %r12
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$80, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movq	16(%rsp), %rdi
	movl	$80, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_10
# %bb.9:                                #   in Loop: Header=BB7_6 Depth=2
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z24__device_stub__derKernelPdS_
.LBB7_10:                               #   in Loop: Header=BB7_6 Depth=2
	movq	8(%rsp), %rsi
	movl	$80, %edx
	movq	%r13, %r12
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$1, %esi
	testb	$1, %r15b
	movl	$0, %r15d
	jne	.LBB7_6
# %bb.11:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movaps	672(%rsp), %xmm0
	movaps	%xmm0, 592(%rsp)
	leaq	688(%rsp), %rbp
	movaps	(%rbp), %xmm0
	movaps	%xmm0, 512(%rsp)
	movaps	16(%rbp), %xmm0
	movaps	%xmm0, 432(%rsp)
	movaps	32(%rbp), %xmm0
	movaps	%xmm0, 352(%rsp)
	movb	$1, %al
	xorl	%ecx, %ecx
	movapd	80(%rsp), %xmm2                 # 16-byte Reload
	movsd	.LCPI7_3(%rip), %xmm3           # xmm3 = mem[0],zero
	movsd	.LCPI7_4(%rip), %xmm4           # xmm4 = mem[0],zero
	movsd	.LCPI7_5(%rip), %xmm5           # xmm5 = mem[0],zero
	movsd	.LCPI7_6(%rip), %xmm6           # xmm6 = mem[0],zero
	movsd	.LCPI7_7(%rip), %xmm7           # xmm7 = mem[0],zero
.LBB7_12:                               #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	192(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm3, %xmm0
	movsd	592(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm1
	addsd	%xmm0, %xmm1
	movsd	512(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm5, %xmm0
	addsd	%xmm1, %xmm0
	movsd	432(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm6, %xmm1
	addsd	%xmm0, %xmm1
	movsd	352(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm7, %xmm0
	addsd	%xmm1, %xmm0
	mulsd	%xmm2, %xmm0
	addsd	112(%rsp,%rcx,8), %xmm0
	movsd	%xmm0, 992(%rsp,%rcx,8)
	movl	$1, %ecx
	testb	$1, %al
	movl	$0, %eax
	jne	.LBB7_12
# %bb.13:                               #   in Loop: Header=BB7_1 Depth=1
	movsd	1000(%rsp), %xmm0               # xmm0 = mem[0],zero
	movsd	%xmm0, 272(%rsp)
	movsd	992(%rsp), %xmm0                # xmm0 = mem[0],zero
	xorps	.LCPI7_2(%rip), %xmm0
	movlps	%xmm0, 280(%rsp)
	movb	$1, %al
	xorl	%ecx, %ecx
	movsd	.LCPI7_8(%rip), %xmm3           # xmm3 = mem[0],zero
	movsd	.LCPI7_9(%rip), %xmm4           # xmm4 = mem[0],zero
	movsd	.LCPI7_10(%rip), %xmm5          # xmm5 = mem[0],zero
.LBB7_14:                               #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	192(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm3, %xmm0
	movsd	592(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm1
	addsd	%xmm0, %xmm1
	movsd	512(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm5, %xmm0
	addsd	%xmm1, %xmm0
	movsd	432(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm5, %xmm1
	addsd	%xmm0, %xmm1
	movsd	352(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm4, %xmm0
	addsd	%xmm1, %xmm0
	movsd	272(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm3, %xmm1
	addsd	%xmm0, %xmm1
	mulsd	%xmm2, %xmm1
	addsd	112(%rsp,%rcx,8), %xmm1
	movsd	%xmm1, 912(%rsp,%rcx,8)
	movl	$1, %ecx
	testb	$1, %al
	movl	$0, %eax
	jne	.LBB7_14
# %bb.15:                               #   in Loop: Header=BB7_1 Depth=1
	movapd	%xmm2, %xmm0
	addsd	96(%rsp), %xmm0                 # 8-byte Folded Reload
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	movsd	912(%rsp), %xmm1                # xmm1 = mem[0],zero
	movsd	%xmm1, 40(%rsp)                 # 8-byte Spill
	movsd	920(%rsp), %xmm1                # xmm1 = mem[0],zero
	movsd	%xmm1, 64(%rsp)                 # 8-byte Spill
	callq	sin
	movsd	40(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	movsd	%xmm1, 56(%rsp)                 # 8-byte Spill
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	cos
	movsd	64(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movapd	%xmm2, %xmm4
	subsd	%xmm0, %xmm4
	movl	$.L.str.3, %edi
	movl	$2, %esi
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	40(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	56(%rsp), %xmm3                 # 8-byte Reload
                                        # xmm3 = mem[0],zero
	movb	$5, %al
	callq	printf
	movaps	592(%rsp), %xmm0
	movaps	%xmm0, 672(%rsp)
	movaps	512(%rsp), %xmm0
	movaps	%xmm0, (%rbp)
	movaps	432(%rsp), %xmm0
	movaps	%xmm0, 16(%rbp)
	movaps	352(%rsp), %xmm0
	movaps	%xmm0, 32(%rbp)
	movaps	272(%rsp), %xmm0
	movaps	%xmm0, 48(%rbp)
	movl	$80, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movl	$80, %esi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movq	8(%rsp), %rdi
	movl	$80, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$80, %edx
	leaq	112(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$80, %edx
	leaq	192(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %r15               # imm = 0x100000001
	movq	%r15, %rdi
	movl	$1, %esi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_17
# %bb.16:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rcx
	movaps	80(%rsp), %xmm0                 # 16-byte Reload
	callq	_Z30__device_stub__Order10FkKernelPdS_S_dS_
.LBB7_17:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rsi
	movl	$80, %edx
	leaq	752(%rsp), %r14
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$80, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	4(%r15), %r14
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_19
# %bb.18:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z24__device_stub__derKernelPdS_
.LBB7_19:                               # %.critedge
                                        #   in Loop: Header=BB7_1 Depth=1
	movq	8(%rsp), %rsi
	movl	$80, %edx
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$80, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$80, %edx
	leaq	112(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$80, %edx
	leaq	192(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	movl	$1, %esi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_21
# %bb.20:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rcx
	movaps	80(%rsp), %xmm0                 # 16-byte Reload
	callq	_Z28__device_stub__Order12KernelPdS_S_dS_
.LBB7_21:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rsi
	movl	$80, %edx
	leaq	752(%rsp), %r12
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$80, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_23
# %bb.22:                               #   in Loop: Header=BB7_1 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z24__device_stub__derKernelPdS_
.LBB7_23:                               #   in Loop: Header=BB7_1 Depth=1
	movq	8(%rsp), %rsi
	movl	$80, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movaps	672(%rsp), %xmm0
	movaps	%xmm0, 592(%rsp)
	movaps	(%rbp), %xmm0
	movaps	%xmm0, 512(%rsp)
	movaps	16(%rbp), %xmm0
	movaps	%xmm0, 432(%rsp)
	movaps	32(%rbp), %xmm0
	movaps	%xmm0, 352(%rsp)
	movaps	48(%rbp), %xmm0
	movaps	%xmm0, 272(%rsp)
	leaq	816(%rsp), %rax
	movaps	(%rax), %xmm0
	movaps	%xmm0, 992(%rsp)
	movb	$1, %al
	xorl	%ecx, %ecx
	xorpd	%xmm2, %xmm2
	movapd	80(%rsp), %xmm3                 # 16-byte Reload
	movsd	.LCPI7_11(%rip), %xmm4          # xmm4 = mem[0],zero
	movsd	.LCPI7_12(%rip), %xmm5          # xmm5 = mem[0],zero
	movsd	.LCPI7_13(%rip), %xmm6          # xmm6 = mem[0],zero
.LBB7_24:                               #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	192(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm2, %xmm0
	movsd	592(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm1
	addsd	%xmm0, %xmm1
	movsd	512(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm5, %xmm0
	addsd	%xmm1, %xmm0
	movsd	432(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm6, %xmm1
	addsd	%xmm0, %xmm1
	movsd	352(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm5, %xmm0
	addsd	%xmm1, %xmm0
	movsd	272(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm1
	addsd	%xmm0, %xmm1
	mulsd	%xmm3, %xmm1
	addsd	112(%rsp,%rcx,8), %xmm1
	movsd	%xmm1, 1152(%rsp,%rcx,8)
	movl	$1, %ecx
	testb	$1, %al
	movl	$0, %eax
	jne	.LBB7_24
# %bb.25:                               #   in Loop: Header=BB7_1 Depth=1
	movsd	1160(%rsp), %xmm0               # xmm0 = mem[0],zero
	movsd	%xmm0, 1072(%rsp)
	movsd	1152(%rsp), %xmm0               # xmm0 = mem[0],zero
	xorps	.LCPI7_2(%rip), %xmm0
	movlps	%xmm0, 1080(%rsp)
	movb	$1, %al
	xorl	%ecx, %ecx
	movq	%rbx, %r15
	movsd	.LCPI7_14(%rip), %xmm2          # xmm2 = mem[0],zero
	movsd	.LCPI7_15(%rip), %xmm4          # xmm4 = mem[0],zero
	movsd	.LCPI7_16(%rip), %xmm5          # xmm5 = mem[0],zero
	movsd	.LCPI7_17(%rip), %xmm6          # xmm6 = mem[0],zero
.LBB7_26:                               #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	192(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm2, %xmm0
	movsd	592(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm1
	addsd	%xmm0, %xmm1
	movsd	512(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm5, %xmm0
	addsd	%xmm1, %xmm0
	movsd	432(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm6, %xmm1
	addsd	%xmm0, %xmm1
	movsd	352(%rsp,%rcx,8), %xmm0         # xmm0 = mem[0],zero
	mulsd	%xmm5, %xmm0
	addsd	%xmm1, %xmm0
	movsd	272(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm1
	addsd	%xmm0, %xmm1
	movsd	1072(%rsp,%rcx,8), %xmm0        # xmm0 = mem[0],zero
	mulsd	%xmm2, %xmm0
	addsd	%xmm1, %xmm0
	mulsd	%xmm3, %xmm0
	addsd	112(%rsp,%rcx,8), %xmm0
	movsd	%xmm0, 832(%rsp,%rcx,8)
	movl	$1, %ecx
	testb	$1, %al
	movl	$0, %eax
	jne	.LBB7_26
# %bb.27:                               #   in Loop: Header=BB7_1 Depth=1
	movsd	832(%rsp), %xmm1                # xmm1 = mem[0],zero
	movsd	%xmm1, 56(%rsp)                 # 8-byte Spill
	movsd	840(%rsp), %xmm2                # xmm2 = mem[0],zero
	movsd	%xmm2, 104(%rsp)                # 8-byte Spill
	movsd	40(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	subsd	%xmm1, %xmm0
	movsd	64(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	subsd	%xmm2, %xmm1
	movl	$.L.str.4, %edi
	movb	$2, %al
	callq	printf
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	sin
	movsd	56(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	movsd	%xmm1, 40(%rsp)                 # 8-byte Spill
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	cos
	movsd	104(%rsp), %xmm2                # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movapd	%xmm2, %xmm4
	subsd	%xmm0, %xmm4
	movl	$.L.str.5, %edi
	movl	$1, %esi
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	56(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm3                 # 8-byte Reload
                                        # xmm3 = mem[0],zero
	movb	$5, %al
	callq	printf
	movb	$1, %al
	xorl	%ecx, %ecx
	movsd	.LCPI7_18(%rip), %xmm0          # xmm0 = mem[0],zero
	movabsq	$4294967297, %rbx               # imm = 0x100000001
.LBB7_28:                               #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	912(%rsp,%rcx,8), %xmm1         # xmm1 = mem[0],zero
	subsd	832(%rsp,%rcx,8), %xmm1
	mulsd	%xmm1, %xmm1
	addsd	%xmm1, %xmm0
	movl	$1, %ecx
	testb	$1, %al
	movl	$0, %eax
	jne	.LBB7_28
# %bb.29:                               #   in Loop: Header=BB7_1 Depth=1
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	leaq	8(%rsp), %rbp
	jb	.LBB7_31
# %bb.30:                               #   in Loop: Header=BB7_1 Depth=1
	xorps	%xmm1, %xmm1
	sqrtsd	%xmm0, %xmm1
	jmp	.LBB7_32
.LBB7_31:                               # %call.sqrt
                                        #   in Loop: Header=BB7_1 Depth=1
	callq	sqrt
	movapd	%xmm0, %xmm1
.LBB7_32:                               # %.split
                                        #   in Loop: Header=BB7_1 Depth=1
	movsd	%xmm1, 40(%rsp)                 # 8-byte Spill
	movsd	.LCPI7_19(%rip), %xmm0          # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	movsd	.LCPI7_20(%rip), %xmm1          # xmm1 = mem[0],zero
	callq	pow
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movsd	%xmm0, 64(%rsp)                 # 8-byte Spill
	movsd	.LCPI7_21(%rip), %xmm1          # xmm1 = mem[0],zero
	ucomisd	%xmm2, %xmm1
	jbe	.LBB7_35
# %bb.33:                               #   in Loop: Header=BB7_1 Depth=1
	movl	$.L.str.6, %edi
	movapd	%xmm2, %xmm0
	movb	$2, %al
	callq	printf
	movaps	832(%rsp), %xmm0
	movaps	%xmm0, 112(%rsp)
	movsd	48(%rsp), %xmm4                 # 8-byte Reload
                                        # xmm4 = mem[0],zero
	movapd	%xmm4, %xmm0
	movsd	.LCPI7_22(%rip), %xmm2          # xmm2 = mem[0],zero
	divsd	%xmm2, %xmm0
	ucomisd	.LCPI7_23(%rip), %xmm0
	jb	.LBB7_36
	jmp	.LBB7_34
.LBB7_35:                               #   in Loop: Header=BB7_1 Depth=1
	movl	$.L.str.7, %edi
	movapd	%xmm2, %xmm0
	movb	$2, %al
	callq	printf
	movsd	96(%rsp), %xmm4                 # 8-byte Reload
                                        # xmm4 = mem[0],zero
	movsd	.LCPI7_22(%rip), %xmm2          # xmm2 = mem[0],zero
.LBB7_36:                               #   in Loop: Header=BB7_1 Depth=1
	movapd	80(%rsp), %xmm3                 # 16-byte Reload
	mulsd	64(%rsp), %xmm3                 # 8-byte Folded Reload
	movapd	%xmm3, %xmm0
	addsd	%xmm4, %xmm0
	movapd	%xmm2, %xmm1
	subsd	%xmm4, %xmm1
	cmpltsd	%xmm0, %xmm2
	andpd	%xmm2, %xmm1
	andnpd	%xmm3, %xmm2
	orpd	%xmm1, %xmm2
	movsd	%xmm4, 96(%rsp)                 # 8-byte Spill
	movapd	%xmm2, 80(%rsp)                 # 16-byte Spill
	jmp	.LBB7_1
.LBB7_34:                               # %.thread
	addq	$1240, %rsp                     # imm = 0x4D8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z6rk1210v, .Lfunc_end7-_Z6rk1210v
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$.L.str.8, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr, %edi
	callq	puts@PLT
	callq	_Z6rk1210v
	movq	(%r14), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r14), %rdi
	callq	hipEventSynchronize
	leaq	12(%rsp), %r15
	movl	$0, (%r15)
	movq	(%rbx), %rsi
	movq	(%r14), %rdx
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	callq	getchar
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	main, .Lfunc_end8-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9derKernelPdS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11guessKernelPdS_S_d, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13order10KernelPdS_S_dS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15Order10FkKernelPdS_S_dS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13Order12KernelPdS_S_dS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$a1, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$a2, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$a3, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$a4, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b10, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b11, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b12, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b13, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b14, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b20, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b21, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b22, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b23, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b24, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b30, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b31, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b32, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b33, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b34, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b40, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b41, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b42, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b43, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$b44, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g10, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g11, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g12, %esi
	movl	$.L__unnamed_32, %edx
	movl	$.L__unnamed_32, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g13, %esi
	movl	$.L__unnamed_33, %edx
	movl	$.L__unnamed_33, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g14, %esi
	movl	$.L__unnamed_34, %edx
	movl	$.L__unnamed_34, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g15, %esi
	movl	$.L__unnamed_35, %edx
	movl	$.L__unnamed_35, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g20, %esi
	movl	$.L__unnamed_36, %edx
	movl	$.L__unnamed_36, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g21, %esi
	movl	$.L__unnamed_37, %edx
	movl	$.L__unnamed_37, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g22, %esi
	movl	$.L__unnamed_38, %edx
	movl	$.L__unnamed_38, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g23, %esi
	movl	$.L__unnamed_39, %edx
	movl	$.L__unnamed_39, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g24, %esi
	movl	$.L__unnamed_40, %edx
	movl	$.L__unnamed_40, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g25, %esi
	movl	$.L__unnamed_41, %edx
	movl	$.L__unnamed_41, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g30, %esi
	movl	$.L__unnamed_42, %edx
	movl	$.L__unnamed_42, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g31, %esi
	movl	$.L__unnamed_43, %edx
	movl	$.L__unnamed_43, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g32, %esi
	movl	$.L__unnamed_44, %edx
	movl	$.L__unnamed_44, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g33, %esi
	movl	$.L__unnamed_45, %edx
	movl	$.L__unnamed_45, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g34, %esi
	movl	$.L__unnamed_46, %edx
	movl	$.L__unnamed_46, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g35, %esi
	movl	$.L__unnamed_47, %edx
	movl	$.L__unnamed_47, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g40, %esi
	movl	$.L__unnamed_48, %edx
	movl	$.L__unnamed_48, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g41, %esi
	movl	$.L__unnamed_49, %edx
	movl	$.L__unnamed_49, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g42, %esi
	movl	$.L__unnamed_50, %edx
	movl	$.L__unnamed_50, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g43, %esi
	movl	$.L__unnamed_51, %edx
	movl	$.L__unnamed_51, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g44, %esi
	movl	$.L__unnamed_52, %edx
	movl	$.L__unnamed_52, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g45, %esi
	movl	$.L__unnamed_53, %edx
	movl	$.L__unnamed_53, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g50, %esi
	movl	$.L__unnamed_54, %edx
	movl	$.L__unnamed_54, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g51, %esi
	movl	$.L__unnamed_55, %edx
	movl	$.L__unnamed_55, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g52, %esi
	movl	$.L__unnamed_56, %edx
	movl	$.L__unnamed_56, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g53, %esi
	movl	$.L__unnamed_57, %edx
	movl	$.L__unnamed_57, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g54, %esi
	movl	$.L__unnamed_58, %edx
	movl	$.L__unnamed_58, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$g55, %esi
	movl	$.L__unnamed_59, %edx
	movl	$.L__unnamed_59, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh10, %esi
	movl	$.L__unnamed_60, %edx
	movl	$.L__unnamed_60, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh11, %esi
	movl	$.L__unnamed_61, %edx
	movl	$.L__unnamed_61, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh12, %esi
	movl	$.L__unnamed_62, %edx
	movl	$.L__unnamed_62, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh13, %esi
	movl	$.L__unnamed_63, %edx
	movl	$.L__unnamed_63, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh14, %esi
	movl	$.L__unnamed_64, %edx
	movl	$.L__unnamed_64, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh15, %esi
	movl	$.L__unnamed_65, %edx
	movl	$.L__unnamed_65, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh20, %esi
	movl	$.L__unnamed_66, %edx
	movl	$.L__unnamed_66, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh21, %esi
	movl	$.L__unnamed_67, %edx
	movl	$.L__unnamed_67, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh22, %esi
	movl	$.L__unnamed_68, %edx
	movl	$.L__unnamed_68, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh23, %esi
	movl	$.L__unnamed_69, %edx
	movl	$.L__unnamed_69, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh24, %esi
	movl	$.L__unnamed_70, %edx
	movl	$.L__unnamed_70, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh25, %esi
	movl	$.L__unnamed_71, %edx
	movl	$.L__unnamed_71, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh30, %esi
	movl	$.L__unnamed_72, %edx
	movl	$.L__unnamed_72, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh31, %esi
	movl	$.L__unnamed_73, %edx
	movl	$.L__unnamed_73, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh32, %esi
	movl	$.L__unnamed_74, %edx
	movl	$.L__unnamed_74, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh33, %esi
	movl	$.L__unnamed_75, %edx
	movl	$.L__unnamed_75, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh34, %esi
	movl	$.L__unnamed_76, %edx
	movl	$.L__unnamed_76, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh35, %esi
	movl	$.L__unnamed_77, %edx
	movl	$.L__unnamed_77, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh40, %esi
	movl	$.L__unnamed_78, %edx
	movl	$.L__unnamed_78, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh41, %esi
	movl	$.L__unnamed_79, %edx
	movl	$.L__unnamed_79, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh42, %esi
	movl	$.L__unnamed_80, %edx
	movl	$.L__unnamed_80, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh43, %esi
	movl	$.L__unnamed_81, %edx
	movl	$.L__unnamed_81, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh44, %esi
	movl	$.L__unnamed_82, %edx
	movl	$.L__unnamed_82, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh45, %esi
	movl	$.L__unnamed_83, %edx
	movl	$.L__unnamed_83, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh50, %esi
	movl	$.L__unnamed_84, %edx
	movl	$.L__unnamed_84, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh51, %esi
	movl	$.L__unnamed_85, %edx
	movl	$.L__unnamed_85, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh52, %esi
	movl	$.L__unnamed_86, %edx
	movl	$.L__unnamed_86, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh53, %esi
	movl	$.L__unnamed_87, %edx
	movl	$.L__unnamed_87, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh54, %esi
	movl	$.L__unnamed_88, %edx
	movl	$.L__unnamed_88, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bh55, %esi
	movl	$.L__unnamed_89, %edx
	movl	$.L__unnamed_89, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	a1,@object                      # @a1
	.local	a1
	.comm	a1,8,8
	.type	a2,@object                      # @a2
	.local	a2
	.comm	a2,8,8
	.type	a3,@object                      # @a3
	.local	a3
	.comm	a3,8,8
	.type	a4,@object                      # @a4
	.local	a4
	.comm	a4,8,8
	.type	b10,@object                     # @b10
	.local	b10
	.comm	b10,8,8
	.type	b11,@object                     # @b11
	.local	b11
	.comm	b11,8,8
	.type	b12,@object                     # @b12
	.local	b12
	.comm	b12,8,8
	.type	b13,@object                     # @b13
	.local	b13
	.comm	b13,8,8
	.type	b14,@object                     # @b14
	.local	b14
	.comm	b14,8,8
	.type	b20,@object                     # @b20
	.local	b20
	.comm	b20,8,8
	.type	b21,@object                     # @b21
	.local	b21
	.comm	b21,8,8
	.type	b22,@object                     # @b22
	.local	b22
	.comm	b22,8,8
	.type	b23,@object                     # @b23
	.local	b23
	.comm	b23,8,8
	.type	b24,@object                     # @b24
	.local	b24
	.comm	b24,8,8
	.type	b30,@object                     # @b30
	.local	b30
	.comm	b30,8,8
	.type	b31,@object                     # @b31
	.local	b31
	.comm	b31,8,8
	.type	b32,@object                     # @b32
	.local	b32
	.comm	b32,8,8
	.type	b33,@object                     # @b33
	.local	b33
	.comm	b33,8,8
	.type	b34,@object                     # @b34
	.local	b34
	.comm	b34,8,8
	.type	b40,@object                     # @b40
	.local	b40
	.comm	b40,8,8
	.type	b41,@object                     # @b41
	.local	b41
	.comm	b41,8,8
	.type	b42,@object                     # @b42
	.local	b42
	.comm	b42,8,8
	.type	b43,@object                     # @b43
	.local	b43
	.comm	b43,8,8
	.type	b44,@object                     # @b44
	.local	b44
	.comm	b44,8,8
	.type	g10,@object                     # @g10
	.local	g10
	.comm	g10,8,8
	.type	g11,@object                     # @g11
	.local	g11
	.comm	g11,8,8
	.type	g12,@object                     # @g12
	.local	g12
	.comm	g12,8,8
	.type	g13,@object                     # @g13
	.local	g13
	.comm	g13,8,8
	.type	g14,@object                     # @g14
	.local	g14
	.comm	g14,8,8
	.type	g15,@object                     # @g15
	.local	g15
	.comm	g15,8,8
	.type	g20,@object                     # @g20
	.local	g20
	.comm	g20,8,8
	.type	g21,@object                     # @g21
	.local	g21
	.comm	g21,8,8
	.type	g22,@object                     # @g22
	.local	g22
	.comm	g22,8,8
	.type	g23,@object                     # @g23
	.local	g23
	.comm	g23,8,8
	.type	g24,@object                     # @g24
	.local	g24
	.comm	g24,8,8
	.type	g25,@object                     # @g25
	.local	g25
	.comm	g25,8,8
	.type	g30,@object                     # @g30
	.local	g30
	.comm	g30,8,8
	.type	g31,@object                     # @g31
	.local	g31
	.comm	g31,8,8
	.type	g32,@object                     # @g32
	.local	g32
	.comm	g32,8,8
	.type	g33,@object                     # @g33
	.local	g33
	.comm	g33,8,8
	.type	g34,@object                     # @g34
	.local	g34
	.comm	g34,8,8
	.type	g35,@object                     # @g35
	.local	g35
	.comm	g35,8,8
	.type	g40,@object                     # @g40
	.local	g40
	.comm	g40,8,8
	.type	g41,@object                     # @g41
	.local	g41
	.comm	g41,8,8
	.type	g42,@object                     # @g42
	.local	g42
	.comm	g42,8,8
	.type	g43,@object                     # @g43
	.local	g43
	.comm	g43,8,8
	.type	g44,@object                     # @g44
	.local	g44
	.comm	g44,8,8
	.type	g45,@object                     # @g45
	.local	g45
	.comm	g45,8,8
	.type	g50,@object                     # @g50
	.local	g50
	.comm	g50,8,8
	.type	g51,@object                     # @g51
	.local	g51
	.comm	g51,8,8
	.type	g52,@object                     # @g52
	.local	g52
	.comm	g52,8,8
	.type	g53,@object                     # @g53
	.local	g53
	.comm	g53,8,8
	.type	g54,@object                     # @g54
	.local	g54
	.comm	g54,8,8
	.type	g55,@object                     # @g55
	.local	g55
	.comm	g55,8,8
	.type	bh10,@object                    # @bh10
	.local	bh10
	.comm	bh10,8,8
	.type	bh11,@object                    # @bh11
	.local	bh11
	.comm	bh11,8,8
	.type	bh12,@object                    # @bh12
	.local	bh12
	.comm	bh12,8,8
	.type	bh13,@object                    # @bh13
	.local	bh13
	.comm	bh13,8,8
	.type	bh14,@object                    # @bh14
	.local	bh14
	.comm	bh14,8,8
	.type	bh15,@object                    # @bh15
	.local	bh15
	.comm	bh15,8,8
	.type	bh20,@object                    # @bh20
	.local	bh20
	.comm	bh20,8,8
	.type	bh21,@object                    # @bh21
	.local	bh21
	.comm	bh21,8,8
	.type	bh22,@object                    # @bh22
	.local	bh22
	.comm	bh22,8,8
	.type	bh23,@object                    # @bh23
	.local	bh23
	.comm	bh23,8,8
	.type	bh24,@object                    # @bh24
	.local	bh24
	.comm	bh24,8,8
	.type	bh25,@object                    # @bh25
	.local	bh25
	.comm	bh25,8,8
	.type	bh30,@object                    # @bh30
	.local	bh30
	.comm	bh30,8,8
	.type	bh31,@object                    # @bh31
	.local	bh31
	.comm	bh31,8,8
	.type	bh32,@object                    # @bh32
	.local	bh32
	.comm	bh32,8,8
	.type	bh33,@object                    # @bh33
	.local	bh33
	.comm	bh33,8,8
	.type	bh34,@object                    # @bh34
	.local	bh34
	.comm	bh34,8,8
	.type	bh35,@object                    # @bh35
	.local	bh35
	.comm	bh35,8,8
	.type	bh40,@object                    # @bh40
	.local	bh40
	.comm	bh40,8,8
	.type	bh41,@object                    # @bh41
	.local	bh41
	.comm	bh41,8,8
	.type	bh42,@object                    # @bh42
	.local	bh42
	.comm	bh42,8,8
	.type	bh43,@object                    # @bh43
	.local	bh43
	.comm	bh43,8,8
	.type	bh44,@object                    # @bh44
	.local	bh44
	.comm	bh44,8,8
	.type	bh45,@object                    # @bh45
	.local	bh45
	.comm	bh45,8,8
	.type	bh50,@object                    # @bh50
	.local	bh50
	.comm	bh50,8,8
	.type	bh51,@object                    # @bh51
	.local	bh51
	.comm	bh51,8,8
	.type	bh52,@object                    # @bh52
	.local	bh52
	.comm	bh52,8,8
	.type	bh53,@object                    # @bh53
	.local	bh53
	.comm	bh53,8,8
	.type	bh54,@object                    # @bh54
	.local	bh54
	.comm	bh54,8,8
	.type	bh55,@object                    # @bh55
	.local	bh55
	.comm	bh55,8,8
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Cuda error in file '%s' in line %i : %s.\n"
	.size	.L.str, 42

	.type	_Z9derKernelPdS_,@object        # @_Z9derKernelPdS_
	.section	.rodata,"a",@progbits
	.globl	_Z9derKernelPdS_
	.p2align	3, 0x0
_Z9derKernelPdS_:
	.quad	_Z24__device_stub__derKernelPdS_
	.size	_Z9derKernelPdS_, 8

	.type	_Z11guessKernelPdS_S_d,@object  # @_Z11guessKernelPdS_S_d
	.globl	_Z11guessKernelPdS_S_d
	.p2align	3, 0x0
_Z11guessKernelPdS_S_d:
	.quad	_Z26__device_stub__guessKernelPdS_S_d
	.size	_Z11guessKernelPdS_S_d, 8

	.type	_Z13order10KernelPdS_S_dS_,@object # @_Z13order10KernelPdS_S_dS_
	.globl	_Z13order10KernelPdS_S_dS_
	.p2align	3, 0x0
_Z13order10KernelPdS_S_dS_:
	.quad	_Z28__device_stub__order10KernelPdS_S_dS_
	.size	_Z13order10KernelPdS_S_dS_, 8

	.type	_Z15Order10FkKernelPdS_S_dS_,@object # @_Z15Order10FkKernelPdS_S_dS_
	.globl	_Z15Order10FkKernelPdS_S_dS_
	.p2align	3, 0x0
_Z15Order10FkKernelPdS_S_dS_:
	.quad	_Z30__device_stub__Order10FkKernelPdS_S_dS_
	.size	_Z15Order10FkKernelPdS_S_dS_, 8

	.type	_Z13Order12KernelPdS_S_dS_,@object # @_Z13Order12KernelPdS_S_dS_
	.globl	_Z13Order12KernelPdS_S_dS_
	.p2align	3, 0x0
_Z13Order12KernelPdS_S_dS_:
	.quad	_Z28__device_stub__Order12KernelPdS_S_dS_
	.size	_Z13Order12KernelPdS_S_dS_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Initial conditions are  t0 = %8.5lf, x0[0] = %18.15lf, x0[1] = %18.15lf\n"
	.size	.L.str.1, 73

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"iter = %d\n"
	.size	.L.str.2, 11

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"10th order iterations = %d, t = %8.5lf, xn10[0] = %18.15lf, xn10[1] = %18.15lf, error[0] = %e, error[1] = %e\n"
	.size	.L.str.3, 110

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"      The estimates of the errors in the 10-th order method by differencing with 12-th order method results are %e      and    %e\n"
	.size	.L.str.4, 131

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"12th order iterations = %d, t = %8.5lf, xn12[0] = %18.15lf, xn12[1] = %18.15lf, error[0] = %e, error[1] = %e\n"
	.size	.L.str.5, 110

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"The step succeeded since est = %e was less than tol = %e\n\n"
	.size	.L.str.6, 59

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"The step failed since est = %e was not less than tol = %e\n\n"
	.size	.L.str.7, 60

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Testing Implicit RK1210 "
	.size	.L.str.8, 25

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Code took: %f milliseconds\n"
	.size	.L.str.10, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9derKernelPdS_"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11guessKernelPdS_S_d"
	.size	.L__unnamed_2, 23

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13order10KernelPdS_S_dS_"
	.size	.L__unnamed_3, 27

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15Order10FkKernelPdS_S_dS_"
	.size	.L__unnamed_4, 29

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z13Order12KernelPdS_S_dS_"
	.size	.L__unnamed_5, 27

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"a1"
	.size	.L__unnamed_6, 3

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"a2"
	.size	.L__unnamed_7, 3

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"a3"
	.size	.L__unnamed_8, 3

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"a4"
	.size	.L__unnamed_9, 3

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"b10"
	.size	.L__unnamed_10, 4

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"b11"
	.size	.L__unnamed_11, 4

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"b12"
	.size	.L__unnamed_12, 4

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"b13"
	.size	.L__unnamed_13, 4

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"b14"
	.size	.L__unnamed_14, 4

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"b20"
	.size	.L__unnamed_15, 4

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"b21"
	.size	.L__unnamed_16, 4

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"b22"
	.size	.L__unnamed_17, 4

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"b23"
	.size	.L__unnamed_18, 4

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"b24"
	.size	.L__unnamed_19, 4

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"b30"
	.size	.L__unnamed_20, 4

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"b31"
	.size	.L__unnamed_21, 4

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"b32"
	.size	.L__unnamed_22, 4

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"b33"
	.size	.L__unnamed_23, 4

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"b34"
	.size	.L__unnamed_24, 4

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"b40"
	.size	.L__unnamed_25, 4

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"b41"
	.size	.L__unnamed_26, 4

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"b42"
	.size	.L__unnamed_27, 4

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"b43"
	.size	.L__unnamed_28, 4

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"b44"
	.size	.L__unnamed_29, 4

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"g10"
	.size	.L__unnamed_30, 4

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"g11"
	.size	.L__unnamed_31, 4

	.type	.L__unnamed_32,@object          # @31
.L__unnamed_32:
	.asciz	"g12"
	.size	.L__unnamed_32, 4

	.type	.L__unnamed_33,@object          # @32
.L__unnamed_33:
	.asciz	"g13"
	.size	.L__unnamed_33, 4

	.type	.L__unnamed_34,@object          # @33
.L__unnamed_34:
	.asciz	"g14"
	.size	.L__unnamed_34, 4

	.type	.L__unnamed_35,@object          # @34
.L__unnamed_35:
	.asciz	"g15"
	.size	.L__unnamed_35, 4

	.type	.L__unnamed_36,@object          # @35
.L__unnamed_36:
	.asciz	"g20"
	.size	.L__unnamed_36, 4

	.type	.L__unnamed_37,@object          # @36
.L__unnamed_37:
	.asciz	"g21"
	.size	.L__unnamed_37, 4

	.type	.L__unnamed_38,@object          # @37
.L__unnamed_38:
	.asciz	"g22"
	.size	.L__unnamed_38, 4

	.type	.L__unnamed_39,@object          # @38
.L__unnamed_39:
	.asciz	"g23"
	.size	.L__unnamed_39, 4

	.type	.L__unnamed_40,@object          # @39
.L__unnamed_40:
	.asciz	"g24"
	.size	.L__unnamed_40, 4

	.type	.L__unnamed_41,@object          # @40
.L__unnamed_41:
	.asciz	"g25"
	.size	.L__unnamed_41, 4

	.type	.L__unnamed_42,@object          # @41
.L__unnamed_42:
	.asciz	"g30"
	.size	.L__unnamed_42, 4

	.type	.L__unnamed_43,@object          # @42
.L__unnamed_43:
	.asciz	"g31"
	.size	.L__unnamed_43, 4

	.type	.L__unnamed_44,@object          # @43
.L__unnamed_44:
	.asciz	"g32"
	.size	.L__unnamed_44, 4

	.type	.L__unnamed_45,@object          # @44
.L__unnamed_45:
	.asciz	"g33"
	.size	.L__unnamed_45, 4

	.type	.L__unnamed_46,@object          # @45
.L__unnamed_46:
	.asciz	"g34"
	.size	.L__unnamed_46, 4

	.type	.L__unnamed_47,@object          # @46
.L__unnamed_47:
	.asciz	"g35"
	.size	.L__unnamed_47, 4

	.type	.L__unnamed_48,@object          # @47
.L__unnamed_48:
	.asciz	"g40"
	.size	.L__unnamed_48, 4

	.type	.L__unnamed_49,@object          # @48
.L__unnamed_49:
	.asciz	"g41"
	.size	.L__unnamed_49, 4

	.type	.L__unnamed_50,@object          # @49
.L__unnamed_50:
	.asciz	"g42"
	.size	.L__unnamed_50, 4

	.type	.L__unnamed_51,@object          # @50
.L__unnamed_51:
	.asciz	"g43"
	.size	.L__unnamed_51, 4

	.type	.L__unnamed_52,@object          # @51
.L__unnamed_52:
	.asciz	"g44"
	.size	.L__unnamed_52, 4

	.type	.L__unnamed_53,@object          # @52
.L__unnamed_53:
	.asciz	"g45"
	.size	.L__unnamed_53, 4

	.type	.L__unnamed_54,@object          # @53
.L__unnamed_54:
	.asciz	"g50"
	.size	.L__unnamed_54, 4

	.type	.L__unnamed_55,@object          # @54
.L__unnamed_55:
	.asciz	"g51"
	.size	.L__unnamed_55, 4

	.type	.L__unnamed_56,@object          # @55
.L__unnamed_56:
	.asciz	"g52"
	.size	.L__unnamed_56, 4

	.type	.L__unnamed_57,@object          # @56
.L__unnamed_57:
	.asciz	"g53"
	.size	.L__unnamed_57, 4

	.type	.L__unnamed_58,@object          # @57
.L__unnamed_58:
	.asciz	"g54"
	.size	.L__unnamed_58, 4

	.type	.L__unnamed_59,@object          # @58
.L__unnamed_59:
	.asciz	"g55"
	.size	.L__unnamed_59, 4

	.type	.L__unnamed_60,@object          # @59
.L__unnamed_60:
	.asciz	"bh10"
	.size	.L__unnamed_60, 5

	.type	.L__unnamed_61,@object          # @60
.L__unnamed_61:
	.asciz	"bh11"
	.size	.L__unnamed_61, 5

	.type	.L__unnamed_62,@object          # @61
.L__unnamed_62:
	.asciz	"bh12"
	.size	.L__unnamed_62, 5

	.type	.L__unnamed_63,@object          # @62
.L__unnamed_63:
	.asciz	"bh13"
	.size	.L__unnamed_63, 5

	.type	.L__unnamed_64,@object          # @63
.L__unnamed_64:
	.asciz	"bh14"
	.size	.L__unnamed_64, 5

	.type	.L__unnamed_65,@object          # @64
.L__unnamed_65:
	.asciz	"bh15"
	.size	.L__unnamed_65, 5

	.type	.L__unnamed_66,@object          # @65
.L__unnamed_66:
	.asciz	"bh20"
	.size	.L__unnamed_66, 5

	.type	.L__unnamed_67,@object          # @66
.L__unnamed_67:
	.asciz	"bh21"
	.size	.L__unnamed_67, 5

	.type	.L__unnamed_68,@object          # @67
.L__unnamed_68:
	.asciz	"bh22"
	.size	.L__unnamed_68, 5

	.type	.L__unnamed_69,@object          # @68
.L__unnamed_69:
	.asciz	"bh23"
	.size	.L__unnamed_69, 5

	.type	.L__unnamed_70,@object          # @69
.L__unnamed_70:
	.asciz	"bh24"
	.size	.L__unnamed_70, 5

	.type	.L__unnamed_71,@object          # @70
.L__unnamed_71:
	.asciz	"bh25"
	.size	.L__unnamed_71, 5

	.type	.L__unnamed_72,@object          # @71
.L__unnamed_72:
	.asciz	"bh30"
	.size	.L__unnamed_72, 5

	.type	.L__unnamed_73,@object          # @72
.L__unnamed_73:
	.asciz	"bh31"
	.size	.L__unnamed_73, 5

	.type	.L__unnamed_74,@object          # @73
.L__unnamed_74:
	.asciz	"bh32"
	.size	.L__unnamed_74, 5

	.type	.L__unnamed_75,@object          # @74
.L__unnamed_75:
	.asciz	"bh33"
	.size	.L__unnamed_75, 5

	.type	.L__unnamed_76,@object          # @75
.L__unnamed_76:
	.asciz	"bh34"
	.size	.L__unnamed_76, 5

	.type	.L__unnamed_77,@object          # @76
.L__unnamed_77:
	.asciz	"bh35"
	.size	.L__unnamed_77, 5

	.type	.L__unnamed_78,@object          # @77
.L__unnamed_78:
	.asciz	"bh40"
	.size	.L__unnamed_78, 5

	.type	.L__unnamed_79,@object          # @78
.L__unnamed_79:
	.asciz	"bh41"
	.size	.L__unnamed_79, 5

	.type	.L__unnamed_80,@object          # @79
.L__unnamed_80:
	.asciz	"bh42"
	.size	.L__unnamed_80, 5

	.type	.L__unnamed_81,@object          # @80
.L__unnamed_81:
	.asciz	"bh43"
	.size	.L__unnamed_81, 5

	.type	.L__unnamed_82,@object          # @81
.L__unnamed_82:
	.asciz	"bh44"
	.size	.L__unnamed_82, 5

	.type	.L__unnamed_83,@object          # @82
.L__unnamed_83:
	.asciz	"bh45"
	.size	.L__unnamed_83, 5

	.type	.L__unnamed_84,@object          # @83
.L__unnamed_84:
	.asciz	"bh50"
	.size	.L__unnamed_84, 5

	.type	.L__unnamed_85,@object          # @84
.L__unnamed_85:
	.asciz	"bh51"
	.size	.L__unnamed_85, 5

	.type	.L__unnamed_86,@object          # @85
.L__unnamed_86:
	.asciz	"bh52"
	.size	.L__unnamed_86, 5

	.type	.L__unnamed_87,@object          # @86
.L__unnamed_87:
	.asciz	"bh53"
	.size	.L__unnamed_87, 5

	.type	.L__unnamed_88,@object          # @87
.L__unnamed_88:
	.asciz	"bh54"
	.size	.L__unnamed_88, 5

	.type	.L__unnamed_89,@object          # @88
.L__unnamed_89:
	.asciz	"bh55"
	.size	.L__unnamed_89, 5

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	" for simple harmonic oscillator example problem \n"
	.size	.Lstr, 50

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__derKernelPdS_
	.addrsig_sym _Z26__device_stub__guessKernelPdS_S_d
	.addrsig_sym _Z28__device_stub__order10KernelPdS_S_dS_
	.addrsig_sym _Z30__device_stub__Order10FkKernelPdS_S_dS_
	.addrsig_sym _Z28__device_stub__Order12KernelPdS_S_dS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym a1
	.addrsig_sym a2
	.addrsig_sym a3
	.addrsig_sym a4
	.addrsig_sym b10
	.addrsig_sym b11
	.addrsig_sym b12
	.addrsig_sym b13
	.addrsig_sym b14
	.addrsig_sym b20
	.addrsig_sym b21
	.addrsig_sym b22
	.addrsig_sym b23
	.addrsig_sym b24
	.addrsig_sym b30
	.addrsig_sym b31
	.addrsig_sym b32
	.addrsig_sym b33
	.addrsig_sym b34
	.addrsig_sym b40
	.addrsig_sym b41
	.addrsig_sym b42
	.addrsig_sym b43
	.addrsig_sym b44
	.addrsig_sym g10
	.addrsig_sym g11
	.addrsig_sym g12
	.addrsig_sym g13
	.addrsig_sym g14
	.addrsig_sym g15
	.addrsig_sym g20
	.addrsig_sym g21
	.addrsig_sym g22
	.addrsig_sym g23
	.addrsig_sym g24
	.addrsig_sym g25
	.addrsig_sym g30
	.addrsig_sym g31
	.addrsig_sym g32
	.addrsig_sym g33
	.addrsig_sym g34
	.addrsig_sym g35
	.addrsig_sym g40
	.addrsig_sym g41
	.addrsig_sym g42
	.addrsig_sym g43
	.addrsig_sym g44
	.addrsig_sym g45
	.addrsig_sym g50
	.addrsig_sym g51
	.addrsig_sym g52
	.addrsig_sym g53
	.addrsig_sym g54
	.addrsig_sym g55
	.addrsig_sym bh10
	.addrsig_sym bh11
	.addrsig_sym bh12
	.addrsig_sym bh13
	.addrsig_sym bh14
	.addrsig_sym bh15
	.addrsig_sym bh20
	.addrsig_sym bh21
	.addrsig_sym bh22
	.addrsig_sym bh23
	.addrsig_sym bh24
	.addrsig_sym bh25
	.addrsig_sym bh30
	.addrsig_sym bh31
	.addrsig_sym bh32
	.addrsig_sym bh33
	.addrsig_sym bh34
	.addrsig_sym bh35
	.addrsig_sym bh40
	.addrsig_sym bh41
	.addrsig_sym bh42
	.addrsig_sym bh43
	.addrsig_sym bh44
	.addrsig_sym bh45
	.addrsig_sym bh50
	.addrsig_sym bh51
	.addrsig_sym bh52
	.addrsig_sym bh53
	.addrsig_sym bh54
	.addrsig_sym bh55
	.addrsig_sym _Z9derKernelPdS_
	.addrsig_sym _Z11guessKernelPdS_S_d
	.addrsig_sym _Z13order10KernelPdS_S_dS_
	.addrsig_sym _Z15Order10FkKernelPdS_S_dS_
	.addrsig_sym _Z13Order12KernelPdS_S_dS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9derKernelPdS_        ; -- Begin function _Z9derKernelPdS_
	.globl	_Z9derKernelPdS_
	.p2align	8
	.type	_Z9derKernelPdS_,@function
_Z9derKernelPdS_:                       ; @_Z9derKernelPdS_
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v2, 4, v0
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[0:1], v2, s[0:1] offset:8
	s_waitcnt vmcnt(0)
	global_store_b64 v2, v[0:1], s[2:3]
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b64 v[0:1], v2, s[0:1]
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v1, 0x80000000, v1
	global_store_b64 v2, v[0:1], s[2:3] offset:8
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9derKernelPdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 4
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9derKernelPdS_, .Lfunc_end0-_Z9derKernelPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 4
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 4
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11guessKernelPdS_S_d  ; -- Begin function _Z11guessKernelPdS_S_d
	.globl	_Z11guessKernelPdS_S_d
	.p2align	8
	.type	_Z11guessKernelPdS_S_d,@function
_Z11guessKernelPdS_S_d:                 ; @_Z11guessKernelPdS_S_d
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v6, 3, v0
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, a1@rel32@lo+4
	s_addc_u32 s9, s9, a1@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3]
	global_load_b64 v[2:3], v6, s[4:5]
	s_load_b64 s[8:9], s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[4:5], s[8:9], s[6:7]
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, a2@rel32@lo+4
	s_addc_u32 s9, s9, a2@rel32@hi+12
	s_load_b64 s[8:9], s[8:9], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[4:5], s[8:9], s[6:7]
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, a3@rel32@lo+4
	s_addc_u32 s9, s9, a3@rel32@hi+12
	s_load_b64 s[8:9], s[8:9], 0x0
	global_store_b64 v6, v[0:1], s[0:1]
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3]
	global_load_b64 v[2:3], v6, s[4:5]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[4:5], s[8:9], s[6:7]
	global_store_b64 v6, v[0:1], s[0:1] offset:16
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3]
	global_load_b64 v[2:3], v6, s[4:5]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
	global_store_b64 v6, v[0:1], s[0:1] offset:32
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3]
	global_load_b64 v[2:3], v6, s[4:5]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, a4@rel32@lo+4
	s_addc_u32 s3, s3, a4@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[4:5], s[2:3], s[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
	global_store_b64 v6, v[0:1], s[0:1] offset:48
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11guessKernelPdS_S_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 10
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11guessKernelPdS_S_d, .Lfunc_end1-_Z11guessKernelPdS_S_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 10
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13order10KernelPdS_S_dS_ ; -- Begin function _Z13order10KernelPdS_S_dS_
	.globl	_Z13order10KernelPdS_S_dS_
	.p2align	8
	.type	_Z13order10KernelPdS_S_dS_,@function
_Z13order10KernelPdS_S_dS_:             ; @_Z13order10KernelPdS_S_dS_
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x20
	v_lshlrev_b32_e32 v12, 3, v0
	s_load_b256 s[0:7], s[0:1], 0x0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b11@rel32@lo+4
	s_addc_u32 s11, s11, b11@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	s_clause 0x5
	global_load_b64 v[0:1], v12, s[8:9]
	global_load_b64 v[2:3], v12, s[4:5]
	global_load_b64 v[4:5], v12, s[8:9] offset:16
	global_load_b64 v[6:7], v12, s[8:9] offset:32
	global_load_b64 v[8:9], v12, s[8:9] offset:48
	global_load_b64 v[10:11], v12, s[2:3]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b10@rel32@lo+4
	s_addc_u32 s11, s11, b10@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b12@rel32@lo+4
	s_addc_u32 s11, s11, b12@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b13@rel32@lo+4
	s_addc_u32 s11, s11, b13@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b14@rel32@lo+4
	s_addc_u32 s11, s11, b14@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b21@rel32@lo+4
	s_addc_u32 s11, s11, b21@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[10:11]
	global_store_b64 v12, v[0:1], s[0:1]
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x5
	global_load_b64 v[0:1], v12, s[8:9]
	global_load_b64 v[2:3], v12, s[4:5]
	global_load_b64 v[4:5], v12, s[8:9] offset:16
	global_load_b64 v[6:7], v12, s[8:9] offset:32
	global_load_b64 v[8:9], v12, s[8:9] offset:48
	global_load_b64 v[10:11], v12, s[2:3]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b20@rel32@lo+4
	s_addc_u32 s11, s11, b20@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b22@rel32@lo+4
	s_addc_u32 s11, s11, b22@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b23@rel32@lo+4
	s_addc_u32 s11, s11, b23@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b24@rel32@lo+4
	s_addc_u32 s11, s11, b24@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b31@rel32@lo+4
	s_addc_u32 s11, s11, b31@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[10:11]
	global_store_b64 v12, v[0:1], s[0:1] offset:16
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x5
	global_load_b64 v[0:1], v12, s[8:9]
	global_load_b64 v[2:3], v12, s[4:5]
	global_load_b64 v[4:5], v12, s[8:9] offset:16
	global_load_b64 v[6:7], v12, s[8:9] offset:32
	global_load_b64 v[8:9], v12, s[8:9] offset:48
	global_load_b64 v[10:11], v12, s[2:3]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b30@rel32@lo+4
	s_addc_u32 s11, s11, b30@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b32@rel32@lo+4
	s_addc_u32 s11, s11, b32@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b33@rel32@lo+4
	s_addc_u32 s11, s11, b33@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, b34@rel32@lo+4
	s_addc_u32 s11, s11, b34@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[10:11]
	global_store_b64 v12, v[0:1], s[0:1] offset:32
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x5
	global_load_b64 v[0:1], v12, s[8:9]
	global_load_b64 v[2:3], v12, s[4:5]
	global_load_b64 v[4:5], v12, s[8:9] offset:16
	global_load_b64 v[6:7], v12, s[8:9] offset:32
	global_load_b64 v[8:9], v12, s[8:9] offset:48
	global_load_b64 v[10:11], v12, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, b41@rel32@lo+4
	s_addc_u32 s3, s3, b41@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_mul_f64 v[0:1], s[2:3], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, b40@rel32@lo+4
	s_addc_u32 s3, s3, b40@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[2:3], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, b42@rel32@lo+4
	s_addc_u32 s3, s3, b42@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[4:5], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, b43@rel32@lo+4
	s_addc_u32 s3, s3, b43@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[6:7], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, b44@rel32@lo+4
	s_addc_u32 s3, s3, b44@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[8:9], v[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[10:11]
	global_store_b64 v12, v[0:1], s[0:1] offset:48
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13order10KernelPdS_S_dS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 12
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13order10KernelPdS_S_dS_, .Lfunc_end2-_Z13order10KernelPdS_S_dS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1260
; NumSgprs: 12
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15Order10FkKernelPdS_S_dS_ ; -- Begin function _Z15Order10FkKernelPdS_S_dS_
	.globl	_Z15Order10FkKernelPdS_S_dS_
	.p2align	8
	.type	_Z15Order10FkKernelPdS_S_dS_,@function
_Z15Order10FkKernelPdS_S_dS_:           ; @_Z15Order10FkKernelPdS_S_dS_
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x20
	v_lshlrev_b32_e32 v14, 3, v0
	s_load_b256 s[0:7], s[0:1], 0x0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g11@rel32@lo+4
	s_addc_u32 s11, s11, g11@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g10@rel32@lo+4
	s_addc_u32 s11, s11, g10@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g12@rel32@lo+4
	s_addc_u32 s11, s11, g12@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g13@rel32@lo+4
	s_addc_u32 s11, s11, g13@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g14@rel32@lo+4
	s_addc_u32 s11, s11, g14@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g15@rel32@lo+4
	s_addc_u32 s11, s11, g15@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g21@rel32@lo+4
	s_addc_u32 s11, s11, g21@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1]
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g20@rel32@lo+4
	s_addc_u32 s11, s11, g20@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g22@rel32@lo+4
	s_addc_u32 s11, s11, g22@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g23@rel32@lo+4
	s_addc_u32 s11, s11, g23@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g24@rel32@lo+4
	s_addc_u32 s11, s11, g24@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g25@rel32@lo+4
	s_addc_u32 s11, s11, g25@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g31@rel32@lo+4
	s_addc_u32 s11, s11, g31@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:16
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g30@rel32@lo+4
	s_addc_u32 s11, s11, g30@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g32@rel32@lo+4
	s_addc_u32 s11, s11, g32@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g33@rel32@lo+4
	s_addc_u32 s11, s11, g33@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g34@rel32@lo+4
	s_addc_u32 s11, s11, g34@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g35@rel32@lo+4
	s_addc_u32 s11, s11, g35@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g41@rel32@lo+4
	s_addc_u32 s11, s11, g41@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:32
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g40@rel32@lo+4
	s_addc_u32 s11, s11, g40@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g42@rel32@lo+4
	s_addc_u32 s11, s11, g42@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g43@rel32@lo+4
	s_addc_u32 s11, s11, g43@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g44@rel32@lo+4
	s_addc_u32 s11, s11, g44@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, g45@rel32@lo+4
	s_addc_u32 s11, s11, g45@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:48
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, g51@rel32@lo+4
	s_addc_u32 s3, s3, g51@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(6) lgkmcnt(0)
	v_mul_f64 v[0:1], s[2:3], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, g50@rel32@lo+4
	s_addc_u32 s3, s3, g50@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[2:3], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, g52@rel32@lo+4
	s_addc_u32 s3, s3, g52@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[4:5], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, g53@rel32@lo+4
	s_addc_u32 s3, s3, g53@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[6:7], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, g54@rel32@lo+4
	s_addc_u32 s3, s3, g54@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[8:9], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, g55@rel32@lo+4
	s_addc_u32 s3, s3, g55@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[10:11], v[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:64
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15Order10FkKernelPdS_S_dS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 12
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15Order10FkKernelPdS_S_dS_, .Lfunc_end3-_Z15Order10FkKernelPdS_S_dS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1832
; NumSgprs: 12
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13Order12KernelPdS_S_dS_ ; -- Begin function _Z13Order12KernelPdS_S_dS_
	.globl	_Z13Order12KernelPdS_S_dS_
	.p2align	8
	.type	_Z13Order12KernelPdS_S_dS_,@function
_Z13Order12KernelPdS_S_dS_:             ; @_Z13Order12KernelPdS_S_dS_
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x20
	v_lshlrev_b32_e32 v14, 3, v0
	s_load_b256 s[0:7], s[0:1], 0x0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh11@rel32@lo+4
	s_addc_u32 s11, s11, bh11@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh10@rel32@lo+4
	s_addc_u32 s11, s11, bh10@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh12@rel32@lo+4
	s_addc_u32 s11, s11, bh12@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh13@rel32@lo+4
	s_addc_u32 s11, s11, bh13@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh14@rel32@lo+4
	s_addc_u32 s11, s11, bh14@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh15@rel32@lo+4
	s_addc_u32 s11, s11, bh15@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh21@rel32@lo+4
	s_addc_u32 s11, s11, bh21@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1]
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh20@rel32@lo+4
	s_addc_u32 s11, s11, bh20@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh22@rel32@lo+4
	s_addc_u32 s11, s11, bh22@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh23@rel32@lo+4
	s_addc_u32 s11, s11, bh23@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh24@rel32@lo+4
	s_addc_u32 s11, s11, bh24@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh25@rel32@lo+4
	s_addc_u32 s11, s11, bh25@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh31@rel32@lo+4
	s_addc_u32 s11, s11, bh31@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:16
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh30@rel32@lo+4
	s_addc_u32 s11, s11, bh30@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh32@rel32@lo+4
	s_addc_u32 s11, s11, bh32@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh33@rel32@lo+4
	s_addc_u32 s11, s11, bh33@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh34@rel32@lo+4
	s_addc_u32 s11, s11, bh34@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh35@rel32@lo+4
	s_addc_u32 s11, s11, bh35@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh41@rel32@lo+4
	s_addc_u32 s11, s11, bh41@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:32
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[0:1], s[10:11], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh40@rel32@lo+4
	s_addc_u32 s11, s11, bh40@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[2:3], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh42@rel32@lo+4
	s_addc_u32 s11, s11, bh42@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[4:5], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh43@rel32@lo+4
	s_addc_u32 s11, s11, bh43@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[6:7], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh44@rel32@lo+4
	s_addc_u32 s11, s11, bh44@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[8:9], v[0:1]
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, bh45@rel32@lo+4
	s_addc_u32 s11, s11, bh45@rel32@hi+12
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[10:11], v[10:11], v[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:48
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x6
	global_load_b64 v[0:1], v14, s[8:9]
	global_load_b64 v[2:3], v14, s[4:5]
	global_load_b64 v[4:5], v14, s[8:9] offset:16
	global_load_b64 v[6:7], v14, s[8:9] offset:32
	global_load_b64 v[8:9], v14, s[8:9] offset:48
	global_load_b64 v[10:11], v14, s[8:9] offset:64
	global_load_b64 v[12:13], v14, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, bh51@rel32@lo+4
	s_addc_u32 s3, s3, bh51@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(6) lgkmcnt(0)
	v_mul_f64 v[0:1], s[2:3], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, bh50@rel32@lo+4
	s_addc_u32 s3, s3, bh50@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[2:3], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, bh52@rel32@lo+4
	s_addc_u32 s3, s3, bh52@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(4) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[4:5], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, bh53@rel32@lo+4
	s_addc_u32 s3, s3, bh53@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[6:7], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, bh54@rel32@lo+4
	s_addc_u32 s3, s3, bh54@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[8:9], v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, bh55@rel32@lo+4
	s_addc_u32 s3, s3, bh55@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], s[2:3], v[10:11], v[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[12:13]
	global_store_b64 v14, v[0:1], s[0:1] offset:64
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13Order12KernelPdS_S_dS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 12
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z13Order12KernelPdS_S_dS_, .Lfunc_end4-_Z13Order12KernelPdS_S_dS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1832
; NumSgprs: 12
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
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	.fill 96, 4, 3214868480
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	.type	a1,@object
	.data
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a1:
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	.size	a1, 8

	.protected	a2                      ; @a2
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a2:
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	.protected	a3                      ; @a3
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a3:
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	.protected	a4                      ; @a4
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a4:
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b10:
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b11:
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b12:
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b13:
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b14:
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b20:
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b21:
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b22:
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b23:
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b24:
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b30:
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b31:
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b32:
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b33:
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b34:
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b40:
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b41:
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b42:
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b43:
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b44:
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g10:
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g12:
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g13:
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g14:
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g15:
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g20:
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g21:
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g22:
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g25:
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g30:
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g32:
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g41:
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g42:
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g43:
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g44:
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g45:
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g51:
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g54:
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g55:
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bh10:
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bh11:
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bh12:
	.quad	0xbf80e27c75e0a843              ; double -0.0082444880936983818
	.size	bh12, 8

	.protected	bh13                    ; @bh13
	.type	bh13,@object
	.globl	bh13
	.p2align	3, 0x0
bh13:
	.quad	0x3f67e1768cbc070f              ; double 0.0029151263642014434
	.size	bh13, 8

	.protected	bh14                    ; @bh14
	.type	bh14,@object
	.globl	bh14
	.p2align	3, 0x0
bh14:
	.quad	0xbf4f9d86eecc165d              ; double -9.6482361331657782E-4
	.size	bh14, 8

	.protected	bh15                    ; @bh15
	.type	bh15,@object
	.globl	bh15
	.p2align	3, 0x0
bh15:
	.quad	0x3f29af1321ded70e              ; double 1.9595249699271743E-4
	.size	bh15, 8

	.protected	bh20                    ; @bh20
	.type	bh20,@object
	.globl	bh20
	.p2align	3, 0x0
bh20:
	.quad	0x3f9048ad66d07b85              ; double 0.015902242088596381
	.size	bh20, 8

	.protected	bh21                    ; @bh21
	.type	bh21,@object
	.globl	bh21
	.p2align	3, 0x0
bh21:
	.quad	0x3fc4d5768063c4ec              ; double 0.16276437062291593
	.size	bh21, 8

	.protected	bh22                    ; @bh22
	.type	bh22,@object
	.globl	bh22
	.p2align	3, 0x0
bh22:
	.quad	0x3fb895869e138415              ; double 0.096031583397703749
	.size	bh22, 8

	.protected	bh23                    ; @bh23
	.type	bh23,@object
	.globl	bh23
	.p2align	3, 0x0
bh23:
	.quad	0xbf8814bef4ec3742              ; double -0.01175831971115893
	.size	bh23, 8

	.protected	bh24                    ; @bh24
	.type	bh24,@object
	.globl	bh24
	.p2align	3, 0x0
bh24:
	.quad	0x3f6aa8dea1bc55d7              ; double 0.0032543514515832417
	.size	bh24, 8

	.protected	bh25                    ; @bh25
	.type	bh25,@object
	.globl	bh25
	.p2align	3, 0x0
bh25:
	.quad	0xbf4445662e376735              ; double -6.1862458499748493E-4
	.size	bh25, 8

	.protected	bh30                    ; @bh30
	.type	bh30,@object
	.globl	bh30
	.p2align	3, 0x0
bh30:
	.quad	0x3fa0000000000000              ; double 0.03125
	.size	bh30, 8

	.protected	bh31                    ; @bh31
	.type	bh31,@object
	.globl	bh31
	.p2align	3, 0x0
bh31:
	.quad	0x3fbe6ae283491e9c              ; double 0.11881843285766042
	.size	bh31, 8

	.protected	bh32                    ; @bh32
	.type	bh32,@object
	.globl	bh32
	.p2align	3, 0x0
bh32:
	.quad	0x3fcfd4fef1b7eb9e              ; double 0.24868761828096536
	.size	bh32, 8

	.protected	bh33                    ; @bh33
	.type	bh33,@object
	.globl	bh33
	.p2align	3, 0x0
bh33:
	.quad	0x3fbc28f5c28f5c29              ; double 0.11
	.size	bh33, 8

	.protected	bh34                    ; @bh34
	.type	bh34,@object
	.globl	bh34
	.p2align	3, 0x0
bh34:
	.quad	0xbf85525c4ddcba11              ; double -0.010410996557394222
	.size	bh34, 8

	.protected	bh35                    ; @bh35
	.type	bh35,@object
	.globl	bh35
	.p2align	3, 0x0
bh35:
	.quad	0x3f5b1d581cd1506e              ; double 0.0016549454187684515
	.size	bh35, 8

	.protected	bh40                    ; @bh40
	.type	bh40,@object
	.globl	bh40
	.p2align	3, 0x0
bh40:
	.quad	0x3f9048ad66d07b85              ; double 0.015902242088596381
	.size	bh40, 8

	.protected	bh41                    ; @bh41
	.type	bh41,@object
	.globl	bh41
	.p2align	3, 0x0
bh41:
	.quad	0x3fc43c841b55db4e              ; double 0.15809680304274781
	.size	bh41, 8

	.protected	bh42                    ; @bh42
	.type	bh42,@object
	.globl	bh42
	.p2align	3, 0x0
bh42:
	.quad	0x3fc82ae3238c92be              ; double 0.18880881534382427
	.size	bh42, 8

	.protected	bh43                    ; @bh43
	.type	bh43,@object
	.globl	bh43
	.p2align	3, 0x0
bh43:
	.quad	0x3fd1f9caf7922a4e              ; double 0.28087114502765054
	.size	bh43, 8

	.protected	bh44                    ; @bh44
	.type	bh44,@object
	.globl	bh44
	.p2align	3, 0x0
bh44:
	.quad	0x3fb895869e138415              ; double 0.096031583397703749
	.size	bh44, 8

	.protected	bh45                    ; @bh45
	.type	bh45,@object
	.globl	bh45
	.p2align	3, 0x0
bh45:
	.quad	0xbf75a6f9678420ac              ; double -0.0052861921651656089
	.size	bh45, 8

	.protected	bh50                    ; @bh50
	.type	bh50,@object
	.globl	bh50
	.p2align	3, 0x0
bh50:
	.quad	0x3fa13f196e71ad15              ; double 0.033684534770907749
	.size	bh50, 8

	.protected	bh51                    ; @bh51
	.type	bh51,@object
	.globl	bh51
	.p2align	3, 0x0
bh51:
	.quad	0x3fbd49d0226356ec              ; double 0.11440754737426645
	.size	bh51, 8

	.protected	bh52                    ; @bh52
	.type	bh52,@object
	.globl	bh52
	.p2align	3, 0x0
bh52:
	.quad	0x3fcf8fac39d7a199              ; double 0.24657204460460205
	.size	bh52, 8

	.protected	bh53                    ; @bh53
	.type	bh53,@object
	.globl	bh53
	.p2align	3, 0x0
bh53:
	.quad	0x3fcaca285cce47fc              ; double 0.20929436236889376
	.size	bh53, 8

	.protected	bh54                    ; @bh54
	.type	bh54,@object
	.globl	bh54
	.p2align	3, 0x0
bh54:
	.quad	0x3fd03f1b3d237004              ; double 0.25385170908498389
	.size	bh54, 8

	.protected	bh55                    ; @bh55
	.type	bh55,@object
	.globl	bh55
	.p2align	3, 0x0
bh55:
	.quad	0x3fad56a7abf44657              ; double 0.05730174993562958
	.size	bh55, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym a1
	.addrsig_sym a2
	.addrsig_sym a3
	.addrsig_sym a4
	.addrsig_sym b10
	.addrsig_sym b11
	.addrsig_sym b12
	.addrsig_sym b13
	.addrsig_sym b14
	.addrsig_sym b20
	.addrsig_sym b21
	.addrsig_sym b22
	.addrsig_sym b23
	.addrsig_sym b24
	.addrsig_sym b30
	.addrsig_sym b31
	.addrsig_sym b32
	.addrsig_sym b33
	.addrsig_sym b34
	.addrsig_sym b40
	.addrsig_sym b41
	.addrsig_sym b42
	.addrsig_sym b43
	.addrsig_sym b44
	.addrsig_sym g10
	.addrsig_sym g11
	.addrsig_sym g12
	.addrsig_sym g13
	.addrsig_sym g14
	.addrsig_sym g15
	.addrsig_sym g20
	.addrsig_sym g21
	.addrsig_sym g22
	.addrsig_sym g23
	.addrsig_sym g24
	.addrsig_sym g25
	.addrsig_sym g30
	.addrsig_sym g31
	.addrsig_sym g32
	.addrsig_sym g33
	.addrsig_sym g34
	.addrsig_sym g35
	.addrsig_sym g40
	.addrsig_sym g41
	.addrsig_sym g42
	.addrsig_sym g43
	.addrsig_sym g44
	.addrsig_sym g45
	.addrsig_sym g50
	.addrsig_sym g51
	.addrsig_sym g52
	.addrsig_sym g53
	.addrsig_sym g54
	.addrsig_sym g55
	.addrsig_sym bh10
	.addrsig_sym bh11
	.addrsig_sym bh12
	.addrsig_sym bh13
	.addrsig_sym bh14
	.addrsig_sym bh15
	.addrsig_sym bh20
	.addrsig_sym bh21
	.addrsig_sym bh22
	.addrsig_sym bh23
	.addrsig_sym bh24
	.addrsig_sym bh25
	.addrsig_sym bh30
	.addrsig_sym bh31
	.addrsig_sym bh32
	.addrsig_sym bh33
	.addrsig_sym bh34
	.addrsig_sym bh35
	.addrsig_sym bh40
	.addrsig_sym bh41
	.addrsig_sym bh42
	.addrsig_sym bh43
	.addrsig_sym bh44
	.addrsig_sym bh45
	.addrsig_sym bh50
	.addrsig_sym bh51
	.addrsig_sym bh52
	.addrsig_sym bh53
	.addrsig_sym bh54
	.addrsig_sym bh55
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9derKernelPdS_
    .private_segment_fixed_size: 0
    .sgpr_count:     4
    .sgpr_spill_count: 0
    .symbol:         _Z9derKernelPdS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11guessKernelPdS_S_d
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z11guessKernelPdS_S_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13order10KernelPdS_S_dS_
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z13order10KernelPdS_S_dS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15Order10FkKernelPdS_S_dS_
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z15Order10FkKernelPdS_S_dS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13Order12KernelPdS_S_dS_
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z13Order12KernelPdS_S_dS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
