#define MAT1 4
#define MAT2 MAT1*MAT1
#define TINY 1.0e-40
#define a(i,j) a[(i)*MAT1+(j)]

#define GO 1
#define NOGO 0

__device__ void d_pivot_decomp(float *a, int *p, int *q){
  int i,j,k;
  int n=MAT1;
  int pi,pj,tmp;
  float max;
  float ftmp;
  for (k=0;k<n;k++){
    pi=-1,pj=-1,max=0.0;
    //find pivot in submatrix a(k:n,k:n)
    for (i=k;i<n;i++) {
      for (j=k;j<n;j++) {
        if (fabs(a(i,j))>max){
          max = fabs(a(i,j));
          pi=i;
          pj=j;
        }
      }
    }
    //Swap Row
    tmp=p[k];
    p[k]=p[pi];
    p[pi]=tmp;
    for (j=0;j<n;j++){
      ftmp=a(k,j);
      a(k,j)=a(pi,j);
      a(pi,j)=ftmp;
    }
    //Swap Col
    tmp=q[k];
    q[k]=q[pj];
    q[pj]=tmp;
    for (i=0;i<n;i++){
      ftmp=a(i,k);
      a(i,k)=a(i,pj);
      a(i,pj)=ftmp;
    }

    //check pivot size and decompose
    if ((fabs(a(k,k))>TINY)){
      for (i=k+1;i<n;i++){
        //Column normalisation
        ftmp=a(i,k)/=a(k,k);
        for (j=k+1;j<n;j++){
          //a(ik)*a(kj) subtracted from lower right submatrix elements
          a(i,j)-=(ftmp*a(k,j));
        }
      }
    }
    //END DECOMPOSE
  }
}

__device__ void d_solve(float *a, float *x, int *p, int *q){
  //forward substitution; see  Golub, Van Loan 96
  int i,ii=0,j;
  float ftmp;
  float xtmp[MAT1];
  //Swap rows (x=Px)
  for (i=0; i<MAT1; i++){
    xtmp[i]=x[p[i]]; //value that should be here
  }
  //Lx=x
  for (i=0;i<MAT1;i++){
    ftmp=xtmp[i];
    if (ii != 0)
      for (j=ii-1;j<i;j++)
        ftmp-=a(i,j)*xtmp[j];
    else
      if (ftmp!=0.0)
        ii=i+1;
    xtmp[i]=ftmp;
  }
  //backward substitution
  //solves Uy=z
  xtmp[MAT1-1]/=a(MAT1-1,MAT1-1);
  for (i=MAT1-2;i>=0;i--){
    ftmp=xtmp[i];
    for (j=i+1;j<MAT1;j++){
      ftmp-=a(i,j)*xtmp[j];
    }
    xtmp[i]=(ftmp)/a(i,i);
  }
  //solves x=Qy
  for (i=0;i<MAT1;i++){
    x[i]=xtmp[q[i]];
  }
}

__global__ void solve(float *A, float *B, int max){
  //Each thread solves the A[id]x[id]=b[id] problem
  int id= blockDim.x*blockIdx.x + threadIdx.x;
  int p_pivot[MAT1],q_pivot[MAT1];
  if ((GO==1) && (id < max)){
    for (int i=0;i<MAT1;i++) {
      p_pivot[i]=q_pivot[i]=i;
    }

    d_pivot_decomp(&A[id*MAT2],&p_pivot[0],&q_pivot[0]);
    d_solve(&A[id*MAT2],&B[id*MAT1],&p_pivot[0],&q_pivot[0]);
  }
}

	.file	"tmpxft_002b949f_00000000-6_cuda-solver.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14d_pivot_decompPfPiS0_
	.type	_Z14d_pivot_decompPfPiS0_, @function
_Z14d_pivot_decompPfPiS0_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z14d_pivot_decompPfPiS0_, .-_Z14d_pivot_decompPfPiS0_
	.globl	_Z7d_solvePfS_PiS0_
	.type	_Z7d_solvePfS_PiS0_, @function
_Z7d_solvePfS_PiS0_:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z7d_solvePfS_PiS0_, .-_Z7d_solvePfS_PiS0_
	.globl	_Z27__device_stub__Z5solvePfS_iPfS_i
	.type	_Z27__device_stub__Z5solvePfS_iPfS_i, @function
_Z27__device_stub__Z5solvePfS_iPfS_i:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5solvePfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z27__device_stub__Z5solvePfS_iPfS_i, .-_Z27__device_stub__Z5solvePfS_iPfS_i
	.globl	_Z5solvePfS_i
	.type	_Z5solvePfS_i, @function
_Z5solvePfS_i:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z5solvePfS_iPfS_i
	.cfi_endproc
.LFE2035:
	.size	_Z5solvePfS_i, .-_Z5solvePfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5solvePfS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5solvePfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define MAT1 4
#define MAT2 MAT1*MAT1
#define TINY 1.0e-40
#define a(i,j) a[(i)*MAT1+(j)]

#define GO 1
#define NOGO 0

__device__ void d_pivot_decomp(float *a, int *p, int *q){
  int i,j,k;
  int n=MAT1;
  int pi,pj,tmp;
  float max;
  float ftmp;
  for (k=0;k<n;k++){
    pi=-1,pj=-1,max=0.0;
    //find pivot in submatrix a(k:n,k:n)
    for (i=k;i<n;i++) {
      for (j=k;j<n;j++) {
        if (fabs(a(i,j))>max){
          max = fabs(a(i,j));
          pi=i;
          pj=j;
        }
      }
    }
    //Swap Row
    tmp=p[k];
    p[k]=p[pi];
    p[pi]=tmp;
    for (j=0;j<n;j++){
      ftmp=a(k,j);
      a(k,j)=a(pi,j);
      a(pi,j)=ftmp;
    }
    //Swap Col
    tmp=q[k];
    q[k]=q[pj];
    q[pj]=tmp;
    for (i=0;i<n;i++){
      ftmp=a(i,k);
      a(i,k)=a(i,pj);
      a(i,pj)=ftmp;
    }

    //check pivot size and decompose
    if ((fabs(a(k,k))>TINY)){
      for (i=k+1;i<n;i++){
        //Column normalisation
        ftmp=a(i,k)/=a(k,k);
        for (j=k+1;j<n;j++){
          //a(ik)*a(kj) subtracted from lower right submatrix elements
          a(i,j)-=(ftmp*a(k,j));
        }
      }
    }
    //END DECOMPOSE
  }
}

__device__ void d_solve(float *a, float *x, int *p, int *q){
  //forward substitution; see  Golub, Van Loan 96
  int i,ii=0,j;
  float ftmp;
  float xtmp[MAT1];
  //Swap rows (x=Px)
  for (i=0; i<MAT1; i++){
    xtmp[i]=x[p[i]]; //value that should be here
  }
  //Lx=x
  for (i=0;i<MAT1;i++){
    ftmp=xtmp[i];
    if (ii != 0)
      for (j=ii-1;j<i;j++)
        ftmp-=a(i,j)*xtmp[j];
    else
      if (ftmp!=0.0)
        ii=i+1;
    xtmp[i]=ftmp;
  }
  //backward substitution
  //solves Uy=z
  xtmp[MAT1-1]/=a(MAT1-1,MAT1-1);
  for (i=MAT1-2;i>=0;i--){
    ftmp=xtmp[i];
    for (j=i+1;j<MAT1;j++){
      ftmp-=a(i,j)*xtmp[j];
    }
    xtmp[i]=(ftmp)/a(i,i);
  }
  //solves x=Qy
  for (i=0;i<MAT1;i++){
    x[i]=xtmp[q[i]];
  }
}

__global__ void solve(float *A, float *B, int max){
  //Each thread solves the A[id]x[id]=b[id] problem
  int id= blockDim.x*blockIdx.x + threadIdx.x;
  int p_pivot[MAT1],q_pivot[MAT1];
  if ((GO==1) && (id < max)){
    for (int i=0;i<MAT1;i++) {
      p_pivot[i]=q_pivot[i]=i;
    }

    d_pivot_decomp(&A[id*MAT2],&p_pivot[0],&q_pivot[0]);
    d_solve(&A[id*MAT2],&B[id*MAT1],&p_pivot[0],&q_pivot[0]);
  }
}

	.text
	.file	"cuda-solver.hip"
	.globl	_Z20__device_stub__solvePfS_i   # -- Begin function _Z20__device_stub__solvePfS_i
	.type	_Z20__device_stub__solvePfS_i,@function
_Z20__device_stub__solvePfS_i:          # @_Z20__device_stub__solvePfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5solvePfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__solvePfS_i, .Lfunc_end0-_Z20__device_stub__solvePfS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5solvePfS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5solvePfS_i,@object           # @_Z5solvePfS_i
	.section	.rodata,"a",@progbits
	.globl	_Z5solvePfS_i
	.p2align	3, 0x0
_Z5solvePfS_i:
	.quad	_Z20__device_stub__solvePfS_i
	.size	_Z5solvePfS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5solvePfS_i"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__solvePfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5solvePfS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5solvePfS_i           ; -- Begin function _Z5solvePfS_i
	.globl	_Z5solvePfS_i
	.p2align	8
	.type	_Z5solvePfS_i,@function
_Z5solvePfS_i:                          ; @_Z5solvePfS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v8
	s_cbranch_execz .LBB0_41
; %bb.1:                                ; %.preheader.preheader
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr8
.LBB0_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 2
	s_cselect_b32 s10, s2, s10
	s_cselect_b32 s6, s2, s6
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 s9, s2, s9
	s_cselect_b32 s5, s2, s5
	s_cmp_eq_u32 s2, 3
	s_cselect_b32 s11, s2, s11
	s_cselect_b32 s7, s2, s7
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s8, s2, s8
	s_cselect_b32 s4, s2, s4
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 4
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	s_load_b128 s[12:15], s[0:1], 0x0
	v_lshlrev_b32_e32 v4, 4, v8
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s11
	v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v10, 0
	s_mov_b32 s10, 0x2777579c
	s_mov_b32 s11, 0x37a16c26
	v_lshlrev_b64 v[13:14], 2, v[4:5]
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
	v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s12, v13
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v14, vcc_lo
.LBB0_4:                                ; %.preheader106.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;     Child Loop BB0_9 Depth 2
                                        ;     Child Loop BB0_11 Depth 2
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_16 Depth 3
	v_lshl_add_u32 v17, v24, 2, v24
	v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v15, -1
	v_dual_mov_b32 v9, v10 :: v_dual_mov_b32 v16, v24
	v_mov_b32_e32 v25, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[17:18]
	s_mov_b32 s1, 0
	v_add_co_u32 v20, vcc_lo, v11, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, v12, v19, vcc_lo
.LBB0_5:                                ; %.preheader.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v23, v21 :: v_dual_mov_b32 v22, v20
	v_mov_b32_e32 v26, v24
	s_mov_b32 s2, 0
.LBB0_6:                                ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v27, v[22:23], off
	v_add_co_u32 v22, vcc_lo, v22, 4
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	v_cmp_lt_u32_e64 s0, 2, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 s2, s0, s2
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e64 vcc_lo, |v27|, v9
	v_dual_cndmask_b32 v25, v25, v16 :: v_dual_add_nc_u32 v28, 1, v26
	v_dual_cndmask_b32 v15, v15, v26 :: v_dual_mov_b32 v26, v28
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, |v27|, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v22, 1, v16
	v_cmp_lt_u32_e32 vcc_lo, 2, v16
	v_add_co_u32 v20, s0, v20, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v21, s0, 0, v21, s0
	v_mov_b32_e32 v16, v22
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_5
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b32_e32 v20, 2, v25
	v_lshlrev_b32_e32 v9, 2, v24
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[22:23], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v9, vcc_lo, v11, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v16, vcc_lo, v12, v21, vcc_lo
	v_add_co_u32 v20, vcc_lo, v11, v22
	v_add_co_ci_u32_e32 v21, vcc_lo, v12, v23, vcc_lo
.LBB0_9:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, v9, s0
	v_add_co_ci_u32_e32 v23, vcc_lo, s1, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v26, vcc_lo, v20, s0
	v_add_co_ci_u32_e32 v27, vcc_lo, s1, v21, vcc_lo
	s_add_u32 s0, s0, 4
	s_clause 0x1
	global_load_b32 v28, v[22:23], off
	global_load_b32 v29, v[26:27], off
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 16
	s_waitcnt vmcnt(1)
	global_store_b32 v[26:27], v28, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[22:23], v29, off
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v16, 31, v15
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[15:16]
	v_add_co_u32 v20, vcc_lo, v11, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, v12, v21, vcc_lo
.LBB0_11:                               ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v9, s0, v24
	global_load_b32 v16, v[20:21], off
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 16
	v_lshlrev_b64 v[22:23], 2, v[9:10]
	v_add_co_u32 v22, vcc_lo, v11, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v23, vcc_lo, v12, v23, vcc_lo
	global_load_b32 v9, v[22:23], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[22:23], v16, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[20:21], v9, off
	v_add_co_u32 v20, vcc_lo, v20, 16
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	s_cbranch_scc1 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v18, vcc_lo, v11, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, v12, v19, vcc_lo
	v_add_nc_u32_e32 v22, 1, v24
	s_mov_b32 s1, exec_lo
	global_load_b32 v9, v[18:19], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e64 v[20:21], |v9|
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f64_e32 s[10:11], v[20:21]
	s_cbranch_execz .LBB0_20
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v9, 4
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e32 3, v24
	s_cbranch_execz .LBB0_19
; %bb.14:                               ; %.lr.ph125.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v26, v22 :: v_dual_add_nc_u32 v9, 1, v17
	v_add_nc_u32_e32 v23, 5, v17
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[9:10]
	v_add_co_u32 v16, vcc_lo, v11, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, v12, v21, vcc_lo
.LBB0_15:                               ; %.lr.ph125.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_16 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v9, v26, 2, v24
	s_mov_b32 s4, 0
	v_lshlrev_b64 v[20:21], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, v11, v20
	v_add_co_ci_u32_e32 v30, vcc_lo, v12, v21, vcc_lo
	s_clause 0x1
	global_load_b32 v9, v[18:19], off
	global_load_b32 v27, v[29:30], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v20, null, v9, v9, v27
	v_div_scale_f32 v31, vcc_lo, v27, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v20, v21, 1.0
	v_fmac_f32_e32 v21, v28, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v31, v21
	v_fma_f32 v32, -v20, v28, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v32, v21
	v_fma_f32 v20, -v20, v28, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v28, v20, v21, v28
	v_dual_mov_b32 v21, v17 :: v_dual_mov_b32 v20, v16
	v_div_fixup_f32 v27, v28, v9, v27
	v_dual_mov_b32 v9, v23 :: v_dual_mov_b32 v28, v24
	global_store_b32 v[29:30], v27, off
.LBB0_16:                               ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_lshlrev_b64 v[29:30], 2, v[9:10]
	v_add_nc_u32_e32 v28, 1, v28
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e64 s0, 2, v28
	v_add_co_u32 v29, vcc_lo, v11, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, v12, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	s_or_b32 s4, s0, s4
	global_load_b32 v31, v[20:21], off
	global_load_b32 v32, v[29:30], off
	v_add_co_u32 v20, vcc_lo, v20, 4
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f32 v31, -v27, v31, v32
	global_store_b32 v[29:30], v31, off
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_16
; %bb.17:                               ; %._crit_edge122.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v9, 1, v26
	v_cmp_lt_u32_e32 vcc_lo, 2, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v26, v9 :: v_dual_add_nc_u32 v23, 4, v23
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_15
; %bb.18:                               ; %Flow167
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v9, v22
.LBB0_19:                               ; %Flow168
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v22, v9
.LBB0_20:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e32 vcc_lo, 1, v15
	v_cmp_eq_u32_e64 s0, 2, v15
	v_cmp_eq_u32_e64 s1, 3, v15
	v_cmp_eq_u32_e64 s2, 1, v24
	v_cmp_eq_u32_e64 s4, 2, v24
	v_cndmask_b32_e32 v9, v0, v1, vcc_lo
	v_cmp_eq_u32_e64 s6, 3, v24
	v_cmp_eq_u32_e64 s8, 0, v24
	v_mov_b32_e32 v24, v22
	v_cmp_eq_u32_e64 s3, 1, v25
	v_cndmask_b32_e64 v9, v9, v2, s0
	v_cmp_eq_u32_e64 s5, 2, v25
	v_cndmask_b32_e64 v19, v4, v5, s2
	v_cmp_eq_u32_e64 s7, 3, v25
	v_cndmask_b32_e64 v16, v4, v5, s3
	v_cndmask_b32_e64 v9, v9, v3, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v6, s4
	v_cndmask_b32_e64 v16, v16, v6, s5
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v1, v9, s2
	v_cndmask_b32_e64 v1, v0, v1, s2
	v_cndmask_b32_e64 v18, v2, v9, s4
	v_cndmask_b32_e64 v0, v0, v9, s8
	v_cndmask_b32_e64 v16, v16, v7, s7
	v_cndmask_b32_e64 v19, v19, v7, s6
	v_cndmask_b32_e64 v1, v1, v2, s4
	v_cndmask_b32_e64 v2, v3, v9, s6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v5, v16, s2
	v_cndmask_b32_e64 v9, v7, v16, s6
	v_cndmask_b32_e64 v20, v1, v3, s6
	v_cndmask_b32_e64 v6, v6, v16, s4
	v_cndmask_b32_e64 v4, v4, v16, s8
	v_cndmask_b32_e64 v5, v5, v19, s3
	v_cndmask_b32_e64 v7, v9, v19, s7
	v_cndmask_b32_e32 v1, v17, v20, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_cndmask_b32_e64 v3, v2, v20, s1
	v_cndmask_b32_e64 v2, v18, v20, s0
	v_cmp_eq_u32_e64 s0, 0, v25
	v_cndmask_b32_e64 v6, v6, v19, s5
	v_cndmask_b32_e32 v0, v0, v20, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v4, v4, v19, s0
	s_or_b32 s9, vcc_lo, s9
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_4
; %bb.21:                               ; %_Z14d_pivot_decompPfPiS0_.exit
	s_or_b32 exec_lo, exec_lo, s9
	v_lshlrev_b32_e32 v8, 2, v8
	s_mov_b64 s[4:5], 0
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v16, vcc_lo, s15, v9, vcc_lo
                                        ; implicit-def: $vgpr7_vgpr8_vgpr9_vgpr10
                                        ; implicit-def: $vgpr7_vgpr8_vgpr9_vgpr10
                                        ; implicit-def: $vgpr7_vgpr8_vgpr9_vgpr10
.LBB0_22:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 2
	v_cndmask_b32_e32 v18, v4, v5, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s4, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v6, s0
	s_cmp_eq_u32 s4, 0
	v_cndmask_b32_e64 v18, v18, v7, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s2, v15, v18
	v_add_co_ci_u32_e64 v19, s2, v16, v19, s2
	s_cselect_b32 s2, -1, 0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	global_load_b32 v18, v[18:19], off
	s_cmp_lg_u32 s4, 4
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v10, v10, v18, s1
	v_cndmask_b32_e64 v9, v9, v18, s0
	v_cndmask_b32_e32 v8, v8, v18, vcc_lo
	v_cndmask_b32_e64 v17, v17, v18, s2
	s_cbranch_scc1 .LBB0_22
; %bb.23:                               ; %.preheader57.i.preheader
	v_mov_b32_e32 v6, 0
	s_mov_b32 s1, 0
	s_mov_b32 s4, -1
.LBB0_24:                               ; %.preheader57.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_27 Depth 2
	s_cmp_eq_u32 s1, 1
	s_mov_b32 s0, exec_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	v_cndmask_b32_e32 v4, v17, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v7, v4, v10, vcc_lo
	v_cmpx_ne_u32_e32 0, v6
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB0_30
; %bb.25:                               ;   in Loop: Header=BB0_24 Depth=1
	s_mov_b32 s6, exec_lo
	v_cmpx_ge_i32_e64 s1, v6
	s_cbranch_execz .LBB0_29
; %bb.26:                               ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_24 Depth=1
	v_add_nc_u32_e32 v4, s4, v6
	v_add_nc_u32_e32 v18, -1, v6
	s_mov_b64 s[2:3], 0
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v12, v5, vcc_lo
.LBB0_27:                               ;   Parent Loop BB0_24 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v19, v[4:5], off
	v_add_nc_u32_e32 v20, s2, v18
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	v_add3_u32 v22, v6, s2, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s0, s1, v22
	v_cndmask_b32_e32 v21, v17, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 s7, s0, s7
	v_cndmask_b32_e32 v21, v21, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, v21, v10, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f32 v7, -v19, v20, v7
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_27
; %bb.28:                               ; %Flow163
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_29:                               ; %Flow164
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_30:                               ; %Flow166
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_and_not1_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_34
; %bb.31:                               ;   in Loop: Header=BB0_24 Depth=1
	v_mov_b32_e32 v6, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_neq_f32_e32 0, v7
; %bb.32:                               ;   in Loop: Header=BB0_24 Depth=1
	s_add_i32 s3, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s3
; %bb.33:                               ; %Flow165
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_34:                               ; %.loopexit.i17
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_eq_u32 s1, 3
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	v_cndmask_b32_e32 v10, v10, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 1
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 0
	v_cndmask_b32_e32 v8, v8, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_i32 s1, s1, 1
	v_cndmask_b32_e32 v17, v17, v7, vcc_lo
	s_add_i32 s4, s4, 4
	s_cmp_lg_u32 s1, 4
	s_cbranch_scc1 .LBB0_24
; %bb.35:
	global_load_b32 v4, v[11:12], off offset:60
	s_mov_b32 s6, 2
	s_mov_b64 s[2:3], 3
	s_mov_b32 s5, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v5, null, v4, v4, v10
	v_div_scale_f32 v18, vcc_lo, v10, v4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v5, v6, 1.0
	v_fmac_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v18, v6
	v_fma_f32 v19, -v5, v7, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v19, v6
	v_fma_f32 v5, -v5, v7, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v5, v5, v6, v7
	v_add_co_u32 v6, vcc_lo, v13, s12
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v14, vcc_lo
	v_div_fixup_f32 v10, v5, v4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v6, 44
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
.LBB0_36:                               ; %.lr.ph68.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_37 Depth 2
	s_cmp_eq_u32 s6, 1
	s_mov_b64 s[0:1], s[2:3]
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v6, v17, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v13, v6, v10, vcc_lo
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
.LBB0_37:                               ;   Parent Loop BB0_36 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v14, v[6:7], off
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v18, v17, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v18, v18, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 4
	v_cndmask_b32_e32 v18, v18, v10, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v13, -v14, v18, v13
	s_cbranch_scc1 .LBB0_37
; %bb.38:                               ; %._crit_edge.i18
                                        ;   in Loop: Header=BB0_36 Depth=1
	s_mul_i32 s4, s6, 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_cmp_eq_u32 s6, 3
	v_add_co_u32 v6, vcc_lo, v11, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v12, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v7, null, v6, v6, v13
	v_div_scale_f32 v19, vcc_lo, v13, v6, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v7, v14, 1.0
	v_fmac_f32_e32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v14
	v_fma_f32 v20, -v7, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v14
	v_fma_f32 v7, -v7, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v14, v18
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	s_cselect_b32 s0, -1, 0
	v_div_fixup_f32 v6, v7, v6, v13
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e64 v9, v9, v6, s0
	v_cndmask_b32_e32 v17, v17, v6, vcc_lo
	v_add_co_u32 v4, vcc_lo, 0xffffffec, v4
	v_cndmask_b32_e64 v8, v8, v6, s1
	s_add_i32 s0, s6, -1
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v5, vcc_lo
	s_add_u32 s2, s2, -1
	s_addc_u32 s3, s3, -1
	s_cmp_lg_u32 s6, 0
	s_mov_b32 s6, s0
	s_cbranch_scc1 .LBB0_36
; %bb.39:                               ; %.preheader.i19.preheader
	s_mov_b64 s[0:1], 0
.LBB0_40:                               ; %.preheader.i19
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v4, v0, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v4, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	v_cndmask_b32_e32 v5, v17, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v4
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v5, v10, vcc_lo
	global_store_b32 v[15:16], v4, off
	v_add_co_u32 v15, vcc_lo, v15, 4
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	s_cbranch_scc0 .LBB0_40
.LBB0_41:                               ; %_Z7d_solvePfS_PiS0_.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5solvePfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5solvePfS_i, .Lfunc_end0-_Z5solvePfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2740
; NumSgprs: 18
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5solvePfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5solvePfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
