#include <stdio.h>
#include <stdlib.h>

/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
__global__ void rates(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {
            float temp9 = temp[j] * 1.0e-9;
            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                switch(k)
                {
                    case 0:
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
                        break;
                    case 6: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9)); 
                        break;
                    default: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f)); 
                        break;
                }
            }
        }
    }
}

int main()
{
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);
        
    // Tensor dimensions
    int nsets = 4, ncells = 4, ncoeff = 8;
    // Loop variables
    int i, j;
    // Tensors
    float *a, *temp, *lam;
    
    /*********************************************************
    * Allocate memory for coefficients and initialize matrix *
    *********************************************************/
    cudaMallocManaged(&a, nsets * ncoeff * sizeof(float));
    
    printf("a:\n");
    
    for(i = 0; i < nsets; i++)
    {
        for(j = 0; j < ncoeff; j++)
        {
            if(j != 7)
            {
                a[i * ncoeff + j] = i * (ncoeff - 1) + j + 1;
            }
            else
            {
                a[i * ncoeff + j] = 0.0;
            }
            printf("%.3f\t", a[i * ncoeff + j]);
        }
        
        printf("\n");
    }
    
    printf("\n");
    
    /***********************************************
    * Do the same for the temperature of each cell *
    ***********************************************/
    cudaMallocManaged(&temp, ncells * sizeof(float));
    printf("temp:\n");
    
    for(i = 0; i < ncells; i++)
    {
        temp[i] = (i + 1) * 1e9;
        printf("%.3f\t", temp[i]);
    }
    
    printf("\n\n");
    
    /*******************************************
    * Allocate space for the summation results *
    *******************************************/
    cudaMallocManaged(&lam, nsets * ncells * sizeof(float));
    
    for(i = 0; i < nsets; i++)
    {
        for(j = 0; j < ncells; j++)
        {
            lam[i * ncells + j] = 0.0;
        }
    }
    
    /****************************************************************
    * Compute ln(lambda) for each set and cell and print the result *
    ****************************************************************/
    dim3 threadsPerBlock(nsets, ncells, ncoeff);
    dim3 numBlocks(1, 1, 1);
    
    cudaEventRecord(start);
    rates<<<numBlocks, threadsPerBlock>>>(a, temp, lam, nsets, ncells, ncoeff);
    cudaEventRecord(stop);
    
    cudaDeviceSynchronize();
    printf("lambda:\n");
    
    for(i = 0; i < nsets; i++)
    {
        for(j = 0; j < ncells; j++)
        {
            printf("%.3f\t", lam[i * ncells + j]);
        }
        
        printf("\n");
    }
    
    /*********************
    * Print elapsed time *
    *********************/
    cudaEventSynchronize(stop);
    float elapsed = 0.0f;
    cudaEventElapsedTime(&elapsed, start, stop);
    printf("\nTime elapsed: %.1f us\n", 1000 * elapsed);
    
    /**************
    * Free memory *
    **************/
    cudaFree(a);
    cudaFree(temp);
    cudaFree(lam);
    
    return 0;
}

	.file	"tmpxft_0025108c_00000000-6_react.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii
	.type	_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii, @function
_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z5ratesPfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii, .-_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii
	.globl	_Z5ratesPfS_S_iii
	.type	_Z5ratesPfS_S_iii, @function
_Z5ratesPfS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z5ratesPfS_S_iii, .-_Z5ratesPfS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"a:\n"
.LC2:
	.string	"%.3f\t"
.LC3:
	.string	"\n"
.LC4:
	.string	"temp:\n"
.LC6:
	.string	"\n\n"
.LC7:
	.string	"lambda:\n"
.LC9:
	.string	"\nTime elapsed: %.1f us\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC2(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$128, %esi
	call	cudaMallocManaged@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L9:
	imull	$-8, %r12d, %r13d
	leaq	28(%r14), %r15
	xorl	%ebx, %ebx
.L12:
	movq	24(%rsp), %rax
	cmpq	$7, %rbx
	je	.L10
	leal	1(%r13,%r12), %ecx
	movslq	%r13d, %rdx
	cvtsi2ssl	%ecx, %xmm0
	movss	%xmm0, (%rax,%rdx,4)
	jmp	.L11
.L10:
	movl	$0x00000000, (%rax,%r15)
.L11:
	leaq	(%rax,%rbx,4), %rax
	movq	%rbp, %rsi
	movl	$2, %edi
	incq	%rbx
	cvtss2sd	(%rax,%r14), %xmm0
	movb	$1, %al
	incl	%r13d
	call	__printf_chk@PLT
	cmpq	$8, %rbx
	jne	.L12
	leaq	.LC3(%rip), %rbx
	xorl	%eax, %eax
	decl	%r12d
	addq	$32, %r14
	movq	%rbx, %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	cmpl	$-4, %r12d
	jne	.L9
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	xorl	%r12d, %r12d
	movl	$16, %esi
	call	cudaMallocManaged@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L14:
	incl	%r12d
	movq	32(%rsp), %rax
	movq	%rbp, %rsi
	movl	$2, %edi
	cvtsi2sdl	%r12d, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%r13)
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	addq	$4, %r13
	cmpl	$4, %r12d
	jne	.L14
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edx
	leaq	40(%rsp), %rdi
	movl	$64, %esi
	call	cudaMallocManaged@PLT
	movq	40(%rsp), %rdi
	xorl	%eax, %eax
	xorl	%esi, %esi
	movl	$16, %ecx
	movl	$8, 56(%rsp)
	rep stosl
	movq	8(%rsp), %rdi
	movl	$1, 68(%rsp)
	movabsq	$17179869188, %rax
	movq	%rax, 48(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	call	cudaEventRecord@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$8, %r9d
	movl	$4, %r8d
	movq	24(%rsp), %rdi
	movl	$4, %ecx
	call	_Z31__device_stub__Z5ratesPfS_S_iiiPfS_S_iii
.L15:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%r13d, %r13d
	call	cudaEventRecord@PLT
	call	cudaDeviceSynchronize@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L16:
	xorl	%r12d, %r12d
.L17:
	leaq	0(,%r12,4), %rax
	addq	40(%rsp), %rax
	movq	%rbp, %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%r13), %xmm0
	incq	%r12
	movb	$1, %al
	call	__printf_chk@PLT
	cmpq	$4, %r12
	jne	.L17
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$16, %r13
	call	__printf_chk@PLT
	cmpq	$64, %r13
	jne	.L16
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$0x00000000, 4(%rsp)
	call	cudaEventElapsedTime@PLT
	movss	.LC8(%rip), %xmm0
	mulss	4(%rsp), %xmm0
	movb	$1, %al
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z5ratesPfS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5ratesPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC5:
	.long	0
	.long	1104006501
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC8:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
__global__ void rates(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {
            float temp9 = temp[j] * 1.0e-9;
            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                switch(k)
                {
                    case 0:
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
                        break;
                    case 6: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9)); 
                        break;
                    default: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f)); 
                        break;
                }
            }
        }
    }
}

int main()
{
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);
        
    // Tensor dimensions
    int nsets = 4, ncells = 4, ncoeff = 8;
    // Loop variables
    int i, j;
    // Tensors
    float *a, *temp, *lam;
    
    /*********************************************************
    * Allocate memory for coefficients and initialize matrix *
    *********************************************************/
    hipMallocManaged(&a, nsets * ncoeff * sizeof(float));
    
    printf("a:\n");
    
    for(i = 0; i < nsets; i++)
    {
        for(j = 0; j < ncoeff; j++)
        {
            if(j != 7)
            {
                a[i * ncoeff + j] = i * (ncoeff - 1) + j + 1;
            }
            else
            {
                a[i * ncoeff + j] = 0.0;
            }
            printf("%.3f\t", a[i * ncoeff + j]);
        }
        
        printf("\n");
    }
    
    printf("\n");
    
    /***********************************************
    * Do the same for the temperature of each cell *
    ***********************************************/
    hipMallocManaged(&temp, ncells * sizeof(float));
    printf("temp:\n");
    
    for(i = 0; i < ncells; i++)
    {
        temp[i] = (i + 1) * 1e9;
        printf("%.3f\t", temp[i]);
    }
    
    printf("\n\n");
    
    /*******************************************
    * Allocate space for the summation results *
    *******************************************/
    hipMallocManaged(&lam, nsets * ncells * sizeof(float));
    
    for(i = 0; i < nsets; i++)
    {
        for(j = 0; j < ncells; j++)
        {
            lam[i * ncells + j] = 0.0;
        }
    }
    
    /****************************************************************
    * Compute ln(lambda) for each set and cell and print the result *
    ****************************************************************/
    dim3 threadsPerBlock(nsets, ncells, ncoeff);
    dim3 numBlocks(1, 1, 1);
    
    hipEventRecord(start);
    rates<<<numBlocks, threadsPerBlock>>>(a, temp, lam, nsets, ncells, ncoeff);
    hipEventRecord(stop);
    
    hipDeviceSynchronize();
    printf("lambda:\n");
    
    for(i = 0; i < nsets; i++)
    {
        for(j = 0; j < ncells; j++)
        {
            printf("%.3f\t", lam[i * ncells + j]);
        }
        
        printf("\n");
    }
    
    /*********************
    * Print elapsed time *
    *********************/
    hipEventSynchronize(stop);
    float elapsed = 0.0f;
    hipEventElapsedTime(&elapsed, start, stop);
    printf("\nTime elapsed: %.1f us\n", 1000 * elapsed);
    
    /**************
    * Free memory *
    **************/
    hipFree(a);
    hipFree(temp);
    hipFree(lam);
    
    return 0;
}

	.text
	.file	"react.hip"
	.globl	_Z20__device_stub__ratesPfS_S_iii # -- Begin function _Z20__device_stub__ratesPfS_S_iii
	.type	_Z20__device_stub__ratesPfS_S_iii,@function
_Z20__device_stub__ratesPfS_S_iii:      # @_Z20__device_stub__ratesPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5ratesPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__ratesPfS_S_iii, .Lfunc_end0-_Z20__device_stub__ratesPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI1_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	movl	$128, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %ebx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB1_1:                                # %.preheader72
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	leaq	7(,%r15,8), %r12
	xorl	%r13d, %r13d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	$7, %r13
	jne	.LBB1_3
# %bb.4:                                #   in Loop: Header=BB1_2 Depth=2
	movq	(%rsp), %rax
	movl	$0, (%rax,%r12,4)
	movss	(%rax,%r12,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	jmp	.LBB1_5
.LBB1_3:                                #   in Loop: Header=BB1_2 Depth=2
	leal	(%rbx,%r13), %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movq	(%rsp), %rax
	addq	%r14, %rax
	movss	%xmm0, (%rax,%r13,4)
.LBB1_5:                                #   in Loop: Header=BB1_2 Depth=2
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	incq	%r13
	cmpq	$8, %r13
	jne	.LBB1_2
# %bb.6:                                #   in Loop: Header=BB1_1 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r15
	addq	$32, %r14
	addq	$7, %rbx
	cmpq	$4, %r15
	jne	.LBB1_1
# %bb.7:
	movl	$10, %edi
	callq	putchar@PLT
	leaq	16(%rsp), %rdi
	movl	$16, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%eax, %eax
.LBB1_8:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%rax), %rbx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebx, %xmm0
	mulsd	.LCPI1_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movq	16(%rsp), %rcx
	movss	%xmm0, (%rcx,%rax,4)
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rax
	cmpq	$4, %rbx
	jne	.LBB1_8
# %bb.9:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	leaq	8(%rsp), %rbx
	movl	$64, %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbx), %rax
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rax)
	movups	%xmm0, 16(%rax)
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 48(%rax)
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_11
# %bb.10:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$4, %ecx
	movl	$4, %r8d
	movl	$8, %r9d
	callq	_Z20__device_stub__ratesPfS_S_iii
.LBB1_11:
	movq	24(%rsp), %rdi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	hipEventRecord
	callq	hipDeviceSynchronize
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB1_12:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_13 Depth 2
	xorl	%r15d, %r15d
.LBB1_13:                               #   Parent Loop BB1_12 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rsp), %rax
	addq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r15,4), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$4, %r15
	jne	.LBB1_13
# %bb.14:                               #   in Loop: Header=BB1_12 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$16, %rbx
	cmpq	$4, %r14
	jne	.LBB1_12
# %bb.15:
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	44(%rsp), %rbx
	movl	$0, (%rbx)
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	mulss	.LCPI1_1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movq	(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5ratesPfS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5ratesPfS_S_iii,@object       # @_Z5ratesPfS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z5ratesPfS_S_iii
	.p2align	3, 0x0
_Z5ratesPfS_S_iii:
	.quad	_Z20__device_stub__ratesPfS_S_iii
	.size	_Z5ratesPfS_S_iii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%.3f\t"
	.size	.L.str.1, 6

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nTime elapsed: %.1f us\n"
	.size	.L.str.6, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5ratesPfS_S_iii"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"a:"
	.size	.Lstr, 3

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"temp:"
	.size	.Lstr.1, 6

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"\n"
	.size	.Lstr.2, 2

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"lambda:"
	.size	.Lstr.3, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__ratesPfS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5ratesPfS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5ratesPfS_S_iii       ; -- Begin function _Z5ratesPfS_S_iii
	.globl	_Z5ratesPfS_S_iii
	.p2align	8
	.type	_Z5ratesPfS_S_iii,@function
_Z5ratesPfS_S_iii:                      ; @_Z5ratesPfS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x34
	s_load_b128 s[8:11], s[0:1], 0x18
	v_and_b32_e32 v3, 0x3ff, v0
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s13, s4, v[3:4]
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB0_21
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x2
	s_load_b32 s11, s[0:1], 0x38
	s_load_b64 s[12:13], s[2:3], 0x0
	s_load_b32 s2, s[2:3], 0x8
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[6:7], s[0:1], 0x10
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s20, 0
	s_mov_b32 s21, 0x3e76c4e1
	v_mad_u64_u32 v[2:3], null, s14, s0, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s11, 0xffff
	s_mul_i32 s14, s13, s0
	s_and_b32 s3, s1, 0xffff
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s9, v2
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	s_mul_i32 s11, s12, s4
	s_mov_b32 s12, 0xe826d695
	s_mov_b32 s13, 0x3e112e0b
	s_mul_i32 s15, s2, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, s10, v3
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_20
; %bb.3:                                ; %.lr.ph62
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mul_lo_u32 v4, v1, s10
	v_mul_lo_u32 v0, v1, s9
	v_mov_b32_e32 v6, v2
	s_mov_b32 s23, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
	s_and_saveexec_b32 s24, s1
	s_cbranch_execz .LBB0_19
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s18, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[7:8], v7
	v_mul_f64 v[7:8], v[7:8], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v12, v[7:8]
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v12
	v_cmp_eq_f32_e64 s2, 1.0, v12
	v_cndmask_b32_e64 v7, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v12, v7
	v_log_f32_e32 v9, v7
	v_add_nc_u32_e32 v7, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x3f317217, v9
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_fma_f32 v11, 0x3f317217, v9, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0x3377d1cf, v9
	v_add_f32_e32 v10, v10, v11
	v_cndmask_b32_e64 v11, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v9|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	v_sub_f32_e32 v13, v9, v11
	v_mov_b32_e32 v9, v3
.LBB0_6:                                ; %NodeBlock
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_17 Depth 4
	s_mov_b32 s26, 0
	s_mov_b32 s3, 0
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 5, v9
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_10
; %bb.7:                                ; %LeafBlock86
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_mov_b32 s3, -1
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_eq_u32_e32 6, v9
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=3
	global_load_b32 v10, v[4:5], off offset:24
	s_xor_b32 s3, exec_lo, -1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v14, v13, v10
.LBB0_9:                                ; %Flow88
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_and_not1_saveexec_b32 s4, s4
; %bb.11:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_6 Depth=3
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	s_and_not1_b32 s3, s3, exec_lo
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr14
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s5
; %bb.12:                               ; %Flow89
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s27, exec_lo, s4
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_6 Depth=3
	v_lshl_add_u32 v10, v9, 1, -5
	s_and_not1_b32 s26, s26, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v10, v10
	v_div_scale_f32 v11, null, 0x40400000, 0x40400000, v10
	v_div_scale_f32 v16, vcc_lo, v10, 0x40400000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v11, v14, 1.0
	v_fmac_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v16, v14
	v_fma_f32 v17, -v11, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v17, v14
	v_fma_f32 v11, -v11, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v14, v15
	v_div_fixup_f32 v10, v11, 0x40400000, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v10, 1.0, s2
	v_cmp_neq_f32_e32 vcc_lo, 0, v14
	v_cmp_neq_f32_e64 s28, v14, |v14|
	v_cndmask_b32_e32 v15, 1.0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v10, |v15|
	v_cmp_lt_f32_e64 s29, |v15|, 1.0
	v_cmp_eq_f32_e64 s5, 0, v15
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s28, s28, s29
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	v_ldexp_f32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, 1.0, v10
	v_add_f32_e32 v17, -1.0, v10
	v_rcp_f32_e32 v16, v11
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v18, v17, v16 :: v_dual_add_f32 v19, -1.0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, v11, v18
	v_sub_f32_e32 v10, v10, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v18, v11, -v20
	v_fmac_f32_e32 v11, v18, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v20, v11
	v_dual_sub_f32 v19, v17, v10 :: v_dual_sub_f32 v20, v10, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v17, v19
	v_sub_f32_e32 v11, v20, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v17, v10
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_f32_e32 v17, v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[9:10]
	v_add_f32_e32 v17, v19, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, v4, v10
	v_add_co_ci_u32_e64 v11, s3, v5, v11, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v16, v17
	global_load_b32 v10, v[10:11], off
	v_add_f32_e32 v11, v18, v16
	v_sub_f32_e32 v17, v11, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v16, v17
	v_dual_mul_f32 v18, v11, v11 :: v_dual_add_f32 v19, v16, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, v11, v11, -v18
	v_fmac_f32_e32 v17, v11, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v18, v17
	v_fmaak_f32 v20, s21, v19, 0x3e91f4c4
	v_sub_f32_e32 v18, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v20, v19, v20, 0x3ecccdef :: v_dual_sub_f32 v17, v17, v18
	v_mul_f32_e32 v21, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, v19, v20, -v21
	v_dual_fmac_f32 v18, v17, v20 :: v_dual_mul_f32 v23, v11, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, v19, v11, -v23
	v_fmac_f32_e32 v24, v19, v16
	v_ldexp_f32 v16, v16, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, v17, v11
	v_add_f32_e32 v20, v21, v18
	v_ldexp_f32 v11, v11, 1
	v_dual_sub_f32 v21, v20, v21 :: v_dual_add_f32 v22, 0x3f2aaaaa, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v18, v18, v21 :: v_dual_add_f32 v21, 0xbf2aaaaa, v22
	v_add_f32_e32 v18, 0x31739010, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v20, v21
	v_add_f32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v22, v18
	v_dual_sub_f32 v20, v22, v17 :: v_dual_add_f32 v19, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, v18, v20
	v_sub_f32_e32 v22, v19, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v22, v24, v22 :: v_dual_mul_f32 v21, v19, v17
	v_fma_f32 v20, v19, v17, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v19, v18
	v_frexp_exp_i32_f32_e32 v18, v15
	v_fmac_f32_e32 v20, v22, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v18, vcc_lo
	v_add_f32_e32 v18, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v17
	v_add_f32_e32 v19, v11, v18
	v_sub_f32_e32 v21, v18, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v22, 0x3f317218, v17 :: v_dual_sub_f32 v11, v19, v11
	v_sub_f32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, 0x3f317218, v17, -v22
	v_dual_sub_f32 v11, v18, v11 :: v_dual_add_f32 v16, v16, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, 0xb102e308, v17
	v_dual_add_f32 v11, v16, v11 :: v_dual_add_f32 v16, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v19, v11
	v_add_f32_e32 v18, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v18, v16 :: v_dual_sub_f32 v19, v17, v19
	v_dual_sub_f32 v22, v16, v22 :: v_dual_sub_f32 v23, v18, v20
	v_sub_f32_e32 v17, v17, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v21, v22 :: v_dual_sub_f32 v16, v16, v23
	v_dual_sub_f32 v11, v11, v19 :: v_dual_add_f32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v21, v11
	v_add_f32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v18, v16
	v_dual_sub_f32 v18, v20, v18 :: v_dual_sub_f32 v17, v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v16, v18 :: v_dual_sub_f32 v19, v19, v17
	v_sub_f32_e32 v11, v11, v17
	v_sub_f32_e32 v17, v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v11, v17
	v_add_f32_e32 v11, v11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v20, v11
	v_sub_f32_e32 v17, v16, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v18, v14, v16 :: v_dual_sub_f32 v11, v11, v17
	v_fma_f32 v16, v14, v16, -v18
	v_cmp_class_f32_e64 vcc_lo, v18, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v14, v11
	v_add_f32_e32 v11, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v11, v18, vcc_lo
	v_sub_f32_e32 v11, v11, v18
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v16, v11
	v_cndmask_b32_e64 v19, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v17|
	v_sub_f32_e32 v20, v17, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_trunc_f32_e32 v17, v14
	v_mul_f32_e32 v21, 0x3fb8aa3b, v20
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v19, v11
	v_fma_f32 v22, 0x3fb8aa3b, v20, -v21
	v_rndne_f32_e32 v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v22, 0x32a5705f, v20 :: v_dual_sub_f32 v21, v21, v23
	v_cvt_i32_f32_e32 v18, v23
	v_add_f32_e32 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v21, v21
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v16, v21, v18
	v_mul_f32_e32 v18, 0.5, v14
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v21, v18
	v_cndmask_b32_e32 v16, 0x7f800000, v16, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v17, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s3, v21, v18
	v_fma_f32 v11, v16, v11, v16
	v_cmp_eq_f32_e64 s4, 0x7f800000, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	v_cndmask_b32_e64 v17, 1.0, v15, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v16, s4
	v_cmp_gt_f32_e64 s4, 0, v14
	v_cndmask_b32_e64 v16, |v14|, 0, s28
	v_bfi_b32 v11, 0x7fffffff, v11, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s5
	v_cndmask_b32_e64 v18, 0x7f800000, 0, s4
	v_cmp_eq_f32_e64 s4, |v15|, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v17, 0x7fc00000, v11, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v15
	v_cndmask_b32_e64 v16, v16, |v15|, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v11, v17, vcc_lo
	v_cndmask_b32_e64 v17, 0, v15, s3
	v_cmp_class_f32_e64 vcc_lo, v14, 0x204
	v_cmp_class_f32_e64 s3, v15, 0x204
	v_bfi_b32 v14, 0x7fffffff, v18, v17
	v_cndmask_b32_e32 v11, v11, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 vcc_lo, s5, s3
	v_cndmask_b32_e32 v11, v11, v14, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, 0x7fc00000, v11, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v14, v11, v10
.LBB0_14:                               ; %Flow90
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	s_and_saveexec_b32 s3, s26
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_6 Depth=3
	global_load_b32 v14, v[4:5], off
.LBB0_16:                               ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v11, v[7:8], off
	s_mov_b32 s3, 0
.LBB0_17:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v10, v11, v14
	global_atomic_cmpswap_b32 v10, v[7:8], v[10:11], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v10, v11
	v_mov_b32_e32 v11, v10
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v9, s15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s10, v9
	s_or_b32 s25, vcc_lo, s25
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_6
.LBB0_19:                               ; %Flow92
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_add_nc_u32_e32 v6, s14, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s9, v6
	s_or_b32 s23, vcc_lo, s23
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_4
.LBB0_20:                               ; %Flow94
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_2
.LBB0_21:                               ; %._crit_edge65
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5ratesPfS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5ratesPfS_S_iii, .Lfunc_end0-_Z5ratesPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2132
; NumSgprs: 32
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5ratesPfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z5ratesPfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
