/*******************************************************************************
 * serveral useful gpu functions will be defined in this file to calculate 
 * weno derivatives
 ******************************************************************************/

__device__ inline
double max2(double x, double y)
{
	return (x<y) ? y : x;
}

__device__ inline
double min2(double x, double y)
{
	return (x<y) ? x : y;
}

// convert subindex to linear index
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{	
	int row_idxn = min2(rows-1, max2(0, row_idx));
	int col_idxn = min2(cols-1, max2(0, col_idx));
	int pge_idxn = min2(pges-1, max2(0, pge_idx));

	int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;

	return ind;
}

__device__ inline
double weno_onesided_derivative(double v1, double v2, double v3, double v4, double v5)
{
	// different choices of ENO derivatives
	double phi1 = 1./3. * v1 	- 7./6. * v2 	+ 11./6. * v3;
	double phi2 = -1./6. * v2 	+ 5./6. * v3 	+ 1./3. * v4;
	double phi3 = 1./3. * v3	+ 5./6. * v4	- 1./6. * v5;

	// smoothness parameter
	double S1 = 13./12. * pow((v1 - 2*v2 + v3),2) + 1./4. * pow((v1 - 4*v2 + 3*v3),2);
	double S2 = 13./12. * pow((v2 - 2*v3 + v4),2) + 1./4. * pow((v2 - v4),2);
	double S3 = 13./12. * pow((v3 - 2*v4 + v5),2) + 1./4. * pow((3*v3 - 4*v4 + v5),2);

	double epsilon = 1e-6;
	double alpha1 = 0.1 / pow( (S1 + epsilon), 2);
	double alpha2 = 0.6 / pow( (S2 + epsilon), 2);
	double alpha3 = 0.3 / pow( (S3 + epsilon), 2);

	// weights for each stencil
	double sum = alpha1 + alpha2 + alpha3;
	double omega1 = alpha1 / sum;
	double omega2 = alpha2 / sum;
	double omega3 = alpha3 / sum;

	return (omega1*phi1 + omega2*phi2 + omega3*phi3);

}

__global__ 
void weno_derivative(double * WENO_back_x, double * WENO_fore_x, double * WENO_back_y, double * WENO_fore_y, double * WENO_back_z, double * WENO_fore_z, double const * lsf, int rows, int cols, int pges, double dx, double dy, double dz)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	double v1 = (lsf[left2] - lsf[left3]) / dx;
	double v2 = (lsf[left1] - lsf[left2]) / dx;
	double v3 = (lsf[ind]   - lsf[left1]) / dx;
	double v4 = (lsf[rght1] - lsf[ind])   / dx;
	double v5 = (lsf[rght2] - lsf[rght1]) / dx;
	double v6 = (lsf[rght3] - lsf[rght2]) / dx;

	WENO_back_x[ind] = weno_onesided_derivative(v1,v2,v3,v4,v5);
	WENO_fore_x[ind] = weno_onesided_derivative(v6,v5,v4,v3,v2);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	v1 = (lsf[back2] - lsf[back3]) / dy;
	v2 = (lsf[back1] - lsf[back2]) / dy;
	v3 = (lsf[ind]	 - lsf[back1]) / dy;
	v4 = (lsf[frnt1] - lsf[ind])  / dy;
	v5 = (lsf[frnt2] - lsf[frnt1]) / dy;
	v6 = (lsf[frnt3] - lsf[frnt2]) / dy;
	
	WENO_back_y[ind] = weno_onesided_derivative(v1,v2,v3,v4,v5);
	WENO_fore_y[ind] = weno_onesided_derivative(v6,v5,v4,v3,v2);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	v1 = (lsf[down2] - lsf[down3]) / dz;
	v2 = (lsf[down1] - lsf[down2]) / dz;
	v3 = (lsf[ind]	 - lsf[down1]) / dz;
	v4 = (lsf[upup1] - lsf[ind])   / dz;
	v5 = (lsf[upup2] - lsf[upup1]) / dz;
	v6 = (lsf[upup3] - lsf[upup2]) / dz;

	WENO_back_z[ind] = weno_onesided_derivative(v1,v2,v3,v4,v5);
	WENO_fore_z[ind] = weno_onesided_derivative(v6,v5,v4,v3,v2);
}	


// calculate numerical Hamiltonian for surface conservation law equation with input vx,vy,vz and
// surface divergence vd of v
__global__ 
void surface_conservation_step(double * step, double const * vx, double const * vy, double const * vz, double const * vd, double const * lsf, double dt, int rows, int cols, int pges, double dx, double dy, double dz)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	double v1 = (lsf[left2] - lsf[left3]) / dx;
	double v2 = (lsf[left1] - lsf[left2]) / dx;
	double v3 = (lsf[ind]   - lsf[left1]) / dx;
	double v4 = (lsf[rght1] - lsf[ind])   / dx;
	double v5 = (lsf[rght2] - lsf[rght1]) / dx;
	double v6 = (lsf[rght3] - lsf[rght2]) / dx;

	double xL= weno_onesided_derivative(v1,v2,v3,v4,v5);
	double xR= weno_onesided_derivative(v6,v5,v4,v3,v2);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	v1 = (lsf[back2] - lsf[back3]) / dy;
	v2 = (lsf[back1] - lsf[back2]) / dy;
	v3 = (lsf[ind]	 - lsf[back1]) / dy;
	v4 = (lsf[frnt1] - lsf[ind])  / dy;
	v5 = (lsf[frnt2] - lsf[frnt1]) / dy;
	v6 = (lsf[frnt3] - lsf[frnt2]) / dy;
	
	double yB = weno_onesided_derivative(v1,v2,v3,v4,v5);
	double yF = weno_onesided_derivative(v6,v5,v4,v3,v2);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	v1 = (lsf[down2] - lsf[down3]) / dz;
	v2 = (lsf[down1] - lsf[down2]) / dz;
	v3 = (lsf[ind]	 - lsf[down1]) / dz;
	v4 = (lsf[upup1] - lsf[ind])   / dz;
	v5 = (lsf[upup2] - lsf[upup1]) / dz;
	v6 = (lsf[upup3] - lsf[upup2]) / dz;

	double zD = weno_onesided_derivative(v1,v2,v3,v4,v5);
	double zU = weno_onesided_derivative(v6,v5,v4,v3,v2);

	step[ind] = (min2(0,vx[ind]) * xR + max2(0,vx[ind]) * xL + 
				 min2(0,vy[ind]) * yF + max2(0,vy[ind]) * yB + 
				 min2(0,vz[ind]) * zU + max2(0,vz[ind]) * zD +
				 lsf[ind] * vd[ind]) * dt ;
}	

// calculate numerical Hamiltonian for surface conservation law equation with finite volume method
// assuming c field and velocity field are already extended
__global__
void spatial_finite_volume_step(double * step, double const * vx, double const * vy, double const * vz, double const * lsf, double dt, int rows, int cols, int pges, double dx, double dy, double dz)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	double numericalFlux = 0; 
	double v_upwind, v_dnwind; // speed in the upwind and downwind direction
	int dnwind, upwind;

	// use linear approximation to calculate speed at the boundary
	dnwind 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	upwind 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);

	v_dnwind = (vx[dnwind] + vx[ind]) / 2.0;
	v_upwind = (vx[upwind] + vx[ind]) / 2.0; 

	numericalFlux += (min2(0,v_dnwind) * lsf[dnwind] - max2(0,v_dnwind) * lsf[ind]) * dy * dz;
	numericalFlux += (max2(0,v_upwind) * lsf[upwind] - min2(0,v_upwind) * lsf[ind]) * dy * dz;

	dnwind 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	upwind 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);

	v_dnwind = (vy[dnwind] + vy[ind]) / 2.0;
	v_upwind = (vy[upwind] + vy[ind]) / 2.0; 

	numericalFlux += (min2(0,v_dnwind) * lsf[dnwind] - max2(0,v_dnwind) * lsf[ind]) * dx * dz;
	numericalFlux += (max2(0,v_upwind) * lsf[upwind] - min2(0,v_upwind) * lsf[ind]) * dx * dz;

	dnwind	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	upwind 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);

	v_dnwind = (vz[dnwind] + vz[ind]) / 2.0;
	v_upwind = (vz[upwind] + vz[ind]) / 2.0; 

	numericalFlux += (min2(0,v_dnwind) * lsf[dnwind] - max2(0,v_dnwind) * lsf[ind]) * dx * dy;
	numericalFlux += (max2(0,v_upwind) * lsf[upwind] - min2(0,v_upwind) * lsf[ind]) * dx * dy;

	step[ind] = numericalFlux * dt / (dx * dy * dz); 
}






















	.file	"tmpxft_0039fc24_00000000-6_nonoscillating_interpolant.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z54__device_stub__Z15weno_derivativePdS_S_S_S_S_PKdiiidddPdS_S_S_S_S_PKdiiiddd
	.type	_Z54__device_stub__Z15weno_derivativePdS_S_S_S_S_PKdiiidddPdS_S_S_S_S_PKdiiiddd, @function
_Z54__device_stub__Z15weno_derivativePdS_S_S_S_S_PKdiiidddPdS_S_S_S_S_PKdiiiddd:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 24(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movsd	%xmm2, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z54__device_stub__Z15weno_derivativePdS_S_S_S_S_PKdiiidddPdS_S_S_S_S_PKdiiiddd, .-_Z54__device_stub__Z15weno_derivativePdS_S_S_S_S_PKdiiidddPdS_S_S_S_S_PKdiiiddd
	.globl	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.type	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd, @function
_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z15weno_derivativePdS_S_S_S_S_PKdiiidddPdS_S_S_S_S_PKdiiiddd
	.cfi_endproc
.LFE2037:
	.size	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd, .-_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.globl	_Z67__device_stub__Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiidddPdPKdS1_S1_S1_S1_diiiddd
	.type	_Z67__device_stub__Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiidddPdPKdS1_S1_S1_S1_diiiddd, @function
_Z67__device_stub__Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiidddPdPKdS1_S1_S1_S1_diiiddd:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movsd	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L8:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z67__device_stub__Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiidddPdPKdS1_S1_S1_S1_diiiddd, .-_Z67__device_stub__Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiidddPdPKdS1_S1_S1_S1_diiiddd
	.globl	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.type	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, @function
_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiidddPdPKdS1_S1_S1_S1_diiiddd
	.cfi_endproc
.LFE2039:
	.size	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, .-_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.globl	_Z65__device_stub__Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiidddPdPKdS1_S1_S1_diiiddd
	.type	_Z65__device_stub__Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiidddPdPKdS1_S1_S1_diiiddd, @function
_Z65__device_stub__Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiidddPdPKdS1_S1_S1_diiiddd:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movl	%r9d, 28(%rsp)
	movsd	%xmm0, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movsd	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L13:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z65__device_stub__Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiidddPdPKdS1_S1_S1_diiiddd, .-_Z65__device_stub__Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiidddPdPKdS1_S1_S1_diiiddd
	.globl	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.type	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, @function
_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiidddPdPKdS1_S1_S1_diiiddd
	.cfi_endproc
.LFE2041:
	.size	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, .-_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd"
.LC1:
	.string	"_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd"
.LC2:
	.string	"_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*******************************************************************************
 * serveral useful gpu functions will be defined in this file to calculate 
 * weno derivatives
 ******************************************************************************/

__device__ inline
double max2(double x, double y)
{
	return (x<y) ? y : x;
}

__device__ inline
double min2(double x, double y)
{
	return (x<y) ? x : y;
}

// convert subindex to linear index
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{	
	int row_idxn = min2(rows-1, max2(0, row_idx));
	int col_idxn = min2(cols-1, max2(0, col_idx));
	int pge_idxn = min2(pges-1, max2(0, pge_idx));

	int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;

	return ind;
}

__device__ inline
double weno_onesided_derivative(double v1, double v2, double v3, double v4, double v5)
{
	// different choices of ENO derivatives
	double phi1 = 1./3. * v1 	- 7./6. * v2 	+ 11./6. * v3;
	double phi2 = -1./6. * v2 	+ 5./6. * v3 	+ 1./3. * v4;
	double phi3 = 1./3. * v3	+ 5./6. * v4	- 1./6. * v5;

	// smoothness parameter
	double S1 = 13./12. * pow((v1 - 2*v2 + v3),2) + 1./4. * pow((v1 - 4*v2 + 3*v3),2);
	double S2 = 13./12. * pow((v2 - 2*v3 + v4),2) + 1./4. * pow((v2 - v4),2);
	double S3 = 13./12. * pow((v3 - 2*v4 + v5),2) + 1./4. * pow((3*v3 - 4*v4 + v5),2);

	double epsilon = 1e-6;
	double alpha1 = 0.1 / pow( (S1 + epsilon), 2);
	double alpha2 = 0.6 / pow( (S2 + epsilon), 2);
	double alpha3 = 0.3 / pow( (S3 + epsilon), 2);

	// weights for each stencil
	double sum = alpha1 + alpha2 + alpha3;
	double omega1 = alpha1 / sum;
	double omega2 = alpha2 / sum;
	double omega3 = alpha3 / sum;

	return (omega1*phi1 + omega2*phi2 + omega3*phi3);

}

__global__ 
void weno_derivative(double * WENO_back_x, double * WENO_fore_x, double * WENO_back_y, double * WENO_fore_y, double * WENO_back_z, double * WENO_fore_z, double const * lsf, int rows, int cols, int pges, double dx, double dy, double dz)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	double v1 = (lsf[left2] - lsf[left3]) / dx;
	double v2 = (lsf[left1] - lsf[left2]) / dx;
	double v3 = (lsf[ind]   - lsf[left1]) / dx;
	double v4 = (lsf[rght1] - lsf[ind])   / dx;
	double v5 = (lsf[rght2] - lsf[rght1]) / dx;
	double v6 = (lsf[rght3] - lsf[rght2]) / dx;

	WENO_back_x[ind] = weno_onesided_derivative(v1,v2,v3,v4,v5);
	WENO_fore_x[ind] = weno_onesided_derivative(v6,v5,v4,v3,v2);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	v1 = (lsf[back2] - lsf[back3]) / dy;
	v2 = (lsf[back1] - lsf[back2]) / dy;
	v3 = (lsf[ind]	 - lsf[back1]) / dy;
	v4 = (lsf[frnt1] - lsf[ind])  / dy;
	v5 = (lsf[frnt2] - lsf[frnt1]) / dy;
	v6 = (lsf[frnt3] - lsf[frnt2]) / dy;
	
	WENO_back_y[ind] = weno_onesided_derivative(v1,v2,v3,v4,v5);
	WENO_fore_y[ind] = weno_onesided_derivative(v6,v5,v4,v3,v2);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	v1 = (lsf[down2] - lsf[down3]) / dz;
	v2 = (lsf[down1] - lsf[down2]) / dz;
	v3 = (lsf[ind]	 - lsf[down1]) / dz;
	v4 = (lsf[upup1] - lsf[ind])   / dz;
	v5 = (lsf[upup2] - lsf[upup1]) / dz;
	v6 = (lsf[upup3] - lsf[upup2]) / dz;

	WENO_back_z[ind] = weno_onesided_derivative(v1,v2,v3,v4,v5);
	WENO_fore_z[ind] = weno_onesided_derivative(v6,v5,v4,v3,v2);
}	


// calculate numerical Hamiltonian for surface conservation law equation with input vx,vy,vz and
// surface divergence vd of v
__global__ 
void surface_conservation_step(double * step, double const * vx, double const * vy, double const * vz, double const * vd, double const * lsf, double dt, int rows, int cols, int pges, double dx, double dy, double dz)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	double v1 = (lsf[left2] - lsf[left3]) / dx;
	double v2 = (lsf[left1] - lsf[left2]) / dx;
	double v3 = (lsf[ind]   - lsf[left1]) / dx;
	double v4 = (lsf[rght1] - lsf[ind])   / dx;
	double v5 = (lsf[rght2] - lsf[rght1]) / dx;
	double v6 = (lsf[rght3] - lsf[rght2]) / dx;

	double xL= weno_onesided_derivative(v1,v2,v3,v4,v5);
	double xR= weno_onesided_derivative(v6,v5,v4,v3,v2);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	v1 = (lsf[back2] - lsf[back3]) / dy;
	v2 = (lsf[back1] - lsf[back2]) / dy;
	v3 = (lsf[ind]	 - lsf[back1]) / dy;
	v4 = (lsf[frnt1] - lsf[ind])  / dy;
	v5 = (lsf[frnt2] - lsf[frnt1]) / dy;
	v6 = (lsf[frnt3] - lsf[frnt2]) / dy;
	
	double yB = weno_onesided_derivative(v1,v2,v3,v4,v5);
	double yF = weno_onesided_derivative(v6,v5,v4,v3,v2);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	v1 = (lsf[down2] - lsf[down3]) / dz;
	v2 = (lsf[down1] - lsf[down2]) / dz;
	v3 = (lsf[ind]	 - lsf[down1]) / dz;
	v4 = (lsf[upup1] - lsf[ind])   / dz;
	v5 = (lsf[upup2] - lsf[upup1]) / dz;
	v6 = (lsf[upup3] - lsf[upup2]) / dz;

	double zD = weno_onesided_derivative(v1,v2,v3,v4,v5);
	double zU = weno_onesided_derivative(v6,v5,v4,v3,v2);

	step[ind] = (min2(0,vx[ind]) * xR + max2(0,vx[ind]) * xL + 
				 min2(0,vy[ind]) * yF + max2(0,vy[ind]) * yB + 
				 min2(0,vz[ind]) * zU + max2(0,vz[ind]) * zD +
				 lsf[ind] * vd[ind]) * dt ;
}	

// calculate numerical Hamiltonian for surface conservation law equation with finite volume method
// assuming c field and velocity field are already extended
__global__
void spatial_finite_volume_step(double * step, double const * vx, double const * vy, double const * vz, double const * lsf, double dt, int rows, int cols, int pges, double dx, double dy, double dz)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	double numericalFlux = 0; 
	double v_upwind, v_dnwind; // speed in the upwind and downwind direction
	int dnwind, upwind;

	// use linear approximation to calculate speed at the boundary
	dnwind 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	upwind 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);

	v_dnwind = (vx[dnwind] + vx[ind]) / 2.0;
	v_upwind = (vx[upwind] + vx[ind]) / 2.0; 

	numericalFlux += (min2(0,v_dnwind) * lsf[dnwind] - max2(0,v_dnwind) * lsf[ind]) * dy * dz;
	numericalFlux += (max2(0,v_upwind) * lsf[upwind] - min2(0,v_upwind) * lsf[ind]) * dy * dz;

	dnwind 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	upwind 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);

	v_dnwind = (vy[dnwind] + vy[ind]) / 2.0;
	v_upwind = (vy[upwind] + vy[ind]) / 2.0; 

	numericalFlux += (min2(0,v_dnwind) * lsf[dnwind] - max2(0,v_dnwind) * lsf[ind]) * dx * dz;
	numericalFlux += (max2(0,v_upwind) * lsf[upwind] - min2(0,v_upwind) * lsf[ind]) * dx * dz;

	dnwind	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	upwind 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);

	v_dnwind = (vz[dnwind] + vz[ind]) / 2.0;
	v_upwind = (vz[upwind] + vz[ind]) / 2.0; 

	numericalFlux += (min2(0,v_dnwind) * lsf[dnwind] - max2(0,v_dnwind) * lsf[ind]) * dx * dy;
	numericalFlux += (max2(0,v_upwind) * lsf[upwind] - min2(0,v_upwind) * lsf[ind]) * dx * dy;

	step[ind] = numericalFlux * dt / (dx * dy * dz); 
}






















	.text
	.file	"nonoscillating_interpolant.hip"
	.globl	_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd # -- Begin function _Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd
	.type	_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd,@function
_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd: # @_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	movq	%r10, 88(%rbx)
	movq	%r11, 96(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd, .Lfunc_end0-_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd # -- Begin function _Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.type	_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd,@function
_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd: # @_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	16(%rsp), %r14
	movsd	%xmm3, (%r14)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r10, 80(%rbx)
	movq	%r11, 88(%rbx)
	movq	%r14, 96(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, .Lfunc_end1-_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd # -- Begin function _Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.type	_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd,@function
_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd: # @_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	4(%rsp), %r10
	movl	%r9d, (%r10)
	leaq	40(%rsp), %r9
	movsd	%xmm1, (%r9)
	leaq	32(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	24(%rsp), %r14
	movsd	%xmm3, (%r14)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r9, 72(%rbx)
	movq	%r11, 80(%rbx)
	movq	%r14, 88(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, .Lfunc_end2-_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd,@object # @_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.section	.rodata,"a",@progbits
	.globl	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.p2align	3, 0x0
_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd:
	.quad	_Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd
	.size	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd, 8

	.type	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd,@object # @_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.globl	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.p2align	3, 0x0
_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd:
	.quad	_Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.size	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, 8

	.type	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd,@object # @_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.globl	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.p2align	3, 0x0
_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd:
	.quad	_Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.size	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd"
	.size	.L__unnamed_1, 41

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd"
	.size	.L__unnamed_2, 54

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd"
	.size	.L__unnamed_3, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__weno_derivativePdS_S_S_S_S_PKdiiiddd
	.addrsig_sym _Z40__device_stub__surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.addrsig_sym _Z41__device_stub__spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.addrsig_sym _Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.addrsig_sym _Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z24weno_onesided_derivativeddddd
	.type	_Z24weno_onesided_derivativeddddd,@function
_Z24weno_onesided_derivativeddddd:      ; @_Z24weno_onesided_derivativeddddd
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_or_saveexec_b32 s0, -1
	scratch_store_b32 off, v40, s32         ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s0
	v_writelane_b32 v40, s34, 0
	v_writelane_b32 v40, s35, 1
	v_writelane_b32 v40, s36, 2
	v_writelane_b32 v40, s37, 3
	v_writelane_b32 v40, s38, 4
	v_writelane_b32 v40, s39, 5
	v_writelane_b32 v40, s40, 6
	v_writelane_b32 v40, s41, 7
	v_writelane_b32 v40, s42, 8
	v_writelane_b32 v40, s43, 9
	v_writelane_b32 v40, s44, 10
	v_writelane_b32 v40, s45, 11
	v_writelane_b32 v40, s46, 12
	v_writelane_b32 v40, s47, 13
	v_writelane_b32 v40, s48, 14
	v_writelane_b32 v40, s49, 15
	v_writelane_b32 v40, s50, 16
	v_writelane_b32 v40, s51, 17
	v_writelane_b32 v40, s52, 18
	v_writelane_b32 v40, s53, 19
	v_writelane_b32 v40, s54, 20
	v_writelane_b32 v40, s55, 21
	v_writelane_b32 v40, s56, 22
	v_writelane_b32 v40, s57, 23
	v_writelane_b32 v40, s58, 24
	v_writelane_b32 v40, s59, 25
	v_writelane_b32 v40, s60, 26
	v_writelane_b32 v40, s61, 27
	v_writelane_b32 v40, s30, 28
	v_writelane_b32 v40, s31, 29
	s_mov_b32 s1, 0xbff2aaaa
	s_mov_b32 s0, 0xaaaaaaab
	s_mov_b32 s29, 0x3fd55555
	v_mul_f64 v[10:11], v[2:3], s[0:1]
	s_mov_b32 s28, 0x55555555
	s_mov_b32 s3, 0x3ffd5555
	s_mov_b32 s2, s28
	v_fma_f64 v[16:17], v[2:3], -2.0, v[0:1]
	s_mov_b32 s1, 0x3feaaaaa
	s_mov_b32 s54, 0x968915a9
	s_mov_b32 s56, 0x4222de17
	s_mov_b32 s55, 0x3fba6564
	s_mov_b32 s57, 0x3fbdee67
	s_mov_b32 s52, 0x3abe935a
	s_mov_b32 s38, 0xfefa39ef
	s_mov_b32 s53, 0x3fbe25e4
	s_mov_b32 s39, 0x3fe62e42
	s_mov_b32 s50, 0x47e6c9c2
	s_mov_b32 s51, 0x3fc110ef
	s_mov_b32 s48, 0xcfa74449
	s_mov_b32 s40, 0x3b39803f
	s_mov_b32 s49, 0x3fc3b13b
	s_mov_b32 s41, 0x3c7abc9e
	s_mov_b32 s46, 0x71bf3c30
	s_mov_b32 s47, 0x3fc745d1
	s_mov_b32 s44, 0x1c7792ce
	s_mov_b32 s45, 0x3fcc71c7
	s_mov_b32 s42, 0x924920da
	s_mov_b32 s43, 0x3fd24924
	s_mov_b32 s36, 0x9999999c
	s_mov_b32 s37, 0x3fd99999
	s_mov_b32 s35, 0xbfe55555
	s_mov_b32 s34, s28
	s_mov_b32 s30, 0xd5df274d
	s_mov_b32 s31, 0x3c8543b0
	s_mov_b32 s26, 0x652b82fe
	s_mov_b32 s27, 0x3ff71547
	s_mov_b32 s19, 0xbfe62e42
	s_mov_b32 s18, s38
	s_mov_b32 s21, 0xbc7abc9e
	s_mov_b32 s20, s40
	v_fma_f64 v[10:11], v[0:1], s[28:29], v[10:11]
	s_mov_b32 s22, 0xfca7ab0c
	s_mov_b32 s24, 0x6a5dcb37
	s_mov_b32 s23, 0x3e928af3
	v_add_f64 v[16:17], v[16:17], v[4:5]
	s_mov_b32 s25, 0x3e5ade15
	s_mov_b32 s16, 0x623fde64
	s_mov_b32 s17, 0x3ec71dee
	s_mov_b32 s14, 0x7c89e6b0
	s_mov_b32 s15, 0x3efa0199
	s_mov_b32 s12, 0x14761f6e
	s_mov_b32 s13, 0x3f2a01a0
	s_mov_b32 s10, 0x1852b7b0
	s_mov_b32 s11, 0x3f56c16c
	s_mov_b32 s8, 0x11122322
	s_mov_b32 s9, 0x3f811111
	s_mov_b32 s6, 0x555502a1
	s_mov_b32 s7, 0x3fa55555
	s_mov_b32 s4, 0x55555511
	s_mov_b32 s5, 0x3fc55555
	v_fma_f64 v[0:1], v[2:3], -4.0, v[0:1]
	s_mov_b32 s59, 0x3ff15555
	s_mov_b32 s58, s28
	s_mov_b32 s61, 0x3fe33333
	s_mov_b32 s60, 0x33333333
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[4:5], s[2:3], v[10:11]
	s_mov_b32 s3, 0xbfc55555
	v_mul_f64 v[12:13], v[2:3], s[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_frexp_mant_f64_e64 v[18:19], |v[16:17]|
	v_fma_f64 v[0:1], 0x40080000, v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[4:5], s[0:1], v[12:13]
	v_fma_f64 v[14:15], v[6:7], s[28:29], v[12:13]
	v_mul_f64 v[12:13], v[6:7], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[4:5], s[28:29], v[12:13]
	s_mov_b32 s29, 0x3fe55555
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[8:9], s[2:3], v[12:13]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	v_cndmask_b32_e64 v20, 0, 1, vcc_lo
	v_ldexp_f64 v[18:19], v[18:19], v20
	v_frexp_exp_i32_f64_e32 v20, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[18:19], 1.0
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v20, vcc_lo
	v_add_f64 v[20:21], v[18:19], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -1.0
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_rcp_f64_e32 v[24:25], v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	v_fma_f64 v[22:23], v[26:27], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[28:29], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[28:29], -v[18:19]
	v_cvt_f64_i32_e32 v[28:29], v32
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[28:29], s[38:39]
	v_mul_f64 v[18:19], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], s[38:39], -v[30:31]
	v_add_f64 v[20:21], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[28:29], s[40:41], v[32:33]
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[30:31], v[28:29]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_mul_f64 v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[32:33], -v[30:31]
	v_add_f64 v[26:27], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[20:21], v[20:21], -v[22:23]
	v_ldexp_f64 v[34:35], v[18:19], 1
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_ldexp_f64 v[30:31], v[20:21], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[20:21], v[26:27], v[24:25]
	v_add_f64 v[26:27], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], -v[22:23]
	v_mul_f64 v[36:37], v[20:21], v[26:27]
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	v_fma_f64 v[24:25], v[26:27], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[26:27], v[20:21], -v[36:37]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[38:39]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[22:23], v[20:21], v[18:19]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[18:19]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[20:21], -v[36:37]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[36:37]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[36:37]
	v_mul_f64 v[36:37], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[24:25], -v[36:37]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[36:37], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[24:25], s[28:29]
	v_add_f64 v[22:23], v[22:23], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[36:37], v[26:27], s[34:35]
	v_add_f64 v[24:25], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	v_add_f64 v[24:25], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	v_add_f64 v[22:23], v[22:23], v[26:27]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[20:21], v[24:25], -v[26:27]
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[20:21]
	v_add_f64 v[20:21], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[34:35], v[18:19]
	v_add_f64 v[24:25], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[32:33], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[28:29], v[18:19]
	v_add_f64 v[26:27], v[32:33], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], v[26:27]
	v_add_f64 v[26:27], v[24:25], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[24:25], v[20:21]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[22:23], v[20:21]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[24:25], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[20:21], v[20:21]
	v_fma_f64 v[20:21], v[20:21], 2.0, -v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], 2.0, v[20:21]
	v_add_f64 v[20:21], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[20:21], -v[22:23]
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_mul_f64 v[22:23], v[20:21], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[22:23], v[22:23]
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[22:23], s[18:19], v[20:21]
	v_fma_f64 v[24:25], v[22:23], s[20:21], v[24:25]
	v_cvt_i32_f64_e32 v22, v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[24:25], s[22:23]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[14:15]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[10:11]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[6:7]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[2:3]
	v_fma_f64 v[26:27], v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[24:25], v[26:27], 1.0
	v_ldexp_f64 v[22:23], v[24:25], v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v23, 0x7ff00000, v23, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e64 v21, 0, v23, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0, v22, vcc_lo
	v_cmp_neq_f64_e64 s0, 0, v[16:17]
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v18, v18, v20
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]|
	v_frexp_mant_f64_e64 v[20:21], |v[0:1]|
	v_mul_f64 v[16:17], 0x40080000, v[4:5]
	v_mul_f64 v[18:19], |v[18:19]|, s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, 0, v19, s0
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_frexp_exp_i32_f64_e32 v22, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[22:23], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[30:31]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_cvt_f64_i32_e32 v[30:31], v34
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[20:21], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[30:31], s[38:39]
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[30:31], s[40:41], v[34:35]
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[34:35], -v[32:33]
	v_add_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[36:37], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	v_ldexp_f64 v[32:33], v[22:23], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27]
	v_add_f64 v[28:29], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	v_mul_f64 v[38:39], v[22:23], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_fma_f64 v[26:27], v[28:29], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[38:39], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[24:25]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
	v_add_f64 v[28:29], v[26:27], s[28:29]
	v_add_f64 v[24:25], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[28:29], s[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[28:29], -v[26:27]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[20:21]
	v_add_f64 v[26:27], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[34:35], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[34:35], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[32:33], v[26:27], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[26:27], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], v[22:23]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	v_mul_f64 v[24:25], v[22:23], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[18:19], v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[20:21], v[26:27]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], s[24:25], s[22:23]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3]
	v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v22, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v25, s0
	v_cmp_neq_f64_e64 s0, 0, v[0:1]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
	v_ldexp_f64 v[20:21], |v[20:21]|, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0, v20, vcc_lo
	v_cndmask_b32_e64 v1, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[18:19], v[0:1]
	v_fma_f64 v[18:19], v[4:5], -2.0, v[2:3]
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	v_fma_f64 v[4:5], v[6:7], -2.0, v[4:5]
	v_add_f64 v[18:19], v[18:19], v[6:7]
	v_fma_f64 v[6:7], v[6:7], -4.0, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_frexp_mant_f64_e64 v[20:21], |v[18:19]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[8:9], |v[6:7]|
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_frexp_exp_i32_f64_e32 v22, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[22:23], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[30:31]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_cvt_f64_i32_e32 v[30:31], v34
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[20:21], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[30:31], s[38:39]
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[30:31], s[40:41], v[34:35]
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[34:35], -v[32:33]
	v_add_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[36:37], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	v_ldexp_f64 v[32:33], v[22:23], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27]
	v_add_f64 v[28:29], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	v_mul_f64 v[38:39], v[22:23], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_fma_f64 v[26:27], v[28:29], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[38:39], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[24:25]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
	v_add_f64 v[28:29], v[26:27], s[28:29]
	v_add_f64 v[24:25], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[28:29], s[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[28:29], -v[26:27]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[20:21]
	v_add_f64 v[26:27], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[34:35], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[34:35], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[32:33], v[26:27], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[26:27], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], v[22:23]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	v_mul_f64 v[24:25], v[22:23], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[18:19], v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[20:21], v[26:27]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], s[24:25], s[22:23]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3]
	v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v22, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v25, s0
	v_cmp_neq_f64_e64 s0, 0, v[18:19]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[18:19]|
	v_mul_f64 v[20:21], |v[20:21]|, s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, 0, v20, vcc_lo
	v_cndmask_b32_e64 v19, 0, v21, s0
	v_frexp_mant_f64_e64 v[20:21], |v[2:3]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21]
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_frexp_exp_i32_f64_e32 v22, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[22:23], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[30:31]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_cvt_f64_i32_e32 v[30:31], v34
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[20:21], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[30:31], s[38:39]
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[30:31], s[40:41], v[34:35]
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[34:35], -v[32:33]
	v_add_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[36:37], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	v_ldexp_f64 v[32:33], v[22:23], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27]
	v_add_f64 v[28:29], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	v_mul_f64 v[38:39], v[22:23], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_fma_f64 v[26:27], v[28:29], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[38:39], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[24:25]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
	v_add_f64 v[28:29], v[26:27], s[28:29]
	v_add_f64 v[24:25], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[28:29], s[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[28:29], -v[26:27]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[20:21]
	v_add_f64 v[26:27], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[34:35], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[34:35], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[32:33], v[26:27], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[26:27], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], v[22:23]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	v_mul_f64 v[24:25], v[22:23], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[18:19], v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[20:21], v[26:27]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], s[24:25], s[22:23]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3]
	v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v22, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v25, s0
	v_cmp_neq_f64_e64 s0, 0, v[2:3]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
	v_ldexp_f64 v[20:21], |v[20:21]|, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v20, vcc_lo
	v_cndmask_b32_e64 v3, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[18:19]
	v_frexp_mant_f64_e64 v[18:19], |v[4:5]|
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[18:19]
	v_cndmask_b32_e64 v20, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[18:19], v[18:19], v20
	v_frexp_exp_i32_f64_e32 v20, v[4:5]
	v_add_f64 v[22:23], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v20, vcc_lo
	v_add_f64 v[20:21], v[18:19], -1.0
	v_add_f64 v[24:25], v[22:23], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_rcp_f64_e32 v[24:25], v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[26:27], v[22:23], -v[28:29]
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[28:29], v[18:19]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[28:29], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	v_add_f64 v[18:19], v[28:29], -v[18:19]
	v_cvt_f64_i32_e32 v[28:29], v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[30:31], v[18:19]
	v_mul_f64 v[30:31], v[28:29], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[24:25], v[18:19]
	v_fma_f64 v[32:33], v[28:29], s[38:39], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[26:27], v[18:19]
	v_fma_f64 v[28:29], v[28:29], s[40:41], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	v_add_f64 v[32:33], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_mul_f64 v[22:23], v[20:21], v[20:21]
	v_add_f64 v[30:31], v[32:33], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[18:19], v[18:19]
	v_fma_f64 v[24:25], v[20:21], v[20:21], -v[22:23]
	v_ldexp_f64 v[34:35], v[18:19], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_ldexp_f64 v[30:31], v[20:21], 1
	v_fma_f64 v[24:25], v[20:21], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], v[24:25]
	v_add_f64 v[22:23], v[26:27], -v[22:23]
	v_mul_f64 v[36:37], v[20:21], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	v_fma_f64 v[24:25], v[26:27], s[56:57], s[54:55]
	v_fma_f64 v[38:39], v[26:27], v[20:21], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[52:53]
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[50:51]
	v_fma_f64 v[18:19], v[22:23], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[48:49]
	v_add_f64 v[20:21], v[36:37], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[46:47]
	v_add_f64 v[36:37], v[20:21], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[44:45]
	v_add_f64 v[18:19], v[18:19], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[42:43]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[36:37], v[26:27], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[26:27]
	v_add_f64 v[24:25], v[36:37], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -v[36:37]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[24:25], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], s[30:31]
	v_add_f64 v[36:37], v[26:27], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[36:37]
	v_add_f64 v[22:23], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[26:27], v[22:23]
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], v[26:27]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	v_fma_f64 v[36:37], v[20:21], v[24:25], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[36:37]
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[30:31], v[20:21]
	v_add_f64 v[18:19], v[34:35], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[32:33]
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[32:33], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], -v[28:29]
	v_add_f64 v[20:21], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_add_f64 v[24:25], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[20:21], -v[24:25]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], 2.0, -v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	v_fma_f64 v[18:19], v[18:19], 2.0, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[18:19]
	v_add_f64 v[24:25], v[20:21], -v[22:23]
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[22:23], v[20:21], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_rndne_f64_e32 v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[20:21]
	v_fma_f64 v[24:25], v[22:23], s[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[22:23], s[20:21], v[24:25]
	v_cvt_i32_f64_e32 v22, v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[16:17]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[12:13]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[8:9]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[4:5]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], 1.0
	v_fma_f64 v[24:25], v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[22:23], v[24:25], v22
	v_cndmask_b32_e32 v23, 0x7ff00000, v23, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0, v22, vcc_lo
	v_cndmask_b32_e64 v21, 0, v23, s0
	v_cmp_neq_f64_e64 s0, 0, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v18, v18, v20
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[4:5]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[18:19], |v[18:19]|, s[58:59]
	s_mov_b32 s58, 0xa0b5ed8d
	s_mov_b32 s59, 0x3eb0c6f7
	v_add_f64 v[0:1], v[0:1], s[58:59]
	v_add_f64 v[2:3], v[2:3], s[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v4, 0, v18, vcc_lo
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0, v19, s0
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	v_ldexp_f64 v[16:17], v[8:9], v16
	v_frexp_exp_i32_f64_e32 v8, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], 1.0
	v_add_f64 v[18:19], v[16:17], -1.0
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[8:9], v8
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_rcp_f64_e32 v[22:23], v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[22:23], v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[22:23], v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[24:25], v[18:19], v[22:23]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[24:25], v[20:21], -v[26:27]
	v_fma_f64 v[16:17], v[24:25], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], v[16:17]
	v_add_f64 v[28:29], v[18:19], -v[20:21]
	v_add_f64 v[26:27], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	v_add_f64 v[16:17], v[26:27], -v[16:17]
	v_mul_f64 v[26:27], v[8:9], s[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[28:29], v[16:17]
	v_fma_f64 v[28:29], v[8:9], s[38:39], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[22:23], v[16:17]
	v_fma_f64 v[8:9], v[8:9], s[40:41], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[24:25], v[16:17]
	v_add_f64 v[28:29], v[26:27], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[24:25]
	v_add_f64 v[26:27], v[28:29], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_mul_f64 v[20:21], v[18:19], v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	v_ldexp_f64 v[26:27], v[18:19], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[16:17], v[16:17]
	v_fma_f64 v[22:23], v[18:19], v[18:19], -v[20:21]
	v_ldexp_f64 v[30:31], v[16:17], 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[18:19], v[24:25], v[22:23]
	v_add_f64 v[24:25], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[24:25], -v[20:21]
	v_mul_f64 v[32:33], v[18:19], v[24:25]
	v_add_f64 v[20:21], v[22:23], -v[20:21]
	v_fma_f64 v[22:23], v[24:25], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[24:25], v[18:19], -v[32:33]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[24:25], v[16:17], v[34:35]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[32:33], v[16:17]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[18:19], -v[32:33]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[32:33]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[36:37]
	v_mul_f64 v[32:33], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[24:25], v[22:23], -v[32:33]
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[32:33], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], s[28:29]
	v_add_f64 v[20:21], v[20:21], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[24:25], s[34:35]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[22:23]
	v_add_f64 v[20:21], v[20:21], v[24:25]
	v_mul_f64 v[24:25], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[18:19], v[22:23], -v[24:25]
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[18:19]
	v_add_f64 v[18:19], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[30:31], v[16:17]
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[20:21], v[16:17]
	v_add_f64 v[20:21], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[28:29], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[8:9], v[16:17]
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], v[24:25]
	v_add_f64 v[24:25], v[22:23], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[8:9]
	v_add_f64 v[16:17], v[22:23], v[18:19]
	v_add_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[20:21]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], v[16:17]
	v_add_f64 v[16:17], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[16:17], 2.0, -v[18:19]
	v_cmp_class_f64_e64 vcc_lo, v[18:19], 0x204
	v_fma_f64 v[8:9], v[8:9], 2.0, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[18:19], v[8:9]
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_dual_cndmask_b32 v17, v17, v19 :: v_dual_cndmask_b32 v16, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[18:19], v[16:17], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[16:17]
	v_add_f64 v[8:9], v[8:9], -v[20:21]
	v_rndne_f64_e32 v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[16:17]
	v_fma_f64 v[20:21], v[18:19], s[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[18:19], s[20:21], v[20:21]
	v_cvt_i32_f64_e32 v18, v[18:19]
	v_fma_f64 v[22:23], v[20:21], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[16:17]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[12:13]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[8:9]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[4:5]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
	v_fma_f64 v[20:21], v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[18:19], v[20:21], v18
	v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, 0, v18, vcc_lo
	v_cndmask_b32_e64 v17, 0, v19, s0
	v_cmp_neq_f64_e64 s0, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[16:17], v[8:9], v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[6:7]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[8:9], |v[8:9]|, -2
	v_cndmask_b32_e32 v9, 0x7ff00000, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v6, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0, v9, s0
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_frexp_mant_f64_e32 v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], s[58:59]
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7]
	v_readlane_b32 s59, v40, 25
	v_readlane_b32 s58, v40, 24
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_frexp_exp_i32_f64_e32 v8, v[0:1]
	v_add_f64 v[16:17], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo
	v_add_f64 v[8:9], v[6:7], -1.0
	v_add_f64 v[18:19], v[16:17], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	v_mul_f64 v[22:23], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23]
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[22:23], v[6:7]
	v_add_f64 v[24:25], v[8:9], -v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	v_add_f64 v[6:7], v[22:23], -v[6:7]
	v_cvt_f64_i32_e32 v[22:23], v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[24:25], v[6:7]
	v_mul_f64 v[24:25], v[22:23], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[18:19], v[6:7]
	v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[20:21], v[6:7]
	v_fma_f64 v[22:23], v[22:23], s[40:41], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	v_add_f64 v[26:27], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_mul_f64 v[16:17], v[8:9], v[8:9]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[6:7], v[6:7]
	v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17]
	v_ldexp_f64 v[28:29], v[6:7], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[24:25], v[8:9], 1
	v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[16:17], v[18:19]
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_mul_f64 v[30:31], v[8:9], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[20:21], s[56:57], s[54:55]
	v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53]
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51]
	v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[48:49]
	v_add_f64 v[8:9], v[30:31], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47]
	v_add_f64 v[30:31], v[8:9], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45]
	v_add_f64 v[6:7], v[6:7], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[42:43]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[20:21], v[18:19]
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[30:31], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[30:31]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[18:19], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], s[30:31]
	v_add_f64 v[30:31], v[20:21], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[20:21], v[16:17]
	v_add_f64 v[20:21], v[20:21], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31]
	v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[20:21], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[8:9]
	v_add_f64 v[6:7], v[28:29], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -v[24:25]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[8:9], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[26:27], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -v[26:27]
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	v_add_f64 v[8:9], v[8:9], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	v_add_f64 v[8:9], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[18:19], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[8:9], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[18:19]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[6:7]
	v_add_f64 v[18:19], v[8:9], -v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[16:17], v[8:9], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rndne_f64_e32 v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	v_fma_f64 v[18:19], v[16:17], s[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[16:17], s[20:21], v[18:19]
	v_cvt_i32_f64_e32 v16, v[16:17]
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[16:17]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[16:17], v[18:19], v16
	v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	v_cndmask_b32_e64 v9, 0, v17, s0
	s_mov_b32 s0, 0x9999999a
	s_mov_b32 s1, 0x3fb99999
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7
	v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[0:1]
	v_div_scale_f64 v[8:9], vcc_lo, s[0:1], v[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
	v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[0:1]
	v_cmp_neq_f64_e64 s0, 0, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0, v6, vcc_lo
	v_cndmask_b32_e64 v1, 0x7ff00000, v7, s0
	v_frexp_mant_f64_e32 v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_frexp_exp_i32_f64_e32 v8, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[6:7], 1.0
	v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo
	v_add_f64 v[8:9], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -1.0
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[16:17], v[20:21]
	v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17]
	v_add_f64 v[16:17], v[22:23], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[8:9], -v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[22:23], -v[6:7]
	v_cvt_f64_i32_e32 v[22:23], v26
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[6:7], v[24:25], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[22:23], s[38:39]
	v_mul_f64 v[6:7], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25]
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[22:23], s[40:41], v[26:27]
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_mul_f64 v[16:17], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17]
	v_ldexp_f64 v[28:29], v[6:7], 1
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[24:25], v[8:9], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19]
	v_add_f64 v[20:21], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_mul_f64 v[30:31], v[8:9], v[20:21]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[20:21], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[30:31], v[6:7]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[8:9], -v[30:31]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[30:31]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37]
	v_mul_f64 v[30:31], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31]
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[30:31], v[16:17]
	v_add_f64 v[20:21], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[18:19], s[28:29]
	v_add_f64 v[16:17], v[16:17], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[30:31], v[20:21], s[34:35]
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[18:19]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21]
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9]
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[28:29], v[6:7]
	v_add_f64 v[18:19], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[26:27], v[8:9]
	v_add_f64 v[18:19], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[18:19], v[8:9]
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[16:17], v[8:9]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[18:19], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[8:9], v[8:9]
	v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
	v_add_f64 v[8:9], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[8:9], -v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_mul_f64 v[16:17], v[8:9], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[16:17], v[16:17]
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], s[18:19], v[8:9]
	v_fma_f64 v[18:19], v[16:17], s[20:21], v[18:19]
	v_cvt_i32_f64_e32 v16, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[22:23]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
	v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
	v_ldexp_f64 v[16:17], v[18:19], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0, v17, s0
	v_cmp_neq_f64_e64 s0, 0, v[2:3]
	v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[60:61]
	v_div_scale_f64 v[8:9], vcc_lo, s[60:61], v[8:9], s[60:61]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9]
	v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[60:61]
	s_mov_b32 s61, 0x3fd33333
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v6, vcc_lo
	v_cndmask_b32_e64 v3, 0x7ff00000, v7, s0
	v_frexp_mant_f64_e32 v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_frexp_exp_i32_f64_e32 v8, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[6:7], 1.0
	v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo
	v_add_f64 v[8:9], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -1.0
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[16:17], v[20:21]
	v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17]
	v_add_f64 v[16:17], v[22:23], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[8:9], -v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[22:23], -v[6:7]
	v_cvt_f64_i32_e32 v[22:23], v26
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[6:7], v[24:25], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[22:23], s[38:39]
	v_mul_f64 v[6:7], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25]
	v_readlane_b32 s39, v40, 5
	v_readlane_b32 s38, v40, 4
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[22:23], s[40:41], v[26:27]
	v_readlane_b32 s41, v40, 7
	v_readlane_b32 s40, v40, 6
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_mul_f64 v[16:17], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17]
	v_ldexp_f64 v[28:29], v[6:7], 1
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[24:25], v[8:9], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19]
	v_add_f64 v[20:21], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_mul_f64 v[30:31], v[8:9], v[20:21]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[20:21], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31]
	v_readlane_b32 s57, v40, 23
	v_readlane_b32 s56, v40, 22
	v_readlane_b32 s55, v40, 21
	v_readlane_b32 s54, v40, 20
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53]
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33]
	v_readlane_b32 s53, v40, 19
	v_readlane_b32 s52, v40, 18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51]
	v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7]
	v_readlane_b32 s51, v40, 17
	v_readlane_b32 s50, v40, 16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[48:49]
	v_add_f64 v[8:9], v[30:31], v[6:7]
	v_readlane_b32 s49, v40, 15
	v_readlane_b32 s48, v40, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47]
	v_add_f64 v[30:31], v[8:9], -v[30:31]
	v_readlane_b32 s47, v40, 13
	v_readlane_b32 s46, v40, 12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45]
	v_add_f64 v[6:7], v[6:7], -v[30:31]
	v_readlane_b32 s45, v40, 11
	v_readlane_b32 s44, v40, 10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[42:43]
	v_readlane_b32 s43, v40, 9
	v_readlane_b32 s42, v40, 8
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37]
	v_readlane_b32 s37, v40, 3
	v_readlane_b32 s36, v40, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[20:21], v[18:19]
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[30:31], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[30:31]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[18:19], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], s[30:31]
	v_add_f64 v[30:31], v[20:21], s[34:35]
	v_readlane_b32 s30, v40, 28
	v_readlane_b32 s31, v40, 29
	v_readlane_b32 s35, v40, 1
	v_readlane_b32 s34, v40, 0
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[18:19]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21]
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9]
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[28:29], v[6:7]
	v_add_f64 v[18:19], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[26:27], v[8:9]
	v_add_f64 v[18:19], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[18:19], v[8:9]
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[16:17], v[8:9]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[18:19], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[8:9], v[8:9]
	v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
	v_add_f64 v[8:9], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[8:9], -v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_mul_f64 v[16:17], v[8:9], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[16:17], v[16:17]
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], s[18:19], v[8:9]
	v_fma_f64 v[18:19], v[16:17], s[20:21], v[18:19]
	v_cvt_i32_f64_e32 v16, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[22:23]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
	v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
	v_ldexp_f64 v[16:17], v[18:19], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0, v17, s0
	v_cmp_neq_f64_e64 s0, 0, v[4:5]
	v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[60:61]
	v_div_scale_f64 v[8:9], vcc_lo, s[60:61], v[8:9], s[60:61]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9]
	v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[60:61]
	v_readlane_b32 s61, v40, 27
	v_readlane_b32 s60, v40, 26
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v6, vcc_lo
	v_cndmask_b32_e64 v5, 0x7ff00000, v7, s0
	v_add_f64 v[6:7], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[4:5]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_div_scale_f64 v[18:19], vcc_lo, v[0:1], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
	v_div_fixup_f64 v[0:1], v[8:9], v[6:7], v[0:1]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_div_scale_f64 v[18:19], vcc_lo, v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
	v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[14:15], v[2:3]
	v_rcp_f64_e32 v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[10:11], v[0:1], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_div_scale_f64 v[18:19], vcc_lo, v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
	v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[12:13], v[4:5], v[0:1]
	s_or_saveexec_b32 s0, -1
	scratch_load_b32 v40, off, s32          ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s0
	s_waitcnt vmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z24weno_onesided_derivativeddddd, .Lfunc_end0-_Z24weno_onesided_derivativeddddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 15076
; NumSgprs: 64
; NumVgprs: 50
; ScratchSize: 8
; MemoryBound: 0
	.text
	.protected	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd ; -- Begin function _Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.globl	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
	.p2align	8
	.type	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd,@function
_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd: ; @_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x6c
	s_load_b128 s[80:83], s[0:1], 0x38
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[63:64], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[56:57], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s80, v63
	v_cmp_gt_i32_e64 s2, s81, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s82, v56
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], v56
	s_add_i32 s2, s82, -1
	v_cvt_f64_i32_e32 v[5:6], v0
	v_add_nc_u32_e32 v9, 2, v0
	v_add_nc_u32_e32 v11, 3, v0
	v_add_nc_u32_e32 v13, -1, v0
	v_add_nc_u32_e32 v15, -2, v0
	v_cvt_f64_i32_e32 v[57:58], s2
	v_add_nc_u32_e32 v7, 1, v0
	v_add_nc_u32_e32 v0, -3, v0
	v_cvt_f64_i32_e32 v[9:10], v9
	v_cvt_f64_i32_e32 v[13:14], v13
	v_cvt_f64_i32_e32 v[15:16], v15
	v_cvt_f64_i32_e32 v[3:4], v63
	v_cvt_f64_i32_e32 v[17:18], v0
	v_cvt_f64_i32_e32 v[11:12], v11
	s_add_i32 s3, s81, -1
	s_add_i32 s2, s80, -1
	v_cvt_f64_i32_e32 v[19:20], s3
	v_cvt_f64_i32_e32 v[64:65], s2
	s_clause 0x1
	s_load_b256 s[64:71], s[0:1], 0x20
	s_load_b128 s[84:87], s[0:1], 0x48
	s_getpc_b64 s[62:63]
	s_add_u32 s62, s62, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s63, s63, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_max_f64 v[0:1], v[1:2], 0
	v_max_f64 v[5:6], v[5:6], 0
	v_max_f64 v[9:10], v[9:10], 0
	v_max_f64 v[13:14], v[13:14], 0
	v_max_f64 v[15:16], v[15:16], 0
	v_max_f64 v[2:3], v[3:4], 0
	v_max_f64 v[17:18], v[17:18], 0
	v_max_f64 v[11:12], v[11:12], 0
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[57:58]
	v_cmp_gt_f64_e64 s2, v[5:6], v[19:20]
	v_cmp_gt_f64_e64 s5, v[9:10], v[19:20]
	v_cmp_gt_f64_e64 s7, v[13:14], v[19:20]
	v_cmp_gt_f64_e64 s8, v[15:16], v[19:20]
	v_cmp_gt_f64_e64 s3, v[2:3], v[64:65]
	v_cmp_gt_f64_e64 s9, v[17:18], v[19:20]
	v_cmp_gt_f64_e64 s6, v[11:12], v[19:20]
	v_dual_cndmask_b32 v1, v1, v58 :: v_dual_cndmask_b32 v0, v0, v57
	v_cvt_f64_i32_e32 v[7:8], v7
	v_cndmask_b32_e64 v6, v6, v20, s2
	v_cndmask_b32_e64 v5, v5, v19, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_cvt_i32_f64_e32 v59, v[5:6]
	v_cndmask_b32_e64 v10, v10, v20, s5
	v_cndmask_b32_e64 v14, v14, v20, s7
	v_cndmask_b32_e64 v16, v16, v20, s8
	v_cndmask_b32_e64 v9, v9, v19, s5
	v_cndmask_b32_e64 v13, v13, v19, s7
	v_cndmask_b32_e64 v15, v15, v19, s8
	v_cndmask_b32_e64 v18, v18, v20, s9
	v_cndmask_b32_e64 v17, v17, v19, s9
	v_cndmask_b32_e64 v3, v3, v65, s3
	v_cndmask_b32_e64 v12, v12, v20, s6
	v_cndmask_b32_e64 v2, v2, v64, s3
	v_cndmask_b32_e64 v11, v11, v19, s6
	v_cvt_i32_f64_e32 v4, v[9:10]
	v_cvt_i32_f64_e32 v6, v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v60, v[2:3]
	v_cvt_i32_f64_e32 v5, v[11:12]
	v_max_f64 v[7:8], v[7:8], 0
	v_mul_lo_u32 v0, v0, s81
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v0, v59
	v_mul_lo_u32 v47, v2, s80
	v_add_nc_u32_e32 v10, v0, v4
	v_add_nc_u32_e32 v4, v0, v6
	v_add_nc_u32_e32 v12, v0, v5
	v_cmp_gt_f64_e64 s4, v[7:8], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v20, s4
	v_cndmask_b32_e64 v7, v7, v19, s4
	v_cvt_i32_f64_e32 v1, v[7:8]
	v_cvt_i32_f64_e32 v7, v[15:16]
	v_cvt_i32_f64_e32 v8, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v0, v1
	v_add_nc_u32_e32 v6, v0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v0, v8
	v_mad_u64_u32 v[0:1], null, v3, s80, v[60:61]
	v_mad_u64_u32 v[2:3], null, v4, s80, v[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[4:5], null, v6, s80, v[60:61]
	v_mad_u64_u32 v[6:7], null, v8, s80, v[60:61]
	v_mad_u64_u32 v[8:9], null, v10, s80, v[60:61]
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_mad_u64_u32 v[10:11], null, v12, s80, v[60:61]
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v12, v47, v60
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v11, 31, v10
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s68, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s68, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo
	v_lshlrev_b64 v[54:55], 3, v[12:13]
	v_add_co_u32 v2, vcc_lo, s68, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s69, v3, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v0, vcc_lo, s68, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo
	v_add_co_u32 v61, vcc_lo, s68, v54
	v_add_co_ci_u32_e32 v62, vcc_lo, s69, v55, vcc_lo
	s_clause 0x2
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_u32 v8, vcc_lo, s68, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo
	s_clause 0x2
	global_load_b64 v[12:13], v[61:62], off
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[8:9], v[8:9], off
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s68, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_clause 0x1
	s_load_b64 s[70:71], s[0:1], 0x58
	s_load_b256 s[72:79], s[0:1], 0x0
	s_waitcnt vmcnt(5)
	v_add_f64 v[6:7], v[4:5], -v[6:7]
	s_waitcnt vmcnt(4)
	v_add_f64 v[4:5], v[2:3], -v[4:5]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[12:13], -v[2:3]
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[0:1], -v[12:13]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[8:9], -v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_div_scale_f64 v[0:1], null, s[84:85], s[84:85], v[6:7]
	v_div_scale_f64 v[10:11], null, s[84:85], s[84:85], v[4:5]
	v_div_scale_f64 v[50:51], vcc_lo, v[6:7], s[84:85], v[6:7]
	v_div_scale_f64 v[16:17], null, s[84:85], s[84:85], v[2:3]
	v_div_scale_f64 v[18:19], null, s[84:85], s[84:85], v[12:13]
	v_div_scale_f64 v[20:21], null, s[84:85], s[84:85], v[14:15]
	v_div_scale_f64 v[22:23], null, s[84:85], s[84:85], v[8:9]
	v_rcp_f64_e32 v[24:25], v[0:1]
	v_rcp_f64_e32 v[26:27], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[28:29], v[16:17]
	v_rcp_f64_e32 v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[32:33], v[20:21]
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s2, v[4:5], s[84:85], v[4:5]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s3, v[2:3], s[84:85], v[2:3]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s4, v[12:13], s[84:85], v[12:13]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s5, v[14:15], s[84:85], v[14:15]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_div_scale_f64 v[44:45], s6, v[8:9], s[84:85], v[8:9]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_mul_f64 v[48:49], v[50:51], v[24:25]
	v_mul_f64 v[52:53], v[36:37], v[26:27]
	v_mul_f64 v[66:67], v[38:39], v[28:29]
	v_mul_f64 v[68:69], v[40:41], v[30:31]
	v_mul_f64 v[70:71], v[42:43], v[32:33]
	v_mul_f64 v[72:73], v[44:45], v[34:35]
	v_fma_f64 v[0:1], -v[0:1], v[48:49], v[50:51]
	v_fma_f64 v[10:11], -v[10:11], v[52:53], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[66:67], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[68:69], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[70:71], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[72:73], v[44:45]
	v_div_fmas_f64 v[0:1], v[0:1], v[24:25], v[48:49]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[10:11], v[10:11], v[26:27], v[52:53]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[66:67]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[68:69]
	s_mov_b32 vcc_lo, s5
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[70:71]
	s_mov_b32 vcc_lo, s6
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[72:73]
	v_div_fixup_f64 v[0:1], v[0:1], s[84:85], v[6:7]
	v_div_fixup_f64 v[41:42], v[10:11], s[84:85], v[4:5]
	v_div_fixup_f64 v[43:44], v[16:17], s[84:85], v[2:3]
	v_div_fixup_f64 v[45:46], v[18:19], s[84:85], v[12:13]
	v_div_fixup_f64 v[50:51], v[20:21], s[84:85], v[14:15]
	v_div_fixup_f64 v[52:53], v[22:23], s[84:85], v[8:9]
	v_dual_mov_b32 v2, v41 :: v_dual_mov_b32 v3, v42
	v_dual_mov_b32 v5, v44 :: v_dual_mov_b32 v4, v43
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v50 :: v_dual_mov_b32 v9, v51
	s_swappc_b64 s[30:31], s[62:63]
	v_add_co_u32 v2, vcc_lo, s72, v54
	v_add_co_ci_u32_e32 v3, vcc_lo, s73, v55, vcc_lo
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v43 :: v_dual_mov_b32 v7, v44
	global_store_b64 v[2:3], v[0:1], off
	v_dual_mov_b32 v0, v52 :: v_dual_mov_b32 v1, v53
	v_dual_mov_b32 v2, v50 :: v_dual_mov_b32 v3, v51
	v_dual_mov_b32 v8, v41 :: v_dual_mov_b32 v9, v42
	s_swappc_b64 s[30:31], s[62:63]
	v_add_nc_u32_e32 v6, -2, v63
	v_add_nc_u32_e32 v8, -3, v63
	v_add_nc_u32_e32 v10, -1, v63
	v_add_nc_u32_e32 v4, 2, v63
	v_add_nc_u32_e32 v2, 1, v63
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[8:9], v8
	v_cvt_f64_i32_e32 v[10:11], v10
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[2:3], v2
	v_add_nc_u32_e32 v12, 3, v63
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[12:13], v12
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[12:13], v[12:13], 0
	v_cmp_gt_f64_e64 s1, v[6:7], v[64:65]
	v_cmp_gt_f64_e64 s2, v[8:9], v[64:65]
	v_cmp_gt_f64_e64 s3, v[10:11], v[64:65]
	v_cmp_gt_f64_e64 s0, v[4:5], v[64:65]
	v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[64:65]
	v_cmp_gt_f64_e64 s4, v[12:13], v[64:65]
	v_cndmask_b32_e64 v7, v7, v65, s1
	v_cndmask_b32_e64 v6, v6, v64, s1
	v_cndmask_b32_e64 v9, v9, v65, s2
	v_cndmask_b32_e64 v8, v8, v64, s2
	v_cndmask_b32_e32 v3, v3, v65, vcc_lo
	v_cndmask_b32_e64 v11, v11, v65, s3
	v_cvt_i32_f64_e32 v6, v[6:7]
	v_cndmask_b32_e64 v10, v10, v64, s3
	v_cndmask_b32_e64 v5, v5, v65, s0
	v_cndmask_b32_e64 v4, v4, v64, s0
	v_cvt_i32_f64_e32 v7, v[8:9]
	v_cndmask_b32_e32 v2, v2, v64, vcc_lo
	v_cvt_i32_f64_e32 v8, v[10:11]
	v_cndmask_b32_e64 v13, v13, v65, s4
	v_cvt_i32_f64_e32 v5, v[4:5]
	v_cndmask_b32_e64 v12, v12, v64, s4
	v_cvt_i32_f64_e32 v14, v[2:3]
	v_add_co_u32 v2, vcc_lo, s74, v54
	v_add_co_ci_u32_e32 v3, vcc_lo, s75, v55, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v9, v[12:13]
	global_store_b64 v[2:3], v[0:1], off
	v_add_nc_u32_e32 v2, v47, v6
	v_add_nc_u32_e32 v4, v47, v7
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v6, v47, v8
	v_add_nc_u32_e32 v8, v47, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v0, v47, v14
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v10, v47, v9
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v2, vcc_lo, s68, v2
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s69, v3, vcc_lo
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v4, vcc_lo, s68, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v6, vcc_lo, s68, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo
	v_add_co_u32 v0, vcc_lo, s68, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo
	s_clause 0x2
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s68, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo
	s_clause 0x2
	global_load_b64 v[12:13], v[61:62], off
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[8:9], v[8:9], off
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v10, vcc_lo, s68, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(5)
	v_add_f64 v[4:5], v[2:3], -v[4:5]
	s_waitcnt vmcnt(4)
	v_add_f64 v[2:3], v[6:7], -v[2:3]
	s_waitcnt vmcnt(3)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[0:1], -v[12:13]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[8:9], -v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_div_scale_f64 v[0:1], null, s[86:87], s[86:87], v[4:5]
	v_div_scale_f64 v[10:11], null, s[86:87], s[86:87], v[2:3]
	v_div_scale_f64 v[48:49], vcc_lo, v[4:5], s[86:87], v[4:5]
	v_div_scale_f64 v[16:17], null, s[86:87], s[86:87], v[6:7]
	v_div_scale_f64 v[18:19], null, s[86:87], s[86:87], v[12:13]
	v_div_scale_f64 v[20:21], null, s[86:87], s[86:87], v[14:15]
	v_div_scale_f64 v[22:23], null, s[86:87], s[86:87], v[8:9]
	v_rcp_f64_e32 v[24:25], v[0:1]
	v_rcp_f64_e32 v[26:27], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[28:29], v[16:17]
	v_rcp_f64_e32 v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[32:33], v[20:21]
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[86:87], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[6:7], s[86:87], v[6:7]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s2, v[12:13], s[86:87], v[12:13]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s3, v[14:15], s[86:87], v[14:15]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_div_scale_f64 v[44:45], s4, v[8:9], s[86:87], v[8:9]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_mul_f64 v[46:47], v[48:49], v[24:25]
	v_mul_f64 v[50:51], v[36:37], v[26:27]
	v_mul_f64 v[52:53], v[38:39], v[28:29]
	v_mul_f64 v[63:64], v[40:41], v[30:31]
	v_mul_f64 v[65:66], v[42:43], v[32:33]
	v_mul_f64 v[67:68], v[44:45], v[34:35]
	v_fma_f64 v[0:1], -v[0:1], v[46:47], v[48:49]
	v_fma_f64 v[10:11], -v[10:11], v[50:51], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[52:53], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[63:64], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[65:66], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[67:68], v[44:45]
	v_div_fmas_f64 v[0:1], v[0:1], v[24:25], v[46:47]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[26:27], v[50:51]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[52:53]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[63:64]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[65:66]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[67:68]
	v_div_fixup_f64 v[0:1], v[0:1], s[86:87], v[4:5]
	v_div_fixup_f64 v[41:42], v[10:11], s[86:87], v[2:3]
	v_div_fixup_f64 v[43:44], v[16:17], s[86:87], v[6:7]
	v_div_fixup_f64 v[45:46], v[18:19], s[86:87], v[12:13]
	v_div_fixup_f64 v[50:51], v[20:21], s[86:87], v[14:15]
	v_div_fixup_f64 v[52:53], v[22:23], s[86:87], v[8:9]
	v_dual_mov_b32 v2, v41 :: v_dual_mov_b32 v3, v42
	v_dual_mov_b32 v4, v43 :: v_dual_mov_b32 v5, v44
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v50 :: v_dual_mov_b32 v9, v51
	s_swappc_b64 s[30:31], s[62:63]
	v_add_co_u32 v2, vcc_lo, s76, v54
	v_add_co_ci_u32_e32 v3, vcc_lo, s77, v55, vcc_lo
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v43 :: v_dual_mov_b32 v7, v44
	global_store_b64 v[2:3], v[0:1], off
	v_dual_mov_b32 v0, v52 :: v_dual_mov_b32 v1, v53
	v_dual_mov_b32 v2, v50 :: v_dual_mov_b32 v3, v51
	v_dual_mov_b32 v8, v41 :: v_dual_mov_b32 v9, v42
	s_swappc_b64 s[30:31], s[62:63]
	v_add_nc_u32_e32 v2, 1, v56
	v_add_nc_u32_e32 v4, 2, v56
	v_add_nc_u32_e32 v6, 3, v56
	v_add_nc_u32_e32 v8, -1, v56
	v_add_nc_u32_e32 v10, -2, v56
	v_cvt_f64_i32_e32 v[2:3], v2
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[6:7], v6
	v_add_nc_u32_e32 v12, -3, v56
	v_cvt_f64_i32_e32 v[8:9], v8
	v_cvt_f64_i32_e32 v[10:11], v10
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[12:13], v12
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_max_f64 v[12:13], v[12:13], 0
	v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[57:58]
	v_cmp_gt_f64_e64 s0, v[4:5], v[57:58]
	v_cmp_gt_f64_e64 s1, v[6:7], v[57:58]
	v_cmp_gt_f64_e64 s2, v[8:9], v[57:58]
	v_cmp_gt_f64_e64 s3, v[10:11], v[57:58]
	v_cmp_gt_f64_e64 s4, v[12:13], v[57:58]
	v_dual_cndmask_b32 v3, v3, v58 :: v_dual_cndmask_b32 v2, v2, v57
	v_cndmask_b32_e64 v5, v5, v58, s0
	v_cndmask_b32_e64 v4, v4, v57, s0
	v_cndmask_b32_e64 v7, v7, v58, s1
	v_cndmask_b32_e64 v6, v6, v57, s1
	v_cndmask_b32_e64 v9, v9, v58, s2
	v_cndmask_b32_e64 v8, v8, v57, s2
	v_cndmask_b32_e64 v11, v11, v58, s3
	v_cndmask_b32_e64 v10, v10, v57, s3
	v_cvt_i32_f64_e32 v14, v[2:3]
	v_cvt_i32_f64_e32 v15, v[4:5]
	v_cndmask_b32_e64 v13, v13, v58, s4
	v_cvt_i32_f64_e32 v16, v[6:7]
	v_cndmask_b32_e64 v12, v12, v57, s4
	v_cvt_i32_f64_e32 v9, v[8:9]
	v_cvt_i32_f64_e32 v10, v[10:11]
	v_add_co_u32 v2, vcc_lo, s78, v54
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f64_e32 v11, v[12:13]
	v_add_co_ci_u32_e32 v3, vcc_lo, s79, v55, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	v_mad_u64_u32 v[4:5], null, v14, s81, v[59:60]
	v_mad_u64_u32 v[5:6], null, v15, s81, v[59:60]
	v_mad_u64_u32 v[6:7], null, v16, s81, v[59:60]
	v_mad_u64_u32 v[7:8], null, v9, s81, v[59:60]
	v_mad_u64_u32 v[8:9], null, v10, s81, v[59:60]
	v_mad_u64_u32 v[9:10], null, v11, s81, v[59:60]
	v_mad_u64_u32 v[10:11], null, v4, s80, v[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[12:13], null, v7, s80, v[60:61]
	v_mad_u64_u32 v[14:15], null, v8, s80, v[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[7:8], null, v9, s80, v[60:61]
	v_mad_u64_u32 v[16:17], null, v5, s80, v[60:61]
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v15, 31, v14
	v_mad_u64_u32 v[4:5], null, v6, s80, v[60:61]
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[14:15]
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_lshlrev_b64 v[6:7], 3, v[12:13]
	v_lshlrev_b64 v[8:9], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s68, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s68, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s69, v3, vcc_lo
	v_lshlrev_b64 v[10:11], 3, v[16:17]
	v_add_co_u32 v6, vcc_lo, s68, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s68, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo
	s_clause 0x2
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v10, vcc_lo, s68, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo
	s_clause 0x2
	global_load_b64 v[12:13], v[61:62], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s68, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(5)
	v_add_f64 v[2:3], v[0:1], -v[2:3]
	s_waitcnt vmcnt(4)
	v_add_f64 v[14:15], v[6:7], -v[0:1]
	s_waitcnt vmcnt(3)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[8:9], -v[12:13]
	s_waitcnt vmcnt(1)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_div_scale_f64 v[0:1], null, s[70:71], s[70:71], v[2:3]
	v_div_scale_f64 v[10:11], null, s[70:71], s[70:71], v[14:15]
	v_div_scale_f64 v[48:49], vcc_lo, v[2:3], s[70:71], v[2:3]
	v_div_scale_f64 v[16:17], null, s[70:71], s[70:71], v[6:7]
	v_div_scale_f64 v[18:19], null, s[70:71], s[70:71], v[12:13]
	v_div_scale_f64 v[20:21], null, s[70:71], s[70:71], v[8:9]
	v_div_scale_f64 v[22:23], null, s[70:71], s[70:71], v[4:5]
	v_rcp_f64_e32 v[24:25], v[0:1]
	v_rcp_f64_e32 v[26:27], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[28:29], v[16:17]
	v_rcp_f64_e32 v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[32:33], v[20:21]
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[14:15], s[70:71], v[14:15]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[6:7], s[70:71], v[6:7]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s2, v[12:13], s[70:71], v[12:13]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s3, v[8:9], s[70:71], v[8:9]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_div_scale_f64 v[44:45], s4, v[4:5], s[70:71], v[4:5]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_mul_f64 v[46:47], v[48:49], v[24:25]
	v_mul_f64 v[50:51], v[36:37], v[26:27]
	v_mul_f64 v[52:53], v[38:39], v[28:29]
	v_mul_f64 v[56:57], v[40:41], v[30:31]
	v_mul_f64 v[58:59], v[42:43], v[32:33]
	v_mul_f64 v[60:61], v[44:45], v[34:35]
	v_fma_f64 v[0:1], -v[0:1], v[46:47], v[48:49]
	v_fma_f64 v[10:11], -v[10:11], v[50:51], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[52:53], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[56:57], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[58:59], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[60:61], v[44:45]
	v_div_fmas_f64 v[0:1], v[0:1], v[24:25], v[46:47]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[26:27], v[50:51]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[52:53]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[56:57]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[58:59]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[60:61]
	v_div_fixup_f64 v[0:1], v[0:1], s[70:71], v[2:3]
	v_div_fixup_f64 v[41:42], v[10:11], s[70:71], v[14:15]
	v_div_fixup_f64 v[43:44], v[16:17], s[70:71], v[6:7]
	v_div_fixup_f64 v[45:46], v[18:19], s[70:71], v[12:13]
	v_div_fixup_f64 v[50:51], v[20:21], s[70:71], v[8:9]
	v_div_fixup_f64 v[52:53], v[22:23], s[70:71], v[4:5]
	v_dual_mov_b32 v2, v41 :: v_dual_mov_b32 v3, v42
	v_dual_mov_b32 v4, v43 :: v_dual_mov_b32 v5, v44
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v9, v51 :: v_dual_mov_b32 v8, v50
	s_swappc_b64 s[30:31], s[62:63]
	v_add_co_u32 v2, vcc_lo, s64, v54
	v_add_co_ci_u32_e32 v3, vcc_lo, s65, v55, vcc_lo
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v43 :: v_dual_mov_b32 v7, v44
	global_store_b64 v[2:3], v[0:1], off
	v_dual_mov_b32 v0, v52 :: v_dual_mov_b32 v1, v53
	v_dual_mov_b32 v2, v50 :: v_dual_mov_b32 v3, v51
	v_dual_mov_b32 v8, v41 :: v_dual_mov_b32 v9, v42
	s_swappc_b64 s[30:31], s[62:63]
	v_add_co_u32 v2, vcc_lo, s66, v54
	v_add_co_ci_u32_e32 v3, vcc_lo, s67, v55, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 74
		.amdhsa_next_free_sgpr 88
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd, .Lfunc_end1-_Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4268
; NumSgprs: 90
; NumVgprs: 74
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 90
; NumVGPRsForWavesPerEU: 74
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd ; -- Begin function _Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.globl	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
	.p2align	8
	.type	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd,@function
_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd: ; @_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x6c
	s_load_b128 s[80:83], s[0:1], 0x38
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[56:57], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[60:61], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s80, v56
	v_cmp_gt_i32_e64 s2, s81, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s82, v60
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], v60
	s_add_i32 s2, s82, -1
	v_cvt_f64_i32_e32 v[5:6], v0
	v_add_nc_u32_e32 v9, 2, v0
	v_add_nc_u32_e32 v11, 3, v0
	v_add_nc_u32_e32 v13, -1, v0
	v_add_nc_u32_e32 v15, -2, v0
	v_cvt_f64_i32_e32 v[61:62], s2
	v_add_nc_u32_e32 v7, 1, v0
	v_add_nc_u32_e32 v0, -3, v0
	v_cvt_f64_i32_e32 v[9:10], v9
	v_cvt_f64_i32_e32 v[13:14], v13
	v_cvt_f64_i32_e32 v[15:16], v15
	v_cvt_f64_i32_e32 v[3:4], v56
	v_cvt_f64_i32_e32 v[17:18], v0
	v_cvt_f64_i32_e32 v[11:12], v11
	s_add_i32 s3, s81, -1
	s_add_i32 s2, s80, -1
	v_cvt_f64_i32_e32 v[19:20], s3
	v_cvt_f64_i32_e32 v[57:58], s2
	s_clause 0x1
	s_load_b256 s[64:71], s[0:1], 0x20
	s_load_b128 s[84:87], s[0:1], 0x48
	s_getpc_b64 s[62:63]
	s_add_u32 s62, s62, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s63, s63, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_max_f64 v[0:1], v[1:2], 0
	v_max_f64 v[5:6], v[5:6], 0
	v_max_f64 v[9:10], v[9:10], 0
	v_max_f64 v[13:14], v[13:14], 0
	v_max_f64 v[15:16], v[15:16], 0
	v_max_f64 v[2:3], v[3:4], 0
	v_max_f64 v[17:18], v[17:18], 0
	v_max_f64 v[11:12], v[11:12], 0
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[61:62]
	v_cmp_gt_f64_e64 s2, v[5:6], v[19:20]
	v_cmp_gt_f64_e64 s5, v[9:10], v[19:20]
	v_cmp_gt_f64_e64 s7, v[13:14], v[19:20]
	v_cmp_gt_f64_e64 s8, v[15:16], v[19:20]
	v_cmp_gt_f64_e64 s3, v[2:3], v[57:58]
	v_cmp_gt_f64_e64 s9, v[17:18], v[19:20]
	v_cmp_gt_f64_e64 s6, v[11:12], v[19:20]
	v_dual_cndmask_b32 v1, v1, v62 :: v_dual_cndmask_b32 v0, v0, v61
	v_cvt_f64_i32_e32 v[7:8], v7
	v_cndmask_b32_e64 v6, v6, v20, s2
	v_cndmask_b32_e64 v5, v5, v19, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_cvt_i32_f64_e32 v63, v[5:6]
	v_cndmask_b32_e64 v10, v10, v20, s5
	v_cndmask_b32_e64 v14, v14, v20, s7
	v_cndmask_b32_e64 v16, v16, v20, s8
	v_cndmask_b32_e64 v9, v9, v19, s5
	v_cndmask_b32_e64 v13, v13, v19, s7
	v_cndmask_b32_e64 v15, v15, v19, s8
	v_cndmask_b32_e64 v18, v18, v20, s9
	v_cndmask_b32_e64 v17, v17, v19, s9
	v_cndmask_b32_e64 v3, v3, v58, s3
	v_cndmask_b32_e64 v12, v12, v20, s6
	v_cndmask_b32_e64 v2, v2, v57, s3
	v_cndmask_b32_e64 v11, v11, v19, s6
	v_cvt_i32_f64_e32 v4, v[9:10]
	v_cvt_i32_f64_e32 v6, v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v68, v[2:3]
	v_cvt_i32_f64_e32 v5, v[11:12]
	v_max_f64 v[7:8], v[7:8], 0
	v_mul_lo_u32 v0, v0, s81
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v0, v63
	v_mul_lo_u32 v47, v2, s80
	v_add_nc_u32_e32 v10, v0, v4
	v_add_nc_u32_e32 v4, v0, v6
	v_add_nc_u32_e32 v12, v0, v5
	v_cmp_gt_f64_e64 s4, v[7:8], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v20, s4
	v_cndmask_b32_e64 v7, v7, v19, s4
	v_cvt_i32_f64_e32 v1, v[7:8]
	v_cvt_i32_f64_e32 v7, v[15:16]
	v_cvt_i32_f64_e32 v8, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v0, v1
	v_add_nc_u32_e32 v6, v0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v0, v8
	v_mad_u64_u32 v[0:1], null, v3, s80, v[68:69]
	v_mad_u64_u32 v[2:3], null, v4, s80, v[68:69]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[4:5], null, v6, s80, v[68:69]
	v_mad_u64_u32 v[6:7], null, v8, s80, v[68:69]
	v_mad_u64_u32 v[8:9], null, v10, s80, v[68:69]
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_mad_u64_u32 v[10:11], null, v12, s80, v[68:69]
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v12, v47, v68
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v11, 31, v10
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s66, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s67, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s66, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s67, v7, vcc_lo
	v_lshlrev_b64 v[64:65], 3, v[12:13]
	v_add_co_u32 v2, vcc_lo, s66, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s67, v3, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v0, vcc_lo, s66, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s67, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, s66, v64
	v_add_co_ci_u32_e32 v13, vcc_lo, s67, v65, vcc_lo
	s_clause 0x2
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_u32 v8, vcc_lo, s66, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s67, v9, vcc_lo
	s_clause 0x2
	global_load_b64 v[66:67], v[12:13], off
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[8:9], v[8:9], off
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s66, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s67, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_clause 0x1
	s_load_b64 s[70:71], s[0:1], 0x58
	s_load_b256 s[72:79], s[0:1], 0x0
	s_waitcnt vmcnt(5)
	v_add_f64 v[6:7], v[4:5], -v[6:7]
	s_waitcnt vmcnt(4)
	v_add_f64 v[4:5], v[2:3], -v[4:5]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[66:67], -v[2:3]
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[0:1], -v[66:67]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[8:9], -v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_div_scale_f64 v[0:1], null, s[84:85], s[84:85], v[6:7]
	v_div_scale_f64 v[10:11], null, s[84:85], s[84:85], v[4:5]
	v_div_scale_f64 v[50:51], vcc_lo, v[6:7], s[84:85], v[6:7]
	v_div_scale_f64 v[16:17], null, s[84:85], s[84:85], v[2:3]
	v_div_scale_f64 v[18:19], null, s[84:85], s[84:85], v[12:13]
	v_div_scale_f64 v[20:21], null, s[84:85], s[84:85], v[14:15]
	v_div_scale_f64 v[22:23], null, s[84:85], s[84:85], v[8:9]
	v_rcp_f64_e32 v[24:25], v[0:1]
	v_rcp_f64_e32 v[26:27], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[28:29], v[16:17]
	v_rcp_f64_e32 v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[32:33], v[20:21]
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s2, v[4:5], s[84:85], v[4:5]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s3, v[2:3], s[84:85], v[2:3]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s4, v[12:13], s[84:85], v[12:13]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s5, v[14:15], s[84:85], v[14:15]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_div_scale_f64 v[44:45], s6, v[8:9], s[84:85], v[8:9]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_mul_f64 v[48:49], v[50:51], v[24:25]
	v_mul_f64 v[52:53], v[36:37], v[26:27]
	v_mul_f64 v[54:55], v[38:39], v[28:29]
	v_mul_f64 v[69:70], v[40:41], v[30:31]
	v_mul_f64 v[71:72], v[42:43], v[32:33]
	v_mul_f64 v[73:74], v[44:45], v[34:35]
	v_fma_f64 v[0:1], -v[0:1], v[48:49], v[50:51]
	v_fma_f64 v[10:11], -v[10:11], v[52:53], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[54:55], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[69:70], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[71:72], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[73:74], v[44:45]
	v_div_fmas_f64 v[0:1], v[0:1], v[24:25], v[48:49]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[10:11], v[10:11], v[26:27], v[52:53]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[54:55]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[69:70]
	s_mov_b32 vcc_lo, s5
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[71:72]
	s_mov_b32 vcc_lo, s6
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[73:74]
	v_div_fixup_f64 v[0:1], v[0:1], s[84:85], v[6:7]
	v_div_fixup_f64 v[43:44], v[10:11], s[84:85], v[4:5]
	v_div_fixup_f64 v[45:46], v[16:17], s[84:85], v[2:3]
	v_div_fixup_f64 v[50:51], v[18:19], s[84:85], v[12:13]
	v_div_fixup_f64 v[52:53], v[20:21], s[84:85], v[14:15]
	v_div_fixup_f64 v[54:55], v[22:23], s[84:85], v[8:9]
	v_dual_mov_b32 v3, v44 :: v_dual_mov_b32 v2, v43
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51
	v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53
	s_swappc_b64 s[30:31], s[62:63]
	v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1
	v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55
	v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53
	v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44
	s_swappc_b64 s[30:31], s[62:63]
	v_dual_mov_b32 v43, v0 :: v_dual_mov_b32 v44, v1
	v_add_nc_u32_e32 v0, 1, v56
	v_add_nc_u32_e32 v4, -2, v56
	v_add_nc_u32_e32 v6, -3, v56
	v_add_nc_u32_e32 v2, 2, v56
	v_add_nc_u32_e32 v8, -1, v56
	v_cvt_f64_i32_e32 v[0:1], v0
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[2:3], v2
	v_add_nc_u32_e32 v10, 3, v56
	v_cvt_f64_i32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[10:11], v10
	v_max_f64 v[0:1], v[0:1], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[57:58]
	v_cmp_gt_f64_e64 s1, v[4:5], v[57:58]
	v_cmp_gt_f64_e64 s2, v[6:7], v[57:58]
	v_cmp_gt_f64_e64 s0, v[2:3], v[57:58]
	v_cmp_gt_f64_e64 s3, v[8:9], v[57:58]
	v_cmp_gt_f64_e64 s4, v[10:11], v[57:58]
	v_cndmask_b32_e32 v1, v1, v58, vcc_lo
	v_cndmask_b32_e64 v5, v5, v58, s1
	v_cndmask_b32_e32 v0, v0, v57, vcc_lo
	v_cndmask_b32_e64 v4, v4, v57, s1
	v_cndmask_b32_e64 v7, v7, v58, s2
	v_cndmask_b32_e64 v6, v6, v57, s2
	v_cndmask_b32_e64 v3, v3, v58, s0
	v_cndmask_b32_e64 v2, v2, v57, s0
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_cvt_i32_f64_e32 v1, v[4:5]
	v_cndmask_b32_e64 v9, v9, v58, s3
	v_cndmask_b32_e64 v8, v8, v57, s3
	v_cvt_i32_f64_e32 v4, v[6:7]
	v_cvt_i32_f64_e32 v3, v[2:3]
	v_cndmask_b32_e64 v11, v11, v58, s4
	v_cndmask_b32_e64 v10, v10, v57, s4
	v_cvt_i32_f64_e32 v5, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v7, v[10:11]
	v_add_nc_u32_e32 v0, v47, v0
	v_add_nc_u32_e32 v2, v47, v1
	v_add_nc_u32_e32 v4, v47, v4
	v_add_nc_u32_e32 v8, v47, v3
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v6, v47, v5
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_nc_u32_e32 v10, v47, v7
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v2, vcc_lo, s66, v2
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_ci_u32_e32 v3, vcc_lo, s67, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s66, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s67, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s66, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s67, v7, vcc_lo
	v_add_co_u32 v0, vcc_lo, s66, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s67, v1, vcc_lo
	s_clause 0x2
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s66, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s67, v9, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[8:9], v[8:9], off
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v10, vcc_lo, s66, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s67, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(4)
	v_add_f64 v[4:5], v[2:3], -v[4:5]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[6:7], -v[2:3]
	v_add_f64 v[6:7], v[66:67], -v[6:7]
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[0:1], -v[66:67]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[8:9], -v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_div_scale_f64 v[0:1], null, s[86:87], s[86:87], v[4:5]
	v_div_scale_f64 v[10:11], null, s[86:87], s[86:87], v[2:3]
	v_div_scale_f64 v[16:17], null, s[86:87], s[86:87], v[6:7]
	v_div_scale_f64 v[53:54], vcc_lo, v[4:5], s[86:87], v[4:5]
	v_div_scale_f64 v[18:19], null, s[86:87], s[86:87], v[12:13]
	v_div_scale_f64 v[20:21], null, s[86:87], s[86:87], v[14:15]
	v_div_scale_f64 v[22:23], null, s[86:87], s[86:87], v[8:9]
	v_rcp_f64_e32 v[24:25], v[0:1]
	v_rcp_f64_e32 v[26:27], v[10:11]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[45:46], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[47:48], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[49:50], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[51:52], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[45:46], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[47:48], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[49:50], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[51:52], v[34:35]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[10:11], v[26:27], 1.0
	v_fma_f64 v[45:46], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[47:48], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[49:50], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[51:52], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[86:87], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[6:7], s[86:87], v[6:7]
	v_fma_f64 v[28:29], v[28:29], v[45:46], v[28:29]
	v_div_scale_f64 v[45:46], s2, v[12:13], s[86:87], v[12:13]
	v_fma_f64 v[30:31], v[30:31], v[47:48], v[30:31]
	v_div_scale_f64 v[47:48], s3, v[14:15], s[86:87], v[14:15]
	v_fma_f64 v[32:33], v[32:33], v[49:50], v[32:33]
	v_div_scale_f64 v[49:50], s4, v[8:9], s[86:87], v[8:9]
	v_fma_f64 v[34:35], v[34:35], v[51:52], v[34:35]
	v_mul_f64 v[51:52], v[53:54], v[24:25]
	v_mul_f64 v[55:56], v[36:37], v[26:27]
	v_mul_f64 v[57:58], v[38:39], v[28:29]
	v_mul_f64 v[69:70], v[45:46], v[30:31]
	v_mul_f64 v[71:72], v[47:48], v[32:33]
	v_mul_f64 v[73:74], v[49:50], v[34:35]
	v_fma_f64 v[0:1], -v[0:1], v[51:52], v[53:54]
	v_fma_f64 v[10:11], -v[10:11], v[55:56], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[57:58], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[69:70], v[45:46]
	v_fma_f64 v[20:21], -v[20:21], v[71:72], v[47:48]
	v_fma_f64 v[22:23], -v[22:23], v[73:74], v[49:50]
	v_div_fmas_f64 v[0:1], v[0:1], v[24:25], v[51:52]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[26:27], v[55:56]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[57:58]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[69:70]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[71:72]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[73:74]
	v_div_fixup_f64 v[0:1], v[0:1], s[86:87], v[4:5]
	v_div_fixup_f64 v[50:51], v[10:11], s[86:87], v[2:3]
	v_div_fixup_f64 v[52:53], v[16:17], s[86:87], v[6:7]
	v_div_fixup_f64 v[54:55], v[18:19], s[86:87], v[12:13]
	v_div_fixup_f64 v[56:57], v[20:21], s[86:87], v[14:15]
	v_div_fixup_f64 v[58:59], v[22:23], s[86:87], v[8:9]
	v_dual_mov_b32 v2, v50 :: v_dual_mov_b32 v3, v51
	v_dual_mov_b32 v4, v52 :: v_dual_mov_b32 v5, v53
	v_dual_mov_b32 v6, v54 :: v_dual_mov_b32 v7, v55
	v_dual_mov_b32 v9, v57 :: v_dual_mov_b32 v8, v56
	s_swappc_b64 s[30:31], s[62:63]
	v_dual_mov_b32 v45, v0 :: v_dual_mov_b32 v46, v1
	v_dual_mov_b32 v0, v58 :: v_dual_mov_b32 v1, v59
	v_dual_mov_b32 v2, v56 :: v_dual_mov_b32 v3, v57
	v_dual_mov_b32 v4, v54 :: v_dual_mov_b32 v5, v55
	v_dual_mov_b32 v6, v52 :: v_dual_mov_b32 v7, v53
	v_dual_mov_b32 v8, v50 :: v_dual_mov_b32 v9, v51
	s_swappc_b64 s[30:31], s[62:63]
	v_dual_mov_b32 v50, v0 :: v_dual_mov_b32 v51, v1
	v_add_nc_u32_e32 v0, 1, v60
	v_add_nc_u32_e32 v2, 2, v60
	v_add_nc_u32_e32 v4, 3, v60
	v_add_nc_u32_e32 v6, -1, v60
	v_add_nc_u32_e32 v8, -2, v60
	v_cvt_f64_i32_e32 v[0:1], v0
	v_cvt_f64_i32_e32 v[2:3], v2
	v_cvt_f64_i32_e32 v[4:5], v4
	v_add_nc_u32_e32 v10, -3, v60
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[10:11], v10
	v_max_f64 v[0:1], v[0:1], 0
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[61:62]
	v_cmp_gt_f64_e64 s0, v[2:3], v[61:62]
	v_cmp_gt_f64_e64 s1, v[4:5], v[61:62]
	v_cmp_gt_f64_e64 s2, v[6:7], v[61:62]
	v_cmp_gt_f64_e64 s3, v[8:9], v[61:62]
	v_cmp_gt_f64_e64 s4, v[10:11], v[61:62]
	v_dual_cndmask_b32 v1, v1, v62 :: v_dual_cndmask_b32 v0, v0, v61
	v_cndmask_b32_e64 v3, v3, v62, s0
	v_cndmask_b32_e64 v2, v2, v61, s0
	v_cndmask_b32_e64 v5, v5, v62, s1
	v_cndmask_b32_e64 v4, v4, v61, s1
	v_cndmask_b32_e64 v7, v7, v62, s2
	v_cndmask_b32_e64 v6, v6, v61, s2
	v_cndmask_b32_e64 v9, v9, v62, s3
	v_cndmask_b32_e64 v8, v8, v61, s3
	v_cvt_i32_f64_e32 v12, v[0:1]
	v_cvt_i32_f64_e32 v3, v[2:3]
	v_cndmask_b32_e64 v11, v11, v62, s4
	v_cvt_i32_f64_e32 v4, v[4:5]
	v_cndmask_b32_e64 v10, v10, v61, s4
	v_cvt_i32_f64_e32 v5, v[6:7]
	v_cvt_i32_f64_e32 v6, v[8:9]
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_i32_f64_e32 v7, v[10:11]
	v_mad_u64_u32 v[0:1], null, v12, s81, v[63:64]
	v_mad_u64_u32 v[1:2], null, v3, s81, v[63:64]
	v_mad_u64_u32 v[2:3], null, v4, s81, v[63:64]
	v_mad_u64_u32 v[3:4], null, v5, s81, v[63:64]
	v_mad_u64_u32 v[4:5], null, v6, s81, v[63:64]
	v_mad_u64_u32 v[5:6], null, v7, s81, v[63:64]
	v_mad_u64_u32 v[6:7], null, v0, s80, v[68:69]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[8:9], null, v3, s80, v[68:69]
	v_mad_u64_u32 v[10:11], null, v4, s80, v[68:69]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[3:4], null, v5, s80, v[68:69]
	v_mad_u64_u32 v[12:13], null, v1, s80, v[68:69]
	v_ashrrev_i32_e32 v9, 31, v8
	v_mad_u64_u32 v[0:1], null, v2, s80, v[68:69]
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	v_lshlrev_b64 v[4:5], 3, v[8:9]
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[12:13]
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v10, vcc_lo, s66, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s67, v11, vcc_lo
	v_add_co_u32 v2, vcc_lo, s66, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s67, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s66, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s67, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s66, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s67, v7, vcc_lo
	s_clause 0x2
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_u32 v8, vcc_lo, s66, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s67, v9, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s66, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s67, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(4)
	v_add_f64 v[2:3], v[10:11], -v[2:3]
	s_waitcnt vmcnt(3)
	v_add_f64 v[10:11], v[4:5], -v[10:11]
	v_add_f64 v[4:5], v[66:67], -v[4:5]
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[6:7], -v[66:67]
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[0:1], -v[8:9]
	v_div_scale_f64 v[0:1], null, s[70:71], s[70:71], v[2:3]
	v_div_scale_f64 v[14:15], null, s[70:71], s[70:71], v[10:11]
	v_div_scale_f64 v[16:17], null, s[70:71], s[70:71], v[4:5]
	v_div_scale_f64 v[58:59], vcc_lo, v[2:3], s[70:71], v[2:3]
	v_div_scale_f64 v[18:19], null, s[70:71], s[70:71], v[12:13]
	v_div_scale_f64 v[20:21], null, s[70:71], s[70:71], v[6:7]
	v_div_scale_f64 v[22:23], null, s[70:71], s[70:71], v[8:9]
	v_rcp_f64_e32 v[24:25], v[0:1]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[47:48], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[52:53], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[56:57], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[47:48], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[52:53], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[54:55], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[56:57], v[34:35]
	v_fma_f64 v[36:37], -v[0:1], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[47:48], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[52:53], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[54:55], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[56:57], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[10:11], s[70:71], v[10:11]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[70:71], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[47:48], v[28:29]
	v_div_scale_f64 v[47:48], s2, v[12:13], s[70:71], v[12:13]
	v_fma_f64 v[30:31], v[30:31], v[52:53], v[30:31]
	v_div_scale_f64 v[52:53], s3, v[6:7], s[70:71], v[6:7]
	v_fma_f64 v[32:33], v[32:33], v[54:55], v[32:33]
	v_div_scale_f64 v[54:55], s4, v[8:9], s[70:71], v[8:9]
	v_fma_f64 v[34:35], v[34:35], v[56:57], v[34:35]
	v_mul_f64 v[56:57], v[58:59], v[24:25]
	v_mul_f64 v[60:61], v[36:37], v[26:27]
	v_mul_f64 v[62:63], v[38:39], v[28:29]
	v_mul_f64 v[68:69], v[47:48], v[30:31]
	v_mul_f64 v[70:71], v[52:53], v[32:33]
	v_mul_f64 v[72:73], v[54:55], v[34:35]
	v_fma_f64 v[0:1], -v[0:1], v[56:57], v[58:59]
	v_fma_f64 v[14:15], -v[14:15], v[60:61], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[62:63], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[68:69], v[47:48]
	v_fma_f64 v[20:21], -v[20:21], v[70:71], v[52:53]
	v_fma_f64 v[22:23], -v[22:23], v[72:73], v[54:55]
	v_div_fmas_f64 v[0:1], v[0:1], v[24:25], v[56:57]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[60:61]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[62:63]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[68:69]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[70:71]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[72:73]
	v_div_fixup_f64 v[0:1], v[0:1], s[70:71], v[2:3]
	v_div_fixup_f64 v[52:53], v[14:15], s[70:71], v[10:11]
	v_div_fixup_f64 v[54:55], v[16:17], s[70:71], v[4:5]
	v_div_fixup_f64 v[56:57], v[18:19], s[70:71], v[12:13]
	v_div_fixup_f64 v[58:59], v[20:21], s[70:71], v[6:7]
	v_div_fixup_f64 v[60:61], v[22:23], s[70:71], v[8:9]
	v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53
	v_dual_mov_b32 v4, v54 :: v_dual_mov_b32 v5, v55
	v_dual_mov_b32 v6, v56 :: v_dual_mov_b32 v7, v57
	v_dual_mov_b32 v9, v59 :: v_dual_mov_b32 v8, v58
	s_swappc_b64 s[30:31], s[62:63]
	v_dual_mov_b32 v62, v0 :: v_dual_mov_b32 v63, v1
	v_dual_mov_b32 v0, v60 :: v_dual_mov_b32 v1, v61
	v_dual_mov_b32 v2, v58 :: v_dual_mov_b32 v3, v59
	v_dual_mov_b32 v4, v56 :: v_dual_mov_b32 v5, v57
	v_dual_mov_b32 v6, v54 :: v_dual_mov_b32 v7, v55
	v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53
	s_swappc_b64 s[30:31], s[62:63]
	v_add_co_u32 v2, vcc_lo, s74, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s75, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s76, v64
	v_add_co_ci_u32_e32 v5, vcc_lo, s77, v65, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_u32 v6, vcc_lo, s78, v64
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s79, v65, vcc_lo
	v_add_co_u32 v8, vcc_lo, s64, v64
	v_add_co_ci_u32_e32 v9, vcc_lo, s65, v65, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(3)
	v_max_f64 v[10:11], v[2:3], v[2:3]
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[2:3]
	s_waitcnt vmcnt(2)
	v_max_f64 v[12:13], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_max_f64 v[10:11], v[10:11], 0
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[4:5]
	v_mul_f64 v[10:11], v[41:42], v[10:11]
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 0, v4
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[43:44], v[2:3], v[10:11]
	v_max_f64 v[10:11], v[12:13], 0
	v_fma_f64 v[2:3], v[50:51], v[4:5], v[2:3]
	v_max_f64 v[4:5], v[6:7], v[6:7]
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[45:46], v[10:11], v[2:3]
	v_fma_f64 v[0:1], v[0:1], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f64 v[2:3], v[4:5], 0
	v_fma_f64 v[0:1], v[62:63], v[2:3], v[0:1]
	v_add_co_u32 v2, vcc_lo, s72, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s73, v65, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[66:67], v[8:9], v[0:1]
	v_mul_f64 v[0:1], v[0:1], s[68:69]
	global_store_b64 v[2:3], v[0:1], off
.LBB2_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 75
		.amdhsa_next_free_sgpr 88
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd, .Lfunc_end2-_Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4428
; NumSgprs: 90
; NumVgprs: 75
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 90
; NumVGPRsForWavesPerEU: 75
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd ; -- Begin function _Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.globl	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
	.p2align	8
	.type	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd,@function
_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd: ; @_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x64
	s_load_b128 s[16:19], s[0:1], 0x30
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	v_bfe_u32 v6, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[2:3], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s14, s4, v[5:6]
	v_mad_u64_u32 v[0:1], null, s15, s3, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s16, v2
	v_cmp_gt_i32_e64 s2, s17, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s18, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_cvt_f64_i32_e32 v[4:5], v0
	s_add_i32 s2, s18, -1
	v_cvt_f64_i32_e32 v[6:7], v3
	v_cvt_f64_i32_e32 v[12:13], s2
	v_cvt_f64_i32_e32 v[10:11], v2
	s_add_i32 s2, s17, -1
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x20
	s_load_b128 s[20:23], s[0:1], 0x40
	v_cvt_f64_i32_e32 v[14:15], s2
	s_add_i32 s2, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[18:19], s2
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[12:13]
	v_add_nc_u32_e32 v1, 1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e64 s2, v[6:7], v[14:15]
	v_cmp_gt_f64_e64 s4, v[10:11], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[8:9], v1
	v_add_nc_u32_e32 v1, -1, v3
	v_add_nc_u32_e32 v3, -1, v2
	v_cvt_f64_i32_e32 v[16:17], v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[16:17], v[16:17], 0
	v_dual_cndmask_b32 v2, v5, v13 :: v_dual_add_nc_u32 v1, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[20:21], v1
	v_cndmask_b32_e32 v1, v4, v12, vcc_lo
	v_cvt_i32_f64_e32 v22, v[1:2]
	v_cndmask_b32_e64 v1, v6, v14, s2
	v_cndmask_b32_e64 v2, v7, v15, s2
	v_cndmask_b32_e64 v7, v10, v18, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v1, v[1:2]
	v_cmp_gt_f64_e64 s3, v[8:9], v[14:15]
	v_cmp_gt_f64_e32 vcc_lo, v[16:17], v[14:15]
	v_mul_lo_u32 v24, v22, s17
	v_cndmask_b32_e64 v6, v9, v15, s3
	v_cndmask_b32_e64 v5, v8, v14, s3
	v_cndmask_b32_e64 v8, v11, v19, s4
	s_load_b256 s[4:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_i32_f64_e32 v11, v[5:6]
	v_max_f64 v[5:6], v[20:21], 0
	v_dual_cndmask_b32 v10, v17, v15 :: v_dual_cndmask_b32 v9, v16, v14
	v_cvt_i32_f64_e32 v2, v[7:8]
	v_add_nc_u32_e32 v7, 1, v0
	v_add_nc_u32_e32 v0, -1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v25, v[9:10]
	v_add_nc_u32_e32 v9, v24, v1
	v_cvt_f64_i32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[14:15], v0
	v_mul_lo_u32 v26, v9, s16
	v_add_nc_u32_e32 v11, v24, v11
	v_cmp_gt_f64_e32 vcc_lo, v[5:6], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v16, v26, v2
	v_add_nc_u32_e32 v0, v24, v25
	v_ashrrev_i32_e32 v17, 31, v16
	v_max_f64 v[7:8], v[7:8], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 3, v[16:17]
	v_dual_cndmask_b32 v5, v5, v18 :: v_dual_cndmask_b32 v6, v6, v19
	v_cvt_f64_i32_e32 v[3:4], v3
	v_cmp_gt_f64_e32 vcc_lo, v[7:8], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_max_f64 v[3:4], v[3:4], 0
	v_cndmask_b32_e32 v8, v8, v13, vcc_lo
	v_mad_u64_u32 v[9:10], null, v11, s16, v[2:3]
	v_mad_u64_u32 v[24:25], null, v0, s16, v[2:3]
	v_cvt_i32_f64_e32 v0, v[5:6]
	v_max_f64 v[5:6], v[14:15], 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_lshlrev_b64 v[14:15], 3, v[24:25]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v20, s2, s6, v9
	v_add_co_ci_u32_e64 v21, s2, s7, v10, s2
	v_add_co_u32 v22, s2, s6, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s2, s7, v17, s2
	v_cmp_gt_f64_e64 s2, v[3:4], v[18:19]
	s_clause 0x1
	global_load_b64 v[20:21], v[20:21], off
	global_load_b64 v[22:23], v[22:23], off
	v_add_co_u32 v24, s3, s6, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v25, s3, s7, v15, s3
	s_load_b64 s[6:7], s[0:1], 0x50
	global_load_b64 v[24:25], v[24:25], off
	v_cndmask_b32_e64 v4, v4, v19, s2
	v_cndmask_b32_e64 v3, v3, v18, s2
	v_cmp_gt_f64_e64 s2, v[5:6], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v11, v[3:4]
	v_add_nc_u32_e32 v3, v26, v0
	v_cndmask_b32_e32 v7, v7, v12, vcc_lo
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_cndmask_b32_e64 v5, v5, v12, s2
	v_cndmask_b32_e64 v6, v6, v13, s2
	v_add_nc_u32_e32 v26, v26, v11
	v_cvt_i32_f64_e32 v0, v[7:8]
	v_add_co_u32 v7, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v18, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v17, vcc_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[18:19], v[18:19], off
	v_ashrrev_i32_e32 v27, 31, v26
	v_cvt_i32_f64_e32 v13, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[26:27]
	v_add_co_u32 v5, vcc_lo, s8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v12, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	v_mad_u64_u32 v[26:27], null, v0, s17, v[1:2]
	v_add_co_u32 v27, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v17, vcc_lo
	v_mad_u64_u32 v[29:30], null, v26, s16, v[2:3]
	global_load_b64 v[27:28], v[27:28], off
	v_mad_u64_u32 v[31:32], null, v13, s17, v[1:2]
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	v_mad_u64_u32 v[34:35], null, v31, s16, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s10, v29
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v30, vcc_lo
	v_add_co_u32 v32, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v33, vcc_lo, s11, v17, vcc_lo
	v_add_co_u32 v9, vcc_lo, s12, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[32:33], v[32:33], off
	global_load_b64 v[9:10], v[9:10], off
	v_ashrrev_i32_e32 v35, 31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[34:35], 3, v[34:35]
	v_add_co_u32 v36, vcc_lo, s10, v34
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v37, vcc_lo, s11, v35, vcc_lo
	v_add_co_u32 v13, vcc_lo, s12, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v15, vcc_lo
	global_load_b64 v[36:37], v[36:37], off
	v_add_co_u32 v2, vcc_lo, s12, v3
	global_load_b64 v[13:14], v[13:14], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v4, vcc_lo
	v_add_co_u32 v11, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_u32 v29, vcc_lo, s12, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v30, vcc_lo
	v_add_co_u32 v34, vcc_lo, s12, v34
	v_add_co_ci_u32_e32 v35, vcc_lo, s13, v35, vcc_lo
	s_clause 0x2
	global_load_b64 v[29:30], v[29:30], off
	global_load_b64 v[11:12], v[11:12], off
	global_load_b64 v[34:35], v[34:35], off
	s_waitcnt vmcnt(14)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_waitcnt vmcnt(13)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[20:21], v[20:21], 0.5
	v_mul_f64 v[22:23], v[22:23], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_max_f64 v[24:25], v[20:21], 0
	v_cmp_nlt_f64_e64 s2, 0, v[20:21]
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[22:23]
	s_waitcnt vmcnt(11)
	v_add_f64 v[7:8], v[7:8], v[18:19]
	s_waitcnt vmcnt(10)
	v_add_f64 v[4:5], v[18:19], v[5:6]
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v21, 0, v21, s2
	v_cndmask_b32_e64 v20, 0, v20, s2
	s_waitcnt vmcnt(9)
	v_mul_f64 v[18:19], v[27:28], v[24:25]
	v_mul_f64 v[6:7], v[7:8], 0.5
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 0, v22
	v_max_f64 v[22:23], v[22:23], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[24:25], v[27:28], v[24:25]
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_waitcnt vmcnt(7)
	v_add_f64 v[0:1], v[0:1], v[32:33]
	s_waitcnt vmcnt(6)
	v_fma_f64 v[8:9], v[9:10], v[20:21], -v[18:19]
	v_max_f64 v[38:39], v[6:7], 0
	v_cmp_nlt_f64_e64 s2, 0, v[6:7]
	s_waitcnt vmcnt(5)
	v_add_f64 v[18:19], v[32:33], v[36:37]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[13:14], v[13:14], v[22:23], -v[24:25]
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[4:5]
	v_mul_f64 v[0:1], v[0:1], 0.5
	v_mul_f64 v[8:9], v[8:9], s[22:23]
	v_mul_f64 v[20:21], v[27:28], v[38:39]
	v_cndmask_b32_e64 v7, 0, v7, s2
	v_cndmask_b32_e64 v6, 0, v6, s2
	v_mul_f64 v[18:19], v[18:19], 0.5
	v_dual_cndmask_b32 v23, 0, v5 :: v_dual_cndmask_b32 v22, 0, v4
	v_max_f64 v[4:5], v[4:5], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[22:23], v[27:28], v[22:23]
	v_max_f64 v[24:25], v[0:1], 0
	v_cmp_nlt_f64_e64 s0, 0, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[8:9], v[8:9], s[6:7], 0
	s_waitcnt vmcnt(3)
	v_fma_f64 v[2:3], v[2:3], v[6:7], -v[20:21]
	v_mul_f64 v[6:7], v[13:14], s[22:23]
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[18:19]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[4:5], v[11:12], v[4:5], -v[22:23]
	v_max_f64 v[10:11], v[18:19], 0
	v_mul_f64 v[13:14], v[27:28], v[24:25]
	v_cndmask_b32_e64 v1, 0, v1, s0
	v_cndmask_b32_e64 v0, 0, v0, s0
	v_mul_f64 v[2:3], v[2:3], s[20:21]
	v_fma_f64 v[6:7], v[6:7], s[6:7], v[8:9]
	v_dual_cndmask_b32 v9, 0, v19 :: v_dual_cndmask_b32 v8, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[8:9], v[27:28], v[8:9]
	v_mul_f64 v[4:5], v[4:5], s[20:21]
	v_fma_f64 v[0:1], v[29:30], v[0:1], -v[13:14]
	v_fma_f64 v[2:3], v[2:3], s[6:7], v[6:7]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[34:35], v[10:11], -v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[0:1], v[0:1], s[20:21]
	v_fma_f64 v[2:3], v[4:5], s[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], v[6:7], s[20:21]
	v_fma_f64 v[0:1], v[0:1], s[22:23], v[2:3]
	v_mul_f64 v[2:3], s[20:21], s[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[4:5], s[22:23], v[0:1]
	v_mul_f64 v[2:3], v[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[14:15]
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
	v_add_co_u32 v2, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v17, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd, .Lfunc_end3-_Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1860
; NumSgprs: 26
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15weno_derivativePdS_S_S_S_S_PKdiiiddd
    .private_segment_fixed_size: 8
    .sgpr_count:     90
    .sgpr_spill_count: 0
    .symbol:         _Z15weno_derivativePdS_S_S_S_S_PKdiiiddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     74
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd
    .private_segment_fixed_size: 8
    .sgpr_count:     90
    .sgpr_spill_count: 0
    .symbol:         _Z25surface_conservation_stepPdPKdS1_S1_S1_S1_diiiddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     75
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z26spatial_finite_volume_stepPdPKdS1_S1_S1_diiiddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
