#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <cuda.h>


__global__ void kernel_grey(uint8_t* start, uint8_t* end, int height, int width)
{
  int i, j, k, l;
  float blur[3][3] = {{1,2,1}, {2,4,2}, {1,2,1}}; // filtro blur gaussian
  float filter[3][3];

  for(int i=0;i<3;i++)
    for(int j=0;j<3;j++)
      filter[i][j]=blur[2-i][2-j];  // antistofi filtrou ana grammes kai ana sthles

  // h thesi tou thread ston pinaka
  size_t x = blockIdx.x * blockDim.x + threadIdx.x;
  size_t y = blockIdx.y * blockDim.y + threadIdx.y;

  float new_val;
  new_val = 0.0;  // h nea timh sthn thesh tou pinaka

  for (i = x-1, k = 0 ; i <= x+1 ; i++, k++) {
    for (j = y-1, l = 0 ; j <= y+1 ; j++, l++) {
      if ( i == -1 || i == height || j == -1 || j == width ) {
        new_val = start[width * x + y]; // an eisai ektos twn diastasevn tou pinaka,
        //pol/se thn timh tou pixel ths theshs, pou allazeis timh, me thn antistoixi thesi tou filtrou
      }
      else {
        new_val += start[width * i + j] * filter[k][l] / 16.0;  // an eisai entos twn diastasevn tou pinaka,
        //pol/se thn timh tou pixel pou koitas me thn antistoixi thesi tou filtrou
      }
    }
  }
  end[width * x + y] = new_val;
}


__global__ void kernel_rgb(uint8_t* start, uint8_t* end, int height, int width)
{
  int i, j, k, l;
  float blur[3][3] = {{1,2,1}, {2,4,2}, {1,2,1}}; // filtro blur gaussian
  float filter[3][3];

  for(int i=0;i<3;i++)
    for(int j=0;j<3;j++)
      filter[i][j]=blur[2-i][2-j];  // antistofi filtrou ana grammes kai ana sthles

  size_t x = blockIdx.x * blockDim.x + threadIdx.x;
  size_t y = blockIdx.y * blockDim.y + threadIdx.y;

  float new_val_red, new_val_blue, new_val_green;
  new_val_red = 0.0;  // h nees times sthn thesh tou pinaka gia red, green and blue
  new_val_blue = 0.0;
  new_val_green = 0.0;

  for (i = x-1, k = 0 ; i <= x+1 ; i++, k++) {
    for (j = (y*3)-3, l = 0 ; j <= (y*3)+3 ; j += 3, l++) {
      if ( i == -1 || i == height || j == -3 || j == (3*width) ) { // an eisai ektos twn diastasevn tou pinaka,
      //pol/se tis times gia red, green and blue tou pixel ths theshs, pou allazeis timh, me thn antistoixi thesi tou filtrou
        new_val_red += start[(width*3) * x + y] * filter[k][l] / 16.0;
        new_val_green += start[(width*3) * x + y + 1] * filter[k][l] / 16.0;
        new_val_blue += start[(width*3) * x + y + 2] * filter[k][l] / 16.0;
      }
      else { // an eisai entos twn diastasevn tou pinaka,
      //pol/se tis times gia red, green and blue tou pixel pou koitas me thn antistoixi thesi tou filtrou
        new_val_red += start[(width*3) * i + j] * filter[k][l] / 16.0;
        new_val_green += start[(width*3) * i + j + 1] * filter[k][l] / 16.0;
        new_val_blue += start[(width*3) * i + j + 2] * filter[k][l] / 16.0;
      }
    }
  }
  end[(width*3) * x + (y*3)] = new_val_red;
  end[(width*3) * x + (y*3) + 1] = new_val_green;
  end[(width*3) * x + (y*3) + 2] = new_val_blue;
}



extern "C" void filtering( uint8_t* table, int height, int width, int loops, char* type, int blocksize)
{
  uint8_t* start, * end, * temp;
  size_t bytes;

  if(strcmp(type, "GREY") == 0) bytes = height * width;
  else bytes = height * width * 3;

  // desmeuse xoro gia kathe vector sthn GPU
  cudaMalloc( &start, bytes*sizeof(uint8_t) );
  cudaMalloc( &end, bytes*sizeof(uint8_t) );

  // antegrapse ta host vectors sthn mnhmh ths suskeuhs
  cudaMemcpy( start, table, bytes, cudaMemcpyHostToDevice );
  cudaMemset( end, 0, bytes );

  int i;

  for(i=0; i<loops; i++) // gia osa loops zhththikan
  {
    if(strcmp(type, "GREY") == 0) // an einai GREY
    {
      int gridX, gridY;
      gridX = (height + blocksize - 1) / blocksize;
      gridY = (width + blocksize - 1) / blocksize;
      dim3 dimBlock(blocksize, blocksize);
      dim3 dimGrid(gridX, gridY);
      kernel_grey<<<dimGrid, dimBlock>>>(start, end, height, width);
    }
    else  // an einai RGB
    {
      int gridX, gridY;
      gridX = (height + blocksize - 1) / blocksize;
      gridY = ((width * 3) + blocksize - 1) / blocksize;
      dim3 dimBlock(blocksize, blocksize);
      dim3 dimGrid(gridX, gridY);
      kernel_rgb<<<dimGrid, dimBlock>>>(start, end, height, width);
    }

    // antimetathese tous pinakes
    temp = start;
    start = end;
    end = temp;
  }

  cudaGetLastError();
  cudaThreadSynchronize();


  // antegrapse thn telikh eikona ston host
  if(loops%2 == 0)
  {
    cudaMemcpy( table, start, bytes, cudaMemcpyDeviceToHost );
  }
  else
  {
    cudaMemcpy( table, end, bytes, cudaMemcpyDeviceToHost );
  }

  // apeleutherwse thn mnhmh ths suskeuhs
  cudaFree(start);
  cudaFree(end);
}

	.file	"tmpxft_003ac658_00000000-6_cuda_functions.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii
	.type	_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii, @function
_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11kernel_greyPhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii, .-_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii
	.globl	_Z11kernel_greyPhS_ii
	.type	_Z11kernel_greyPhS_ii, @function
_Z11kernel_greyPhS_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii
	.cfi_endproc
.LFE2057:
	.size	_Z11kernel_greyPhS_ii, .-_Z11kernel_greyPhS_ii
	.globl	_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii
	.type	_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii, @function
_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10kernel_rgbPhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii, .-_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii
	.globl	_Z10kernel_rgbPhS_ii
	.type	_Z10kernel_rgbPhS_ii, @function
_Z10kernel_rgbPhS_ii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii
	.cfi_endproc
.LFE2059:
	.size	_Z10kernel_rgbPhS_ii, .-_Z10kernel_rgbPhS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GREY"
	.text
	.globl	filtering
	.type	filtering, @function
filtering:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%ecx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%esi, %r13d
	leaq	.LC0(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r13d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	imull	%r12d, %ebp
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 8(%rsp)
	movq	%r8, %rdi
	movq	%r8, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	strcmp@PLT
	testl	%eax, %eax
	je	.L26
	leal	0(%rbp,%rbp,2), %ebp
.L26:
	movslq	%ebp, %rbp
	leaq	32(%rsp), %rdi
	xorl	%r15d, %r15d
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movq	%rbp, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leal	(%r12,%r12,2), %eax
	leal	-1(%rbx,%rax), %eax
	movl	%eax, 28(%rsp)
.L16:
	cmpl	%r14d, %r15d
	jge	.L28
	movq	16(%rsp), %rdi
	leaq	.LC0(%rip), %rsi
	call	strcmp@PLT
	movl	%ebx, 48(%rsp)
	movl	%eax, %ecx
	leal	-1(%r13,%rbx), %eax
	movl	%ebx, 52(%rsp)
	cltd
	movl	$1, 56(%rsp)
	idivl	%ebx
	movl	%eax, 60(%rsp)
	testl	%ecx, %ecx
	jne	.L17
	leal	-1(%r12,%rbx), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cltd
	movl	$1, %esi
	movl	$1, 68(%rsp)
	idivl	%ebx
	movq	48(%rsp), %rdx
	movl	%eax, 64(%rsp)
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%r13d, %edx
	call	_Z35__device_stub__Z11kernel_greyPhS_iiPhS_ii
	jmp	.L19
.L17:
	movl	28(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 68(%rsp)
	cltd
	idivl	%ebx
	movq	48(%rsp), %rdx
	movl	%eax, 64(%rsp)
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%r13d, %edx
	call	_Z34__device_stub__Z10kernel_rgbPhS_iiPhS_ii
.L19:
	movq	32(%rsp), %rax
	movq	40(%rsp), %rdx
	incl	%r15d
	movq	%rdx, 32(%rsp)
	movq	%rax, 40(%rsp)
	jmp	.L16
.L28:
	call	cudaGetLastError@PLT
	call	cudaThreadSynchronize@PLT
	andl	$1, %r14d
	movl	$2, %ecx
	movq	%rbp, %rdx
	jne	.L22
	movq	32(%rsp), %rsi
	jmp	.L27
.L22:
	movq	40(%rsp), %rsi
.L27:
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	filtering, .-filtering
	.section	.rodata.str1.1
.LC1:
	.string	"_Z10kernel_rgbPhS_ii"
.LC2:
	.string	"_Z11kernel_greyPhS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10kernel_rgbPhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11kernel_greyPhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <hip/hip_runtime.h>


__global__ void kernel_grey(uint8_t* start, uint8_t* end, int height, int width)
{
  int i, j, k, l;
  float blur[3][3] = {{1,2,1}, {2,4,2}, {1,2,1}}; // filtro blur gaussian
  float filter[3][3];

  for(int i=0;i<3;i++)
    for(int j=0;j<3;j++)
      filter[i][j]=blur[2-i][2-j];  // antistofi filtrou ana grammes kai ana sthles

  // h thesi tou thread ston pinaka
  size_t x = blockIdx.x * blockDim.x + threadIdx.x;
  size_t y = blockIdx.y * blockDim.y + threadIdx.y;

  float new_val;
  new_val = 0.0;  // h nea timh sthn thesh tou pinaka

  for (i = x-1, k = 0 ; i <= x+1 ; i++, k++) {
    for (j = y-1, l = 0 ; j <= y+1 ; j++, l++) {
      if ( i == -1 || i == height || j == -1 || j == width ) {
        new_val = start[width * x + y]; // an eisai ektos twn diastasevn tou pinaka,
        //pol/se thn timh tou pixel ths theshs, pou allazeis timh, me thn antistoixi thesi tou filtrou
      }
      else {
        new_val += start[width * i + j] * filter[k][l] / 16.0;  // an eisai entos twn diastasevn tou pinaka,
        //pol/se thn timh tou pixel pou koitas me thn antistoixi thesi tou filtrou
      }
    }
  }
  end[width * x + y] = new_val;
}


__global__ void kernel_rgb(uint8_t* start, uint8_t* end, int height, int width)
{
  int i, j, k, l;
  float blur[3][3] = {{1,2,1}, {2,4,2}, {1,2,1}}; // filtro blur gaussian
  float filter[3][3];

  for(int i=0;i<3;i++)
    for(int j=0;j<3;j++)
      filter[i][j]=blur[2-i][2-j];  // antistofi filtrou ana grammes kai ana sthles

  size_t x = blockIdx.x * blockDim.x + threadIdx.x;
  size_t y = blockIdx.y * blockDim.y + threadIdx.y;

  float new_val_red, new_val_blue, new_val_green;
  new_val_red = 0.0;  // h nees times sthn thesh tou pinaka gia red, green and blue
  new_val_blue = 0.0;
  new_val_green = 0.0;

  for (i = x-1, k = 0 ; i <= x+1 ; i++, k++) {
    for (j = (y*3)-3, l = 0 ; j <= (y*3)+3 ; j += 3, l++) {
      if ( i == -1 || i == height || j == -3 || j == (3*width) ) { // an eisai ektos twn diastasevn tou pinaka,
      //pol/se tis times gia red, green and blue tou pixel ths theshs, pou allazeis timh, me thn antistoixi thesi tou filtrou
        new_val_red += start[(width*3) * x + y] * filter[k][l] / 16.0;
        new_val_green += start[(width*3) * x + y + 1] * filter[k][l] / 16.0;
        new_val_blue += start[(width*3) * x + y + 2] * filter[k][l] / 16.0;
      }
      else { // an eisai entos twn diastasevn tou pinaka,
      //pol/se tis times gia red, green and blue tou pixel pou koitas me thn antistoixi thesi tou filtrou
        new_val_red += start[(width*3) * i + j] * filter[k][l] / 16.0;
        new_val_green += start[(width*3) * i + j + 1] * filter[k][l] / 16.0;
        new_val_blue += start[(width*3) * i + j + 2] * filter[k][l] / 16.0;
      }
    }
  }
  end[(width*3) * x + (y*3)] = new_val_red;
  end[(width*3) * x + (y*3) + 1] = new_val_green;
  end[(width*3) * x + (y*3) + 2] = new_val_blue;
}



extern "C" void filtering( uint8_t* table, int height, int width, int loops, char* type, int blocksize)
{
  uint8_t* start, * end, * temp;
  size_t bytes;

  if(strcmp(type, "GREY") == 0) bytes = height * width;
  else bytes = height * width * 3;

  // desmeuse xoro gia kathe vector sthn GPU
  hipMalloc( &start, bytes*sizeof(uint8_t) );
  hipMalloc( &end, bytes*sizeof(uint8_t) );

  // antegrapse ta host vectors sthn mnhmh ths suskeuhs
  hipMemcpy( start, table, bytes, hipMemcpyHostToDevice );
  hipMemset( end, 0, bytes );

  int i;

  for(i=0; i<loops; i++) // gia osa loops zhththikan
  {
    if(strcmp(type, "GREY") == 0) // an einai GREY
    {
      int gridX, gridY;
      gridX = (height + blocksize - 1) / blocksize;
      gridY = (width + blocksize - 1) / blocksize;
      dim3 dimBlock(blocksize, blocksize);
      dim3 dimGrid(gridX, gridY);
      kernel_grey<<<dimGrid, dimBlock>>>(start, end, height, width);
    }
    else  // an einai RGB
    {
      int gridX, gridY;
      gridX = (height + blocksize - 1) / blocksize;
      gridY = ((width * 3) + blocksize - 1) / blocksize;
      dim3 dimBlock(blocksize, blocksize);
      dim3 dimGrid(gridX, gridY);
      kernel_rgb<<<dimGrid, dimBlock>>>(start, end, height, width);
    }

    // antimetathese tous pinakes
    temp = start;
    start = end;
    end = temp;
  }

  hipGetLastError();
  hipDeviceSynchronize();


  // antegrapse thn telikh eikona ston host
  if(loops%2 == 0)
  {
    hipMemcpy( table, start, bytes, hipMemcpyDeviceToHost );
  }
  else
  {
    hipMemcpy( table, end, bytes, hipMemcpyDeviceToHost );
  }

  // apeleutherwse thn mnhmh ths suskeuhs
  hipFree(start);
  hipFree(end);
}

	.text
	.file	"cuda_functions.hip"
	.globl	_Z26__device_stub__kernel_greyPhS_ii # -- Begin function _Z26__device_stub__kernel_greyPhS_ii
	.type	_Z26__device_stub__kernel_greyPhS_ii,@function
_Z26__device_stub__kernel_greyPhS_ii:   # @_Z26__device_stub__kernel_greyPhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11kernel_greyPhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__kernel_greyPhS_ii, .Lfunc_end0-_Z26__device_stub__kernel_greyPhS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__kernel_rgbPhS_ii # -- Begin function _Z25__device_stub__kernel_rgbPhS_ii
	.type	_Z25__device_stub__kernel_rgbPhS_ii,@function
_Z25__device_stub__kernel_rgbPhS_ii:    # @_Z25__device_stub__kernel_rgbPhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10kernel_rgbPhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__kernel_rgbPhS_ii, .Lfunc_end1-_Z25__device_stub__kernel_rgbPhS_ii
	.cfi_endproc
                                        # -- End function
	.globl	filtering                       # -- Begin function filtering
	.type	filtering,@function
filtering:                              # @filtering
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movq	%r8, %r15
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movl	%edx, %r12d
	movl	%esi, %r13d
	movq	%rdi, %rbx
	movl	$.L.str, %esi
	movq	%r8, %rdi
	callq	strcmp
	movq	%r12, 40(%rsp)                  # 8-byte Spill
	movl	%r12d, %ecx
	movq	%r13, 32(%rsp)                  # 8-byte Spill
	imull	%r13d, %ecx
	testl	%eax, %eax
	leal	(%rcx,%rcx,2), %eax
	cmovel	%ecx, %eax
	movslq	%eax, %r12
	leaq	24(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%rbx, 64(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	movq	%r12, 56(%rsp)                  # 8-byte Spill
	movq	%r12, %rdx
	callq	hipMemset
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	jle	.LBB2_8
# %bb.1:                                # %.lr.ph
	movq	32(%rsp), %rax                  # 8-byte Reload
	addl	%r14d, %eax
	decl	%eax
	movq	40(%rsp), %rdx                  # 8-byte Reload
	leal	(%rdx,%rdx,2), %ecx
	leal	(%r14,%rcx), %ebx
	decl	%ebx
	movl	%r14d, %ecx
	movq	%rcx, %rbp
	shlq	$32, %rbp
	orq	%rcx, %rbp
	leal	(%r14,%rdx), %ecx
	decl	%ecx
	movl	%ecx, 52(%rsp)                  # 4-byte Spill
	cltd
	idivl	%r14d
	movl	%eax, %r12d
	movl	12(%rsp), %r13d                 # 4-byte Reload
.LBB2_2:                                # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %esi
	movq	%r15, %rdi
	callq	strcmp
	testl	%eax, %eax
	je	.LBB2_3
# %bb.5:                                #   in Loop: Header=BB2_2 Depth=1
	movl	%ebx, %eax
	cltd
	idivl	%r14d
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rax
	leaq	(%rax,%r12), %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:                                #   in Loop: Header=BB2_2 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movq	40(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z25__device_stub__kernel_rgbPhS_ii
	jmp	.LBB2_7
.LBB2_3:                                #   in Loop: Header=BB2_2 Depth=1
	movl	52(%rsp), %eax                  # 4-byte Reload
	cltd
	idivl	%r14d
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rax
	leaq	(%rax,%r12), %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.4:                                #   in Loop: Header=BB2_2 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movq	40(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z26__device_stub__kernel_greyPhS_ii
.LBB2_7:                                #   in Loop: Header=BB2_2 Depth=1
	movq	24(%rsp), %rax
	movq	16(%rsp), %rcx
	movq	%rcx, 24(%rsp)
	movq	%rax, 16(%rsp)
	decl	%r13d
	jne	.LBB2_2
.LBB2_8:                                # %._crit_edge
	callq	hipGetLastError
	callq	hipDeviceSynchronize
	testb	$1, 12(%rsp)                    # 1-byte Folded Reload
	leaq	24(%rsp), %rax
	leaq	16(%rsp), %rcx
	cmoveq	%rax, %rcx
	movq	(%rcx), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	filtering, .Lfunc_end2-filtering
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11kernel_greyPhS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10kernel_rgbPhS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11kernel_greyPhS_ii,@object   # @_Z11kernel_greyPhS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z11kernel_greyPhS_ii
	.p2align	3, 0x0
_Z11kernel_greyPhS_ii:
	.quad	_Z26__device_stub__kernel_greyPhS_ii
	.size	_Z11kernel_greyPhS_ii, 8

	.type	_Z10kernel_rgbPhS_ii,@object    # @_Z10kernel_rgbPhS_ii
	.globl	_Z10kernel_rgbPhS_ii
	.p2align	3, 0x0
_Z10kernel_rgbPhS_ii:
	.quad	_Z25__device_stub__kernel_rgbPhS_ii
	.size	_Z10kernel_rgbPhS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"GREY"
	.size	.L.str, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11kernel_greyPhS_ii"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10kernel_rgbPhS_ii"
	.size	.L__unnamed_2, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__kernel_greyPhS_ii
	.addrsig_sym _Z25__device_stub__kernel_rgbPhS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11kernel_greyPhS_ii
	.addrsig_sym _Z10kernel_rgbPhS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11kernel_greyPhS_ii   ; -- Begin function _Z11kernel_greyPhS_ii
	.globl	_Z11kernel_greyPhS_ii
	.p2align	8
	.type	_Z11kernel_greyPhS_ii,@function
_Z11kernel_greyPhS_ii:                  ; @_Z11kernel_greyPhS_ii
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x4
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v12, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	v_mov_b32_e32 v6, 4.0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v3, s1, v12
	s_mul_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s0, v1
	s_mov_b32 s0, 0
	v_add3_u32 v0, v2, v3, v0
	v_dual_mov_b32 v2, 1.0 :: v_dual_mov_b32 v3, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v0, 36
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v3
	v_mov_b32_e32 v9, v3
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v0, 24, v10
	ds_store_b128 v10, v[2:5]
	ds_store_b128 v10, v[6:9] offset:16
	ds_store_b32 v10, v2 offset:32
.LBB0_1:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_2addr_b32 v[4:5], v0 offset1:1
	ds_load_b32 v2, v0 offset:8
	v_add_nc_u32_e32 v0, -12, v0
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 36
	s_waitcnt lgkmcnt(1)
	v_mov_b32_e32 v3, v5
	s_waitcnt lgkmcnt(0)
	scratch_store_b96 off, v[2:4], s1
	s_cbranch_scc1 .LBB0_1
; %bb.2:
	s_clause 0x2
	s_load_b32 s0, s[2:3], 0x24
	s_load_b128 s[4:7], s[2:3], 0x0
	s_load_b64 s[8:9], s[2:3], 0x10
	s_mov_b32 s10, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s0, 0xffff
	s_lshr_b32 s0, s0, 16
	v_mad_u64_u32 v[6:7], null, s14, s1, v[1:2]
	s_mul_i32 s15, s15, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v14, 0 :: v_dual_add_nc_u32 v13, s15, v12
                                        ; implicit-def: $vgpr0_vgpr1
	v_add_nc_u32_e32 v2, -1, v6
	v_add_co_u32 v4, s1, v6, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v5, null, 0, 0, s1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u64_e32 vcc_lo, v[4:5], v[2:3]
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.3:                                ; %.lr.ph65
	v_mad_u64_u32 v[0:1], null, v6, s9, 0
	s_ashr_i32 s0, s9, 31
	v_mul_lo_u32 v3, s9, v2
	s_sub_i32 s11, s15, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v6, s0, v[1:2]
	v_add_nc_u32_e32 v8, -1, v13
	v_add_co_u32 v6, s0, v13, 1
	v_add_co_ci_u32_e64 v7, null, 0, 0, s0
	v_add_co_u32 v11, s0, s4, v13
	v_mov_b32_e32 v1, v10
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e64 v16, null, s5, 0, s0
	v_add3_u32 v15, v12, v3, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_add_co_u32 v8, s0, v11, v0
	v_add_co_ci_u32_e64 v9, s0, v16, v1, s0
	v_mov_b32_e32 v16, 16
.LBB0_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_cmp_eq_u32_e64 s1, s8, v2
	v_cmp_eq_u32_e64 s13, -1, v2
	v_cmp_ne_u32_e64 s0, -1, v2
	v_mov_b32_e32 v3, v16
	v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v18, v12
	s_mov_b32 s14, 0
	s_xor_b32 s16, s1, -1
.LBB0_6:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v10, s15, v18
	s_mov_b32 s1, s13
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=2
	v_add_nc_u32_e32 v11, s11, v18
	v_cmp_ne_u32_e64 s1, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s2, 1, v11
	s_and_b32 s18, s16, s1
	s_mov_b32 s1, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s18, s2, s18
	s_and_saveexec_b32 s2, s18
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=2
	v_add_nc_u32_e32 v11, s15, v17
	v_cvt_f64_f32_e32 v[21:22], v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 31, v11
	v_add_co_u32 v19, s1, s4, v11
	v_add_co_ci_u32_e64 v20, s1, s5, v20, s1
	s_xor_b32 s1, exec_lo, -1
	global_load_u8 v11, v[19:20], off
	scratch_load_b32 v19, v3, off
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v11, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v19, v11
	v_cvt_f64_f32_e32 v[19:20], v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], 0x3fb00000, v[19:20], v[21:22]
	v_cvt_f32_f64_e32 v14, v[19:20]
.LBB0_9:                                ; %Flow102
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s13, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s1, s2, s1
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_6 Depth=2
	global_load_u8 v11, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v14, v11
.LBB0_12:                               ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_nc_u32_e32 v18, 1, v18
	v_add_nc_u32_e32 v17, 1, v17
	v_add_nc_u32_e32 v3, 4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s1, v[6:7], v[10:11]
	s_or_b32 s14, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_6
; %bb.13:                               ; %Flow103
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_14:                               ; %Flow104
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v2, 1, v2
	v_add_nc_u32_e32 v15, s9, v15
	v_add_nc_u32_e32 v16, 12, v16
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, v[4:5], v[2:3]
	s_or_b32 s10, s0, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_4
; %bb.15:                               ; %._crit_edge66.loopexit
	s_or_b32 exec_lo, exec_lo, s10
	v_cvt_i32_f32_e32 v3, v14
                                        ; implicit-def: $vgpr6_vgpr7
.LBB0_16:                               ; %Flow105
	s_and_not1_saveexec_b32 s0, s3
; %bb.17:                               ; %.._crit_edge66_crit_edge
	v_mad_u64_u32 v[0:1], null, v6, s9, 0
	s_ashr_i32 s1, s9, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, v6, s1, v[1:2]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v1, v2
; %bb.18:                               ; %._crit_edge66
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v13
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	global_store_b8 v[0:1], v3, off
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11kernel_greyPhS_ii
		.amdhsa_group_segment_fixed_size 36864
		.amdhsa_private_segment_fixed_size 64
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11kernel_greyPhS_ii, .Lfunc_end0-_Z11kernel_greyPhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 21
; NumVgprs: 23
; ScratchSize: 64
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 36864 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z10kernel_rgbPhS_ii    ; -- Begin function _Z10kernel_rgbPhS_ii
	.globl	_Z10kernel_rgbPhS_ii
	.p2align	8
	.type	_Z10kernel_rgbPhS_ii,@function
_Z10kernel_rgbPhS_ii:                   ; @_Z10kernel_rgbPhS_ii
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x4
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	v_mov_b32_e32 v7, 4.0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v4, s1, v1
	s_mul_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s0, v2
	s_mov_b32 s0, 0
	v_add3_u32 v0, v3, v4, v0
	v_dual_mov_b32 v3, 1.0 :: v_dual_mov_b32 v4, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v0, 36
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, v4
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v9, v3
	v_mov_b32_e32 v10, v4
	ds_store_b128 v11, v[3:6]
	ds_store_b128 v11, v[7:10] offset:16
	v_add_nc_u32_e32 v0, 24, v11
	ds_store_b32 v11, v3 offset:32
.LBB1_1:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_2addr_b32 v[5:6], v0 offset1:1
	ds_load_b32 v3, v0 offset:8
	v_add_nc_u32_e32 v0, -12, v0
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 36
	s_waitcnt lgkmcnt(1)
	v_mov_b32_e32 v4, v6
	s_waitcnt lgkmcnt(0)
	scratch_store_b96 off, v[3:5], s1
	s_cbranch_scc1 .LBB1_1
; %bb.2:
	s_clause 0x2
	s_load_b32 s0, s[2:3], 0x24
	s_load_b64 s[8:9], s[2:3], 0x10
	s_load_b128 s[4:7], s[2:3], 0x0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s10, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s9, 3
	s_and_b32 s1, s0, 0xffff
	s_lshr_b32 s0, s0, 16
	v_mad_u64_u32 v[8:9], null, s14, s1, v[2:3]
	v_mad_u64_u32 v[9:10], null, s15, s0, v[1:2]
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, -1, v8
	v_add_co_u32 v6, s1, v8, 1
	v_add_co_ci_u32_e64 v7, null, 0, 0, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_ge_u64_e32 vcc_lo, v[6:7], v[4:5]
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s0
	s_cbranch_execz .LBB1_14
; %bb.3:                                ; %.lr.ph116
	v_mad_u64_u32 v[0:1], null, v8, s3, 0
	v_mad_u64_u32 v[2:3], null, v9, 3, 0
	v_add_co_u32 v5, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v16, null, s5, 0, s0
	s_ashr_i32 s0, s3, 31
	v_mov_b32_e32 v21, 16
	v_mad_u64_u32 v[14:15], null, v8, s0, v[1:2]
	v_add_nc_u32_e32 v12, -3, v2
	v_add_co_u32 v8, vcc_lo, v2, 3
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_dual_mov_b32 v1, v14 :: v_dual_mov_b32 v22, 0
	v_mad_u64_u32 v[10:11], null, s3, v4, -3
	v_add_co_u32 v11, s0, v5, v0
	v_cmp_ge_u64_e32 vcc_lo, v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e64 v12, s0, v16, v1, s0
	v_mov_b32_e32 v15, 0
	s_add_i32 s11, s3, 3
.LBB1_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB1_12
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_4 Depth=1
	v_cmp_eq_u32_e64 s0, -1, v4
	v_cmp_eq_u32_e64 s1, s8, v4
	v_mov_b32_e32 v5, v21
	v_mov_b32_e32 v13, v2
	s_mov_b32 s13, 0
.LBB1_6:                                ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_cvt_f64_f32_e32 v[16:17], v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, 0, v13
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr23
	s_or_b32 s14, s1, s2
	v_cmp_ne_u32_e64 s2, s11, v13
	s_or_b32 s14, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, s14, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s14, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s2
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=2
	v_add_nc_u32_e32 v14, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_u32 v18, s2, s4, v14
	v_add_co_ci_u32_e64 v19, s2, s5, v15, s2
	global_load_u8 v14, v[18:19], off
	scratch_load_b32 v23, v5, off
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v14, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v23, v14
	v_cvt_f64_f32_e32 v[14:15], v14
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], 0x3fb00000, v[14:15], v[16:17]
                                        ; implicit-def: $vgpr16_vgpr17
.LBB1_8:                                ; %Flow
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_and_not1_saveexec_b32 s2, s14
	s_cbranch_execz .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_6 Depth=2
	global_load_u8 v14, v[11:12], off
	scratch_load_b32 v23, v5, off
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v18, v11
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v14, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v23, v14
	v_cvt_f64_f32_e32 v[14:15], v14
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], 0x3fb00000, v[14:15], v[16:17]
.LBB1_10:                               ;   in Loop: Header=BB1_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	global_load_u16 v16, v[18:19], off offset:1
	v_cvt_f64_f32_e32 v[18:19], v22
	v_cvt_f32_f64_e32 v15, v[14:15]
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_nc_u32_e32 v5, 4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_u64_e64 s2, v[8:9], v[13:14]
	v_add_nc_u32_e32 v13, 3, v13
	s_or_b32 s13, s2, s13
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v17, v16
	v_cvt_f32_ubyte1_e32 v16, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, v23, v17
	v_mul_f32_e32 v25, v23, v16
	v_cvt_f64_f32_e32 v[16:17], v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[22:23], v24
	v_cvt_f64_f32_e32 v[24:25], v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], 0x3fb00000, v[22:23], v[16:17]
	v_fma_f64 v[18:19], 0x3fb00000, v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v20, v[16:17]
	v_cvt_f32_f64_e32 v22, v[18:19]
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_6
; %bb.11:                               ; %Flow170
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_12:                               ; %Flow171
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v10, s3, v10
	v_add_nc_u32_e32 v21, 12, v21
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, v[6:7], v[4:5]
	s_or_b32 s10, s0, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_4
; %bb.13:                               ; %._crit_edge117.loopexit
	s_or_b32 exec_lo, exec_lo, s10
	v_cvt_i32_f32_e32 v5, v15
	v_cvt_i32_f32_e32 v12, v20
	v_cvt_i32_f32_e32 v11, v22
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr9_vgpr10
.LBB1_14:                               ; %Flow172
	s_and_not1_saveexec_b32 s0, s9
; %bb.15:                               ; %.._crit_edge117_crit_edge
	v_mad_u64_u32 v[0:1], null, v8, s3, 0
	s_ashr_i32 s1, s3, 31
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v8, s1, v[1:2]
	v_mad_u64_u32 v[2:3], null, v9, 3, 0
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v1, v4
; %bb.16:                               ; %._crit_edge117
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_lshlrev_b16 v4, 8, v12
	v_and_b32_e32 v5, 0xff, v5
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_or_b32_e32 v2, v5, v4
	s_clause 0x1
	global_store_b8 v[0:1], v11, off offset:2
	global_store_b16 v[0:1], v2, off
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10kernel_rgbPhS_ii
		.amdhsa_group_segment_fixed_size 36864
		.amdhsa_private_segment_fixed_size 64
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10kernel_rgbPhS_ii, .Lfunc_end1-_Z10kernel_rgbPhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1048
; NumSgprs: 18
; NumVgprs: 26
; ScratchSize: 64
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 36864 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 36864
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11kernel_greyPhS_ii
    .private_segment_fixed_size: 64
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z11kernel_greyPhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 36864
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10kernel_rgbPhS_ii
    .private_segment_fixed_size: 64
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10kernel_rgbPhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
