__device__ void saxpy( float a, float *b, float *c )
{
	c[0] += a*b[0];
	c[1] += a*b[1];
	c[2] += a*b[2];
	c[3] += a*b[3];
	c[4] += a*b[4];
	c[5] += a*b[5];
	c[6] += a*b[6];
	c[7] += a*b[7];
	c[8] += a*b[8];
	c[9] += a*b[9];
	c[10] += a*b[10];
	c[11] += a*b[11];
	c[12] += a*b[12];
	c[13] += a*b[13];
	c[14] += a*b[14];
	c[15] += a*b[15];
}

extern "C" __global__ void sgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
	const int inx = threadIdx.x;
	const int iny = threadIdx.y;
	const int ibx = blockIdx.x * 64;
	const int iby = blockIdx.y * 16;
	const int id  = inx + iny*16;

	A += ibx + id;
	B += iby + inx + __mul24( iny, ldb );
	C += ibx + id  + __mul24( iby, ldc );
	
	float a[4] = {A[0], A[lda], A[2*lda], A[3*lda]};
	float b = B[0];
	
	const float *Blast = B + k*ldb;

	A += 4*lda;
	B += 4*ldb;
    
	__shared__ float bs[4][16];
	float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
    
	do
	{
		float as[4] = {a[0], a[1], a[2], a[3]};
		
		bs[iny][inx] = b;
		__syncthreads();
		
		a[0] = A[0*lda];
		a[1] = A[1*lda];
		a[2] = A[2*lda];
		a[3] = A[3*lda];
		b    = B[0];
		
		saxpy( as[0], &bs[0][0], c );
		saxpy( as[1], &bs[1][0], c );
		saxpy( as[2], &bs[2][0], c );
		saxpy( as[3], &bs[3][0], c );
		
		A += 4*lda;
		B += 4*ldb;
		__syncthreads();
		
	} while( B < Blast );
	
	bs[iny][inx] = b;
	__syncthreads();
	
	saxpy( a[0], &bs[0][0], c );
	saxpy( a[1], &bs[1][0], c );
	saxpy( a[2], &bs[2][0], c );
	saxpy( a[3], &bs[3][0], c );

	for( int i = 0; i < 16; i++, C += ldc )
		C[0] = alpha*c[i] + beta*C[0];
}	

extern "C" __global__ void sgemmNN( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
	const int inx = threadIdx.x;
	const int iny = threadIdx.y;
	const int ibx = blockIdx.x * 64;
	const int iby = blockIdx.y * 16;
	const int id = inx + iny*16;
	
	A += ibx + id;
	B += inx + __mul24( iby + iny, ldb );
	C += ibx + id  + __mul24( iby, ldc );
	
	const float *Blast = B + k;
	
	float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
    
	do
	{
		float a[4] = { A[0*lda], A[1*lda], A[2*lda], A[3*lda] };

		__shared__ float bs[16][17];
		bs[inx][iny]    = B[0*ldb];
		bs[inx][iny+4]  = B[4*ldb];
		bs[inx][iny+8]  = B[8*ldb];
		bs[inx][iny+12] = B[12*ldb];
		__syncthreads();

		A += 4*lda;
		saxpy( a[0], &bs[0][0], c );		a[0] = A[0*lda];
		saxpy( a[1], &bs[1][0], c );		a[1] = A[1*lda];
		saxpy( a[2], &bs[2][0], c );		a[2] = A[2*lda];
		saxpy( a[3], &bs[3][0], c );		a[3] = A[3*lda];

		A += 4*lda;
		saxpy( a[0], &bs[4][0], c );		a[0] = A[0*lda];
		saxpy( a[1], &bs[5][0], c );		a[1] = A[1*lda];
		saxpy( a[2], &bs[6][0], c );		a[2] = A[2*lda];
		saxpy( a[3], &bs[7][0], c );		a[3] = A[3*lda];

		A += 4*lda;
		saxpy( a[0], &bs[8][0], c );		a[0] = A[0*lda];
		saxpy( a[1], &bs[9][0], c );		a[1] = A[1*lda];
		saxpy( a[2], &bs[10][0], c );		a[2] = A[2*lda];
		saxpy( a[3], &bs[11][0], c );		a[3] = A[3*lda];

		A += 4*lda;
		saxpy( a[0], &bs[12][0], c );
		saxpy( a[1], &bs[13][0], c );
		saxpy( a[2], &bs[14][0], c );
		saxpy( a[3], &bs[15][0], c );
		
		B += 16;
		__syncthreads();
	} while( B < Blast );
	
	for( int i = 0; i < 16; i++, C += ldc )
                C[0] = alpha*c[i] + beta*C[0];
}	

	.file	"tmpxft_002454e9_00000000-6_sgemmN.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5saxpyfPfS_
	.type	_Z5saxpyfPfS_, @function
_Z5saxpyfPfS_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z5saxpyfPfS_, .-_Z5saxpyfPfS_
	.globl	_Z38__device_stub__Z7sgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
	.type	_Z38__device_stub__Z7sgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff, @function
_Z38__device_stub__Z7sgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	sgemmNT(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z38__device_stub__Z7sgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff, .-_Z38__device_stub__Z7sgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
	.globl	sgemmNT
	.type	sgemmNT, @function
sgemmNT:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z7sgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
	.cfi_endproc
.LFE2034:
	.size	sgemmNT, .-sgemmNT
	.globl	_Z38__device_stub__Z7sgemmNNPKfiS0_iPfiiffPKfiS0_iPfiiff
	.type	_Z38__device_stub__Z7sgemmNNPKfiS0_iPfiiffPKfiS0_iPfiiff, @function
_Z38__device_stub__Z7sgemmNNPKfiS0_iPfiiffPKfiS0_iPfiiff:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	sgemmNN(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L10:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z38__device_stub__Z7sgemmNNPKfiS0_iPfiiffPKfiS0_iPfiiff, .-_Z38__device_stub__Z7sgemmNNPKfiS0_iPfiiffPKfiS0_iPfiiff
	.globl	sgemmNN
	.type	sgemmNN, @function
sgemmNN:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z7sgemmNNPKfiS0_iPfiiffPKfiS0_iPfiiff
	.cfi_endproc
.LFE2036:
	.size	sgemmNN, .-sgemmNN
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"sgemmNN"
.LC1:
	.string	"sgemmNT"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	sgemmNN(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	sgemmNT(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__ void saxpy( float a, float *b, float *c )
{
	c[0] += a*b[0];
	c[1] += a*b[1];
	c[2] += a*b[2];
	c[3] += a*b[3];
	c[4] += a*b[4];
	c[5] += a*b[5];
	c[6] += a*b[6];
	c[7] += a*b[7];
	c[8] += a*b[8];
	c[9] += a*b[9];
	c[10] += a*b[10];
	c[11] += a*b[11];
	c[12] += a*b[12];
	c[13] += a*b[13];
	c[14] += a*b[14];
	c[15] += a*b[15];
}

extern "C" __global__ void sgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
	const int inx = threadIdx.x;
	const int iny = threadIdx.y;
	const int ibx = blockIdx.x * 64;
	const int iby = blockIdx.y * 16;
	const int id  = inx + iny*16;

	A += ibx + id;
	B += iby + inx + __mul24( iny, ldb );
	C += ibx + id  + __mul24( iby, ldc );
	
	float a[4] = {A[0], A[lda], A[2*lda], A[3*lda]};
	float b = B[0];
	
	const float *Blast = B + k*ldb;

	A += 4*lda;
	B += 4*ldb;
    
	__shared__ float bs[4][16];
	float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
    
	do
	{
		float as[4] = {a[0], a[1], a[2], a[3]};
		
		bs[iny][inx] = b;
		__syncthreads();
		
		a[0] = A[0*lda];
		a[1] = A[1*lda];
		a[2] = A[2*lda];
		a[3] = A[3*lda];
		b    = B[0];
		
		saxpy( as[0], &bs[0][0], c );
		saxpy( as[1], &bs[1][0], c );
		saxpy( as[2], &bs[2][0], c );
		saxpy( as[3], &bs[3][0], c );
		
		A += 4*lda;
		B += 4*ldb;
		__syncthreads();
		
	} while( B < Blast );
	
	bs[iny][inx] = b;
	__syncthreads();
	
	saxpy( a[0], &bs[0][0], c );
	saxpy( a[1], &bs[1][0], c );
	saxpy( a[2], &bs[2][0], c );
	saxpy( a[3], &bs[3][0], c );

	for( int i = 0; i < 16; i++, C += ldc )
		C[0] = alpha*c[i] + beta*C[0];
}	

extern "C" __global__ void sgemmNN( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
	const int inx = threadIdx.x;
	const int iny = threadIdx.y;
	const int ibx = blockIdx.x * 64;
	const int iby = blockIdx.y * 16;
	const int id = inx + iny*16;
	
	A += ibx + id;
	B += inx + __mul24( iby + iny, ldb );
	C += ibx + id  + __mul24( iby, ldc );
	
	const float *Blast = B + k;
	
	float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
    
	do
	{
		float a[4] = { A[0*lda], A[1*lda], A[2*lda], A[3*lda] };

		__shared__ float bs[16][17];
		bs[inx][iny]    = B[0*ldb];
		bs[inx][iny+4]  = B[4*ldb];
		bs[inx][iny+8]  = B[8*ldb];
		bs[inx][iny+12] = B[12*ldb];
		__syncthreads();

		A += 4*lda;
		saxpy( a[0], &bs[0][0], c );		a[0] = A[0*lda];
		saxpy( a[1], &bs[1][0], c );		a[1] = A[1*lda];
		saxpy( a[2], &bs[2][0], c );		a[2] = A[2*lda];
		saxpy( a[3], &bs[3][0], c );		a[3] = A[3*lda];

		A += 4*lda;
		saxpy( a[0], &bs[4][0], c );		a[0] = A[0*lda];
		saxpy( a[1], &bs[5][0], c );		a[1] = A[1*lda];
		saxpy( a[2], &bs[6][0], c );		a[2] = A[2*lda];
		saxpy( a[3], &bs[7][0], c );		a[3] = A[3*lda];

		A += 4*lda;
		saxpy( a[0], &bs[8][0], c );		a[0] = A[0*lda];
		saxpy( a[1], &bs[9][0], c );		a[1] = A[1*lda];
		saxpy( a[2], &bs[10][0], c );		a[2] = A[2*lda];
		saxpy( a[3], &bs[11][0], c );		a[3] = A[3*lda];

		A += 4*lda;
		saxpy( a[0], &bs[12][0], c );
		saxpy( a[1], &bs[13][0], c );
		saxpy( a[2], &bs[14][0], c );
		saxpy( a[3], &bs[15][0], c );
		
		B += 16;
		__syncthreads();
	} while( B < Blast );
	
	for( int i = 0; i < 16; i++, C += ldc )
                C[0] = alpha*c[i] + beta*C[0];
}	

	.text
	.file	"sgemmN.hip"
	.globl	__device_stub__sgemmNT          # -- Begin function __device_stub__sgemmNT
	.type	__device_stub__sgemmNT,@function
__device_stub__sgemmNT:                 # @__device_stub__sgemmNT
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	movq	%r10, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sgemmNT, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__sgemmNT, .Lfunc_end0-__device_stub__sgemmNT
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__sgemmNN          # -- Begin function __device_stub__sgemmNN
	.type	__device_stub__sgemmNN,@function
__device_stub__sgemmNN:                 # @__device_stub__sgemmNN
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	movq	%r10, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sgemmNN, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__sgemmNN, .Lfunc_end1-__device_stub__sgemmNN
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sgemmNT, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sgemmNN, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	sgemmNT,@object                 # @sgemmNT
	.section	.rodata,"a",@progbits
	.globl	sgemmNT
	.p2align	3, 0x0
sgemmNT:
	.quad	__device_stub__sgemmNT
	.size	sgemmNT, 8

	.type	sgemmNN,@object                 # @sgemmNN
	.globl	sgemmNN
	.p2align	3, 0x0
sgemmNN:
	.quad	__device_stub__sgemmNN
	.size	sgemmNN, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"sgemmNT"
	.size	.L__unnamed_1, 8

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"sgemmNN"
	.size	.L__unnamed_2, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__sgemmNT
	.addrsig_sym __device_stub__sgemmNN
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym sgemmNT
	.addrsig_sym sgemmNN
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	sgemmNT                 ; -- Begin function sgemmNT
	.globl	sgemmNT
	.p2align	8
	.type	sgemmNT,@function
sgemmNT:                                ; @sgemmNT
; %bb.0:
	v_bfe_u32 v15, v0, 10, 10
	s_clause 0x1
	s_load_b32 s16, s[0:1], 0x8
	s_load_b32 s12, s[0:1], 0x18
	v_dual_mov_b32 v35, 0 :: v_dual_and_b32 v0, 0x3ff, v0
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_lshlrev_b32_e32 v1, 4, v15
	s_lshl_b32 s4, s14, 6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v16, v1, v0, s4
	s_lshl_b32 s4, s15, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s17, s16, 31
	v_lshlrev_b64 v[1:2], 2, v[16:17]
	v_mul_i32_i24_e32 v5, s12, v15
	s_lshl_b64 s[18:19], s[16:17], 2
	s_lshl_b32 s20, s16, 2
	s_lshl_b64 s[22:23], s[16:17], 3
	s_ashr_i32 s21, s20, 31
	v_add_co_u32 v3, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
	v_add3_u32 v5, s4, v0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v3, s18
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_u32 v9, vcc_lo, v7, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v8, vcc_lo
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v9, s18
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v10, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v6, vcc_lo
	s_clause 0x3
	global_load_b32 v25, v[3:4], off
	global_load_b32 v24, v[7:8], off
	global_load_b32 v23, v[9:10], off
	global_load_b32 v22, v[11:12], off
	global_load_b32 v27, v[13:14], off
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v26, v15, 6, v0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v7, v0
	v_mov_b32_e32 v8, v0
	v_mov_b32_e32 v9, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s10, s5, s12
	v_mov_b32_e32 v10, v0
	s_ashr_i32 s11, s10, 31
	v_mov_b32_e32 v11, v0
	s_lshl_b64 s[10:11], s[10:11], 2
	v_mov_b32_e32 v12, v0
	v_add_co_u32 v18, vcc_lo, v13, s10
	s_lshl_b32 s10, s12, 2
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v14, vcc_lo
	s_ashr_i32 s11, s10, 31
	s_lshl_b64 s[12:13], s[20:21], 2
	s_lshl_b64 s[10:11], s[10:11], 2
	s_add_u32 s5, s22, s12
	v_add_co_u32 v28, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v29, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s20, v16
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v17, vcc_lo
	v_add_co_u32 v17, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_addc_u32 s14, s23, s13
	v_add_co_u32 v31, vcc_lo, s5, v1
	s_add_u32 s5, s18, s12
	v_add_co_ci_u32_e32 v32, vcc_lo, s14, v2, vcc_lo
	v_mad_i64_i32 v[20:21], null, s16, 12, v[3:4]
	s_addc_u32 s14, s19, s13
	v_add_co_u32 v33, vcc_lo, s5, v1
	v_add_co_ci_u32_e32 v34, vcc_lo, s14, v2, vcc_lo
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v3, v0
	v_mov_b32_e32 v4, v0
	v_mov_b32_e32 v5, v0
	v_mov_b32_e32 v6, v0
	v_mov_b32_e32 v13, v0
	v_mov_b32_e32 v14, v0
	v_mov_b32_e32 v15, v0
	s_mov_b32 s5, 0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v36, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v37, vcc_lo, s9, v29, vcc_lo
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v88, v22 :: v_dual_mov_b32 v89, v23
	v_add_co_u32 v22, vcc_lo, s2, v17
	v_add_co_ci_u32_e32 v23, vcc_lo, s3, v30, vcc_lo
	v_add_co_u32 v38, vcc_lo, s2, v33
	v_add_co_ci_u32_e32 v39, vcc_lo, s3, v34, vcc_lo
	v_add_co_u32 v40, vcc_lo, s2, v31
	v_add_co_ci_u32_e32 v41, vcc_lo, s3, v32, vcc_lo
	v_add_co_u32 v42, vcc_lo, s2, v20
	v_add_co_ci_u32_e32 v43, vcc_lo, s3, v21, vcc_lo
	v_dual_mov_b32 v90, v25 :: v_dual_mov_b32 v91, v24
	s_waitcnt vmcnt(0)
	ds_store_b32 v26, v27
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_clause 0x3
	global_load_b32 v25, v[22:23], off
	global_load_b32 v24, v[38:39], off
	global_load_b32 v23, v[40:41], off
	global_load_b32 v22, v[42:43], off
	global_load_b32 v27, v[36:37], off
	ds_load_b128 v[36:39], v35
	ds_load_b128 v[40:43], v35 offset:16
	ds_load_b128 v[44:47], v35 offset:32
	ds_load_b128 v[48:51], v35 offset:48
	ds_load_b128 v[52:55], v35 offset:64
	ds_load_b128 v[56:59], v35 offset:80
	ds_load_b128 v[60:63], v35 offset:96
	ds_load_b128 v[64:67], v35 offset:112
	ds_load_b128 v[68:71], v35 offset:128
	ds_load_b128 v[72:75], v35 offset:144
	ds_load_b128 v[76:79], v35 offset:160
	ds_load_b128 v[80:83], v35 offset:176
	s_add_u32 s8, s8, s10
	s_addc_u32 s9, s9, s11
	v_add_co_u32 v84, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v85, vcc_lo, s9, v29, vcc_lo
	s_add_u32 s2, s2, s12
	s_addc_u32 s3, s3, s13
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v1, v90, v37
	v_cmp_ge_u64_e32 vcc_lo, v[84:85], v[18:19]
	ds_load_b128 v[84:87], v35 offset:192
	v_fmac_f32_e32 v0, v90, v36
	v_fmac_f32_e32 v3, v90, v39
	v_fmac_f32_e32 v2, v90, v38
	ds_load_b128 v[36:39], v35 offset:208
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v5, v90, v41
	v_fmac_f32_e32 v4, v90, v40
	v_fmac_f32_e32 v7, v90, v43
	v_fmac_f32_e32 v6, v90, v42
	ds_load_b128 v[40:43], v35 offset:224
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v9, v90, v45
	v_fmac_f32_e32 v8, v90, v44
	v_fmac_f32_e32 v11, v90, v47
	v_fmac_f32_e32 v10, v90, v46
	ds_load_b128 v[44:47], v35 offset:240
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v13, v90, v49
	v_fmac_f32_e32 v12, v90, v48
	v_fmac_f32_e32 v15, v90, v51
	s_waitcnt lgkmcnt(11)
	v_dual_fmac_f32 v14, v90, v50 :: v_dual_fmac_f32 v1, v91, v53
	v_fmac_f32_e32 v0, v91, v52
	v_fmac_f32_e32 v3, v91, v55
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v15, v91, v67
	v_fmac_f32_e32 v2, v91, v54
	v_fmac_f32_e32 v5, v91, v57
	v_fmac_f32_e32 v4, v91, v56
	v_fmac_f32_e32 v7, v91, v59
	v_fmac_f32_e32 v6, v91, v58
	v_fmac_f32_e32 v9, v91, v61
	v_fmac_f32_e32 v8, v91, v60
	v_fmac_f32_e32 v11, v91, v63
	v_fmac_f32_e32 v10, v91, v62
	v_fmac_f32_e32 v13, v91, v65
	v_fmac_f32_e32 v12, v91, v64
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v14, v91, v66 :: v_dual_fmac_f32 v1, v89, v69
	v_fmac_f32_e32 v0, v89, v68
	v_fmac_f32_e32 v3, v89, v71
	v_fmac_f32_e32 v2, v89, v70
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v5, v89, v73
	v_fmac_f32_e32 v4, v89, v72
	v_fmac_f32_e32 v7, v89, v75
	v_fmac_f32_e32 v6, v89, v74
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v9, v89, v77
	v_fmac_f32_e32 v8, v89, v76
	v_fmac_f32_e32 v11, v89, v79
	v_fmac_f32_e32 v10, v89, v78
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v13, v89, v81
	v_fmac_f32_e32 v12, v89, v80
	v_fmac_f32_e32 v15, v89, v83
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v14, v89, v82 :: v_dual_fmac_f32 v1, v88, v85
	v_fmac_f32_e32 v0, v88, v84
	v_fmac_f32_e32 v3, v88, v87
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v88, v47
	v_fmac_f32_e32 v2, v88, v86
	v_fmac_f32_e32 v5, v88, v37
	v_fmac_f32_e32 v4, v88, v36
	v_fmac_f32_e32 v7, v88, v39
	v_fmac_f32_e32 v6, v88, v38
	v_fmac_f32_e32 v9, v88, v41
	v_fmac_f32_e32 v8, v88, v40
	v_fmac_f32_e32 v11, v88, v43
	v_fmac_f32_e32 v10, v88, v42
	v_fmac_f32_e32 v13, v88, v45
	v_fmac_f32_e32 v12, v88, v44
	v_fmac_f32_e32 v14, v88, v46
	s_or_b32 s5, vcc_lo, s5
	s_waitcnt vmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_1
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v46, 0
	ds_store_b32 v26, v27
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b128 v[18:21], v46
	ds_load_b128 v[26:29], v46 offset:16
	s_lshl_b32 s2, s15, 12
	s_bfe_i32 s3, s4, 0x180000
	s_ashr_i32 s2, s2, 8
	s_load_b64 s[0:1], s[0:1], 0x20
	v_mad_u64_u32 v[30:31], null, s3, s2, v[16:17]
	s_ashr_i32 s5, s4, 31
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v31, 31, v30
	v_lshlrev_b64 v[16:17], 2, v[30:31]
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v1, v25, v19
	ds_load_b128 v[30:33], v46 offset:32
	ds_load_b128 v[34:37], v46 offset:48
	ds_load_b128 v[38:41], v46 offset:64
	v_fmac_f32_e32 v0, v25, v18
	v_fmac_f32_e32 v3, v25, v21
	v_fmac_f32_e32 v2, v25, v20
	ds_load_b128 v[18:21], v46 offset:80
	ds_load_b128 v[42:45], v46 offset:224
	v_add_co_u32 v16, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	s_lshl_b64 s[0:1], s[4:5], 2
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v1, v24, v39
	v_fmac_f32_e32 v0, v24, v38
	v_fmac_f32_e32 v3, v24, v41
	v_dual_fmac_f32 v5, v25, v27 :: v_dual_fmac_f32 v2, v24, v40
	v_fmac_f32_e32 v4, v25, v26
	ds_load_b128 v[38:41], v46 offset:144
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v5, v24, v19
	v_dual_fmac_f32 v7, v25, v29 :: v_dual_fmac_f32 v4, v24, v18
	v_fmac_f32_e32 v6, v25, v28
	ds_load_b128 v[26:29], v46 offset:96
	v_fmac_f32_e32 v7, v24, v21
	v_dual_fmac_f32 v9, v25, v31 :: v_dual_fmac_f32 v6, v24, v20
	v_fmac_f32_e32 v8, v25, v30
	v_fmac_f32_e32 v11, v25, v33
	v_fmac_f32_e32 v10, v25, v32
	ds_load_b128 v[30:33], v46 offset:112
	ds_load_b128 v[18:21], v46 offset:160
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v9, v24, v27
	v_fmac_f32_e32 v8, v24, v26
	v_fmac_f32_e32 v11, v24, v29
	v_dual_fmac_f32 v13, v25, v35 :: v_dual_fmac_f32 v10, v24, v28
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v25, v34 :: v_dual_fmac_f32 v13, v24, v31
	v_dual_fmac_f32 v15, v25, v37 :: v_dual_fmac_f32 v12, v24, v30
	v_fmac_f32_e32 v14, v25, v36
	ds_load_b128 v[34:37], v46 offset:128
	ds_load_b128 v[25:28], v46 offset:176
	v_fmac_f32_e32 v15, v24, v33
	v_fmac_f32_e32 v14, v24, v32
	ds_load_b128 v[29:32], v46 offset:192
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v1, v23, v35
	v_fmac_f32_e32 v2, v23, v36
	v_fmac_f32_e32 v3, v23, v37
	v_fmac_f32_e32 v0, v23, v34
	ds_load_b128 v[33:36], v46 offset:208
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v1, v22, v30
	v_fmac_f32_e32 v2, v22, v31
	v_fmac_f32_e32 v3, v22, v32
	v_dual_fmac_f32 v5, v23, v39 :: v_dual_fmac_f32 v0, v22, v29
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, v23, v40 :: v_dual_fmac_f32 v5, v22, v34
	v_dual_fmac_f32 v7, v23, v41 :: v_dual_fmac_f32 v6, v22, v35
	v_fmac_f32_e32 v4, v23, v38
	ds_load_b128 v[37:40], v46 offset:240
	v_fmac_f32_e32 v7, v22, v36
	v_dual_fmac_f32 v9, v23, v19 :: v_dual_fmac_f32 v4, v22, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, v23, v18 :: v_dual_fmac_f32 v9, v22, v43
	v_dual_fmac_f32 v11, v23, v21 :: v_dual_fmac_f32 v8, v22, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v23, v20 :: v_dual_fmac_f32 v11, v22, v45
	v_dual_fmac_f32 v13, v23, v26 :: v_dual_fmac_f32 v10, v22, v44
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v23, v25 :: v_dual_fmac_f32 v13, v22, v38
	v_dual_fmac_f32 v15, v23, v28 :: v_dual_fmac_f32 v12, v22, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v14, v23, v27 :: v_dual_fmac_f32 v15, v22, v40
	v_fmac_f32_e32 v14, v22, v39
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v18, v[16:17], off
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	v_movrels_b32_e32 v19, v0
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 16
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v18, s7, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v18, s6, v19
	global_store_b32 v[16:17], v18, off
	v_add_co_u32 v16, vcc_lo, v16, s0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	s_cbranch_scc0 .LBB0_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sgemmNT
		.amdhsa_group_segment_fixed_size 256
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 92
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	sgemmNT, .Lfunc_end0-sgemmNT
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1776
; NumSgprs: 26
; NumVgprs: 92
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 256 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 92
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	sgemmNN                 ; -- Begin function sgemmNN
	.globl	sgemmNN
	.p2align	8
	.type	sgemmNN,@function
sgemmNN:                                ; @sgemmNN
; %bb.0:
	s_clause 0x2
	s_load_b32 s18, s[0:1], 0x18
	s_load_b32 s8, s[0:1], 0x8
	s_load_b128 s[4:7], s[0:1], 0x28
	v_bfe_u32 v4, v0, 10, 10
	s_lshl_b32 s16, s15, 12
	v_and_b32_e32 v5, 0x3ff, v0
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[10:11], s[0:1], 0x0
	v_lshl_add_u32 v0, v4, 8, s16
	v_dual_mov_b32 v76, 0 :: v_dual_lshlrev_b32 v1, 4, v4
	s_lshl_b32 s9, s14, 6
	v_mov_b32_e32 v77, 0x3fc
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v0, 8, v0
	v_add3_u32 v16, v1, v5, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v17, 31, v16
	s_waitcnt lgkmcnt(0)
	v_mad_i32_i24 v0, s18, v0, v5
	s_lshl_b32 s20, s18, 2
	s_ashr_i32 s15, s5, 31
	s_mov_b32 s14, s5
	v_lshlrev_b64 v[2:3], 2, v[16:17]
	v_ashrrev_i32_e32 v1, 31, v0
	s_lshl_b64 s[14:15], s[14:15], 2
	s_ashr_i32 s19, s18, 31
	s_ashr_i32 s21, s20, 31
	s_ashr_i32 s9, s8, 31
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_lshl_b32 s22, s8, 1
	s_mul_i32 s12, s8, 3
	s_lshl_b64 s[24:25], s[18:19], 4
	s_ashr_i32 s23, s22, 31
	s_ashr_i32 s13, s12, 31
	v_add_co_u32 v18, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v44, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v45, vcc_lo, s11, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, v18, s14
	s_lshl_b64 s[2:3], s[20:21], 2
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v19, vcc_lo
	s_lshl_b64 s[14:15], s[8:9], 2
	s_add_u32 s5, s24, s2
	s_addc_u32 s17, s25, s3
	s_lshl_b64 s[18:19], s[18:19], 5
	s_mul_i32 s27, s8, 28
	s_add_u32 s18, s18, s2
	s_mul_i32 s28, s8, 36
	s_addc_u32 s19, s19, s3
	s_mul_hi_i32 s26, s8, 28
	s_mul_hi_i32 s29, s12, 12
	s_add_u32 s20, s27, s28
	s_addc_u32 s21, s26, s29
	s_lshl_b64 s[24:25], s[8:9], 3
	s_mul_i32 s33, s8, 24
	s_add_u32 s24, s10, s24
	s_addc_u32 s25, s11, s25
	v_add_co_u32 v47, vcc_lo, s24, v2
	s_mul_i32 s24, s8, 12
	v_add_co_ci_u32_e32 v48, vcc_lo, s25, v3, vcc_lo
	s_mul_hi_i32 s25, s8, 12
	s_add_u32 s30, s10, s24
	s_addc_u32 s31, s11, s25
	s_mul_hi_i32 s34, s8, 24
	s_add_u32 s24, s33, s28
	s_addc_u32 s25, s34, s29
	s_add_u32 s28, s10, s24
	s_addc_u32 s29, s11, s25
	s_lshl_b64 s[24:25], s[12:13], 3
	v_add_co_u32 v49, vcc_lo, s30, v2
	s_add_u32 s30, s33, s24
	v_add_co_ci_u32_e32 v50, vcc_lo, s31, v3, vcc_lo
	s_addc_u32 s31, s34, s25
	s_lshl_b64 s[22:23], s[22:23], 2
	v_add_co_u32 v51, vcc_lo, s28, v2
	s_add_u32 s28, s30, s22
	v_add_co_ci_u32_e32 v52, vcc_lo, s29, v3, vcc_lo
	s_addc_u32 s29, s31, s23
	s_add_u32 s28, s10, s28
	s_addc_u32 s29, s11, s29
	s_add_u32 s27, s27, s24
	v_add_co_u32 v53, vcc_lo, s28, v2
	s_addc_u32 s26, s26, s25
	s_add_u32 s27, s10, s27
	v_add_co_ci_u32_e32 v54, vcc_lo, s29, v3, vcc_lo
	s_addc_u32 s26, s11, s26
	v_add_co_u32 v55, vcc_lo, s27, v2
	v_lshlrev_b32_e32 v0, 2, v4
	v_add_co_ci_u32_e32 v56, vcc_lo, s26, v3, vcc_lo
	s_add_u32 s26, s10, s30
	s_addc_u32 s27, s11, s31
	v_add_co_u32 v57, vcc_lo, s26, v2
	v_add_co_ci_u32_e32 v58, vcc_lo, s27, v3, vcc_lo
	v_mad_u32_u24 v46, 0x44, v5, v0
	v_add_co_u32 v0, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
	s_mul_i32 s27, s8, 20
	s_mul_hi_i32 s26, s8, 20
	s_add_u32 s24, s27, s24
	s_addc_u32 s25, s26, s25
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_add_u32 s24, s10, s24
	s_addc_u32 s25, s11, s25
	v_add_co_u32 v17, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v59, vcc_lo, s25, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s27, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s26, v1, vcc_lo
	s_add_u32 s24, s10, s22
	s_addc_u32 s25, s11, s23
	v_add_co_u32 v60, vcc_lo, s24, v4
	s_add_u32 s24, s10, s33
	v_add_co_ci_u32_e32 v61, vcc_lo, s25, v5, vcc_lo
	s_addc_u32 s25, s11, s34
	v_add_co_u32 v62, vcc_lo, s24, v0
	s_lshl_b64 s[8:9], s[8:9], 4
	s_lshl_b64 s[12:13], s[12:13], 2
	v_add_co_ci_u32_e32 v63, vcc_lo, s25, v1, vcc_lo
	s_add_u32 s12, s8, s12
	v_add_co_u32 v64, vcc_lo, s10, v4
	s_addc_u32 s13, s9, s13
	s_add_u32 s12, s10, s12
	v_add_co_ci_u32_e32 v65, vcc_lo, s11, v5, vcc_lo
	s_addc_u32 s13, s11, s13
	v_add_co_u32 v66, vcc_lo, s12, v2
	s_add_u32 s12, s8, s22
	v_add_co_ci_u32_e32 v67, vcc_lo, s13, v3, vcc_lo
	s_addc_u32 s13, s9, s23
	s_add_u32 s12, s10, s12
	s_addc_u32 s13, s11, s13
	v_add_co_u32 v68, vcc_lo, s12, v2
	s_add_u32 s12, s10, s27
	v_add_co_ci_u32_e32 v69, vcc_lo, s13, v3, vcc_lo
	s_addc_u32 s13, s11, s26
	v_add_co_u32 v70, vcc_lo, s12, v2
	s_add_u32 s8, s10, s8
	v_add_co_ci_u32_e32 v71, vcc_lo, s13, v3, vcc_lo
	s_addc_u32 s9, s11, s9
	v_add_co_u32 v72, vcc_lo, s8, v2
	v_mov_b32_e32 v0, 0
	s_add_u32 s8, s10, s14
	v_add_co_ci_u32_e32 v73, vcc_lo, s9, v3, vcc_lo
	s_addc_u32 s9, s11, s15
	v_add_co_u32 v74, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v75, vcc_lo, s9, v3, vcc_lo
	v_dual_mov_b32 v78, 0x404 :: v_dual_mov_b32 v1, v0
	v_dual_mov_b32 v79, 0x40c :: v_dual_mov_b32 v2, v0
	v_dual_mov_b32 v80, 0x414 :: v_dual_mov_b32 v3, v0
	v_dual_mov_b32 v81, 0x41c :: v_dual_mov_b32 v4, v0
	v_dual_mov_b32 v82, 0x424 :: v_dual_mov_b32 v5, v0
	v_dual_mov_b32 v83, 0x42c :: v_dual_mov_b32 v6, v0
	v_dual_mov_b32 v84, 0x434 :: v_dual_mov_b32 v7, v0
	v_mov_b32_e32 v8, v0
	v_mov_b32_e32 v9, v0
	v_mov_b32_e32 v10, v0
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v12, v0
	v_mov_b32_e32 v13, v0
	v_mov_b32_e32 v14, v0
	v_mov_b32_e32 v15, v0
	s_mov_b32 s10, 0
	s_mov_b64 s[8:9], 0
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v40, vcc_lo, v44, s8
	v_add_co_ci_u32_e32 v41, vcc_lo, s9, v45, vcc_lo
	v_add_co_u32 v42, vcc_lo, v74, s8
	v_add_co_ci_u32_e32 v43, vcc_lo, s9, v75, vcc_lo
	v_add_co_u32 v32, vcc_lo, v47, s8
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v48, vcc_lo
	v_add_co_u32 v34, vcc_lo, v49, s8
	v_add_co_ci_u32_e32 v35, vcc_lo, s9, v50, vcc_lo
	v_add_co_u32 v86, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v87, vcc_lo, s3, v19, vcc_lo
	v_add_co_u32 v88, vcc_lo, v18, s5
	v_add_co_ci_u32_e32 v89, vcc_lo, s17, v19, vcc_lo
	v_add_co_u32 v90, vcc_lo, v18, s18
	v_add_co_ci_u32_e32 v91, vcc_lo, s19, v19, vcc_lo
	s_clause 0x3
	global_load_b32 v85, v[18:19], off
	global_load_b32 v92, v[86:87], off
	global_load_b32 v93, v[88:89], off
	global_load_b32 v94, v[90:91], off
	s_clause 0x3
	global_load_b32 v95, v[40:41], off
	global_load_b32 v40, v[42:43], off
	global_load_b32 v43, v[32:33], off
	global_load_b32 v96, v[34:35], off
	v_add_co_u32 v22, vcc_lo, v72, s8
	v_add_co_ci_u32_e32 v23, vcc_lo, s9, v73, vcc_lo
	v_add_co_u32 v24, vcc_lo, v70, s8
	v_add_co_ci_u32_e32 v25, vcc_lo, s9, v71, vcc_lo
	v_add_co_u32 v26, vcc_lo, v68, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s9, v69, vcc_lo
	v_add_co_u32 v28, vcc_lo, v66, s8
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v67, vcc_lo
	v_add_co_u32 v30, vcc_lo, v64, s8
	v_add_co_ci_u32_e32 v31, vcc_lo, s9, v65, vcc_lo
	v_add_co_u32 v36, vcc_lo, v62, s8
	v_add_co_ci_u32_e32 v37, vcc_lo, s9, v63, vcc_lo
	v_add_co_u32 v38, vcc_lo, v60, s8
	v_add_co_ci_u32_e32 v39, vcc_lo, s9, v61, vcc_lo
	v_add_co_u32 v86, vcc_lo, v17, s8
	v_add_co_ci_u32_e32 v87, vcc_lo, s9, v59, vcc_lo
	v_add_co_u32 v88, vcc_lo, v57, s8
	v_add_co_ci_u32_e32 v89, vcc_lo, s9, v58, vcc_lo
	v_add_co_u32 v41, vcc_lo, v55, s8
	v_add_co_ci_u32_e32 v42, vcc_lo, s9, v56, vcc_lo
	v_add_co_u32 v34, vcc_lo, v53, s8
	v_add_co_ci_u32_e32 v35, vcc_lo, s9, v54, vcc_lo
	v_add_co_u32 v90, vcc_lo, v51, s8
	v_add_co_ci_u32_e32 v91, vcc_lo, s9, v52, vcc_lo
	v_add_co_u32 v18, vcc_lo, v18, 64
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	s_add_u32 s8, s8, s20
	s_addc_u32 s9, s9, s21
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_u64_e32 vcc_lo, v[18:19], v[20:21]
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(6)
	ds_store_2addr_b32 v46, v85, v92 offset1:4
	s_waitcnt vmcnt(4)
	ds_store_2addr_b32 v46, v93, v94 offset0:8 offset1:12
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_clause 0x8
	global_load_b32 v93, v[22:23], off
	global_load_b32 v97, v[24:25], off
	global_load_b32 v98, v[26:27], off
	global_load_b32 v99, v[28:29], off
	global_load_b32 v100, v[30:31], off
	global_load_b32 v101, v[36:37], off
	global_load_b32 v102, v[38:39], off
	global_load_b32 v103, v[86:87], off
	global_load_b32 v104, v[88:89], off
	ds_load_b128 v[22:25], v76
	ds_load_b128 v[26:29], v76 offset:16
	s_clause 0x1
	global_load_b32 v105, v[41:42], off
	global_load_b32 v106, v[34:35], off
	ds_load_b128 v[30:33], v76 offset:32
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v1, v95, v23
	v_fmac_f32_e32 v0, v95, v22
	v_fmac_f32_e32 v3, v95, v25
	v_fmac_f32_e32 v2, v95, v24
	ds_load_b128 v[22:25], v76 offset:48
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v5, v95, v27
	v_fmac_f32_e32 v4, v95, v26
	v_fmac_f32_e32 v7, v95, v29
	v_fmac_f32_e32 v6, v95, v28
	ds_load_2addr_b32 v[26:27], v76 offset0:17 offset1:18
	ds_load_2addr_b32 v[28:29], v76 offset0:19 offset1:20
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v9, v95, v31
	v_fmac_f32_e32 v8, v95, v30
	v_fmac_f32_e32 v11, v95, v33
	v_fmac_f32_e32 v10, v95, v32
	ds_load_2addr_b32 v[30:31], v76 offset0:21 offset1:22
	ds_load_2addr_b32 v[32:33], v76 offset0:23 offset1:24
	ds_load_2addr_b32 v[34:35], v76 offset0:25 offset1:26
	ds_load_2addr_b32 v[36:37], v76 offset0:27 offset1:28
	ds_load_2addr_b32 v[38:39], v76 offset0:29 offset1:30
	ds_load_2addr_b32 v[41:42], v76 offset0:31 offset1:32
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v13, v95, v23
	v_fmac_f32_e32 v12, v95, v22
	v_fmac_f32_e32 v15, v95, v25
	v_fmac_f32_e32 v14, v95, v24
	global_load_b32 v95, v[90:91], off
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v1, v40, v27
	v_fmac_f32_e32 v0, v40, v26
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v3, v40, v29
	v_fmac_f32_e32 v2, v40, v28
	ds_load_2addr_b64 v[22:25], v76 offset0:17 offset1:18
	ds_load_2addr_b64 v[26:29], v76 offset0:19 offset1:20
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v40, v31
	v_fmac_f32_e32 v4, v40, v30
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v7, v40, v33
	v_fmac_f32_e32 v6, v40, v32
	ds_load_2addr_b64 v[30:33], v76 offset0:21 offset1:22
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v9, v40, v35
	v_fmac_f32_e32 v8, v40, v34
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v11, v40, v37
	v_fmac_f32_e32 v10, v40, v36
	ds_load_2addr_b64 v[34:37], v76 offset0:23 offset1:24
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v13, v40, v39
	v_fmac_f32_e32 v12, v40, v38
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v4, v43, v26
	v_fmac_f32_e32 v3, v43, v25
	v_fmac_f32_e32 v2, v43, v24
	v_fmac_f32_e32 v1, v43, v23
	v_fmac_f32_e32 v0, v43, v22
	ds_load_2addr_b32 v[22:23], v76 offset0:51 offset1:52
	ds_load_2addr_b32 v[24:25], v76 offset0:53 offset1:54
	v_fmac_f32_e32 v5, v43, v27
	v_fmac_f32_e32 v7, v43, v29
	v_fmac_f32_e32 v6, v43, v28
	ds_load_2addr_b32 v[26:27], v76 offset0:55 offset1:56
	ds_load_2addr_b32 v[28:29], v76 offset0:57 offset1:58
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v9, v43, v31
	v_fmac_f32_e32 v8, v43, v30
	v_fmac_f32_e32 v11, v43, v33
	v_fmac_f32_e32 v10, v43, v32
	ds_load_2addr_b32 v[30:31], v76 offset0:59 offset1:60
	ds_load_2addr_b32 v[32:33], v76 offset0:61 offset1:62
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v13, v43, v35
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v12, v43, v34 :: v_dual_fmac_f32 v3, v96, v25
	v_fmac_f32_e32 v2, v96, v24
	v_fmac_f32_e32 v1, v96, v23
	v_fmac_f32_e32 v0, v96, v22
	v_fmac_f32_e32 v15, v40, v42
	v_fmac_f32_e32 v14, v40, v41
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v5, v96, v27
	v_fmac_f32_e32 v4, v96, v26
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v7, v96, v29
	v_fmac_f32_e32 v15, v43, v37
	v_fmac_f32_e32 v14, v43, v36
	ds_load_2addr_b32 v[34:35], v76 offset0:63 offset1:64
	ds_load_2addr_b32 v[36:37], v76 offset0:65 offset1:66
	ds_load_b128 v[22:25], v76 offset:272
	v_fmac_f32_e32 v6, v96, v28
	ds_load_b128 v[26:29], v76 offset:288
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v9, v96, v31
	v_fmac_f32_e32 v8, v96, v30
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v11, v96, v33
	v_fmac_f32_e32 v10, v96, v32
	ds_load_b128 v[30:33], v76 offset:304
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v13, v96, v35
	v_fmac_f32_e32 v12, v96, v34
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v15, v96, v37
	v_fmac_f32_e32 v14, v96, v36
	ds_load_b128 v[34:37], v76 offset:320
	ds_load_2addr_b32 v[38:39], v76 offset0:85 offset1:86
	ds_load_2addr_b32 v[40:41], v76 offset0:87 offset1:88
	ds_load_2addr_b32 v[42:43], v76 offset0:89 offset1:90
	ds_load_2addr_b32 v[85:86], v76 offset0:91 offset1:92
	ds_load_2addr_b32 v[87:88], v76 offset0:93 offset1:94
	ds_load_2addr_b32 v[89:90], v76 offset0:95 offset1:96
	ds_load_2addr_b32 v[91:92], v76 offset0:97 offset1:98
	s_waitcnt vmcnt(11) lgkmcnt(10)
	v_fmac_f32_e32 v1, v93, v23
	v_fmac_f32_e32 v3, v93, v25
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v5, v93, v27
	v_fmac_f32_e32 v7, v93, v29
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v9, v93, v31
	v_fmac_f32_e32 v11, v93, v33
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v13, v93, v35
	v_fmac_f32_e32 v14, v93, v36
	v_fmac_f32_e32 v15, v93, v37
	s_waitcnt vmcnt(10) lgkmcnt(6)
	v_fmac_f32_e32 v1, v97, v39
	v_fmac_f32_e32 v0, v93, v22
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v3, v97, v41
	v_fmac_f32_e32 v2, v93, v24
	ds_load_2addr_b64 v[22:25], v76 offset0:51 offset1:52
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v5, v97, v43
	v_fmac_f32_e32 v4, v93, v26
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v7, v97, v86
	v_fmac_f32_e32 v6, v93, v28
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v9, v97, v88
	v_fmac_f32_e32 v8, v93, v30
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v11, v97, v90
	v_fmac_f32_e32 v10, v93, v32
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v13, v97, v92
	v_fmac_f32_e32 v12, v93, v34
	ds_load_2addr_b32 v[93:94], v76 offset0:99 offset1:100
	ds_load_2addr_b64 v[26:29], v76 offset0:53 offset1:54
	ds_load_2addr_b64 v[30:33], v76 offset0:55 offset1:56
	ds_load_2addr_b64 v[34:37], v76 offset0:57 offset1:58
	s_waitcnt vmcnt(9) lgkmcnt(4)
	v_dual_fmac_f32 v1, v98, v23 :: v_dual_fmac_f32 v0, v97, v38
	v_dual_fmac_f32 v3, v98, v25 :: v_dual_fmac_f32 v2, v97, v40
	ds_load_2addr_b32 v[38:39], v76 offset0:119 offset1:120
	ds_load_2addr_b32 v[40:41], v76 offset0:121 offset1:122
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v15, v97, v94
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v5, v98, v27 :: v_dual_fmac_f32 v4, v97, v42
	v_fmac_f32_e32 v7, v98, v29
	v_fmac_f32_e32 v6, v97, v85
	ds_load_2addr_b32 v[42:43], v76 offset0:123 offset1:124
	ds_load_2addr_b32 v[85:86], v76 offset0:125 offset1:126
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v9, v98, v31
	v_dual_fmac_f32 v8, v97, v87 :: v_dual_fmac_f32 v11, v98, v33
	v_fmac_f32_e32 v10, v97, v89
	ds_load_2addr_b32 v[87:88], v76 offset0:127 offset1:128
	ds_load_2addr_b32 v[89:90], v76 offset0:129 offset1:130
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v13, v98, v35
	v_dual_fmac_f32 v12, v97, v91 :: v_dual_fmac_f32 v15, v98, v37
	v_fmac_f32_e32 v14, v97, v93
	ds_load_2addr_b32 v[91:92], v76 offset0:131 offset1:132
	ds_load_2addr_b32 v[93:94], v76 offset0:133 offset1:134
	s_waitcnt vmcnt(8) lgkmcnt(7)
	v_dual_fmac_f32 v1, v99, v39 :: v_dual_fmac_f32 v0, v98, v22
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v3, v99, v41 :: v_dual_fmac_f32 v2, v98, v24
	ds_load_b128 v[22:25], v76 offset:544
	v_fmac_f32_e32 v0, v99, v38
	ds_load_2addr_b32 v[38:39], v76 offset0:153 offset1:154
	v_fmac_f32_e32 v2, v99, v40
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v5, v99, v43 :: v_dual_fmac_f32 v4, v98, v26
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v7, v99, v86 :: v_dual_fmac_f32 v6, v98, v28
	ds_load_b128 v[26:29], v76 offset:560
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v9, v99, v88 :: v_dual_fmac_f32 v8, v98, v30
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v11, v99, v90 :: v_dual_fmac_f32 v10, v98, v32
	ds_load_b128 v[30:33], v76 offset:576
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v13, v99, v92 :: v_dual_fmac_f32 v12, v98, v34
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v15, v99, v94 :: v_dual_fmac_f32 v14, v98, v36
	ds_load_b128 v[34:37], v76 offset:592
	v_fmac_f32_e32 v4, v99, v42
	v_fmac_f32_e32 v6, v99, v85
	v_fmac_f32_e32 v8, v99, v87
	v_fmac_f32_e32 v10, v99, v89
	v_fmac_f32_e32 v12, v99, v91
	v_fmac_f32_e32 v14, v99, v93
	ds_load_2addr_b32 v[40:41], v76 offset0:155 offset1:156
	ds_load_2addr_b32 v[42:43], v76 offset0:157 offset1:158
	s_waitcnt vmcnt(7) lgkmcnt(6)
	v_fmac_f32_e32 v1, v100, v23
	v_fmac_f32_e32 v0, v100, v22
	v_fmac_f32_e32 v3, v100, v25
	v_fmac_f32_e32 v2, v100, v24
	ds_load_2addr_b32 v[85:86], v76 offset0:159 offset1:160
	ds_load_2addr_b32 v[87:88], v76 offset0:161 offset1:162
	ds_load_2addr_b32 v[89:90], v76 offset0:163 offset1:164
	ds_load_2addr_b32 v[91:92], v76 offset0:165 offset1:166
	ds_load_2addr_b32 v[93:94], v76 offset0:167 offset1:168
	ds_load_2addr_b64 v[22:25], v76 offset0:85 offset1:86
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v9, v100, v31
	s_waitcnt vmcnt(6)
	v_dual_fmac_f32 v8, v100, v30 :: v_dual_fmac_f32 v1, v101, v39
	v_dual_fmac_f32 v0, v101, v38 :: v_dual_fmac_f32 v5, v100, v27
	v_fmac_f32_e32 v4, v100, v26
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v13, v100, v35
	v_fmac_f32_e32 v12, v100, v34
	v_fmac_f32_e32 v15, v100, v37
	ds_load_2addr_b32 v[38:39], v76 offset0:187 offset1:188
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v3, v101, v41
	v_fmac_f32_e32 v2, v101, v40
	ds_load_2addr_b32 v[40:41], v76 offset0:189 offset1:190
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v5, v101, v43
	v_fmac_f32_e32 v4, v101, v42
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v9, v101, v88
	v_dual_fmac_f32 v7, v100, v29 :: v_dual_fmac_f32 v8, v101, v87
	v_fmac_f32_e32 v6, v100, v28
	ds_load_2addr_b64 v[26:29], v76 offset0:87 offset1:88
	s_waitcnt vmcnt(5) lgkmcnt(3)
	v_fmac_f32_e32 v0, v102, v22
	v_dual_fmac_f32 v14, v100, v36 :: v_dual_fmac_f32 v15, v101, v94
	ds_load_2addr_b64 v[34:37], v76 offset0:91 offset1:92
	v_fmac_f32_e32 v7, v101, v86
	v_fmac_f32_e32 v6, v101, v85
	v_fmac_f32_e32 v13, v101, v92
	v_dual_fmac_f32 v11, v100, v33 :: v_dual_fmac_f32 v12, v101, v91
	v_fmac_f32_e32 v10, v100, v32
	ds_load_2addr_b64 v[30:33], v76 offset0:89 offset1:90
	ds_load_2addr_b32 v[42:43], v76 offset0:191 offset1:192
	ds_load_2addr_b32 v[85:86], v76 offset0:193 offset1:194
	v_fmac_f32_e32 v11, v101, v90
	v_dual_fmac_f32 v14, v101, v93 :: v_dual_fmac_f32 v1, v102, v23
	v_fmac_f32_e32 v10, v101, v89
	ds_load_2addr_b32 v[87:88], v76 offset0:195 offset1:196
	ds_load_2addr_b32 v[89:90], v76 offset0:197 offset1:198
	ds_load_2addr_b32 v[91:92], v76 offset0:199 offset1:200
	ds_load_2addr_b32 v[93:94], v76 offset0:201 offset1:202
	s_waitcnt vmcnt(4) lgkmcnt(10)
	v_dual_fmac_f32 v2, v102, v24 :: v_dual_fmac_f32 v1, v103, v39
	v_dual_fmac_f32 v3, v102, v25 :: v_dual_fmac_f32 v0, v103, v38
	ds_load_b128 v[22:25], v76 offset:816
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v4, v102, v26
	v_dual_fmac_f32 v5, v102, v27 :: v_dual_fmac_f32 v2, v103, v40
	v_dual_fmac_f32 v6, v102, v28 :: v_dual_fmac_f32 v3, v103, v41
	v_fmac_f32_e32 v7, v102, v29
	ds_load_2addr_b32 v[38:39], v76 offset0:221 offset1:222
	ds_load_2addr_b32 v[40:41], v76 offset0:223 offset1:224
	ds_load_b128 v[26:29], v76 offset:832
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v4, v103, v42
	s_waitcnt lgkmcnt(8)
	v_dual_fmac_f32 v10, v102, v32 :: v_dual_fmac_f32 v7, v103, v86
	v_fmac_f32_e32 v13, v102, v35
	v_fmac_f32_e32 v5, v103, v43
	v_dual_fmac_f32 v9, v102, v31 :: v_dual_fmac_f32 v6, v103, v85
	v_fmac_f32_e32 v8, v102, v30
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v10, v103, v89
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v12, v102, v34 :: v_dual_fmac_f32 v13, v103, v92
	v_fmac_f32_e32 v15, v102, v37
	v_fmac_f32_e32 v9, v103, v88
	v_dual_fmac_f32 v11, v102, v33 :: v_dual_fmac_f32 v8, v103, v87
	v_fmac_f32_e32 v14, v102, v36
	ds_load_b128 v[30:33], v76 offset:848
	ds_load_b128 v[34:37], v76 offset:864
	ds_load_2addr_b32 v[42:43], v76 offset0:225 offset1:226
	ds_load_2addr_b32 v[85:86], v76 offset0:227 offset1:228
	ds_load_2addr_b32 v[87:88], v76 offset0:229 offset1:230
	v_fmac_f32_e32 v11, v103, v90
	v_fmac_f32_e32 v12, v103, v91
	s_waitcnt vmcnt(3) lgkmcnt(8)
	v_dual_fmac_f32 v14, v103, v93 :: v_dual_fmac_f32 v1, v104, v23
	ds_load_2addr_b32 v[89:90], v76 offset0:231 offset1:232
	ds_load_2addr_b32 v[91:92], v76 offset0:233 offset1:234
	v_dual_fmac_f32 v15, v103, v94 :: v_dual_fmac_f32 v2, v104, v24
	s_waitcnt vmcnt(2) lgkmcnt(9)
	v_dual_fmac_f32 v0, v104, v22 :: v_dual_fmac_f32 v1, v105, v39
	v_fmac_f32_e32 v3, v104, v25
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v5, v104, v27 :: v_dual_fmac_f32 v2, v105, v40
	v_fmac_f32_e32 v6, v104, v28
	v_fmac_f32_e32 v0, v105, v38
	v_dual_fmac_f32 v4, v104, v26 :: v_dual_fmac_f32 v3, v105, v41
	v_fmac_f32_e32 v7, v104, v29
	ds_load_2addr_b32 v[93:94], v76 offset0:235 offset1:236
	ds_load_2addr_b64 v[22:25], v76 offset0:119 offset1:120
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v4, v105, v42
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v10, v104, v32 :: v_dual_fmac_f32 v7, v105, v86
	v_fmac_f32_e32 v13, v104, v35
	v_fmac_f32_e32 v5, v105, v43
	v_dual_fmac_f32 v9, v104, v31 :: v_dual_fmac_f32 v6, v105, v85
	v_fmac_f32_e32 v8, v104, v30
	ds_load_2addr_b32 v[38:39], v77 offset1:1
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v10, v105, v89
	v_fmac_f32_e32 v9, v105, v88
	v_dual_fmac_f32 v11, v104, v33 :: v_dual_fmac_f32 v8, v105, v87
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v12, v104, v34 :: v_dual_fmac_f32 v13, v105, v92
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v104, v36 :: v_dual_fmac_f32 v11, v105, v90
	v_dual_fmac_f32 v15, v104, v37 :: v_dual_fmac_f32 v12, v105, v91
	ds_load_2addr_b64 v[34:37], v76 offset0:125 offset1:126
	ds_load_2addr_b64 v[26:29], v76 offset0:121 offset1:122
	ds_load_2addr_b64 v[30:33], v76 offset0:123 offset1:124
	ds_load_2addr_b32 v[40:41], v78 offset1:1
	ds_load_2addr_b32 v[42:43], v79 offset1:1
	ds_load_2addr_b32 v[85:86], v80 offset1:1
	s_waitcnt vmcnt(1) lgkmcnt(7)
	v_dual_fmac_f32 v14, v105, v93 :: v_dual_fmac_f32 v1, v106, v23
	ds_load_2addr_b32 v[87:88], v81 offset1:1
	ds_load_2addr_b32 v[89:90], v82 offset1:1
	v_dual_fmac_f32 v15, v105, v94 :: v_dual_fmac_f32 v2, v106, v24
	s_waitcnt vmcnt(0) lgkmcnt(8)
	v_dual_fmac_f32 v0, v106, v22 :: v_dual_fmac_f32 v1, v95, v39
	v_fmac_f32_e32 v3, v106, v25
	ds_load_2addr_b32 v[22:23], v83 offset1:1
	ds_load_2addr_b32 v[24:25], v84 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v0, v95, v38
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v4, v106, v26
	v_dual_fmac_f32 v5, v106, v27 :: v_dual_fmac_f32 v2, v95, v40
	v_dual_fmac_f32 v6, v106, v28 :: v_dual_fmac_f32 v3, v95, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v7, v106, v29 :: v_dual_fmac_f32 v4, v95, v42
	v_dual_fmac_f32 v10, v106, v32 :: v_dual_fmac_f32 v5, v95, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v9, v106, v31 :: v_dual_fmac_f32 v6, v95, v85
	v_fmac_f32_e32 v8, v106, v30
	v_fmac_f32_e32 v7, v95, v86
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v13, v106, v35 :: v_dual_fmac_f32 v10, v95, v89
	v_dual_fmac_f32 v12, v106, v34 :: v_dual_fmac_f32 v9, v95, v88
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v11, v106, v33 :: v_dual_fmac_f32 v8, v95, v87
	v_dual_fmac_f32 v14, v106, v36 :: v_dual_fmac_f32 v13, v95, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v15, v106, v37 :: v_dual_fmac_f32 v12, v95, v22
	v_fmac_f32_e32 v11, v95, v90
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v95, v24
	v_fmac_f32_e32 v15, v95, v25
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_1
; %bb.2:                                ; %.preheader
	s_or_b32 exec_lo, exec_lo, s10
	s_ashr_i32 s2, s16, 8
	s_bfe_i32 s3, s4, 0x180000
	s_load_b64 s[0:1], s[0:1], 0x20
	v_mad_u64_u32 v[17:18], null, s3, s2, v[16:17]
	s_ashr_i32 s5, s4, 31
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[16:17], 2, v[17:18]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	s_lshl_b64 s[0:1], s[4:5], 2
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v18, v[16:17], off
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	v_movrels_b32_e32 v19, v0
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 16
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v18, s7, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v18, s6, v19
	global_store_b32 v[16:17], v18, off
	v_add_co_u32 v16, vcc_lo, v16, s0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	s_cbranch_scc0 .LBB1_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sgemmNN
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 107
		.amdhsa_next_free_sgpr 35
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	sgemmNN, .Lfunc_end1-sgemmNN
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3620
; NumSgprs: 37
; NumVgprs: 107
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 13
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 107
; Occupancy: 12
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 256
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sgemmNT
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         sgemmNT.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     92
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sgemmNN
    .private_segment_fixed_size: 0
    .sgpr_count:     37
    .sgpr_spill_count: 0
    .symbol:         sgemmNN.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     107
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
