#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <curand_kernel.h>
#include <stdlib.h>
#include <cuda.h>
#include <sys/time.h>
#include "cudaS_ssdToOutput_kernels.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
cudaSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
unsigned int batchSize = 1;
unsigned int nbClass = 1;
unsigned int nbAnchors = 1;
unsigned int channelWidth = 1;
unsigned int channelHeight = 1;
unsigned int nbProposals = 1;
unsigned int *nbValidROIs = NULL;
cudaMalloc(&nbValidROIs, XSIZE*YSIZE);
unsigned int cls = 1;
unsigned int totalParts = 1;
unsigned int totalTemplates = 1;
unsigned int maxParts = 1;
unsigned int maxTemplates = 1;
unsigned int cumulParts = 1;
unsigned int cumulTemplates = 1;
unsigned int nbParts = 1;
unsigned int nbTemplates = 1;
float xRatio = 1;
float yRatio = 1;
float xOutputRatio = 1;
float yOutputRatio = 1;
const float *roi_bbox = NULL;
cudaMalloc(&roi_bbox, XSIZE*YSIZE);
const float *roi_anchors = NULL;
cudaMalloc(&roi_anchors, XSIZE*YSIZE);
const float *anchors = NULL;
cudaMalloc(&anchors, XSIZE*YSIZE);
const float *inputs_parts = NULL;
cudaMalloc(&inputs_parts, XSIZE*YSIZE);
const float *inputs_templates = NULL;
cudaMalloc(&inputs_templates, XSIZE*YSIZE);
float *outputs = NULL;
cudaMalloc(&outputs, XSIZE*YSIZE);
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
cudaFree(0);
cudaS_ssdToOutput_kernels<<<gridBlock,threadBlock>>>(batchSize,nbClass,nbAnchors,channelWidth,channelHeight,nbProposals,nbValidROIs,cls,totalParts,totalTemplates,maxParts,maxTemplates,cumulParts,cumulTemplates,nbParts,nbTemplates,xRatio,yRatio,xOutputRatio,yOutputRatio,roi_bbox,roi_anchors,anchors,inputs_parts,inputs_templates,outputs);
cudaDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
cudaS_ssdToOutput_kernels<<<gridBlock,threadBlock>>>(batchSize,nbClass,nbAnchors,channelWidth,channelHeight,nbProposals,nbValidROIs,cls,totalParts,totalTemplates,maxParts,maxTemplates,cumulParts,cumulTemplates,nbParts,nbTemplates,xRatio,yRatio,xOutputRatio,yOutputRatio,roi_bbox,roi_anchors,anchors,inputs_parts,inputs_templates,outputs);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
cudaS_ssdToOutput_kernels<<<gridBlock,threadBlock>>>(batchSize,nbClass,nbAnchors,channelWidth,channelHeight,nbProposals,nbValidROIs,cls,totalParts,totalTemplates,maxParts,maxTemplates,cumulParts,cumulTemplates,nbParts,nbTemplates,xRatio,yRatio,xOutputRatio,yOutputRatio,roi_bbox,roi_anchors,anchors,inputs_parts,inputs_templates,outputs);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}}
	.file	"tmpxft_002ec4cf_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3954:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3954:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.type	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, @function
_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf:
.LFB3976:
	.cfi_startproc
	endbr64
	subq	$392, %rsp
	.cfi_def_cfa_offset 400
	movq	400(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movq	480(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	488(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	496(%rsp), %rax
	movl	%r8d, 76(%rsp)
	movq	%rax, 24(%rsp)
	movq	504(%rsp), %rax
	movl	%r9d, 72(%rsp)
	movq	%rax, 16(%rsp)
	movq	512(%rsp), %rax
	movss	%xmm0, 60(%rsp)
	movq	%rax, 8(%rsp)
	movq	520(%rsp), %rax
	movss	%xmm1, 56(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm2, 52(%rsp)
	movss	%xmm3, 48(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 376(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	416(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	424(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	432(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	472(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 360(%rsp)
	movq	%rsp, %rax
	movq	%rax, 368(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 408
	leaq	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 416
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 408
	popq	%rdx
	.cfi_def_cfa_offset 400
.L2:
	movq	376(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$392, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3976:
	.size	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, .-_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.globl	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.type	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, @function
_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf:
.LFB3977:
	.cfi_startproc
	endbr64
	jmp	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.cfi_endproc
.LFE3977:
	.size	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, .-_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3948:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movq	8(%rbx), %rdi
	leaq	16(%rsp), %rsi
	xorl	%ebx, %ebx
	movl	$10, %edx
	call	__isoc23_strtol@PLT
	movl	%eax, 12(%rsp)
.L9:
	cmpl	%ebx, 12(%rsp)
	jle	.L26
	leaq	blocks_(%rip), %rbp
.L19:
	leaq	matrices_(%rip), %rax
	leaq	24(%rsp), %rdi
	movl	0(%rbp), %r13d
	movl	4(%rbp), %r12d
	movl	(%rax,%rbx,8), %eax
	movl	%eax, 4(%rsp)
	leaq	4+matrices_(%rip), %rax
	movl	4(%rsp), %r14d
	movl	(%rax,%rbx,8), %r15d
	xorl	%eax, %eax
	movq	%rax, 24(%rsp)
	imull	%r15d, %r14d
	movslq	%r14d, %r14
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	xorl	%edx, %edx
	leaq	32(%rsp), %rdi
	movq	%r14, %rsi
	movq	%rdx, 32(%rsp)
	call	cudaMalloc@PLT
	xorl	%ecx, %ecx
	leaq	40(%rsp), %rdi
	movq	%r14, %rsi
	movq	%rcx, 40(%rsp)
	call	cudaMalloc@PLT
	xorl	%esi, %esi
	leaq	48(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	xorl	%edi, %edi
	movq	%r14, %rsi
	movq	%rdi, 56(%rsp)
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	xorl	%r8d, %r8d
	leaq	64(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r8, 64(%rsp)
	call	cudaMalloc@PLT
	xorl	%r9d, %r9d
	leaq	72(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r9, 72(%rsp)
	call	cudaMalloc@PLT
	movl	4(%rsp), %ecx
.L10:
	movl	%ecx, %eax
	cltd
	idivl	%r13d
	movl	%eax, %esi
	testl	%edx, %edx
	je	.L27
	incl	%ecx
	jmp	.L10
.L27:
	movl	%r15d, %ecx
.L12:
	movl	%ecx, %eax
	cltd
	idivl	%r12d
	testl	%edx, %edx
	je	.L28
	incl	%ecx
	jmp	.L12
.L28:
	xorl	%edi, %edi
	movl	%esi, 80(%rsp)
	movl	%eax, 84(%rsp)
	movl	$1, 88(%rsp)
	movl	%r13d, 92(%rsp)
	movl	%r12d, 96(%rsp)
	movl	$1, 100(%rsp)
	call	cudaFree@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	72(%rsp)
	.cfi_def_cfa_offset 184
	movl	$1, %r9d
	movl	$1, %r8d
	movl	$1, %ecx
	pushq	72(%rsp)
	.cfi_def_cfa_offset 192
	movl	$1, %edx
	movl	$1, %esi
	movl	$1, %edi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 200
	pushq	72(%rsp)
	.cfi_def_cfa_offset 208
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	pushq	$1
	.cfi_def_cfa_offset 232
	pushq	$1
	.cfi_def_cfa_offset 240
	pushq	$1
	.cfi_def_cfa_offset 248
	pushq	$1
	.cfi_def_cfa_offset 256
	pushq	$1
	.cfi_def_cfa_offset 264
	pushq	$1
	.cfi_def_cfa_offset 272
	pushq	$1
	.cfi_def_cfa_offset 280
	pushq	$1
	.cfi_def_cfa_offset 288
	movss	.LC0(%rip), %xmm3
	pushq	$1
	.cfi_def_cfa_offset 296
	pushq	144(%rsp)
	.cfi_def_cfa_offset 304
	movaps	%xmm3, %xmm2
	movaps	%xmm3, %xmm1
	movaps	%xmm3, %xmm0
	call	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	subq	$-128, %rsp
	.cfi_def_cfa_offset 176
.L14:
	call	cudaDeviceSynchronize@PLT
	movl	$10, %r14d
.L16:
	movl	100(%rsp), %ecx
	movq	92(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	72(%rsp)
	.cfi_def_cfa_offset 184
	movl	$1, %r9d
	movl	$1, %r8d
	movl	$1, %ecx
	pushq	72(%rsp)
	.cfi_def_cfa_offset 192
	movl	$1, %edx
	movl	$1, %esi
	movl	$1, %edi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 200
	pushq	72(%rsp)
	.cfi_def_cfa_offset 208
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	pushq	$1
	.cfi_def_cfa_offset 232
	pushq	$1
	.cfi_def_cfa_offset 240
	pushq	$1
	.cfi_def_cfa_offset 248
	pushq	$1
	.cfi_def_cfa_offset 256
	pushq	$1
	.cfi_def_cfa_offset 264
	pushq	$1
	.cfi_def_cfa_offset 272
	pushq	$1
	.cfi_def_cfa_offset 280
	pushq	$1
	.cfi_def_cfa_offset 288
	movss	.LC0(%rip), %xmm3
	pushq	$1
	.cfi_def_cfa_offset 296
	pushq	144(%rsp)
	.cfi_def_cfa_offset 304
	movaps	%xmm3, %xmm2
	movaps	%xmm3, %xmm1
	movaps	%xmm3, %xmm0
	call	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	subq	$-128, %rsp
	.cfi_def_cfa_offset 176
.L15:
	decl	%r14d
	jne	.L16
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	movl	$1000, 8(%rsp)
	movq	%rax, %r14
.L18:
	movl	100(%rsp), %ecx
	movq	92(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	72(%rsp)
	.cfi_def_cfa_offset 184
	movl	$1, %r9d
	movl	$1, %r8d
	movl	$1, %ecx
	pushq	72(%rsp)
	.cfi_def_cfa_offset 192
	movl	$1, %edx
	movl	$1, %esi
	movl	$1, %edi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 200
	pushq	72(%rsp)
	.cfi_def_cfa_offset 208
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	pushq	$1
	.cfi_def_cfa_offset 232
	pushq	$1
	.cfi_def_cfa_offset 240
	pushq	$1
	.cfi_def_cfa_offset 248
	pushq	$1
	.cfi_def_cfa_offset 256
	pushq	$1
	.cfi_def_cfa_offset 264
	pushq	$1
	.cfi_def_cfa_offset 272
	pushq	$1
	.cfi_def_cfa_offset 280
	pushq	$1
	.cfi_def_cfa_offset 288
	movss	.LC0(%rip), %xmm3
	pushq	$1
	.cfi_def_cfa_offset 296
	pushq	144(%rsp)
	.cfi_def_cfa_offset 304
	movaps	%xmm3, %xmm2
	movaps	%xmm3, %xmm1
	movaps	%xmm3, %xmm0
	call	_Z81__device_stub__Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_PfjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	subq	$-128, %rsp
	.cfi_def_cfa_offset 176
.L17:
	decl	8(%rsp)
	jne	.L18
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	movl	$91, %esi
	leaq	_ZSt4cout(%rip), %rdi
	addq	$8, %rbp
	subq	%r14, %rax
	cvtsi2ssq	%rax, %xmm0
	divss	.LC1(%rip), %xmm0
	movss	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movss	8(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$44, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	$40, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movl	$44, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movl	$41, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	$44, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	$40, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	4(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movl	$44, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	%r15d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movl	$41, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	$93, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	160+blocks_(%rip), %rax
	cmpq	%rax, %rbp
	jne	.L19
	incq	%rbx
	jmp	.L9
.L26:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3948:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf"
.LC3:
	.string	"precalc_xorwow_matrix"
.LC4:
	.string	"precalc_xorwow_offset_matrix"
.LC5:
	.string	"mrg32k3aM1"
.LC6:
	.string	"mrg32k3aM2"
.LC7:
	.string	"mrg32k3aM1SubSeq"
.LC8:
	.string	"mrg32k3aM2SubSeq"
.LC9:
	.string	"mrg32k3aM1Seq"
.LC10:
	.string	"mrg32k3aM2Seq"
.LC11:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3979:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3979:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	matrices_
	.data
	.align 32
	.type	matrices_, @object
	.size	matrices_, 56
matrices_:
	.long	240
	.long	240
	.long	496
	.long	496
	.long	784
	.long	784
	.long	1016
	.long	1016
	.long	1232
	.long	1232
	.long	1680
	.long	1680
	.long	2024
	.long	2024
	.globl	blocks_
	.align 32
	.type	blocks_, @object
	.size	blocks_, 160
blocks_:
	.long	8
	.long	8
	.long	16
	.long	16
	.long	24
	.long	24
	.long	32
	.long	32
	.long	1
	.long	64
	.long	1
	.long	128
	.long	1
	.long	192
	.long	1
	.long	256
	.long	1
	.long	320
	.long	1
	.long	384
	.long	1
	.long	448
	.long	1
	.long	512
	.long	1
	.long	576
	.long	1
	.long	640
	.long	1
	.long	704
	.long	1
	.long	768
	.long	1
	.long	832
	.long	1
	.long	896
	.long	1
	.long	960
	.long	1
	.long	1024
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include "cudaS_ssdToOutput_kernels.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
hipSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
unsigned int batchSize = 1;
unsigned int nbClass = 1;
unsigned int nbAnchors = 1;
unsigned int channelWidth = 1;
unsigned int channelHeight = 1;
unsigned int nbProposals = 1;
unsigned int *nbValidROIs = NULL;
hipMalloc(&nbValidROIs, XSIZE*YSIZE);
unsigned int cls = 1;
unsigned int totalParts = 1;
unsigned int totalTemplates = 1;
unsigned int maxParts = 1;
unsigned int maxTemplates = 1;
unsigned int cumulParts = 1;
unsigned int cumulTemplates = 1;
unsigned int nbParts = 1;
unsigned int nbTemplates = 1;
float xRatio = 1;
float yRatio = 1;
float xOutputRatio = 1;
float yOutputRatio = 1;
const float *roi_bbox = NULL;
hipMalloc(&roi_bbox, XSIZE*YSIZE);
const float *roi_anchors = NULL;
hipMalloc(&roi_anchors, XSIZE*YSIZE);
const float *anchors = NULL;
hipMalloc(&anchors, XSIZE*YSIZE);
const float *inputs_parts = NULL;
hipMalloc(&inputs_parts, XSIZE*YSIZE);
const float *inputs_templates = NULL;
hipMalloc(&inputs_templates, XSIZE*YSIZE);
float *outputs = NULL;
hipMalloc(&outputs, XSIZE*YSIZE);
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
hipFree(0);
cudaS_ssdToOutput_kernels<<<gridBlock,threadBlock>>>(batchSize,nbClass,nbAnchors,channelWidth,channelHeight,nbProposals,nbValidROIs,cls,totalParts,totalTemplates,maxParts,maxTemplates,cumulParts,cumulTemplates,nbParts,nbTemplates,xRatio,yRatio,xOutputRatio,yOutputRatio,roi_bbox,roi_anchors,anchors,inputs_parts,inputs_templates,outputs);
hipDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
cudaS_ssdToOutput_kernels<<<gridBlock,threadBlock>>>(batchSize,nbClass,nbAnchors,channelWidth,channelHeight,nbProposals,nbValidROIs,cls,totalParts,totalTemplates,maxParts,maxTemplates,cumulParts,cumulTemplates,nbParts,nbTemplates,xRatio,yRatio,xOutputRatio,yOutputRatio,roi_bbox,roi_anchors,anchors,inputs_parts,inputs_templates,outputs);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
cudaS_ssdToOutput_kernels<<<gridBlock,threadBlock>>>(batchSize,nbClass,nbAnchors,channelWidth,channelHeight,nbProposals,nbValidROIs,cls,totalParts,totalTemplates,maxParts,maxTemplates,cumulParts,cumulTemplates,nbParts,nbTemplates,xRatio,yRatio,xOutputRatio,yOutputRatio,roi_bbox,roi_anchors,anchors,inputs_parts,inputs_templates,outputs);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}}
	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf # -- Begin function _Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.type	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf,@function
_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf: # @_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$304, %rsp                      # imm = 0x130
	.cfi_def_cfa_offset 352
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	44(%rsp), %r10
	movl	%edi, (%r10)
	leaq	40(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	36(%rsp), %r11
	movl	%edx, (%r11)
	leaq	32(%rsp), %r14
	movl	%ecx, (%r14)
	leaq	28(%rsp), %r15
	movl	%r8d, (%r15)
	leaq	24(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	16(%rsp), %rcx
	movss	%xmm1, (%rcx)
	leaq	12(%rsp), %rdx
	movss	%xmm2, (%rdx)
	leaq	8(%rsp), %rsi
	movss	%xmm3, (%rsi)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r11, 16(%rbx)
	movq	%r14, 24(%rbx)
	movq	%r15, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	352(%rsp), %rdi
	movq	%rdi, 48(%rbx)
	leaq	360(%rsp), %rdi
	movq	%rdi, 56(%rbx)
	leaq	368(%rsp), %rdi
	movq	%rdi, 64(%rbx)
	leaq	376(%rsp), %rdi
	movq	%rdi, 72(%rbx)
	leaq	384(%rsp), %rdi
	movq	%rdi, 80(%rbx)
	leaq	392(%rsp), %rdi
	movq	%rdi, 88(%rbx)
	leaq	400(%rsp), %rdi
	movq	%rdi, 96(%rbx)
	leaq	408(%rsp), %rdi
	movq	%rdi, 104(%rbx)
	leaq	416(%rsp), %rdi
	movq	%rdi, 112(%rbx)
	leaq	424(%rsp), %rdi
	movq	%rdi, 120(%rbx)
	movq	%rax, 128(%rbx)
	movq	%rcx, 136(%rbx)
	movq	%rdx, 144(%rbx)
	movq	%rsi, 152(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 200(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$320, %rsp                      # imm = 0x140
	.cfi_adjust_cfa_offset -320
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, .Lfunc_end0-_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3f800000                      # float 1
.LCPI1_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	xorl	%edi, %edi
	callq	hipSetDevice
	movq	8(%rbx), %rdi
	leaq	112(%rsp), %rsi
	movl	$10, %edx
	callq	__isoc23_strtol
	testl	%eax, %eax
	jle	.LBB1_20
# %bb.1:                                # %.preheader175.preheader
	movl	%eax, %eax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movl	$1, %r12d
	xorl	%eax, %eax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
.LBB1_2:                                # %.preheader175
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
                                        #       Child Loop BB1_4 Depth 3
                                        #       Child Loop BB1_6 Depth 3
                                        #       Child Loop BB1_10 Depth 3
                                        #       Child Loop BB1_14 Depth 3
	xorl	%ecx, %ecx
.LBB1_3:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_4 Depth 3
                                        #       Child Loop BB1_6 Depth 3
                                        #       Child Loop BB1_10 Depth 3
                                        #       Child Loop BB1_14 Depth 3
	movq	72(%rsp), %rax                  # 8-byte Reload
	movl	matrices_(,%rax,8), %r13d
	movl	matrices_+4(,%rax,8), %eax
	movl	blocks_(,%rcx,8), %ebp
	movq	%rcx, 104(%rsp)                 # 8-byte Spill
	movl	blocks_+4(,%rcx,8), %r14d
	xorl	%r15d, %r15d
	movq	%r15, 64(%rsp)
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	imull	%r13d, %eax
	movslq	%eax, %rbx
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r15, 56(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r15, 48(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r15, 40(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r15, 32(%rsp)
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r15, 24(%rsp)
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r15, 16(%rsp)
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	%r13d, 92(%rsp)                 # 4-byte Spill
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%r13d, %eax
	cltd
	idivl	%ebp
	incl	%r13d
	testl	%edx, %edx
	jne	.LBB1_4
# %bb.5:                                # %.preheader.preheader
                                        #   in Loop: Header=BB1_3 Depth=2
	movl	%eax, %ecx
	movl	12(%rsp), %esi                  # 4-byte Reload
.LBB1_6:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%esi, %eax
	cltd
	idivl	%r14d
	incl	%esi
	testl	%edx, %edx
	jne	.LBB1_6
# %bb.7:                                #   in Loop: Header=BB1_3 Depth=2
	movl	%eax, %ebx
	movl	%ecx, %eax
	shlq	$32, %rbx
	orq	%rax, %rbx
	movq	%r14, %r13
	shlq	$32, %r13
	orq	%rbp, %r13
	xorl	%edi, %edi
	callq	hipFree
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:                                #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edi
	movl	$1, %esi
	movl	$1, %edx
	movl	$1, %ecx
	movl	$1, %r8d
	movl	$1, %r9d
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm1
	movaps	%xmm0, %xmm2
	movaps	%xmm0, %xmm3
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
.LBB1_9:                                #   in Loop: Header=BB1_3 Depth=2
	callq	hipDeviceSynchronize
	movl	$10, %r15d
.LBB1_10:                               #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.11:                               #   in Loop: Header=BB1_10 Depth=3
	movl	$1, %edi
	movl	$1, %esi
	movl	$1, %edx
	movl	$1, %ecx
	movl	$1, %r8d
	movl	$1, %r9d
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm1
	movaps	%xmm0, %xmm2
	movaps	%xmm0, %xmm3
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
.LBB1_12:                               #   in Loop: Header=BB1_10 Depth=3
	decl	%r15d
	jne	.LBB1_10
# %bb.13:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1000, %r15d                    # imm = 0x3E8
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	movq	%rax, 80(%rsp)                  # 8-byte Spill
.LBB1_14:                               #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.15:                               #   in Loop: Header=BB1_14 Depth=3
	movl	$1, %edi
	movl	$1, %esi
	movl	$1, %edx
	movl	$1, %ecx
	movl	$1, %r8d
	movl	$1, %r9d
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm1
	movaps	%xmm0, %xmm2
	movaps	%xmm0, %xmm3
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
.LBB1_16:                               #   in Loop: Header=BB1_14 Depth=3
	decl	%r15d
	jne	.LBB1_14
# %bb.17:                               #   in Loop: Header=BB1_3 Depth=2
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	subq	80(%rsp), %rax                  # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI1_1(%rip), %xmm0
	movss	%xmm0, 80(%rsp)                 # 4-byte Spill
	movb	$91, 11(%rsp)
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	cmpq	$0, _ZSt4cout+16(%rax)
	je	.LBB1_21
# %bb.18:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$_ZSt4cout, %edi
	movl	$1, %edx
	leaq	11(%rsp), %r15
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_22
.LBB1_21:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$91, %esi
	callq	_ZNSo3putEc
	leaq	11(%rsp), %r15
.LBB1_22:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
                                        #   in Loop: Header=BB1_3 Depth=2
	movl	12(%rsp), %r13d                 # 4-byte Reload
	xorps	%xmm0, %xmm0
	cvtss2sd	80(%rsp), %xmm0                 # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movb	$44, 11(%rsp)
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_24
# %bb.23:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_25
.LBB1_24:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$44, %esi
	callq	_ZNSo3putEc
.LBB1_25:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit136
                                        #   in Loop: Header=BB1_3 Depth=2
	movb	$40, 11(%rsp)
	movq	(%rbx), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_27
# %bb.26:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_28
.LBB1_27:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$40, %esi
	callq	_ZNSo3putEc
.LBB1_28:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit139
                                        #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movb	$44, 11(%rsp)
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_30
# %bb.29:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_31
.LBB1_30:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$44, %esi
	callq	_ZNSo3putEc
.LBB1_31:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit142
                                        #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movb	$41, 11(%rsp)
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_33
# %bb.32:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_34
.LBB1_33:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$41, %esi
	callq	_ZNSo3putEc
.LBB1_34:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit145
                                        #   in Loop: Header=BB1_3 Depth=2
	movb	$44, 11(%rsp)
	movq	(%rbx), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_36
# %bb.35:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_37
.LBB1_36:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$44, %esi
	callq	_ZNSo3putEc
.LBB1_37:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit148
                                        #   in Loop: Header=BB1_3 Depth=2
	movb	$40, 11(%rsp)
	movq	(%rbx), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_39
# %bb.38:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_40
.LBB1_39:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$40, %esi
	callq	_ZNSo3putEc
.LBB1_40:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit151
                                        #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	92(%rsp), %esi                  # 4-byte Reload
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movb	$44, 11(%rsp)
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_42
# %bb.41:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_43
.LBB1_42:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$44, %esi
	callq	_ZNSo3putEc
.LBB1_43:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit154
                                        #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movb	$41, 11(%rsp)
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_45
# %bb.44:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_46
.LBB1_45:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$41, %esi
	callq	_ZNSo3putEc
.LBB1_46:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit157
                                        #   in Loop: Header=BB1_3 Depth=2
	movb	$93, 11(%rsp)
	movq	(%rbx), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rbx,%rax)
	je	.LBB1_48
# %bb.47:                               #   in Loop: Header=BB1_3 Depth=2
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %rbx
	jmp	.LBB1_49
.LBB1_48:                               #   in Loop: Header=BB1_3 Depth=2
	movq	%rbx, %rdi
	movl	$93, %esi
	callq	_ZNSo3putEc
.LBB1_49:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit160
                                        #   in Loop: Header=BB1_3 Depth=2
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	104(%rsp), %rcx                 # 8-byte Reload
	incq	%rcx
	cmpq	$20, %rcx
	jne	.LBB1_3
# %bb.19:                               #   in Loop: Header=BB1_2 Depth=1
	movq	72(%rsp), %rcx                  # 8-byte Reload
	incq	%rcx
	movq	%rcx, %rax
	movq	%rcx, 72(%rsp)                  # 8-byte Spill
	cmpq	96(%rsp), %rcx                  # 8-byte Folded Reload
	jne	.LBB1_2
.LBB1_20:                               # %._crit_edge
	xorl	%eax, %eax
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf,@object # @_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.p2align	3, 0x0
_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf:
	.quad	_Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.size	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, 8

	.type	blocks_,@object                 # @blocks_
	.data
	.globl	blocks_
	.p2align	4, 0x0
blocks_:
	.long	8                               # 0x8
	.long	8                               # 0x8
	.long	16                              # 0x10
	.long	16                              # 0x10
	.long	24                              # 0x18
	.long	24                              # 0x18
	.long	32                              # 0x20
	.long	32                              # 0x20
	.long	1                               # 0x1
	.long	64                              # 0x40
	.long	1                               # 0x1
	.long	128                             # 0x80
	.long	1                               # 0x1
	.long	192                             # 0xc0
	.long	1                               # 0x1
	.long	256                             # 0x100
	.long	1                               # 0x1
	.long	320                             # 0x140
	.long	1                               # 0x1
	.long	384                             # 0x180
	.long	1                               # 0x1
	.long	448                             # 0x1c0
	.long	1                               # 0x1
	.long	512                             # 0x200
	.long	1                               # 0x1
	.long	576                             # 0x240
	.long	1                               # 0x1
	.long	640                             # 0x280
	.long	1                               # 0x1
	.long	704                             # 0x2c0
	.long	1                               # 0x1
	.long	768                             # 0x300
	.long	1                               # 0x1
	.long	832                             # 0x340
	.long	1                               # 0x1
	.long	896                             # 0x380
	.long	1                               # 0x1
	.long	960                             # 0x3c0
	.long	1                               # 0x1
	.long	1024                            # 0x400
	.size	blocks_, 160

	.type	matrices_,@object               # @matrices_
	.globl	matrices_
	.p2align	4, 0x0
matrices_:
	.long	240                             # 0xf0
	.long	240                             # 0xf0
	.long	496                             # 0x1f0
	.long	496                             # 0x1f0
	.long	784                             # 0x310
	.long	784                             # 0x310
	.long	1016                            # 0x3f8
	.long	1016                            # 0x3f8
	.long	1232                            # 0x4d0
	.long	1232                            # 0x4d0
	.long	1680                            # 0x690
	.long	1680                            # 0x690
	.long	2024                            # 0x7e8
	.long	2024                            # 0x7e8
	.size	matrices_, 56

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf"
	.size	.L__unnamed_1, 68

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf ; -- Begin function _Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.globl	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
	.p2align	8
	.type	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf,@function
_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf: ; @_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x94
	s_load_b32 s12, s[0:1], 0x14
	v_and_b32_e32 v0, 31, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s13, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s12, v2
	s_cbranch_execz .LBB0_32
; %bb.1:
	s_clause 0x1
	s_load_b64 s[16:17], s[0:1], 0x18
	s_load_b128 s[28:31], s[0:1], 0x4
	s_mov_b32 s2, s15
	s_ashr_i32 s3, s15, 31
	s_load_b256 s[4:11], s[0:1], 0x20
	s_lshl_b64 s[18:19], s[2:3], 2
	s_mul_i32 s15, s15, s12
                                        ; implicit-def: $vgpr1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s16, s18
	s_addc_u32 s17, s17, s19
	s_mul_i32 s13, s15, s28
	s_load_b32 s3, s[16:17], 0x0
	s_load_b128 s[24:27], s[0:1], 0x78
	s_mul_i32 s12, s4, s12
                                        ; implicit-def: $sgpr16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add3_u32 v4, s12, s13, v2
	s_mov_b32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, s3, v2
	s_mul_i32 s3, s8, 3
	s_and_saveexec_b32 s13, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB0_8
; %bb.2:
	s_lshl_b32 s16, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s16, s3
	s_add_i32 s12, s12, 6
	s_cmp_ge_u32 s14, s7
	v_mul_lo_u32 v0, v4, s12
	v_mov_b32_e32 v1, 0
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, 1, v0
	v_add_nc_u32_e32 v4, 2, v0
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_dual_mov_b32 v5, v1 :: v_dual_add_nc_u32 v6, 3, v0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_dual_mov_b32 v7, v1 :: v_dual_add_nc_u32 v8, 4, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v10, vcc_lo, s26, v10
	v_mov_b32_e32 v9, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s27, v11, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v2, vcc_lo, s26, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s27, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s26, v4
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s26, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s27, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s26, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s27, v9, vcc_lo
	s_clause 0x4
	global_store_b32 v[10:11], v1, off
	global_store_b32 v[2:3], v1, off
	global_store_b32 v[4:5], v1, off
	global_store_b32 v[6:7], v1, off
	global_store_b32 v[8:9], v1, off
	s_cbranch_scc1 .LBB0_4
; %bb.3:
	s_lshl_b32 s17, s14, 1
	v_mov_b32_e32 v3, v1
	v_add3_u32 v2, s17, 6, v0
	v_mov_b32_e32 v5, v1
	v_add3_u32 v4, s17, 7, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s26, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s27, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s26, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	s_clause 0x1
	global_store_b32 v[2:3], v1, off
	global_store_b32 v[4:5], v1, off
.LBB0_4:
	s_cmp_ge_u32 s14, s8
	s_cbranch_scc1 .LBB0_6
; %bb.5:
	s_mul_i32 s12, s14, 3
	v_mov_b32_e32 v2, 0
	s_add_i32 s16, s16, s12
	s_mov_b32 s12, -1
	v_add3_u32 v1, s16, 6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add3_u32 v1, s16, 7, v0
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s26, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s27, v4, vcc_lo
	v_add3_u32 v1, s16, 8, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s26, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	s_mov_b32 s16, 0
	s_clause 0x1
	global_store_b32 v[3:4], v2, off
	global_store_b32 v[5:6], v2, off
	s_branch .LBB0_7
.LBB0_6:
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $vgpr1
.LBB0_7:                                ; %Flow448
	s_and_b32 s12, s12, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_8:                                ; %Flow447
	s_or_saveexec_b32 s13, s13
	v_mov_b32_e32 v3, s16
	s_xor_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB0_30
; %bb.9:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x58
	s_load_b128 s[36:39], s[0:1], 0x40
	s_load_b32 s1, s[0:1], 0x50
	v_add_nc_u32_e32 v0, s15, v2
	s_cmp_lg_u32 s14, 0
	s_mov_b32 s28, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v0, 2, v0
	s_cbranch_scc1 .LBB0_11
; %bb.10:
	v_mov_b32_e32 v1, 0
	s_lshl_b32 s0, s7, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v0
	s_add_i32 s0, s0, s3
	v_mov_b32_e32 v6, v1
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_add_i32 s0, s0, 6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	global_load_b32 v9, v[2:3], off
	v_mul_lo_u32 v2, v4, s0
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s26, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v9, off
	global_load_b32 v3, v[5:6], off
	v_dual_mov_b32 v6, v1 :: v_dual_add_nc_u32 v5, 1, v2
	v_dual_mov_b32 v8, v1 :: v_dual_add_nc_u32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s26, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v3, off
	global_load_b32 v3, v[7:8], off
	v_dual_mov_b32 v6, v1 :: v_dual_add_nc_u32 v5, 2, v2
	v_dual_mov_b32 v8, v1 :: v_dual_add_nc_u32 v7, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s26, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v3, off
	global_load_b32 v3, v[7:8], off
	v_dual_mov_b32 v6, v1 :: v_dual_add_nc_u32 v5, 3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s26, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v3, off
	v_add_nc_u32_e32 v5, 4, v2
	v_add_nc_u32_e32 v2, 5, v2
	v_dual_mov_b32 v8, v1 :: v_dual_add_nc_u32 v7, 4, v0
	v_mov_b32_e32 v6, v1
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	v_add_co_u32 v7, vcc_lo, s16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s26, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v1, vcc_lo, s26, v1
	v_cvt_f32_u32_e32 v8, s4
	v_add_co_ci_u32_e32 v2, vcc_lo, s27, v2, vcc_lo
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b32 v[5:6], v7, off
	global_store_b32 v[1:2], v8, off
.LBB0_11:
	s_cmp_ge_u32 s14, s11
	s_cbranch_scc0 .LBB0_14
; %bb.12:
	s_cmp_lt_u32 s14, s7
	s_mov_b32 s15, 0
	s_cbranch_scc0 .LBB0_15
; %bb.13:
	s_lshl_b32 s0, s14, 1
	s_mov_b32 s28, -1
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s16, 0
	s_branch .LBB0_16
.LBB0_14:
	s_mov_b32 s15, -1
.LBB0_15:
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr0
.LBB0_16:                               ; %Flow
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
	s_and_b32 vcc_lo, exec_lo, s15
	s_mul_i32 s15, s31, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s15, s2
	s_cbranch_vccz .LBB0_18
; %bb.17:
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 2, v0
	s_mul_i32 s0, s4, s29
	s_mul_i32 s4, s2, s29
	s_mov_b32 s28, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_mul_i32 s4, s4, s5
	s_lshl_b32 s4, s4, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s18, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	v_add_co_u32 v5, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	global_load_b32 v7, v[2:3], off
	v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, 1, v0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v9, v[5:6], off
	global_load_b32 v3, v[2:3], off
	v_mov_b32_e32 v2, v1
	s_waitcnt vmcnt(2)
	v_cvt_u32_f32_e32 v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v1, s0, v10, 2
	s_lshl_b32 s0, s14, 1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s20, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s21, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_cvt_u32_f32_e32 v11, v3
	global_load_b128 v[5:8], v[1:2], off
	v_mul_lo_u32 v1, s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 1, v1
	v_cvt_u32_f32_e32 v1, v9
	v_add3_u32 v9, s0, s9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v11, s30, v[1:2]
	v_cvt_f32_u32_e32 v1, v1
	v_mul_lo_u32 v3, s15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, s4, v3
	v_add_nc_u32_e32 v9, s15, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v2, vcc_lo, s22, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, s22, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[2:3], off
	global_load_b32 v12, v[9:10], off
	v_cvt_f32_u32_e32 v2, v11
	s_waitcnt vmcnt(2)
	v_fma_f32 v5, s37, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v6, s38, v2, v6
	v_fmac_f32_e32 v8, s38, v2
	v_fma_f32 v1, s37, v1, v7
	v_cvt_i32_f32_e32 v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v5, v6
	v_cvt_i32_f32_e32 v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v1, v1
	v_sub_nc_u32_e32 v11, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v13, v1, v2
	v_cvt_f64_i32_e32 v[1:2], v2
	v_cvt_f64_i32_e32 v[5:6], v5
	v_cvt_f64_i32_e32 v[7:8], v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[9:10], v13
	v_fma_f64 v[5:6], v[7:8], 0.5, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[1:2], v[9:10], 0.5, v[1:2]
	v_cvt_f32_f64_e32 v5, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v1, v[1:2]
	v_cvt_f32_i32_e32 v2, v11
	v_cvt_f32_i32_e32 v6, v13
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v5, v3, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v1, v12, v6 :: v_dual_mul_f32 v2, s1, v5
	v_mul_f32_e32 v1, s39, v1
.LBB0_18:                               ; %Flow445
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB0_20
; %bb.19:                               ; %.sink.split
	s_lshl_b32 s1, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s3
	s_add_i32 s1, s1, 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v4, s1, s[0:1]
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, 6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[6:7]
	v_add_nc_u32_e32 v6, 7, v5
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s26, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s26, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	s_clause 0x1
	global_store_b32 v[7:8], v2, off
	global_store_b32 v[5:6], v1, off
.LBB0_20:
	s_cmp_ge_u32 s14, s36
	s_cbranch_scc0 .LBB0_23
; %bb.21:
	s_cmp_lt_u32 s14, s8
	s_cbranch_scc0 .LBB0_24
; %bb.22:
	s_lshl_b32 s0, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s0, s3
	s_add_i32 s1, s1, 6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_lo_u32 v1, v4, s1
	s_mul_i32 s1, s14, 3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, s0, s1, v1
	v_mov_b32_e32 v2, 0
	s_mov_b32 s1, 0
	s_or_b32 s0, s12, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 6, v3
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, 7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_add_co_u32 v5, vcc_lo, s26, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v6, vcc_lo
	v_add_nc_u32_e32 v1, 8, v3
	v_add_co_u32 v7, vcc_lo, s26, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v8, vcc_lo
	s_clause 0x1
	global_store_b32 v[5:6], v2, off
	global_store_b32 v[7:8], v2, off
	s_branch .LBB0_25
.LBB0_23:
	s_mov_b32 s4, -1
	s_mov_b32 s0, s12
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr1
	s_branch .LBB0_26
.LBB0_24:
	s_mov_b32 s0, s12
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr1
.LBB0_25:                               ; %Flow451
	s_mov_b32 s4, 0
.LBB0_26:                               ; %Flow450
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_28
; %bb.27:
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
	s_mul_i32 s1, s36, 3
	s_mul_i32 s14, s14, 3
	s_or_b32 s0, s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v0, 2, v0
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v7, vcc_lo, s18, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	global_load_b32 v0, v[7:8], off
	v_add_co_u32 v2, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[5:6], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(2)
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v3, s1, v0
	s_waitcnt vmcnt(1)
	v_cvt_u32_f32_e32 v0, v5
	s_waitcnt vmcnt(0)
	v_cvt_u32_f32_e32 v5, v2
	s_mul_i32 s1, s2, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s6
	s_mul_i32 s1, s1, 3
	v_add3_u32 v6, s14, s10, v3
	v_mad_u64_u32 v[2:3], null, v5, s30, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, s15, v6
	v_add3_u32 v2, v2, s1, v0
	s_lshl_b32 s1, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s2, s1, s3
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v5, s15, v2
	s_add_i32 s2, s2, 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, v4, s2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v11, s1, s14, v0
	global_load_b32 v9, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, 0x3fb8aa3b, v9
	v_add_nc_u32_e32 v7, s15, v5
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v2, vcc_lo, s24, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s24, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v8, v[2:3], off
	global_load_b32 v10, v[5:6], off
	v_fma_f32 v5, 0x3fb8aa3b, v9, -v4
	v_add_nc_u32_e32 v0, 6, v11
	v_rndne_f32_e32 v7, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, 0x32a5705f, v9
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v7
	v_cvt_i32_f32_e32 v7, v7
	v_add_f32_e32 v4, v4, v5
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v6, 0x3fb8aa3b, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fb8aa3b, v8, -v6
	v_rndne_f32_e32 v13, v6
	v_fmac_f32_e32 v12, 0x32a5705f, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v13
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v0, 0x3fb8aa3b, v10 :: v_dual_add_f32 v5, v6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_rndne_f32_e32 v15, v0
	v_fma_f32 v14, 0x3fb8aa3b, v10, -v0
	v_exp_f32_e32 v12, v4
	v_add_co_u32 v4, vcc_lo, s26, v2
	v_sub_f32_e32 v16, v0, v15
	v_add_nc_u32_e32 v0, 7, v11
	v_fmac_f32_e32 v14, 0x32a5705f, v10
	v_cvt_i32_f32_e32 v2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_f32_e32 v6, v16, v14
	v_exp_f32_e32 v14, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v3, vcc_lo
	v_ldexp_f32 v12, v12, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(TRANS32_DEP_2)
	v_exp_f32_e32 v16, v6
	v_add_co_u32 v6, vcc_lo, s26, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s27, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_cvt_i32_f32_e32 v3, v15
	v_ldexp_f32 v0, v14, v2
	v_cndmask_b32_e32 v2, 0, v12, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v8
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_4)
	v_ldexp_f32 v1, v16, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v8
	v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
	s_clause 0x1
	global_store_b32 v[4:5], v2, off
	global_store_b32 v[6:7], v0, off
	v_cndmask_b32_e32 v3, 0x7f800000, v1, vcc_lo
	v_add_nc_u32_e32 v1, 8, v11
	s_branch .LBB0_29
.LBB0_28:
	v_mov_b32_e32 v3, s1
.LBB0_29:                               ; %Flow452
	s_and_not1_b32 s1, s12, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s12, s1, s0
.LBB0_30:                               ; %Flow449
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s12
	s_cbranch_execz .LBB0_32
; %bb.31:                               ; %.sink.split361
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s26, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s27, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_32:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 392
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf, .Lfunc_end0-_Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2988
; NumSgprs: 42
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         128
        .size:           8
        .value_kind:     global_buffer
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         140
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         144
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         148
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         150
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         152
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         154
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         156
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         158
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         200
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 392
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     42
    .sgpr_spill_count: 0
    .symbol:         _Z25cudaS_ssdToOutput_kernelsjjjjjjPjjjjjjjjjjffffPKfS1_S1_S1_S1_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
