/***************************************************************************//**
 * \file LHS2.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the left hand side for the poission solve
 */

#include "LHS2.h"

namespace kernels
{
/*
 * calculates the boundary terms for the left hand side matrix for the poisson solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 * param dt change in time
 */
__global__
void LHS2_BC(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x;
	if (ip >= nx*ny)
		return;
	int	I	= ip % nx,
		J	= ip / nx;
	if (I != 0 && I != nx-1 && J != 0 && J != ny-1)
		return;
	int numE = 0;
	if (J == 0)
	{
		numE = I*4;
		if (I!=0)
			numE-=1;
	}
	else if (J == ny-1)
	{
		numE = nx*4-2 + (J-1)*(nx*5-2) + I*4;
		if (I!=0)
			numE-=1;
	}
	else
	{
		numE = nx*4-2   +    (J-1)*(nx*5 - 2) + I*5;
		if (I != 0)
			numE -= 1;
	}

	double temp = 0;

	//EAST
	//if not on the east wall and east is outside the body, add east term
	if (I != nx-1)//not at east boundry
	{
		row[numE] = ip;
		col[numE] = ip + 1;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
		numE++;
		temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
	}

	//WEST
	//if not on west wall and west is outside the body, add west term
	if (I != 0)//not at west boundary
	{
		row[numE] = ip;
		col[numE] = ip - 1;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		numE++;
	}

	//NORTH
	//if not on north wall and north is outside the body, add north term
	if (J != ny-1)//not at north boundry
	{
		row[numE] = ip;
		col[numE] = ip + nx;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		numE++;
	}

	//SOUTH
	//if not on south wall and south is outside the body, add south term
	if (J != 0)//not at south boundry
	{
		row[numE] = ip;
		col[numE] = ip - nx;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		numE++;
	}

	//MID
	row[numE] = ip;
	col[numE] = ip;
	val[numE] = temp;

	//do some jank so the solver works, although this modifies the matricies it doesn't really change the results
	if (ip == 0)
		val[numE] += val[numE];
		//val[numE] = 0;
		//val[numE] *= val[numE];
}

/*
 * calculates the middle terms for the left hand side matrix for the poisson solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 * param dt change in time
 */
__global__
void LHS2_mid_nobody(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x;
	if (ip >= nx*ny)
		return;
	int	I	= ip % nx,
		J	= ip / nx;

	if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
		return;

	int numE= nx*4-2   +    (J-1)*(nx*5 - 2) + I*5 - 1;
	double temp = 0;
	//EAST
	row[numE] = ip;
	col[numE] = ip + 1;
	val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
	numE++;
	temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);

	//WEST
	row[numE] = ip;
	col[numE] = ip - 1;
	val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
	temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
	numE++;

	//NORTH
	row[numE] = ip;
	col[numE] = ip + nx;
	val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
	temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
	numE++;

	//SOUTH
	row[numE] = ip;
	col[numE] = ip - nx;
	val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
	temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
	numE++;

	//MID
	row[numE] = ip;
	col[numE] = ip;
	val[numE] = temp;

	//do some jank so the solver works, although this modifies the matricies it doesn't really change the results
	if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
	{
		val[numE] += val[numE];
	}
}























}

	.file	"tmpxft_0021a994_00000000-6_LHS2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
	.type	_Z50__device_stub__ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, @function
_Z50__device_stub__ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, .-_Z50__device_stub__ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
	.globl	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.type	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid, @function
_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
	.cfi_endproc
.LFE2033:
	.size	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid, .-_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.globl	_Z59__device_stub__ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
	.type	_Z59__device_stub__ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, @function
_Z59__device_stub__ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z59__device_stub__ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, .-_Z59__device_stub__ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
	.globl	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.type	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid, @function
_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
	.cfi_endproc
.LFE2035:
	.size	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid, .-_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid"
.LC1:
	.string	"_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/***************************************************************************//**
 * \file LHS2.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the left hand side for the poission solve
 */


#include <hip/hip_runtime.h>
#include "LHS2.h"

namespace kernels
{
/*
 * calculates the boundary terms for the left hand side matrix for the poisson solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 * param dt change in time
 */
__global__
void LHS2_BC(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x;
	if (ip >= nx*ny)
		return;
	int	I	= ip % nx,
		J	= ip / nx;
	if (I != 0 && I != nx-1 && J != 0 && J != ny-1)
		return;
	int numE = 0;
	if (J == 0)
	{
		numE = I*4;
		if (I!=0)
			numE-=1;
	}
	else if (J == ny-1)
	{
		numE = nx*4-2 + (J-1)*(nx*5-2) + I*4;
		if (I!=0)
			numE-=1;
	}
	else
	{
		numE = nx*4-2   +    (J-1)*(nx*5 - 2) + I*5;
		if (I != 0)
			numE -= 1;
	}

	double temp = 0;

	//EAST
	//if not on the east wall and east is outside the body, add east term
	if (I != nx-1)//not at east boundry
	{
		row[numE] = ip;
		col[numE] = ip + 1;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
		numE++;
		temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
	}

	//WEST
	//if not on west wall and west is outside the body, add west term
	if (I != 0)//not at west boundary
	{
		row[numE] = ip;
		col[numE] = ip - 1;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		numE++;
	}

	//NORTH
	//if not on north wall and north is outside the body, add north term
	if (J != ny-1)//not at north boundry
	{
		row[numE] = ip;
		col[numE] = ip + nx;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		numE++;
	}

	//SOUTH
	//if not on south wall and south is outside the body, add south term
	if (J != 0)//not at south boundry
	{
		row[numE] = ip;
		col[numE] = ip - nx;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		numE++;
	}

	//MID
	row[numE] = ip;
	col[numE] = ip;
	val[numE] = temp;

	//do some jank so the solver works, although this modifies the matricies it doesn't really change the results
	if (ip == 0)
		val[numE] += val[numE];
		//val[numE] = 0;
		//val[numE] *= val[numE];
}

/*
 * calculates the middle terms for the left hand side matrix for the poisson solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 * param dt change in time
 */
__global__
void LHS2_mid_nobody(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x;
	if (ip >= nx*ny)
		return;
	int	I	= ip % nx,
		J	= ip / nx;

	if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
		return;

	int numE= nx*4-2   +    (J-1)*(nx*5 - 2) + I*5 - 1;
	double temp = 0;
	//EAST
	row[numE] = ip;
	col[numE] = ip + 1;
	val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
	numE++;
	temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);

	//WEST
	row[numE] = ip;
	col[numE] = ip - 1;
	val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
	temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
	numE++;

	//NORTH
	row[numE] = ip;
	col[numE] = ip + nx;
	val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
	temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
	numE++;

	//SOUTH
	row[numE] = ip;
	col[numE] = ip - nx;
	val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
	temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
	numE++;

	//MID
	row[numE] = ip;
	col[numE] = ip;
	val[numE] = temp;

	//do some jank so the solver works, although this modifies the matricies it doesn't really change the results
	if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
	{
		val[numE] += val[numE];
	}
}























}

	.text
	.file	"LHS2.hip"
	.globl	_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid # -- Begin function _ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid
	.type	_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid,@function
_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid: # @_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid, .Lfunc_end0-_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid
	.cfi_endproc
                                        # -- End function
	.globl	_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid # -- Begin function _ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.type	_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid,@function
_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid: # @_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid, .Lfunc_end1-_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid,@object # @_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.section	.rodata,"a",@progbits
	.globl	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.p2align	3, 0x0
_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid:
	.quad	_ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid
	.size	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid, 8

	.type	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid,@object # @_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.globl	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.p2align	3, 0x0
_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid:
	.quad	_ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.size	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid"
	.size	.L__unnamed_1, 37

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid"
	.size	.L__unnamed_2, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN7kernels22__device_stub__LHS2_BCEPiS0_PdS1_S1_iid
	.addrsig_sym _ZN7kernels30__device_stub__LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.addrsig_sym _ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid ; -- Begin function _ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.globl	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
	.p2align	8
	.type	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid,@function
_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid:   ; @_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b64 s[12:13], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s13, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_21
; %bb.1:
	s_ashr_i32 s2, s12, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s3, s12, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s3, s3, s2
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s2, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v3
	v_mul_lo_u32 v0, v4, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v1, v0
	v_cmp_eq_u32_e64 s5, 0, v8
	v_cmp_ne_u32_e64 s3, 0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s2, s5
	s_and_saveexec_b32 s6, s3
; %bb.2:
	s_add_i32 s2, s12, -1
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cmp_eq_u32_e64 s2, s2, v8
	s_add_i32 s4, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s4, s4, v4
	s_or_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s4
	s_and_not1_b32 s4, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s4, s2
; %bb.3:                                ; %Flow202
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_21
; %bb.4:
	v_cmp_ne_u32_e64 s2, 0, v4
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_10
; %bb.5:
	s_lshl_b32 s6, s12, 2
	v_add_nc_u32_e32 v0, -1, v4
	s_add_i32 s6, s6, -2
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s6, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, v0, s7, s[6:7]
	s_add_i32 s6, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s6, v4
	s_and_saveexec_b32 s6, vcc_lo
	s_xor_b32 s6, exec_lo, s6
; %bb.6:
	v_mad_u64_u32 v[2:3], null, v8, 5, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v2, 0, s5
	v_add_nc_u32_e32 v2, v5, v0
                                        ; implicit-def: $vgpr5_vgpr6
; %bb.7:                                ; %Flow
	s_and_not1_saveexec_b32 s6, s6
; %bb.8:
	v_lshl_add_u32 v0, v8, 2, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, 0, s5
	v_add_nc_u32_e32 v2, v5, v0
; %bb.9:                                ; %Flow200
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_10:                               ; %Flow201
	s_and_not1_saveexec_b32 s4, s4
; %bb.11:
	v_lshl_add_u32 v0, v8, 2, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v0, 0, s5
; %bb.12:
	s_or_b32 exec_lo, exec_lo, s4
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[14:15], s[0:1], 0x20
	s_load_b64 s[0:1], s[0:1], 0x30
	s_add_i32 s16, s12, -1
	v_mov_b32_e32 v6, 0
	v_cmp_ne_u32_e32 vcc_lo, s16, v8
	v_mov_b32_e32 v7, 0
	v_ashrrev_i32_e32 v9, 31, v8
	s_and_saveexec_b32 s16, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 3, v[8:9]
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v0, 1, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b128 v[10:13], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[10:11], v[12:13]
	v_mul_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], 0.5
	v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], -s[0:1]
	v_div_scale_f64 v[18:19], vcc_lo, -s[0:1], v[10:11], -s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
	v_div_fixup_f64 v[10:11], v[12:13], v[10:11], -s[0:1]
	v_lshlrev_b64 v[12:13], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_store_b64 v[12:13], v[10:11], off
	global_load_b128 v[10:13], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[5:6], v[10:11], v[5:6]
	v_mul_f64 v[5:6], v[5:6], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[10:11], null, v[5:6], v[5:6], s[0:1]
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, s[0:1], v[5:6], s[0:1]
	v_mul_f64 v[16:17], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[5:6], v[10:11], v[5:6], s[0:1]
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	v_add_co_u32 v12, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_store_b32 v[12:13], v1, off
	global_store_b32 v[10:11], v0, off
	v_add_f64 v[6:7], v[5:6], 0
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s16
	s_and_saveexec_b32 s16, s3
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v0, -1, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v9, vcc_lo
	global_load_b128 v[8:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	v_mul_f64 v[8:9], v[8:9], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], -s[0:1]
	v_div_scale_f64 v[18:19], vcc_lo, -s[0:1], v[8:9], -s[0:1]
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[18:19]
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[8:9], v[10:11], v[8:9], -s[0:1]
	v_lshlrev_b64 v[10:11], 3, v[2:3]
	v_add_co_u32 v10, vcc_lo, s8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_store_b64 v[10:11], v[8:9], off
	global_load_b128 v[8:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], 0.5
	v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, s[0:1], v[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[14:15], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
	v_div_fixup_f64 v[8:9], v[10:11], v[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	v_add_co_u32 v10, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_store_b32 v[10:11], v1, off
	global_store_b32 v[8:9], v0, off
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s3, s13, -1
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_ne_u32_e32 vcc_lo, s3, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_18
; %bb.17:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v0, s12, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, vcc_lo, s14, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v9, vcc_lo
	global_load_b128 v[8:11], v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[8:9], v[10:11]
	v_mul_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], 0.5
	v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], -s[0:1]
	v_div_scale_f64 v[18:19], vcc_lo, -s[0:1], v[8:9], -s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[16:17]
	v_div_fixup_f64 v[8:9], v[10:11], v[8:9], -s[0:1]
	v_lshlrev_b64 v[10:11], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_store_b64 v[10:11], v[8:9], off
	global_load_b128 v[8:11], v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], v[10:11]
	v_mul_f64 v[8:9], v[8:9], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], s[0:1]
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, s[0:1], v[8:9], s[0:1]
	v_mul_f64 v[16:17], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[8:9], v[10:11], v[8:9], s[0:1]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_store_b32 v[10:11], v1, off
	global_store_b32 v[8:9], v0, off
.LBB0_18:
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_lshlrev_b64 v[3:4], 3, v[4:5]
	v_subrev_nc_u32_e32 v0, s12, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v4, vcc_lo
	global_load_b128 v[8:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[10:11], v[3:4]
	v_mul_f64 v[3:4], v[3:4], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[8:9], null, v[3:4], v[3:4], -s[0:1]
	v_div_scale_f64 v[16:17], vcc_lo, -s[0:1], v[3:4], -s[0:1]
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
	v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
	v_mul_f64 v[14:15], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[8:9], v[14:15], v[16:17]
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[8:9], v[3:4], -s[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[8:9], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_store_b64 v[8:9], v[4:5], off
	global_load_b128 v[8:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[10:11], v[4:5]
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], s[0:1]
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_div_scale_f64 v[12:13], vcc_lo, s[0:1], v[4:5], s[0:1]
	v_mul_f64 v[14:15], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[8:9], v[4:5], s[0:1]
	v_add_f64 v[6:7], v[6:7], v[4:5]
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_store_b32 v[8:9], v1, off
	global_store_b32 v[3:4], v0, off
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, 0x80000000, v7, vcc_lo
	v_cndmask_b32_e32 v3, 0, v6, vcc_lo
	v_add_f64 v[4:5], v[6:7], v[3:4]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b32 v[8:9], v1, off
	global_store_b32 v[6:7], v1, off
	global_store_b64 v[2:3], v[4:5], off
.LBB0_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid, .Lfunc_end0-_ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2472
; NumSgprs: 19
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid ; -- Begin function _ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.globl	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
	.p2align	8
	.type	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid,@function
_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid: ; @_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b64 s[12:13], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s13, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_6
; %bb.1:
	s_ashr_i32 s2, s12, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s3, s12, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s3, s3, s2
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s2, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v3
	v_mul_lo_u32 v0, v4, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_6
; %bb.2:
	s_add_i32 s2, s12, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cmp_ne_u32_e64 s2, s2, v2
	s_add_i32 s3, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s3, s3, v4
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_6
; %bb.3:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v3, 31, v2
	s_lshl_b32 s2, s12, 2
	v_add_nc_u32_e32 v0, -1, v4
	s_add_i32 s2, s2, -2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[2:3]
	s_add_i32 s3, s2, s12
	v_lshl_add_u32 v2, v2, 2, v2
	v_mul_lo_u32 v0, v0, s3
	v_add3_u32 v2, s2, v2, v0
	v_add_nc_u32_e32 v0, 1, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
	s_load_b64 s[10:11], s[0:1], 0x30
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b64 s[0:1], s[0:1], 0x20
	global_load_b128 v[5:8], v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[5:6], v[5:6], v[7:8]
	v_mul_f64 v[5:6], v[5:6], 0.5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], -s[10:11]
	v_div_scale_f64 v[15:16], vcc_lo, -s[10:11], v[5:6], -s[10:11]
	v_rcp_f64_e32 v[11:12], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[13:14], v[15:16]
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[5:6], v[7:8], v[5:6], -s[10:11]
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v12, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b32 v[12:13], v1, off offset:-4
	global_store_b32 v[14:15], v0, off offset:-4
	global_store_b64 v[2:3], v[5:6], off offset:-8
	s_clause 0x1
	global_load_b64 v[16:17], v[9:10], off offset:8
	global_load_b128 v[5:8], v[9:10], off offset:-8
	v_add_nc_u32_e32 v0, -1, v1
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[7:8], v[16:17]
	v_add_f64 v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[7:8], v[16:17]
	v_mul_f64 v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[16:17], 0.5
	v_mul_f64 v[5:6], v[5:6], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[7:8], null, v[16:17], v[16:17], s[10:11]
	v_div_scale_f64 v[18:19], null, v[5:6], v[5:6], -s[10:11]
	v_div_scale_f64 v[28:29], vcc_lo, s[10:11], v[16:17], s[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[20:21], v[7:8]
	v_rcp_f64_e32 v[22:23], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[7:8], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[7:8], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_div_scale_f64 v[24:25], s2, -s[10:11], v[5:6], -s[10:11]
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[26:27], v[28:29], v[20:21]
	v_mul_f64 v[30:31], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], -v[7:8], v[26:27], v[28:29]
	v_fma_f64 v[18:19], -v[18:19], v[30:31], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[20:21], v[7:8], v[20:21], v[26:27]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[7:8], v[18:19], v[22:23], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[16:17], v[20:21], v[16:17], s[10:11]
	v_div_fixup_f64 v[6:7], v[7:8], v[5:6], -s[10:11]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v18, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s1, v5, vcc_lo
	v_add_f64 v[16:17], v[16:17], 0
	global_store_b64 v[2:3], v[6:7], off
	global_load_b128 v[4:7], v[9:10], off offset:-8
	global_load_b128 v[8:11], v[18:19], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], v[6:7], v[4:5]
	v_mul_f64 v[6:7], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[8:9], v[4:5], 0.5
	v_mul_f64 v[4:5], v[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[8:9], v[8:9], s[10:11]
	v_div_scale_f64 v[10:11], null, v[4:5], v[4:5], -s[10:11]
	v_div_scale_f64 v[30:31], vcc_lo, s[10:11], v[8:9], s[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[22:23], v[6:7]
	v_rcp_f64_e32 v[24:25], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[6:7], v[22:23], 1.0
	v_fma_f64 v[28:29], -v[10:11], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], -v[6:7], v[22:23], 1.0
	v_fma_f64 v[28:29], -v[10:11], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_div_scale_f64 v[26:27], s0, -s[10:11], v[4:5], -s[10:11]
	v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[28:29], v[30:31], v[22:23]
	v_mul_f64 v[32:33], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], -v[6:7], v[28:29], v[30:31]
	v_fma_f64 v[10:11], -v[10:11], v[32:33], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[22:23], v[6:7], v[22:23], v[28:29]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[6:7], v[10:11], v[24:25], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[8:9], v[22:23], v[8:9], s[10:11]
	v_div_fixup_f64 v[4:5], v[6:7], v[4:5], -s[10:11]
	v_add_nc_u32_e32 v6, s12, v1
	global_store_b32 v[12:13], v1, off
	global_store_b32 v[14:15], v0, off
	global_store_b32 v[12:13], v1, off offset:4
	global_store_b32 v[14:15], v6, off offset:4
	global_store_b64 v[2:3], v[4:5], off offset:8
	s_clause 0x1
	global_load_b64 v[10:11], v[18:19], off offset:8
	global_load_b128 v[4:7], v[18:19], off offset:-8
	v_subrev_nc_u32_e32 v0, s12, v1
	v_add_f64 v[8:9], v[16:17], v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[6:7], v[10:11]
	v_add_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], v[6:7], v[10:11]
	v_mul_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], v[10:11], 0.5
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[10:11], v[10:11], s[10:11]
	v_div_scale_f64 v[24:25], null, v[4:5], v[4:5], -s[10:11]
	v_div_scale_f64 v[34:35], vcc_lo, s[10:11], v[10:11], s[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[26:27], v[6:7]
	v_rcp_f64_e32 v[28:29], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[6:7], v[26:27], 1.0
	v_fma_f64 v[32:33], -v[24:25], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], -v[6:7], v[26:27], 1.0
	v_fma_f64 v[32:33], -v[24:25], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27]
	v_div_scale_f64 v[30:31], s0, -s[10:11], v[4:5], -s[10:11]
	v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[34:35], v[26:27]
	v_mul_f64 v[36:37], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], -v[6:7], v[32:33], v[34:35]
	v_fma_f64 v[24:25], -v[24:25], v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[26:27], v[6:7], v[26:27], v[32:33]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[6:7], v[24:25], v[28:29], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[10:11], v[26:27], v[10:11], s[10:11]
	v_div_fixup_f64 v[4:5], v[6:7], v[4:5], -s[10:11]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	global_store_b64 v[2:3], v[4:5], off offset:16
	global_load_b128 v[4:7], v[18:19], off offset:-8
	global_store_b32 v[12:13], v1, off offset:8
	global_store_b32 v[14:15], v0, off offset:8
	global_store_b32 v[12:13], v1, off offset:12
	global_store_b32 v[14:15], v1, off offset:12
	global_load_b32 v0, v[12:13], off offset:12
	s_waitcnt vmcnt(1)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[6:7], v[4:5]
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], s[10:11]
	v_rcp_f64_e32 v[18:19], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[6:7], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[18:19], v[24:25], v[18:19]
	v_fma_f64 v[14:15], -v[6:7], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, s[10:11], v[4:5], s[10:11]
	v_mul_f64 v[18:19], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[18:19], v[14:15]
	v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[18:19]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[6:7], v[4:5], s[10:11]
	v_add_f64 v[4:5], v[8:9], v[4:5]
	global_store_b64 v[2:3], v[4:5], off offset:24
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_6
; %bb.4:
	s_lshr_b32 s0, s13, 31
	s_lshr_b32 s1, s12, 31
	s_add_i32 s0, s13, s0
	s_add_i32 s1, s12, s1
	s_ashr_i32 s0, s0, 1
	s_ashr_i32 s1, s1, 1
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s1
	v_cmp_eq_u32_e32 vcc_lo, s0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_add_f64 v[0:1], v[4:5], v[4:5]
	global_store_b64 v[2:3], v[0:1], off offset:24
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid, .Lfunc_end1-_ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1960
; NumSgprs: 18
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels7LHS2_BCEPiS0_PdS1_S1_iid.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels15LHS2_mid_nobodyEPiS0_PdS1_S1_iid.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
