/**
 * Vector Addition with CUDA (Fall 2016):
 * 
 * Members:
 * Emanuelle Crespi, Tolga Keskinoglu
 *
 * This test implements a parallel vector addition: C = A + B
 * discussed in the methodology section of Optimizing CPU-GPU Interactions.
 *
 * The following code makes use of the function call vectorAdd( int n, int *A, int *B, int *C )
 * to perform a vector addition of two arrays A and B of length n 
 *
 * The output is verified before the program terminates to see that every 
 * element of index i has C[i] == A[i] + B[i]
 *
 * We can see that there is a significant speedup in comparison to the time it takes
 * to perform the vectorAdd in the serial code.
 *
 * The output of the performance is displayed in seconds. 
 * The runtime results are to be compared with the performance of vector.c
 *
 */

// System includes
#include <stdlib.h>
#include <stdio.h>
#include <time.h>

// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// defines dimension of vectored data as XDIM
#define XDIM 413124 
#define THREADS_PER_BLOCK 1024

// Performs a vector addition of arrays v1 and v2
// in parallel on the GPU.  The index i is specified as 
// a particular thread within some block on the device
// This allows for parallel computation on the device
__global__ void vectorAdd( int n, int *v1, int *v2, int *v ){
	int i =  blockIdx.x*blockDim.x + threadIdx.x;
	if( i < n ){ 
		v[i] = v1[i] + v2[i];
	}	
}

int main(void){
	int i, v1[XDIM], v2[XDIM], v[XDIM];
        int *d_v1, *d_v2, *d_v, size = sizeof(int)*XDIM; 
	cudaError_t error;

	//Populate data in v1 and v2
	for( i = 0; i < XDIM; i++ ){
		v1[i] = (i % 5)+1; 
		v2[i] = (i % 5)+1;
	}

	//set up space on GPU device
	cudaMalloc( (void **) &d_v1, size );
	cudaMalloc( (void **) &d_v2, size );
	cudaMalloc( (void **) &d_v, size );

	//write data to GPU device
	cudaMemcpy( d_v1, v1, size, cudaMemcpyHostToDevice ); 
	cudaMemcpy( d_v2, v2, size, cudaMemcpyHostToDevice ); 
	/*******************************for testing purposes****************************************
	 *******************************************************************************************/
	cudaDeviceSynchronize();

    	// Allocate CUDA events that we'll use for timing
    	cudaEvent_t start;
    	error = cudaEventCreate(&start);

    	if (error != cudaSuccess)
    	{
        	fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	cudaEvent_t stop;
    	error = cudaEventCreate(&stop);

    	if (error != cudaSuccess)
    	{
        	fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	// Record the start event
    	error = cudaEventRecord(start, NULL);

    	if (error != cudaSuccess)
    	{
        	fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

 	vectorAdd<<<(XDIM+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( XDIM, d_v1, d_v2, d_v );
	
	// Record the stop event
    	error = cudaEventRecord(stop, NULL);

    	if (error != cudaSuccess)
    	{
        	fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	// Wait for the stop event to complete
    	error = cudaEventSynchronize(stop);

    	if (error != cudaSuccess)
    	{
        	fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	float msecTotal = 0.0f;
    	error = cudaEventElapsedTime(&msecTotal, start, stop);

    	if (error != cudaSuccess)
    	{
        	fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	// Compute and print the performance
    	float msecPerVecAdd = msecTotal / 1;

    	printf( "Performance= %.06f sec\n", msecPerVecAdd/1000.0 );
	/*******************************************************************************************
	 ****************************** for testing purposes ***************************************/
		

	//Retrieve data from GPU
	cudaMemcpy( v, d_v, size, cudaMemcpyDeviceToHost ); 
	
	//Validate for correctness
	for( i = 0; i < XDIM; i++ ){
		if( v[i] != v1[i] + v2[i] ){
			printf("WRONG!!\n");
			exit(EXIT_FAILURE);
		}
	}	
	
	return 0;
}

	.file	"tmpxft_002672ad_00000000-6_vectorAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_
	.type	_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_, @function
_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9vectorAddiPiS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_, .-_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_
	.globl	_Z9vectorAddiPiS_S_
	.type	_Z9vectorAddiPiS_S_, @function
_Z9vectorAddiPiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z9vectorAddiPiS_S_, .-_Z9vectorAddiPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to create start event (error code %s)!\n"
.LC1:
	.string	"Failed to create stop event (error code %s)!\n"
.LC2:
	.string	"Failed to record start event (error code %s)!\n"
.LC3:
	.string	"Failed to record stop event (error code %s)!\n"
.LC4:
	.string	"Failed to synchronize on the stop event (error code %s)!\n"
.LC6:
	.string	"Failed to get time elapsed between events (error code %s)!\n"
.LC8:
	.string	"Performance= %.06f sec\n"
.LC9:
	.string	"WRONG!!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	-4956160(%rsp), %r11
	.cfi_def_cfa 11, 4956192
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$1408, %rsp
	.cfi_def_cfa_offset 4957600
	xorl	%ecx, %ecx
	movl	$5, %esi
	movq	%fs:40, %rax
	movq	%rax, 4957560(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rbx
	leaq	1652568(%rsp), %rbp
.L9:
	movl	%ecx, %eax
	cltd
	idivl	%esi
	incl	%edx
	movl	%edx, (%rbx,%rcx,4)
	movl	%edx, 0(%rbp,%rcx,4)
	incq	%rcx
	cmpq	$413124, %rcx
	jne	.L9
	leaq	8(%rsp), %rdi
	movl	$1652496, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1652496, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1652496, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1652496, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1652496, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L10
	call	cudaGetErrorString@PLT
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L23
.L10:
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L11
	call	cudaGetErrorString@PLT
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rcx
.L23:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L24:
	movl	$1, %edi
	call	exit@PLT
.L11:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L12
	call	cudaGetErrorString@PLT
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L23
.L12:
	movl	$4194305, %edx
	movl	$1073741925, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$413124, %edi
	movq	8(%rsp), %rsi
	call	_Z33__device_stub__Z9vectorAddiPiS_S_iPiS_S_
.L13:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L14
	call	cudaGetErrorString@PLT
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L23
.L14:
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L15
	call	cudaGetErrorString@PLT
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L23
.L15:
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	60(%rsp), %rdi
	movl	$0x00000000, 60(%rsp)
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L16
	call	cudaGetErrorString@PLT
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L23
.L16:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	leaq	3305064(%rsp), %r12
	divsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$1652496, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
.L18:
	movl	0(%rbp,%rax), %edx
	addl	(%rbx,%rax), %edx
	cmpl	%edx, (%r12,%rax)
	je	.L17
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L24
.L17:
	addq	$4, %rax
	cmpq	$1652496, %rax
	jne	.L18
	movq	4957560(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$4957568, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z9vectorAddiPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9vectorAddiPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC7:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * Vector Addition with CUDA (Fall 2016):
 * 
 * Members:
 * Emanuelle Crespi, Tolga Keskinoglu
 *
 * This test implements a parallel vector addition: C = A + B
 * discussed in the methodology section of Optimizing CPU-GPU Interactions.
 *
 * The following code makes use of the function call vectorAdd( int n, int *A, int *B, int *C )
 * to perform a vector addition of two arrays A and B of length n 
 *
 * The output is verified before the program terminates to see that every 
 * element of index i has C[i] == A[i] + B[i]
 *
 * We can see that there is a significant speedup in comparison to the time it takes
 * to perform the vectorAdd in the serial code.
 *
 * The output of the performance is displayed in seconds. 
 * The runtime results are to be compared with the performance of vector.c
 *
 */

// System includes

#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>

// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// defines dimension of vectored data as XDIM
#define XDIM 413124 
#define THREADS_PER_BLOCK 1024

// Performs a vector addition of arrays v1 and v2
// in parallel on the GPU.  The index i is specified as 
// a particular thread within some block on the device
// This allows for parallel computation on the device
__global__ void vectorAdd( int n, int *v1, int *v2, int *v ){
	int i =  blockIdx.x*blockDim.x + threadIdx.x;
	if( i < n ){ 
		v[i] = v1[i] + v2[i];
	}	
}

int main(void){
	int i, v1[XDIM], v2[XDIM], v[XDIM];
        int *d_v1, *d_v2, *d_v, size = sizeof(int)*XDIM; 
	hipError_t error;

	//Populate data in v1 and v2
	for( i = 0; i < XDIM; i++ ){
		v1[i] = (i % 5)+1; 
		v2[i] = (i % 5)+1;
	}

	//set up space on GPU device
	hipMalloc( (void **) &d_v1, size );
	hipMalloc( (void **) &d_v2, size );
	hipMalloc( (void **) &d_v, size );

	//write data to GPU device
	hipMemcpy( d_v1, v1, size, hipMemcpyHostToDevice ); 
	hipMemcpy( d_v2, v2, size, hipMemcpyHostToDevice ); 
	/*******************************for testing purposes****************************************
	 *******************************************************************************************/
	hipDeviceSynchronize();

    	// Allocate CUDA events that we'll use for timing
    	hipEvent_t start;
    	error = hipEventCreate(&start);

    	if (error != hipSuccess)
    	{
        	fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	hipEvent_t stop;
    	error = hipEventCreate(&stop);

    	if (error != hipSuccess)
    	{
        	fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	// Record the start event
    	error = hipEventRecord(start, NULL);

    	if (error != hipSuccess)
    	{
        	fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

 	vectorAdd<<<(XDIM+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( XDIM, d_v1, d_v2, d_v );
	
	// Record the stop event
    	error = hipEventRecord(stop, NULL);

    	if (error != hipSuccess)
    	{
        	fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	// Wait for the stop event to complete
    	error = hipEventSynchronize(stop);

    	if (error != hipSuccess)
    	{
        	fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	float msecTotal = 0.0f;
    	error = hipEventElapsedTime(&msecTotal, start, stop);

    	if (error != hipSuccess)
    	{
        	fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
        	exit(EXIT_FAILURE);
    	}

    	// Compute and print the performance
    	float msecPerVecAdd = msecTotal / 1;

    	printf( "Performance= %.06f sec\n", msecPerVecAdd/1000.0 );
	/*******************************************************************************************
	 ****************************** for testing purposes ***************************************/
		

	//Retrieve data from GPU
	hipMemcpy( v, d_v, size, hipMemcpyDeviceToHost ); 
	
	//Validate for correctness
	for( i = 0; i < XDIM; i++ ){
		if( v[i] != v1[i] + v2[i] ){
			printf("WRONG!!\n");
			exit(EXIT_FAILURE);
		}
	}	
	
	return 0;
}

	.text
	.file	"vectorAdd.hip"
	.globl	_Z24__device_stub__vectorAddiPiS_S_ # -- Begin function _Z24__device_stub__vectorAddiPiS_S_
	.type	_Z24__device_stub__vectorAddiPiS_S_,@function
_Z24__device_stub__vectorAddiPiS_S_:    # @_Z24__device_stub__vectorAddiPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9vectorAddiPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__vectorAddiPiS_S_, .Lfunc_end0-_Z24__device_stub__vectorAddiPiS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$4957544, %rsp                  # imm = 0x4BA568
	.cfi_def_cfa_offset 4957568
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$1, %eax
	xorl	%ecx, %ecx
	movl	$3435973837, %edx               # imm = 0xCCCCCCCD
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ecx, %esi
	imulq	%rdx, %rsi
	shrq	$34, %rsi
	leal	(%rsi,%rsi,4), %esi
	movl	%eax, %edi
	subl	%esi, %edi
	movl	%edi, 1652544(%rsp,%rcx,4)
	movl	%edi, 48(%rsp,%rcx,4)
	incq	%rcx
	incl	%eax
	cmpq	$413124, %rcx                   # imm = 0x64DC4
	jne	.LBB1_1
# %bb.2:
	leaq	40(%rsp), %rbx
	movl	$1652496, %esi                  # imm = 0x193710
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r14
	movl	$1652496, %esi                  # imm = 0x193710
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$1652496, %esi                  # imm = 0x193710
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	1652544(%rsp), %rsi
	movl	$1652496, %edx                  # imm = 0x193710
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	leaq	48(%rsp), %rsi
	movl	$1652496, %edx                  # imm = 0x193710
	movl	$1, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.3:
	movq	%rsp, %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.4:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.5:
	movabsq	$4294967700, %rdi               # imm = 0x100000194
	leaq	620(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.6:
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	$413124, %edi                   # imm = 0x64DC4
	callq	_Z24__device_stub__vectorAddiPiS_S_
.LBB1_7:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.8:
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	testl	%eax, %eax
	jne	.LBB1_20
# %bb.9:
	leaq	12(%rsp), %rdi
	movl	$0, (%rdi)
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	hipEventElapsedTime
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.10:
	cvtss2sd	12(%rsp), %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rsi
	leaq	3305040(%rsp), %rdi
	movl	$1652496, %edx                  # imm = 0x193710
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
.LBB1_11:                               # =>This Inner Loop Header: Depth=1
	movl	48(%rsp,%rax,4), %ecx
	addl	1652544(%rsp,%rax,4), %ecx
	cmpl	%ecx, 3305040(%rsp,%rax,4)
	jne	.LBB1_14
# %bb.12:                               #   in Loop: Header=BB1_11 Depth=1
	incq	%rax
	cmpq	$413124, %rax                   # imm = 0x64DC4
	jne	.LBB1_11
# %bb.13:
	xorl	%eax, %eax
	addq	$4957544, %rsp                  # imm = 0x4BA568
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_14:
	.cfi_def_cfa_offset 4957568
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB1_15:
	movl	$1, %edi
	callq	exit
.LBB1_16:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	jmp	.LBB1_22
.LBB1_17:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	jmp	.LBB1_22
.LBB1_18:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	jmp	.LBB1_22
.LBB1_19:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.3, %esi
	jmp	.LBB1_22
.LBB1_20:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	jmp	.LBB1_22
.LBB1_21:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
.LBB1_22:
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB1_15
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9vectorAddiPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9vectorAddiPiS_S_,@object     # @_Z9vectorAddiPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z9vectorAddiPiS_S_
	.p2align	3, 0x0
_Z9vectorAddiPiS_S_:
	.quad	_Z24__device_stub__vectorAddiPiS_S_
	.size	_Z9vectorAddiPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to create start event (error code %s)!\n"
	.size	.L.str, 47

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Failed to create stop event (error code %s)!\n"
	.size	.L.str.1, 46

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to record start event (error code %s)!\n"
	.size	.L.str.2, 47

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to record stop event (error code %s)!\n"
	.size	.L.str.3, 46

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to synchronize on the stop event (error code %s)!\n"
	.size	.L.str.4, 58

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to get time elapsed between events (error code %s)!\n"
	.size	.L.str.5, 60

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Performance= %.06f sec\n"
	.size	.L.str.6, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9vectorAddiPiS_S_"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"WRONG!!"
	.size	.Lstr, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__vectorAddiPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9vectorAddiPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9vectorAddiPiS_S_     ; -- Begin function _Z9vectorAddiPiS_S_
	.globl	_Z9vectorAddiPiS_S_
	.p2align	8
	.type	_Z9vectorAddiPiS_S_,@function
_Z9vectorAddiPiS_S_:                    ; @_Z9vectorAddiPiS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9vectorAddiPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9vectorAddiPiS_S_, .Lfunc_end0-_Z9vectorAddiPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9vectorAddiPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9vectorAddiPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
