/*
 * ising_cuda_v1.cu
 *
 *  Created on: Dec 26, 2019
 *      Author: Charalampos Eleftheriadis
 */

#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define N 512
#define threadsNum 64

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

// Kernel Function.
__global__ void spin(int *G, double *w, int *newG, int n) {

    // Calculates Atomic Spin index.
    int index = blockIdx.x*blockDim.x + threadIdx.x;

    // Checks for out of bounds indexing and if so quits.
    if (index >= n*n)
        return;

    double weightSum = 0;

    // Calculates weight contribution for each neighboring Atomic Spin and sums it.
    weightSum += w[0] * G[((index/n - 2 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[1] * G[((index/n - 2 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[2] * G[((index/n - 2 + n)%n) * n + (index)%n];
    weightSum += w[3] * G[((index/n - 2 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[4] * G[((index/n - 2 + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[5] * G[((index/n - 1 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[6] * G[((index/n - 1 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[7] * G[((index/n - 1 + n)%n) * n + (index)%n];
    weightSum += w[8] * G[((index/n - 1 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[9] * G[((index/n - 1 + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[10] * G[((index/n + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[11] * G[((index/n + n)%n) * n + (index - 1 + n)%n];
    // w[12] is not contributing anything. It's the current Atomic Spin.
    weightSum += w[13] * G[((index/n + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[14] * G[((index/n + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[15] * G[((index/n + 1 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[16] * G[((index/n + 1 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[17] * G[((index/n + 1 + n)%n) * n + (index)%n];
    weightSum += w[18] * G[((index/n + 1 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[19] * G[((index/n + 1 + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[20] * G[((index/n + 2 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[21] * G[((index/n + 2 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[22] * G[((index/n + 2 + n)%n) * n + (index)%n];
    weightSum += w[23] * G[((index/n + 2 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[24] * G[((index/n + 2 + n)%n) * n + (index + 2 + n)%n];

    //! Can it be done more efficiently?
    if (weightSum > 0.0001)
        newG[index] = 1;
    else if (weightSum < -0.0001)
        newG[index] = -1;
    else
        newG[index] = G[index];

}

// Kernel Function that checks whether the new Atomic Spins Matrix is the same as the old one.
__global__ void check(int *G, int *newG, int n, int *same) {

    // Calculates Atomic Spin index.
    int index = blockIdx.x*blockDim.x + threadIdx.x;

    // Checks for out of bounds indexing and if so quits.
    if (index >= n*n)
        return;

    if (G[index] != newG[index])
	*same = 0;

}

void ising(int *G, double *w, int k, int n) {

    // Creates and transfers the Weight Matrix to GPU memory.
    double *w_d;
    int w_size = 25*sizeof(double);
    gpuErrchk( cudaMalloc((void **) &w_d, w_size) );
    gpuErrchk( cudaMemcpy(w_d, w, w_size, cudaMemcpyHostToDevice) );

    // Creates and transfers the Atomic Spins Matrix to GPU memory.
    int *G_d;
    int G_size = n*n*sizeof(int);
    gpuErrchk( cudaMalloc((void **) &G_d, G_size) );
    gpuErrchk( cudaMemcpy(G_d, G, G_size, cudaMemcpyHostToDevice) );

    // Creates the new Atomic Spins Matrix to GPU memory.
    int *newG_d;
    gpuErrchk( cudaMalloc((void **) &newG_d, G_size) );

    // Creates and transfers a flag that states whether the new Atomic Spins Matrix and the old are the same to GPU memory.
    int same = 1;
    int *same_d;
    gpuErrchk( cudaMalloc((void **) &same_d, sizeof(int)) );
    gpuErrchk( cudaMemcpy(same_d, &same, sizeof(int), cudaMemcpyHostToDevice) );

    // Creates a temporary variable for Atomic Spins Matrices' pointers swapping.
    int *temp_d;

    // Checks if function has to be iterated.
    for (int i=0; i<k; i++) {
        // Calls the kernel function balancing load to (n*n+threadsNum-1)/threadsNum blocks with threadsNum threads each.
        spin<<<(n*n+threadsNum-1)/threadsNum,threadsNum>>>(G_d, w_d, newG_d, n);
        gpuErrchk( cudaPeekAtLastError() );
        gpuErrchk( cudaDeviceSynchronize() );
        
	check<<<(n*n+threadsNum-1)/threadsNum,threadsNum>>>(G_d, newG_d, n, same_d);
        gpuErrchk( cudaPeekAtLastError() );
        gpuErrchk( cudaDeviceSynchronize() );
	gpuErrchk( cudaMemcpy(&same, same_d, sizeof(int), cudaMemcpyDeviceToHost) );
	if (same)
	    break;

        // Atomix Spin Matrices' pointers swapping.
        temp_d = G_d;
        G_d = newG_d;
        newG_d = temp_d;
    }

    // Copies data from GPU to CPU memory.
    gpuErrchk( cudaMemcpy(G, G_d, G_size, cudaMemcpyDeviceToHost) );

    // Cleanup.
    gpuErrchk( cudaFree(w_d) );
    gpuErrchk( cudaFree(G_d) );
    gpuErrchk( cudaFree(newG_d) );

}

int main() {

    // Weight Matrix.
    double w[] = { 0.004, 0.016, 0.026, 0.016, 0.004,
                   0.016, 0.071, 0.117, 0.071, 0.016,
                   0.026, 0.117, 0.000, 0.117, 0.026,
                   0.016, 0.071, 0.117, 0.071, 0.016,
                   0.004, 0.016, 0.026, 0.016, 0.004 };

    // Number of dimensions for the square Atomic Spins Matrix.
    int n = N;

    // Allocates memory for the Atomic Spins Matrix.
    int *G = (int *)malloc(n*n * sizeof(int));


    // Randomizes seed.
    srand(time(NULL));

    // Fills the Atomic Spins Matrix with "-1" and "1" values from a uniform distribution.
    for (int i=0; i<n*n; i++)
        G[i] = ((rand() % 2) * 2) - 1;

    /*
    // Reads configuration file.
    size_t readStatus;
    FILE *conf_init = fopen("conf-init.bin","rb");
    int initG[n*n];
    readStatus = fread(&initG, sizeof(int), n*n, conf_init);
    if (readStatus != n*n)
        printf("Could not read conf-init.bin file.\n");
    fclose(conf_init);

    // Fills the Atomic Spins Matrix with "-1" and "1" values from configuration file.
    for (int i=0; i<n*n; i++)
        G[i] = initG[i];
    */

    ising(G, w, 10, n);

    /*
    // Reads configuration file for state after one iteration.
    size_t readStatus1;
    FILE *conf_1 = fopen("conf-1.bin","rb");
    int G1[n*n];
    readStatus1 = fread(&G1, sizeof(int), n*n, conf_1);
    if (readStatus1 != n*n)
        printf("Could not read conf-1.bin file.\n");
    fclose(conf_1);

    // Checks for errors.
    int errorsNum = 0;
    for (int i=0; i<n; i++)
        for (int j=0; j<n; j++)
            if (G[i*n+j] != G1[i*n+j])
                errorsNum++;
    if (errorsNum == 0)
        printf("Correct Results!\n");
    else
        printf("Wrong Results. Number of errors: %d\n", errorsNum);


    // Checks the results.
    for (int i=0; i<n; i++) {
        for (int j=0; j<n; j++) {
            if (G[i*n+j] == G1[i*n+j])
                printf("=");
            else
                printf("!");
        }
        printf("\n");
    }
    printf("\n\n");
    */

    return 0;

}

	.file	"tmpxft_002f7d5c_00000000-6_ising_cuda_v1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC1:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC1(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z28__device_stub__Z4spinPiPdS_iPiPdS_i
	.type	_Z28__device_stub__Z4spinPiPdS_iPiPdS_i, @function
_Z28__device_stub__Z4spinPiPdS_iPiPdS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4spinPiPdS_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z28__device_stub__Z4spinPiPdS_iPiPdS_i, .-_Z28__device_stub__Z4spinPiPdS_iPiPdS_i
	.globl	_Z4spinPiPdS_i
	.type	_Z4spinPiPdS_i, @function
_Z4spinPiPdS_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z4spinPiPdS_iPiPdS_i
	.cfi_endproc
.LFE2055:
	.size	_Z4spinPiPdS_i, .-_Z4spinPiPdS_i
	.globl	_Z29__device_stub__Z5checkPiS_iS_PiS_iS_
	.type	_Z29__device_stub__Z5checkPiS_iS_PiS_iS_, @function
_Z29__device_stub__Z5checkPiS_iS_PiS_iS_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5checkPiS_iS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L17:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z29__device_stub__Z5checkPiS_iS_PiS_iS_, .-_Z29__device_stub__Z5checkPiS_iS_PiS_iS_
	.globl	_Z5checkPiS_iS_
	.type	_Z5checkPiS_iS_, @function
_Z5checkPiS_iS_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z5checkPiS_iS_PiS_iS_
	.cfi_endproc
.LFE2057:
	.size	_Z5checkPiS_iS_, .-_Z5checkPiS_iS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/LambisElef/ece-auth-ising-cuda/master/ising_cuda_v1.cu"
	.text
	.globl	_Z5isingPiPdii
	.type	_Z5isingPiPdii, @function
_Z5isingPiPdii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movabsq	$4294967360, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	movl	$200, %esi
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	28(%rsp), %r15
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$98, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	%rbx, %rsi
	movq	32(%rsp), %rdi
	movl	%ebp, %ebx
	imull	%ebp, %ebx
	movl	$1, %ecx
	movl	$200, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$99, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leal	0(,%rbx,4), %eax
	leaq	40(%rsp), %rdi
	addl	$63, %ebx
	cltq
	sarl	$6, %ebx
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$104, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$105, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$109, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	movl	$1, 28(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$114, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$115, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
.L23:
	cmpl	%r13d, %r14d
	jge	.L28
	movl	%ebx, 64(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%r12, 76(%rsp)
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	movl	$1, 84(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%ebp, %ecx
	movq	40(%rsp), %rdi
	call	_Z28__device_stub__Z4spinPiPdS_iPiPdS_i
.L24:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$124, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$125, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	%ebx, 64(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	movq	%r12, 76(%rsp)
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	movl	$1, 84(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rsi
	movl	%ebp, %edx
	movq	40(%rsp), %rdi
	call	_Z29__device_stub__Z5checkPiS_iS_PiS_iS_
.L25:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$128, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$129, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r15, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$130, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	cmpl	$0, 28(%rsp)
	je	.L26
.L28:
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$141, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$144, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$145, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$146, %edx
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L26:
	movq	40(%rsp), %rax
	movq	48(%rsp), %rdx
	incl	%r14d
	movq	%rdx, 40(%rsp)
	movq	%rax, 48(%rsp)
	jmp	.L23
.L29:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z5isingPiPdii, .-_Z5isingPiPdii
	.section	.rodata
	.align 32
.LC0:
	.long	-755914244
	.long	1064329805
	.long	-755914244
	.long	1066426957
	.long	1992864825
	.long	1067098046
	.long	-755914244
	.long	1066426957
	.long	-755914244
	.long	1064329805
	.long	-755914244
	.long	1066426957
	.long	1443109011
	.long	1068641550
	.long	1168231105
	.long	1069413302
	.long	1443109011
	.long	1068641550
	.long	-755914244
	.long	1066426957
	.long	1992864825
	.long	1067098046
	.long	1168231105
	.long	1069413302
	.long	0
	.long	0
	.long	1168231105
	.long	1069413302
	.long	1992864825
	.long	1067098046
	.long	-755914244
	.long	1066426957
	.long	1443109011
	.long	1068641550
	.long	1168231105
	.long	1069413302
	.long	1443109011
	.long	1068641550
	.long	-755914244
	.long	1066426957
	.long	-755914244
	.long	1064329805
	.long	-755914244
	.long	1066426957
	.long	1992864825
	.long	1067098046
	.long	-755914244
	.long	1066426957
	.long	-755914244
	.long	1064329805
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	movl	$50, %ecx
	movl	$2, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$208, %rsp
	.cfi_def_cfa_offset 240
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	rep movsl
	movl	$1048576, %edi
	call	malloc@PLT
	xorl	%edi, %edi
	movq	%rax, %rbx
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L33:
	call	rand@PLT
	cltd
	idivl	%r12d
	leal	-1(%rdx,%rdx), %eax
	movl	%eax, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	$262144, %rbp
	jne	.L33
	movl	$512, %ecx
	movl	$10, %edx
	movq	%rsp, %rsi
	movq	%rbx, %rdi
	call	_Z5isingPiPdii
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$208, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z5checkPiS_iS_"
.LC4:
	.string	"_Z4spinPiPdS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5checkPiS_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4spinPiPdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * ising_cuda_v1.cu
 *
 *  Created on: Dec 26, 2019
 *      Author: Charalampos Eleftheriadis
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define N 512
#define threadsNum 64

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

// Kernel Function.
__global__ void spin(int *G, double *w, int *newG, int n) {

    // Calculates Atomic Spin index.
    int index = blockIdx.x*blockDim.x + threadIdx.x;

    // Checks for out of bounds indexing and if so quits.
    if (index >= n*n)
        return;

    double weightSum = 0;

    // Calculates weight contribution for each neighboring Atomic Spin and sums it.
    weightSum += w[0] * G[((index/n - 2 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[1] * G[((index/n - 2 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[2] * G[((index/n - 2 + n)%n) * n + (index)%n];
    weightSum += w[3] * G[((index/n - 2 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[4] * G[((index/n - 2 + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[5] * G[((index/n - 1 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[6] * G[((index/n - 1 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[7] * G[((index/n - 1 + n)%n) * n + (index)%n];
    weightSum += w[8] * G[((index/n - 1 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[9] * G[((index/n - 1 + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[10] * G[((index/n + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[11] * G[((index/n + n)%n) * n + (index - 1 + n)%n];
    // w[12] is not contributing anything. It's the current Atomic Spin.
    weightSum += w[13] * G[((index/n + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[14] * G[((index/n + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[15] * G[((index/n + 1 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[16] * G[((index/n + 1 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[17] * G[((index/n + 1 + n)%n) * n + (index)%n];
    weightSum += w[18] * G[((index/n + 1 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[19] * G[((index/n + 1 + n)%n) * n + (index + 2 + n)%n];

    weightSum += w[20] * G[((index/n + 2 + n)%n) * n + (index - 2 + n)%n];
    weightSum += w[21] * G[((index/n + 2 + n)%n) * n + (index - 1 + n)%n];
    weightSum += w[22] * G[((index/n + 2 + n)%n) * n + (index)%n];
    weightSum += w[23] * G[((index/n + 2 + n)%n) * n + (index + 1 + n)%n];
    weightSum += w[24] * G[((index/n + 2 + n)%n) * n + (index + 2 + n)%n];

    //! Can it be done more efficiently?
    if (weightSum > 0.0001)
        newG[index] = 1;
    else if (weightSum < -0.0001)
        newG[index] = -1;
    else
        newG[index] = G[index];

}

// Kernel Function that checks whether the new Atomic Spins Matrix is the same as the old one.
__global__ void check(int *G, int *newG, int n, int *same) {

    // Calculates Atomic Spin index.
    int index = blockIdx.x*blockDim.x + threadIdx.x;

    // Checks for out of bounds indexing and if so quits.
    if (index >= n*n)
        return;

    if (G[index] != newG[index])
	*same = 0;

}

void ising(int *G, double *w, int k, int n) {

    // Creates and transfers the Weight Matrix to GPU memory.
    double *w_d;
    int w_size = 25*sizeof(double);
    gpuErrchk( hipMalloc((void **) &w_d, w_size) );
    gpuErrchk( hipMemcpy(w_d, w, w_size, hipMemcpyHostToDevice) );

    // Creates and transfers the Atomic Spins Matrix to GPU memory.
    int *G_d;
    int G_size = n*n*sizeof(int);
    gpuErrchk( hipMalloc((void **) &G_d, G_size) );
    gpuErrchk( hipMemcpy(G_d, G, G_size, hipMemcpyHostToDevice) );

    // Creates the new Atomic Spins Matrix to GPU memory.
    int *newG_d;
    gpuErrchk( hipMalloc((void **) &newG_d, G_size) );

    // Creates and transfers a flag that states whether the new Atomic Spins Matrix and the old are the same to GPU memory.
    int same = 1;
    int *same_d;
    gpuErrchk( hipMalloc((void **) &same_d, sizeof(int)) );
    gpuErrchk( hipMemcpy(same_d, &same, sizeof(int), hipMemcpyHostToDevice) );

    // Creates a temporary variable for Atomic Spins Matrices' pointers swapping.
    int *temp_d;

    // Checks if function has to be iterated.
    for (int i=0; i<k; i++) {
        // Calls the kernel function balancing load to (n*n+threadsNum-1)/threadsNum blocks with threadsNum threads each.
        spin<<<(n*n+threadsNum-1)/threadsNum,threadsNum>>>(G_d, w_d, newG_d, n);
        gpuErrchk( hipPeekAtLastError() );
        gpuErrchk( hipDeviceSynchronize() );
        
	check<<<(n*n+threadsNum-1)/threadsNum,threadsNum>>>(G_d, newG_d, n, same_d);
        gpuErrchk( hipPeekAtLastError() );
        gpuErrchk( hipDeviceSynchronize() );
	gpuErrchk( hipMemcpy(&same, same_d, sizeof(int), hipMemcpyDeviceToHost) );
	if (same)
	    break;

        // Atomix Spin Matrices' pointers swapping.
        temp_d = G_d;
        G_d = newG_d;
        newG_d = temp_d;
    }

    // Copies data from GPU to CPU memory.
    gpuErrchk( hipMemcpy(G, G_d, G_size, hipMemcpyDeviceToHost) );

    // Cleanup.
    gpuErrchk( hipFree(w_d) );
    gpuErrchk( hipFree(G_d) );
    gpuErrchk( hipFree(newG_d) );

}

int main() {

    // Weight Matrix.
    double w[] = { 0.004, 0.016, 0.026, 0.016, 0.004,
                   0.016, 0.071, 0.117, 0.071, 0.016,
                   0.026, 0.117, 0.000, 0.117, 0.026,
                   0.016, 0.071, 0.117, 0.071, 0.016,
                   0.004, 0.016, 0.026, 0.016, 0.004 };

    // Number of dimensions for the square Atomic Spins Matrix.
    int n = N;

    // Allocates memory for the Atomic Spins Matrix.
    int *G = (int *)malloc(n*n * sizeof(int));


    // Randomizes seed.
    srand(time(NULL));

    // Fills the Atomic Spins Matrix with "-1" and "1" values from a uniform distribution.
    for (int i=0; i<n*n; i++)
        G[i] = ((rand() % 2) * 2) - 1;

    /*
    // Reads configuration file.
    size_t readStatus;
    FILE *conf_init = fopen("conf-init.bin","rb");
    int initG[n*n];
    readStatus = fread(&initG, sizeof(int), n*n, conf_init);
    if (readStatus != n*n)
        printf("Could not read conf-init.bin file.\n");
    fclose(conf_init);

    // Fills the Atomic Spins Matrix with "-1" and "1" values from configuration file.
    for (int i=0; i<n*n; i++)
        G[i] = initG[i];
    */

    ising(G, w, 10, n);

    /*
    // Reads configuration file for state after one iteration.
    size_t readStatus1;
    FILE *conf_1 = fopen("conf-1.bin","rb");
    int G1[n*n];
    readStatus1 = fread(&G1, sizeof(int), n*n, conf_1);
    if (readStatus1 != n*n)
        printf("Could not read conf-1.bin file.\n");
    fclose(conf_1);

    // Checks for errors.
    int errorsNum = 0;
    for (int i=0; i<n; i++)
        for (int j=0; j<n; j++)
            if (G[i*n+j] != G1[i*n+j])
                errorsNum++;
    if (errorsNum == 0)
        printf("Correct Results!\n");
    else
        printf("Wrong Results. Number of errors: %d\n", errorsNum);


    // Checks the results.
    for (int i=0; i<n; i++) {
        for (int j=0; j<n; j++) {
            if (G[i*n+j] == G1[i*n+j])
                printf("=");
            else
                printf("!");
        }
        printf("\n");
    }
    printf("\n\n");
    */

    return 0;

}

	.text
	.file	"ising_cuda_v1.hip"
	.globl	_Z19__device_stub__spinPiPdS_i  # -- Begin function _Z19__device_stub__spinPiPdS_i
	.type	_Z19__device_stub__spinPiPdS_i,@function
_Z19__device_stub__spinPiPdS_i:         # @_Z19__device_stub__spinPiPdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4spinPiPdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__spinPiPdS_i, .Lfunc_end0-_Z19__device_stub__spinPiPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__checkPiS_iS_ # -- Begin function _Z20__device_stub__checkPiS_iS_
	.type	_Z20__device_stub__checkPiS_iS_,@function
_Z20__device_stub__checkPiS_iS_:        # @_Z20__device_stub__checkPiS_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5checkPiS_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__checkPiS_iS_, .Lfunc_end1-_Z20__device_stub__checkPiS_iS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z5isingPiPdii                  # -- Begin function _Z5isingPiPdii
	.type	_Z5isingPiPdii,@function
_Z5isingPiPdii:                         # @_Z5isingPiPdii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, %r15
	movq	%rdi, %r12
	leaq	32(%rsp), %rdi
	movl	$200, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_1
# %bb.3:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movq	32(%rsp), %rdi
	movl	$200, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.5:                                # %_Z9gpuAssert10hipError_tPKcib.exit29
	movl	%ebp, %r15d
	imull	%r15d, %r15d
	leal	(,%r15,4), %eax
	movslq	%eax, %r13
	movq	%rsp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKcib.exit31
	movq	(%rsp), %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit33
	leaq	16(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcib.exit35
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	movl	$1, 12(%rsp)
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit37
	movq	%r13, 40(%rsp)                  # 8-byte Spill
	movq	24(%rsp), %rdi
	leaq	12(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_42
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKcib.exit39.preheader
	testl	%r14d, %r14d
	jle	.LBB2_33
# %bb.15:                               # %.lr.ph
	movabsq	$4294967360, %r12               # imm = 0x100000040
	addl	$63, %r15d
	shrl	$6, %r15d
	leaq	(%r15,%r12), %r13
	addq	$-64, %r13
	leaq	12(%rsp), %rbx
.LBB2_16:                               # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_18
# %bb.17:                               #   in Loop: Header=BB2_16 Depth=1
	movq	(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z19__device_stub__spinPiPdS_i
.LBB2_18:                               #   in Loop: Header=BB2_16 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB2_19
# %bb.21:                               # %_Z9gpuAssert10hipError_tPKcib.exit41
                                        #   in Loop: Header=BB2_16 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB2_22
# %bb.23:                               # %_Z9gpuAssert10hipError_tPKcib.exit43
                                        #   in Loop: Header=BB2_16 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_25
# %bb.24:                               #   in Loop: Header=BB2_16 Depth=1
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	callq	_Z20__device_stub__checkPiS_iS_
.LBB2_25:                               #   in Loop: Header=BB2_16 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB2_26
# %bb.27:                               # %_Z9gpuAssert10hipError_tPKcib.exit45
                                        #   in Loop: Header=BB2_16 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB2_28
# %bb.29:                               # %_Z9gpuAssert10hipError_tPKcib.exit47
                                        #   in Loop: Header=BB2_16 Depth=1
	movq	24(%rsp), %rsi
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_30
# %bb.31:                               # %_Z9gpuAssert10hipError_tPKcib.exit49
                                        #   in Loop: Header=BB2_16 Depth=1
	cmpl	$0, 12(%rsp)
	jne	.LBB2_33
# %bb.32:                               # %_Z9gpuAssert10hipError_tPKcib.exit39
                                        #   in Loop: Header=BB2_16 Depth=1
	movq	(%rsp), %rax
	movq	16(%rsp), %rcx
	movq	%rcx, (%rsp)
	movq	%rax, 16(%rsp)
	decl	%r14d
	jne	.LBB2_16
.LBB2_33:                               # %_Z9gpuAssert10hipError_tPKcib.exit49._crit_edge
	movq	(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_34
# %bb.35:                               # %_Z9gpuAssert10hipError_tPKcib.exit51
	movq	32(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB2_36
# %bb.37:                               # %_Z9gpuAssert10hipError_tPKcib.exit53
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB2_38
# %bb.39:                               # %_Z9gpuAssert10hipError_tPKcib.exit55
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB2_40
# %bb.41:                               # %_Z9gpuAssert10hipError_tPKcib.exit57
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_19:
	.cfi_def_cfa_offset 112
	movl	%eax, %r15d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$126, %r8d
	jmp	.LBB2_20
.LBB2_26:
	movl	%eax, %r15d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$130, %r8d
	jmp	.LBB2_20
.LBB2_30:
	movl	%eax, %r15d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$132, %r8d
	jmp	.LBB2_20
.LBB2_22:
	movl	%eax, %r15d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$127, %r8d
	jmp	.LBB2_20
.LBB2_28:
	movl	%eax, %r15d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$131, %r8d
.LBB2_20:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r15d, %edi
	callq	exit
.LBB2_1:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$100, %r8d
	jmp	.LBB2_2
.LBB2_4:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$101, %r8d
	jmp	.LBB2_2
.LBB2_6:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$106, %r8d
	jmp	.LBB2_2
.LBB2_8:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$107, %r8d
	jmp	.LBB2_2
.LBB2_10:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$111, %r8d
	jmp	.LBB2_2
.LBB2_12:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$116, %r8d
	jmp	.LBB2_2
.LBB2_42:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$117, %r8d
	jmp	.LBB2_2
.LBB2_34:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$143, %r8d
	jmp	.LBB2_2
.LBB2_36:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$146, %r8d
	jmp	.LBB2_2
.LBB2_38:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$147, %r8d
	jmp	.LBB2_2
.LBB2_40:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$148, %r8d
.LBB2_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z5isingPiPdii, .Lfunc_end2-_Z5isingPiPdii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$200, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsp, %rdi
	movl	$.L__const.main.w, %esi
	movl	$200, %edx
	callq	memcpy@PLT
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, %rbx
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	andl	$2147483646, %ecx               # imm = 0x7FFFFFFE
	subl	%ecx, %eax
	leal	-1(,%rax,2), %eax
	movl	%eax, (%rbx,%r14,4)
	incq	%r14
	cmpq	$262144, %r14                   # imm = 0x40000
	jne	.LBB3_1
# %bb.2:
	movq	%rsp, %rsi
	movq	%rbx, %rdi
	movl	$10, %edx
	movl	$512, %ecx                      # imm = 0x200
	callq	_Z5isingPiPdii
	xorl	%eax, %eax
	addq	$200, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4spinPiPdS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5checkPiS_iS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4spinPiPdS_i,@object          # @_Z4spinPiPdS_i
	.section	.rodata,"a",@progbits
	.globl	_Z4spinPiPdS_i
	.p2align	3, 0x0
_Z4spinPiPdS_i:
	.quad	_Z19__device_stub__spinPiPdS_i
	.size	_Z4spinPiPdS_i, 8

	.type	_Z5checkPiS_iS_,@object         # @_Z5checkPiS_iS_
	.globl	_Z5checkPiS_iS_
	.p2align	3, 0x0
_Z5checkPiS_iS_:
	.quad	_Z20__device_stub__checkPiS_iS_
	.size	_Z5checkPiS_iS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/LambisElef/ece-auth-ising-cuda/master/ising_cuda_v1.hip"
	.size	.L.str, 118

	.type	.L__const.main.w,@object        # @__const.main.w
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
.L__const.main.w:
	.quad	0x3f70624dd2f1a9fc              # double 0.0040000000000000001
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3f9a9fbe76c8b439              # double 0.025999999999999999
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3f70624dd2f1a9fc              # double 0.0040000000000000001
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3fb22d0e56041893              # double 0.070999999999999994
	.quad	0x3fbdf3b645a1cac1              # double 0.11700000000000001
	.quad	0x3fb22d0e56041893              # double 0.070999999999999994
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3f9a9fbe76c8b439              # double 0.025999999999999999
	.quad	0x3fbdf3b645a1cac1              # double 0.11700000000000001
	.quad	0x0000000000000000              # double 0
	.quad	0x3fbdf3b645a1cac1              # double 0.11700000000000001
	.quad	0x3f9a9fbe76c8b439              # double 0.025999999999999999
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3fb22d0e56041893              # double 0.070999999999999994
	.quad	0x3fbdf3b645a1cac1              # double 0.11700000000000001
	.quad	0x3fb22d0e56041893              # double 0.070999999999999994
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3f70624dd2f1a9fc              # double 0.0040000000000000001
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3f9a9fbe76c8b439              # double 0.025999999999999999
	.quad	0x3f90624dd2f1a9fc              # double 0.016
	.quad	0x3f70624dd2f1a9fc              # double 0.0040000000000000001
	.size	.L__const.main.w, 200

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.1, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4spinPiPdS_i"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z5checkPiS_iS_"
	.size	.L__unnamed_2, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__spinPiPdS_i
	.addrsig_sym _Z20__device_stub__checkPiS_iS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4spinPiPdS_i
	.addrsig_sym _Z5checkPiS_iS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4spinPiPdS_i          ; -- Begin function _Z4spinPiPdS_i
	.globl	_Z4spinPiPdS_i
	.p2align	8
	.type	_Z4spinPiPdS_i,@function
_Z4spinPiPdS_i:                         ; @_Z4spinPiPdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s22, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s22, s22
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_ashr_i32 s2, s22, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s3, s22, s2
	v_add_nc_u32_e32 v7, s22, v1
	s_xor_b32 s23, s3, s2
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[20:21], s[0:1], 0x10
	v_cvt_f32_u32_e32 v0, s23
	s_sub_i32 s3, 0, s23
	v_add_nc_u32_e32 v4, v1, v2
	v_add_nc_u32_e32 v11, -1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v4, v4, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v4, v0
	v_mul_lo_u32 v5, v3, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v5
	v_add_nc_u32_e32 v5, 1, v3
	v_subrev_nc_u32_e32 v6, s23, v4
	v_cmp_le_u32_e32 vcc_lo, s23, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v4, v4, v6
	v_xor_b32_e32 v6, s2, v2
	s_waitcnt lgkmcnt(0)
	s_load_b512 s[0:15], s[18:19], 0x0
	v_add_nc_u32_e32 v5, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s23, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_add_nc_u32_e32 v5, -2, v7
	v_xor_b32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v3, v6
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v3, s22, -2, v10
	v_add_nc_u32_e32 v5, v5, v6
	v_add_nc_u32_e32 v22, s22, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_xor_b32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v9, v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v4
	v_mul_lo_u32 v9, v9, s23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v3, v0
	v_sub_nc_u32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, s23
	v_subrev_nc_u32_e32 v9, s23, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v8
	v_subrev_nc_u32_e32 v8, s23, v3
	v_cmp_le_u32_e32 vcc_lo, s23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v5
	v_ashrrev_i32_e32 v8, 31, v11
	v_subrev_nc_u32_e32 v12, s23, v3
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v11, v11, v8
	v_cndmask_b32_e32 v3, v3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v11, v8
	v_subrev_nc_u32_e32 v11, s23, v5
	v_cmp_le_u32_e32 vcc_lo, s23, v5
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v12, v9, v0
	v_cndmask_b32_e32 v5, v5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v4
	v_xor_b32_e32 v4, v5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v5, v12, s23
	v_mul_lo_u32 v11, v3, s22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v3, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v11, v4
	v_subrev_nc_u32_e32 v9, s23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_cmp_le_u32_e32 vcc_lo, s23, v3
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	v_add_co_u32 v5, vcc_lo, s16, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	v_subrev_nc_u32_e32 v9, s23, v3
	v_cmp_le_u32_e32 vcc_lo, s23, v3
	global_load_b32 v12, v[5:6], off
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v8
	v_sub_nc_u32_e32 v3, v3, v8
	v_add_nc_u32_e32 v8, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v3, v11
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_nc_u32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_xor_b32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v13, v8, v0
	v_add_co_u32 v5, vcc_lo, s16, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	global_load_b32 v14, v[5:6], off
	v_mul_lo_u32 v6, v13, s23
	v_mul_lo_u32 v5, v10, s22
	v_sub_nc_u32_e32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v1, v5
	v_subrev_nc_u32_e32 v16, s23, v8
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v5, v11
	v_dual_cndmask_b32 v8, v8, v16 :: v_dual_add_nc_u32 v13, 2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_subrev_nc_u32_e32 v16, s23, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v15, 31, v13
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, v13, v15
	v_add_co_u32 v6, vcc_lo, s16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v7, vcc_lo
	v_xor_b32_e32 v13, v13, v15
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_hi_u32 v17, v13, v0
	v_cndmask_b32_e32 v8, v8, v16, vcc_lo
	global_load_b32 v16, v[6:7], off
	v_xor_b32_e32 v6, v8, v9
	v_add3_u32 v8, s22, -1, v10
	v_mul_lo_u32 v7, v17, s23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v9
	v_sub_nc_u32_e32 v9, v13, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v8
	v_add_nc_u32_e32 v7, v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v17, s23, v9
	v_add_nc_u32_e32 v18, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_cndmask_b32_e32 v9, v9, v17, vcc_lo
	v_xor_b32_e32 v17, v18, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s16, v7
	v_mul_hi_u32 v19, v17, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	v_subrev_nc_u32_e32 v18, s23, v9
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v9, v18, vcc_lo
	global_load_b32 v18, v[7:8], off
	v_mul_lo_u32 v7, v19, s23
	v_xor_b32_e32 v8, v9, v15
	v_sub_nc_u32_e32 v9, v17, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v8, v15
	v_subrev_nc_u32_e32 v15, s23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v7, v11
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	v_cndmask_b32_e32 v11, v9, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_subrev_nc_u32_e32 v15, s23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_cmp_le_u32_e32 vcc_lo, s23, v11
	v_cndmask_b32_e32 v11, v11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v11, v13
	global_load_b32 v17, v[8:9], off
	v_sub_nc_u32_e32 v8, v11, v13
	v_ashrrev_i32_e32 v13, 31, v22
	v_mul_lo_u32 v11, v8, s22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v22, v13
	v_xor_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v11, v4
	v_mul_hi_u32 v15, v10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v19, v[8:9], off
	v_add_nc_u32_e32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v20, v[8:9], off
	v_add_nc_u32_e32 v8, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v21, v[8:9], off
	v_add_nc_u32_e32 v8, v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v23, v[8:9], off
	v_mul_lo_u32 v8, v15, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v10, v8
	v_add_nc_u32_e32 v8, v11, v7
	v_subrev_nc_u32_e32 v15, s23, v9
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[10:11], v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v9, v15, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	v_subrev_nc_u32_e32 v15, s23, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_cmp_le_u32_e32 vcc_lo, s23, v12
	v_cndmask_b32_e32 v12, v12, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v12, v12, v13
	global_load_b32 v24, v[8:9], off
	v_sub_nc_u32_e32 v8, v12, v13
	v_mul_lo_u32 v25, v8, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v25, v4
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[10:11], s[0:1], v[10:11], 0
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[12:13], v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v26, v[8:9], off
	v_add_nc_u32_e32 v8, v25, v3
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s16, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	v_fma_f64 v[10:11], s[2:3], v[12:13], v[10:11]
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[14:15], v16
	global_load_b32 v16, v[8:9], off
	v_add_nc_u32_e32 v9, 1, v22
	v_add_nc_u32_e32 v8, v25, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v27, 31, v9
	v_fma_f64 v[10:11], s[4:5], v[14:15], v[10:11]
	v_add_nc_u32_e32 v14, v9, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[12:13], v18
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_xor_b32_e32 v14, v14, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_mul_hi_u32 v15, v14, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v18, v[8:9], off
	v_mul_lo_u32 v8, v15, s23
	v_sub_nc_u32_e32 v9, v14, v8
	v_add_nc_u32_e32 v8, v25, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v28, s23, v9
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	v_fma_f64 v[10:11], s[6:7], v[12:13], v[10:11]
	v_cndmask_b32_e32 v12, v9, v28, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[14:15], v17
	s_load_b256 s[0:7], s[18:19], 0x40
	v_subrev_nc_u32_e32 v13, s23, v12
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_cmp_le_u32_e32 vcc_lo, s23, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	v_add_co_u32 v8, vcc_lo, s16, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	v_xor_b32_e32 v12, v12, v27
	global_load_b32 v17, v[8:9], off
	v_sub_nc_u32_e32 v8, v12, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v25, v8, s22
	v_add_nc_u32_e32 v8, v25, v4
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[12:13], v19
	v_fma_f64 v[10:11], s[8:9], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v19, v[8:9], off
	v_add_nc_u32_e32 v8, v25, v3
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[14:15], v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_fma_f64 v[10:11], s[10:11], v[12:13], v[10:11]
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v20, v[8:9], off
	v_add_nc_u32_e32 v8, v25, v5
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[12:13], v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v21, v[8:9], off
	v_add_nc_u32_e32 v9, 2, v22
	v_add_nc_u32_e32 v8, v25, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v22, 31, v9
	v_fma_f64 v[10:11], s[12:13], v[14:15], v[10:11]
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[14:15], v23
	v_fma_f64 v[10:11], s[14:15], v[12:13], v[10:11]
	v_add_nc_u32_e32 v12, v9, v22
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v12, v12, v22
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v12, v0
	v_add_co_u32 v8, vcc_lo, s16, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	v_mul_lo_u32 v0, v0, s23
	global_load_b32 v23, v[8:9], off
	v_add_nc_u32_e32 v8, v25, v7
	v_sub_nc_u32_e32 v0, v12, v0
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[12:13], v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v9, s23, v0
	v_cmp_le_u32_e32 vcc_lo, s23, v0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[10:11], s[0:1], v[14:15], v[10:11]
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v14, s23, v0
	v_cmp_le_u32_e32 vcc_lo, s23, v0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v14, vcc_lo
	v_add_co_u32 v8, vcc_lo, s16, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	v_xor_b32_e32 v0, v0, v22
	s_waitcnt vmcnt(7)
	v_cvt_f64_i32_e32 v[14:15], v26
	global_load_b32 v24, v[8:9], off
	v_sub_nc_u32_e32 v0, v0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s22
	v_add_nc_u32_e32 v8, v0, v4
	v_add_nc_u32_e32 v3, v0, v3
	v_fma_f64 v[10:11], s[2:3], v[12:13], v[10:11]
	v_add_nc_u32_e32 v7, v0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
	global_load_b32 v22, v[8:9], off
	v_fma_f64 v[10:11], s[4:5], v[14:15], v[10:11]
	global_load_b32 v14, v[3:4], off
	s_waitcnt vmcnt(9)
	v_cvt_f64_i32_e32 v[8:9], v16
	v_add_nc_u32_e32 v3, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[12:13], v18
	v_fma_f64 v[8:9], s[6:7], v[8:9], v[10:11]
	s_load_b512 s[0:15], s[18:19], 0x68
	global_load_b32 v10, v[3:4], off
	v_add_nc_u32_e32 v3, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
	global_load_b32 v11, v[3:4], off
	s_waitcnt vmcnt(9)
	v_cvt_f64_i32_e32 v[5:6], v17
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[8:9], s[0:1], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], s[2:3], v[5:6], v[8:9]
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	global_load_b32 v0, v[7:8], off
	s_waitcnt vmcnt(9)
	v_cvt_f64_i32_e32 v[3:4], v19
	s_waitcnt vmcnt(8)
	v_cvt_f64_i32_e32 v[7:8], v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], s[4:5], v[3:4], v[5:6]
	s_waitcnt vmcnt(7)
	v_cvt_f64_i32_e32 v[5:6], v21
	v_fma_f64 v[3:4], s[6:7], v[7:8], v[3:4]
	s_load_b256 s[0:7], s[18:19], 0xa8
	s_waitcnt vmcnt(6)
	v_cvt_f64_i32_e32 v[7:8], v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], s[8:9], v[5:6], v[3:4]
	s_waitcnt vmcnt(5)
	v_cvt_f64_i32_e32 v[5:6], v24
	v_fma_f64 v[3:4], s[10:11], v[7:8], v[3:4]
	s_waitcnt vmcnt(4)
	v_cvt_f64_i32_e32 v[7:8], v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], s[12:13], v[5:6], v[3:4]
	s_waitcnt vmcnt(3)
	v_cvt_f64_i32_e32 v[5:6], v14
	v_fma_f64 v[3:4], s[14:15], v[7:8], v[3:4]
	s_waitcnt vmcnt(2)
	v_cvt_f64_i32_e32 v[7:8], v10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], s[0:1], v[5:6], v[3:4]
	s_waitcnt vmcnt(1)
	v_cvt_f64_i32_e32 v[5:6], v11
	s_mov_b32 s1, 0x3f1a36e2
	s_mov_b32 s0, 0xeb1c432d
	v_fma_f64 v[3:4], s[2:3], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], s[4:5], v[5:6], v[3:4]
	s_waitcnt vmcnt(0)
	v_cvt_f64_i32_e32 v[5:6], v0
                                        ; implicit-def: $vgpr0
	v_fma_f64 v[3:4], s[6:7], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[0:1], v[3:4]
	s_and_saveexec_b32 s1, vcc_lo
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB0_5
; %bb.2:
	s_mov_b32 s1, 0xbf1a36e2
	v_mov_b32_e32 v0, -1
	v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[3:4]
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
.LBB0_4:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_5:                                ; %Flow288
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, 1
.LBB0_7:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s20, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s21, v2, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v0, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4spinPiPdS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4spinPiPdS_i, .Lfunc_end0-_Z4spinPiPdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2796
; NumSgprs: 26
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5checkPiS_iS_         ; -- Begin function _Z5checkPiS_iS_
	.globl	_Z5checkPiS_iS_
	.p2align	8
	.type	_Z5checkPiS_iS_,@function
_Z5checkPiS_iS_:                        ; @_Z5checkPiS_iS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s3, s3, s3
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_3
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_load_b64 s[0:1], s[0:1], 0x18
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v0, s[0:1]
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5checkPiS_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5checkPiS_iS_, .Lfunc_end1-_Z5checkPiS_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 188
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4spinPiPdS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z4spinPiPdS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5checkPiS_iS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5checkPiS_iS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
