#include <cuda_runtime.h>

__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);

extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
	double * d_A, * d_B, * d_C;

	cudaMalloc((void **)&d_A, m * k * sizeof(double *));
	cudaMalloc((void **)&d_B, k * n * sizeof(double *));
	cudaMalloc((void **)&d_C, m * n * sizeof(double *));

	cudaMemcpy(d_A, A, m * k * sizeof(double *), cudaMemcpyHostToDevice);
    cudaMemcpy(d_B, B, k * n * sizeof(double *), cudaMemcpyHostToDevice);

    matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);

    cudaMemcpy(C, d_C, m * n * sizeof(double *), cudaMemcpyDeviceToHost);

	cudaFree(d_A);
	cudaFree(d_B);
	cudaFree(d_C);
}
}

__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){

    int i, j, l;
    double x;
	
	
	for(i=0;i < m; i++){
		for(j=0;j<n;j++){
			d_C[i*n + j]=0;
		}
		for(l=0;l < k;l++){
			x = d_A[i*k + l];
			for(j=0;j < n; j++){
				d_C[i*n + j] += x * d_B[l*n + j];
			}
		}
	}

}

	.file	"tmpxft_00318f4f_00000000-6_matmult_gpu1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
	.type	_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_, @function
_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18matmult_gpu1KerneliiiPdS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_, .-_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
	.globl	_Z18matmult_gpu1KerneliiiPdS_S_
	.type	_Z18matmult_gpu1KerneliiiPdS_S_, @function
_Z18matmult_gpu1KerneliiiPdS_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
	.cfi_endproc
.LFE2034:
	.size	_Z18matmult_gpu1KerneliiiPdS_S_, .-_Z18matmult_gpu1KerneliiiPdS_S_
	.globl	matmult_gpu1
	.type	matmult_gpu1, @function
matmult_gpu1:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movl	%edi, %edx
	imull	%r12d, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movslq	%edx, %rdx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	salq	$3, %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rsi
	leaq	40(%rsp), %rdi
	movq	%rdx, 24(%rsp)
	call	cudaMalloc@PLT
	movl	%r12d, %eax
	leaq	48(%rsp), %rdi
	imull	%ebp, %eax
	cltq
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	%ebx, %eax
	leaq	56(%rsp), %rdi
	imull	%ebp, %eax
	cltq
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movl	%r12d, %edx
	movl	%ebp, %esi
	movq	40(%rsp), %rcx
	movl	%ebx, %edi
	call	_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
.L9:
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	matmult_gpu1, .-matmult_gpu1
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18matmult_gpu1KerneliiiPdS_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18matmult_gpu1KerneliiiPdS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>

__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);

extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
	double * d_A, * d_B, * d_C;

	hipMalloc((void **)&d_A, m * k * sizeof(double *));
	hipMalloc((void **)&d_B, k * n * sizeof(double *));
	hipMalloc((void **)&d_C, m * n * sizeof(double *));

	hipMemcpy(d_A, A, m * k * sizeof(double *), hipMemcpyHostToDevice);
    hipMemcpy(d_B, B, k * n * sizeof(double *), hipMemcpyHostToDevice);

    matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);

    hipMemcpy(C, d_C, m * n * sizeof(double *), hipMemcpyDeviceToHost);

	hipFree(d_A);
	hipFree(d_B);
	hipFree(d_C);
}
}

__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){

    int i, j, l;
    double x;
	
	
	for(i=0;i < m; i++){
		for(j=0;j<n;j++){
			d_C[i*n + j]=0;
		}
		for(l=0;l < k;l++){
			x = d_A[i*k + l];
			for(j=0;j < n; j++){
				d_C[i*n + j] += x * d_B[l*n + j];
			}
		}
	}

}

	.text
	.file	"matmult_gpu1.hip"
	.globl	matmult_gpu1                    # -- Begin function matmult_gpu1
	.type	matmult_gpu1,@function
matmult_gpu1:                           # @matmult_gpu1
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 48(%rsp)                   # 8-byte Spill
	movq	%r8, 40(%rsp)                   # 8-byte Spill
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movl	%edx, %ebp
	movl	%esi, %r14d
	movl	%edi, %r15d
	movl	%edx, %eax
	imull	%edi, %eax
	movslq	%eax, %r13
	shlq	$3, %r13
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movl	%ebp, %eax
	imull	%r14d, %eax
	movslq	%eax, %rbx
	shlq	$3, %rbx
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	%r14d, %eax
	imull	%r15d, %eax
	movslq	%eax, %r12
	shlq	$3, %r12
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movl	%r15d, %edi
	movl	%r14d, %esi
	movl	%ebp, %edx
	callq	_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.LBB0_2:
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	matmult_gpu1, .Lfunc_end0-matmult_gpu1
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_ # -- Begin function _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
	.type	_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_,@function
_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_: # @_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18matmult_gpu1KerneliiiPdS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_, .Lfunc_end1-_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18matmult_gpu1KerneliiiPdS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18matmult_gpu1KerneliiiPdS_S_,@object # @_Z18matmult_gpu1KerneliiiPdS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z18matmult_gpu1KerneliiiPdS_S_
	.p2align	3, 0x0
_Z18matmult_gpu1KerneliiiPdS_S_:
	.quad	_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
	.size	_Z18matmult_gpu1KerneliiiPdS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18matmult_gpu1KerneliiiPdS_S_"
	.size	.L__unnamed_1, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18matmult_gpu1KerneliiiPdS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18matmult_gpu1KerneliiiPdS_S_ ; -- Begin function _Z18matmult_gpu1KerneliiiPdS_S_
	.globl	_Z18matmult_gpu1KerneliiiPdS_S_
	.p2align	8
	.type	_Z18matmult_gpu1KerneliiiPdS_S_,@function
_Z18matmult_gpu1KerneliiiPdS_S_:        ; @_Z18matmult_gpu1KerneliiiPdS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_11
; %bb.1:                                ; %.preheader36.lr.ph
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x20
	s_cmp_gt_i32 s5, 0
	s_mov_b32 s13, 0
	s_cselect_b32 s0, -1, 0
	s_cmp_gt_i32 s6, 0
	v_cndmask_b32_e64 v0, 0, 1, s0
	s_cselect_b32 s0, -1, 0
	s_mov_b32 s14, s13
	v_cndmask_b32_e64 v1, 0, 1, s0
	s_mov_b32 s7, 0
	v_cmp_ne_u32_e64 s0, 1, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e64 s1, 1, v1
.LBB0_2:                                ; %.preheader36
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_8 Depth 3
	s_mov_b32 s15, s13
	s_mov_b32 s12, s5
	s_lshl_b64 s[16:17], s[14:15], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s2, s16
	s_addc_u32 s17, s3, s17
	s_and_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[18:19], s[16:17]
	s_cbranch_vccnz .LBB0_4
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, v0
	s_add_i32 s12, s12, -1
	global_store_b64 v0, v[0:1], s[18:19]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_10
; %bb.5:                                ; %.lr.ph41
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s12, 0
	s_mul_i32 s15, s7, s6
	s_mov_b32 s22, s12
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_8 Depth 3
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_9
; %bb.7:                                ; %.lr.ph39
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mov_b32 s21, s13
	s_add_u32 s18, s10, s18
	s_addc_u32 s19, s11, s19
	s_add_i32 s20, s22, s15
	s_mov_b32 s23, s5
	s_lshl_b64 s[20:21], s[20:21], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s8, s20
	s_addc_u32 s21, s9, s21
	global_load_b64 v[1:2], v0, s[20:21]
	s_mov_b64 s[20:21], s[16:17]
.LBB0_8:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[18:19]
	global_load_b64 v[5:6], v0, s[20:21]
	s_add_i32 s23, s23, -1
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], v[1:2], v[3:4], v[5:6]
	global_store_b64 v0, v[3:4], s[20:21]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s23, 0
	s_cbranch_scc1 .LBB0_8
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_add_i32 s22, s22, 1
	s_add_i32 s12, s12, s5
	s_cmp_lg_u32 s22, s6
	s_cbranch_scc1 .LBB0_6
.LBB0_10:                               ; %._crit_edge42
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s7, s7, 1
	s_add_i32 s14, s14, s5
	s_cmp_lg_u32 s7, s4
	s_cbranch_scc1 .LBB0_2
.LBB0_11:                               ; %._crit_edge44
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18matmult_gpu1KerneliiiPdS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18matmult_gpu1KerneliiiPdS_S_, .Lfunc_end0-_Z18matmult_gpu1KerneliiiPdS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 368
; NumSgprs: 26
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18matmult_gpu1KerneliiiPdS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z18matmult_gpu1KerneliiiPdS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
