#include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/


int halo_buffer_size = 0;
char *halo_buffer_d = NULL;








__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {

int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);

if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {

if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
}
	.file	"tmpxft_0037f5ad_00000000-6_copy_kernel_frombuf.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
	.type	_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii, @function
_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 304
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii, .-_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
	.globl	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.type	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, @function
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .-_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	halo_buffer_d
	.bss
	.align 8
	.type	halo_buffer_d, @object
	.size	halo_buffer_d, 8
halo_buffer_d:
	.zero	8
	.globl	halo_buffer_size
	.align 4
	.type	halo_buffer_size, @object
	.size	halo_buffer_size, 4
halo_buffer_size:
	.zero	4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/


int halo_buffer_size = 0;
char *halo_buffer_d = NULL;








__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {

int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);

if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {

if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
}
	.text
	.file	"copy_kernel_frombuf.hip"
	.globl	_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii # -- Begin function _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.type	_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@function
_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii: # @_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .Lfunc_end0-_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	halo_buffer_size,@object        # @halo_buffer_size
	.bss
	.globl	halo_buffer_size
	.p2align	2, 0x0
halo_buffer_size:
	.long	0                               # 0x0
	.size	halo_buffer_size, 4

	.type	halo_buffer_d,@object           # @halo_buffer_d
	.globl	halo_buffer_d
	.p2align	3, 0x0
halo_buffer_d:
	.quad	0
	.size	halo_buffer_d, 8

	.type	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@object # @_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.p2align	3, 0x0
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
	.quad	_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.size	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii"
	.size	.L__unnamed_1, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii ; -- Begin function _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.globl	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
	.p2align	8
	.type	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@function
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii: ; @_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b512 s[16:31], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_cmp_lg_u32 s22, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s13, s3, v[1:2]
	v_mul_lo_u32 v4, v2, s22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s16, v4
	s_cbranch_scc0 .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, s17, v1
	s_mov_b32 s4, 0
	s_and_b32 s3, vcc_lo, exec_lo
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s4, -1
	s_mov_b32 s3, 0
.LBB0_3:                                ; %Flow193
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	v_cmp_gt_i32_e32 vcc_lo, s17, v1
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s4
.LBB0_5:                                ; %Flow194
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB0_42
; %bb.6:
	v_bfe_u32 v2, v0, 10, 10
	s_load_b32 s3, s[0:1], 0x68
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, s14, s2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v5, s23
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s3, 0xffff
	v_add_nc_u32_e32 v2, s18, v5
	s_cmp_lg_u32 s23, 1
	s_cbranch_scc0 .LBB0_8
; %bb.7:
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, s19, v2
	s_mov_b32 s4, 0
	s_and_b32 s3, vcc_lo, exec_lo
	s_branch .LBB0_9
.LBB0_8:
	s_mov_b32 s4, -1
	s_mov_b32 s3, 0
.LBB0_9:                                ; %Flow190
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_11
; %bb.10:
	v_cmp_gt_i32_e32 vcc_lo, s19, v2
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s4
.LBB0_11:                               ; %Flow191
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_42
; %bb.12:
	v_bfe_u32 v0, v0, 20, 10
	s_and_b32 s2, s2, 0xffff
	s_cmp_lg_u32 s24, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1]
	v_mul_lo_u32 v0, v6, s24
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s20, v0
	s_cbranch_scc0 .LBB0_14
; %bb.13:
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, s21, v3
	s_mov_b32 s3, 0
	s_and_b32 s2, vcc_lo, exec_lo
	s_branch .LBB0_15
.LBB0_14:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
.LBB0_15:                               ; %Flow187
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_17
; %bb.16:
	v_cmp_gt_i32_e32 vcc_lo, s21, v3
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
.LBB0_17:                               ; %Flow188
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_42
; %bb.18:
	s_load_b64 s[2:3], s[0:1], 0x50
	v_mad_u64_u32 v[6:7], null, v3, s26, v[2:3]
	s_mov_b32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, v6, s25, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s3, 0
	s_cselect_b32 s4, -1, 0
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_20
; %bb.19:
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v1, v2, s31
	s_mul_i32 s3, s2, s31
	s_branch .LBB0_21
.LBB0_20:
	s_mov_b32 s5, -1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $sgpr3
.LBB0_21:                               ; %Flow186
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_23
; %bb.22:
	s_mul_i32 s3, s2, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_lo_u32 v1, s3, v2
.LBB0_23:
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_42
; %bb.24:                               ; %.lr.ph
	s_mul_i32 s5, s30, s24
	s_mul_i32 s6, s29, s23
	v_mul_lo_u32 v0, s5, v0
	s_mul_i32 s5, s28, s22
	v_mul_lo_u32 v2, s6, v5
	v_mul_lo_u32 v3, s5, v4
	s_load_b128 s[12:15], s[0:1], 0x0
	s_mul_i32 s5, s26, s25
	s_ashr_i32 s1, s31, 31
	s_cmp_gt_u32 s31, 3
	s_mov_b32 s0, s31
	s_mov_b32 s10, 0
	s_mov_b32 s11, 0
	v_add3_u32 v0, v2, v0, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v3, s3, v0
	s_mul_i32 s3, s5, s27
	s_mul_i32 s5, s3, s31
	s_cselect_b32 s3, -1, 0
	s_ashr_i32 s6, s5, 31
	s_and_b32 s4, exec_lo, s4
	s_cselect_b32 s8, s1, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v2, vcc_lo
	v_add_co_u32 v6, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v4, vcc_lo
	s_cselect_b32 s9, s31, s5
.LBB0_25:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_27 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_29
; %bb.26:                               ; %.lr.ph.i.i.preheader
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_ashr_i32 s4, s10, 31
	v_add_co_u32 v2, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v3, vcc_lo, s4, v7, vcc_lo
	s_mov_b64 s[6:7], 0
	s_mov_b64 s[4:5], s[0:1]
.LBB0_27:                               ; %.lr.ph.i.i
                                        ;   Parent Loop BB0_25 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, v0, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
	global_load_u8 v10, v[4:5], off
	s_add_u32 s4, s4, -4
	s_addc_u32 s5, s5, -1
	s_add_u32 s6, s6, 4
	v_cmp_gt_u64_e64 s12, s[4:5], 3
	s_addc_u32 s7, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	global_store_b8 v[8:9], v10, off
	global_load_u8 v10, v[4:5], off offset:1
	s_waitcnt vmcnt(0)
	global_store_b8 v[8:9], v10, off offset:1
	global_load_u8 v10, v[4:5], off offset:2
	s_waitcnt vmcnt(0)
	global_store_b8 v[8:9], v10, off offset:2
	global_load_u8 v4, v[4:5], off offset:3
	s_waitcnt vmcnt(0)
	global_store_b8 v[8:9], v4, off offset:3
	s_cbranch_vccnz .LBB0_27
; %bb.28:                               ; %Flow182
                                        ;   in Loop: Header=BB0_25 Depth=1
	v_add_co_u32 v4, vcc_lo, v0, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_branch .LBB0_30
.LBB0_29:                               ;   in Loop: Header=BB0_25 Depth=1
	s_mul_i32 s4, s11, s31
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_ashr_i32 s5, s4, 31
	v_add_co_u32 v2, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
	s_mov_b64 s[4:5], s[0:1]
.LBB0_30:                               ; %NodeBlock176
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i64_e64 s6, s[4:5], 2
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_36
; %bb.31:                               ; %NodeBlock
                                        ;   in Loop: Header=BB0_25 Depth=1
	v_cmp_gt_i64_e64 s6, s[4:5], 2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_mov_b32 s6, -1
	s_cbranch_vccz .LBB0_34
; %bb.32:                               ; %LeafBlock174
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_cmp_eq_u64 s[4:5], 3
	s_mov_b32 s6, 0
	s_cbranch_scc0 .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_u8 v8, v[2:3], off offset:2
	s_mov_b32 s6, -1
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:2
.LBB0_34:                               ; %Flow178
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_mov_b32 s7, 0
	s_and_b32 vcc_lo, exec_lo, s6
	s_mov_b32 s6, 0
	s_cbranch_vccz .LBB0_37
; %bb.35:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_u8 v8, v[2:3], off offset:1
	s_mov_b32 s6, -1
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:1
	s_branch .LBB0_37
.LBB0_36:                               ;   in Loop: Header=BB0_25 Depth=1
	s_mov_b32 s7, -1
	s_mov_b32 s6, 0
.LBB0_37:                               ; %Flow
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_and_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccz .LBB0_39
; %bb.38:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_cmp_eq_u64 s[4:5], 1
	s_cselect_b32 s6, -1, 0
.LBB0_39:                               ; %Flow181
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v2, off
.LBB0_41:                               ; %_ZL6memcpyPvPKvm.exit
                                        ;   in Loop: Header=BB0_25 Depth=1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_add_i32 s11, s11, 1
	s_add_i32 s10, s10, s31
	s_cmp_lg_u32 s11, s2
	s_cbranch_scc1 .LBB0_25
.LBB0_42:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .Lfunc_end0-_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1124
; NumSgprs: 34
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
