/*********************************************************************
*
*  © (or copyright) 2020. Triad National Security, LLC.
*  All rights reserved.
*  This program was produced under U.S. Government contract 
*  89233218CNA000001 for Los AlamosNational Laboratory (LANL), 
*  which is operated by Triad National Security, LLC for the U.S.
*  Department of Energy/National Nuclear Security Administration. 
*  All rights in the program are reserved by Triad National 
*  Security, LLC, and the U.S. Department of Energy/National Nuclear
*  Security Administration. The Government is granted for itself 
*  and others acting on its behalf a nonexclusive, paid-up, 
*  irrevocable worldwide license in this material to reproduce, 
*  prepare derivative works, distribute copies to the public, 
*  perform publicly and display publicly, and to permit others 
*  to do so.
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*   * Redistributions of source code must retain the above copyright
*     notice, this list of conditions and the following disclaimer.
*   * Redistributions in binary form must reproduce the above
*     copyright notice, this list of conditions and the following
*     disclaimer in the documentation and/or other materials provided
*     with the distribution.
*   * Neither the name of the copyright holder nor the names of its
*     contributors may be used to endorse or promote products derived
*     from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
*  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
*  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
*  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
*  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
*  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
*  POSSIBILITY OF SUCH DAMAGE.
*
* Author: Alex von Sternberg
*********************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>

#define THREADS_PER_BLOCK 256

__device__ bool d_error;

__global__ void crs(float* fPoints, int* iPoints, int cloudSize, int maxRay, float* fStart, int* iStart, float* fStartVoxel, int* outPoints, int* outSizes, int* min, int* max, float resolution)
{
  int index = threadIdx.x + blockIdx.x * blockDim.x;

  // if there are extra threads, don't run them
  if(index >= cloudSize)
    return;

  // init vars
  bool done = false;

  // calculate normal vector in direction of sensor->point
  float direction[3] = {fPoints[index]-fStart[0], fPoints[cloudSize+index]-fStart[1], fPoints[2*cloudSize+index]-fStart[2]};
  float directionMagnitude = powf(powf(direction[0],2) + powf(direction[1],2) + powf(direction[2],2),0.5);

  // variables used for ray casting algorithm
  int stepDirection[3];        // +/- step in each cardinal direction
  float accumulatedError[3];   // error accumulated in each direction
  float deltaError[3];         // change in error accumulated for a step in a direction
  int currentIndex[3];         // for tracking the index as we trace
  int pointIndex[3];           // index of final occupied point
  bool usePI = true;          // we only check for the final point if it is on the map, 
                               // otherwise we are done when we leave the map

  // Set the starting position to the sensor position, and the final index
  for(int i = 0; i < 3; i++)
  {
    currentIndex[i] = iStart[i];
  }
  pointIndex[0] = iPoints[index];
  pointIndex[1] = iPoints[cloudSize+index];
  pointIndex[2] = iPoints[2*cloudSize+index];

  // If the occupied point is in the map, we use it as a stopping point
  if(pointIndex[0] < min[0] || pointIndex[0] > max[0] ||
     pointIndex[1] < min[1] || pointIndex[1] > max[1] ||
     pointIndex[2] < min[2] || pointIndex[2] > max[2])
    usePI = false;

  // check direction magnitude for divide by zero or same cell
  if(fabs(directionMagnitude) < resolution)
  {
    d_error = true;
    return;
  }

  // set up initial values in each direction
  for(int dir = 0; dir < 3; dir++)
  {
    direction[dir] = fdividef(direction[dir],directionMagnitude);
    if(direction[dir] > 0.0)
      stepDirection[dir] = 1;
    else if(direction[dir] < 0.0)
      stepDirection[dir] = -1;

    float voxelBorder = fStartVoxel[dir] + stepDirection[dir]*resolution*0.5;
    accumulatedError[dir] = fdividef((voxelBorder - fStart[dir]),direction[dir]);
    deltaError[dir] = fdividef(resolution,fabs(direction[dir]));
  }
  
  int count = 0;
  // loop until we are out of map bounds
  while(!done)
  {
    // find direction of min error
    int dim = 2;
    if(fabs(accumulatedError[0]) < fabs(accumulatedError[1]) && fabs(accumulatedError[0]) < fabs(accumulatedError[2]))
      dim = 0;
    else if(fabs(accumulatedError[1]) < fabs(accumulatedError[0]) && fabs(accumulatedError[1]) < fabs(accumulatedError[2]))
      dim = 1;

    // advance in direction of min error
    currentIndex[dim] = currentIndex[dim] + stepDirection[dim];
    accumulatedError[dim] = accumulatedError[dim] + deltaError[dim]; 

    // done if we are at occ point
    if(usePI)
    {
      if(currentIndex[0] == pointIndex[0] &&
         currentIndex[1] == pointIndex[1] &&
         currentIndex[2] == pointIndex[2])
      {
        done = true;
      }
    }

    // if we are off the map, we are done. 
    if(currentIndex[0] < min[0] || currentIndex[0] > max[0] ||
       currentIndex[1] < min[1] || currentIndex[1] > max[1] ||
       currentIndex[2] < min[2] || currentIndex[2] > max[2])
    {
      done = true;
    }
      
    //otherwise we mark the current index as unoccupied
    if(!done)
    {
      outPoints[index*maxRay+count] = currentIndex[0];
      outPoints[index*maxRay+(cloudSize*maxRay)+count] = currentIndex[1];
      outPoints[index*maxRay+(2*cloudSize*maxRay)+count] = currentIndex[2];
    }
    count = count + 1;
  }
  outSizes[index] = count;
  return;
}

bool castRays(float* fPoints, int* iPoints, int cloudSize, int maxRay, float* fStart, int* iStart, float* fStartVoxel, int* outPoints, int* outSizes, int minX, int maxX, int minY, int maxY, int minZ, int maxZ, float resolution) 
{
  // Device copies of three inputs and output, size of allocated memory, num of threads and blocks
  float *d_fPoints, *d_fStart, *d_fStartVoxel;
  int *d_iPoints, *d_outPoints, *d_iStart, *d_outSizes, *d_min, *d_max;
  int min[3] = {minX, minY, minZ};
  int max[3] = {maxX, maxY, maxZ};
  int thr, blk;
  bool h_error = false;
  int temp;
  for(int i = 0; i < 3; i ++)
  {
    if(min[i] > max[i])
    {
      temp = min[i];
      min[i] = max[i];
      max[i] = temp;
    }
  }
  //cudaMemset(&d_error,0,sizeof(bool));

  // Alloc memory for device copies of inputs and outputs
  cudaMalloc((void**)&d_fPoints, ((cloudSize*3) * sizeof(float)));
  cudaMalloc((void**)&d_iPoints, ((cloudSize*3) * sizeof(int)));
  cudaMalloc((void**)&d_fStart, (3 * sizeof(float)));
  cudaMalloc((void**)&d_iStart, (3 * sizeof(int)));
  cudaMalloc((void**)&d_fStartVoxel, (3 * sizeof(float)));
  cudaMalloc((void**)&d_min, (3 * sizeof(int)));
  cudaMalloc((void**)&d_max, (3 * sizeof(int)));
  cudaMalloc((void**)&d_outPoints, ((cloudSize*maxRay*3) * sizeof(int)));
  cudaMalloc((void**)&d_outSizes, (cloudSize * sizeof(int)));

  // Copy inputs to device
  cudaMemcpy(d_fPoints, fPoints, ((cloudSize*3) * sizeof(float)), cudaMemcpyHostToDevice);
  cudaMemcpy(d_iPoints, iPoints, ((cloudSize*3) * sizeof(int)), cudaMemcpyHostToDevice);
  cudaMemcpy(d_fStart, fStart, (3 * sizeof(float)), cudaMemcpyHostToDevice);
  cudaMemcpy(d_iStart, iStart, (3 * sizeof(int)), cudaMemcpyHostToDevice);
  cudaMemcpy(d_fStartVoxel, fStartVoxel, (3 * sizeof(float)), cudaMemcpyHostToDevice);
  cudaMemcpy(d_min, min, (3 * sizeof(int)), cudaMemcpyHostToDevice);
  cudaMemcpy(d_max, max, (3 * sizeof(int)), cudaMemcpyHostToDevice);

  // Calculates blocks and threads and launch average3 kernel on GPU
  thr=THREADS_PER_BLOCK;
  blk=cloudSize/THREADS_PER_BLOCK+1;
  crs<<<blk,thr>>>(d_fPoints, d_iPoints, cloudSize, maxRay, d_fStart, d_iStart, d_fStartVoxel, d_outPoints, 
                   d_outSizes, d_min, d_max, resolution);

  // Wait for the GPU to finish
  cudaDeviceSynchronize();

  //// Copy result back to host and cleanup
  cudaMemcpy(outPoints, d_outPoints, (cloudSize*maxRay*3) * sizeof(int), cudaMemcpyDeviceToHost);
  cudaMemcpy(outSizes, d_outSizes, cloudSize * sizeof(int), cudaMemcpyDeviceToHost);
  //cudaMemcpyFromSymbol(&h_error, "d_error", sizeof(bool), 0, cudaMemcpyDeviceToHost);
  cudaFree(d_outSizes); 
  cudaFree(d_outPoints);  
  cudaFree(d_max);  
  cudaFree(d_min);  
  cudaFree(d_fStartVoxel); 
  cudaFree(d_iStart); 
  cudaFree(d_fStart); 
  cudaFree(d_iPoints); 
  cudaFree(d_fPoints);
  return !h_error;
}

	.file	"tmpxft_00216605_00000000-6_rolling_map.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f
	.type	_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f, @function
_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	296(%rsp), %rax
	movl	%edx, 76(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	304(%rsp), %rax
	movl	%ecx, 72(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	312(%rsp), %rax
	movq	%r8, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	320(%rsp), %rax
	movq	%r9, 56(%rsp)
	movq	%rax, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f, .-_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f
	.globl	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.type	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f, @function
_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f
	.cfi_endproc
.LFE2053:
	.size	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f, .-_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.globl	_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif
	.type	_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif, @function
_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	264(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	272(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	movl	280(%rsp), %eax
	movl	%eax, 160(%rsp)
	movl	296(%rsp), %eax
	movl	%eax, 164(%rsp)
	movl	312(%rsp), %eax
	movl	%eax, 168(%rsp)
	movl	288(%rsp), %eax
	movl	%eax, 172(%rsp)
	movl	304(%rsp), %eax
	movl	%eax, 176(%rsp)
	movl	320(%rsp), %eax
	movl	%eax, 180(%rsp)
	xorl	%eax, %eax
.L10:
	movl	160(%rsp,%rax), %edx
	movl	172(%rsp,%rax), %ecx
	cmpl	%ecx, %edx
	jle	.L9
	movl	%ecx, 160(%rsp,%rax)
	movl	%edx, 172(%rsp,%rax)
.L9:
	addq	$4, %rax
	cmpq	$12, %rax
	jne	.L10
	leal	(%rbx,%rbx,2), %eax
	leaq	64(%rsp), %rdi
	movss	%xmm0, 60(%rsp)
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	leaq	104(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	leaq	120(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	leaq	128(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	movl	%ebx, %eax
	leaq	96(%rsp), %rdi
	imull	%ebp, %eax
	leal	(%rax,%rax,2), %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	movslq	%ebx, %rax
	leaq	112(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	88(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movq	104(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movq	120(%rsp), %rdi
	movl	$1, %ecx
	leaq	160(%rsp), %rsi
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$12, %edx
	movq	128(%rsp), %rdi
	leaq	172(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	%ebx, %eax
	movl	$256, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	idivl	%ecx
	movl	$16777217, %edx
	movl	$1, %ecx
	salq	$8, %rdx
	incl	%eax
	movl	%eax, 136(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 140(%rsp)
	movq	136(%rsp), %rdi
	movl	144(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	60(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L11
	pushq	%rax
	.cfi_def_cfa_offset 264
	movl	%ebp, %ecx
	movl	%ebx, %edx
	pushq	136(%rsp)
	.cfi_def_cfa_offset 272
	pushq	136(%rsp)
	.cfi_def_cfa_offset 280
	pushq	136(%rsp)
	.cfi_def_cfa_offset 288
	pushq	128(%rsp)
	.cfi_def_cfa_offset 296
	pushq	120(%rsp)
	.cfi_def_cfa_offset 304
	movq	152(%rsp), %r9
	movq	120(%rsp), %r8
	movq	136(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z46__device_stub__Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_fPfPiiiS_S0_S_S0_S0_S0_S0_f
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L11:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	96(%rsp), %rsi
	movl	$2, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdx
	movq	112(%rsp), %rsi
	movl	$2, %ecx
	movq	48(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	movb	$1, %al
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif, .-_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f"
.LC1:
	.string	"d_error"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZL7d_error(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7d_error
	.comm	_ZL7d_error,1,1
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*********************************************************************
*
*  © (or copyright) 2020. Triad National Security, LLC.
*  All rights reserved.
*  This program was produced under U.S. Government contract 
*  89233218CNA000001 for Los AlamosNational Laboratory (LANL), 
*  which is operated by Triad National Security, LLC for the U.S.
*  Department of Energy/National Nuclear Security Administration. 
*  All rights in the program are reserved by Triad National 
*  Security, LLC, and the U.S. Department of Energy/National Nuclear
*  Security Administration. The Government is granted for itself 
*  and others acting on its behalf a nonexclusive, paid-up, 
*  irrevocable worldwide license in this material to reproduce, 
*  prepare derivative works, distribute copies to the public, 
*  perform publicly and display publicly, and to permit others 
*  to do so.
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*   * Redistributions of source code must retain the above copyright
*     notice, this list of conditions and the following disclaimer.
*   * Redistributions in binary form must reproduce the above
*     copyright notice, this list of conditions and the following
*     disclaimer in the documentation and/or other materials provided
*     with the distribution.
*   * Neither the name of the copyright holder nor the names of its
*     contributors may be used to endorse or promote products derived
*     from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
*  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
*  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
*  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
*  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
*  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
*  POSSIBILITY OF SUCH DAMAGE.
*
* Author: Alex von Sternberg
*********************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>


#define THREADS_PER_BLOCK 256

__device__ bool d_error;

__global__ void crs(float* fPoints, int* iPoints, int cloudSize, int maxRay, float* fStart, int* iStart, float* fStartVoxel, int* outPoints, int* outSizes, int* min, int* max, float resolution)
{
  int index = threadIdx.x + blockIdx.x * blockDim.x;

  // if there are extra threads, don't run them
  if(index >= cloudSize)
    return;

  // init vars
  bool done = false;

  // calculate normal vector in direction of sensor->point
  float direction[3] = {fPoints[index]-fStart[0], fPoints[cloudSize+index]-fStart[1], fPoints[2*cloudSize+index]-fStart[2]};
  float directionMagnitude = powf(powf(direction[0],2) + powf(direction[1],2) + powf(direction[2],2),0.5);

  // variables used for ray casting algorithm
  int stepDirection[3];        // +/- step in each cardinal direction
  float accumulatedError[3];   // error accumulated in each direction
  float deltaError[3];         // change in error accumulated for a step in a direction
  int currentIndex[3];         // for tracking the index as we trace
  int pointIndex[3];           // index of final occupied point
  bool usePI = true;          // we only check for the final point if it is on the map, 
                               // otherwise we are done when we leave the map

  // Set the starting position to the sensor position, and the final index
  for(int i = 0; i < 3; i++)
  {
    currentIndex[i] = iStart[i];
  }
  pointIndex[0] = iPoints[index];
  pointIndex[1] = iPoints[cloudSize+index];
  pointIndex[2] = iPoints[2*cloudSize+index];

  // If the occupied point is in the map, we use it as a stopping point
  if(pointIndex[0] < min[0] || pointIndex[0] > max[0] ||
     pointIndex[1] < min[1] || pointIndex[1] > max[1] ||
     pointIndex[2] < min[2] || pointIndex[2] > max[2])
    usePI = false;

  // check direction magnitude for divide by zero or same cell
  if(fabs(directionMagnitude) < resolution)
  {
    d_error = true;
    return;
  }

  // set up initial values in each direction
  for(int dir = 0; dir < 3; dir++)
  {
    direction[dir] = fdividef(direction[dir],directionMagnitude);
    if(direction[dir] > 0.0)
      stepDirection[dir] = 1;
    else if(direction[dir] < 0.0)
      stepDirection[dir] = -1;

    float voxelBorder = fStartVoxel[dir] + stepDirection[dir]*resolution*0.5;
    accumulatedError[dir] = fdividef((voxelBorder - fStart[dir]),direction[dir]);
    deltaError[dir] = fdividef(resolution,fabs(direction[dir]));
  }
  
  int count = 0;
  // loop until we are out of map bounds
  while(!done)
  {
    // find direction of min error
    int dim = 2;
    if(fabs(accumulatedError[0]) < fabs(accumulatedError[1]) && fabs(accumulatedError[0]) < fabs(accumulatedError[2]))
      dim = 0;
    else if(fabs(accumulatedError[1]) < fabs(accumulatedError[0]) && fabs(accumulatedError[1]) < fabs(accumulatedError[2]))
      dim = 1;

    // advance in direction of min error
    currentIndex[dim] = currentIndex[dim] + stepDirection[dim];
    accumulatedError[dim] = accumulatedError[dim] + deltaError[dim]; 

    // done if we are at occ point
    if(usePI)
    {
      if(currentIndex[0] == pointIndex[0] &&
         currentIndex[1] == pointIndex[1] &&
         currentIndex[2] == pointIndex[2])
      {
        done = true;
      }
    }

    // if we are off the map, we are done. 
    if(currentIndex[0] < min[0] || currentIndex[0] > max[0] ||
       currentIndex[1] < min[1] || currentIndex[1] > max[1] ||
       currentIndex[2] < min[2] || currentIndex[2] > max[2])
    {
      done = true;
    }
      
    //otherwise we mark the current index as unoccupied
    if(!done)
    {
      outPoints[index*maxRay+count] = currentIndex[0];
      outPoints[index*maxRay+(cloudSize*maxRay)+count] = currentIndex[1];
      outPoints[index*maxRay+(2*cloudSize*maxRay)+count] = currentIndex[2];
    }
    count = count + 1;
  }
  outSizes[index] = count;
  return;
}

bool castRays(float* fPoints, int* iPoints, int cloudSize, int maxRay, float* fStart, int* iStart, float* fStartVoxel, int* outPoints, int* outSizes, int minX, int maxX, int minY, int maxY, int minZ, int maxZ, float resolution) 
{
  // Device copies of three inputs and output, size of allocated memory, num of threads and blocks
  float *d_fPoints, *d_fStart, *d_fStartVoxel;
  int *d_iPoints, *d_outPoints, *d_iStart, *d_outSizes, *d_min, *d_max;
  int min[3] = {minX, minY, minZ};
  int max[3] = {maxX, maxY, maxZ};
  int thr, blk;
  bool h_error = false;
  int temp;
  for(int i = 0; i < 3; i ++)
  {
    if(min[i] > max[i])
    {
      temp = min[i];
      min[i] = max[i];
      max[i] = temp;
    }
  }
  //cudaMemset(&d_error,0,sizeof(bool));

  // Alloc memory for device copies of inputs and outputs
  hipMalloc((void**)&d_fPoints, ((cloudSize*3) * sizeof(float)));
  hipMalloc((void**)&d_iPoints, ((cloudSize*3) * sizeof(int)));
  hipMalloc((void**)&d_fStart, (3 * sizeof(float)));
  hipMalloc((void**)&d_iStart, (3 * sizeof(int)));
  hipMalloc((void**)&d_fStartVoxel, (3 * sizeof(float)));
  hipMalloc((void**)&d_min, (3 * sizeof(int)));
  hipMalloc((void**)&d_max, (3 * sizeof(int)));
  hipMalloc((void**)&d_outPoints, ((cloudSize*maxRay*3) * sizeof(int)));
  hipMalloc((void**)&d_outSizes, (cloudSize * sizeof(int)));

  // Copy inputs to device
  hipMemcpy(d_fPoints, fPoints, ((cloudSize*3) * sizeof(float)), hipMemcpyHostToDevice);
  hipMemcpy(d_iPoints, iPoints, ((cloudSize*3) * sizeof(int)), hipMemcpyHostToDevice);
  hipMemcpy(d_fStart, fStart, (3 * sizeof(float)), hipMemcpyHostToDevice);
  hipMemcpy(d_iStart, iStart, (3 * sizeof(int)), hipMemcpyHostToDevice);
  hipMemcpy(d_fStartVoxel, fStartVoxel, (3 * sizeof(float)), hipMemcpyHostToDevice);
  hipMemcpy(d_min, min, (3 * sizeof(int)), hipMemcpyHostToDevice);
  hipMemcpy(d_max, max, (3 * sizeof(int)), hipMemcpyHostToDevice);

  // Calculates blocks and threads and launch average3 kernel on GPU
  thr=THREADS_PER_BLOCK;
  blk=cloudSize/THREADS_PER_BLOCK+1;
  crs<<<blk,thr>>>(d_fPoints, d_iPoints, cloudSize, maxRay, d_fStart, d_iStart, d_fStartVoxel, d_outPoints, 
                   d_outSizes, d_min, d_max, resolution);

  // Wait for the GPU to finish
  hipDeviceSynchronize();

  //// Copy result back to host and cleanup
  hipMemcpy(outPoints, d_outPoints, (cloudSize*maxRay*3) * sizeof(int), hipMemcpyDeviceToHost);
  hipMemcpy(outSizes, d_outSizes, cloudSize * sizeof(int), hipMemcpyDeviceToHost);
  //cudaMemcpyFromSymbol(&h_error, "d_error", sizeof(bool), 0, cudaMemcpyDeviceToHost);
  hipFree(d_outSizes); 
  hipFree(d_outPoints);  
  hipFree(d_max);  
  hipFree(d_min);  
  hipFree(d_fStartVoxel); 
  hipFree(d_iStart); 
  hipFree(d_fStart); 
  hipFree(d_iPoints); 
  hipFree(d_fPoints);
  return !h_error;
}

	.text
	.file	"rolling_map.hip"
	.globl	_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f # -- Begin function _Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.type	_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f,@function
_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f: # @_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f, .Lfunc_end0-_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.cfi_endproc
                                        # -- End function
	.globl	_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif # -- Begin function _Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif
	.type	_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif,@function
_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif:  # @_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 68(%rsp)                 # 4-byte Spill
	movq	%r9, 128(%rsp)                  # 8-byte Spill
	movq	%r8, 120(%rsp)                  # 8-byte Spill
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, 112(%rsp)                 # 8-byte Spill
	movq	%rdi, 104(%rsp)                 # 8-byte Spill
	movl	256(%rsp), %eax
	movl	240(%rsp), %ecx
	movl	224(%rsp), %edx
	movl	248(%rsp), %esi
	movl	232(%rsp), %edi
	movl	216(%rsp), %r8d
	movl	%r8d, 84(%rsp)
	movl	%edi, 88(%rsp)
	movl	%esi, 92(%rsp)
	movl	%edx, 72(%rsp)
	movl	%ecx, 76(%rsp)
	movl	%eax, 80(%rsp)
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	84(%rsp,%rax,4), %ecx
	movl	72(%rsp,%rax,4), %edx
	cmpl	%edx, %ecx
	jle	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movl	%edx, 84(%rsp,%rax,4)
	movl	%ecx, 72(%rsp,%rax,4)
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rax
	cmpq	$3, %rax
	jne	.LBB1_1
# %bb.4:
	leal	(%r15,%r15,2), %eax
	movslq	%eax, %rbx
	leaq	(,%rbx,4), %rbp
	leaq	96(%rsp), %r13
	movq	%r13, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$12, %esi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$12, %esi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$12, %esi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$12, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$12, %esi
	callq	hipMalloc
	imull	%r14d, %ebx
	movslq	%ebx, %r12
	shlq	$2, %r12
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%r14d, 64(%rsp)                 # 4-byte Spill
	movslq	%r15d, %r14
	leaq	(,%r14,4), %rbx
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rax
	movq	(%rax), %rdi
	movl	$12, %edx
	movq	120(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$12, %edx
	movq	128(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	movl	$12, %edx
	movq	192(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	leaq	84(%rsp), %rsi
	movl	$12, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	leaq	72(%rsp), %rsi
	movl	$12, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	255(%r14), %edi
	testl	%r14d, %r14d
	cmovnsl	%r15d, %edi
	sarl	$8, %edi
	incl	%edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	96(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	56(%rsp), %r8
	movq	24(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%r15d, %edx
	movl	72(%rsp), %ecx                  # 4-byte Reload
	movss	76(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	8(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB1_6:
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rsi
	movq	200(%rsp), %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	208(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movb	$1, %al
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif, .Lfunc_end1-_Z8castRaysPfPiiiS_S0_S_S0_S0_iiiiiif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_error, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$1, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_error,@object                 # @d_error
	.local	d_error
	.comm	d_error,1,1
	.type	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f,@object # @_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.section	.rodata,"a",@progbits
	.globl	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.p2align	3, 0x0
_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f:
	.quad	_Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.size	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"d_error"
	.size	.L__unnamed_2, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_error
	.addrsig_sym _Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f ; -- Begin function _Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.globl	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
	.p2align	8
	.type	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f,@function
_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f:       ; @_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b64 s[22:23], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s22, v5
	s_cbranch_execz .LBB0_43
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_add_nc_u32_e32 v7, s22, v5
	v_ashrrev_i32_e32 v6, 31, v5
	s_ashr_i32 s3, s22, 31
	s_mov_b32 s2, s22
                                        ; implicit-def: $sgpr20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, s22, v7
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[0:1], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v11, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v13, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v1, vcc_lo
	s_clause 0x2
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[11:12], off
	global_load_b32 v4, v[13:14], off
	s_clause 0x2
	s_load_b256 s[8:15], s[0:1], 0x18
	s_load_b128 s[16:19], s[0:1], 0x38
	s_load_b64 s[24:25], s[0:1], 0x48
	s_mov_b64 s[4:5], 0
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[26:27], s[8:9], 0x0
	s_load_b32 s28, s[8:9], 0x8
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_load_b32 s29, s[10:11], 0x0
	s_cmp_eq_u32 s4, 2
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s22, s29, s22
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 s21, s29, s21
	s_cmp_eq_u32 s4, 0
	s_cselect_b32 s20, s29, s20
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s4, 3
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	v_add_co_u32 v12, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s5, exec_lo
	global_load_b32 v11, v[12:13], off
	v_add_co_u32 v12, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[0:1], off
	s_load_b32 s2, s[18:19], 0x0
                                        ; implicit-def: $sgpr6
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s2, v11
	v_cmpx_le_i32_e64 s2, v11
	s_cbranch_execz .LBB0_13
; %bb.4:
	s_load_b32 s3, s[24:25], 0x0
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $sgpr6
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s2, s3, v11
	v_cmpx_ge_i32_e64 s3, v11
	s_cbranch_execz .LBB0_12
; %bb.5:
	s_load_b32 s4, s[18:19], 0x4
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $sgpr6
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_cmp_gt_i32_e64 s3, s4, v12
	v_cmpx_le_i32_e64 s4, v12
	s_cbranch_execz .LBB0_11
; %bb.6:
	s_load_b32 s4, s[24:25], 0x4
	s_mov_b32 s29, exec_lo
                                        ; implicit-def: $sgpr6
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s11, s4, v12
	v_cmpx_ge_i32_e64 s4, v12
	s_cbranch_execz .LBB0_10
; %bb.7:
	s_load_b32 s4, s[18:19], 0x8
	s_mov_b32 s31, exec_lo
                                        ; implicit-def: $sgpr6
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_i32_e64 s30, s4, v13
	v_cmpx_le_i32_e64 s4, v13
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_load_b32 s4, s[24:25], 0x8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_and_not1_b32 s30, s30, exec_lo
	s_mov_b32 s6, -1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s4, s4, v13
	s_and_b32 s4, s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s30, s30, s4
.LBB0_9:                                ; %Flow266
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s4, s11, exec_lo
	s_and_b32 s11, s30, exec_lo
	s_or_b32 s11, s4, s11
.LBB0_10:                               ; %Flow265
	s_or_b32 exec_lo, exec_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, s11, exec_lo
	s_or_b32 s3, s3, s4
.LBB0_11:                               ; %Flow264
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s2, s2, s3
.LBB0_12:                               ; %Flow263
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, vcc_lo, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 vcc_lo, s3, s2
.LBB0_13:                               ; %Flow262
	s_or_b32 exec_lo, exec_lo, s5
	v_dual_subrev_f32 v6, s26, v2 :: v_dual_subrev_f32 v15, s28, v4
	v_subrev_f32_e32 v14, s27, v3
	s_and_saveexec_b32 s2, vcc_lo
; %bb.14:
	s_and_not1_b32 s6, s6, exec_lo
; %bb.15:
	s_or_b32 exec_lo, exec_lo, s2
	v_frexp_mant_f32_e64 v0, |v6|
	v_cmp_eq_f32_e64 s2, 1.0, v6
	v_frexp_mant_f32_e64 v4, |v14|
	v_frexp_mant_f32_e64 v17, |v15|
	v_frexp_exp_i32_f32_e32 v3, v6
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	v_frexp_exp_i32_f32_e32 v16, v14
	v_frexp_exp_i32_f32_e32 v19, v15
	v_cmp_gt_f32_e64 s3, 0x3f2aaaab, v17
	s_mov_b32 s7, 0x3e76c4e1
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, 0, 1, s3
	v_subrev_co_ci_u32_e64 v19, vcc_lo, 0, v19, s3
	v_ldexp_f32 v1, v0, v1
	v_cndmask_b32_e64 v0, 2.0, 1.0, s2
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v4
	v_ldexp_f32 v17, v17, v22
	v_cvt_f32_i32_e32 v3, v3
	v_add_f32_e32 v2, 1.0, v1
	v_cvt_f32_i32_e32 v19, v19
	v_cndmask_b32_e64 v20, 0, 1, s2
	v_subrev_co_ci_u32_e64 v16, vcc_lo, 0, v16, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v23, -1.0, v2
	v_cmp_class_f32_e64 s10, v6, 0x204
	v_ldexp_f32 v4, v4, v20
	v_add_f32_e32 v21, -1.0, v1
	v_add_f32_e32 v25, 1.0, v17
	v_sub_f32_e32 v1, v1, v23
	v_rcp_f32_e32 v18, v2
	v_add_f32_e32 v22, 1.0, v4
	v_mul_f32_e32 v28, 0x3f317218, v3
	v_rcp_f32_e32 v26, v25
	v_add_f32_e32 v33, -1.0, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_add_f32_e32 v31, -1.0, v22
	v_rcp_f32_e32 v23, v22
	v_mul_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v2, v20
	v_fma_f32 v2, v20, v2, -v24
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v27, -1.0, v4 :: v_dual_fmac_f32 v2, v20, v1
	v_cvt_f32_i32_e32 v1, v16
	v_add_f32_e32 v16, -1.0, v17
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v30, v27, v23 :: v_dual_sub_f32 v17, v17, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v29, v24, v2
	v_mul_f32_e32 v32, v16, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v35, v22, v30 :: v_dual_sub_f32 v4, v4, v31
	v_sub_f32_e32 v34, v21, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v31, v25, v32
	v_fma_f32 v22, v30, v22, -v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v21, v21, v34
	v_fma_f32 v25, v32, v25, -v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v22, v30, v4
	v_sub_f32_e32 v24, v29, v24
	v_sub_f32_e32 v21, v21, v29
	v_mul_f32_e32 v4, 0x3f317218, v1
	v_fmac_f32_e32 v25, v32, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v17, 0x3f317218, v19 :: v_dual_sub_f32 v2, v24, v2
	v_fma_f32 v24, 0x3f317218, v3, -v28
	v_fma_f32 v33, 0x3f317218, v1, -v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v36, 0x3f317218, v19, -v17
	v_dual_add_f32 v2, v2, v21 :: v_dual_add_f32 v21, v35, v22
	v_add_f32_e32 v29, v31, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v33, 0xb102e308, v1 :: v_dual_fmac_f32 v24, 0xb102e308, v3
	v_add_f32_e32 v2, v34, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v34, v27, v21 :: v_dual_sub_f32 v35, v21, v35
	v_dual_sub_f32 v37, v16, v29 :: v_dual_mul_f32 v2, v18, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v18, v27, v34 :: v_dual_sub_f32 v27, v29, v31
	v_sub_f32_e32 v22, v35, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v31, v20, v2 :: v_dual_sub_f32 v18, v18, v21
	v_sub_f32_e32 v16, v16, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v21, v27, v25
	v_dual_sub_f32 v3, v31, v20 :: v_dual_add_f32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v16, v29
	v_add_f32_e32 v20, v28, v24
	v_sub_f32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v3, v34, v18
	v_add_f32_e32 v1, v21, v16
	v_dual_add_f32 v21, v4, v33 :: v_dual_mul_f32 v16, v31, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v36, 0xb102e308, v19 :: v_dual_add_f32 v19, v2, v2
	v_add_f32_e32 v1, v37, v1
	v_mul_f32_e32 v3, v23, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v18, v31, v31, -v16
	v_sub_f32_e32 v22, v20, v28
	v_ldexp_f32 v37, v2, 1
	v_dual_mul_f32 v1, v26, v1 :: v_dual_sub_f32 v4, v21, v4
	v_fmac_f32_e32 v18, v31, v19
	v_add_f32_e32 v19, v30, v3
	v_add_f32_e32 v25, v17, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v23, v32, v1
	v_sub_f32_e32 v22, v24, v22
	v_add_f32_e32 v26, v16, v18
	v_mul_f32_e32 v28, v19, v19
	v_sub_f32_e32 v4, v33, v4
	v_dual_sub_f32 v24, v23, v32 :: v_dual_sub_f32 v17, v25, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v29, s7, v26, 0x3e91f4c4 :: v_dual_sub_f32 v16, v26, v16
	v_mul_f32_e32 v39, v31, v26
	v_sub_f32_e32 v1, v1, v24
	v_sub_f32_e32 v27, v19, v30
	v_fma_f32 v24, v19, v19, -v28
	v_sub_f32_e32 v16, v18, v16
	v_fma_f32 v44, v26, v31, -v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v34, v1, v1 :: v_dual_sub_f32 v3, v3, v27
	v_dual_mul_f32 v27, v23, v23 :: v_dual_fmac_f32 v44, v26, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v30, v3, v3 :: v_dual_fmaak_f32 v29, v26, v29, 0x3ecccdef
	v_fma_f32 v32, v23, v23, -v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v44, v16, v31
	v_dual_fmac_f32 v24, v19, v30 :: v_dual_mul_f32 v35, v26, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v32, v23, v34
	v_ldexp_f32 v30, v31, 1
	v_add_f32_e32 v31, v39, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v18, v26, v29, -v35
	v_add_f32_e32 v38, v27, v32
	v_add_f32_e32 v34, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v18, v16, v29 :: v_dual_fmaak_f32 v41, s7, v38, 0x3e91f4c4
	v_fmaak_f32 v29, s7, v34, 0x3e91f4c4
	v_sub_f32_e32 v27, v38, v27
	v_dual_sub_f32 v28, v34, v28 :: v_dual_mul_f32 v43, v23, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v42, v35, v18 :: v_dual_fmaak_f32 v41, v38, v41, 0x3ecccdef
	v_dual_mul_f32 v40, v19, v34 :: v_dual_fmaak_f32 v29, v34, v29, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v24, v24, v28 :: v_dual_sub_f32 v35, v42, v35
	v_add_f32_e32 v45, 0x3f2aaaaa, v42
	v_fma_f32 v28, v34, v19, -v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v26, v34, v29
	v_dual_sub_f32 v18, v18, v35 :: v_dual_add_f32 v35, 0xbf2aaaaa, v45
	v_sub_f32_e32 v27, v32, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v16, v34, v29, -v26
	v_fma_f32 v32, v38, v23, -v43
	v_add_f32_e32 v2, 0x31739010, v18
	v_sub_f32_e32 v18, v42, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, v24, v29
	v_add_f32_e32 v2, v2, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v45, v2
	v_fmac_f32_e32 v28, v34, v3
	v_ldexp_f32 v3, v3, 1
	v_mul_f32_e32 v29, v31, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v35, v38, v41 :: v_dual_fmac_f32 v28, v24, v19
	v_sub_f32_e32 v24, v45, v18
	v_fma_f32 v34, v38, v41, -v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v34, v27, v41
	v_fmac_f32_e32 v32, v38, v1
	v_ldexp_f32 v1, v1, 1
	v_add_f32_e32 v41, v35, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v27, v23
	v_sub_f32_e32 v27, v31, v39
	v_add_f32_e32 v39, v26, v16
	v_dual_sub_f32 v27, v44, v27 :: v_dual_add_f32 v2, v2, v24
	v_fma_f32 v24, v31, v18, -v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v24, v31, v2 :: v_dual_add_f32 v31, 0x3f2aaaaa, v41
	v_sub_f32_e32 v2, v41, v35
	v_fmac_f32_e32 v24, v27, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v2, v34, v2
	v_add_f32_e32 v34, v43, v32
	v_add_f32_e32 v18, 0xbf2aaaaa, v31
	v_dual_sub_f32 v26, v39, v26 :: v_dual_add_f32 v27, v29, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v2, 0x31739010, v2
	v_add_f32_e32 v38, v40, v28
	v_sub_f32_e32 v18, v41, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v16, v26 :: v_dual_sub_f32 v29, v27, v29
	v_add_f32_e32 v2, v2, v18
	v_add_f32_e32 v42, 0x3f2aaaaa, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v24, v24, v29 :: v_dual_sub_f32 v29, v34, v43
	v_dual_sub_f32 v35, v38, v40 :: v_dual_add_f32 v26, 0xbf2aaaaa, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v24, v37, v24
	v_sub_f32_e32 v28, v28, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v26, v39, v26
	v_add_f32_e32 v39, v31, v2
	v_dual_sub_f32 v31, v31, v39 :: v_dual_add_f32 v16, 0x31739010, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v37, v34, v39 :: v_dual_add_f32 v16, v16, v26
	v_add_f32_e32 v26, v30, v27
	v_add_f32_e32 v18, v42, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v30, v26, v30
	v_sub_f32_e32 v40, v42, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v27, v27, v30
	v_mul_f32_e32 v30, v38, v18
	v_add_f32_e32 v16, v16, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, v24, v27
	v_fma_f32 v27, v38, v18, -v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v27, v38, v16
	v_ldexp_f32 v16, v19, 1
	v_sub_f32_e32 v19, v32, v29
	v_fmac_f32_e32 v27, v28, v18
	v_ldexp_f32 v18, v23, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v30, v27
	v_sub_f32_e32 v30, v23, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v32, v16, v23 :: v_dual_sub_f32 v27, v27, v30
	v_add_f32_e32 v35, v26, v24
	v_dual_sub_f32 v16, v32, v16 :: v_dual_add_f32 v3, v3, v27
	v_add_f32_e32 v2, v2, v31
	v_fma_f32 v31, v34, v39, -v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v26, v35, v26
	v_dual_sub_f32 v16, v23, v16 :: v_dual_fmac_f32 v31, v34, v2
	v_add_f32_e32 v2, v20, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v24, v24, v26 :: v_dual_add_f32 v3, v3, v16
	v_fmac_f32_e32 v31, v19, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v2, v20
	v_add_f32_e32 v30, v22, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v28, v37, v31
	v_sub_f32_e32 v29, v2, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v19, v35, v19 :: v_dual_sub_f32 v26, v28, v37
	v_dual_sub_f32 v20, v20, v29 :: v_dual_add_f32 v29, v18, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v19, v19, v20
	v_sub_f32_e32 v20, v31, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v29, v18
	v_sub_f32_e32 v26, v30, v22
	v_add_f32_e32 v19, v30, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v1, v1, v20 :: v_dual_sub_f32 v18, v28, v18
	v_sub_f32_e32 v23, v30, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v24, v26 :: v_dual_add_f32 v27, v2, v19
	v_dual_add_f32 v1, v1, v18 :: v_dual_sub_f32 v20, v22, v23
	v_add_f32_e32 v18, v32, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v16, v16, v20
	v_add_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v2, v27, v2 :: v_dual_sub_f32 v23, v20, v21
	v_dual_sub_f32 v2, v19, v2 :: v_dual_add_f32 v19, v29, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v16, v2
	v_dual_sub_f32 v16, v36, v17 :: v_dual_sub_f32 v17, v18, v32
	v_sub_f32_e32 v22, v19, v29
	v_add_f32_e32 v26, v25, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v24, v27, v2
	v_dual_sub_f32 v18, v18, v23 :: v_dual_sub_f32 v3, v3, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v1, v1, v22
	v_sub_f32_e32 v17, v20, v23
	v_sub_f32_e32 v22, v24, v27
	v_dual_mul_f32 v27, v0, v24 :: v_dual_sub_f32 v28, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v21, v17 :: v_dual_sub_f32 v2, v2, v22
	v_fma_f32 v21, v0, v24, -v27
	v_add_f32_e32 v22, v4, v3
	v_cmp_class_f32_e64 vcc_lo, v27, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v17, v18, v17 :: v_dual_sub_f32 v18, v19, v28
	v_fmac_f32_e32 v21, v0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v19, v22, v4
	v_sub_f32_e32 v23, v26, v28
	v_add_f32_e32 v17, v22, v17
	v_add_f32_e32 v2, v16, v1
	v_add_f32_e32 v24, v27, v21
	v_sub_f32_e32 v22, v22, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v23, v25, v23 :: v_dual_add_f32 v28, v20, v17
	v_sub_f32_e32 v3, v3, v19
	v_cndmask_b32_e32 v29, v24, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v4, v4, v22 :: v_dual_sub_f32 v25, v2, v16
	v_dual_sub_f32 v19, v28, v20 :: v_dual_add_f32 v18, v18, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v29
	v_dual_add_f32 v3, v3, v4 :: v_dual_sub_f32 v22, v2, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v17, v19
	v_add_f32_e32 v2, v2, v18
	v_cndmask_b32_e64 v20, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v14
	v_sub_f32_e32 v1, v1, v25
	v_dual_add_f32 v3, v3, v4 :: v_dual_sub_f32 v16, v16, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v17, v29, v20 :: v_dual_add_f32 v4, v26, v2
	v_cndmask_b32_e64 v19, 2.0, 1.0, vcc_lo
	v_dual_add_f32 v22, v28, v3 :: v_dual_add_f32 v1, v1, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v18, 0x3fb8aa3b, v17
	v_sub_f32_e32 v16, v4, v26
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v26, v22, v28
	v_mul_f32_e32 v28, v19, v22
	v_rndne_f32_e32 v25, v18
	v_fma_f32 v23, 0x3fb8aa3b, v17, -v18
	v_dual_sub_f32 v2, v2, v16 :: v_dual_sub_f32 v3, v3, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v18, v25
	v_fma_f32 v18, v19, v22, -v28
	v_fmac_f32_e32 v23, 0x32a5705f, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v1, v1, v2 :: v_dual_fmac_f32 v18, v19, v3
	v_add_f32_e32 v2, v16, v23
	v_cndmask_b32_e64 v16, 2.0, 1.0, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v28, 0x204
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v3, v4, v1
	v_add_f32_e32 v22, v28, v18
	v_sub_f32_e32 v23, v24, v27
	v_cvt_i32_f32_e32 v24, v25
	v_exp_f32_e32 v2, v2
	v_sub_f32_e32 v4, v3, v4
	v_dual_cndmask_b32 v25, v22, v28 :: v_dual_mul_f32 v26, v16, v3
	v_sub_f32_e32 v22, v22, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v1, v4
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v25
	v_sub_f32_e32 v4, v21, v23
	v_fma_f32 v3, v16, v3, -v26
	s_delay_alu instid0(TRANS32_DEP_1)
	v_ldexp_f32 v2, v2, v24
	v_trunc_f32_e32 v24, v0
	v_cndmask_b32_e64 v21, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v29|
	v_fmac_f32_e32 v3, v16, v1
	v_cmp_class_f32_e64 s3, v26, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v18, v18, v22 :: v_dual_sub_f32 v23, v25, v21
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v17
	v_add_f32_e32 v4, v20, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v17
	v_dual_mul_f32 v17, 0.5, v0 :: v_dual_mul_f32 v20, 0x3fb8aa3b, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v24, v0
	v_add_f32_e32 v0, v26, v3
	v_fma_f32 v27, 0x3fb8aa3b, v23, -v20
	v_rndne_f32_e32 v29, v20
	v_fma_f32 v1, v2, v4, v2
	v_trunc_f32_e32 v4, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, 0x32a5705f, v23
	v_cmp_neq_f32_e64 s2, v4, v17
	v_cndmask_b32_e64 v17, v0, v26, s3
	v_cmp_eq_f32_e64 s3, 0x7f800000, v2
	v_sub_f32_e32 v4, v20, v29
	v_sub_f32_e32 v0, v0, v26
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s3
	v_cmp_eq_f32_e64 s3, 0x42b17218, v17
	v_cndmask_b32_e64 v2, 1.0, v6, s2
	v_add_f32_e32 v4, v4, v27
	v_cvt_i32_f32_e32 v27, v29
	v_sub_f32_e32 v0, v3, v0
	v_cndmask_b32_e64 v20, 0, 0x37000000, s3
	v_bfi_b32 v1, 0x7fffffff, v1, v2
	v_exp_f32_e32 v2, v4
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v25|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v4, v17, v20
	v_cndmask_b32_e32 v24, 0x7fc00000, v1, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(TRANS32_DEP_1)
	v_cndmask_b32_e64 v18, 0, v18, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v23
	v_mul_f32_e32 v28, 0x3fb8aa3b, v4
	v_cmp_nlt_f32_e64 s4, 0x42b17218, v4
	v_ldexp_f32 v2, v2, v27
	v_add_f32_e32 v18, v21, v18
	v_cndmask_b32_e64 v29, 0x7f800000, 0, vcc_lo
	v_fma_f32 v22, 0x3fb8aa3b, v4, -v28
	v_rndne_f32_e32 v27, v28
	v_cndmask_b32_e64 v2, 0, v2, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v17|
	v_mul_f32_e32 v17, 0.5, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_fmac_f32 v22, 0x32a5705f, v4 :: v_dual_sub_f32 v25, v28, v27
	v_cndmask_b32_e64 v28, 0, v6, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v23
	v_trunc_f32_e32 v23, v19
	v_cndmask_b32_e64 v0, 0, v0, s3
	v_add_f32_e32 v21, v25, v22
	v_cvt_i32_f32_e32 v25, v27
	v_cndmask_b32_e64 v2, 0x7f800000, v2, s2
	v_cmp_gt_f32_e64 s2, 0, v6
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v4
	v_exp_f32_e32 v21, v21
	v_bfi_b32 v22, 0x7fffffff, v29, v28
	v_fma_f32 v18, v2, v18, v2
	v_cndmask_b32_e64 v1, v1, v24, s2
	v_mul_f32_e32 v24, 0.5, v19
	v_cmp_eq_f32_e64 s2, 0x7f800000, v2
	v_add_f32_e32 v0, v20, v0
	v_trunc_f32_e32 v4, v16
	s_or_b32 vcc_lo, vcc_lo, s10
	s_load_b32 s10, s[0:1], 0x50
	v_cndmask_b32_e64 v2, v18, v2, s2
	v_ldexp_f32 v3, v21, v25
	v_trunc_f32_e32 v18, v24
	v_cmp_eq_f32_e64 s2, v23, v19
	v_cndmask_b32_e32 v1, v1, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, 0, v3, s3
	v_cmp_neq_f32_e64 s3, v18, v24
	v_trunc_f32_e32 v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 0x7f800000, v3, s4
	s_and_b32 s3, s2, s3
	v_cmp_eq_f32_e64 s4, v4, v16
	v_cndmask_b32_e64 v19, 1.0, v14, s3
	v_cmp_neq_f32_e64 s5, v18, v17
	v_fma_f32 v0, v3, v0, v3
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v3
	v_cndmask_b32_e64 v17, 0, v14, s3
	v_bfi_b32 v2, 0x7fffffff, v2, v19
	v_cmp_gt_f32_e64 s3, 0, v14
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_and_b32 vcc_lo, s4, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, 0x7fc00000, v2, s2
	v_cmp_eq_f32_e64 s2, 0, v14
	v_cndmask_b32_e32 v3, 1.0, v15, vcc_lo
	v_cmp_class_f32_e64 s5, v14, 0x204
	v_cndmask_b32_e64 v2, v2, v4, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0x7f800000, 0, s2
	v_bfi_b32 v0, 0x7fffffff, v0, v3
	v_cmp_eq_f32_e64 s3, 0, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_bfi_b32 v3, 0x7fffffff, v16, v17
	v_cndmask_b32_e32 v17, 0, v15, vcc_lo
	s_or_b32 vcc_lo, s2, s5
	v_cndmask_b32_e64 v4, 0x7fc00000, v0, s4
	v_cndmask_b32_e64 v16, 0x7f800000, 0, s3
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v15
	v_cmp_class_f32_e64 s2, v15, 0x204
	s_delay_alu instid0(VALU_DEP_4)
	v_bfi_b32 v3, 0x7fffffff, v16, v17
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v6, v6
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v14, v14
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
	s_or_b32 vcc_lo, s3, s2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v1, v2 :: v_dual_cndmask_b32 v0, 0x7fc00000, v0
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v1, |v0|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, v2
	v_add_f32_e32 v2, 1.0, v1
	v_add_f32_e32 v4, -1.0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	v_add_f32_e32 v17, -1.0, v2
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v1, v1, v17 :: v_dual_mul_f32 v16, v4, v3
	v_mul_f32_e32 v18, v2, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v16, v2, -v18
	v_fmac_f32_e32 v2, v16, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v18, v2
	v_dual_sub_f32 v17, v4, v1 :: v_dual_sub_f32 v18, v1, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v17
	v_dual_sub_f32 v2, v18, v2 :: v_dual_sub_f32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v2, v1
	v_add_f32_e32 v1, v17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v3, v1
	v_add_f32_e32 v2, v16, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v2, v16
	v_dual_mul_f32 v4, v2, v2 :: v_dual_sub_f32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v2, v2, -v4
	v_add_f32_e32 v16, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v2, v16
	v_add_f32_e32 v16, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v17, s7, v16, 0x3e91f4c4
	v_sub_f32_e32 v4, v16, v4
	v_dual_mul_f32 v20, v2, v16 :: v_dual_fmaak_f32 v17, v16, v17, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v4
	v_fma_f32 v21, v16, v2, -v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v16, v17
	v_fmac_f32_e32 v21, v16, v1
	v_ldexp_f32 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v4, v16, v17, -v18
	v_fmac_f32_e32 v21, v3, v2
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v3, v17
	v_dual_add_f32 v16, v20, v21 :: v_dual_add_f32 v17, v18, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v18, v17, v18 :: v_dual_add_f32 v19, 0x3f2aaaaa, v17
	v_sub_f32_e32 v4, v4, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, 0xbf2aaaaa, v19
	v_dual_add_f32 v4, 0x31739010, v4 :: v_dual_sub_f32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v17
	v_add_f32_e32 v3, v19, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v19, v3
	v_mul_f32_e32 v18, v16, v3
	v_sub_f32_e32 v19, v16, v20
	v_add_f32_e32 v4, v4, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, v16, v3, -v18
	v_sub_f32_e32 v19, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v16, v4
	v_frexp_exp_i32_f32_e32 v4, v0
	v_fmac_f32_e32 v17, v19, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_add_f32_e32 v4, v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_add_f32_e32 v16, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v18, v4, v18 :: v_dual_mul_f32 v19, 0x3f317218, v3
	v_sub_f32_e32 v2, v16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v17, v18
	v_fma_f32 v18, 0x3f317218, v3, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v2, v4, v2 :: v_dual_add_f32 v1, v1, v17
	v_dual_fmac_f32 v18, 0xb102e308, v3 :: v_dual_add_f32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v19, v18 :: v_dual_add_f32 v3, v16, v1
	v_sub_f32_e32 v19, v2, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v2, v3
	v_sub_f32_e32 v16, v3, v16
	v_dual_sub_f32 v18, v18, v19 :: v_dual_sub_f32 v17, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v1, v1, v16 :: v_dual_sub_f32 v20, v4, v17
	v_sub_f32_e32 v3, v3, v17
	v_add_f32_e32 v16, v18, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v20
	v_add_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v16, v18
	v_add_f32_e32 v2, v16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v16, v3
	v_sub_f32_e32 v1, v1, v3
	v_add_f32_e32 v17, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v18, v16
	v_sub_f32_e32 v4, v17, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v1, v3
	v_cndmask_b32_e64 v3, 0.5, 1.0, vcc_lo
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v2, v17
	v_dual_mul_f32 v16, v3, v2 :: v_dual_sub_f32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v3, v2, -v16
	v_cmp_class_f32_e64 vcc_lo, v16, 0x204
	v_fmac_f32_e32 v2, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v16, v2
	v_cndmask_b32_e32 v4, v1, v16, vcc_lo
	v_sub_f32_e32 v1, v1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_sub_f32_e32 v1, v2, v1
	v_cmp_eq_f32_e64 s0, 0, v0
	v_cmp_class_f32_e64 s1, v0, 0x204
	v_cndmask_b32_e64 v17, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v4, v17
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_trunc_f32_e32 v4, v3
	v_mul_f32_e32 v19, 0x3fb8aa3b, v18
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v17, v1
	v_fma_f32 v20, 0x3fb8aa3b, v18, -v19
	v_rndne_f32_e32 v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, 0x32a5705f, v18 :: v_dual_sub_f32 v19, v19, v21
	v_cvt_i32_f32_e32 v16, v21
	v_add_f32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v19, v19
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v19, v16
	v_mul_f32_e32 v16, 0.5, v3
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v19, v16
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s2, v19, v16
	v_fma_f32 v1, v2, v1, v2
	v_cmp_eq_f32_e64 s3, 0x7f800000, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	v_cndmask_b32_e64 v3, 1.0, v0, s2
	v_cndmask_b32_e64 v4, 0, v0, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v1, v2, s3
	v_cndmask_b32_e64 v2, 0x7f800000, 0, s0
	v_bfi_b32 v1, 0x7fffffff, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v2, 0x7fffffff, v2, v4
	v_cndmask_b32_e32 v3, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_or_b32 vcc_lo, s0, s1
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v20, 0x7fc00000, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_nlt_f32_e64 |v20|, s10
	s_xor_b32 s7, exec_lo, s1
	s_cbranch_execz .LBB0_41
; %bb.16:                               ; %.preheader149.preheader
	s_mov_b64 s[4:5], 0
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2
                                        ; implicit-def: $vgpr2_vgpr3_vgpr4
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr2_vgpr3_vgpr4
.LBB0_17:                               ; %.preheader149
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 1
	s_mov_b32 s0, exec_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 2
	v_cndmask_b32_e32 v21, v6, v14, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v21, v21, v15, vcc_lo
	v_div_scale_f32 v22, null, v20, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	v_div_scale_f32 v24, vcc_lo, v21, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, v24, v23
	v_fma_f32 v26, -v22, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v26, v23
	v_fma_f32 v22, -v22, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v22, v22, v23, v25
	v_div_fixup_f32 v21, v22, v20, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f32_e32 0, v21
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_21
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_f32_e32 0, v21
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	s_cmp_lg_u32 s4, 2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s4, 1
	v_cndmask_b32_e32 v2, -1, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s4, 0
	v_cndmask_b32_e32 v1, -1, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v0, -1, v0, vcc_lo
; %bb.20:                               ; %Flow251
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_21:                               ; %Flow253
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_and_not1_saveexec_b32 s0, s0
; %bb.22:                               ;   in Loop: Header=BB0_17 Depth=1
	s_cmp_lg_u32 s4, 2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s4, 1
	v_cndmask_b32_e32 v2, 1, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s4, 0
	v_cndmask_b32_e32 v1, 1, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v0, 1, v0, vcc_lo
; %bb.23:                               ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_eq_u32 s4, 0
	s_load_b32 s3, s[12:13], 0x0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s4, 1
	v_cndmask_b32_e64 v6, v6, v21, s0
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s4, 2
	v_cndmask_b32_e64 v22, v0, v1, s1
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e64 v14, v14, v21, s1
	v_cndmask_b32_e64 v15, v15, v21, s2
	s_add_u32 s4, s4, 1
	v_cndmask_b32_e64 v22, v22, v2, s2
	s_addc_u32 s5, s5, 0
	s_add_u32 s12, s12, 4
	s_addc_u32 s13, s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v22, v22
	v_mul_f32_e32 v24, s10, v22
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[22:23], s3
	s_load_b32 s3, s[8:9], 0x0
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	v_cvt_f64_f32_e32 v[24:25], v24
	s_cmp_eq_u32 s4, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[24:25], 0.5, v[22:23]
	v_cvt_f32_f64_e32 v22, v[22:23]
	v_and_b32_e32 v23, 0x7fffffff, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v25, null, v23, v23, s10
	v_rcp_f32_e32 v27, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v27, 1.0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v27, v29, v27 :: v_dual_subrev_f32 v22, s3, v22
	v_div_scale_f32 v23, s3, s10, v23, s10
	v_div_scale_f32 v24, null, v21, v21, v22
	v_div_scale_f32 v30, vcc_lo, v22, v21, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v29, v23, v27
	v_rcp_f32_e32 v26, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v32, -v25, v29, v23
	v_fmac_f32_e32 v29, v32, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v24, v26, 1.0
	v_fma_f32 v23, -v25, v29, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v26, v28, v26
	v_mul_f32_e32 v28, v30, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v24, v28, v30
	v_fmac_f32_e32 v28, v31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v24, v28, v30
	v_div_fmas_f32 v24, v24, v26, v28
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v23, v23, v27, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v22, v24, v21, v22
	v_div_fixup_f32 v21, v23, |v21|, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v22, s2
	v_cndmask_b32_e64 v3, v3, v22, s1
	v_cndmask_b32_e64 v16, v16, v22, s0
	v_cndmask_b32_e64 v19, v19, v21, s2
	v_cndmask_b32_e64 v18, v18, v21, s1
	v_cndmask_b32_e64 v17, v17, v21, s0
	s_cbranch_scc0 .LBB0_17
; %bb.24:                               ; %.preheader
	v_mul_lo_u32 v14, v5, s23
	v_mul_lo_u32 v15, v7, s23
	v_mul_lo_u32 v10, v10, s23
	v_dual_mov_b32 v5, s20 :: v_dual_mov_b32 v6, s21
	v_dual_mov_b32 v7, s22 :: v_dual_mov_b32 v20, 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB0_25:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v22, v20, s[18:19]
	v_cmp_lt_f32_e64 s0, |v3|, |v16|
	v_cmp_lt_f32_e64 s1, |v3|, |v4|
	v_cmp_lt_f32_e64 s2, |v16|, |v3|
	v_cmp_lt_f32_e64 s3, |v16|, |v4|
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	v_cndmask_b32_e64 v21, 2, 1, s0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v21, v21, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cmp_eq_u32_e64 s0, 2, v21
	v_cmp_eq_u32_e64 s1, 0, v21
	v_dual_cndmask_b32 v23, v5, v6 :: v_dual_cndmask_b32 v24, v0, v1
	v_cndmask_b32_e64 v23, v23, v7, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, v24, v2, s0
	v_add_nc_u32_e32 v23, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v5, v23, s1
	v_cndmask_b32_e64 v7, v7, v23, s0
	v_cndmask_b32_e32 v6, v6, v23, vcc_lo
                                        ; implicit-def: $sgpr1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s8, v5, v22
	v_cmpx_ge_i32_e64 v5, v22
	s_cbranch_execz .LBB0_35
; %bb.26:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_b32 v22, v20, s[24:25]
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $sgpr1
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v5, v22
	v_cmpx_le_i32_e64 v5, v22
	s_cbranch_execz .LBB0_34
; %bb.27:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_b32 v22, v20, s[18:19] offset:4
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $sgpr2
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s0, v6, v22
	v_cmpx_ge_i32_e64 v6, v22
	s_cbranch_execz .LBB0_33
; %bb.28:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_b32 v22, v20, s[24:25] offset:4
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $sgpr2
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e64 s12, v6, v22
	v_cmpx_le_i32_e64 v6, v22
	s_cbranch_execz .LBB0_32
; %bb.29:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_b32 v22, v20, s[18:19] offset:8
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $sgpr2
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s20, v7, v22
	v_cmpx_ge_i32_e64 v7, v22
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_25 Depth=1
	global_load_b32 v22, v20, s[24:25] offset:8
	v_cmp_eq_u32_e64 s1, v5, v11
	v_cmp_eq_u32_e64 s2, v6, v12
	v_cmp_eq_u32_e64 s3, v7, v13
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s22, s6, s1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s22, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_not1_b32 s3, s20, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e64 s1, v7, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s20, s3, s1
.LBB0_31:                               ; %Flow250
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s12, exec_lo
	s_and_b32 s3, s20, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s12, s1, s3
.LBB0_32:                               ; %Flow249
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s1, s12, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s0, s0, s1
.LBB0_33:                               ; %Flow248
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, vcc_lo, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_and_b32 s1, s2, exec_lo
	s_or_b32 vcc_lo, s3, s0
.LBB0_34:                               ; %Flow247
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s0, s8, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s8, s0, s2
.LBB0_35:                               ; %Flow
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s0, s8
; %bb.36:                               ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 s1, s1, exec_lo
; %bb.37:                               ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_xor_b32 s2, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_25 Depth=1
	v_add_nc_u32_e32 v22, s5, v14
	v_add_nc_u32_e32 v24, s5, v15
	v_add_nc_u32_e32 v26, s5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v23, 31, v22
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v27, 31, v26
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, s14, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s15, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v24, vcc_lo, s14, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s15, v25, vcc_lo
	v_add_co_u32 v26, vcc_lo, s14, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s15, v27, vcc_lo
	s_clause 0x2
	global_store_b32 v[22:23], v5, off
	global_store_b32 v[24:25], v6, off
	global_store_b32 v[26:27], v7, off
.LBB0_39:                               ;   in Loop: Header=BB0_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cmp_eq_u32_e64 s0, 2, v21
	s_and_b32 s1, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 s4, s1, s4
	v_dual_cndmask_b32 v22, v16, v3 :: v_dual_cndmask_b32 v23, v17, v18
	s_add_i32 s5, s5, 1
	v_cndmask_b32_e64 v22, v22, v4, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, v23, v19, s0
	v_add_f32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_mov_b32_e32 v21, s5
	v_cndmask_b32_e64 v4, v4, v22, s0
	v_cndmask_b32_e32 v16, v16, v22, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_25
; %bb.40:
	s_or_b32 exec_lo, exec_lo, s4
	v_add_co_u32 v0, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v9, vcc_lo
	global_store_b32 v[0:1], v21, off
.LBB0_41:                               ; %Flow255
	s_and_not1_saveexec_b32 s0, s7
	s_cbranch_execz .LBB0_43
; %bb.42:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_error@rel32@lo+4
	s_addc_u32 s1, s1, d_error@rel32@hi+12
	global_store_b8 v0, v1, s[0:1]
.LBB0_43:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f, .Lfunc_end0-_Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6304
; NumSgprs: 34
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_error                 ; @d_error
	.type	d_error,@object
	.section	.bss,"aw",@nobits
	.globl	d_error
d_error:
	.byte	0                               ; 0x0
	.size	d_error, 1

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_error
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z3crsPfPiiiS_S0_S_S0_S0_S0_S0_f.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
