#include <stdio.h>
#include <cuda_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }


inline void gpuAssert(cudaError_t code, const char *file, int line,
		      bool abort = true)
{
    if (code != cudaSuccess) {
	fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
		file, line);
	if (abort)
	    exit(code);
    }
}


__global__ void kernel(int reads, size_t size,
		       volatile uint64_t * first, float *dsum)
{

    int blockId = blockIdx.x + blockIdx.y * gridDim.x;

    int threadId = blockId * (blockDim.x * blockDim.y)
	+ (threadIdx.y * blockDim.x) + threadIdx.x;

    int local_sum = 0;

    printf(" I am %d\n", threadId);

    while (reads--) {
	local_sum = first[0] + 666;
    }
	
   *dsum = local_sum;

}



int main(int argc, char **argv)
{

    int opt, BLOCKS = 1, THREADS = 1, reads = 1, size = 1;

    cudaEvent_t start, stop;
    float elapsed_time;

    while ((opt = getopt(argc, argv, "b:t:r:s:")) != -1) {

		switch (opt) {

			case 'b':
			    BLOCKS = atoi(optarg);
			    break;
			case 't':
			    THREADS = atoi(optarg);
			    break;
			case 'r':
			    reads = atoi(optarg);
			    break;
			case 's':
			    size = atoi(optarg);
			    break;
			default:
			    fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -r [reads] -s [size]\n",
				    argv[0]);
			    exit(EXIT_FAILURE);
		}
    }

    volatile uint64_t *h_mem;

    volatile uint64_t *d_mem;

    float *dsum;

    size_t h_mem_size = size * sizeof(uint64_t);

    gpuErrchk(cudaEventCreate(&start));

    gpuErrchk(cudaEventCreate(&stop));

    gpuErrchk(cudaHostAlloc
	      ((void **) &h_mem, (size_t) h_mem_size, cudaHostAllocMapped));

    gpuErrchk(cudaMallocManaged((void **) &dsum, sizeof(float)));

    memset((void *)h_mem, 1, h_mem_size);


    gpuErrchk(cudaHostGetDevicePointer
	      ((void **) &d_mem, (void *) h_mem, 0));

    *dsum = 0;

    gpuErrchk(cudaEventRecord(start, 0));

    kernel <<< BLOCKS, THREADS >>> (reads, size, d_mem, dsum);

    gpuErrchk(cudaDeviceSynchronize());

    assert(*dsum != 0);

    gpuErrchk(cudaEventRecord(stop, 0));

    gpuErrchk(cudaEventSynchronize(stop));

    gpuErrchk(cudaEventElapsedTime(&elapsed_time, start, stop));

    printf("\n\tElapsed time : %f ms \n\n", elapsed_time);

    return 0;
}

	.file	"tmpxft_002e49d4_00000000-6_load_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3407:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3407:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3403:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3403:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z30__device_stub__Z6kernelimPVmPfimPVmPf
	.type	_Z30__device_stub__Z6kernelimPVmPfimPVmPf, @function
_Z30__device_stub__Z6kernelimPVmPfimPVmPf:
.LFB3429:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6kernelimPVmPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3429:
	.size	_Z30__device_stub__Z6kernelimPVmPfimPVmPf, .-_Z30__device_stub__Z6kernelimPVmPfimPVmPf
	.globl	_Z6kernelimPVmPf
	.type	_Z6kernelimPVmPf, @function
_Z6kernelimPVmPf:
.LFB3430:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6kernelimPVmPfimPVmPf
	.cfi_endproc
.LFE3430:
	.size	_Z6kernelimPVmPf, .-_Z6kernelimPVmPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Usage: %s -b [blocks] -t [threads] -r [reads] -s [size]\n"
.LC2:
	.string	"b:t:r:s:"
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/gganagno/GHammer/master/3_device_memory/cache_operator_tests/ptx_enforce/load_test/load_test.cu"
.LC5:
	.string	"\n\tElapsed time : %f ms \n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3404:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC2(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$1, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$1, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	$1, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$1, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
.L18:
	movl	12(%rsp), %edi
	movq	%r15, %rdx
	movq	%r14, %rsi
	call	getopt@PLT
	cmpl	$-1, %eax
	je	.L30
	cmpl	$115, %eax
	je	.L19
	jg	.L20
	cmpl	$98, %eax
	je	.L21
	cmpl	$114, %eax
	jne	.L23
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
	jmp	.L18
.L20:
	cmpl	$116, %eax
	jne	.L23
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %r13d
	jmp	.L18
.L21:
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %r12d
	jmp	.L18
.L19:
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movslq	%eax, %rbx
	jmp	.L18
.L23:
	movq	stderr(%rip), %rdi
	movq	(%r14), %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rdx
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L30:
	leaq	24(%rsp), %rdi
	leaq	.LC3(%rip), %r14
	call	cudaEventCreate@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$101, %edx
	movl	%eax, %edi
	leaq	0(,%rbx,8), %r15
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$1, %ecx
	movl	$103, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	40(%rsp), %rdi
	movl	$2, %edx
	movq	%r15, %rsi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$105, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	56(%rsp), %rdi
	movl	$1, %edx
	movl	$4, %esi
	call	cudaMallocManaged@PLT
	movl	$1, %ecx
	movl	$108, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	40(%rsp), %rdi
	movb	$1, %al
	movq	%r15, %rcx
	xorl	%edx, %edx
	rep stosb
	leaq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	call	cudaHostGetDevicePointer@PLT
	movl	$1, %ecx
	movl	$113, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	56(%rsp), %rax
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movl	$0x00000000, (%rax)
	call	cudaEventRecord@PLT
	movl	$1, %ecx
	movl	$118, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	%r13d, 76(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	%r12d, 64(%rsp)
	movq	%rax, 80(%rsp)
	movl	84(%rsp), %ecx
	movq	%rax, 68(%rsp)
	movq	76(%rsp), %rdx
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	%rbx, %rsi
	movl	%ebp, %edi
	call	_Z30__device_stub__Z6kernelimPVmPfimPVmPf
.L27:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$122, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$1, %ecx
	movl	$126, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	$1, %ecx
	movl	$128, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	76(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	%r14, %rsi
	movl	$1, %ecx
	movl	$130, %edx
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	76(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3404:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z6kernelimPVmPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3432:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelimPVmPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3432:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }


inline void gpuAssert(hipError_t code, const char *file, int line,
		      bool abort = true)
{
    if (code != hipSuccess) {
	fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code),
		file, line);
	if (abort)
	    exit(code);
    }
}


__global__ void kernel(int reads, size_t size,
		       volatile uint64_t * first, float *dsum)
{

    int blockId = blockIdx.x + blockIdx.y * gridDim.x;

    int threadId = blockId * (blockDim.x * blockDim.y)
	+ (threadIdx.y * blockDim.x) + threadIdx.x;

    int local_sum = 0;

    printf(" I am %d\n", threadId);

    while (reads--) {
	local_sum = first[0] + 666;
    }
	
   *dsum = local_sum;

}



int main(int argc, char **argv)
{

    int opt, BLOCKS = 1, THREADS = 1, reads = 1, size = 1;

    hipEvent_t start, stop;
    float elapsed_time;

    while ((opt = getopt(argc, argv, "b:t:r:s:")) != -1) {

		switch (opt) {

			case 'b':
			    BLOCKS = atoi(optarg);
			    break;
			case 't':
			    THREADS = atoi(optarg);
			    break;
			case 'r':
			    reads = atoi(optarg);
			    break;
			case 's':
			    size = atoi(optarg);
			    break;
			default:
			    fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -r [reads] -s [size]\n",
				    argv[0]);
			    exit(EXIT_FAILURE);
		}
    }

    volatile uint64_t *h_mem;

    volatile uint64_t *d_mem;

    float *dsum;

    size_t h_mem_size = size * sizeof(uint64_t);

    gpuErrchk(hipEventCreate(&start));

    gpuErrchk(hipEventCreate(&stop));

    gpuErrchk(hipHostAlloc
	      ((void **) &h_mem, (size_t) h_mem_size, hipHostMallocMapped));

    gpuErrchk(hipMallocManaged((void **) &dsum, sizeof(float)));

    memset((void *)h_mem, 1, h_mem_size);


    gpuErrchk(hipHostGetDevicePointer
	      ((void **) &d_mem, (void *) h_mem, 0));

    *dsum = 0;

    gpuErrchk(hipEventRecord(start, 0));

    kernel <<< BLOCKS, THREADS >>> (reads, size, d_mem, dsum);

    gpuErrchk(hipDeviceSynchronize());

    assert(*dsum != 0);

    gpuErrchk(hipEventRecord(stop, 0));

    gpuErrchk(hipEventSynchronize(stop));

    gpuErrchk(hipEventElapsedTime(&elapsed_time, start, stop));

    printf("\n\tElapsed time : %f ms \n\n", elapsed_time);

    return 0;
}

	.text
	.file	"load_test.hip"
	.globl	_Z21__device_stub__kernelimPVmPf # -- Begin function _Z21__device_stub__kernelimPVmPf
	.type	_Z21__device_stub__kernelimPVmPf,@function
_Z21__device_stub__kernelimPVmPf:       # @_Z21__device_stub__kernelimPVmPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelimPVmPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelimPVmPf, .Lfunc_end0-_Z21__device_stub__kernelimPVmPf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r12
	movl	%edi, %r13d
	movl	$1, %r15d
	movl	$1, %ebx
	movl	$1, %ebp
	movl	$1, %r14d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edx
	movl	%r13d, %edi
	movq	%r12, %rsi
	callq	getopt
	cmpl	$98, %eax
	jne	.LBB1_2
# %bb.37:                               #   in Loop: Header=BB1_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %r14d
	jmp	.LBB1_1
.LBB1_2:                                #   in Loop: Header=BB1_1 Depth=1
	cmpl	$114, %eax
	jg	.LBB1_6
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	cmpl	$-1, %eax
	je	.LBB1_11
# %bb.4:                                #   in Loop: Header=BB1_1 Depth=1
	cmpl	$114, %eax
	jne	.LBB1_10
# %bb.5:                                #   in Loop: Header=BB1_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %ebx
	jmp	.LBB1_1
.LBB1_6:                                #   in Loop: Header=BB1_1 Depth=1
	cmpl	$115, %eax
	je	.LBB1_9
# %bb.7:                                #   in Loop: Header=BB1_1 Depth=1
	cmpl	$116, %eax
	jne	.LBB1_10
# %bb.8:                                #   in Loop: Header=BB1_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %ebp
	jmp	.LBB1_1
.LBB1_9:                                #   in Loop: Header=BB1_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %r15d
	jmp	.LBB1_1
.LBB1_11:
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKcib.exit
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.16:                               # %_Z9gpuAssert10hipError_tPKcib.exit21
	movslq	%r15d, %r15
	leaq	(,%r15,8), %r12
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	movl	$2, %edx
	callq	hipHostAlloc
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.19:                               # %_Z9gpuAssert10hipError_tPKcib.exit23
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_20
# %bb.21:                               # %_Z9gpuAssert10hipError_tPKcib.exit25
	movq	32(%rsp), %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	callq	memset@PLT
	movq	32(%rsp), %rsi
	leaq	48(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostGetDevicePointer
	testl	%eax, %eax
	jne	.LBB1_22
# %bb.23:                               # %_Z9gpuAssert10hipError_tPKcib.exit27
	movq	24(%rsp), %rax
	movl	$0, (%rax)
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB1_24
# %bb.25:                               # %_Z9gpuAssert10hipError_tPKcib.exit29
	movl	%r14d, %edi
	btsq	$32, %rdi
	movl	%ebp, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_27
# %bb.26:
	movq	48(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	%ebx, %edi
	movq	%r15, %rsi
	callq	_Z21__device_stub__kernelimPVmPf
.LBB1_27:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_28
# %bb.30:                               # %_Z9gpuAssert10hipError_tPKcib.exit31
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB1_31
# %bb.32:                               # %_Z9gpuAssert10hipError_tPKcib.exit33
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	testl	%eax, %eax
	jne	.LBB1_33
# %bb.34:                               # %_Z9gpuAssert10hipError_tPKcib.exit35
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	20(%rsp), %rdi
	callq	hipEventElapsedTime
	testl	%eax, %eax
	jne	.LBB1_35
# %bb.36:                               # %_Z9gpuAssert10hipError_tPKcib.exit37
	cvtss2sd	20(%rsp), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_10:
	.cfi_def_cfa_offset 112
	movq	stderr(%rip), %rdi
	movq	(%r12), %rdx
	movl	$.L.str.1, %esi
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.LBB1_12:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$101, %r8d
	jmp	.LBB1_13
.LBB1_15:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$103, %r8d
	jmp	.LBB1_13
.LBB1_17:
	movl	%eax, %r13d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$106, %r8d
	jmp	.LBB1_18
.LBB1_20:
	movl	%eax, %r13d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$108, %r8d
.LBB1_18:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r13d, %edi
	callq	exit
.LBB1_22:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$114, %r8d
	jmp	.LBB1_13
.LBB1_24:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$118, %r8d
.LBB1_13:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r12d, %edi
	callq	exit
.LBB1_28:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$122, %r8d
	jmp	.LBB1_29
.LBB1_31:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$126, %r8d
	jmp	.LBB1_29
.LBB1_33:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$128, %r8d
	jmp	.LBB1_29
.LBB1_35:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str.2, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$130, %r8d
.LBB1_29:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelimPVmPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelimPVmPf,@object        # @_Z6kernelimPVmPf
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelimPVmPf
	.p2align	3, 0x0
_Z6kernelimPVmPf:
	.quad	_Z21__device_stub__kernelimPVmPf
	.size	_Z6kernelimPVmPf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"b:t:r:s:"
	.size	.L.str, 9

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Usage: %s -b [blocks] -t [threads] -r [reads] -s [size]\n"
	.size	.L.str.1, 57

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/gganagno/GHammer/master/3_device_memory/cache_operator_tests/ptx_enforce/load_test/load_test.hip"
	.size	.L.str.2, 159

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\n\tElapsed time : %f ms \n\n"
	.size	.L.str.3, 26

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.4, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelimPVmPf"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelimPVmPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelimPVmPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelimPVmPf        ; -- Begin function _Z6kernelimPVmPf
	.globl	_Z6kernelimPVmPf
	.p2align	8
	.type	_Z6kernelimPVmPf,@function
_Z6kernelimPVmPf:                       ; @_Z6kernelimPVmPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s19, s[0:1], 0x20
	s_load_b32 s18, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x70
	v_mbcnt_lo_u32_b32 v29, -1, 0
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v29
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v5
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v1, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[4:5] offset:40
	global_load_b64 v[6:7], v1, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v3, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[7:8], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[9:10]
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB0_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[4:5] offset:40
	global_load_b64 v[11:12], v1, s[4:5]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v8, v3, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
	v_mov_b32_e32 v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
	v_mov_b32_e32 v7, v3
	global_load_b64 v[7:8], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %Flow344
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:                                ; %Flow346
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[9:10], v6, s[4:5] offset:40
	global_load_b128 v[1:4], v6, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v9
	v_readfirstlane_b32 s9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, v6
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v1, s11
	v_add_co_ci_u32_e32 v12, vcc_lo, s12, v2, vcc_lo
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, v7
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
	v_dual_mov_b32 v5, 33 :: v_dual_mov_b32 v8, v6
	v_mov_b32_e32 v7, v6
	v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v14, s23
	v_dual_mov_b32 v12, s21 :: v_dual_mov_b32 v13, s22
	s_clause 0x3
	global_store_b128 v[9:10], v[5:8], off
	global_store_b128 v[9:10], v[11:14], off offset:16
	global_store_b128 v[9:10], v[11:14], off offset:32
	global_store_b128 v[9:10], v[11:14], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_16
; %bb.9:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s9, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v11, s[4:5] offset:40
	v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s7, v4
	v_and_b32_e32 v3, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v5, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_add_co_u32 v7, vcc_lo, v1, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB0_12
; %bb.10:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s12, 0
.LBB0_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_11
.LBB0_12:                               ; %Flow342
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v6, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v5, s12, 0
	global_load_b64 v[3:4], v6, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_16
; %bb.15:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:                               ; %Flow343
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v1, vcc_lo, v1, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s10, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_19:                               ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s3, -1
.LBB0_22:                               ; %Flow337
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_17
; %bb.23:
	global_load_b64 v[1:2], v[9:10], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_27
; %bb.24:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[4:5] offset:40
	global_load_b64 v[10:11], v9, s[4:5] offset:24 glc
	global_load_b64 v[7:8], v9, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s2, 0
.LBB0_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_26
.LBB0_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_113
; %bb.28:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v31, 0 :: v_dual_and_b32 v32, 2, v1
	v_dual_mov_b32 v4, v2 :: v_dual_and_b32 v3, -3, v1
	v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
	s_mov_b64 s[8:9], 10
.LBB0_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
                                        ;     Child Loop BB0_39 Depth 2
                                        ;     Child Loop BB0_47 Depth 2
                                        ;     Child Loop BB0_55 Depth 2
                                        ;     Child Loop BB0_63 Depth 2
                                        ;     Child Loop BB0_71 Depth 2
                                        ;     Child Loop BB0_79 Depth 2
                                        ;     Child Loop BB0_87 Depth 2
                                        ;     Child Loop BB0_95 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_110 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s2, s[8:9], 56
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr21
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_mov_b32 s2, -1
	s_cbranch_scc1 .LBB0_34
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB0_33
; %bb.31:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_lshl_b64 s[2:3], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[6:7]
.LBB0_32:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v5, v31, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s2, s12
	v_or_b32_e32 v11, v5, v11
	v_or_b32_e32 v12, v6, v12
	s_cbranch_scc1 .LBB0_32
.LBB0_33:                               ; %Flow313
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s21, 0
.LBB0_34:                               ; %Flow315
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b64 s[2:3], s[6:7]
	s_cbranch_vccnz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[11:12], v31, s[6:7]
	s_add_i32 s21, s10, -8
	s_add_u32 s2, s6, 8
	s_addc_u32 s3, s7, 0
.LBB0_36:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB0_41
; %bb.37:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB0_40
; %bb.38:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_39:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v5, v31, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v13, v5, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v6, v14
	s_cbranch_scc1 .LBB0_39
.LBB0_40:                               ; %Flow308
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB0_42
.LBB0_41:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr20
.LBB0_42:                               ; %Flow310
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[13:14], v31, s[2:3]
	s_add_i32 s20, s21, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_44:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_49
; %bb.45:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_48
; %bb.46:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_47:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v5, v31, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v15, v5, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v6, v16
	s_cbranch_scc1 .LBB0_47
.LBB0_48:                               ; %Flow303
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s21, 0
	s_branch .LBB0_50
.LBB0_49:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr21
.LBB0_50:                               ; %Flow305
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[15:16], v31, s[2:3]
	s_add_i32 s21, s20, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_52:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB0_57
; %bb.53:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB0_56
; %bb.54:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_55:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v5, v31, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v17, v5, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v6, v18
	s_cbranch_scc1 .LBB0_55
.LBB0_56:                               ; %Flow298
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB0_58
.LBB0_57:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr20
.LBB0_58:                               ; %Flow300
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[17:18], v31, s[2:3]
	s_add_i32 s20, s21, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_60:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_65
; %bb.61:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_64
; %bb.62:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_63:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v5, v31, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v19, v5, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v6, v20
	s_cbranch_scc1 .LBB0_63
.LBB0_64:                               ; %Flow293
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s21, 0
	s_branch .LBB0_66
.LBB0_65:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr21
.LBB0_66:                               ; %Flow295
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[19:20], v31, s[2:3]
	s_add_i32 s21, s20, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_68:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB0_73
; %bb.69:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB0_72
; %bb.70:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_71:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v5, v31, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v21, v5, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v6, v22
	s_cbranch_scc1 .LBB0_71
.LBB0_72:                               ; %Flow288
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB0_74
.LBB0_73:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr20
.LBB0_74:                               ; %Flow290
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_76
; %bb.75:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[21:22], v31, s[2:3]
	s_add_i32 s20, s21, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_76:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_81
; %bb.77:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[2:3]
.LBB0_79:                               ; %.preheader.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v5, v31, s[16:17]
	s_add_i32 s20, s20, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v30, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[30:31]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s20, 0
	v_or_b32_e32 v23, v5, v23
	v_or_b32_e32 v24, v6, v24
	s_cbranch_scc1 .LBB0_79
.LBB0_80:                               ; %Flow283
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
.LBB0_82:                               ; %Flow285
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[23:24], v31, s[2:3]
.LBB0_84:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v30, v29 :: v_dual_mov_b32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v30
	v_mov_b32_e32 v6, 0
	v_cmp_eq_u32_e64 s2, s2, v30
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_90
; %bb.85:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[27:28], v31, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v31, s[4:5] offset:40
	global_load_b64 v[9:10], v31, s[4:5]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v6, v6, v28
	v_and_b32_e32 v5, v5, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v25, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v25, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[25:26], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v31, v[25:28], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[27:28]
	s_cbranch_execz .LBB0_89
; %bb.86:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s13, 0
.LBB0_87:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v31, s[4:5] offset:40
	global_load_b64 v[25:26], v31, s[4:5]
	v_dual_mov_b32 v28, v6 :: v_dual_mov_b32 v27, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[25:26]
	v_and_b32_e32 v25, v10, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[6:7]
	v_mov_b32_e32 v6, v9
	global_load_b64 v[25:26], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v31, v[25:28], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[27:28]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_87
; %bb.88:                               ; %Flow278
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_89:                               ; %Flow280
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_90:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	global_load_b64 v[9:10], v31, s[4:5] offset:40
	global_load_b128 v[25:28], v31, s[4:5]
	v_readfirstlane_b32 s12, v5
	v_readfirstlane_b32 s13, v6
	s_mov_b32 s22, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v9
	v_readfirstlane_b32 s17, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[12:13], s[16:17]
	s_mul_i32 s3, s17, 24
	s_mul_hi_u32 s20, s16, 24
	s_mul_i32 s21, s16, 24
	s_and_saveexec_b32 s23, s2
	s_cbranch_execz .LBB0_92
; %bb.91:                               ;   in Loop: Header=BB0_29 Depth=1
	v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, v31
	s_add_i32 s22, s20, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, s21
	v_add_co_ci_u32_e32 v10, vcc_lo, s22, v26, vcc_lo
	global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_92:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v5, 0, v4
	v_or_b32_e32 v6, v3, v32
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s22, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s22, s22, 28
	v_dual_cndmask_b32 v10, v5, v4 :: v_dual_cndmask_b32 v5, v6, v3
	v_lshlrev_b64 v[3:4], 6, v[30:31]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v27, s16
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	s_and_b32 s22, s22, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v27, vcc_lo, v6, v3
	v_and_or_b32 v9, 0xffffff1f, v5, s22
	v_add_co_ci_u32_e32 v28, vcc_lo, v28, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[27:28], v[9:12], off
	global_store_b128 v[27:28], v[13:16], off offset:16
	global_store_b128 v[27:28], v[17:20], off offset:32
	global_store_b128 v[27:28], v[21:24], off offset:48
	s_and_saveexec_b32 s16, s2
	s_cbranch_execz .LBB0_100
; %bb.93:                               ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x1
	global_load_b64 v[13:14], v31, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v31, s[4:5] offset:40
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v3
	v_readfirstlane_b32 s23, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[12:13]
	s_mul_i32 s17, s23, 24
	s_mul_hi_u32 s23, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s23, s23, s17
	v_add_co_u32 v9, vcc_lo, v25, s22
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v26, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v31, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB0_96
; %bb.94:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s22, 0
.LBB0_95:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s12 :: v_dual_mov_b32 v4, s13
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v31, v[3:6], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_95
.LBB0_96:                               ; %Flow276
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[3:4], v31, s[4:5] offset:16
	s_mov_b32 s22, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v5, s22, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_29 Depth=1
	s_bcnt1_i32_b32 s22, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v30, s22
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[30:31], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b32 v30, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v30
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[30:31], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100:                              ; %Flow277
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s20, s20, s3
	v_add_co_u32 v3, vcc_lo, v25, s21
	v_add_co_ci_u32_e32 v4, vcc_lo, s20, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_101:                              ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_101 Depth=2
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_103:                              ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v5
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_106
.LBB0_105:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s3, -1
.LBB0_106:                              ; %Flow271
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_101
; %bb.107:                              ;   in Loop: Header=BB0_29 Depth=1
	global_load_b128 v[3:6], v[27:28], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_111
; %bb.108:                              ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x2
	global_load_b64 v[5:6], v31, s[4:5] offset:40
	global_load_b64 v[13:14], v31, s[4:5] offset:24 glc
	global_load_b64 v[11:12], v31, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v15, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
	v_and_b32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v9, v5
	v_mul_hi_u32 v15, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, vcc_lo, v11, v5
	v_mov_b32_e32 v11, v13
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v6, v15, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[5:6], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v31, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_111
; %bb.109:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s2, 0
.LBB0_110:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[5:6], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v31, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_110
.LBB0_111:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB0_29
; %bb.112:                              ; %Flow316
	s_mov_b32 s2, 0
	s_branch .LBB0_114
.LBB0_113:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_114:                              ; %Flow331
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_143
; %bb.115:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v3, v29
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v3
	v_cmp_eq_u32_e64 s2, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_121
; %bb.116:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[7:8], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v11, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[7:8]
	s_cbranch_execz .LBB0_120
; %bb.117:                              ; %.preheader3.i.i.i15.preheader
	s_mov_b32 s7, 0
.LBB0_118:                              ; %.preheader3.i.i.i15
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[11:12], v4, s[4:5]
	v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
	global_load_b64 v[5:6], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_118
; %bb.119:                              ; %Flow328
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_120:                              ; %Flow330
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_121:                              ; %.loopexit4.i.i.i10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[4:5] offset:40
	global_load_b128 v[5:8], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v11
	v_readfirstlane_b32 s9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_123
; %bb.122:
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, v4
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v5, s11
	v_add_co_ci_u32_e32 v14, vcc_lo, s12, v6, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_123:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[9:10], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v9
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v1, 0xffffff1f, v1, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
	v_mov_b32_e32 v3, v4
	v_dual_mov_b32 v9, s20 :: v_dual_mov_b32 v12, s23
	v_dual_mov_b32 v10, s21 :: v_dual_mov_b32 v11, s22
	s_clause 0x3
	global_store_b128 v[7:8], v[1:4], off
	global_store_b128 v[7:8], v[9:12], off offset:16
	global_store_b128 v[7:8], v[9:12], off offset:32
	global_store_b128 v[7:8], v[9:12], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_131
; %bb.124:
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s6
	v_mov_b32_e32 v13, s7
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[4:5] offset:32 glc
	global_load_b64 v[1:2], v11, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v1
	v_readfirstlane_b32 s13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v9, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v6, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB0_127
; %bb.125:                              ; %.preheader1.i.i.i13.preheader
	s_mov_b32 s12, 0
.LBB0_126:                              ; %.preheader1.i.i.i13
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7
	s_sleep 1
	global_store_b64 v[9:10], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[1:2], v11, v[1:4], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_126
.LBB0_127:                              ; %Flow326
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v4, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v3, s12, 0
	global_load_b64 v[1:2], v4, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_129
; %bb.128:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB0_129:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB0_131
; %bb.130:
	global_load_b32 v1, v[1:2], off offset:24
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[1:2], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_131:                              ; %Flow327
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v1, vcc_lo, v5, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s10, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_132:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_132 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_134:                              ;   in Loop: Header=BB0_132 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_137
.LBB0_136:                              ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s3, -1
.LBB0_137:                              ; %Flow321
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_132
; %bb.138:
	global_load_b128 v[3:6], v[7:8], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_142
; %bb.139:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[1:2], v9, s[4:5] offset:40
	global_load_b64 v[10:11], v9, s[4:5] offset:24 glc
	global_load_b64 v[7:8], v9, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v5, v5, v12
	v_and_b32_e32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v5, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v7, v1
	v_mov_b32_e32 v7, v10
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_mov_b32_e32 v8, v11
	global_store_b64 v[1:2], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v9, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[7:8], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_142
; %bb.140:                              ; %.preheader.i.i.i12.preheader
	s_mov_b32 s2, 0
.LBB0_141:                              ; %.preheader.i.i.i12
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[7:8]
	v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_141
.LBB0_142:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_143:                              ; %__ockl_printf_append_string_n.exit
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v29
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v29
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_149
; %bb.144:
	v_mov_b32_e32 v5, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[8:9], v5, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v5, s[4:5] offset:40
	global_load_b64 v[6:7], v5, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v10, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v10, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v7, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v5, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[8:9]
	s_cbranch_execz .LBB0_148
; %bb.145:                              ; %.preheader3.i.i.i22.preheader
	s_mov_b32 s7, 0
.LBB0_146:                              ; %.preheader3.i.i.i22
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v5, s[4:5] offset:40
	global_load_b64 v[10:11], v5, s[4:5]
	v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v8, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[2:3]
	v_mov_b32_e32 v2, v6
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v5, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[8:9]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_146
; %bb.147:                              ; %Flow264
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_148:                              ; %Flow266
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_149:                              ; %.loopexit4.i.i.i16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v30, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[5:6], v30, s[4:5] offset:40
	global_load_b128 v[7:10], v30, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v5
	v_readfirstlane_b32 s9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_151
; %bb.150:
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, v30
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v7, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v8, vcc_lo
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[1:2], v[11:14], off offset:8
.LBB0_151:
	s_or_b32 exec_lo, exec_lo, s13
	v_bfe_u32 v1, v0, 10, 10
	s_mul_i32 s12, s19, s15
	s_lshr_b32 s13, s18, 16
	s_add_i32 s12, s12, s14
	s_lshl_b64 s[8:9], s[8:9], 12
	v_mad_u64_u32 v[11:12], null, s12, s13, v[1:2]
	s_mov_b32 s12, 0
	v_lshlrev_b64 v[1:2], 6, v[29:30]
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v9, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	s_and_b32 s8, s18, 0xffff
	v_and_or_b32 v3, 0xffffff1d, v3, 34
	v_mad_u64_u32 v[5:6], null, v11, s8, v[0:1]
	v_add_co_u32 v0, vcc_lo, v9, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v2, vcc_lo
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v6, v30
	v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v10, s13
	v_mov_b32_e32 v12, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[3:6], off
	global_store_b128 v[0:1], v[9:12], off offset:16
	global_store_b128 v[0:1], v[9:12], off offset:32
	global_store_b128 v[0:1], v[9:12], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_159
; %bb.152:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, s6
	v_mov_b32_e32 v10, s7
	s_clause 0x1
	global_load_b64 v[11:12], v6, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v6, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v4, vcc_lo, v7, s12
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v8, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_155
; %bb.153:                              ; %.preheader1.i.i.i20.preheader
	s_mov_b32 s12, 0
.LBB0_154:                              ; %.preheader1.i.i.i20
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v6, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_154
.LBB0_155:                              ; %Flow262
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_157
; %bb.156:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_157:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_159
; %bb.158:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_159:                              ; %Flow263
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v0, vcc_lo, v7, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_160:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_160 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_162:                              ;   in Loop: Header=BB0_160 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v2
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_160 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_165
.LBB0_164:                              ;   in Loop: Header=BB0_160 Depth=1
	s_mov_b32 s3, -1
.LBB0_165:                              ; %Flow257
                                        ;   in Loop: Header=BB0_160 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_160
; %bb.166:
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_170
; %bb.167:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[4:5] offset:40
	global_load_b64 v[7:8], v6, s[4:5] offset:24 glc
	global_load_b64 v[4:5], v6, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s6
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_170
; %bb.168:                              ; %.preheader.i.i.i19.preheader
	s_mov_b32 s2, 0
.LBB0_169:                              ; %.preheader.i.i.i19
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_169
.LBB0_170:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s4, 0
	s_cbranch_scc1 .LBB0_174
; %bb.171:                              ; %.lr.ph.preheader
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
.LBB0_172:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	flat_load_b64 v[2:3], v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, 0
	s_cbranch_scc1 .LBB0_172
; %bb.173:                              ; %._crit_edge
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, 0x29a, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_i32_e32 v0, v0
	s_branch .LBB0_175
.LBB0_174:
	v_mov_b32_e32 v0, 0
.LBB0_175:
	v_mov_b32_e32 v1, 0
	global_store_b32 v1, v0, s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelimPVmPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelimPVmPf, .Lfunc_end0-_Z6kernelimPVmPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6852
; NumSgprs: 26
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	" I am %d\n"
	.size	.str, 10

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelimPVmPf
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelimPVmPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
