// *----------------------------------------------
// 	Author Contact Information:
// 	Hao Gao
// 	hao.gao@emory.edu || hao.gao.2012@gmail.com
// 	Department of Mathematics and Computer Science, Emory University
// 	Department of Radiology and Imaging Sciences, Emory University
//
// 	Copyright (c) Hao Gao 2012
// ----------------------------------------------*/
//
// If you find this code useful, you may cite the following reference:
// H. Gao. "Fast parallel algorithms for the X-ray transform and its adjoint", Medical Physics (2012).
// The full source codes are available at https://sites.google.com/site/fastxraytransform

#include <math.h>
#include <malloc.h>
#define ABS(a) (a>0?a:-(a))

#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 16

extern "C" void Ax_fan_mf_gpu_new(float *X,float *y,float SO,float OD,float scale,int nx,int ny,int nv,float *sd_phi,int nd,float *y_det,int *id_X,int nt);

__global__ void Ax_fan_mf_gpu_new_kernel(float *X,float *y,float SO,float OD,float scale,int nx,int ny,int nv,float *sd_phi,int nd,float *y_det,int *id_X)
// Please note that this version has O(Nx) per thread, since GPU threads are already saturated.
// O(1) per thread can be achieved by parallelizing the "for" loop here, given sufficient number of GPU threads.
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx0=threadIdx.x;
	int ty0=threadIdx.y;

	int iv=bx*BLOCK_SIZE_x+tx0;
	int id=by*BLOCK_SIZE_y+ty0;

    if(iv<nv&&id<nd)
    {
		int n,nx2,ny2,ix,iy,c1,c2;
		float *x,cos_phi,sin_phi,x1,y1,x2,y2,xx1,yy1,xx2,yy2,slope,l,d;

		nx2=nx/2;ny2=ny/2;
		n=nx*ny;

		x=&X[id_X[iv]*n];
        cos_phi=(float)cos(sd_phi[iv]);sin_phi=(float)sin(sd_phi[iv]);
        x1=cos_phi*(-SO);
        y1=sin_phi*(-SO);

        x2=cos_phi*OD-sin_phi*y_det[id];
        y2=sin_phi*OD+cos_phi*y_det[id];

        y[iv*nd+id]=0;
        if(ABS(x1-x2)>ABS(y1-y2))
        {   slope=(y2-y1)/(x2-x1);
            for(ix=0;ix<nx;ix++)
            {   xx1=(float)(ix-nx2);xx2=xx1+1;
                if(slope>=0)
                {   yy1=y1+slope*(xx1-x1)+ny2;
                    yy2=y1+slope*(xx2-x1)+ny2;
                }
                else
                {   yy1=y1+slope*(xx2-x1)+ny2;
                    yy2=y1+slope*(xx1-x1)+ny2;
                }
                c1=(int)floor(yy1);
                c2=(int)floor(yy2);

                if(c2==c1)// c1 and c2 differs less than 1
                {   if(c1>=0&&c1<=ny-1)
                    {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                        iy=c1;y[iv*nd+id]+=l*x[iy*nx+ix];
                    }
                }
                else
                {   if(c2>0&&c2<ny)
                    {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                        iy=c1;y[iv*nd+id]+=((c2-yy1)/d)*l*x[iy*nx+ix];
                        iy=c2;y[iv*nd+id]+=((yy2-c2)/d)*l*x[iy*nx+ix];
                    }
                    else
                    {   if(c2==0)
                        {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                            iy=c2;y[iv*nd+id]+=((yy2-c2)/d)*l*x[iy*nx+ix];
                        }
                        if(c2==ny)
                        {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                            iy=c1;y[iv*nd+id]+=((c2-yy1)/d)*l*x[iy*nx+ix];
                        }
                    }
                }
            }
        }
        else
        {   slope=(x2-x1)/(y2-y1);
            for(iy=0;iy<ny;iy++)
            {   yy1=(float)(iy-ny2);yy2=yy1+1;

                if(slope>=0)
                {   xx1=x1+slope*(yy1-y1)+nx2;
                    xx2=x1+slope*(yy2-y1)+nx2;
                }
                else
                {   xx1=x1+slope*(yy2-y1)+nx2;
                    xx2=x1+slope*(yy1-y1)+nx2;
                }
                c1=(int)floor(xx1);
                c2=(int)floor(xx2);

                if(c2==c1)// c1 and c2 differs less than 1
                {   if(c1>=0&&c1<=nx-1)
                    {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                        ix=c1;y[iv*nd+id]+=l*x[iy*nx+ix];
                    }
                }
                else
                {   if(c2>0&&c2<nx)
                    {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                        ix=c1;y[iv*nd+id]+=((c2-xx1)/d)*l*x[iy*nx+ix];
                        ix=c2;y[iv*nd+id]+=((xx2-c2)/d)*l*x[iy*nx+ix];
                    }
                    else
                    {   if(c2==0)
                        {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                            ix=c2;y[iv*nd+id]+=((xx2-c2)/d)*l*x[iy*nx+ix];
                        }
                        if(c2==ny)
                        {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                            ix=c1;y[iv*nd+id]+=((c2-xx1)/d)*l*x[iy*nx+ix];
                        }
                    }
                }
            }
        }
        y[iv*nd+id]*=scale;
    }
}

void Ax_fan_mf_gpu_new(float *X,float *y,float SO,float OD,float scale,int nx,int ny,int nv,float *sd_phi,int nd,float *y_det,int *id_X,int nt)
// A new method for computing the X-ray transform (infinitely-narrow beam)
// The algorithm details are available in
// H. Gao. "Fast parallel algorithms for the X-ray transform and its adjoint", Medical Physics (2012).
{   float *y_d,*X_d,*sd_phi_d,*y_det_d;
	int *id_X_d;

	cudaMalloc(&y_d,nv*nd*sizeof(float));
	cudaMalloc(&X_d,nx*ny*nt*sizeof(float));
	cudaMalloc(&sd_phi_d,nv*sizeof(float));
	cudaMalloc(&y_det_d,nd*sizeof(float));
	cudaMalloc(&id_X_d,nv*sizeof(int));

	cudaMemcpy(X_d,X,nx*ny*nt*sizeof(float),cudaMemcpyHostToDevice);
	cudaMemcpy(sd_phi_d,sd_phi,nv*sizeof(float),cudaMemcpyHostToDevice);
	cudaMemcpy(y_det_d,y_det,nd*sizeof(float),cudaMemcpyHostToDevice);
	cudaMemcpy(id_X_d,id_X,nv*sizeof(int),cudaMemcpyHostToDevice);

	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);
	dim3 dimGrid_t((nv+dimBlock.x-1)/dimBlock.x,(nd+dimBlock.y-1)/dimBlock.y);

	Ax_fan_mf_gpu_new_kernel<<<dimGrid_t, dimBlock>>>(X_d,y_d,SO,OD,scale,nx,ny,nv,sd_phi_d,nd,y_det_d,id_X_d);

	cudaMemcpy(y,y_d,nv*nd*sizeof(float),cudaMemcpyDeviceToHost);

    cudaFree(y_d);cudaFree(X_d);cudaFree(sd_phi_d);cudaFree(y_det_d);cudaFree(id_X_d);
}

	.file	"tmpxft_002a7dd0_00000000-6_Ax_fan_mf_gpu_new.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi
	.type	_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi, @function
_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	264(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	272(%rsp), %rax
	movl	%edx, 32(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi, .-_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi
	.globl	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.type	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, @function
_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi
	.cfi_endproc
.LFE2053:
	.size	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, .-_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.globl	Ax_fan_mf_gpu_new
	.type	Ax_fan_mf_gpu_new, @function
Ax_fan_mf_gpu_new:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	movq	232(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	88(%rsp), %rdi
	movss	%xmm0, 76(%rsp)
	movl	224(%rsp), %r13d
	movq	%rax, 40(%rsp)
	movq	240(%rsp), %rax
	movss	%xmm1, 72(%rsp)
	movq	%rax, 48(%rsp)
	movss	%xmm2, 68(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	movl	%r8d, %eax
	imull	%r13d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	96(%rsp), %rdi
	imull	%r12d, %eax
	imull	248(%rsp), %eax
	cltq
	leaq	0(,%rax,4), %rdx
	movq	%rdx, %rsi
	movq	%rdx, 56(%rsp)
	call	cudaMalloc@PLT
	movslq	%ebx, %rax
	leaq	104(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movslq	%r13d, %rax
	leaq	112(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	120(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdx
	movq	96(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	104(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	112(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	120(%rsp), %rdi
	call	cudaMemcpy@PLT
	leal	15(%rbx), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$4, %eax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	%eax, 140(%rsp)
	leal	15(%r13), %eax
	shrl	$4, %eax
	movl	%eax, 144(%rsp)
	movq	140(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	68(%rsp), %xmm2
	movss	72(%rsp), %xmm1
	testl	%eax, %eax
	movss	76(%rsp), %xmm0
	jne	.L9
	pushq	%rax
	.cfi_def_cfa_offset 232
	movl	%ebx, %r8d
	movl	%r12d, %ecx
	movl	%ebp, %edx
	pushq	128(%rsp)
	.cfi_def_cfa_offset 240
	pushq	128(%rsp)
	.cfi_def_cfa_offset 248
	pushq	%r13
	.cfi_def_cfa_offset 256
	movq	136(%rsp), %r9
	movq	120(%rsp), %rsi
	movq	128(%rsp), %rdi
	call	_Z59__device_stub__Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_PiPfS_fffiiiS_iS_Pi
	addq	$32, %rsp
	.cfi_def_cfa_offset 224
.L9:
	movq	16(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	movq	32(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	Ax_fan_mf_gpu_new, .-Ax_fan_mf_gpu_new
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// *----------------------------------------------
// 	Author Contact Information:
// 	Hao Gao
// 	hao.gao@emory.edu || hao.gao.2012@gmail.com
// 	Department of Mathematics and Computer Science, Emory University
// 	Department of Radiology and Imaging Sciences, Emory University
//
// 	Copyright (c) Hao Gao 2012
// ----------------------------------------------*/
//
// If you find this code useful, you may cite the following reference:
// H. Gao. "Fast parallel algorithms for the X-ray transform and its adjoint", Medical Physics (2012).
// The full source codes are available at https://sites.google.com/site/fastxraytransform


#include <hip/hip_runtime.h>
#include <math.h>
#include <malloc.h>
#define ABS(a) (a>0?a:-(a))

#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 16

extern "C" void Ax_fan_mf_gpu_new(float *X,float *y,float SO,float OD,float scale,int nx,int ny,int nv,float *sd_phi,int nd,float *y_det,int *id_X,int nt);

__global__ void Ax_fan_mf_gpu_new_kernel(float *X,float *y,float SO,float OD,float scale,int nx,int ny,int nv,float *sd_phi,int nd,float *y_det,int *id_X)
// Please note that this version has O(Nx) per thread, since GPU threads are already saturated.
// O(1) per thread can be achieved by parallelizing the "for" loop here, given sufficient number of GPU threads.
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx0=threadIdx.x;
	int ty0=threadIdx.y;

	int iv=bx*BLOCK_SIZE_x+tx0;
	int id=by*BLOCK_SIZE_y+ty0;

    if(iv<nv&&id<nd)
    {
		int n,nx2,ny2,ix,iy,c1,c2;
		float *x,cos_phi,sin_phi,x1,y1,x2,y2,xx1,yy1,xx2,yy2,slope,l,d;

		nx2=nx/2;ny2=ny/2;
		n=nx*ny;

		x=&X[id_X[iv]*n];
        cos_phi=(float)cos(sd_phi[iv]);sin_phi=(float)sin(sd_phi[iv]);
        x1=cos_phi*(-SO);
        y1=sin_phi*(-SO);

        x2=cos_phi*OD-sin_phi*y_det[id];
        y2=sin_phi*OD+cos_phi*y_det[id];

        y[iv*nd+id]=0;
        if(ABS(x1-x2)>ABS(y1-y2))
        {   slope=(y2-y1)/(x2-x1);
            for(ix=0;ix<nx;ix++)
            {   xx1=(float)(ix-nx2);xx2=xx1+1;
                if(slope>=0)
                {   yy1=y1+slope*(xx1-x1)+ny2;
                    yy2=y1+slope*(xx2-x1)+ny2;
                }
                else
                {   yy1=y1+slope*(xx2-x1)+ny2;
                    yy2=y1+slope*(xx1-x1)+ny2;
                }
                c1=(int)floor(yy1);
                c2=(int)floor(yy2);

                if(c2==c1)// c1 and c2 differs less than 1
                {   if(c1>=0&&c1<=ny-1)
                    {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                        iy=c1;y[iv*nd+id]+=l*x[iy*nx+ix];
                    }
                }
                else
                {   if(c2>0&&c2<ny)
                    {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                        iy=c1;y[iv*nd+id]+=((c2-yy1)/d)*l*x[iy*nx+ix];
                        iy=c2;y[iv*nd+id]+=((yy2-c2)/d)*l*x[iy*nx+ix];
                    }
                    else
                    {   if(c2==0)
                        {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                            iy=c2;y[iv*nd+id]+=((yy2-c2)/d)*l*x[iy*nx+ix];
                        }
                        if(c2==ny)
                        {   d=yy2-yy1;l=(float)sqrt(d*d+1);
                            iy=c1;y[iv*nd+id]+=((c2-yy1)/d)*l*x[iy*nx+ix];
                        }
                    }
                }
            }
        }
        else
        {   slope=(x2-x1)/(y2-y1);
            for(iy=0;iy<ny;iy++)
            {   yy1=(float)(iy-ny2);yy2=yy1+1;

                if(slope>=0)
                {   xx1=x1+slope*(yy1-y1)+nx2;
                    xx2=x1+slope*(yy2-y1)+nx2;
                }
                else
                {   xx1=x1+slope*(yy2-y1)+nx2;
                    xx2=x1+slope*(yy1-y1)+nx2;
                }
                c1=(int)floor(xx1);
                c2=(int)floor(xx2);

                if(c2==c1)// c1 and c2 differs less than 1
                {   if(c1>=0&&c1<=nx-1)
                    {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                        ix=c1;y[iv*nd+id]+=l*x[iy*nx+ix];
                    }
                }
                else
                {   if(c2>0&&c2<nx)
                    {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                        ix=c1;y[iv*nd+id]+=((c2-xx1)/d)*l*x[iy*nx+ix];
                        ix=c2;y[iv*nd+id]+=((xx2-c2)/d)*l*x[iy*nx+ix];
                    }
                    else
                    {   if(c2==0)
                        {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                            ix=c2;y[iv*nd+id]+=((xx2-c2)/d)*l*x[iy*nx+ix];
                        }
                        if(c2==ny)
                        {   d=xx2-xx1;l=(float)sqrt(d*d+1);
                            ix=c1;y[iv*nd+id]+=((c2-xx1)/d)*l*x[iy*nx+ix];
                        }
                    }
                }
            }
        }
        y[iv*nd+id]*=scale;
    }
}

void Ax_fan_mf_gpu_new(float *X,float *y,float SO,float OD,float scale,int nx,int ny,int nv,float *sd_phi,int nd,float *y_det,int *id_X,int nt)
// A new method for computing the X-ray transform (infinitely-narrow beam)
// The algorithm details are available in
// H. Gao. "Fast parallel algorithms for the X-ray transform and its adjoint", Medical Physics (2012).
{   float *y_d,*X_d,*sd_phi_d,*y_det_d;
	int *id_X_d;

	hipMalloc(&y_d,nv*nd*sizeof(float));
	hipMalloc(&X_d,nx*ny*nt*sizeof(float));
	hipMalloc(&sd_phi_d,nv*sizeof(float));
	hipMalloc(&y_det_d,nd*sizeof(float));
	hipMalloc(&id_X_d,nv*sizeof(int));

	hipMemcpy(X_d,X,nx*ny*nt*sizeof(float),hipMemcpyHostToDevice);
	hipMemcpy(sd_phi_d,sd_phi,nv*sizeof(float),hipMemcpyHostToDevice);
	hipMemcpy(y_det_d,y_det,nd*sizeof(float),hipMemcpyHostToDevice);
	hipMemcpy(id_X_d,id_X,nv*sizeof(int),hipMemcpyHostToDevice);

	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);
	dim3 dimGrid_t((nv+dimBlock.x-1)/dimBlock.x,(nd+dimBlock.y-1)/dimBlock.y);

	Ax_fan_mf_gpu_new_kernel<<<dimGrid_t, dimBlock>>>(X_d,y_d,SO,OD,scale,nx,ny,nv,sd_phi_d,nd,y_det_d,id_X_d);

	hipMemcpy(y,y_d,nv*nd*sizeof(float),hipMemcpyDeviceToHost);

    hipFree(y_d);hipFree(X_d);hipFree(sd_phi_d);hipFree(y_det_d);hipFree(id_X_d);
}

	.text
	.file	"Ax_fan_mf_gpu_new.hip"
	.globl	_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi # -- Begin function _Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.type	_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi,@function
_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi: # @_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	8(%rsp), %r14
	movl	%edx, (%r14)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%rdx, 48(%rbx)
	movq	%rcx, 56(%rbx)
	movq	%r8, 64(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, .Lfunc_end0-_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.cfi_endproc
                                        # -- End function
	.globl	Ax_fan_mf_gpu_new               # -- Begin function Ax_fan_mf_gpu_new
	.type	Ax_fan_mf_gpu_new,@function
Ax_fan_mf_gpu_new:                      # @Ax_fan_mf_gpu_new
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 72(%rsp)                   # 8-byte Spill
	movl	%r8d, %ebx
	movl	%ecx, %r15d
	movl	%edx, %r12d
	movss	%xmm2, 48(%rsp)                 # 4-byte Spill
	movss	%xmm1, 44(%rsp)                 # 4-byte Spill
	movss	%xmm0, 40(%rsp)                 # 4-byte Spill
	movq	%rsi, 80(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movslq	144(%rsp), %rbp
	movl	%ebp, %eax
	imull	%r8d, %eax
	movslq	%eax, %r14
	shlq	$2, %r14
	leaq	32(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%r15d, 56(%rsp)                 # 4-byte Spill
	movl	%r12d, 52(%rsp)                 # 4-byte Spill
	imull	%r12d, %r15d
	imull	168(%rsp), %r15d
	movslq	%r15d, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%ebx, 60(%rsp)                  # 4-byte Spill
	movslq	%ebx, %rbx
	leaq	(,%rbx,4), %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	%rbp, %r13
	shlq	$2, %r13
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	152(%rsp), %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movq	160(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	addl	$15, %ebx
	shrl	$4, %ebx
	leal	15(%rbp), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rbx, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	48(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	52(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	56(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movl	60(%rsp), %edx                  # 4-byte Reload
	movl	64(%rsp), %ecx                  # 4-byte Reload
	movl	68(%rsp), %r8d                  # 4-byte Reload
	pushq	8(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	callq	_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_2:
	movq	32(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	Ax_fan_mf_gpu_new, .Lfunc_end1-Ax_fan_mf_gpu_new
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi,@object # @_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.section	.rodata,"a",@progbits
	.globl	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.p2align	3, 0x0
_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi:
	.quad	_Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.size	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi"
	.size	.L__unnamed_1, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi ; -- Begin function _Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.globl	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
	.p2align	8
	.type	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi,@function
_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi: ; @_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[12:13], s[0:1], 0x20
	s_load_b32 s16, s[0:1], 0x30
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 4, v1
	v_lshl_add_u32 v2, s15, 4, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s13, v0
	v_cmp_gt_i32_e64 s2, s16, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_52
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x38
	v_ashrrev_i32_e32 v1, 31, v0
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v4, v[3:4], off
	global_load_b32 v1, v[5:6], off
                                        ; implicit-def: $vgpr6
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, 0x7fffffff, v4
	v_cmp_ngt_f32_e64 s10, 0x48000000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v3, 23, v5
	s_and_saveexec_b32 s2, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v8, 0
	v_and_or_b32 v16, v5, s2, 0x800000
	v_add_nc_u32_e32 v14, 0xffffff88, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v16, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v14
	v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0x3c439041, v16, v[7:8]
	v_add_nc_u32_e32 v15, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v10
	v_cmp_lt_u32_e64 s2, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xdb629599, v16, v[7:8]
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v6, v10, v6 :: v_dual_add_nc_u32 v17, v17, v15
	v_mov_b32_e32 v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v17
	v_mad_u64_u32 v[11:12], null, 0xf534ddc0, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v12
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0xfc2757d1, v16, v[7:8]
	v_cndmask_b32_e64 v6, v9, v6, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v13
	v_mad_u64_u32 v[13:14], null, 0x4e441529, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v14
	v_mad_u64_u32 v[14:15], null, 0xa2f9836e, v16, v[7:8]
	v_cndmask_b32_e64 v7, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v13, v11 :: v_dual_add_nc_u32 v7, v7, v17
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v13, v15, v13
	v_cndmask_b32_e32 v12, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v11, v14, v8, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v13, v14, s2
	v_cndmask_b32_e64 v8, v8, v12, s2
	v_sub_nc_u32_e32 v14, 32, v7
	v_cndmask_b32_e64 v12, v12, v9, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v13, v11, s3
	v_cndmask_b32_e64 v11, v11, v8, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v12, s3
	v_cndmask_b32_e64 v6, v12, v6, s3
	v_alignbit_b32 v15, v13, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v11, v8, v14
	v_cndmask_b32_e32 v7, v15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v8, v6, v14
	v_cndmask_b32_e32 v9, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v10, v7, 29, 1
	v_cndmask_b32_e32 v8, v13, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v7, v9, 30
	v_sub_nc_u32_e32 v12, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v6, v8, v6, 30
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v9, v12
	v_xor_b32_e32 v6, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v13, v11
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	v_alignbit_b32 v11, v11, v8, v9
	v_alignbit_b32 v6, v8, v6, v9
	v_lshrrev_b32_e32 v9, 29, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v11, v6, 9
	v_lshlrev_b32_e32 v9, 31, v9
	v_lshrrev_b32_e32 v11, 9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v12, v8
	v_or_b32_e32 v14, 0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v12, 32, v12
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v16, 31, v12
	v_alignbit_b32 v6, v8, v6, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v8, v11, v14
	v_add_lshl_u32 v11, v12, v13, 23
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	v_sub_nc_u32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3fc90fda, v8, -v12
	v_add_nc_u32_e32 v6, 0x33000000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v8, v8, 0x33a22168, v11
	v_or_b32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v6
	v_lshrrev_b32_e32 v7, 30, v7
	v_dual_add_f32 v6, v12, v8 :: v_dual_add_nc_u32 v7, v10, v7
.LBB0_3:                                ; %Flow448
	s_or_saveexec_b32 s2, s4
	s_load_b128 s[4:7], s[0:1], 0x10
	v_mul_f32_e64 v10, 0x3f22f983, |v4|
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v10
	v_fma_f32 v6, 0xbfc90fda, v7, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
; %bb.5:                                ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s2, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v18, v5, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v18, 0
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v12
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	v_add_nc_u32_e32 v3, 0xffffff88, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v3
	v_mov_b32_e32 v9, v13
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	v_cndmask_b32_e32 v8, v12, v8, vcc_lo
	v_add_nc_u32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v14
	v_cmp_lt_u32_e64 s2, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v17, v3
	v_mov_b32_e32 v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v3
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v16
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v3, v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v9, v13, v11
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v16, v10, s2
	v_cndmask_b32_e64 v13, v15, v16, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s2
	v_sub_nc_u32_e32 v15, 32, v3
	v_cndmask_b32_e64 v14, v14, v9, s2
	v_cndmask_b32_e64 v8, v9, v8, s2
	v_cndmask_b32_e64 v13, v13, v11, s3
	v_cndmask_b32_e64 v11, v11, v10, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s3
	v_cndmask_b32_e64 v8, v14, v8, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v13, v11, v15
	v_alignbit_b32 v12, v11, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v10, v8, v15
	v_cndmask_b32_e32 v3, v16, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v10, v14, v10
	v_bfe_u32 v11, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v3, v9, 30
	v_alignbit_b32 v9, v9, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 0, v11
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_xor_b32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v12
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v12, v12, v9, v10
	v_alignbit_b32 v8, v9, v8, v10
	v_lshrrev_b32_e32 v10, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v12, v8, 9
	v_lshlrev_b32_e32 v10, 31, v10
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v13, v9
	v_or_b32_e32 v15, 0.5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v13, 32, v13
	v_sub_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, 31, v13
	v_alignbit_b32 v8, v9, v8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v9, v12, v15
	v_add_lshl_u32 v12, v13, v14, 23
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, 0x3fc90fda, v9
	v_sub_nc_u32_e32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v9, -v13
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v9, v9, 0x33a22168, v12
	v_or_b32_e32 v8, v8, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	v_dual_add_f32 v8, v13, v9 :: v_dual_add_nc_u32 v9, v11, v3
.LBB0_7:                                ; %Flow447
	s_and_not1_saveexec_b32 s2, s10
; %bb.8:
	v_rndne_f32_e32 v3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0xbfc90fda, v3, |v4|
	v_cvt_i32_f32_e32 v9, v3
	v_fmamk_f32 v8, v3, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v8, v3, 0xa7c234c4, v8
; %bb.9:                                ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s2, 0xb94c1982
	s_mov_b32 s3, 0x37d75334
	v_xor_b32_e32 v5, v5, v4
	v_mul_f32_e32 v12, v8, v8
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_mul_f32_e32 v3, v6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v16, s2, v12, 0x3c0881c4 :: v_dual_and_b32 v13, 1, v9
	v_lshlrev_b32_e32 v9, 30, v9
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v16, v12, v16, 0xbe2aaa9d
	v_fmaak_f32 v14, s2, v3, 0x3c0881c4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s12, s7
	global_load_b32 v10, v[10:11], off
	v_and_b32_e32 v11, 1, v7
	v_dual_fmaak_f32 v14, v3, v14, 0xbe2aaa9d :: v_dual_lshlrev_b32 v7, 30, v7
	v_fmaak_f32 v15, s3, v3, 0xbab64f3b
	v_and_b32_e32 v9, 0x80000000, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v1, s8, v1
	v_dual_mul_f32 v14, v3, v14 :: v_dual_fmaak_f32 v17, s3, v12, 0xbab64f3b
	v_dual_fmaak_f32 v15, v3, v15, 0x3d2aabf7 :: v_dual_mul_f32 v16, v12, v16
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v6, v6, v14 :: v_dual_fmaak_f32 v17, v12, v17, 0x3d2aabf7
	v_dual_fmaak_f32 v15, v3, v15, 0xbf000004 :: v_dual_fmac_f32 v8, v8, v16
	s_lshr_b32 s8, s7, 31
	s_lshr_b32 s9, s12, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v17, v12, v17, 0xbf000004
	v_fma_f32 v3, v3, v15, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v12, v17, 1.0
	v_cndmask_b32_e64 v3, -v6, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v12, v8 :: v_dual_and_b32 v7, 0x80000000, v7
	v_xor_b32_e32 v3, v7, v3
	v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v5, v5, v9, v6
	v_cndmask_b32_e32 v9, 0x7fc00000, v3, vcc_lo
	v_mad_u64_u32 v[3:4], null, v0, s16, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, 0x7fc00000, v5, vcc_lo
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_f32_e32 v6, s5, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v9, v10
	v_mul_f32_e32 v0, v10, v11
	v_fma_f32 v10, v11, -s4, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f32 v7, v9, s5, -v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_add_i32 s5, s7, s8
	s_ashr_i32 s8, s5, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v9, -s4, -v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	s_add_i32 s0, s12, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s9, s0, 1
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e64 v13, -v10, v10, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v12
	v_mul_f32_e64 v10, v11, -s4
	v_cndmask_b32_e64 v12, -v12, v12, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	v_mul_f32_e64 v9, v9, -s4
	global_store_b32 v[0:1], v8, off
	v_cmpx_ngt_f32_e32 v12, v13
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_30
; %bb.10:
	s_cmp_lt_i32 s12, 1
	s_cbranch_scc1 .LBB0_29
; %bb.11:                               ; %.lr.ph
	v_dual_sub_f32 v4, v7, v9 :: v_dual_sub_f32 v5, v6, v10
	v_cvt_f32_i32_e32 v13, s12
	s_mov_b32 s4, 0
	s_sub_i32 s11, 0, s9
	s_mov_b32 s13, 0
	v_div_scale_f32 v6, null, v5, v5, v4
	v_div_scale_f32 v11, vcc_lo, v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	v_fmac_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v11, v7
	v_fma_f32 v12, -v6, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v12, v7
	v_cvt_f32_i32_e32 v12, s8
	v_fma_f32 v6, -v6, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v7, v8
	v_mov_b32_e32 v8, 0
	v_div_fixup_f32 v11, v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nle_f32_e64 s0, 0, v11
.LBB0_12:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s11, s13
	s_mov_b32 s2, 0
	v_cvt_f32_i32_e32 v4, s1
                                        ; implicit-def: $vgpr15
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v4
	v_cndmask_b32_e64 v6, v4, v5, s0
	v_cndmask_b32_e64 v4, v5, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v10
	v_fma_f32 v4, v11, v4, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v6, v10
                                        ; implicit-def: $vgpr6
	v_add_f32_e32 v14, v4, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v11, v5, v9
	v_add_f32_e32 v7, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v5, v14
	v_floor_f32_e32 v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v5, v5
	v_cvt_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e64 v5, v4
	s_xor_b32 s14, exec_lo, s1
	s_cbranch_execz .LBB0_22
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v5
	v_cmp_le_i32_e64 s1, s7, v5
	s_mov_b32 s5, 0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s2
	s_cbranch_execz .LBB0_19
; %bb.14:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_12 Depth=1
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[4:5], 2
	v_add_co_u32 v15, vcc_lo, v2, s16
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v3, vcc_lo
	global_load_b32 v6, v[15:16], off
	v_sub_f32_e32 v15, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, v15, v15, 1.0
	v_mul_f32_e32 v17, 0x4f800000, v16
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	v_div_scale_f32 v18, null, v15, v15, v14
	v_sqrt_f32_e32 v19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v17, v18
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v22, 1, v19
	v_add_nc_u32_e32 v21, -1, v19
	v_fma_f32 v20, -v18, v17, 1.0
	v_fma_f32 v24, -v22, v19, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v23, -v21, v19, v16
	v_fmac_f32_e32 v17, v20, v17
	v_div_scale_f32 v20, s1, v14, v15, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s2, 0, v23
	v_mul_f32_e32 v25, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v21, s2
	v_cmp_lt_f32_e64 s2, 0, v24
	v_fma_f32 v21, -v18, v25, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v19, v22, s2
	v_fmac_f32_e32 v25, v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, 0x37800000, v19
	v_fma_f32 v18, -v18, v25, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, v19, v21, vcc_lo
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f32 v17, v18, v17, v25
	v_cmp_class_f32_e64 vcc_lo, v16, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v15, v17, v15, v14
	v_cndmask_b32_e32 v16, v19, v16, vcc_lo
	v_mul_f32_e32 v15, v15, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v8, v15, v6
	global_store_b32 v[0:1], v8, off
.LBB0_16:                               ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_mov_b32 s5, 0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr6
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e64 s12, v5
	s_xor_b32 s15, exec_lo, s1
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v5, v14, v7
	v_sub_f32_e32 v6, v13, v7
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v14, null, v5, v5, v6
	v_rcp_f32_e32 v16, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v14, v16, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v17, v16
	v_fma_f32 v7, v5, v5, 1.0
	v_div_scale_f32 v18, vcc_lo, v6, v5, v6
	v_dual_mul_f32 v15, 0x4f800000, v7 :: v_dual_mul_f32 v20, v18, v16
	v_cmp_gt_f32_e64 s1, 0xf800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, -v14, v20, v18
	v_cndmask_b32_e64 v7, v7, v15, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v23, v16
	v_sqrt_f32_e32 v15, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v14, v20, v18
	v_div_fmas_f32 v14, v14, v16, v20
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, -1, v15
	v_add_nc_u32_e32 v19, 1, v15
	v_cmp_class_f32_e64 vcc_lo, v7, 0x260
	v_div_fixup_f32 v5, v14, v5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v21, -v17, v15, v7
	v_fma_f32 v22, -v19, v15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v21
	v_cndmask_b32_e64 v15, v15, v17, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v22
	v_cndmask_b32_e64 v15, v15, v19, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, 0x37800000, v15
	v_cndmask_b32_e64 v15, v15, v17, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v15, v7, vcc_lo
	v_dual_mul_f32 v15, v6, v5 :: v_dual_add_nc_u32 v6, s4, v4
.LBB0_18:                               ; %Flow432
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s5, exec_lo
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
.LBB0_19:                               ; %Flow431
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s15, s3
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_12 Depth=1
	v_dual_sub_f32 v6, v14, v7 :: v_dual_add_nc_u32 v15, s4, v4
	s_or_b32 s5, s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v2, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, v3, v16, vcc_lo
	global_load_b32 v4, v[15:16], off
	v_fma_f32 v15, v6, v6, 1.0
	v_cvt_f32_i32_e32 v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v17, 0x4f800000, v15 :: v_dual_sub_f32 v14, v14, v16
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v15
	v_div_scale_f32 v19, null, v6, v6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_rcp_f32_e32 v21, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_sqrt_f32_e32 v18, v15
	v_sub_f32_e32 v7, v16, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v19, v21, 1.0
	v_add_nc_u32_e32 v20, -1, v18
	v_div_scale_f32 v17, null, v6, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, v25, v21 :: v_dual_add_nc_u32 v24, 1, v18
	v_fma_f32 v23, -v20, v18, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v17
	v_cmp_ge_f32_e64 s2, 0, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v18, v20, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v17, v16, 1.0
	v_fma_f32 v18, -v24, v18, v15
	v_div_scale_f32 v25, s2, v14, v6, v14
	v_fmac_f32_e32 v16, v22, v16
	v_div_scale_f32 v22, s1, v7, v6, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s3, 0, v18
	v_mul_f32_e32 v23, v22, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v20, v24, s3
	v_mul_f32_e32 v20, v25, v21
	v_fma_f32 v26, -v17, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v24, 0x37800000, v18 :: v_dual_fmac_f32 v23, v26, v16
	v_fma_f32 v26, -v19, v20, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v18, v18, v24, vcc_lo
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v17, -v17, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v16, v17, v16, v23
	v_cmp_class_f32_e64 vcc_lo, v15, 0x260
	v_div_fixup_f32 v7, v16, v6, v7
	v_cndmask_b32_e32 v15, v18, v15, vcc_lo
	v_fmac_f32_e32 v20, v26, v21
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v19, v20, v25
	v_div_fmas_f32 v16, v17, v21, v20
	v_mul_f32_e32 v17, v15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v14, v16, v6, v14
	v_mad_u64_u32 v[6:7], null, s13, s7, v[5:6]
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v8, v17, v4 :: v_dual_mul_f32 v15, v15, v14
	global_store_b32 v[0:1], v8, off
.LBB0_21:                               ; %Flow433
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s5, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr7
.LBB0_22:                               ; %Flow
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s3, s14
	s_cbranch_execz .LBB0_26
; %bb.23:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_i32_e64 s1, s7, v4
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s14, vcc_lo, s1
	s_mov_b32 s1, s2
	s_and_saveexec_b32 s5, s14
	s_cbranch_execz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v5, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v5, v5, 1.0
	v_mul_f32_e32 v6, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_sqrt_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v7, -1, v6
	v_add_nc_u32_e32 v14, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v7, v6, v5
	v_fma_f32 v16, -v14, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v15
	v_cndmask_b32_e64 v6, v6, v7, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s1, 0, v16
	v_cndmask_b32_e64 v6, v6, v14, s1
	s_or_b32 s1, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, 0x37800000, v6
	v_cndmask_b32_e32 v14, v6, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_mad_u64_u32 v[6:7], null, s13, s7, v[4:5]
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v14, v5, vcc_lo
.LBB0_25:                               ; %Flow435
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s2, s2, s1
.LBB0_26:                               ; %Flow434
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_28
; %bb.27:                               ; %.sink.split367
                                        ;   in Loop: Header=BB0_12 Depth=1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v3, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v15, v4
	global_store_b32 v[0:1], v8, off
.LBB0_28:                               ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s13, s13, 1
	s_add_i32 s4, s4, s7
	s_cmp_lg_u32 s12, s13
	s_cbranch_scc1 .LBB0_12
.LBB0_29:                               ; %Flow437
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr7
.LBB0_30:                               ; %Flow446
	s_and_not1_saveexec_b32 s10, s10
	s_cbranch_execz .LBB0_51
; %bb.31:
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB0_50
; %bb.32:                               ; %.lr.ph343
	v_dual_sub_f32 v6, v6, v10 :: v_dual_sub_f32 v7, v7, v9
	s_sub_i32 s8, 0, s8
	s_mov_b64 s[4:5], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v8, null, v7, v7, v6
	v_div_scale_f32 v13, vcc_lo, v6, v7, v6
	v_rcp_f32_e32 v11, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v8, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v8, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v12, v13
	v_div_fmas_f32 v8, v8, v11, v12
	v_cvt_f32_i32_e32 v11, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v6, v8, v7, v6
	v_mov_b32_e32 v8, 0
	v_cvt_f32_i32_e32 v7, s9
	v_cmp_nle_f32_e64 s0, 0, v6
.LBB0_33:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s8, s4
	s_mov_b32 s2, 0
	v_cvt_f32_i32_e32 v12, s1
                                        ; implicit-def: $vgpr16
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, 1.0, v12
	v_cndmask_b32_e64 v14, v12, v13, s0
	v_cndmask_b32_e64 v12, v13, v12, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v9
	v_fma_f32 v12, v6, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v14, v9 :: v_dual_add_f32 v14, v12, v7
	v_fma_f32 v13, v6, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v15, v14
	v_add_f32_e32 v13, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v15, v15
	v_floor_f32_e32 v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v12, v12
	v_cmpx_ne_u32_e64 v15, v12
	s_xor_b32 s9, exec_lo, s1
	s_cbranch_execz .LBB0_43
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v15
	v_cmp_le_i32_e64 s1, s12, v15
	s_mov_b32 s11, 0
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s2
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s11, exec_lo
	v_cmpx_eq_u32_e32 0, v15
	s_cbranch_execz .LBB0_37
; %bb.36:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b32 v16, v[4:5], off
	v_sub_f32_e32 v17, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v18, v17, v17, 1.0
	v_div_scale_f32 v20, null, v17, v17, v14
	v_mul_f32_e32 v19, 0x4f800000, v18
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	v_rcp_f32_e32 v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v21, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v19, 1.0
	v_add_nc_u32_e32 v23, -1, v21
	v_dual_fmac_f32 v19, v22, v19 :: v_dual_add_nc_u32 v24, 1, v21
	v_div_scale_f32 v22, s1, v14, v17, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, -v23, v21, v18
	v_fma_f32 v26, -v24, v21, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v27, v22, v19
	v_cmp_ge_f32_e64 s2, 0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v23, s2
	v_cmp_lt_f32_e64 s2, 0, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, -v20, v27, v22
	v_cndmask_b32_e64 v21, v21, v24, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, v23, v19
	v_mul_f32_e32 v23, 0x37800000, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v20, v27, v22
	v_cndmask_b32_e32 v21, v21, v23, vcc_lo
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v20, v19, v27
	v_cmp_class_f32_e64 vcc_lo, v18, 0x260
	v_cndmask_b32_e32 v18, v21, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v17, v19, v17, v14
	v_mul_f32_e32 v17, v17, v18
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v8, v17, v16
	global_store_b32 v[0:1], v8, off
.LBB0_37:                               ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s11, 0
                                        ; implicit-def: $vgpr16
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e64 s12, v15
	s_xor_b32 s13, exec_lo, s1
	s_cbranch_execz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_33 Depth=1
	v_sub_f32_e32 v14, v14, v13
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, v14, v14, 1.0
	v_dual_sub_f32 v13, v11, v13 :: v_dual_mul_f32 v16, 0x4f800000, v15
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_div_scale_f32 v17, null, v14, v14, v13
	v_div_scale_f32 v21, s1, v13, v14, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v18, v15
	v_rcp_f32_e32 v16, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v16, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, v19, v16 :: v_dual_add_nc_u32 v19, 1, v18
	v_dual_mul_f32 v23, v21, v16 :: v_dual_add_nc_u32 v20, -1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v19, v18, v15
	v_fma_f32 v22, -v20, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v22
	v_cndmask_b32_e64 v18, v18, v20, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s2, 0, v24
	v_fma_f32 v20, -v17, v23, v21
	v_cndmask_b32_e64 v18, v18, v19, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, 0x37800000, v18
	v_dual_fmac_f32 v23, v20, v16 :: v_dual_cndmask_b32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v17, v23, v21
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f32 v16, v17, v16, v23
	v_cmp_class_f32_e64 vcc_lo, v15, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v13, v16, v14, v13
	v_cndmask_b32_e32 v15, v18, v15, vcc_lo
	v_mul_f32_e32 v16, v15, v13
.LBB0_39:                               ; %Flow440
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s11, exec_lo
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr15
.LBB0_40:                               ; %Flow439
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_and_not1_saveexec_b32 s13, s3
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mad_u64_u32 v[16:17], null, v12, s7, s[4:5]
	s_or_b32 s11, s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v2, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, v3, v17, vcc_lo
	global_load_b32 v12, v[16:17], off
	v_sub_f32_e32 v16, v14, v13
	v_cvt_f32_i32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, v16, v16, 1.0
	v_mul_f32_e32 v19, 0x4f800000, v18
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v17, v13 :: v_dual_cndmask_b32 v18, v18, v19
	v_div_scale_f32 v25, s1, v13, v16, v13
	v_sub_f32_e32 v14, v14, v17
	v_div_scale_f32 v17, null, v16, v16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v21, v18
	v_rcp_f32_e32 v20, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v17, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, v23, v20 :: v_dual_add_nc_u32 v27, 1, v21
	v_mul_f32_e32 v29, v25, v20
	v_div_scale_f32 v19, null, v16, v16, v14
	v_div_scale_f32 v28, s2, v14, v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v22, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v19, v22, 1.0
	v_fmac_f32_e32 v22, v26, v22
	v_add_nc_u32_e32 v24, -1, v21
	v_fma_f32 v26, -v27, v21, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v24, v21, v18
	v_cmp_ge_f32_e64 s3, 0, v23
	v_mul_f32_e32 v23, v28, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v24, s3
	v_cmp_lt_f32_e64 s3, 0, v26
	v_fma_f32 v24, -v17, v29, v25
	v_cndmask_b32_e64 v21, v21, v27, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v29, v24, v20
	v_fma_f32 v24, -v19, v23, v28
	v_mul_f32_e32 v26, 0x37800000, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, -v17, v29, v25
	v_fmac_f32_e32 v23, v24, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v21, v26, vcc_lo
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v19, -v19, v23, v28
	v_div_fmas_f32 v17, v17, v20, v29
	v_cmp_class_f32_e64 vcc_lo, v18, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v13, v17, v16, v13
	v_cndmask_b32_e32 v18, v21, v18, vcc_lo
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v17, v19, v22, v23
	v_mul_f32_e32 v13, v18, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v14, v17, v16, v14
	v_mul_f32_e32 v16, v18, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v8, v13, v12
	v_mov_b32_e32 v12, v15
	global_store_b32 v[0:1], v8, off
.LBB0_42:                               ; %Flow441
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s11, exec_lo
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
.LBB0_43:                               ; %Flow438
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_and_not1_saveexec_b32 s3, s9
	s_cbranch_execz .LBB0_47
; %bb.44:                               ;   in Loop: Header=BB0_33 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v12
	v_cmp_gt_i32_e64 s1, s12, v12
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s11, vcc_lo, s1
	s_mov_b32 s1, s2
	s_and_saveexec_b32 s9, s11
	s_cbranch_execz .LBB0_46
; %bb.45:                               ;   in Loop: Header=BB0_33 Depth=1
	v_sub_f32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, v13, v13, 1.0
	v_mul_f32_e32 v14, 0x4f800000, v13
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	v_sqrt_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v15, -1, v14
	v_add_nc_u32_e32 v16, 1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v15, v14, v13
	v_fma_f32 v18, -v16, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v17
	v_cndmask_b32_e64 v14, v14, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s1, 0, v18
	v_cndmask_b32_e64 v14, v14, v16, s1
	s_or_b32 s1, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, 0x37800000, v14
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x260
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v14, v13, vcc_lo
.LBB0_46:                               ; %Flow443
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s2, s2, s1
.LBB0_47:                               ; %Flow442
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_49
; %bb.48:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_33 Depth=1
	v_mul_lo_u32 v12, v12, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, v2, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v3, v13, vcc_lo
	global_load_b32 v12, v[12:13], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v16, v12
	global_store_b32 v[0:1], v8, off
.LBB0_49:                               ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s7, s4
	s_cbranch_scc0 .LBB0_33
	s_branch .LBB0_51
.LBB0_50:
	v_mov_b32_e32 v8, 0
.LBB0_51:                               ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, s6, v8
	global_store_b32 v[0:1], v2, off
.LBB0_52:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 72
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi, .Lfunc_end0-_Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5672
; NumSgprs: 20
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 72
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z24Ax_fan_mf_gpu_new_kernelPfS_fffiiiS_iS_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
