#include "includes.h"
__device__ void generate2DGaussian(double * output, double sigma, int sz, bool normalize) {

/*x and y coordinates of thread in kernel. The gaussian filters are
*small enough for the kernel to fit into a single thread block of sz*sz*/
const int colIdx = threadIdx.x;
const int rowIdx = threadIdx.y;
int linearIdx = rowIdx*sz + colIdx;

/*calculate distance from centre of filter*/
int distx = abs(colIdx - sz/2);
int disty = abs(rowIdx - sz/2);

output[linearIdx] = exp(-(pow((double)(distx), 2.0)+pow((double)(disty), 2.0))/(2*(pow(sigma, 2.0))));

if(normalize==true) {

/*wait until all threads have assigned a value to their index in the output array*/
__syncthreads();

int i, j;
double sum=0.0;

for(i=0; i<sz; i++) {
for(j=0; j<sz; j++) {
sum += output[i*sz + j];
}
}

/*Let all threads calculate the sum before changing the value of the output array*/
__syncthreads();

output[linearIdx]/=sum;
}
}
__global__ void getGaussian(double * output, double sigma) {

int sz = ceil(sigma*3) * 2 + 1;
int linearIdx = threadIdx.y*sz + threadIdx.x;
if(linearIdx>=sz*sz) return;

generate2DGaussian(output, sigma, sz, false);

}
	.file	"tmpxft_00288f24_00000000-6_getGaussian.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18generate2DGaussianPddib
	.type	_Z18generate2DGaussianPddib, @function
_Z18generate2DGaussianPddib:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z18generate2DGaussianPddib, .-_Z18generate2DGaussianPddib
	.globl	_Z32__device_stub__Z11getGaussianPddPdd
	.type	_Z32__device_stub__Z11getGaussianPddPdd, @function
_Z32__device_stub__Z11getGaussianPddPdd:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movsd	%xmm0, (%rsp)
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11getGaussianPdd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z32__device_stub__Z11getGaussianPddPdd, .-_Z32__device_stub__Z11getGaussianPddPdd
	.globl	_Z11getGaussianPdd
	.type	_Z11getGaussianPdd, @function
_Z11getGaussianPdd:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z11getGaussianPddPdd
	.cfi_endproc
.LFE2034:
	.size	_Z11getGaussianPdd, .-_Z11getGaussianPdd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11getGaussianPdd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11getGaussianPdd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ void generate2DGaussian(double * output, double sigma, int sz, bool normalize) {

/*x and y coordinates of thread in kernel. The gaussian filters are
*small enough for the kernel to fit into a single thread block of sz*sz*/
const int colIdx = threadIdx.x;
const int rowIdx = threadIdx.y;
int linearIdx = rowIdx*sz + colIdx;

/*calculate distance from centre of filter*/
int distx = abs(colIdx - sz/2);
int disty = abs(rowIdx - sz/2);

output[linearIdx] = exp(-(pow((double)(distx), 2.0)+pow((double)(disty), 2.0))/(2*(pow(sigma, 2.0))));

if(normalize==true) {

/*wait until all threads have assigned a value to their index in the output array*/
__syncthreads();

int i, j;
double sum=0.0;

for(i=0; i<sz; i++) {
for(j=0; j<sz; j++) {
sum += output[i*sz + j];
}
}

/*Let all threads calculate the sum before changing the value of the output array*/
__syncthreads();

output[linearIdx]/=sum;
}
}
__global__ void getGaussian(double * output, double sigma) {

int sz = ceil(sigma*3) * 2 + 1;
int linearIdx = threadIdx.y*sz + threadIdx.x;
if(linearIdx>=sz*sz) return;

generate2DGaussian(output, sigma, sz, false);

}
	.text
	.file	"getGaussian.hip"
	.globl	_Z26__device_stub__getGaussianPdd # -- Begin function _Z26__device_stub__getGaussianPdd
	.type	_Z26__device_stub__getGaussianPdd,@function
_Z26__device_stub__getGaussianPdd:      # @_Z26__device_stub__getGaussianPdd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11getGaussianPdd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__getGaussianPdd, .Lfunc_end0-_Z26__device_stub__getGaussianPdd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11getGaussianPdd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11getGaussianPdd,@object      # @_Z11getGaussianPdd
	.section	.rodata,"a",@progbits
	.globl	_Z11getGaussianPdd
	.p2align	3, 0x0
_Z11getGaussianPdd:
	.quad	_Z26__device_stub__getGaussianPdd
	.size	_Z11getGaussianPdd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11getGaussianPdd"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__getGaussianPdd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11getGaussianPdd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11getGaussianPdd      ; -- Begin function _Z11getGaussianPdd
	.globl	_Z11getGaussianPdd
	.p2align	8
	.type	_Z11getGaussianPdd,@function
_Z11getGaussianPdd:                     ; @_Z11getGaussianPdd
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_bfe_u32 v7, v0, 10, 10
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[1:2], 0x40080000, s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ceil_f64_e32 v[1:2], v[1:2]
	v_fma_f64 v[1:2], v[1:2], 2.0, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	v_mad_u64_u32 v[0:1], null, v7, v3, v[2:3]
	v_mul_lo_u32 v1, v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v0, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshrrev_b32_e32 v1, 31, v3
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s22, 0x968915a9
	s_mov_b32 s30, 0x4222de17
	v_add_nc_u32_e32 v1, v3, v1
	s_mov_b32 s23, 0x3fba6564
	s_mov_b32 s31, 0x3fbdee67
	s_mov_b32 s28, 0x3abe935a
	s_mov_b32 s29, 0x3fbe25e4
	v_ashrrev_i32_e32 v1, 1, v1
	s_mov_b32 s26, 0x47e6c9c2
	s_mov_b32 s27, 0x3fc110ef
	s_mov_b32 s16, 0xcfa74449
	s_mov_b32 s17, 0x3fc3b13b
	v_sub_nc_u32_e32 v3, v2, v1
	v_sub_nc_u32_e32 v9, v7, v1
	s_mov_b32 s18, 0x71bf3c30
	s_mov_b32 s19, 0x3fc745d1
	s_mov_b32 s20, 0x1c7792ce
	v_sub_nc_u32_e32 v4, 0, v3
	v_sub_nc_u32_e32 v10, 0, v9
	s_mov_b32 s21, 0x3fcc71c7
	s_mov_b32 s24, 0x924920da
	s_mov_b32 s25, 0x3fd24924
	v_max_i32_e32 v8, v3, v4
	v_max_i32_e32 v9, v9, v10
	s_mov_b32 s14, 0x9999999c
	s_mov_b32 s15, 0x3fd99999
	s_mov_b32 s7, 0xbfe55555
	v_cvt_f64_i32_e32 v[3:4], v8
	s_mov_b32 s6, s2
	s_mov_b32 s12, 0xd5df274d
	s_mov_b32 s13, 0x3c8543b0
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s5, 0x3fe62e42
	s_mov_b32 s34, 0x555502a1
	s_mov_b32 s35, 0x3fa55555
	s_mov_b32 s36, 0x55555511
	s_mov_b32 s37, 0x3fc55555
	s_mov_b32 s38, 11
	s_mov_b32 s39, 0x3fe00000
	s_mov_b32 s40, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e64 v[5:6], |v[3:4]|
	v_frexp_exp_i32_f64_e32 v3, v[3:4]
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[5:6]
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_ldexp_f64 v[10:11], v[5:6], v11
	v_cvt_f64_i32_e32 v[5:6], v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[10:11], 1.0
	v_frexp_mant_f64_e64 v[14:15], |v[5:6]|
	v_add_f64 v[26:27], v[10:11], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[16:17], v[12:13]
	v_cmp_gt_f64_e64 s0, s[2:3], v[14:15]
	v_add_f64 v[28:29], v[12:13], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v18, 0, 1, s0
	v_add_f64 v[10:11], v[10:11], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[14:15], v[14:15], v18
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
	v_add_f64 v[20:21], v[14:15], 1.0
	v_fma_f64 v[16:17], v[18:19], v[16:17], v[16:17]
	v_add_f64 v[32:33], v[14:15], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[18:19], v[20:21]
	v_fma_f64 v[22:23], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[22:23], v[16:17], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[20:21], v[18:19], 1.0
	v_mul_f64 v[22:23], v[26:27], v[16:17]
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[12:13], v[22:23]
	v_fma_f64 v[24:25], -v[20:21], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[22:23], v[12:13], -v[30:31]
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[22:23], v[10:11], v[12:13]
	v_mul_f64 v[24:25], v[32:33], v[18:19]
	v_add_f64 v[12:13], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[30:31], v[10:11]
	v_mul_f64 v[28:29], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[14:15], -v[12:13]
	v_fma_f64 v[14:15], v[24:25], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[26:27], -v[34:35]
	v_fma_f64 v[12:13], v[24:25], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[34:35], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[26:27], -v[20:21]
	v_add_f64 v[30:31], v[28:29], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[14:15], -v[10:11]
	v_add_f64 v[14:15], v[26:27], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[32:33], -v[30:31]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_add_f64 v[14:15], v[30:31], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[32:33], -v[26:27]
	v_add_f64 v[10:11], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[14:15], -v[12:13]
	v_add_f64 v[14:15], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], v[16:17], v[10:11]
	v_add_f64 v[12:13], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[22:23], v[10:11]
	v_add_f64 v[12:13], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[14:15], -v[22:23]
	v_mul_f64 v[12:13], v[18:19], v[12:13]
	v_mul_f64 v[18:19], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[14:15], v[14:15], -v[18:19]
	v_add_f64 v[22:23], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[16:17], -v[24:25]
	v_fma_f64 v[20:21], v[14:15], v[22:23], v[20:21]
	v_mul_f64 v[22:23], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], -v[24:25]
	v_frexp_mant_f64_e64 v[24:25], |s[10:11]|
	v_add_f64 v[26:27], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[16:17], v[16:17], -v[22:23]
	v_add_f64 v[30:31], v[12:13], v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e64 s1, s[2:3], v[24:25]
	v_add_f64 v[18:19], v[26:27], -v[18:19]
	v_mul_f64 v[54:55], v[14:15], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[16:17], v[30:31], v[28:29]
	v_cndmask_b32_e64 v32, 0, 1, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[20:21], -v[18:19]
	v_ldexp_f64 v[24:25], v[24:25], v32
	v_fma_f64 v[32:33], v[26:27], s[30:31], s[22:23]
	v_add_f64 v[34:35], v[22:23], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[24:25], 1.0
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[28:29]
	v_add_f64 v[42:43], v[24:25], -1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[38:39], v[34:35], s[30:31], s[22:23]
	v_add_f64 v[22:23], v[34:35], -v[22:23]
	v_rcp_f64_e32 v[36:37], v[30:31]
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[26:27]
	v_add_f64 v[44:45], v[30:31], -1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[28:29]
	v_add_f64 v[22:23], v[28:29], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[30:31], v[36:37], 1.0
	v_add_f64 v[24:25], v[24:25], -v[44:45]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[26:27]
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[40:41], v[36:37], v[36:37]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[20:21]
	v_fma_f64 v[40:41], -v[30:31], v[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[18:19]
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[40:41], v[36:37], v[36:37]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[26:27], v[32:33], s[14:15]
	v_mul_f64 v[40:41], v[42:43], v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[24:25]
	v_mul_f64 v[48:49], v[26:27], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[46:47], v[30:31], v[40:41]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[26:27], v[32:33], -v[48:49]
	v_fma_f64 v[30:31], v[40:41], v[30:31], -v[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[18:19], v[32:33], v[20:21]
	v_fma_f64 v[24:25], v[40:41], v[24:25], v[30:31]
	v_mul_f64 v[30:31], v[34:35], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[44:45], v[48:49], v[20:21]
	v_add_f64 v[32:33], v[46:47], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[34:35], v[38:39], -v[30:31]
	v_add_f64 v[52:53], v[44:45], s[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[50:51], v[42:43], -v[32:33]
	v_add_f64 v[48:49], v[44:45], -v[48:49]
	v_fma_f64 v[28:29], v[22:23], v[38:39], v[28:29]
	v_add_f64 v[38:39], v[32:33], -v[46:47]
	v_add_f64 v[46:47], v[52:53], s[6:7]
	v_add_f64 v[42:43], v[42:43], -v[50:51]
	v_add_f64 v[20:21], v[20:21], -v[48:49]
	v_fma_f64 v[48:49], v[26:27], v[14:15], -v[54:55]
	v_add_f64 v[56:57], v[30:31], v[28:29]
	v_add_f64 v[24:25], v[38:39], -v[24:25]
	v_add_f64 v[38:39], v[44:45], -v[46:47]
	v_add_f64 v[32:33], v[42:43], -v[32:33]
	v_add_f64 v[20:21], v[20:21], s[12:13]
	v_fma_f64 v[26:27], v[26:27], v[10:11], v[48:49]
	v_add_f64 v[42:43], v[56:57], s[2:3]
	v_add_f64 v[30:31], v[56:57], -v[30:31]
	v_mul_f64 v[44:45], v[16:17], v[34:35]
	v_ldexp_f64 v[10:11], v[10:11], 1
	v_add_f64 v[24:25], v[24:25], v[32:33]
	v_add_f64 v[20:21], v[20:21], v[38:39]
	v_fma_f64 v[18:19], v[18:19], v[14:15], v[26:27]
	v_add_f64 v[26:27], v[42:43], s[6:7]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_fma_f64 v[30:31], v[34:35], v[16:17], -v[44:45]
	v_ldexp_f64 v[14:15], v[14:15], 1
	v_add_f64 v[24:25], v[50:51], v[24:25]
	v_add_f64 v[32:33], v[52:53], v[20:21]
	v_add_f64 v[38:39], v[54:55], v[18:19]
	v_add_f64 v[26:27], v[56:57], -v[26:27]
	v_add_f64 v[28:29], v[28:29], s[12:13]
	v_fma_f64 v[30:31], v[34:35], v[12:13], v[30:31]
	v_ldexp_f64 v[12:13], v[12:13], 1
	v_mul_f64 v[24:25], v[36:37], v[24:25]
	v_add_f64 v[34:35], v[52:53], -v[32:33]
	v_mul_f64 v[36:37], v[38:39], v[32:33]
	v_add_f64 v[26:27], v[28:29], v[26:27]
	v_fma_f64 v[22:23], v[22:23], v[16:17], v[30:31]
	v_add_f64 v[30:31], v[38:39], -v[54:55]
	v_ldexp_f64 v[16:17], v[16:17], 1
	v_add_f64 v[28:29], v[40:41], v[24:25]
	v_add_f64 v[20:21], v[20:21], v[34:35]
	v_fma_f64 v[34:35], v[38:39], v[32:33], -v[36:37]
	v_add_f64 v[46:47], v[42:43], v[26:27]
	v_add_f64 v[48:49], v[44:45], v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_add_f64 v[40:41], v[28:29], -v[40:41]
	v_fma_f64 v[20:21], v[38:39], v[20:21], v[34:35]
	v_mul_f64 v[38:39], v[28:29], v[28:29]
	v_add_f64 v[30:31], v[42:43], -v[46:47]
	v_mul_f64 v[34:35], v[48:49], v[46:47]
	v_add_f64 v[24:25], v[24:25], -v[40:41]
	v_fma_f64 v[18:19], v[18:19], v[32:33], v[20:21]
	v_add_f64 v[20:21], v[48:49], -v[44:45]
	v_add_f64 v[26:27], v[26:27], v[30:31]
	v_fma_f64 v[30:31], v[48:49], v[46:47], -v[34:35]
	v_fma_f64 v[32:33], v[28:29], v[28:29], -v[38:39]
	v_add_f64 v[40:41], v[24:25], v[24:25]
	v_add_f64 v[42:43], v[36:37], v[18:19]
	v_add_f64 v[20:21], v[22:23], -v[20:21]
	v_fma_f64 v[22:23], v[48:49], v[26:27], v[30:31]
	v_cvt_f64_i32_e32 v[30:31], v3
	v_frexp_exp_i32_f64_e32 v3, v[5:6]
	v_fma_f64 v[26:27], v[28:29], v[40:41], v[32:33]
	v_add_f64 v[32:33], v[14:15], v[42:43]
	v_add_f64 v[36:37], v[42:43], -v[36:37]
	v_fma_f64 v[20:21], v[20:21], v[46:47], v[22:23]
	v_mul_f64 v[40:41], v[30:31], s[4:5]
	v_subrev_co_ci_u32_e64 v3, vcc_lo, 0, v3, s0
	v_cmp_eq_u32_e32 vcc_lo, 1, v8
	v_cmp_eq_u32_e64 s0, 1, v9
	v_add_f64 v[22:23], v[38:39], v[26:27]
	v_add_f64 v[14:15], v[32:33], -v[14:15]
	v_add_f64 v[18:19], v[18:19], -v[36:37]
	v_add_f64 v[36:37], v[34:35], v[20:21]
	v_fma_f64 v[46:47], v[30:31], s[4:5], -v[40:41]
	v_fma_f64 v[44:45], v[22:23], s[30:31], s[22:23]
	s_mov_b32 s22, 0x3b39803f
	v_add_f64 v[14:15], v[42:43], -v[14:15]
	v_add_f64 v[10:11], v[10:11], v[18:19]
	v_cvt_f64_i32_e32 v[18:19], v3
	v_add_f64 v[42:43], v[16:17], v[36:37]
	v_add_f64 v[34:35], v[36:37], -v[34:35]
	s_mov_b32 s23, 0x3c7abc9e
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[30:31], v[30:31], s[22:23], v[46:47]
	v_frexp_exp_i32_f64_e32 v3, s[10:11]
	s_mov_b32 s30, 0x11122322
	s_mov_b32 s31, 0x3f811111
	v_fma_f64 v[44:45], v[22:23], v[44:45], s[28:29]
	s_mov_b32 s28, 0x1852b7b0
	s_mov_b32 s29, 0x3f56c16c
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_mul_f64 v[14:15], v[18:19], s[4:5]
	v_add_f64 v[16:17], v[42:43], -v[16:17]
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	v_fma_f64 v[34:35], v[22:23], v[44:45], s[26:27]
	v_add_f64 v[44:45], v[40:41], v[30:31]
	s_mov_b32 s26, 0x14761f6e
	v_add_f64 v[46:47], v[32:33], v[10:11]
	v_fma_f64 v[48:49], v[18:19], s[4:5], -v[14:15]
	v_add_f64 v[16:17], v[36:37], -v[16:17]
	v_add_f64 v[12:13], v[12:13], v[20:21]
	s_mov_b32 s27, 0x3f2a01a0
	v_fma_f64 v[20:21], v[22:23], v[34:35], s[16:17]
	v_add_f64 v[40:41], v[44:45], -v[40:41]
	s_mov_b32 s17, 0xbc7abc9e
	v_add_f64 v[34:35], v[44:45], v[46:47]
	v_fma_f64 v[18:19], v[18:19], s[22:23], v[48:49]
	v_add_f64 v[32:33], v[46:47], -v[32:33]
	v_add_f64 v[12:13], v[12:13], v[16:17]
	s_mov_b32 s16, s22
	v_fma_f64 v[16:17], v[22:23], v[20:21], s[18:19]
	v_add_f64 v[30:31], v[30:31], -v[40:41]
	s_mov_b32 s18, 0xfca7ab0c
	v_add_f64 v[20:21], v[34:35], -v[44:45]
	v_add_f64 v[36:37], v[14:15], v[18:19]
	v_add_f64 v[10:11], v[10:11], -v[32:33]
	v_add_f64 v[48:49], v[42:43], v[12:13]
	s_mov_b32 s19, 0x3e928af3
	v_fma_f64 v[16:17], v[22:23], v[16:17], s[20:21]
	s_mov_b32 s20, 0x6a5dcb37
	s_mov_b32 s21, 0x3e5ade15
	v_add_f64 v[50:51], v[34:35], -v[20:21]
	v_add_f64 v[20:21], v[46:47], -v[20:21]
	v_add_f64 v[14:15], v[36:37], -v[14:15]
	v_add_f64 v[52:53], v[36:37], v[48:49]
	v_fma_f64 v[16:17], v[22:23], v[16:17], s[24:25]
	s_mov_b32 s24, 0x7c89e6b0
	s_mov_b32 s25, 0x3efa0199
	v_add_f64 v[32:33], v[44:45], -v[50:51]
	v_add_f64 v[44:45], v[30:31], v[10:11]
	v_add_f64 v[14:15], v[18:19], -v[14:15]
	v_add_f64 v[40:41], v[52:53], -v[36:37]
	v_fma_f64 v[16:17], v[22:23], v[16:17], s[14:15]
	s_mov_b32 s15, 0xbfe62e42
	s_mov_b32 s14, s4
	v_add_f64 v[20:21], v[20:21], v[32:33]
	v_add_f64 v[32:33], v[48:49], -v[42:43]
	v_add_f64 v[50:51], v[44:45], -v[30:31]
	v_add_f64 v[42:43], v[52:53], -v[40:41]
	v_add_f64 v[18:19], v[48:49], -v[40:41]
	v_mul_f64 v[46:47], v[22:23], v[16:17]
	v_add_f64 v[20:21], v[44:45], v[20:21]
	v_add_f64 v[12:13], v[12:13], -v[32:33]
	v_add_f64 v[38:39], v[44:45], -v[50:51]
	v_add_f64 v[32:33], v[36:37], -v[42:43]
	v_add_f64 v[10:11], v[10:11], -v[50:51]
	v_mul_f64 v[44:45], v[28:29], v[22:23]
	v_fma_f64 v[36:37], v[22:23], v[16:17], -v[46:47]
	v_add_f64 v[40:41], v[34:35], v[20:21]
	v_add_f64 v[42:43], v[14:15], v[12:13]
	v_add_f64 v[30:31], v[30:31], -v[38:39]
	v_add_f64 v[18:19], v[18:19], v[32:33]
	v_fma_f64 v[16:17], v[26:27], v[16:17], v[36:37]
	v_add_f64 v[32:33], v[40:41], -v[34:35]
	v_add_f64 v[34:35], v[42:43], -v[14:15]
	v_add_f64 v[10:11], v[10:11], v[30:31]
	v_add_f64 v[18:19], v[42:43], v[18:19]
	v_add_f64 v[36:37], v[46:47], v[16:17]
	v_add_f64 v[20:21], v[20:21], -v[32:33]
	v_add_f64 v[30:31], v[42:43], -v[34:35]
	v_add_f64 v[12:13], v[12:13], -v[34:35]
	v_add_f64 v[32:33], v[52:53], v[18:19]
	v_fma_f64 v[34:35], v[22:23], v[28:29], -v[44:45]
	v_add_f64 v[38:39], v[36:37], s[2:3]
	v_add_f64 v[42:43], v[36:37], -v[46:47]
	v_add_f64 v[10:11], v[10:11], v[20:21]
	v_add_f64 v[14:15], v[14:15], -v[30:31]
	v_add_f64 v[20:21], v[32:33], -v[52:53]
	v_add_f64 v[30:31], v[38:39], s[6:7]
	v_add_f64 v[16:17], v[16:17], -v[42:43]
	v_cmp_eq_f64_e64 s7, s[10:11], 1.0
	v_add_f64 v[42:43], v[40:41], v[10:11]
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[18:19], -v[20:21]
	v_fma_f64 v[20:21], v[22:23], v[24:25], v[34:35]
	v_mov_b32_e32 v22, 0
	v_cndmask_b32_e64 v23, 2.0, 0x3ff00000, vcc_lo
	v_ldexp_f64 v[24:25], v[24:25], 1
	v_add_f64 v[18:19], v[36:37], -v[30:31]
	v_add_f64 v[16:17], v[16:17], s[12:13]
	s_mov_b32 s12, 0x652b82fe
	v_add_f64 v[30:31], v[42:43], -v[40:41]
	v_mul_f64 v[34:35], v[22:23], v[42:43]
	v_mul_f64 v[40:41], v[22:23], 0.5
	v_add_f64 v[12:13], v[12:13], v[14:15]
	s_mov_b32 s13, 0x3ff71547
	v_add_f64 v[14:15], v[16:17], v[18:19]
	v_fma_f64 v[16:17], v[26:27], v[28:29], v[20:21]
	v_trunc_f64_e32 v[18:19], v[22:23]
	v_add_f64 v[10:11], v[10:11], -v[30:31]
	v_fma_f64 v[20:21], v[22:23], v[42:43], -v[34:35]
	v_add_f64 v[26:27], v[32:33], v[12:13]
	v_ldexp_f64 v[28:29], v[28:29], 1
	v_add_f64 v[30:31], v[38:39], v[14:15]
	v_add_f64 v[36:37], v[44:45], v[16:17]
	v_cmp_eq_f64_e32 vcc_lo, v[18:19], v[22:23]
	v_fma_f64 v[10:11], v[22:23], v[10:11], v[20:21]
	v_cndmask_b32_e64 v23, 2.0, 0x3ff00000, s0
	v_add_f64 v[8:9], v[26:27], -v[32:33]
	v_cmp_class_f64_e64 s0, v[34:35], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[18:19], v[22:23], v[26:27]
	v_add_f64 v[20:21], v[38:39], -v[30:31]
	v_mul_f64 v[32:33], v[36:37], v[30:31]
	v_add_f64 v[8:9], v[12:13], -v[8:9]
	v_fma_f64 v[12:13], v[22:23], v[26:27], -v[18:19]
	v_add_f64 v[26:27], v[36:37], -v[44:45]
	v_cmp_class_f64_e64 s2, v[18:19], 0x204
	v_add_f64 v[14:15], v[14:15], v[20:21]
	v_fma_f64 v[20:21], v[36:37], v[30:31], -v[32:33]
	v_fma_f64 v[8:9], v[22:23], v[8:9], v[12:13]
	v_add_f64 v[12:13], v[16:17], -v[26:27]
	v_add_f64 v[16:17], v[34:35], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[36:37], v[14:15], v[20:21]
	v_add_f64 v[20:21], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[12:13], v[12:13], v[30:31], v[14:15]
	v_cndmask_b32_e64 v15, v17, v35, s0
	v_cndmask_b32_e64 v14, v16, v34, s0
	v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s1
	v_add_f64 v[16:17], v[16:17], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[30:31], v[14:15], s[12:13]
	v_cvt_f64_i32_e32 v[42:43], v3
	v_cndmask_b32_e64 v27, v21, v19, s2
	v_cndmask_b32_e64 v26, v20, v18, s2
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[14:15]
	v_add_f64 v[18:19], v[20:21], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[36:37], v[26:27], s[12:13]
	v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[26:27]
	v_add_f64 v[38:39], v[32:33], v[12:13]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_rndne_f64_e32 v[30:31], v[30:31]
	v_mul_f64 v[50:51], v[42:43], s[4:5]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_rndne_f64_e32 v[36:37], v[36:37]
	v_add_f64 v[44:45], v[28:29], v[38:39]
	v_add_f64 v[32:33], v[38:39], -v[32:33]
	v_fma_f64 v[46:47], v[30:31], s[14:15], v[14:15]
	v_cvt_i32_f64_e32 v3, v[30:31]
	v_fma_f64 v[48:49], v[36:37], s[14:15], v[26:27]
	v_cvt_i32_f64_e32 v5, v[36:37]
	v_add_f64 v[28:29], v[44:45], -v[28:29]
	v_add_f64 v[12:13], v[12:13], -v[32:33]
	v_fma_f64 v[32:33], v[30:31], s[16:17], v[46:47]
	v_fma_f64 v[46:47], v[36:37], s[16:17], v[48:49]
	v_fma_f64 v[48:49], v[42:43], s[4:5], -v[50:51]
	v_trunc_f64_e32 v[36:37], v[22:23]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[14:15]
	v_cmp_nlt_f64_e64 s5, 0x40900000, v[26:27]
	v_add_f64 v[28:29], v[38:39], -v[28:29]
	v_add_f64 v[12:13], v[24:25], v[12:13]
	v_fma_f64 v[24:25], v[32:33], s[20:21], s[18:19]
	v_fma_f64 v[38:39], v[46:47], s[20:21], s[18:19]
	v_fma_f64 v[42:43], v[42:43], s[22:23], v[48:49]
	s_mov_b32 s22, 0x623fde64
	s_mov_b32 s23, 0x3ec71dee
	v_cmp_eq_f64_e64 s1, v[36:37], v[22:23]
	v_add_f64 v[12:13], v[12:13], v[28:29]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[22:23]
	v_fma_f64 v[28:29], v[46:47], v[38:39], s[22:23]
	v_add_f64 v[38:39], v[50:51], v[42:43]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[44:45], v[12:13]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[24:25]
	v_add_f64 v[50:51], v[38:39], -v[50:51]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[52:53], v[38:39], v[48:49]
	v_add_f64 v[44:45], v[48:49], -v[44:45]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[26:27]
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[26:27]
	v_add_f64 v[42:43], v[42:43], -v[50:51]
	v_add_f64 v[54:55], v[52:53], -v[38:39]
	v_add_f64 v[12:13], v[12:13], -v[44:45]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[28:29]
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[28:29]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[56:57], v[52:53], -v[54:55]
	v_add_f64 v[44:45], v[48:49], -v[54:55]
	v_add_f64 v[48:49], v[42:43], v[12:13]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[30:31]
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[30:31]
	v_add_f64 v[38:39], v[38:39], -v[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[34:35]
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[38:39], v[44:45], v[38:39]
	v_add_f64 v[44:45], v[48:49], -v[42:43]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[36:37]
	v_add_f64 v[38:39], v[48:49], v[38:39]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[48:49], v[48:49], -v[44:45]
	v_add_f64 v[12:13], v[12:13], -v[44:45]
	v_fma_f64 v[24:25], v[32:33], v[24:25], s[38:39]
	v_fma_f64 v[28:29], v[46:47], v[28:29], s[38:39]
	v_add_f64 v[50:51], v[52:53], v[38:39]
	v_add_f64 v[42:43], v[42:43], -v[48:49]
	v_mul_f64 v[48:49], v[22:23], 0.5
	v_fma_f64 v[24:25], v[32:33], v[24:25], 1.0
	v_fma_f64 v[28:29], v[46:47], v[28:29], 1.0
	v_add_f64 v[44:45], v[50:51], -v[52:53]
	v_add_f64 v[12:13], v[12:13], v[42:43]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[24:25], v[32:33], v[24:25], 1.0
	v_trunc_f64_e32 v[32:33], v[40:41]
	v_fma_f64 v[28:29], v[46:47], v[28:29], 1.0
	v_add_f64 v[30:31], v[38:39], -v[44:45]
	v_trunc_f64_e32 v[38:39], v[48:49]
	v_ldexp_f64 v[24:25], v[24:25], v3
	v_cmp_neq_f64_e64 s0, v[32:33], v[40:41]
	v_ldexp_f64 v[28:29], v[28:29], v5
	v_add_f64 v[12:13], v[12:13], v[30:31]
	v_cmp_neq_f64_e64 s2, v[38:39], v[48:49]
	v_cndmask_b32_e64 v3, 0x7ff00000, v25, s3
	s_and_b32 vcc_lo, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v25, 0, v3, s4
	v_cndmask_b32_e64 v5, 0x7ff00000, v29, s5
	v_cndmask_b32_e64 v29, 0, v5, s6
	v_add_f64 v[22:23], v[50:51], v[12:13]
	s_and_b32 s0, s1, s2
	s_and_b32 s1, s4, s3
	s_and_b32 s2, s6, s5
	s_and_b32 s3, s7, exec_lo
	s_cselect_b32 s41, 0x3ff00000, 2.0
	v_cmp_neq_f64_e64 s6, 0x7ff00000, |v[14:15]|
	v_cmp_neq_f64_e64 s7, 0x7ff00000, |v[26:27]|
	v_cndmask_b32_e64 v24, 0, v24, s1
	v_cndmask_b32_e64 v28, 0, v28, s2
	v_cndmask_b32_e64 v14, 0x3ff00000, v6, s0
	v_cndmask_b32_e64 v6, 0, v6, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_class_f64_e64 s1, v[24:25], 0x204
	v_cmp_class_f64_e64 s2, v[28:29], 0x204
	v_add_f64 v[30:31], v[22:23], -v[50:51]
	v_mul_f64 v[32:33], s[40:41], v[22:23]
	v_cndmask_b32_e64 v11, 0, v11, s6
	v_cndmask_b32_e64 v10, 0, v10, s6
	v_cndmask_b32_e64 v9, 0, v9, s7
	v_cndmask_b32_e64 v8, 0, v8, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[24:25], v[10:11], v[24:25]
	v_fma_f64 v[8:9], v[28:29], v[8:9], v[28:29]
	v_add_f64 v[12:13], v[12:13], -v[30:31]
	v_fma_f64 v[22:23], s[40:41], v[22:23], -v[32:33]
	v_cmp_class_f64_e64 s3, v[32:33], 0x204
	v_cndmask_b32_e64 v11, v11, v25, s1
	v_cndmask_b32_e64 v10, v10, v24, s1
	v_cndmask_b32_e64 v9, v9, v29, s2
	v_cndmask_b32_e64 v8, v8, v28, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_bfi_b32 v9, 0x7fffffff, v9, v14
	v_fma_f64 v[12:13], s[40:41], v[12:13], v[22:23]
	v_add_f64 v[22:23], v[32:33], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v31, v23, v33, s3
	v_cndmask_b32_e64 v30, v22, v32, s3
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[36:37], v[30:31], s[12:13]
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[30:31]|
	v_cmp_nlt_f64_e64 s4, 0x40900000, v[30:31]
	v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[30:31]
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	v_mul_f64 v[22:23], s[40:41], 0.5
	v_rndne_f64_e32 v[36:37], v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v13, s3
	v_cndmask_b32_e64 v12, 0, v12, s3
	s_and_b32 s3, s5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[36:37], s[14:15], v[30:31]
	v_cvt_i32_f64_e32 v3, v[36:37]
	v_fma_f64 v[38:39], v[36:37], s[16:17], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[38:39], s[20:21], s[18:19]
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[24:25]
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[28:29]
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[34:35]
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[38:39], v[40:41], s[38:39]
	v_fma_f64 v[40:41], v[38:39], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[38:39], v[40:41], 1.0
	v_ldexp_f64 v[32:33], v[36:37], v3
	v_trunc_f64_e32 v[36:37], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 0x7ff00000, v33, s4
	v_cndmask_b32_e64 v30, 0, v32, s3
	v_trunc_f64_e32 v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, 0, v3, s5
	v_cmp_eq_f64_e64 s5, s[40:41], v[36:37]
	v_cmp_class_f64_e64 s40, s[10:11], 0x204
	v_cmp_eq_f64_e64 s41, s[10:11], 0
	v_fma_f64 v[12:13], v[30:31], v[12:13], v[30:31]
	v_cmp_class_f64_e64 s4, v[30:31], 0x204
	v_cmp_neq_f64_e64 s3, v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v13, v31, s4
	v_cndmask_b32_e64 v3, v12, v30, s4
	v_cmp_eq_u32_e64 s4, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, 0, v3, s5
	v_cndmask_b32_e64 v2, 0x7ff00000, 0, s4
	s_and_b32 s33, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s33, exec_lo
	s_cselect_b32 s3, s11, 0x3ff00000
	v_bfi_b32 v5, 0x7fffffff, v5, s3
	v_cmp_lt_f64_e64 s3, s[10:11], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v13, 0x7ff80000, v5, s5
	v_cmp_eq_u32_e64 s5, v7, v1
	v_cndmask_b32_e32 v7, 0x3ff00000, v4, vcc_lo
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_or_b32 vcc_lo, s41, s40
	s_and_b32 s0, s41, exec_lo
	s_cselect_b32 s0, 0, 0x7ff00000
	v_cndmask_b32_e64 v1, 0x7ff00000, 0, s5
	v_bfi_b32 v4, 0x7fffffff, v2, v4
	v_bfi_b32 v7, 0x7fffffff, v11, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v6, 0x7fffffff, v1, v6
	v_cndmask_b32_e64 v4, v7, v4, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v6, v9, v6, s5
	v_cndmask_b32_e64 v5, v5, v13, s3
	v_cndmask_b32_e64 v3, v3, v12, s3
	s_and_b32 s3, s33, exec_lo
	s_cselect_b32 s3, s11, 0
	v_mov_b32_e32 v12, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v3, 0, vcc_lo
	v_cndmask_b32_e64 v3, v10, 0, s4
	v_bfi_b32 v2, 0x7fffffff, s0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v5, v2, vcc_lo
	v_cndmask_b32_e64 v5, v8, 0, s5
	v_cmp_o_f64_e64 vcc_lo, s[10:11], s[10:11]
	v_add_f64 v[1:2], v[1:2], v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_cndmask_b32_e32 v2, 0x7ff80000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], -v[3:4]
	v_div_scale_f64 v[11:12], vcc_lo, -v[3:4], v[1:2], -v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
	v_div_fixup_f64 v[1:2], v[5:6], v[1:2], -v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[3:4], v[1:2], s[12:13]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[1:2]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[1:2]
	v_rndne_f64_e32 v[3:4], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[3:4], s[14:15], v[1:2]
	v_cvt_i32_f64_e32 v9, v[3:4]
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[3:4], s[16:17], v[5:6]
	v_fma_f64 v[7:8], v[5:6], s[20:21], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[22:23]
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[26:27]
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[30:31]
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[36:37]
	v_fma_f64 v[7:8], v[5:6], v[7:8], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[7:8], 1.0
	v_fma_f64 v[3:4], v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[3:4], v[3:4], v9
	v_cndmask_b32_e32 v4, 0x7ff00000, v4, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11getGaussianPdd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 42
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11getGaussianPdd, .Lfunc_end0-_Z11getGaussianPdd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5364
; NumSgprs: 44
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 44
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11getGaussianPdd
    .private_segment_fixed_size: 0
    .sgpr_count:     44
    .sgpr_spill_count: 0
    .symbol:         _Z11getGaussianPdd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
