//nvcc -ptx EM5.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double *r,
                     double *z,
                     double * ar0,
                     double * br0,
                     double * az0,
                     double * bz0,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz ) {
    int globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
    int localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
    int threadsPerBlock = blockDim.x*blockDim.y;
    int n = localThreadIdx + globalBlockIndex*threadsPerBlock;
    if ( n >= parNum ){
        return;
    }
    double r0 = r[n];
    double z0 = z[n];
    int ar,az,a1,a2,a3,a4;
    double b1,b2,b3,b4;
    // Er
    ar = floor(r0/dr-0.5);
    az = floor(z0/dz);
    a1 = ar + az * gridR + 1;
    a2 = (ar+1) + az * gridR + 1;
    a3 = ar + (az+1) * gridR + 1;
    a4 = (ar+1) + (az+1) * gridR + 1;
    if( ar<0 ){
        b1 = 0;
        b2 = (az*dz+dz-z0)/dz;
        b3 = 0;
        b4 = (z0-az*dz)/dz;
        a1 = 1;
        a3 = 1;
    }
    else if( ar >= gridR-1 ){
        b1 = (az*dz+dz-z0)/dz;
        b2 = 0;
        b3 = (z0-az*dz)/dz;
        b4 = 0;
        a2 = 1;
        a4 = 1;
    }
    else{
        b1 = ((ar+1.5)*dr-r0)*((az+1)*dz-z0)/(dr*dz);
        b2 = (r0-(ar+0.5)*dr)*((az+1)*dz-z0)/(dr*dz);
        b3 = ((ar+1.5)*dr-r0)*(z0-az*dz)/(dr*dz);
        b4 = (r0-(ar+0.5)*dr)*(z0-az*dz)/(dr*dz);    
    }
    ar0[n] = a1;
    ar0[n+parNum] = a2;
    ar0[n+2*parNum] = a3;
    ar0[n+3*parNum] = a4;

    br0[n] = b1;
    br0[n+parNum] = b2;
    br0[n+2*parNum] = b3;
    br0[n+3*parNum] = b4;
    // Ez
    ar = floor(r0/dr);
    az = floor(z0/dz-0.5);
    a1 = ar + az * (gridR+1) + 1;
    a2 = (ar+1) + az * (gridR+1) + 1;
    a3 = ar + (az+1) * (gridR+1) + 1;
    a4 = (ar+1) + (az+1) * (gridR+1) + 1;
    if( az<0 ){
        b1 = 0;
        b2 = 0;
        b3 = (ar*dr+dr-r0)/dr;
        b4 = (r0-ar*dr)/dr;
        a1 = 1;
        a2 = 1;
    }
    else if( az >= gridZ-1 ){
        b1 = (ar*dr+dr-r0)/dr;
        b2 = (r0-ar*dr)/dr;
        b3 = 0;
        b4 = 0;
        a3 = 1;
        a4 = 1;
    }
    else{
        b1 = ((ar+1)*dr-r0)*((az+1.5)*dz-z0)/(dr*dz);
        b2 = (r0-ar*dr)*((az+1.5)*dz-z0)/(dr*dz);
        b3 = ((ar+1)*dr-r0)*(z0-(az+0.5)*dz)/(dr*dz);
        b4 = (r0-ar*dr)*(z0-(az+0.5)*dz)/(dr*dz);
        
    }
    az0[n] = a1;
    az0[n+parNum] = a2;
    az0[n+2*parNum] = a3;
    az0[n+3*parNum] = a4;

    bz0[n] = b1;
    bz0[n+parNum] = b2;
    bz0[n+2*parNum] = b3;
    bz0[n+3*parNum] = b4;
}


__global__ void processMandelbrotElement( 
                     double *r,
                     double *z,
                     double * ar0,
                     double * br0,
                     double * az0,
                     double * bz0,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz ) {
        EM1(r, z, ar0, br0, az0, bz0, parNum, gridR, gridZ, dr, dz);
}

	.file	"tmpxft_003300e8_00000000-6_EM5.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3EM1PdS_S_S_S_S_iiidd
	.type	_Z3EM1PdS_S_S_S_S_iiidd, @function
_Z3EM1PdS_S_S_S_S_iiidd:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z3EM1PdS_S_S_S_S_iiidd, .-_Z3EM1PdS_S_S_S_S_iiidd
	.globl	_Z59__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_iiiddPdS_S_S_S_S_iiidd
	.type	_Z59__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_iiiddPdS_S_S_S_S_iiidd, @function
_Z59__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_iiiddPdS_S_S_S_S_iiidd:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movsd	%xmm0, 8(%rsp)
	movsd	%xmm1, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L4:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z59__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_iiiddPdS_S_S_S_S_iiidd, .-_Z59__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_iiiddPdS_S_S_S_S_iiidd
	.globl	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.type	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd, @function
_Z24processMandelbrotElementPdS_S_S_S_S_iiidd:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_iiiddPdS_S_S_S_S_iiidd
	.cfi_endproc
.LFE2034:
	.size	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd, .-_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24processMandelbrotElementPdS_S_S_S_S_iiidd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//nvcc -ptx EM5.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double *r,
                     double *z,
                     double * ar0,
                     double * br0,
                     double * az0,
                     double * bz0,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz ) {
    int globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
    int localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
    int threadsPerBlock = blockDim.x*blockDim.y;
    int n = localThreadIdx + globalBlockIndex*threadsPerBlock;
    if ( n >= parNum ){
        return;
    }
    double r0 = r[n];
    double z0 = z[n];
    int ar,az,a1,a2,a3,a4;
    double b1,b2,b3,b4;
    // Er
    ar = floor(r0/dr-0.5);
    az = floor(z0/dz);
    a1 = ar + az * gridR + 1;
    a2 = (ar+1) + az * gridR + 1;
    a3 = ar + (az+1) * gridR + 1;
    a4 = (ar+1) + (az+1) * gridR + 1;
    if( ar<0 ){
        b1 = 0;
        b2 = (az*dz+dz-z0)/dz;
        b3 = 0;
        b4 = (z0-az*dz)/dz;
        a1 = 1;
        a3 = 1;
    }
    else if( ar >= gridR-1 ){
        b1 = (az*dz+dz-z0)/dz;
        b2 = 0;
        b3 = (z0-az*dz)/dz;
        b4 = 0;
        a2 = 1;
        a4 = 1;
    }
    else{
        b1 = ((ar+1.5)*dr-r0)*((az+1)*dz-z0)/(dr*dz);
        b2 = (r0-(ar+0.5)*dr)*((az+1)*dz-z0)/(dr*dz);
        b3 = ((ar+1.5)*dr-r0)*(z0-az*dz)/(dr*dz);
        b4 = (r0-(ar+0.5)*dr)*(z0-az*dz)/(dr*dz);    
    }
    ar0[n] = a1;
    ar0[n+parNum] = a2;
    ar0[n+2*parNum] = a3;
    ar0[n+3*parNum] = a4;

    br0[n] = b1;
    br0[n+parNum] = b2;
    br0[n+2*parNum] = b3;
    br0[n+3*parNum] = b4;
    // Ez
    ar = floor(r0/dr);
    az = floor(z0/dz-0.5);
    a1 = ar + az * (gridR+1) + 1;
    a2 = (ar+1) + az * (gridR+1) + 1;
    a3 = ar + (az+1) * (gridR+1) + 1;
    a4 = (ar+1) + (az+1) * (gridR+1) + 1;
    if( az<0 ){
        b1 = 0;
        b2 = 0;
        b3 = (ar*dr+dr-r0)/dr;
        b4 = (r0-ar*dr)/dr;
        a1 = 1;
        a2 = 1;
    }
    else if( az >= gridZ-1 ){
        b1 = (ar*dr+dr-r0)/dr;
        b2 = (r0-ar*dr)/dr;
        b3 = 0;
        b4 = 0;
        a3 = 1;
        a4 = 1;
    }
    else{
        b1 = ((ar+1)*dr-r0)*((az+1.5)*dz-z0)/(dr*dz);
        b2 = (r0-ar*dr)*((az+1.5)*dz-z0)/(dr*dz);
        b3 = ((ar+1)*dr-r0)*(z0-(az+0.5)*dz)/(dr*dz);
        b4 = (r0-ar*dr)*(z0-(az+0.5)*dz)/(dr*dz);
        
    }
    az0[n] = a1;
    az0[n+parNum] = a2;
    az0[n+2*parNum] = a3;
    az0[n+3*parNum] = a4;

    bz0[n] = b1;
    bz0[n+parNum] = b2;
    bz0[n+2*parNum] = b3;
    bz0[n+3*parNum] = b4;
}


__global__ void processMandelbrotElement( 
                     double *r,
                     double *z,
                     double * ar0,
                     double * br0,
                     double * az0,
                     double * bz0,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz ) {
        EM1(r, z, ar0, br0, az0, bz0, parNum, gridR, gridZ, dr, dz);
}

	.text
	.file	"EM5.hip"
	.globl	_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd # -- Begin function _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd
	.type	_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd,@function
_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd: # @_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	24(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	16(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r9, 72(%rbx)
	movq	%r10, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24processMandelbrotElementPdS_S_S_S_S_iiidd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd, .Lfunc_end0-_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24processMandelbrotElementPdS_S_S_S_S_iiidd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd,@object # @_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.section	.rodata,"a",@progbits
	.globl	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.p2align	3, 0x0
_Z24processMandelbrotElementPdS_S_S_S_S_iiidd:
	.quad	_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd
	.size	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24processMandelbrotElementPdS_S_S_S_S_iiidd"
	.size	.L__unnamed_1, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_iiidd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd ; -- Begin function _Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.globl	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
	.p2align	8
	.type	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd,@function
_Z24processMandelbrotElementPdS_S_S_S_S_iiidd: ; @_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x50
	s_load_b32 s5, s[0:1], 0x5c
	s_add_u32 s2, s0, 0x50
	s_addc_u32 s3, s1, 0
	s_load_b128 s[16:19], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s4, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s6, s14
	s_cmp_lt_u32 s14, s4
	s_cselect_b32 s4, 12, 18
	v_mov_b32_e32 v1, s4
	global_load_u16 v4, v1, s[2:3]
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_lshr_b32 s2, s5, 16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s6, s2, v[1:2]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, v4, v[0:1]
	v_cmpx_gt_i32_e64 s16, v6
	s_cbranch_execz .LBB0_18
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v7, 31, v6
	s_load_b128 s[12:15], s[0:1], 0x40
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x20
	global_load_b64 v[2:3], v[2:3], off
	s_mov_b32 s0, exec_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[7:8], null, s[12:13], s[12:13], v[2:3]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[9:10], null, s[14:15], s[14:15], v[4:5]
	v_div_scale_f64 v[19:20], vcc_lo, v[2:3], s[12:13], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[11:12], v[7:8]
	v_rcp_f64_e32 v[13:14], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	v_div_scale_f64 v[15:16], s2, v[4:5], s[14:15], v[4:5]
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[17:18], v[19:20], v[11:12]
	v_mul_f64 v[21:22], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], -v[7:8], v[17:18], v[19:20]
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
	v_fma_f64 v[9:10], -v[9:10], v[21:22], v[15:16]
                                        ; implicit-def: $vgpr15_vgpr16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[17:18]
	s_mov_b32 vcc_lo, s2
                                        ; implicit-def: $vgpr17_vgpr18
	v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[7:8], v[7:8], s[12:13], v[2:3]
	v_div_fixup_f64 v[9:10], v[9:10], s[14:15], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[7:8], -0.5
	v_floor_f64_e32 v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f64_e32 v[11:12], v[11:12]
	v_cvt_i32_f64_e32 v24, v[13:14]
                                        ; implicit-def: $vgpr13_vgpr14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v26, v[11:12]
	v_mul_lo_u32 v27, v24, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, s17, v27
	v_add_nc_u32_e32 v11, 2, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v21, v11, v27
	v_add_nc_u32_e32 v22, v11, v28
                                        ; implicit-def: $vgpr11_vgpr12
	v_cmpx_lt_i32_e32 -1, v26
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.2:
	v_add_nc_u32_e32 v11, 1, v26
	s_add_i32 s0, s17, -1
	s_mov_b32 s2, 1
	v_cmp_le_i32_e32 vcc_lo, s0, v26
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr0_sgpr1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v20, v11, v27
	v_add_nc_u32_e32 v19, v28, v11
                                        ; implicit-def: $vgpr11_vgpr12
	s_and_saveexec_b32 s19, vcc_lo
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_cvt_f64_i32_e32 v[11:12], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[11:12], s[14:15], s[14:15]
	v_fma_f64 v[15:16], -v[11:12], s[14:15], v[4:5]
	v_add_f64 v[13:14], v[13:14], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[17:18], null, s[14:15], s[14:15], v[15:16]
	v_div_scale_f64 v[11:12], null, s[14:15], s[14:15], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[23:24], v[17:18]
	v_div_scale_f64 v[29:30], vcc_lo, v[13:14], s[14:15], v[13:14]
	v_rcp_f64_e32 v[21:22], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	v_fma_f64 v[25:26], -v[11:12], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	v_fma_f64 v[25:26], -v[11:12], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_div_scale_f64 v[25:26], s0, v[15:16], s[14:15], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[29:30], v[21:22]
	v_mul_f64 v[31:32], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], -v[11:12], v[27:28], v[29:30]
	v_fma_f64 v[17:18], -v[17:18], v[31:32], v[25:26]
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[11:12], v[11:12], v[21:22], v[27:28]
	s_mov_b32 vcc_lo, s0
	s_mov_b64 s[0:1], 0
	v_div_fmas_f64 v[17:18], v[17:18], v[23:24], v[31:32]
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[11:12], v[11:12], s[14:15], v[13:14]
	v_div_fixup_f64 v[13:14], v[17:18], s[14:15], v[15:16]
.LBB0_4:                                ; %Flow50
	s_or_saveexec_b32 s19, s19
	v_dual_mov_b32 v23, s2 :: v_dual_mov_b32 v18, s1
	v_dual_mov_b32 v16, s1 :: v_dual_mov_b32 v15, s0
	v_mov_b32_e32 v17, s0
	v_mov_b32_e32 v25, s2
	s_xor_b32 exec_lo, exec_lo, s19
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_cvt_f64_i32_e32 v[11:12], v26
	v_add_nc_u32_e32 v13, 1, v24
	v_cvt_f64_i32_e32 v[17:18], v24
	v_mul_f64 v[23:24], s[12:13], s[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[13:14], v13
	v_add_f64 v[15:16], 0x3ff80000, v[11:12]
	v_add_f64 v[11:12], v[11:12], 0.5
	v_fma_f64 v[17:18], -v[17:18], s[14:15], v[4:5]
	v_fma_f64 v[13:14], v[13:14], s[14:15], -v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[15:16], v[15:16], s[12:13], -v[2:3]
	v_fma_f64 v[11:12], -v[11:12], s[12:13], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[25:26], v[15:16], v[13:14]
	v_mul_f64 v[13:14], v[11:12], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[15:16]
	v_mul_f64 v[27:28], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[11:12], null, v[23:24], v[23:24], v[25:26]
	v_div_scale_f64 v[17:18], null, v[23:24], v[23:24], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[29:30], null, v[23:24], v[23:24], v[15:16]
	v_div_scale_f64 v[31:32], null, v[23:24], v[23:24], v[27:28]
	v_div_scale_f64 v[49:50], vcc_lo, v[25:26], v[23:24], v[25:26]
	v_rcp_f64_e32 v[33:34], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[35:36], v[17:18]
	v_rcp_f64_e32 v[37:38], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[39:40], v[31:32]
	v_fma_f64 v[41:42], -v[11:12], v[33:34], 1.0
	v_fma_f64 v[43:44], -v[17:18], v[35:36], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[45:46], -v[29:30], v[37:38], 1.0
	v_fma_f64 v[47:48], -v[31:32], v[39:40], 1.0
	v_fma_f64 v[33:34], v[33:34], v[41:42], v[33:34]
	v_fma_f64 v[35:36], v[35:36], v[43:44], v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[37:38], v[37:38], v[45:46], v[37:38]
	v_fma_f64 v[39:40], v[39:40], v[47:48], v[39:40]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[41:42], -v[11:12], v[33:34], 1.0
	v_fma_f64 v[43:44], -v[17:18], v[35:36], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[45:46], -v[29:30], v[37:38], 1.0
	v_fma_f64 v[47:48], -v[31:32], v[39:40], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[33:34], v[33:34], v[41:42], v[33:34]
	v_div_scale_f64 v[41:42], s0, v[13:14], v[23:24], v[13:14]
	v_fma_f64 v[35:36], v[35:36], v[43:44], v[35:36]
	v_div_scale_f64 v[43:44], s1, v[15:16], v[23:24], v[15:16]
	v_fma_f64 v[37:38], v[37:38], v[45:46], v[37:38]
	v_div_scale_f64 v[45:46], s2, v[27:28], v[23:24], v[27:28]
	v_fma_f64 v[39:40], v[39:40], v[47:48], v[39:40]
	v_mul_f64 v[47:48], v[49:50], v[33:34]
	v_mul_f64 v[51:52], v[41:42], v[35:36]
	v_mul_f64 v[53:54], v[43:44], v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[55:56], v[45:46], v[39:40]
	v_fma_f64 v[11:12], -v[11:12], v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], -v[17:18], v[51:52], v[41:42]
	v_fma_f64 v[29:30], -v[29:30], v[53:54], v[43:44]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], -v[31:32], v[55:56], v[45:46]
	v_div_fmas_f64 v[11:12], v[11:12], v[33:34], v[47:48]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[17:18], v[17:18], v[35:36], v[51:52]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[29:30], v[29:30], v[37:38], v[53:54]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[31:32], v[31:32], v[39:40], v[55:56]
	v_div_fixup_f64 v[11:12], v[11:12], v[23:24], v[25:26]
	v_mov_b32_e32 v25, v21
	v_div_fixup_f64 v[17:18], v[17:18], v[23:24], v[13:14]
	v_div_fixup_f64 v[13:14], v[29:30], v[23:24], v[15:16]
	v_div_fixup_f64 v[15:16], v[31:32], v[23:24], v[27:28]
	v_mov_b32_e32 v23, v22
.LBB0_6:                                ; %Flow51
	s_or_b32 exec_lo, exec_lo, s19
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
.LBB0_7:                                ; %Flow52
	s_and_not1_saveexec_b32 s1, s3
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_cvt_f64_i32_e32 v[11:12], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[11:12], s[14:15], s[14:15]
	v_fma_f64 v[11:12], -v[11:12], s[14:15], v[4:5]
	v_add_f64 v[13:14], v[13:14], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[17:18], null, s[14:15], s[14:15], v[11:12]
	v_div_scale_f64 v[15:16], null, s[14:15], s[14:15], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[23:24], v[17:18]
	v_div_scale_f64 v[29:30], vcc_lo, v[13:14], s[14:15], v[13:14]
	v_rcp_f64_e32 v[19:20], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	v_fma_f64 v[25:26], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	v_fma_f64 v[25:26], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
	v_div_scale_f64 v[25:26], s0, v[11:12], s[14:15], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[29:30], v[19:20]
	v_mul_f64 v[31:32], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], -v[15:16], v[27:28], v[29:30]
	v_fma_f64 v[17:18], -v[17:18], v[31:32], v[25:26]
	v_mov_b32_e32 v25, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[27:28]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[19:20], v[17:18], v[23:24], v[31:32]
	v_mov_b32_e32 v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[17:18], v[15:16], s[14:15], v[13:14]
	v_div_fixup_f64 v[15:16], v[19:20], s[14:15], v[11:12]
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v20, 1
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v19, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_f64 v[9:10], v[9:10], -0.5
	v_floor_f64_e32 v[7:8], v[7:8]
	v_cvt_f64_i32_e32 v[20:21], v20
	v_cvt_f64_i32_e32 v[30:31], v25
	v_cvt_f64_i32_e32 v[32:33], v19
	v_cvt_f64_i32_e32 v[34:35], v23
	v_add3_u32 v6, s16, s16, v6
	v_add_co_u32 v28, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v1, vcc_lo
	s_ashr_i32 s1, s16, 31
	s_mov_b32 s0, s16
	v_add_nc_u32_e32 v25, s16, v6
	v_add_co_u32 v36, vcc_lo, s10, v0
	s_lshl_b64 s[20:21], s[0:1], 3
	v_add_co_ci_u32_e32 v37, vcc_lo, s11, v1, vcc_lo
	s_add_i32 s2, s17, 1
	v_add_co_u32 v38, vcc_lo, v28, s20
	v_ashrrev_i32_e32 v26, 31, v25
	v_add_co_ci_u32_e32 v39, vcc_lo, s21, v29, vcc_lo
	v_add_co_u32 v40, vcc_lo, v36, s20
	v_add_co_ci_u32_e32 v41, vcc_lo, s21, v37, vcc_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr19
	s_mov_b32 s0, exec_lo
	v_floor_f64_e32 v[9:10], v[9:10]
	v_cvt_i32_f64_e32 v22, v[7:8]
	v_ashrrev_i32_e32 v7, 31, v6
	global_store_b64 v[28:29], v[20:21], off
	v_cvt_i32_f64_e32 v24, v[9:10]
	v_lshlrev_b64 v[8:9], 3, v[6:7]
	v_lshlrev_b64 v[6:7], 3, v[25:26]
	v_add_nc_u32_e32 v26, 1, v22
	v_add_nc_u32_e32 v28, 2, v22
                                        ; implicit-def: $vgpr25
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v42, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v43, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v44, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v45, vcc_lo, s11, v9, vcc_lo
	v_add_co_u32 v46, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v47, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v48, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v49, vcc_lo, s11, v7, vcc_lo
	s_clause 0x2
	global_store_b64 v[38:39], v[30:31], off
	global_store_b64 v[42:43], v[32:33], off
	global_store_b64 v[46:47], v[34:35], off
	s_clause 0x3
	global_store_b64 v[36:37], v[11:12], off
	global_store_b64 v[40:41], v[17:18], off
	global_store_b64 v[44:45], v[13:14], off
	global_store_b64 v[48:49], v[15:16], off
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr18
	v_mul_lo_u32 v27, s2, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, s2, v27
	v_add_nc_u32_e32 v20, v10, v26
	v_add_nc_u32_e32 v21, v10, v28
                                        ; implicit-def: $vgpr10_vgpr11
	v_cmpx_lt_i32_e32 -1, v24
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_15
; %bb.10:
	s_add_i32 s0, s18, -1
	v_add_nc_u32_e32 v19, v27, v26
	v_add_nc_u32_e32 v18, v27, v28
	v_cmp_le_i32_e32 vcc_lo, s0, v24
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr9
	s_and_saveexec_b32 s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_cvt_f64_i32_e32 v[4:5], v22
	s_mov_b32 s9, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[4:5], s[12:13], s[12:13]
	v_add_f64 v[10:11], v[10:11], -v[2:3]
	v_fma_f64 v[2:3], -v[4:5], s[12:13], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[12:13], s[12:13], v[10:11]
	v_div_scale_f64 v[12:13], null, s[12:13], s[12:13], v[2:3]
	v_div_scale_f64 v[24:25], vcc_lo, v[10:11], s[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[4:5]
	v_rcp_f64_e32 v[16:17], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[4:5], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], -v[4:5], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_div_scale_f64 v[20:21], s0, v[2:3], s[12:13], v[2:3]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[24:25], v[14:15]
	v_mul_f64 v[26:27], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], v[22:23], v[24:25]
                                        ; implicit-def: $vgpr24
	v_fma_f64 v[12:13], -v[12:13], v[26:27], v[20:21]
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[4:5], v[4:5], v[14:15], v[22:23]
	s_mov_b32 vcc_lo, s0
	s_mov_b64 s[0:1], 0
	v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[26:27]
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[10:11], v[4:5], s[12:13], v[10:11]
                                        ; implicit-def: $vgpr4_vgpr5
	v_div_fixup_f64 v[12:13], v[12:13], s[12:13], v[2:3]
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_12:                               ; %Flow
	s_or_saveexec_b32 s8, s2
	v_mov_b32_e32 v17, s1
	v_dual_mov_b32 v15, s1 :: v_dual_mov_b32 v14, s0
	v_dual_mov_b32 v23, s9 :: v_dual_mov_b32 v16, s0
	v_mov_b32_e32 v25, s9
	s_xor_b32 exec_lo, exec_lo, s8
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_cvt_f64_i32_e32 v[10:11], v24
	v_cvt_f64_i32_e32 v[12:13], v26
	v_cvt_f64_i32_e32 v[16:17], v22
	v_mul_f64 v[22:23], s[12:13], s[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], 0x3ff80000, v[10:11]
	v_add_f64 v[10:11], v[10:11], 0.5
	v_fma_f64 v[12:13], v[12:13], s[12:13], -v[2:3]
	v_fma_f64 v[2:3], -v[16:17], s[12:13], v[2:3]
	v_fma_f64 v[14:15], v[14:15], s[14:15], -v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[10:11], s[14:15], v[4:5]
	v_mul_f64 v[10:11], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[2:3], v[14:15]
	v_mul_f64 v[16:17], v[12:13], v[4:5]
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[4:5], null, v[22:23], v[22:23], v[10:11]
	v_div_scale_f64 v[12:13], null, v[22:23], v[22:23], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], v[16:17]
	v_div_scale_f64 v[26:27], null, v[22:23], v[22:23], v[2:3]
	v_div_scale_f64 v[44:45], vcc_lo, v[10:11], v[22:23], v[10:11]
	v_rcp_f64_e32 v[28:29], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[12:13]
	v_rcp_f64_e32 v[32:33], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[26:27]
	v_fma_f64 v[36:37], -v[4:5], v[28:29], 1.0
	v_fma_f64 v[38:39], -v[12:13], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[24:25], v[32:33], 1.0
	v_fma_f64 v[42:43], -v[26:27], v[34:35], 1.0
	v_fma_f64 v[28:29], v[28:29], v[36:37], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[38:39], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[32:33], v[32:33], v[40:41], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[42:43], v[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[4:5], v[28:29], 1.0
	v_fma_f64 v[38:39], -v[12:13], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], -v[24:25], v[32:33], 1.0
	v_fma_f64 v[42:43], -v[26:27], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[28:29], v[28:29], v[36:37], v[28:29]
	v_div_scale_f64 v[36:37], s0, v[14:15], v[22:23], v[14:15]
	v_fma_f64 v[30:31], v[30:31], v[38:39], v[30:31]
	v_div_scale_f64 v[38:39], s1, v[16:17], v[22:23], v[16:17]
	v_fma_f64 v[32:33], v[32:33], v[40:41], v[32:33]
	v_div_scale_f64 v[40:41], s2, v[2:3], v[22:23], v[2:3]
	v_fma_f64 v[34:35], v[34:35], v[42:43], v[34:35]
	v_mul_f64 v[42:43], v[44:45], v[28:29]
	v_mul_f64 v[46:47], v[36:37], v[30:31]
	v_mul_f64 v[48:49], v[38:39], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[50:51], v[40:41], v[34:35]
	v_fma_f64 v[4:5], -v[4:5], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[12:13], -v[12:13], v[46:47], v[36:37]
	v_fma_f64 v[24:25], -v[24:25], v[48:49], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], -v[26:27], v[50:51], v[40:41]
	v_div_fmas_f64 v[4:5], v[4:5], v[28:29], v[42:43]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[12:13], v[12:13], v[30:31], v[46:47]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[48:49]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[26:27], v[26:27], v[34:35], v[50:51]
	v_div_fixup_f64 v[10:11], v[4:5], v[22:23], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[12:13], v[12:13], v[22:23], v[14:15]
	v_div_fixup_f64 v[16:17], v[24:25], v[22:23], v[16:17]
	v_mov_b32_e32 v25, v20
	v_div_fixup_f64 v[14:15], v[26:27], v[22:23], v[2:3]
	v_mov_b32_e32 v23, v21
.LBB0_14:                               ; %Flow48
	s_or_b32 exec_lo, exec_lo, s8
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
.LBB0_15:                               ; %Flow49
	s_and_not1_saveexec_b32 s1, s3
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_cvt_f64_i32_e32 v[4:5], v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[4:5], s[12:13], s[12:13]
	v_add_f64 v[10:11], v[10:11], -v[2:3]
	v_fma_f64 v[2:3], -v[4:5], s[12:13], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[12:13], s[12:13], v[10:11]
	v_div_scale_f64 v[12:13], null, s[12:13], s[12:13], v[2:3]
	v_div_scale_f64 v[24:25], vcc_lo, v[10:11], s[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[4:5]
	v_rcp_f64_e32 v[16:17], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[4:5], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], -v[4:5], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_div_scale_f64 v[18:19], s0, v[2:3], s[12:13], v[2:3]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[24:25], v[14:15]
	v_mul_f64 v[26:27], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], v[22:23], v[24:25]
	v_fma_f64 v[12:13], -v[12:13], v[26:27], v[18:19]
	v_dual_mov_b32 v19, 1 :: v_dual_mov_b32 v18, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[4:5], v[4:5], v[14:15], v[22:23]
	s_mov_b32 vcc_lo, s0
	v_mov_b32_e32 v23, v21
	v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[16:17], v[4:5], s[12:13], v[10:11]
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	v_div_fixup_f64 v[14:15], v[12:13], s[12:13], v[2:3]
	v_mov_b32_e32 v25, v20
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s1
	v_cvt_f64_i32_e32 v[2:3], v19
	v_cvt_f64_i32_e32 v[4:5], v18
	v_cvt_f64_i32_e32 v[18:19], v25
	v_cvt_f64_i32_e32 v[20:21], v23
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v22, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v24, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v26, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v28, vcc_lo, v22, s20
	v_add_co_ci_u32_e32 v29, vcc_lo, s21, v23, vcc_lo
	v_add_co_u32 v30, vcc_lo, v0, s20
	v_add_co_ci_u32_e32 v31, vcc_lo, s21, v1, vcc_lo
	s_clause 0x3
	global_store_b64 v[22:23], v[2:3], off
	global_store_b64 v[28:29], v[4:5], off
	global_store_b64 v[24:25], v[18:19], off
	global_store_b64 v[26:27], v[20:21], off
	s_clause 0x3
	global_store_b64 v[0:1], v[10:11], off
	global_store_b64 v[30:31], v[12:13], off
	global_store_b64 v[8:9], v[16:17], off
	global_store_b64 v[6:7], v[14:15], off
.LBB0_18:                               ; %_Z3EM1PdS_S_S_S_S_iiidd.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24processMandelbrotElementPdS_S_S_S_S_iiidd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 57
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24processMandelbrotElementPdS_S_S_S_S_iiidd, .Lfunc_end0-_Z24processMandelbrotElementPdS_S_S_S_S_iiidd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3340
; NumSgprs: 24
; NumVgprs: 57
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 57
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24processMandelbrotElementPdS_S_S_S_S_iiidd
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z24processMandelbrotElementPdS_S_S_S_S_iiidd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     57
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
