#include "includes.h"
__global__ static void update_inverse_cuda (float *Ainv, float *u, int N, int rowstride, int k)
{
__shared__ float A_k[NMAX], u_shared[NMAX], Ainv_u[NMAX], Ainv_shared[NMAX];
A_k[threadIdx.x] = Ainv[k*rowstride+threadIdx.x];
u_shared[threadIdx.x] = u[threadIdx.x];

// First, compute k'th element of Ainv_u
Ainv_u[threadIdx.x] = u_shared[threadIdx.x] * A_k[threadIdx.x];
__syncthreads();
for (int n=N>>1; n>0; n = n>>1) {
float a;
if (threadIdx.x < n)
a = Ainv_u[2*threadIdx.x] + Ainv_u[2*threadIdx.x+1];
__syncthreads();
Ainv_u[threadIdx.x] = a;
__syncthreads();
}
float prefact = -1.0f/(1.0f + Ainv_u[0]);

for (int row=0; row<N; row++) {
Ainv_shared[threadIdx.x] = Ainv[row*rowstride+threadIdx.x];
__syncthreads();
Ainv_u[threadIdx.x] = u_shared[threadIdx.x] * Ainv_shared[threadIdx.x];
for (int n=N>>1; n>0; n = n>>1) {
float a;
if (threadIdx.x < n)
a = Ainv_u[2*threadIdx.x] + Ainv_u[2*threadIdx.x+1];
__syncthreads();
Ainv_u[threadIdx.x] = a;
__syncthreads();
}
__syncthreads();
// Now Ainv_u[0] has the row'th element of Ainv_u.
Ainv[row*rowstride + threadIdx.x] =
Ainv_shared[threadIdx.x] + prefact*Ainv_u[0]*A_k[threadIdx.x];
}

}
	.file	"tmpxft_002eb40f_00000000-6_update_inverse_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL19update_inverse_cudaPfS_iii, @function
_ZL19update_inverse_cudaPfS_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 4(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movl	%r8d, 12(%rsp)
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZL19update_inverse_cudaPfS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_ZL19update_inverse_cudaPfS_iii, .-_ZL19update_inverse_cudaPfS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19update_inverse_cudaPfS_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZL19update_inverse_cudaPfS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void update_inverse_cuda (float *Ainv, float *u, int N, int rowstride, int k)
{
__shared__ float A_k[NMAX], u_shared[NMAX], Ainv_u[NMAX], Ainv_shared[NMAX];
A_k[threadIdx.x] = Ainv[k*rowstride+threadIdx.x];
u_shared[threadIdx.x] = u[threadIdx.x];

// First, compute k'th element of Ainv_u
Ainv_u[threadIdx.x] = u_shared[threadIdx.x] * A_k[threadIdx.x];
__syncthreads();
for (int n=N>>1; n>0; n = n>>1) {
float a;
if (threadIdx.x < n)
a = Ainv_u[2*threadIdx.x] + Ainv_u[2*threadIdx.x+1];
__syncthreads();
Ainv_u[threadIdx.x] = a;
__syncthreads();
}
float prefact = -1.0f/(1.0f + Ainv_u[0]);

for (int row=0; row<N; row++) {
Ainv_shared[threadIdx.x] = Ainv[row*rowstride+threadIdx.x];
__syncthreads();
Ainv_u[threadIdx.x] = u_shared[threadIdx.x] * Ainv_shared[threadIdx.x];
for (int n=N>>1; n>0; n = n>>1) {
float a;
if (threadIdx.x < n)
a = Ainv_u[2*threadIdx.x] + Ainv_u[2*threadIdx.x+1];
__syncthreads();
Ainv_u[threadIdx.x] = a;
__syncthreads();
}
__syncthreads();
// Now Ainv_u[0] has the row'th element of Ainv_u.
Ainv[row*rowstride + threadIdx.x] =
Ainv_shared[threadIdx.x] + prefact*Ainv_u[0]*A_k[threadIdx.x];
}

}
	.text
	.file	"update_inverse_cuda.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL19update_inverse_cudaPfS_iii,"axG",@progbits,_ZL19update_inverse_cudaPfS_iii,comdat
	.globl	_ZL19update_inverse_cudaPfS_iii ; -- Begin function _ZL19update_inverse_cudaPfS_iii
	.p2align	8
	.type	_ZL19update_inverse_cudaPfS_iii,@function
_ZL19update_inverse_cudaPfS_iii:        ; @_ZL19update_inverse_cudaPfS_iii
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v3, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 0x400, v3
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s6, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v5, v3, s[2:3]
	global_load_b32 v1, v[1:2], off
	s_ashr_i32 s2, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s2, 0
	s_cselect_b32 s3, -1, 0
	s_cmp_lt_i32 s2, 1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v1, v5
	ds_store_b32 v3, v5 offset:1536
	ds_store_2addr_stride64_b32 v3, v1, v2 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v1, v4, v3
	s_mov_b32 s6, s2
                                        ; implicit-def: $vgpr2
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s6, v0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b64 v[5:6], v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v5, v6
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_lshr_b32 s7, s6, 1
	s_cmp_lt_u32 s6, 2
	s_mov_b32 s6, s7
	s_barrier
	buffer_gl0_inv
	ds_store_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_13
; %bb.6:                                ; %.lr.ph40
	v_mov_b32_e32 v5, 0
	s_mov_b32 s6, 0
                                        ; implicit-def: $vgpr10
	ds_load_b32 v1, v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, 1.0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v1, v1, 1.0
	v_div_scale_f32 v8, vcc_lo, 1.0, v1, 1.0
	v_rcp_f32_e32 v6, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v2, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v6
	v_mul_f32_e32 v7, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v2, v7, v8
	v_fmac_f32_e32 v7, v9, v6
	v_add_nc_u32_e32 v9, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v7, v8
	v_div_fmas_f32 v2, v2, v6, v7
	v_add_nc_u32_e32 v6, 0x200, v3
	v_add_nc_u32_e32 v7, 0x600, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v8, v2, v1, 1.0
.LBB0_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	v_mad_u64_u32 v[1:2], null, s6, s5, v[0:1]
	v_mov_b32_e32 v2, v5
	s_mov_b32 s7, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s3
	global_load_b32 v11, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v11
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v7
	ds_load_b32 v12, v3
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v11, v11, v12
	ds_store_b32 v4, v11
	s_cbranch_vccz .LBB0_9
	s_branch .LBB0_12
.LBB0_8:                                ;   in Loop: Header=BB0_9 Depth=2
	s_mov_b32 s7, s8
.LBB0_9:                                ; %.lr.ph35
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_u32_e64 s7, v0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=2
	ds_load_b64 v[10:11], v9
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v10, v10, v11
.LBB0_11:                               ;   in Loop: Header=BB0_9 Depth=2
	s_or_b32 exec_lo, exec_lo, s8
	s_lshr_b32 s8, s7, 1
	s_cmp_lt_u32 s7, 2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_store_b32 v4, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_8
.LBB0_12:                               ; %._crit_edge36
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v5 offset:1024
	ds_load_b32 v12, v3
	ds_load_b32 v13, v6
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s6, s4
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v11, v8, v11
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v11, -v11, v13, v12
	global_store_b32 v[1:2], v11, off
	s_cbranch_scc0 .LBB0_7
.LBB0_13:                               ; %._crit_edge41
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL19update_inverse_cudaPfS_iii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 9
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL19update_inverse_cudaPfS_iii,"axG",@progbits,_ZL19update_inverse_cudaPfS_iii,comdat
.Lfunc_end0:
	.size	_ZL19update_inverse_cudaPfS_iii, .Lfunc_end0-_ZL19update_inverse_cudaPfS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 704
; NumSgprs: 11
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 11
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL19update_inverse_cudaPfS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     11
    .sgpr_spill_count: 0
    .symbol:         _ZL19update_inverse_cudaPfS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
