/*
 * CS 4444
 * Steven Stetzler
 * Homework 5: Matrix-Matrix Multiplication with CUDA
 */

#include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#include <stdlib.h>
#include <iostream>

using namespace std;

// If the specified error code refers to a real error, report it and quit the program
void check_error(cudaError e) { 
    if (e != cudaSuccess) {
        printf("\nCUDA error: %s\n", cudaGetErrorString(e));
        exit(1);
    }
}

// A GPU implementation of matrix multiplication.
// Given three N x N matrices A, B, and C we compute C = A x B
__global__ void matrix_mult_gpu(float* A, float* B, float* C, int N) {
    // Get the row and column of C that this thread should work on
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    
    int k, idx;
    float sum;   
    
    // Ignore threads that would compute values outside of the boundary of the matrix
    if (row < N && col < N) {
        idx = row * N + col;
        sum = 0;
        for (k = 0; k < N; k++) {
            sum += A[row * N + k] * B[k * N + col];
        }
        C[idx] = sum;
    } 
}

// A naive (no cache blocking) CPU implementation of matrix multiplication
// Given three N x N matrices A, B, and C we compute C = A x B
void matrix_mult_cpu(float* A, float* B, float* C, int N) {
    int row, col, k, idx;
    float sum;

    for (row = 0; row < N; row++) {
        for (col = 0; col < N; col++) {
            idx = row * N + col;
            sum = 0;
            for (k = 0; k < N; k++) {
                sum += A[row * N + k] * B[k * N + col];
            }
            C[idx] = sum;
        }
    }
}

// Compare the values in two N x N matrices C and C_CPU
void compareHostAndGpuOutput(float* C, float* C_CPU, int N) {
    int totalElements = N * N;
    int missmatchCount = 0;
    for (int i = 0; i < totalElements; i++) {
        if (fabs(C[i] - C_CPU[i]) > 0.01) {
            missmatchCount++;
            printf("mismatch at index %i: %f\t%f\n", i, C[i], C_CPU[i]);
        }
    }
    if (missmatchCount > 0) {
        printf("Computation is incorrect: outputs do not match in %d indexes\n", missmatchCount);
    } else {
        printf("Computation is correct: CPU and GPU outputs match\n");
    }
}

// Main method
int main(int argc, char** argv) {
    // The problem size N is the dimension of the arrays
    int N = (argc > 1) ? atoi(argv[1]) : 100;
    // Option whether or not to check GPU output against CPU implementation
    // Should not be included for large N, as CPU will be very slow
    int check_cpu = (argc > 2) ? atoi(argv[2]) : 0;
    // Options to specify the thread gridding
    int thread_x = (argc > 3) ? atoi(argv[3]) : 32;
    int thread_y = (argc > 4) ? atoi(argv[4]) : 32;
    // Option to specify the number of trials for run time tests of the GPU
    int n_trials = (argc > 5) ? atoi(argv[5]) : 10;

    // Compute block gridding from the thread gridding
    // This is the minimum size block gridding given the size of the array and the thread gridding that guarantees that all values
    // in C will be computed
    int grid_x = (int) ceil((double) N / thread_x);
    int grid_y = (int) ceil((double) N / thread_y);

    // Print run parameters
    printf("N = %d\nGrid: %d x %d\nThreads: %d x %d\nTrials: %d\n", N, grid_x, grid_y, thread_x, thread_y, n_trials);

    // Specify block and thread gridding
    dim3 block_per_grid(grid_x, grid_y , 1);
    dim3 thread_per_block(thread_x, thread_y, 1);
    
    // Create and allocate three arrays
    float* A = (float*) malloc(N * N * sizeof(float));
    float* B = (float*) malloc(N * N * sizeof(float));
    float* C = (float*) malloc(N * N * sizeof(float));
    
    // Create pointers for GPU arrays, but do not allocate yet!
    float* A_GPU;
    float* B_GPU;
    float* C_GPU;

    // Perform random initialization of the arrays
    int i, j;
    float val;
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            val = (rand() % 1000) * 0.001;
            A[i * N + j] = val;
            B[i * N + j] = val;
            C[i * N + j] = val;
        }
    }

    clock_t start, end;
    double elapsed;

    // If we want to check against CPU, perform CPU matrix multiplication and time it
    if (check_cpu) {
        start = clock();
        matrix_mult_cpu(A, B, C, N);
        end = clock();
        
        elapsed = (end - start) / (double) CLOCKS_PER_SEC;
        printf("CPU: %.10f seconds\n", elapsed);
    }

    double copy_avg_time = 0;
    double comp_avg_time = 0;

    // For each trial in run time analysis
    for (i = 0 ; i < n_trials; i++) {
        // Time the copy operation
        start = clock();

        // Allocate arrays on GPU
        check_error(cudaMalloc((void **) &A_GPU, N * N * sizeof(float)));
        check_error(cudaMalloc((void **) &B_GPU, N * N * sizeof(float)));
        check_error(cudaMalloc((void **) &C_GPU, N * N * sizeof(float)));
        // Copy in values from A, B, and C
        check_error(cudaMemcpy(A_GPU, A, N * N * sizeof(float), cudaMemcpyHostToDevice));
        check_error(cudaMemcpy(B_GPU, B, N * N * sizeof(float), cudaMemcpyHostToDevice));
        check_error(cudaMemcpy(C_GPU, C, N * N * sizeof(float), cudaMemcpyHostToDevice));

        end = clock();

        elapsed = (end - start) / (double) CLOCKS_PER_SEC;
        copy_avg_time += elapsed; 
       
        // Time the computation operation 
        start = clock();
        
        // Perform GPU matrix multiply
        matrix_mult_gpu<<<block_per_grid, thread_per_block>>>(A_GPU, B_GPU, C_GPU, N);
        cudaDeviceSynchronize();
        
        end = clock();

        elapsed = (end - start) / (double) CLOCKS_PER_SEC;
        comp_avg_time += elapsed; 
        
        // Free arrays if this isn't our last trial
        if (i != n_trials - 1) {
            check_error(cudaFree(A_GPU));
            check_error(cudaFree(B_GPU));
            check_error(cudaFree(C_GPU));
        }
    }

    // Print timing results    
    printf("GPU_copy: %.10f seconds\n", copy_avg_time / n_trials);
    printf("GPU: %.10f seconds\n", comp_avg_time / n_trials);

    // If we wanted to check against CPU, do so
    if (check_cpu) {
        // Copy result from GPU
        float* C_GPU_Copy = (float*) malloc(N * N * sizeof(float));
        check_error(cudaMemcpy(C_GPU_Copy, C_GPU, N * N * sizeof(float), cudaMemcpyDeviceToHost));
        // Compare GPU and CPU output
        compareHostAndGpuOutput(C, C_GPU_Copy, N);
    }

    return 0;
}


	.file	"tmpxft_0036d998_00000000-6_Steven_Stetzler_Matrix_Multiply.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\nCUDA error: %s\n"
	.text
	.globl	_Z11check_error9cudaError
	.type	_Z11check_error9cudaError, @function
_Z11check_error9cudaError:
.LFB3635:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z11check_error9cudaError, .-_Z11check_error9cudaError
	.globl	_Z15matrix_mult_cpuPfS_S_i
	.type	_Z15matrix_mult_cpuPfS_S_i, @function
_Z15matrix_mult_cpuPfS_S_i:
.LFB3636:
	.cfi_startproc
	endbr64
	movq	%rdi, %r10
	xorl	%r9d, %r9d
	movslq	%ecx, %rdi
	movq	%rsi, %r11
	salq	$2, %rdi
	xorl	%esi, %esi
	cmpl	%ecx, %r9d
	jl	.L17
	ret
.L17:
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
.L12:
	xorl	%eax, %eax
	leaq	(%r10,%rsi), %r12
	leaq	(%rdx,%rsi), %rbp
.L11:
	leaq	(%r11,%rax,4), %rbx
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
.L10:
	movss	(%r12,%r8,4), %xmm1
	mulss	(%rbx), %xmm1
	incq	%r8
	addq	%rdi, %rbx
	addss	%xmm1, %xmm0
	cmpl	%r8d, %ecx
	jg	.L10
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpl	%eax, %ecx
	jg	.L11
	incl	%r9d
	addq	%rdi, %rsi
	cmpl	%ecx, %r9d
	jl	.L12
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z15matrix_mult_cpuPfS_S_i, .-_Z15matrix_mult_cpuPfS_S_i
	.section	.rodata.str1.1
.LC4:
	.string	"mismatch at index %i: %f\t%f\n"
.LC5:
	.string	"Computation is incorrect: outputs do not match in %d indexes\n"
.LC6:
	.string	"Computation is correct: CPU and GPU outputs match\n"
	.text
	.globl	_Z23compareHostAndGpuOutputPfS_i
	.type	_Z23compareHostAndGpuOutputPfS_i, @function
_Z23compareHostAndGpuOutputPfS_i:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%edx, %r12d
	imull	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
.L19:
	cmpl	%ebx, %r12d
	jle	.L26
	movss	0(%r13,%rbx,4), %xmm0
	movss	(%r14,%rbx,4), %xmm1
	movaps	%xmm0, %xmm2
	subss	%xmm1, %xmm2
	andps	.LC2(%rip), %xmm2
	cvtss2sd	%xmm2, %xmm2
	comisd	.LC3(%rip), %xmm2
	jbe	.L20
	movl	%ebx, %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	incl	%ebp
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
.L20:
	incq	%rbx
	jmp	.L19
.L26:
	testl	%ebp, %ebp
	jle	.L23
	popq	%rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebp, %edx
	leaq	.LC5(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%r12
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L23:
	.cfi_restore_state
	popq	%rbx
	.cfi_def_cfa_offset 40
	leaq	.LC6(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%r12
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z23compareHostAndGpuOutputPfS_i, .-_Z23compareHostAndGpuOutputPfS_i
	.globl	_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i
	.type	_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15matrix_mult_gpuPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L27:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i
	.globl	_Z15matrix_mult_gpuPfS_S_i
	.type	_Z15matrix_mult_gpuPfS_S_i, @function
_Z15matrix_mult_gpuPfS_S_i:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3664:
	.size	_Z15matrix_mult_gpuPfS_S_i, .-_Z15matrix_mult_gpuPfS_S_i
	.section	.rodata.str1.1
.LC8:
	.string	"N = %d\nGrid: %d x %d\nThreads: %d x %d\nTrials: %d\n"
.LC11:
	.string	"CPU: %.10f seconds\n"
.LC12:
	.string	"GPU_copy: %.10f seconds\n"
.LC13:
	.string	"GPU: %.10f seconds\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jle	.L44
	movq	8(%rsi), %rdi
	movq	%rsi, %r15
	call	atoi@PLT
	cmpl	$2, 8(%rsp)
	movl	%eax, %ebx
	je	.L45
	movq	16(%r15), %rdi
	call	atoi@PLT
	cmpl	$3, 8(%rsp)
	movl	%eax, %r12d
	je	.L46
	movq	24(%r15), %rdi
	call	atoi@PLT
	cmpl	$4, 8(%rsp)
	movl	%eax, %r14d
	je	.L47
	movq	32(%r15), %rdi
	movl	$10, %ebp
	call	atoi@PLT
	cmpl	$5, 8(%rsp)
	movl	%eax, %r13d
	je	.L33
	movq	40(%r15), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
	jmp	.L33
.L44:
	movl	$32, %r13d
	movl	$32, %r14d
	xorl	%r12d, %r12d
	movl	$100, %ebx
	jmp	.L57
.L45:
	movl	$32, %r13d
	movl	$32, %r14d
	xorl	%r12d, %r12d
	jmp	.L57
.L46:
	movl	$32, %r13d
	movl	$32, %r14d
	jmp	.L57
.L47:
	movl	$32, %r13d
.L57:
	movl	$10, %ebp
.L33:
	cvtsi2sdl	%ebx, %xmm1
	cvtsi2sdl	%r14d, %xmm2
	movaps	%xmm1, %xmm0
	movsd	%xmm1, 8(%rsp)
	divsd	%xmm2, %xmm0
	call	ceil@PLT
	movsd	8(%rsp), %xmm1
	cvttsd2sil	%xmm0, %r15d
	cvtsi2sdl	%r13d, %xmm0
	divsd	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	call	ceil@PLT
	pushq	%rbp
	.cfi_def_cfa_offset 184
	movl	%r14d, %r9d
	movl	%r15d, %ecx
	cvttsd2sil	%xmm0, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 192
	movl	%ebx, %edx
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	%r8d, 24(%rsp)
	call	__printf_chk@PLT
	movl	%ebx, %eax
	movl	24(%rsp), %r8d
	movl	%r15d, 96(%rsp)
	imull	%ebx, %eax
	movl	%r14d, 108(%rsp)
	xorl	%r15d, %r15d
	xorl	%r14d, %r14d
	movl	%r8d, 100(%rsp)
	movl	%r13d, 112(%rsp)
	cltq
	movl	$1, 104(%rsp)
	salq	$2, %rax
	movl	$1, 116(%rsp)
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movq	24(%rsp), %rdi
	movq	%rax, 56(%rsp)
	call	malloc@PLT
	movq	24(%rsp), %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rax, 32(%rsp)
	movslq	%ebx, %rax
	salq	$2, %rax
	movq	%rax, 40(%rsp)
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L34:
	cmpl	%ebx, %r14d
	jge	.L58
	movq	24(%rsp), %rax
	leaq	(%rax,%r15), %rsi
.L35:
	movq	%rsi, 32(%rsp)
	call	rand@PLT
	movl	$1000, %edi
	movq	32(%rsp), %rsi
	cltd
	idivl	%edi
	movq	40(%rsp), %rax
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC9(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%r15)
	movq	16(%rsp), %rax
	movss	%xmm0, 0(%r13,%r15)
	movss	%xmm0, (%rax,%r15)
	addq	$4, %r15
	cmpq	%rsi, %r15
	jne	.L35
	incl	%r14d
	jmp	.L34
.L58:
	testl	%r12d, %r12d
	je	.L37
	call	clock@PLT
	movq	40(%rsp), %rdi
	movq	%r13, %rsi
	movl	%ebx, %ecx
	movq	16(%rsp), %rdx
	movq	%rax, %r14
	call	_Z15matrix_mult_cpuPfS_S_i
	call	clock@PLT
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	subq	%r14, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC10(%rip), %xmm0
	call	__printf_chk@PLT
.L37:
	movq	$0x000000000, 32(%rsp)
	xorl	%r14d, %r14d
	movq	$0x000000000, 24(%rsp)
.L38:
	cmpl	%ebp, %r14d
	jge	.L59
	call	clock@PLT
	movq	8(%rsp), %rsi
	leaq	56(%rsp), %rdi
	movq	%rax, %r15
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	call	clock@PLT
	subq	%r15, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC10(%rip), %xmm0
	addsd	24(%rsp), %xmm0
	movsd	%xmm0, 24(%rsp)
	call	clock@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %r15
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebx, %ecx
	movq	56(%rsp), %rdi
	call	_Z40__device_stub__Z15matrix_mult_gpuPfS_S_iPfS_S_i
.L39:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	subq	%r15, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC10(%rip), %xmm0
	leal	-1(%rbp), %eax
	addsd	32(%rsp), %xmm0
	movsd	%xmm0, 32(%rsp)
	cmpl	%r14d, %eax
	je	.L40
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
.L40:
	incl	%r14d
	jmp	.L38
.L59:
	cvtsi2sdl	%ebp, %xmm1
	movsd	24(%rsp), %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	divsd	%xmm1, %xmm0
	movsd	%xmm1, 24(%rsp)
	call	__printf_chk@PLT
	movsd	32(%rsp), %xmm0
	movsd	24(%rsp), %xmm1
	movb	$1, %al
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	testl	%r12d, %r12d
	je	.L42
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	%rax, %rdi
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	16(%rsp), %rdi
	movl	%ebx, %edx
	movq	%rbp, %rsi
	call	_Z23compareHostAndGpuOutputPfS_i
.L42:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.section	.rodata.str1.1
.LC14:
	.string	"_Z15matrix_mult_gpuPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15matrix_mult_gpuPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	1202590843
	.long	1065646817
	.align 8
.LC9:
	.long	-755914244
	.long	1062232653
	.align 8
.LC10:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * CS 4444
 * Steven Stetzler
 * Homework 5: Matrix-Matrix Multiplication with CUDA
 */

#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>

#include <sys/time.h>
#include <stdlib.h>
#include <iostream>

using namespace std;

// If the specified error code refers to a real error, report it and quit the program
void check_error(hipError_t e) { 
    if (e != hipSuccess) {
        printf("\nCUDA error: %s\n", hipGetErrorString(e));
        exit(1);
    }
}

// A GPU implementation of matrix multiplication.
// Given three N x N matrices A, B, and C we compute C = A x B
__global__ void matrix_mult_gpu(float* A, float* B, float* C, int N) {
    // Get the row and column of C that this thread should work on
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    
    int k, idx;
    float sum;   
    
    // Ignore threads that would compute values outside of the boundary of the matrix
    if (row < N && col < N) {
        idx = row * N + col;
        sum = 0;
        for (k = 0; k < N; k++) {
            sum += A[row * N + k] * B[k * N + col];
        }
        C[idx] = sum;
    } 
}

// A naive (no cache blocking) CPU implementation of matrix multiplication
// Given three N x N matrices A, B, and C we compute C = A x B
void matrix_mult_cpu(float* A, float* B, float* C, int N) {
    int row, col, k, idx;
    float sum;

    for (row = 0; row < N; row++) {
        for (col = 0; col < N; col++) {
            idx = row * N + col;
            sum = 0;
            for (k = 0; k < N; k++) {
                sum += A[row * N + k] * B[k * N + col];
            }
            C[idx] = sum;
        }
    }
}

// Compare the values in two N x N matrices C and C_CPU
void compareHostAndGpuOutput(float* C, float* C_CPU, int N) {
    int totalElements = N * N;
    int missmatchCount = 0;
    for (int i = 0; i < totalElements; i++) {
        if (fabs(C[i] - C_CPU[i]) > 0.01) {
            missmatchCount++;
            printf("mismatch at index %i: %f\t%f\n", i, C[i], C_CPU[i]);
        }
    }
    if (missmatchCount > 0) {
        printf("Computation is incorrect: outputs do not match in %d indexes\n", missmatchCount);
    } else {
        printf("Computation is correct: CPU and GPU outputs match\n");
    }
}

// Main method
int main(int argc, char** argv) {
    // The problem size N is the dimension of the arrays
    int N = (argc > 1) ? atoi(argv[1]) : 100;
    // Option whether or not to check GPU output against CPU implementation
    // Should not be included for large N, as CPU will be very slow
    int check_cpu = (argc > 2) ? atoi(argv[2]) : 0;
    // Options to specify the thread gridding
    int thread_x = (argc > 3) ? atoi(argv[3]) : 32;
    int thread_y = (argc > 4) ? atoi(argv[4]) : 32;
    // Option to specify the number of trials for run time tests of the GPU
    int n_trials = (argc > 5) ? atoi(argv[5]) : 10;

    // Compute block gridding from the thread gridding
    // This is the minimum size block gridding given the size of the array and the thread gridding that guarantees that all values
    // in C will be computed
    int grid_x = (int) ceil((double) N / thread_x);
    int grid_y = (int) ceil((double) N / thread_y);

    // Print run parameters
    printf("N = %d\nGrid: %d x %d\nThreads: %d x %d\nTrials: %d\n", N, grid_x, grid_y, thread_x, thread_y, n_trials);

    // Specify block and thread gridding
    dim3 block_per_grid(grid_x, grid_y , 1);
    dim3 thread_per_block(thread_x, thread_y, 1);
    
    // Create and allocate three arrays
    float* A = (float*) malloc(N * N * sizeof(float));
    float* B = (float*) malloc(N * N * sizeof(float));
    float* C = (float*) malloc(N * N * sizeof(float));
    
    // Create pointers for GPU arrays, but do not allocate yet!
    float* A_GPU;
    float* B_GPU;
    float* C_GPU;

    // Perform random initialization of the arrays
    int i, j;
    float val;
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            val = (rand() % 1000) * 0.001;
            A[i * N + j] = val;
            B[i * N + j] = val;
            C[i * N + j] = val;
        }
    }

    clock_t start, end;
    double elapsed;

    // If we want to check against CPU, perform CPU matrix multiplication and time it
    if (check_cpu) {
        start = clock();
        matrix_mult_cpu(A, B, C, N);
        end = clock();
        
        elapsed = (end - start) / (double) CLOCKS_PER_SEC;
        printf("CPU: %.10f seconds\n", elapsed);
    }

    double copy_avg_time = 0;
    double comp_avg_time = 0;

    // For each trial in run time analysis
    for (i = 0 ; i < n_trials; i++) {
        // Time the copy operation
        start = clock();

        // Allocate arrays on GPU
        check_error(hipMalloc((void **) &A_GPU, N * N * sizeof(float)));
        check_error(hipMalloc((void **) &B_GPU, N * N * sizeof(float)));
        check_error(hipMalloc((void **) &C_GPU, N * N * sizeof(float)));
        // Copy in values from A, B, and C
        check_error(hipMemcpy(A_GPU, A, N * N * sizeof(float), hipMemcpyHostToDevice));
        check_error(hipMemcpy(B_GPU, B, N * N * sizeof(float), hipMemcpyHostToDevice));
        check_error(hipMemcpy(C_GPU, C, N * N * sizeof(float), hipMemcpyHostToDevice));

        end = clock();

        elapsed = (end - start) / (double) CLOCKS_PER_SEC;
        copy_avg_time += elapsed; 
       
        // Time the computation operation 
        start = clock();
        
        // Perform GPU matrix multiply
        matrix_mult_gpu<<<block_per_grid, thread_per_block>>>(A_GPU, B_GPU, C_GPU, N);
        hipDeviceSynchronize();
        
        end = clock();

        elapsed = (end - start) / (double) CLOCKS_PER_SEC;
        comp_avg_time += elapsed; 
        
        // Free arrays if this isn't our last trial
        if (i != n_trials - 1) {
            check_error(hipFree(A_GPU));
            check_error(hipFree(B_GPU));
            check_error(hipFree(C_GPU));
        }
    }

    // Print timing results    
    printf("GPU_copy: %.10f seconds\n", copy_avg_time / n_trials);
    printf("GPU: %.10f seconds\n", comp_avg_time / n_trials);

    // If we wanted to check against CPU, do so
    if (check_cpu) {
        // Copy result from GPU
        float* C_GPU_Copy = (float*) malloc(N * N * sizeof(float));
        check_error(hipMemcpy(C_GPU_Copy, C_GPU, N * N * sizeof(float), hipMemcpyDeviceToHost));
        // Compare GPU and CPU output
        compareHostAndGpuOutput(C, C_GPU_Copy, N);
    }

    return 0;
}


	.text
	.file	"Steven_Stetzler_Matrix_Multiply.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z11check_error10hipError_t     # -- Begin function _Z11check_error10hipError_t
	.type	_Z11check_error10hipError_t,@function
_Z11check_error10hipError_t:            # @_Z11check_error10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB0_2
# %bb.1:
	retq
.LBB0_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_error10hipError_t, .Lfunc_end0-_Z11check_error10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__matrix_mult_gpuPfS_S_i # -- Begin function _Z30__device_stub__matrix_mult_gpuPfS_S_i
	.type	_Z30__device_stub__matrix_mult_gpuPfS_S_i,@function
_Z30__device_stub__matrix_mult_gpuPfS_S_i: # @_Z30__device_stub__matrix_mult_gpuPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15matrix_mult_gpuPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__matrix_mult_gpuPfS_S_i, .Lfunc_end1-_Z30__device_stub__matrix_mult_gpuPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z15matrix_mult_cpuPfS_S_i      # -- Begin function _Z15matrix_mult_cpuPfS_S_i
	.type	_Z15matrix_mult_cpuPfS_S_i,@function
_Z15matrix_mult_cpuPfS_S_i:             # @_Z15matrix_mult_cpuPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB2_8
# %bb.1:                                # %.preheader.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB2_2:                                # %.lr.ph30
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_3 Depth 2
                                        #       Child Loop BB2_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB2_3:                                # %.lr.ph
                                        #   Parent Loop BB2_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_4 Depth 3
	xorps	%xmm0, %xmm0
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        #     Parent Loop BB2_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r13,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	incq	%r13
	addq	%r8, %r12
	cmpq	%r13, %rax
	jne	.LBB2_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_3 Depth=2
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB2_3
# %bb.6:                                # %._crit_edge31
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB2_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB2_8:                                # %._crit_edge33
	retq
.Lfunc_end2:
	.size	_Z15matrix_mult_cpuPfS_S_i, .Lfunc_end2-_Z15matrix_mult_cpuPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z23compareHostAndGpuOutputPfS_i
.LCPI3_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI3_1:
	.quad	0x3f847ae147ae147b              # double 0.01
	.text
	.globl	_Z23compareHostAndGpuOutputPfS_i
	.type	_Z23compareHostAndGpuOutputPfS_i,@function
_Z23compareHostAndGpuOutputPfS_i:       # @_Z23compareHostAndGpuOutputPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%edx, %edx
	je	.LBB3_7
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %ebx
	movq	%rsi, %r14
	movq	%rdi, %r15
	imull	%ebx, %ebx
	cmpl	$1, %ebx
	adcl	$0, %ebx
	xorl	%r12d, %r12d
	movaps	.LCPI3_0(%rip), %xmm3           # xmm3 = [NaN,NaN,NaN,NaN]
	movsd	.LCPI3_1(%rip), %xmm4           # xmm4 = mem[0],zero
	xorl	%ebp, %ebp
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r15,%r12,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	(%r14,%r12,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm2
	subss	%xmm1, %xmm2
	andps	%xmm3, %xmm2
	cvtss2sd	%xmm2, %xmm2
	ucomisd	%xmm4, %xmm2
	jbe	.LBB3_4
# %bb.3:                                #   in Loop: Header=BB3_2 Depth=1
	incl	%ebp
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str.1, %edi
	movl	%r12d, %esi
	movb	$2, %al
	callq	printf
	movsd	.LCPI3_1(%rip), %xmm4           # xmm4 = mem[0],zero
	movaps	.LCPI3_0(%rip), %xmm3           # xmm3 = [NaN,NaN,NaN,NaN]
.LBB3_4:                                #   in Loop: Header=BB3_2 Depth=1
	incq	%r12
	cmpq	%r12, %rbx
	jne	.LBB3_2
# %bb.5:                                # %._crit_edge
	testl	%ebp, %ebp
	jle	.LBB3_7
# %bb.6:
	movl	$.L.str.2, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB3_7:                                # %._crit_edge.thread
	.cfi_def_cfa_offset 48
	movl	$.Lstr, %edi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end3:
	.size	_Z23compareHostAndGpuOutputPfS_i, .Lfunc_end3-_Z23compareHostAndGpuOutputPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI4_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$100, %r15d
	movb	$1, %r12b
	movl	$32, %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	cmpl	$2, %edi
	jl	.LBB4_1
# %bb.2:
	movq	%rsi, %r14
	movl	%edi, %ebp
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r15d
	cmpl	$2, %ebp
	je	.LBB4_1
# %bb.3:
	movq	16(%r14), %rdi
	callq	atoi
	testl	%eax, %eax
	sete	%r12b
	cmpl	$4, %ebp
	jb	.LBB4_1
# %bb.4:
	movq	24(%r14), %rdi
	callq	atoi
	movl	%eax, %ebx
	cmpl	$4, %ebp
	je	.LBB4_6
# %bb.5:
	movq	32(%r14), %rdi
	callq	atoi
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	cmpl	$6, %ebp
	jb	.LBB4_6
# %bb.7:
	movq	40(%r14), %rdi
	callq	atoi
	movl	%eax, %r13d
	jmp	.LBB4_8
.LBB4_1:
	movl	$32, %ebp
	movl	$10, %r13d
.LBB4_9:                                # %.thread127
	cvtsi2sd	%r15d, %xmm0
	movsd	%xmm0, 24(%rsp)                 # 8-byte Spill
	cvtsi2sd	%ebp, %xmm1
	divsd	%xmm1, %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %ebx
	movq	32(%rsp), %r14                  # 8-byte Reload
	xorps	%xmm1, %xmm1
	cvtsi2sd	%r14d, %xmm1
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %ecx
	movl	%r13d, (%rsp)
	movl	$.L.str.4, %edi
	movl	%r15d, %esi
	movq	%rbx, 64(%rsp)                  # 8-byte Spill
	movl	%ebx, %edx
	movq	%rcx, 72(%rsp)                  # 8-byte Spill
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%ebp, %r8d
	movl	%r14d, %r9d
	xorl	%eax, %eax
	callq	printf
	movl	%r15d, %ebx
	imull	%ebx, %ebx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	%rbx, 112(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	testl	%r15d, %r15d
	movb	%r12b, 15(%rsp)                 # 1-byte Spill
	movl	%r13d, 52(%rsp)                 # 4-byte Spill
	jle	.LBB4_23
# %bb.10:                               # %.preheader.lr.ph
	movl	%ebp, 104(%rsp)                 # 4-byte Spill
	movl	%r15d, %ebx
	xorl	%r12d, %r12d
	xorl	%eax, %eax
	movl	%r15d, 108(%rsp)                # 4-byte Spill
.LBB4_11:                               # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_12 Depth 2
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%eax, %eax
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbp
	movq	80(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %r14
	movq	40(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %r15
	xorl	%r13d, %r13d
.LBB4_12:                               #   Parent Loop BB4_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movsd	.LCPI4_0(%rip), %xmm1           # xmm1 = mem[0],zero
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$1000, %ecx, %ecx               # imm = 0x3E8
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r15,%r13,4)
	movss	%xmm0, (%r14,%r13,4)
	movss	%xmm0, (%rbp,%r13,4)
	incq	%r13
	cmpq	%r13, %rbx
	jne	.LBB4_12
# %bb.13:                               # %._crit_edge
                                        #   in Loop: Header=BB4_11 Depth=1
	incq	%r12
	movl	108(%rsp), %r15d                # 4-byte Reload
	movq	16(%rsp), %rax                  # 8-byte Reload
	addl	%r15d, %eax
	cmpq	%rbx, %r12
	jne	.LBB4_11
# %bb.14:                               # %._crit_edge133
	movb	15(%rsp), %r12b                 # 1-byte Reload
	testb	%r12b, %r12b
	movl	52(%rsp), %r13d                 # 4-byte Reload
	movq	32(%rsp), %r14                  # 8-byte Reload
	movl	104(%rsp), %ebp                 # 4-byte Reload
	jne	.LBB4_26
# %bb.15:
	callq	clock
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	testl	%r15d, %r15d
	jle	.LBB4_22
# %bb.16:                               # %.preheader.lr.ph.i
	leaq	(,%rbx,4), %rax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB4_17:                               # %.lr.ph30.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_18 Depth 2
                                        #       Child Loop BB4_19 Depth 3
	movl	%ecx, %esi
	movq	40(%rsp), %rdi                  # 8-byte Reload
	leaq	(%rdi,%rsi,4), %rsi
	movq	%rdx, %rdi
	imulq	%rbx, %rdi
	movq	24(%rsp), %r8                   # 8-byte Reload
	leaq	(%r8,%rdi,4), %rdi
	movq	80(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
.LBB4_18:                               # %.lr.ph.i
                                        #   Parent Loop BB4_17 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_19 Depth 3
	xorpd	%xmm0, %xmm0
	movq	%r8, %r10
	xorl	%r11d, %r11d
.LBB4_19:                               #   Parent Loop BB4_17 Depth=1
                                        #     Parent Loop BB4_18 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rsi,%r11), %xmm1              # xmm1 = mem[0],zero,zero,zero
	mulss	(%r10), %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %r11
	addq	%rax, %r10
	cmpq	%r11, %rax
	jne	.LBB4_19
# %bb.20:                               # %._crit_edge.i
                                        #   in Loop: Header=BB4_18 Depth=2
	movss	%xmm0, (%rdi,%r9,4)
	incq	%r9
	addq	$4, %r8
	cmpq	%rbx, %r9
	jne	.LBB4_18
# %bb.21:                               # %._crit_edge31.i
                                        #   in Loop: Header=BB4_17 Depth=1
	incq	%rdx
	addl	%r15d, %ecx
	cmpq	%rbx, %rdx
	jne	.LBB4_17
.LBB4_22:
	movq	16(%rsp), %rbx                  # 8-byte Reload
	jmp	.LBB4_25
.LBB4_23:                               # %._crit_edge133.thread
	testb	%r12b, %r12b
	jne	.LBB4_26
# %bb.24:                               # %.thread
	callq	clock
	movq	%rax, %rbx
.LBB4_25:                               # %_Z15matrix_mult_cpuPfS_S_i.exit
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI4_1(%rip), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
.LBB4_26:
	testl	%r13d, %r13d
	jle	.LBB4_27
# %bb.28:                               # %.lr.ph138
	movl	%ebp, %eax
	movq	72(%rsp), %rbp                  # 8-byte Reload
	shlq	$32, %rbp
	addq	64(%rsp), %rbp                  # 8-byte Folded Reload
	shlq	$32, %r14
	orq	%rax, %r14
	xorpd	%xmm1, %xmm1
	movl	%r13d, %ebx
	xorpd	%xmm0, %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	movq	112(%rsp), %r12                 # 8-byte Reload
.LBB4_29:                               # =>This Inner Loop Header: Depth=1
	movsd	%xmm1, 32(%rsp)                 # 8-byte Spill
	callq	clock
	movq	%rax, %r13
	leaq	96(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	leaq	88(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	leaq	56(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	96(%rsp), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	88(%rsp), %rdi
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	56(%rsp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	callq	clock
	subq	%r13, %rax
	xorps	%xmm1, %xmm1
	cvtsi2sd	%rax, %xmm1
	movsd	.LCPI4_1(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	%xmm0, %xmm1
	movsd	%xmm1, 72(%rsp)                 # 8-byte Spill
	callq	clock
	movq	%rax, %r13
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_31
# %bb.30:                               #   in Loop: Header=BB4_29 Depth=1
	movq	96(%rsp), %rdi
	movq	88(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	%r15d, %ecx
	callq	_Z30__device_stub__matrix_mult_gpuPfS_S_i
.LBB4_31:                               #   in Loop: Header=BB4_29 Depth=1
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r13, %rax
	cvtsi2sd	%rax, %xmm2
	divsd	.LCPI4_1(%rip), %xmm2
	cmpl	$1, %ebx
	je	.LBB4_33
# %bb.32:                               #   in Loop: Header=BB4_29 Depth=1
	movq	96(%rsp), %rdi
	movsd	%xmm2, 64(%rsp)                 # 8-byte Spill
	callq	hipFree
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	88(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	56(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movsd	64(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
.LBB4_33:                               #   in Loop: Header=BB4_29 Depth=1
	movsd	32(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	addsd	72(%rsp), %xmm1                 # 8-byte Folded Reload
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	addsd	%xmm2, %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	decl	%ebx
	jne	.LBB4_29
	jmp	.LBB4_34
.LBB4_27:
	xorpd	%xmm0, %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	xorpd	%xmm1, %xmm1
.LBB4_34:                               # %._crit_edge139
	xorps	%xmm0, %xmm0
	cvtsi2sdl	52(%rsp), %xmm0         # 4-byte Folded Reload
	movsd	%xmm0, 40(%rsp)                 # 8-byte Spill
	divsd	%xmm0, %xmm1
	movl	$.L.str.6, %edi
	movapd	%xmm1, %xmm0
	movb	$1, %al
	callq	printf
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	40(%rsp), %xmm0                 # 8-byte Folded Reload
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	cmpb	$0, 15(%rsp)                    # 1-byte Folded Reload
	jne	.LBB4_36
# %bb.35:
	movq	112(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	56(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rsi
	movl	%r15d, %edx
	callq	_Z23compareHostAndGpuOutputPfS_i
.LBB4_36:
	xorl	%eax, %eax
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_6:
	.cfi_def_cfa_offset 176
	movl	$10, %r13d
.LBB4_8:                                # %.thread127
	movl	%ebx, %ebp
	jmp	.LBB4_9
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15matrix_mult_gpuPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nCUDA error: %s\n"
	.size	.L.str, 17

	.type	_Z15matrix_mult_gpuPfS_S_i,@object # @_Z15matrix_mult_gpuPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15matrix_mult_gpuPfS_S_i
	.p2align	3, 0x0
_Z15matrix_mult_gpuPfS_S_i:
	.quad	_Z30__device_stub__matrix_mult_gpuPfS_S_i
	.size	_Z15matrix_mult_gpuPfS_S_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"mismatch at index %i: %f\t%f\n"
	.size	.L.str.1, 29

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Computation is incorrect: outputs do not match in %d indexes\n"
	.size	.L.str.2, 62

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"N = %d\nGrid: %d x %d\nThreads: %d x %d\nTrials: %d\n"
	.size	.L.str.4, 50

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"CPU: %.10f seconds\n"
	.size	.L.str.5, 20

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"GPU_copy: %.10f seconds\n"
	.size	.L.str.6, 25

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"GPU: %.10f seconds\n"
	.size	.L.str.7, 20

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15matrix_mult_gpuPfS_S_i"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Computation is correct: CPU and GPU outputs match"
	.size	.Lstr, 50

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__matrix_mult_gpuPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15matrix_mult_gpuPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15matrix_mult_gpuPfS_S_i ; -- Begin function _Z15matrix_mult_gpuPfS_S_i
	.globl	_Z15matrix_mult_gpuPfS_S_i
	.p2align	8
	.type	_Z15matrix_mult_gpuPfS_S_i,@function
_Z15matrix_mult_gpuPfS_S_i:             ; @_Z15matrix_mult_gpuPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v2, v0
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_lo_u32 v1, v2, s2
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s3, s2
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s3, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc1 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15matrix_mult_gpuPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15matrix_mult_gpuPfS_S_i, .Lfunc_end0-_Z15matrix_mult_gpuPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15matrix_mult_gpuPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15matrix_mult_gpuPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
