// nvcc backGroundSubtractionWyatt.cu -o temp.exe -lm

#include <math.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>

// size of vector
#define FRAMES 5		// Number of frames
#define PIXELS_PER_FRAME 10	// Number of pixels per frame

#define BLOCK 128  // Size of blocks, best if it is a power of 2.

// Globals
int *BlockOfFrames_CPU, *BlockOfFrames_GPU;
float *MeanFrame_GPU;
float *BlockOfLogNormalFrames_GPU;
float *MeanLogNormalFrame_GPU;
float *MedianLogNormalFrame_GPU;
float *StdvLogNormalFrame_GPU;
int *NewFrame_CPU, *NewFrame_GPU;
int *BlackAndWhiteFrame_CPU, *BlackAndWhiteFrame_GPU;

// These globals can be removed after debugging.
float *BlockOfLogNormalFrames_CPU;
float *MeanFrame_CPU;
float *MeanLogNormalFrame_CPU;
float *MedianLogNormalFrame_CPU;
float *StdvLogNormalFrame_CPU;

dim3 dimBlock, dimGrid;

void AllocateMemory()
{
	// This are the set of frames that will be used to generate the log normal frame
	// and the standard deviation frame
	BlockOfFrames_CPU = (int *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(int));
	cudaMalloc((void**)&BlockOfFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(int));
	cudaMalloc((void**)&BlockOfLogNormalFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(float));  
	
	// Will hold the log normal frame and the standard deviation of the frames minus the log normal
	cudaMalloc((void**)&MeanFrame_GPU,		PIXELS_PER_FRAME*sizeof(float));
	cudaMalloc((void**)&MeanLogNormalFrame_GPU,	PIXELS_PER_FRAME*sizeof(float));
	cudaMalloc((void**)&MedianLogNormalFrame_GPU,	PIXELS_PER_FRAME*sizeof(float));
	cudaMalloc((void**)&StdvLogNormalFrame_GPU,	PIXELS_PER_FRAME*sizeof(float));
	
	NewFrame_CPU 			= (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
	BlackAndWhiteFrame_CPU 		= (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
	cudaMalloc((void**)&NewFrame_GPU,		PIXELS_PER_FRAME*sizeof(int));
	cudaMalloc((void**)&BlackAndWhiteFrame_GPU,	PIXELS_PER_FRAME*sizeof(int));
	
	// These all can be removed latter. I'm just using them for debuging
	BlockOfLogNormalFrames_CPU 	= (float *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(float));
	MeanFrame_CPU 			= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
	MeanLogNormalFrame_CPU 		= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
	MedianLogNormalFrame_CPU 	= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
	StdvLogNormalFrame_CPU 		= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
}
	
void loadPixels()
{
	/*
	However you get 300,000 by 80 pixels loaded in here then CUDA will do the rest.
	This is loading the big vector from 1st 300,000 then from 2nd 300,000 and so on until frame 80.
	It may be faster to load the pixels the other way 80 first pixels then 80 second pixels and so on 300000 times.
	Test it and see.
	I just load (below) some small values to check that everything is working.
	M is the number of frames and N is the number of pixels per frame
	*/
	for(int i = 0; i < FRAMES; i++)
	{
		for(int j = 0; j < PIXELS_PER_FRAME; j++)
		{
			BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = i;
			if(i == 4) BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = 12;
		}
	}
}

void loadNewFrame()
{
	//This is where you will load the image to be processed.
	for(int i = 0; i < PIXELS_PER_FRAME; i++)
	{
		NewFrame_CPU[i] = i*2;
	}
}

void SetUpCudaDevices()
{
	dimBlock.x = BLOCK;
	dimBlock.y = 1;
	dimBlock.z = 1;

	dimGrid.x = ((PIXELS_PER_FRAME - 1)/BLOCK)+1;
	dimGrid.y = 1;
	dimGrid.z = 1;
}

__global__ void creatingMeanPixelFrame(float *meanFrame, int *allFrames, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	if(pixel < pixelsPerFrame)
	{
		double sum = 0.0;
		for(int i = 0; i < frames; i++)
		{
			sum += allFrames[pixel + pixelsPerFrame*i];
		}
		meanFrame[pixel] = sum/(float)frames;
	}
}

__global__ void creatingLogNormalFrames(float *meanFrame, int *allFrames, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int id;
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	if(pixel < pixelsPerFrame)
	{
		for(int i = 0; i < frames; i++)
		{
			//Same screen location (pixel) but moving through frames (i).
			id = pixel + pixelsPerFrame*i;
			
			allFramesLogNormal[id] = (float)allFrames[id] -  meanFrame[pixel];
			allFramesLogNormal[id] = abs(allFramesLogNormal[id]);
			
			//Can't take log of zero so to be safe check and move it off zero.
			if(allFramesLogNormal[id] == 0.0f) 
			{
				allFramesLogNormal[id] = 0.000001f;
			}
			
			allFramesLogNormal[id] = logf(allFramesLogNormal[id]);
			
			//allFramesLogNormal[id] = (float)allFrames[id];  // Remove after debugging.
		}
	}
}

__global__ void creatingMeanLogNormalFrame(float *meanlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	if(pixel < pixelsPerFrame)
	{
		double sum = 0.0;
		for(int i = 0; i < frames; i++)
		{
			sum += allFramesLogNormal[pixel + pixelsPerFrame*i];
		}
		meanlogNormalFrame[pixel] = sum/(float)frames;
	}
}

__global__ void creatingMedianLogNormalFrame(float *medianlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	int used[FRAMES], index, count;
	float median = 0.0;
	float small;
	if(pixel < pixelsPerFrame)
	{
		for(int i = 0; i < frames; i++)
		{
			used[i] = 0;
		}
		if(frames%2 == 0)
		{
			int middle2 = frames/2;
			int middle1 = middle2 - 1;
			index = -1;
			count = 0;
			while(count <= middle2)
			{
				small = 10000000.0f;  //Needs to be a number larger than anything you would get in a log of a pixel.
				for(int i = 0; i < frames; i++)
				{
					if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small && used[i] == 0)
					{
						small = allFramesLogNormal[pixel + pixelsPerFrame*i];
						index = i;
					}
				}
				if(index == -1) printf("\nError no index found\n");
				used[index] = 1;
	
				if(count == middle1 || count == middle2) 
				{	
					median += allFramesLogNormal[pixel + pixelsPerFrame*index];
				}
				
				count++;
			}
			median /=2.0f;
		}
		else
		{
			int middle = frames/2;
			index = -1;
			count = 0;
			while(count <= middle)
			{
				small = 10000000.0f;  //Needs to be a number larger than anything you would get in a log of a pixel.
				for(int i = 0; i < frames; i++)
				{
					if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small)
					{
						if(used[i] == 0)
						{
							small = allFramesLogNormal[pixel + pixelsPerFrame*i];
							index = i;
						}
					}
				}
				if(index == -1) printf("\nError no index found\n");
				used[index] = 1;
				
				if(count == middle) 
				{
					median += allFramesLogNormal[pixel + pixelsPerFrame*index];
				}
				
				count++;
			}
		}
		medianlogNormalFrame[pixel] = median;
	}
}

__global__ void creatingStdvLogNormalFrame(float *stdvLogNormalFrame, float *meanLogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	float temp;
	if(pixel < pixelsPerFrame)
	{
		double sum = 0.0;
		for(int i = 0; i < frames; i++)
		{
			temp = allFramesLogNormal[pixel + pixelsPerFrame*i] - meanLogNormalFrame[pixel];
			sum += temp*temp;
		}
		stdvLogNormalFrame[pixel] = sqrtf((sum)/(float)(frames-1));
	}
}

__global__ void CreateBlackAndWHiteFrame(int *BlackAndWhiteFrame_GPU, int *NewFrame_GPU, float *StdvLogNormalFrame_GPU, float *MeanLogNormalFrame_GPU, int pixelsPerFrame)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	
	float breakPoint = 2.0f; // ************** not sure what this value should be ??????????
	
	if(pixel < pixelsPerFrame)
	{
		float CDF = 0.5f + 0.5f*erff((logf((float)NewFrame_GPU[pixel]) - MeanLogNormalFrame_GPU[pixel])/sqrtf(2.0*StdvLogNormalFrame_GPU[pixel]));
		if(CDF < breakPoint)
		{
			BlackAndWhiteFrame_GPU[pixel] = 0;
		}
		else
		{
			BlackAndWhiteFrame_GPU[pixel] = 1;  //Can remove this if you do a memset before you use the data.
		}
	}
}

void errorCheck(const char *message)
{
	cudaError_t  error;
	error = cudaGetLastError();

	if(error != cudaSuccess)
	{
		printf("\n CUDA ERROR: %s = %s\n", message, cudaGetErrorString(error));
		exit(0);
	}
}

void stats()
{

	cudaMemcpyAsync(BlockOfLogNormalFrames_CPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME*FRAMES*sizeof(float), cudaMemcpyDeviceToHost);
	errorCheck("copy Mean frame down");
	cudaMemcpyAsync(MeanFrame_CPU, MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
	errorCheck("copy Mean frame down");
	cudaMemcpyAsync(MeanLogNormalFrame_CPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
	errorCheck("copy MeanLogNormal frame down");
	cudaMemcpyAsync(MedianLogNormalFrame_CPU, MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
	errorCheck("copy MedianLogNormal frame down");
	cudaMemcpyAsync(StdvLogNormalFrame_CPU, StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
	errorCheck("copy StdvLogNormal frame down");
	
	printf("\n\n");
	printf("frames");
	for(int j = 0; j < FRAMES; j++)
	{
		printf("\n");
		for(int i = 0; i < PIXELS_PER_FRAME; i++)
		{
			printf("%d ", BlockOfFrames_CPU[i + j*PIXELS_PER_FRAME]);
		}
	}
	
	printf("\n\n");
	printf("log normal frames");
	for(int j = 0; j < FRAMES; j++)
	{
		printf("\n");
		for(int i = 0; i < PIXELS_PER_FRAME; i++)
		{
			printf("%f ", BlockOfLogNormalFrames_CPU[i + j*PIXELS_PER_FRAME]);
		}
	}
	
	printf("\n\n");
	for(int i = 0; i < PIXELS_PER_FRAME; i++)
	{
		printf("MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n", i, MeanFrame_CPU[i], i, MeanLogNormalFrame_CPU[i], i, MedianLogNormalFrame_CPU[i], i, StdvLogNormalFrame_CPU[i]);
	}
	
	printf("\n");
	for(int i = 0; i < PIXELS_PER_FRAME; i++)
	{
		printf("NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n", i, NewFrame_CPU[i], i, BlackAndWhiteFrame_CPU[i]);
	}
}

void cleanUp()
{
	free(BlockOfFrames_CPU);
	free(NewFrame_CPU);
	free(BlackAndWhiteFrame_CPU);

	cudaFree(BlockOfFrames_GPU);
	cudaFree(BlockOfLogNormalFrames_GPU);
	cudaFree(MeanFrame_GPU);
	cudaFree(MeanLogNormalFrame_GPU);
	cudaFree(MedianLogNormalFrame_GPU);
	cudaFree(StdvLogNormalFrame_GPU);
	cudaFree(NewFrame_GPU);
	cudaFree(BlackAndWhiteFrame_GPU);
	
	// These can be removed latter. I just used them for debuging.
	free(BlockOfLogNormalFrames_CPU);
	free(MeanFrame_CPU);
	free(MeanLogNormalFrame_CPU);
	free(MedianLogNormalFrame_CPU);
	free(StdvLogNormalFrame_CPU);
}

int main()
{
	AllocateMemory();
	SetUpCudaDevices();
	loadPixels();
	
	cudaMemcpyAsync(BlockOfFrames_GPU, BlockOfFrames_CPU, PIXELS_PER_FRAME*FRAMES*sizeof(int), cudaMemcpyHostToDevice);
	errorCheck("copyFramessUp");
	cudaDeviceSynchronize();
	creatingMeanPixelFrame<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingMeanPixelFrame");
	
	creatingLogNormalFrames<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingLogNormalFrames");
	
	creatingMeanLogNormalFrame<<<dimGrid,dimBlock>>>(MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingMeanLogNormalFrame");
	
	creatingMedianLogNormalFrame<<<dimGrid,dimBlock>>>(MedianLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingMedianLogNormalFrame");
	
	creatingStdvLogNormalFrame<<<dimGrid,dimBlock>>>(StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingStdvLogNormalFrame");
	
	cudaDeviceSynchronize();
	
	loadNewFrame();
	cudaMemcpyAsync(NewFrame_GPU, NewFrame_CPU, PIXELS_PER_FRAME*sizeof(int), cudaMemcpyHostToDevice);
	errorCheck("copy New frame up");
	
	CreateBlackAndWHiteFrame<<<dimGrid,dimBlock>>>(BlackAndWhiteFrame_GPU, NewFrame_GPU, StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME);
	errorCheck("creatingStdvLogNormalFrame");
	cudaMemcpyAsync(BlackAndWhiteFrame_CPU, BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
	errorCheck("copy black and white frame down");
	
	//Do stuff with black and white frame
	
	stats();
	cleanUp();
	printf("\n DONE \n");
}

	.file	"tmpxft_003b5906_00000000-6_backGroundSubtractionWyatt.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14AllocateMemoryv
	.type	_Z14AllocateMemoryv, @function
_Z14AllocateMemoryv:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$200, %edi
	call	malloc@PLT
	movl	$200, %esi
	leaq	BlockOfFrames_GPU(%rip), %rdi
	movq	%rax, BlockOfFrames_CPU(%rip)
	call	cudaMalloc@PLT
	movl	$200, %esi
	leaq	BlockOfLogNormalFrames_GPU(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$40, %esi
	leaq	MeanFrame_GPU(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$40, %esi
	leaq	MeanLogNormalFrame_GPU(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$40, %esi
	leaq	MedianLogNormalFrame_GPU(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$40, %esi
	leaq	StdvLogNormalFrame_GPU(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$40, %edi
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, NewFrame_CPU(%rip)
	call	malloc@PLT
	movl	$40, %esi
	leaq	NewFrame_GPU(%rip), %rdi
	movq	%rax, BlackAndWhiteFrame_CPU(%rip)
	call	cudaMalloc@PLT
	movl	$40, %esi
	leaq	BlackAndWhiteFrame_GPU(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$200, %edi
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, BlockOfLogNormalFrames_CPU(%rip)
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, MeanFrame_CPU(%rip)
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, MeanLogNormalFrame_CPU(%rip)
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, MedianLogNormalFrame_CPU(%rip)
	call	malloc@PLT
	movq	%rax, StdvLogNormalFrame_CPU(%rip)
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z14AllocateMemoryv, .-_Z14AllocateMemoryv
	.globl	_Z10loadPixelsv
	.type	_Z10loadPixelsv, @function
_Z10loadPixelsv:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	BlockOfFrames_CPU(%rip), %rcx
	xorl	%eax, %eax
	movl	$12, %edi
.L5:
	cmpl	$4, %eax
	movl	%edi, %esi
	cmovne	%eax, %esi
	xorl	%edx, %edx
.L6:
	movl	%esi, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$10, %rdx
	jne	.L6
	incl	%eax
	addq	$40, %rcx
	cmpl	$5, %eax
	jne	.L5
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10loadPixelsv, .-_Z10loadPixelsv
	.globl	_Z12loadNewFramev
	.type	_Z12loadNewFramev, @function
_Z12loadNewFramev:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	NewFrame_CPU(%rip), %rdx
	xorl	%eax, %eax
.L11:
	leal	(%rax,%rax), %ecx
	movl	%ecx, (%rdx,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.L11
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z12loadNewFramev, .-_Z12loadNewFramev
	.globl	_Z16SetUpCudaDevicesv
	.type	_Z16SetUpCudaDevicesv, @function
_Z16SetUpCudaDevicesv:
.LFB2030:
	.cfi_startproc
	endbr64
	movl	$1, 8+dimBlock(%rip)
	movl	$33554433, %eax
	movl	$1, 8+dimGrid(%rip)
	salq	$7, %rax
	movq	%rax, dimBlock(%rip)
	subq	$127, %rax
	movq	%rax, dimGrid(%rip)
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z16SetUpCudaDevicesv, .-_Z16SetUpCudaDevicesv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n CUDA ERROR: %s = %s\n"
	.text
	.globl	_Z10errorCheckPKc
	.type	_Z10errorCheckPKc, @function
_Z10errorCheckPKc:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L14
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L14:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z10errorCheckPKc, .-_Z10errorCheckPKc
	.section	.rodata.str1.1
.LC1:
	.string	"copy Mean frame down"
.LC2:
	.string	"copy MeanLogNormal frame down"
.LC3:
	.string	"copy MedianLogNormal frame down"
.LC4:
	.string	"copy StdvLogNormal frame down"
.LC5:
	.string	"\n\n"
.LC6:
	.string	"frames"
.LC7:
	.string	"\n"
.LC8:
	.string	"%d "
.LC9:
	.string	"log normal frames"
.LC10:
	.string	"%f "
.LC11:
	.string	"MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n"
.LC12:
	.string	"NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n"
	.text
	.globl	_Z5statsv
	.type	_Z5statsv, @function
_Z5statsv:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%r8d, %r8d
	movl	$2, %ecx
	movl	$200, %edx
	movq	BlockOfLogNormalFrames_GPU(%rip), %rsi
	movq	BlockOfLogNormalFrames_CPU(%rip), %rdi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	leaq	.LC5(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	leaq	.LC7(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leaq	.LC1(%rip), %rbx
	call	cudaMemcpyAsync@PLT
	movq	%rbx, %rdi
	call	_Z10errorCheckPKc
	movq	MeanFrame_GPU(%rip), %rsi
	xorl	%r8d, %r8d
	movq	MeanFrame_CPU(%rip), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpyAsync@PLT
	movq	%rbx, %rdi
	xorl	%ebx, %ebx
	call	_Z10errorCheckPKc
	movq	MeanLogNormalFrame_GPU(%rip), %rsi
	xorl	%r8d, %r8d
	movq	MeanLogNormalFrame_CPU(%rip), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpyAsync@PLT
	leaq	.LC2(%rip), %rdi
	call	_Z10errorCheckPKc
	movq	MedianLogNormalFrame_GPU(%rip), %rsi
	xorl	%r8d, %r8d
	movq	MedianLogNormalFrame_CPU(%rip), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpyAsync@PLT
	leaq	.LC3(%rip), %rdi
	call	_Z10errorCheckPKc
	movq	StdvLogNormalFrame_GPU(%rip), %rsi
	xorl	%r8d, %r8d
	movq	StdvLogNormalFrame_CPU(%rip), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpyAsync@PLT
	leaq	.LC4(%rip), %rdi
	call	_Z10errorCheckPKc
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %r14
.L18:
	leaq	0(,%rbp,4), %rax
	movq	%r14, %rsi
	movl	$2, %edi
	addq	BlockOfFrames_CPU(%rip), %rax
	movl	(%rax,%rbx), %edx
	incq	%rbp
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$10, %rbp
	jne	.L18
	addq	$40, %rbx
	cmpq	$200, %rbx
	jne	.L19
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %r14
.L21:
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
.L20:
	leaq	0(,%rbp,4), %rax
	movq	%r14, %rsi
	movl	$2, %edi
	addq	BlockOfLogNormalFrames_CPU(%rip), %rax
	cvtss2sd	(%rax,%rbx), %xmm0
	incq	%rbp
	movb	$1, %al
	call	__printf_chk@PLT
	cmpq	$10, %rbp
	jne	.L20
	addq	$40, %rbx
	cmpq	$200, %rbx
	jne	.L21
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	.LC11(%rip), %rbp
.L22:
	movq	MeanFrame_CPU(%rip), %rax
	movl	%ebx, %edx
	movl	%ebx, %r9d
	movl	%ebx, %r8d
	movl	%ebx, %ecx
	movq	%rbp, %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movq	StdvLogNormalFrame_CPU(%rip), %rax
	cvtss2sd	(%rax,%rbx,4), %xmm3
	movq	MedianLogNormalFrame_CPU(%rip), %rax
	cvtss2sd	(%rax,%rbx,4), %xmm2
	movq	MeanLogNormalFrame_CPU(%rip), %rax
	cvtss2sd	(%rax,%rbx,4), %xmm1
	movb	$4, %al
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L22
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	.LC12(%rip), %rbp
.L23:
	movq	NewFrame_CPU(%rip), %rax
	movl	%ebx, %edx
	movl	%ebx, %r8d
	movq	%rbp, %rsi
	movl	$2, %edi
	movl	(%rax,%rbx,4), %ecx
	movq	BlackAndWhiteFrame_CPU(%rip), %rax
	movl	(%rax,%rbx,4), %r9d
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L23
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z5statsv, .-_Z5statsv
	.globl	_Z7cleanUpv
	.type	_Z7cleanUpv, @function
_Z7cleanUpv:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	BlockOfFrames_CPU(%rip), %rdi
	call	free@PLT
	movq	NewFrame_CPU(%rip), %rdi
	call	free@PLT
	movq	BlackAndWhiteFrame_CPU(%rip), %rdi
	call	free@PLT
	movq	BlockOfFrames_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	BlockOfLogNormalFrames_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	MeanFrame_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	MeanLogNormalFrame_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	MedianLogNormalFrame_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	StdvLogNormalFrame_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	NewFrame_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	BlackAndWhiteFrame_GPU(%rip), %rdi
	call	cudaFree@PLT
	movq	BlockOfLogNormalFrames_CPU(%rip), %rdi
	call	free@PLT
	movq	MeanFrame_CPU(%rip), %rdi
	call	free@PLT
	movq	MeanLogNormalFrame_CPU(%rip), %rdi
	call	free@PLT
	movq	MedianLogNormalFrame_CPU(%rip), %rdi
	call	free@PLT
	movq	StdvLogNormalFrame_CPU(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z7cleanUpv, .-_Z7cleanUpv
	.globl	_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
	.type	_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii, @function
_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22creatingMeanPixelFramePfPiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii, .-_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
	.globl	_Z22creatingMeanPixelFramePfPiii
	.type	_Z22creatingMeanPixelFramePfPiii, @function
_Z22creatingMeanPixelFramePfPiii:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
	.cfi_endproc
.LFE2060:
	.size	_Z22creatingMeanPixelFramePfPiii, .-_Z22creatingMeanPixelFramePfPiii
	.globl	_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
	.type	_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii, @function
_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z23creatingLogNormalFramesPfPiS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L38:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii, .-_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
	.globl	_Z23creatingLogNormalFramesPfPiS_ii
	.type	_Z23creatingLogNormalFramesPfPiS_ii, @function
_Z23creatingLogNormalFramesPfPiS_ii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
	.cfi_endproc
.LFE2062:
	.size	_Z23creatingLogNormalFramesPfPiS_ii, .-_Z23creatingLogNormalFramesPfPiS_ii
	.globl	_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
	.type	_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii, @function
_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26creatingMeanLogNormalFramePfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L43:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii, .-_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
	.globl	_Z26creatingMeanLogNormalFramePfS_ii
	.type	_Z26creatingMeanLogNormalFramePfS_ii, @function
_Z26creatingMeanLogNormalFramePfS_ii:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
	.cfi_endproc
.LFE2064:
	.size	_Z26creatingMeanLogNormalFramePfS_ii, .-_Z26creatingMeanLogNormalFramePfS_ii
	.globl	_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
	.type	_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii, @function
_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z28creatingMedianLogNormalFramePfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L48:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii, .-_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
	.globl	_Z28creatingMedianLogNormalFramePfS_ii
	.type	_Z28creatingMedianLogNormalFramePfS_ii, @function
_Z28creatingMedianLogNormalFramePfS_ii:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
	.cfi_endproc
.LFE2066:
	.size	_Z28creatingMedianLogNormalFramePfS_ii, .-_Z28creatingMedianLogNormalFramePfS_ii
	.globl	_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
	.type	_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii, @function
_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L53
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26creatingStdvLogNormalFramePfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L53:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L55
	call	__stack_chk_fail@PLT
.L55:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii, .-_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
	.globl	_Z26creatingStdvLogNormalFramePfS_S_ii
	.type	_Z26creatingStdvLogNormalFramePfS_S_ii, @function
_Z26creatingStdvLogNormalFramePfS_S_ii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2068:
	.size	_Z26creatingStdvLogNormalFramePfS_S_ii, .-_Z26creatingStdvLogNormalFramePfS_S_ii
	.globl	_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
	.type	_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i, @function
_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z24CreateBlackAndWHiteFramePiS_PfS0_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L58:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L60
	call	__stack_chk_fail@PLT
.L60:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i, .-_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
	.globl	_Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.type	_Z24CreateBlackAndWHiteFramePiS_PfS0_i, @function
_Z24CreateBlackAndWHiteFramePiS_PfS0_i:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
	.cfi_endproc
.LFE2070:
	.size	_Z24CreateBlackAndWHiteFramePiS_PfS0_i, .-_Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.section	.rodata.str1.1
.LC13:
	.string	"copyFramessUp"
.LC14:
	.string	"creatingMeanPixelFrame"
.LC15:
	.string	"creatingLogNormalFrames"
.LC16:
	.string	"creatingMeanLogNormalFrame"
.LC17:
	.string	"creatingMedianLogNormalFrame"
.LC18:
	.string	"creatingStdvLogNormalFrame"
.LC19:
	.string	"copy New frame up"
.LC20:
	.string	"copy black and white frame down"
.LC21:
	.string	"\n DONE \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	call	_Z14AllocateMemoryv
	xorl	%r8d, %r8d
	call	_Z16SetUpCudaDevicesv
	call	_Z10loadPixelsv
	movl	$1, %ecx
	movl	$200, %edx
	movq	BlockOfFrames_CPU(%rip), %rsi
	movq	BlockOfFrames_GPU(%rip), %rdi
	call	cudaMemcpyAsync@PLT
	leaq	.LC13(%rip), %rdi
	call	_Z10errorCheckPKc
	call	cudaDeviceSynchronize@PLT
	movl	8+dimBlock(%rip), %ecx
	xorl	%r9d, %r9d
	movq	dimBlock(%rip), %rdx
	movq	dimGrid(%rip), %rdi
	movl	8+dimGrid(%rip), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	movq	BlockOfFrames_GPU(%rip), %rsi
	movl	$5, %ecx
	movl	$10, %edx
	movq	MeanFrame_GPU(%rip), %rdi
	call	_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
.L64:
	leaq	.LC14(%rip), %rdi
	call	_Z10errorCheckPKc
	movl	8+dimBlock(%rip), %ecx
	xorl	%r9d, %r9d
	movq	dimBlock(%rip), %rdx
	movq	dimGrid(%rip), %rdi
	movl	8+dimGrid(%rip), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	movq	BlockOfLogNormalFrames_GPU(%rip), %rdx
	movq	BlockOfFrames_GPU(%rip), %rsi
	movl	$10, %ecx
	movl	$5, %r8d
	movq	MeanFrame_GPU(%rip), %rdi
	call	_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
.L65:
	leaq	.LC15(%rip), %rdi
	call	_Z10errorCheckPKc
	movl	8+dimBlock(%rip), %ecx
	xorl	%r9d, %r9d
	movq	dimBlock(%rip), %rdx
	movq	dimGrid(%rip), %rdi
	movl	8+dimGrid(%rip), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	movq	BlockOfLogNormalFrames_GPU(%rip), %rsi
	movl	$5, %ecx
	movl	$10, %edx
	movq	MeanLogNormalFrame_GPU(%rip), %rdi
	call	_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
.L66:
	leaq	.LC16(%rip), %rdi
	call	_Z10errorCheckPKc
	movl	8+dimBlock(%rip), %ecx
	xorl	%r9d, %r9d
	movq	dimBlock(%rip), %rdx
	movq	dimGrid(%rip), %rdi
	movl	8+dimGrid(%rip), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movq	BlockOfLogNormalFrames_GPU(%rip), %rsi
	movl	$5, %ecx
	movl	$10, %edx
	movq	MedianLogNormalFrame_GPU(%rip), %rdi
	call	_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
.L67:
	leaq	.LC17(%rip), %rdi
	call	_Z10errorCheckPKc
	movl	8+dimBlock(%rip), %ecx
	xorl	%r9d, %r9d
	movq	dimBlock(%rip), %rdx
	movq	dimGrid(%rip), %rdi
	movl	8+dimGrid(%rip), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movq	BlockOfLogNormalFrames_GPU(%rip), %rdx
	movq	MeanLogNormalFrame_GPU(%rip), %rsi
	movl	$10, %ecx
	movl	$5, %r8d
	movq	StdvLogNormalFrame_GPU(%rip), %rdi
	call	_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
.L68:
	leaq	.LC18(%rip), %rbx
	movq	%rbx, %rdi
	call	_Z10errorCheckPKc
	call	cudaDeviceSynchronize@PLT
	xorl	%r8d, %r8d
	call	_Z12loadNewFramev
	movl	$1, %ecx
	movl	$40, %edx
	movq	NewFrame_CPU(%rip), %rsi
	movq	NewFrame_GPU(%rip), %rdi
	call	cudaMemcpyAsync@PLT
	leaq	.LC19(%rip), %rdi
	call	_Z10errorCheckPKc
	movl	8+dimBlock(%rip), %ecx
	xorl	%r9d, %r9d
	movq	dimBlock(%rip), %rdx
	movq	dimGrid(%rip), %rdi
	movl	8+dimGrid(%rip), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	movq	MeanLogNormalFrame_GPU(%rip), %rcx
	movq	StdvLogNormalFrame_GPU(%rip), %rdx
	movl	$10, %r8d
	movq	NewFrame_GPU(%rip), %rsi
	movq	BlackAndWhiteFrame_GPU(%rip), %rdi
	call	_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
.L69:
	movq	%rbx, %rdi
	call	_Z10errorCheckPKc
	movq	BlackAndWhiteFrame_GPU(%rip), %rsi
	xorl	%r8d, %r8d
	movq	BlackAndWhiteFrame_CPU(%rip), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpyAsync@PLT
	leaq	.LC20(%rip), %rdi
	call	_Z10errorCheckPKc
	call	_Z5statsv
	call	_Z7cleanUpv
	leaq	.LC21(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z24CreateBlackAndWHiteFramePiS_PfS0_i"
.LC23:
	.string	"_Z26creatingStdvLogNormalFramePfS_S_ii"
.LC24:
	.string	"_Z28creatingMedianLogNormalFramePfS_ii"
.LC25:
	.string	"_Z26creatingMeanLogNormalFramePfS_ii"
.LC26:
	.string	"_Z23creatingLogNormalFramesPfPiS_ii"
.LC27:
	.string	"_Z22creatingMeanPixelFramePfPiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2072:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24CreateBlackAndWHiteFramePiS_PfS0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26creatingStdvLogNormalFramePfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28creatingMedianLogNormalFramePfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26creatingMeanLogNormalFramePfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23creatingLogNormalFramesPfPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22creatingMeanPixelFramePfPiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2072:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	dimGrid
	.data
	.align 8
	.type	dimGrid, @object
	.size	dimGrid, 12
dimGrid:
	.long	1
	.long	1
	.long	1
	.globl	dimBlock
	.align 8
	.type	dimBlock, @object
	.size	dimBlock, 12
dimBlock:
	.long	1
	.long	1
	.long	1
	.globl	StdvLogNormalFrame_CPU
	.bss
	.align 8
	.type	StdvLogNormalFrame_CPU, @object
	.size	StdvLogNormalFrame_CPU, 8
StdvLogNormalFrame_CPU:
	.zero	8
	.globl	MedianLogNormalFrame_CPU
	.align 8
	.type	MedianLogNormalFrame_CPU, @object
	.size	MedianLogNormalFrame_CPU, 8
MedianLogNormalFrame_CPU:
	.zero	8
	.globl	MeanLogNormalFrame_CPU
	.align 8
	.type	MeanLogNormalFrame_CPU, @object
	.size	MeanLogNormalFrame_CPU, 8
MeanLogNormalFrame_CPU:
	.zero	8
	.globl	MeanFrame_CPU
	.align 8
	.type	MeanFrame_CPU, @object
	.size	MeanFrame_CPU, 8
MeanFrame_CPU:
	.zero	8
	.globl	BlockOfLogNormalFrames_CPU
	.align 8
	.type	BlockOfLogNormalFrames_CPU, @object
	.size	BlockOfLogNormalFrames_CPU, 8
BlockOfLogNormalFrames_CPU:
	.zero	8
	.globl	BlackAndWhiteFrame_GPU
	.align 8
	.type	BlackAndWhiteFrame_GPU, @object
	.size	BlackAndWhiteFrame_GPU, 8
BlackAndWhiteFrame_GPU:
	.zero	8
	.globl	BlackAndWhiteFrame_CPU
	.align 8
	.type	BlackAndWhiteFrame_CPU, @object
	.size	BlackAndWhiteFrame_CPU, 8
BlackAndWhiteFrame_CPU:
	.zero	8
	.globl	NewFrame_GPU
	.align 8
	.type	NewFrame_GPU, @object
	.size	NewFrame_GPU, 8
NewFrame_GPU:
	.zero	8
	.globl	NewFrame_CPU
	.align 8
	.type	NewFrame_CPU, @object
	.size	NewFrame_CPU, 8
NewFrame_CPU:
	.zero	8
	.globl	StdvLogNormalFrame_GPU
	.align 8
	.type	StdvLogNormalFrame_GPU, @object
	.size	StdvLogNormalFrame_GPU, 8
StdvLogNormalFrame_GPU:
	.zero	8
	.globl	MedianLogNormalFrame_GPU
	.align 8
	.type	MedianLogNormalFrame_GPU, @object
	.size	MedianLogNormalFrame_GPU, 8
MedianLogNormalFrame_GPU:
	.zero	8
	.globl	MeanLogNormalFrame_GPU
	.align 8
	.type	MeanLogNormalFrame_GPU, @object
	.size	MeanLogNormalFrame_GPU, 8
MeanLogNormalFrame_GPU:
	.zero	8
	.globl	BlockOfLogNormalFrames_GPU
	.align 8
	.type	BlockOfLogNormalFrames_GPU, @object
	.size	BlockOfLogNormalFrames_GPU, 8
BlockOfLogNormalFrames_GPU:
	.zero	8
	.globl	MeanFrame_GPU
	.align 8
	.type	MeanFrame_GPU, @object
	.size	MeanFrame_GPU, 8
MeanFrame_GPU:
	.zero	8
	.globl	BlockOfFrames_GPU
	.align 8
	.type	BlockOfFrames_GPU, @object
	.size	BlockOfFrames_GPU, 8
BlockOfFrames_GPU:
	.zero	8
	.globl	BlockOfFrames_CPU
	.align 8
	.type	BlockOfFrames_CPU, @object
	.size	BlockOfFrames_CPU, 8
BlockOfFrames_CPU:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// nvcc backGroundSubtractionWyatt.cu -o temp.exe -lm


#include <hip/hip_runtime.h>
#include <math.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>

// size of vector
#define FRAMES 5		// Number of frames
#define PIXELS_PER_FRAME 10	// Number of pixels per frame

#define BLOCK 128  // Size of blocks, best if it is a power of 2.

// Globals
int *BlockOfFrames_CPU, *BlockOfFrames_GPU;
float *MeanFrame_GPU;
float *BlockOfLogNormalFrames_GPU;
float *MeanLogNormalFrame_GPU;
float *MedianLogNormalFrame_GPU;
float *StdvLogNormalFrame_GPU;
int *NewFrame_CPU, *NewFrame_GPU;
int *BlackAndWhiteFrame_CPU, *BlackAndWhiteFrame_GPU;

// These globals can be removed after debugging.
float *BlockOfLogNormalFrames_CPU;
float *MeanFrame_CPU;
float *MeanLogNormalFrame_CPU;
float *MedianLogNormalFrame_CPU;
float *StdvLogNormalFrame_CPU;

dim3 dimBlock, dimGrid;

void AllocateMemory()
{
	// This are the set of frames that will be used to generate the log normal frame
	// and the standard deviation frame
	BlockOfFrames_CPU = (int *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(int));
	hipMalloc((void**)&BlockOfFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(int));
	hipMalloc((void**)&BlockOfLogNormalFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(float));  
	
	// Will hold the log normal frame and the standard deviation of the frames minus the log normal
	hipMalloc((void**)&MeanFrame_GPU,		PIXELS_PER_FRAME*sizeof(float));
	hipMalloc((void**)&MeanLogNormalFrame_GPU,	PIXELS_PER_FRAME*sizeof(float));
	hipMalloc((void**)&MedianLogNormalFrame_GPU,	PIXELS_PER_FRAME*sizeof(float));
	hipMalloc((void**)&StdvLogNormalFrame_GPU,	PIXELS_PER_FRAME*sizeof(float));
	
	NewFrame_CPU 			= (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
	BlackAndWhiteFrame_CPU 		= (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
	hipMalloc((void**)&NewFrame_GPU,		PIXELS_PER_FRAME*sizeof(int));
	hipMalloc((void**)&BlackAndWhiteFrame_GPU,	PIXELS_PER_FRAME*sizeof(int));
	
	// These all can be removed latter. I'm just using them for debuging
	BlockOfLogNormalFrames_CPU 	= (float *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(float));
	MeanFrame_CPU 			= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
	MeanLogNormalFrame_CPU 		= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
	MedianLogNormalFrame_CPU 	= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
	StdvLogNormalFrame_CPU 		= (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
}
	
void loadPixels()
{
	/*
	However you get 300,000 by 80 pixels loaded in here then CUDA will do the rest.
	This is loading the big vector from 1st 300,000 then from 2nd 300,000 and so on until frame 80.
	It may be faster to load the pixels the other way 80 first pixels then 80 second pixels and so on 300000 times.
	Test it and see.
	I just load (below) some small values to check that everything is working.
	M is the number of frames and N is the number of pixels per frame
	*/
	for(int i = 0; i < FRAMES; i++)
	{
		for(int j = 0; j < PIXELS_PER_FRAME; j++)
		{
			BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = i;
			if(i == 4) BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = 12;
		}
	}
}

void loadNewFrame()
{
	//This is where you will load the image to be processed.
	for(int i = 0; i < PIXELS_PER_FRAME; i++)
	{
		NewFrame_CPU[i] = i*2;
	}
}

void SetUpCudaDevices()
{
	dimBlock.x = BLOCK;
	dimBlock.y = 1;
	dimBlock.z = 1;

	dimGrid.x = ((PIXELS_PER_FRAME - 1)/BLOCK)+1;
	dimGrid.y = 1;
	dimGrid.z = 1;
}

__global__ void creatingMeanPixelFrame(float *meanFrame, int *allFrames, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	if(pixel < pixelsPerFrame)
	{
		double sum = 0.0;
		for(int i = 0; i < frames; i++)
		{
			sum += allFrames[pixel + pixelsPerFrame*i];
		}
		meanFrame[pixel] = sum/(float)frames;
	}
}

__global__ void creatingLogNormalFrames(float *meanFrame, int *allFrames, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int id;
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	if(pixel < pixelsPerFrame)
	{
		for(int i = 0; i < frames; i++)
		{
			//Same screen location (pixel) but moving through frames (i).
			id = pixel + pixelsPerFrame*i;
			
			allFramesLogNormal[id] = (float)allFrames[id] -  meanFrame[pixel];
			allFramesLogNormal[id] = abs(allFramesLogNormal[id]);
			
			//Can't take log of zero so to be safe check and move it off zero.
			if(allFramesLogNormal[id] == 0.0f) 
			{
				allFramesLogNormal[id] = 0.000001f;
			}
			
			allFramesLogNormal[id] = logf(allFramesLogNormal[id]);
			
			//allFramesLogNormal[id] = (float)allFrames[id];  // Remove after debugging.
		}
	}
}

__global__ void creatingMeanLogNormalFrame(float *meanlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	if(pixel < pixelsPerFrame)
	{
		double sum = 0.0;
		for(int i = 0; i < frames; i++)
		{
			sum += allFramesLogNormal[pixel + pixelsPerFrame*i];
		}
		meanlogNormalFrame[pixel] = sum/(float)frames;
	}
}

__global__ void creatingMedianLogNormalFrame(float *medianlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	int used[FRAMES], index, count;
	float median = 0.0;
	float small;
	if(pixel < pixelsPerFrame)
	{
		for(int i = 0; i < frames; i++)
		{
			used[i] = 0;
		}
		if(frames%2 == 0)
		{
			int middle2 = frames/2;
			int middle1 = middle2 - 1;
			index = -1;
			count = 0;
			while(count <= middle2)
			{
				small = 10000000.0f;  //Needs to be a number larger than anything you would get in a log of a pixel.
				for(int i = 0; i < frames; i++)
				{
					if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small && used[i] == 0)
					{
						small = allFramesLogNormal[pixel + pixelsPerFrame*i];
						index = i;
					}
				}
				if(index == -1) printf("\nError no index found\n");
				used[index] = 1;
	
				if(count == middle1 || count == middle2) 
				{	
					median += allFramesLogNormal[pixel + pixelsPerFrame*index];
				}
				
				count++;
			}
			median /=2.0f;
		}
		else
		{
			int middle = frames/2;
			index = -1;
			count = 0;
			while(count <= middle)
			{
				small = 10000000.0f;  //Needs to be a number larger than anything you would get in a log of a pixel.
				for(int i = 0; i < frames; i++)
				{
					if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small)
					{
						if(used[i] == 0)
						{
							small = allFramesLogNormal[pixel + pixelsPerFrame*i];
							index = i;
						}
					}
				}
				if(index == -1) printf("\nError no index found\n");
				used[index] = 1;
				
				if(count == middle) 
				{
					median += allFramesLogNormal[pixel + pixelsPerFrame*index];
				}
				
				count++;
			}
		}
		medianlogNormalFrame[pixel] = median;
	}
}

__global__ void creatingStdvLogNormalFrame(float *stdvLogNormalFrame, float *meanLogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	float temp;
	if(pixel < pixelsPerFrame)
	{
		double sum = 0.0;
		for(int i = 0; i < frames; i++)
		{
			temp = allFramesLogNormal[pixel + pixelsPerFrame*i] - meanLogNormalFrame[pixel];
			sum += temp*temp;
		}
		stdvLogNormalFrame[pixel] = sqrtf((sum)/(float)(frames-1));
	}
}

__global__ void CreateBlackAndWHiteFrame(int *BlackAndWhiteFrame_GPU, int *NewFrame_GPU, float *StdvLogNormalFrame_GPU, float *MeanLogNormalFrame_GPU, int pixelsPerFrame)
{
	int pixel = threadIdx.x + blockIdx.x*blockDim.x;
	
	float breakPoint = 2.0f; // ************** not sure what this value should be ??????????
	
	if(pixel < pixelsPerFrame)
	{
		float CDF = 0.5f + 0.5f*erff((logf((float)NewFrame_GPU[pixel]) - MeanLogNormalFrame_GPU[pixel])/sqrtf(2.0*StdvLogNormalFrame_GPU[pixel]));
		if(CDF < breakPoint)
		{
			BlackAndWhiteFrame_GPU[pixel] = 0;
		}
		else
		{
			BlackAndWhiteFrame_GPU[pixel] = 1;  //Can remove this if you do a memset before you use the data.
		}
	}
}

void errorCheck(const char *message)
{
	hipError_t  error;
	error = hipGetLastError();

	if(error != hipSuccess)
	{
		printf("\n CUDA ERROR: %s = %s\n", message, hipGetErrorString(error));
		exit(0);
	}
}

void stats()
{

	hipMemcpyAsync(BlockOfLogNormalFrames_CPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME*FRAMES*sizeof(float), hipMemcpyDeviceToHost);
	errorCheck("copy Mean frame down");
	hipMemcpyAsync(MeanFrame_CPU, MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
	errorCheck("copy Mean frame down");
	hipMemcpyAsync(MeanLogNormalFrame_CPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
	errorCheck("copy MeanLogNormal frame down");
	hipMemcpyAsync(MedianLogNormalFrame_CPU, MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
	errorCheck("copy MedianLogNormal frame down");
	hipMemcpyAsync(StdvLogNormalFrame_CPU, StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
	errorCheck("copy StdvLogNormal frame down");
	
	printf("\n\n");
	printf("frames");
	for(int j = 0; j < FRAMES; j++)
	{
		printf("\n");
		for(int i = 0; i < PIXELS_PER_FRAME; i++)
		{
			printf("%d ", BlockOfFrames_CPU[i + j*PIXELS_PER_FRAME]);
		}
	}
	
	printf("\n\n");
	printf("log normal frames");
	for(int j = 0; j < FRAMES; j++)
	{
		printf("\n");
		for(int i = 0; i < PIXELS_PER_FRAME; i++)
		{
			printf("%f ", BlockOfLogNormalFrames_CPU[i + j*PIXELS_PER_FRAME]);
		}
	}
	
	printf("\n\n");
	for(int i = 0; i < PIXELS_PER_FRAME; i++)
	{
		printf("MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n", i, MeanFrame_CPU[i], i, MeanLogNormalFrame_CPU[i], i, MedianLogNormalFrame_CPU[i], i, StdvLogNormalFrame_CPU[i]);
	}
	
	printf("\n");
	for(int i = 0; i < PIXELS_PER_FRAME; i++)
	{
		printf("NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n", i, NewFrame_CPU[i], i, BlackAndWhiteFrame_CPU[i]);
	}
}

void cleanUp()
{
	free(BlockOfFrames_CPU);
	free(NewFrame_CPU);
	free(BlackAndWhiteFrame_CPU);

	hipFree(BlockOfFrames_GPU);
	hipFree(BlockOfLogNormalFrames_GPU);
	hipFree(MeanFrame_GPU);
	hipFree(MeanLogNormalFrame_GPU);
	hipFree(MedianLogNormalFrame_GPU);
	hipFree(StdvLogNormalFrame_GPU);
	hipFree(NewFrame_GPU);
	hipFree(BlackAndWhiteFrame_GPU);
	
	// These can be removed latter. I just used them for debuging.
	free(BlockOfLogNormalFrames_CPU);
	free(MeanFrame_CPU);
	free(MeanLogNormalFrame_CPU);
	free(MedianLogNormalFrame_CPU);
	free(StdvLogNormalFrame_CPU);
}

int main()
{
	AllocateMemory();
	SetUpCudaDevices();
	loadPixels();
	
	hipMemcpyAsync(BlockOfFrames_GPU, BlockOfFrames_CPU, PIXELS_PER_FRAME*FRAMES*sizeof(int), hipMemcpyHostToDevice);
	errorCheck("copyFramessUp");
	hipDeviceSynchronize();
	creatingMeanPixelFrame<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingMeanPixelFrame");
	
	creatingLogNormalFrames<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingLogNormalFrames");
	
	creatingMeanLogNormalFrame<<<dimGrid,dimBlock>>>(MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingMeanLogNormalFrame");
	
	creatingMedianLogNormalFrame<<<dimGrid,dimBlock>>>(MedianLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingMedianLogNormalFrame");
	
	creatingStdvLogNormalFrame<<<dimGrid,dimBlock>>>(StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
	errorCheck("creatingStdvLogNormalFrame");
	
	hipDeviceSynchronize();
	
	loadNewFrame();
	hipMemcpyAsync(NewFrame_GPU, NewFrame_CPU, PIXELS_PER_FRAME*sizeof(int), hipMemcpyHostToDevice);
	errorCheck("copy New frame up");
	
	CreateBlackAndWHiteFrame<<<dimGrid,dimBlock>>>(BlackAndWhiteFrame_GPU, NewFrame_GPU, StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME);
	errorCheck("creatingStdvLogNormalFrame");
	hipMemcpyAsync(BlackAndWhiteFrame_CPU, BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
	errorCheck("copy black and white frame down");
	
	//Do stuff with black and white frame
	
	stats();
	cleanUp();
	printf("\n DONE \n");
}

	.text
	.file	"backGroundSubtractionWyatt.hip"
	.globl	_Z14AllocateMemoryv             # -- Begin function _Z14AllocateMemoryv
	.type	_Z14AllocateMemoryv,@function
_Z14AllocateMemoryv:                    # @_Z14AllocateMemoryv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$200, %edi
	callq	malloc
	movq	%rax, BlockOfFrames_CPU(%rip)
	movl	$BlockOfFrames_GPU, %edi
	movl	$200, %esi
	callq	hipMalloc
	movl	$BlockOfLogNormalFrames_GPU, %edi
	movl	$200, %esi
	callq	hipMalloc
	movl	$MeanFrame_GPU, %edi
	movl	$40, %esi
	callq	hipMalloc
	movl	$MeanLogNormalFrame_GPU, %edi
	movl	$40, %esi
	callq	hipMalloc
	movl	$MedianLogNormalFrame_GPU, %edi
	movl	$40, %esi
	callq	hipMalloc
	movl	$StdvLogNormalFrame_GPU, %edi
	movl	$40, %esi
	callq	hipMalloc
	movl	$40, %edi
	callq	malloc
	movq	%rax, NewFrame_CPU(%rip)
	movl	$40, %edi
	callq	malloc
	movq	%rax, BlackAndWhiteFrame_CPU(%rip)
	movl	$NewFrame_GPU, %edi
	movl	$40, %esi
	callq	hipMalloc
	movl	$BlackAndWhiteFrame_GPU, %edi
	movl	$40, %esi
	callq	hipMalloc
	movl	$200, %edi
	callq	malloc
	movq	%rax, BlockOfLogNormalFrames_CPU(%rip)
	movl	$40, %edi
	callq	malloc
	movq	%rax, MeanFrame_CPU(%rip)
	movl	$40, %edi
	callq	malloc
	movq	%rax, MeanLogNormalFrame_CPU(%rip)
	movl	$40, %edi
	callq	malloc
	movq	%rax, MedianLogNormalFrame_CPU(%rip)
	movl	$40, %edi
	callq	malloc
	movq	%rax, StdvLogNormalFrame_CPU(%rip)
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z14AllocateMemoryv, .Lfunc_end0-_Z14AllocateMemoryv
	.cfi_endproc
                                        # -- End function
	.globl	_Z10loadPixelsv                 # -- Begin function _Z10loadPixelsv
	.type	_Z10loadPixelsv,@function
_Z10loadPixelsv:                        # @_Z10loadPixelsv
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
	movl	$12, %ecx
	xorl	%edx, %edx
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	cmpq	$4, %rdx
	movl	%edx, %esi
	cmovel	%ecx, %esi
	xorl	%edi, %edi
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	BlockOfFrames_CPU(%rip), %r8
	addq	%rax, %r8
	movl	%esi, (%r8,%rdi,4)
	incq	%rdi
	cmpq	$10, %rdi
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rdx
	addq	$40, %rax
	cmpq	$5, %rdx
	jne	.LBB1_1
# %bb.4:
	retq
.Lfunc_end1:
	.size	_Z10loadPixelsv, .Lfunc_end1-_Z10loadPixelsv
	.cfi_endproc
                                        # -- End function
	.globl	_Z12loadNewFramev               # -- Begin function _Z12loadNewFramev
	.type	_Z12loadNewFramev,@function
_Z12loadNewFramev:                      # @_Z12loadNewFramev
	.cfi_startproc
# %bb.0:
	movq	NewFrame_CPU(%rip), %rax
	xorl	%ecx, %ecx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ecx, (%rax,%rcx,2)
	addq	$2, %rcx
	cmpq	$20, %rcx
	jne	.LBB2_1
# %bb.2:
	retq
.Lfunc_end2:
	.size	_Z12loadNewFramev, .Lfunc_end2-_Z12loadNewFramev
	.cfi_endproc
                                        # -- End function
	.globl	_Z16SetUpCudaDevicesv           # -- Begin function _Z16SetUpCudaDevicesv
	.type	_Z16SetUpCudaDevicesv,@function
_Z16SetUpCudaDevicesv:                  # @_Z16SetUpCudaDevicesv
	.cfi_startproc
# %bb.0:
	movabsq	$4294967424, %rax               # imm = 0x100000080
	movq	%rax, dimBlock(%rip)
	movl	$1, %eax
	movl	%eax, dimBlock+8(%rip)
	movabsq	$4294967297, %rcx               # imm = 0x100000001
	movq	%rcx, dimGrid(%rip)
	movl	%eax, dimGrid+8(%rip)
	retq
.Lfunc_end3:
	.size	_Z16SetUpCudaDevicesv, .Lfunc_end3-_Z16SetUpCudaDevicesv
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__creatingMeanPixelFramePfPiii # -- Begin function _Z37__device_stub__creatingMeanPixelFramePfPiii
	.type	_Z37__device_stub__creatingMeanPixelFramePfPiii,@function
_Z37__device_stub__creatingMeanPixelFramePfPiii: # @_Z37__device_stub__creatingMeanPixelFramePfPiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22creatingMeanPixelFramePfPiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z37__device_stub__creatingMeanPixelFramePfPiii, .Lfunc_end4-_Z37__device_stub__creatingMeanPixelFramePfPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__creatingLogNormalFramesPfPiS_ii # -- Begin function _Z38__device_stub__creatingLogNormalFramesPfPiS_ii
	.type	_Z38__device_stub__creatingLogNormalFramesPfPiS_ii,@function
_Z38__device_stub__creatingLogNormalFramesPfPiS_ii: # @_Z38__device_stub__creatingLogNormalFramesPfPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23creatingLogNormalFramesPfPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z38__device_stub__creatingLogNormalFramesPfPiS_ii, .Lfunc_end5-_Z38__device_stub__creatingLogNormalFramesPfPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__creatingMeanLogNormalFramePfS_ii # -- Begin function _Z41__device_stub__creatingMeanLogNormalFramePfS_ii
	.type	_Z41__device_stub__creatingMeanLogNormalFramePfS_ii,@function
_Z41__device_stub__creatingMeanLogNormalFramePfS_ii: # @_Z41__device_stub__creatingMeanLogNormalFramePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26creatingMeanLogNormalFramePfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z41__device_stub__creatingMeanLogNormalFramePfS_ii, .Lfunc_end6-_Z41__device_stub__creatingMeanLogNormalFramePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__creatingMedianLogNormalFramePfS_ii # -- Begin function _Z43__device_stub__creatingMedianLogNormalFramePfS_ii
	.type	_Z43__device_stub__creatingMedianLogNormalFramePfS_ii,@function
_Z43__device_stub__creatingMedianLogNormalFramePfS_ii: # @_Z43__device_stub__creatingMedianLogNormalFramePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28creatingMedianLogNormalFramePfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z43__device_stub__creatingMedianLogNormalFramePfS_ii, .Lfunc_end7-_Z43__device_stub__creatingMedianLogNormalFramePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii # -- Begin function _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
	.type	_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii,@function
_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii: # @_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26creatingStdvLogNormalFramePfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii, .Lfunc_end8-_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i # -- Begin function _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
	.type	_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i,@function
_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i: # @_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24CreateBlackAndWHiteFramePiS_PfS0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i, .Lfunc_end9-_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z10errorCheckPKc               # -- Begin function _Z10errorCheckPKc
	.type	_Z10errorCheckPKc,@function
_Z10errorCheckPKc:                      # @_Z10errorCheckPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB10_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB10_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	xorl	%edi, %edi
	callq	exit
.Lfunc_end10:
	.size	_Z10errorCheckPKc, .Lfunc_end10-_Z10errorCheckPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z5statsv                       # -- Begin function _Z5statsv
	.type	_Z5statsv,@function
_Z5statsv:                              # @_Z5statsv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	BlockOfLogNormalFrames_CPU(%rip), %rdi
	movq	BlockOfLogNormalFrames_GPU(%rip), %rsi
	movl	$200, %edx
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.1, %edi
	callq	_Z10errorCheckPKc
	movq	MeanFrame_CPU(%rip), %rdi
	movq	MeanFrame_GPU(%rip), %rsi
	movl	$40, %edx
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.1, %edi
	callq	_Z10errorCheckPKc
	movq	MeanLogNormalFrame_CPU(%rip), %rdi
	movq	MeanLogNormalFrame_GPU(%rip), %rsi
	movl	$40, %edx
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.2, %edi
	callq	_Z10errorCheckPKc
	movq	MedianLogNormalFrame_CPU(%rip), %rdi
	movq	MedianLogNormalFrame_GPU(%rip), %rsi
	movl	$40, %edx
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.3, %edi
	callq	_Z10errorCheckPKc
	movq	StdvLogNormalFrame_CPU(%rip), %rdi
	movq	StdvLogNormalFrame_GPU(%rip), %rsi
	movl	$40, %edx
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.4, %edi
	callq	_Z10errorCheckPKc
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB11_1:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB11_2 Depth 2
	movl	$10, %edi
	callq	putchar@PLT
	xorl	%r15d, %r15d
.LBB11_2:                               #   Parent Loop BB11_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	BlockOfFrames_CPU(%rip), %rax
	addq	%rbx, %rax
	movl	(%rax,%r15,4), %esi
	movl	$.L.str.8, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB11_2
# %bb.3:                                #   in Loop: Header=BB11_1 Depth=1
	incq	%r14
	addq	$40, %rbx
	cmpq	$5, %r14
	jne	.LBB11_1
# %bb.4:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
	movl	$.L.str.9, %edi
	xorl	%eax, %eax
	callq	printf
	xorl	%r14d, %r14d
.LBB11_5:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB11_6 Depth 2
	movl	$10, %edi
	callq	putchar@PLT
	xorl	%r15d, %r15d
.LBB11_6:                               #   Parent Loop BB11_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	BlockOfLogNormalFrames_CPU(%rip), %rax
	addq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r15,4), %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB11_6
# %bb.7:                                #   in Loop: Header=BB11_5 Depth=1
	incq	%r14
	addq	$40, %rbx
	cmpq	$5, %r14
	jne	.LBB11_5
# %bb.8:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
.LBB11_9:                               # =>This Inner Loop Header: Depth=1
	movq	MeanFrame_CPU(%rip), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movq	MeanLogNormalFrame_CPU(%rip), %rax
	xorps	%xmm1, %xmm1
	cvtss2sd	(%rax,%rbx,4), %xmm1
	movq	MedianLogNormalFrame_CPU(%rip), %rax
	xorps	%xmm2, %xmm2
	cvtss2sd	(%rax,%rbx,4), %xmm2
	movq	StdvLogNormalFrame_CPU(%rip), %rax
	xorps	%xmm3, %xmm3
	cvtss2sd	(%rax,%rbx,4), %xmm3
	movl	$.L.str.11, %edi
	movl	%ebx, %esi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	movl	%ebx, %r8d
	movb	$4, %al
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB11_9
# %bb.10:
	movl	$10, %edi
	callq	putchar@PLT
	xorl	%ebx, %ebx
.LBB11_11:                              # =>This Inner Loop Header: Depth=1
	movq	NewFrame_CPU(%rip), %rax
	movl	(%rax,%rbx,4), %edx
	movq	BlackAndWhiteFrame_CPU(%rip), %rax
	movl	(%rax,%rbx,4), %r8d
	movl	$.L.str.12, %edi
	movl	%ebx, %esi
	movl	%ebx, %ecx
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB11_11
# %bb.12:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z5statsv, .Lfunc_end11-_Z5statsv
	.cfi_endproc
                                        # -- End function
	.globl	_Z7cleanUpv                     # -- Begin function _Z7cleanUpv
	.type	_Z7cleanUpv,@function
_Z7cleanUpv:                            # @_Z7cleanUpv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	BlockOfFrames_CPU(%rip), %rdi
	callq	free
	movq	NewFrame_CPU(%rip), %rdi
	callq	free
	movq	BlackAndWhiteFrame_CPU(%rip), %rdi
	callq	free
	movq	BlockOfFrames_GPU(%rip), %rdi
	callq	hipFree
	movq	BlockOfLogNormalFrames_GPU(%rip), %rdi
	callq	hipFree
	movq	MeanFrame_GPU(%rip), %rdi
	callq	hipFree
	movq	MeanLogNormalFrame_GPU(%rip), %rdi
	callq	hipFree
	movq	MedianLogNormalFrame_GPU(%rip), %rdi
	callq	hipFree
	movq	StdvLogNormalFrame_GPU(%rip), %rdi
	callq	hipFree
	movq	NewFrame_GPU(%rip), %rdi
	callq	hipFree
	movq	BlackAndWhiteFrame_GPU(%rip), %rdi
	callq	hipFree
	movq	BlockOfLogNormalFrames_CPU(%rip), %rdi
	callq	free
	movq	MeanFrame_CPU(%rip), %rdi
	callq	free
	movq	MeanLogNormalFrame_CPU(%rip), %rdi
	callq	free
	movq	MedianLogNormalFrame_CPU(%rip), %rdi
	callq	free
	movq	StdvLogNormalFrame_CPU(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	free                            # TAILCALL
.Lfunc_end12:
	.size	_Z7cleanUpv, .Lfunc_end12-_Z7cleanUpv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	_Z14AllocateMemoryv
	movabsq	$4294967424, %rax               # imm = 0x100000080
	movq	%rax, dimBlock(%rip)
	movl	$1, %eax
	movl	%eax, dimBlock+8(%rip)
	movabsq	$4294967297, %rcx               # imm = 0x100000001
	movq	%rcx, dimGrid(%rip)
	movl	%eax, dimGrid+8(%rip)
	xorl	%eax, %eax
	movl	$12, %ecx
	xorl	%edx, %edx
.LBB13_1:                               # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_2 Depth 2
	cmpq	$4, %rdx
	movl	%edx, %esi
	cmovel	%ecx, %esi
	xorl	%edi, %edi
.LBB13_2:                               #   Parent Loop BB13_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	BlockOfFrames_CPU(%rip), %r8
	addq	%rax, %r8
	movl	%esi, (%r8,%rdi,4)
	incq	%rdi
	cmpq	$10, %rdi
	jne	.LBB13_2
# %bb.3:                                #   in Loop: Header=BB13_1 Depth=1
	incq	%rdx
	addq	$40, %rax
	cmpq	$5, %rdx
	jne	.LBB13_1
# %bb.4:                                # %_Z10loadPixelsv.exit
	movq	BlockOfFrames_GPU(%rip), %rdi
	movq	BlockOfFrames_CPU(%rip), %rsi
	movl	$200, %edx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.13, %edi
	callq	_Z10errorCheckPKc
	callq	hipDeviceSynchronize
	movq	dimGrid(%rip), %rdi
	movl	dimGrid+8(%rip), %esi
	movq	dimBlock(%rip), %rdx
	movl	dimBlock+8(%rip), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_6
# %bb.5:
	movq	MeanFrame_GPU(%rip), %rdi
	movq	BlockOfFrames_GPU(%rip), %rsi
	movl	$10, %edx
	movl	$5, %ecx
	callq	_Z37__device_stub__creatingMeanPixelFramePfPiii
.LBB13_6:
	movl	$.L.str.14, %edi
	callq	_Z10errorCheckPKc
	movq	dimGrid(%rip), %rdi
	movl	dimGrid+8(%rip), %esi
	movq	dimBlock(%rip), %rdx
	movl	dimBlock+8(%rip), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_8
# %bb.7:
	movq	MeanFrame_GPU(%rip), %rdi
	movq	BlockOfFrames_GPU(%rip), %rsi
	movq	BlockOfLogNormalFrames_GPU(%rip), %rdx
	movl	$10, %ecx
	movl	$5, %r8d
	callq	_Z38__device_stub__creatingLogNormalFramesPfPiS_ii
.LBB13_8:
	movl	$.L.str.15, %edi
	callq	_Z10errorCheckPKc
	movq	dimGrid(%rip), %rdi
	movl	dimGrid+8(%rip), %esi
	movq	dimBlock(%rip), %rdx
	movl	dimBlock+8(%rip), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_10
# %bb.9:
	movq	MeanLogNormalFrame_GPU(%rip), %rdi
	movq	BlockOfLogNormalFrames_GPU(%rip), %rsi
	movl	$10, %edx
	movl	$5, %ecx
	callq	_Z41__device_stub__creatingMeanLogNormalFramePfS_ii
.LBB13_10:
	movl	$.L.str.16, %edi
	callq	_Z10errorCheckPKc
	movq	dimGrid(%rip), %rdi
	movl	dimGrid+8(%rip), %esi
	movq	dimBlock(%rip), %rdx
	movl	dimBlock+8(%rip), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_12
# %bb.11:
	movq	MedianLogNormalFrame_GPU(%rip), %rdi
	movq	BlockOfLogNormalFrames_GPU(%rip), %rsi
	movl	$10, %edx
	movl	$5, %ecx
	callq	_Z43__device_stub__creatingMedianLogNormalFramePfS_ii
.LBB13_12:
	movl	$.L.str.17, %edi
	callq	_Z10errorCheckPKc
	movq	dimGrid(%rip), %rdi
	movl	dimGrid+8(%rip), %esi
	movq	dimBlock(%rip), %rdx
	movl	dimBlock+8(%rip), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_14
# %bb.13:
	movq	StdvLogNormalFrame_GPU(%rip), %rdi
	movq	MeanLogNormalFrame_GPU(%rip), %rsi
	movq	BlockOfLogNormalFrames_GPU(%rip), %rdx
	movl	$10, %ecx
	movl	$5, %r8d
	callq	_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
.LBB13_14:
	movl	$.L.str.18, %edi
	callq	_Z10errorCheckPKc
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
	movq	NewFrame_CPU(%rip), %rsi
.LBB13_15:                              # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rsi,%rax,2)
	addq	$2, %rax
	cmpq	$20, %rax
	jne	.LBB13_15
# %bb.16:                               # %_Z12loadNewFramev.exit
	movq	NewFrame_GPU(%rip), %rdi
	movl	$40, %edx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.19, %edi
	callq	_Z10errorCheckPKc
	movq	dimGrid(%rip), %rdi
	movl	dimGrid+8(%rip), %esi
	movq	dimBlock(%rip), %rdx
	movl	dimBlock+8(%rip), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_18
# %bb.17:
	movq	BlackAndWhiteFrame_GPU(%rip), %rdi
	movq	NewFrame_GPU(%rip), %rsi
	movq	StdvLogNormalFrame_GPU(%rip), %rdx
	movq	MeanLogNormalFrame_GPU(%rip), %rcx
	movl	$10, %r8d
	callq	_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
.LBB13_18:
	movl	$.L.str.18, %edi
	callq	_Z10errorCheckPKc
	movq	BlackAndWhiteFrame_CPU(%rip), %rdi
	movq	BlackAndWhiteFrame_GPU(%rip), %rsi
	movl	$40, %edx
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movl	$.L.str.20, %edi
	callq	_Z10errorCheckPKc
	callq	_Z5statsv
	callq	_Z7cleanUpv
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	main, .Lfunc_end13-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB14_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB14_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22creatingMeanPixelFramePfPiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23creatingLogNormalFramesPfPiS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26creatingMeanLogNormalFramePfS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28creatingMedianLogNormalFramePfS_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26creatingStdvLogNormalFramePfS_S_ii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24CreateBlackAndWHiteFramePiS_PfS0_i, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end14:
	.size	__hip_module_ctor, .Lfunc_end14-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB15_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB15_2:
	retq
.Lfunc_end15:
	.size	__hip_module_dtor, .Lfunc_end15-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	BlockOfFrames_CPU,@object       # @BlockOfFrames_CPU
	.bss
	.globl	BlockOfFrames_CPU
	.p2align	3, 0x0
BlockOfFrames_CPU:
	.quad	0
	.size	BlockOfFrames_CPU, 8

	.type	BlockOfFrames_GPU,@object       # @BlockOfFrames_GPU
	.globl	BlockOfFrames_GPU
	.p2align	3, 0x0
BlockOfFrames_GPU:
	.quad	0
	.size	BlockOfFrames_GPU, 8

	.type	MeanFrame_GPU,@object           # @MeanFrame_GPU
	.globl	MeanFrame_GPU
	.p2align	3, 0x0
MeanFrame_GPU:
	.quad	0
	.size	MeanFrame_GPU, 8

	.type	BlockOfLogNormalFrames_GPU,@object # @BlockOfLogNormalFrames_GPU
	.globl	BlockOfLogNormalFrames_GPU
	.p2align	3, 0x0
BlockOfLogNormalFrames_GPU:
	.quad	0
	.size	BlockOfLogNormalFrames_GPU, 8

	.type	MeanLogNormalFrame_GPU,@object  # @MeanLogNormalFrame_GPU
	.globl	MeanLogNormalFrame_GPU
	.p2align	3, 0x0
MeanLogNormalFrame_GPU:
	.quad	0
	.size	MeanLogNormalFrame_GPU, 8

	.type	MedianLogNormalFrame_GPU,@object # @MedianLogNormalFrame_GPU
	.globl	MedianLogNormalFrame_GPU
	.p2align	3, 0x0
MedianLogNormalFrame_GPU:
	.quad	0
	.size	MedianLogNormalFrame_GPU, 8

	.type	StdvLogNormalFrame_GPU,@object  # @StdvLogNormalFrame_GPU
	.globl	StdvLogNormalFrame_GPU
	.p2align	3, 0x0
StdvLogNormalFrame_GPU:
	.quad	0
	.size	StdvLogNormalFrame_GPU, 8

	.type	NewFrame_CPU,@object            # @NewFrame_CPU
	.globl	NewFrame_CPU
	.p2align	3, 0x0
NewFrame_CPU:
	.quad	0
	.size	NewFrame_CPU, 8

	.type	NewFrame_GPU,@object            # @NewFrame_GPU
	.globl	NewFrame_GPU
	.p2align	3, 0x0
NewFrame_GPU:
	.quad	0
	.size	NewFrame_GPU, 8

	.type	BlackAndWhiteFrame_CPU,@object  # @BlackAndWhiteFrame_CPU
	.globl	BlackAndWhiteFrame_CPU
	.p2align	3, 0x0
BlackAndWhiteFrame_CPU:
	.quad	0
	.size	BlackAndWhiteFrame_CPU, 8

	.type	BlackAndWhiteFrame_GPU,@object  # @BlackAndWhiteFrame_GPU
	.globl	BlackAndWhiteFrame_GPU
	.p2align	3, 0x0
BlackAndWhiteFrame_GPU:
	.quad	0
	.size	BlackAndWhiteFrame_GPU, 8

	.type	BlockOfLogNormalFrames_CPU,@object # @BlockOfLogNormalFrames_CPU
	.globl	BlockOfLogNormalFrames_CPU
	.p2align	3, 0x0
BlockOfLogNormalFrames_CPU:
	.quad	0
	.size	BlockOfLogNormalFrames_CPU, 8

	.type	MeanFrame_CPU,@object           # @MeanFrame_CPU
	.globl	MeanFrame_CPU
	.p2align	3, 0x0
MeanFrame_CPU:
	.quad	0
	.size	MeanFrame_CPU, 8

	.type	MeanLogNormalFrame_CPU,@object  # @MeanLogNormalFrame_CPU
	.globl	MeanLogNormalFrame_CPU
	.p2align	3, 0x0
MeanLogNormalFrame_CPU:
	.quad	0
	.size	MeanLogNormalFrame_CPU, 8

	.type	MedianLogNormalFrame_CPU,@object # @MedianLogNormalFrame_CPU
	.globl	MedianLogNormalFrame_CPU
	.p2align	3, 0x0
MedianLogNormalFrame_CPU:
	.quad	0
	.size	MedianLogNormalFrame_CPU, 8

	.type	StdvLogNormalFrame_CPU,@object  # @StdvLogNormalFrame_CPU
	.globl	StdvLogNormalFrame_CPU
	.p2align	3, 0x0
StdvLogNormalFrame_CPU:
	.quad	0
	.size	StdvLogNormalFrame_CPU, 8

	.type	dimBlock,@object                # @dimBlock
	.data
	.globl	dimBlock
	.p2align	3, 0x0
dimBlock:
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.size	dimBlock, 12

	.type	dimGrid,@object                 # @dimGrid
	.globl	dimGrid
	.p2align	3, 0x0
dimGrid:
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.size	dimGrid, 12

	.type	_Z22creatingMeanPixelFramePfPiii,@object # @_Z22creatingMeanPixelFramePfPiii
	.section	.rodata,"a",@progbits
	.globl	_Z22creatingMeanPixelFramePfPiii
	.p2align	3, 0x0
_Z22creatingMeanPixelFramePfPiii:
	.quad	_Z37__device_stub__creatingMeanPixelFramePfPiii
	.size	_Z22creatingMeanPixelFramePfPiii, 8

	.type	_Z23creatingLogNormalFramesPfPiS_ii,@object # @_Z23creatingLogNormalFramesPfPiS_ii
	.globl	_Z23creatingLogNormalFramesPfPiS_ii
	.p2align	3, 0x0
_Z23creatingLogNormalFramesPfPiS_ii:
	.quad	_Z38__device_stub__creatingLogNormalFramesPfPiS_ii
	.size	_Z23creatingLogNormalFramesPfPiS_ii, 8

	.type	_Z26creatingMeanLogNormalFramePfS_ii,@object # @_Z26creatingMeanLogNormalFramePfS_ii
	.globl	_Z26creatingMeanLogNormalFramePfS_ii
	.p2align	3, 0x0
_Z26creatingMeanLogNormalFramePfS_ii:
	.quad	_Z41__device_stub__creatingMeanLogNormalFramePfS_ii
	.size	_Z26creatingMeanLogNormalFramePfS_ii, 8

	.type	_Z28creatingMedianLogNormalFramePfS_ii,@object # @_Z28creatingMedianLogNormalFramePfS_ii
	.globl	_Z28creatingMedianLogNormalFramePfS_ii
	.p2align	3, 0x0
_Z28creatingMedianLogNormalFramePfS_ii:
	.quad	_Z43__device_stub__creatingMedianLogNormalFramePfS_ii
	.size	_Z28creatingMedianLogNormalFramePfS_ii, 8

	.type	_Z26creatingStdvLogNormalFramePfS_S_ii,@object # @_Z26creatingStdvLogNormalFramePfS_S_ii
	.globl	_Z26creatingStdvLogNormalFramePfS_S_ii
	.p2align	3, 0x0
_Z26creatingStdvLogNormalFramePfS_S_ii:
	.quad	_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
	.size	_Z26creatingStdvLogNormalFramePfS_S_ii, 8

	.type	_Z24CreateBlackAndWHiteFramePiS_PfS0_i,@object # @_Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.globl	_Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.p2align	3, 0x0
_Z24CreateBlackAndWHiteFramePiS_PfS0_i:
	.quad	_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
	.size	_Z24CreateBlackAndWHiteFramePiS_PfS0_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n CUDA ERROR: %s = %s\n"
	.size	.L.str, 23

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"copy Mean frame down"
	.size	.L.str.1, 21

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"copy MeanLogNormal frame down"
	.size	.L.str.2, 30

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"copy MedianLogNormal frame down"
	.size	.L.str.3, 32

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"copy StdvLogNormal frame down"
	.size	.L.str.4, 30

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"frames"
	.size	.L.str.6, 7

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"%d "
	.size	.L.str.8, 4

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"log normal frames"
	.size	.L.str.9, 18

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"%f "
	.size	.L.str.10, 4

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n"
	.size	.L.str.11, 107

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n"
	.size	.L.str.12, 48

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"copyFramessUp"
	.size	.L.str.13, 14

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"creatingMeanPixelFrame"
	.size	.L.str.14, 23

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"creatingLogNormalFrames"
	.size	.L.str.15, 24

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"creatingMeanLogNormalFrame"
	.size	.L.str.16, 27

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"creatingMedianLogNormalFrame"
	.size	.L.str.17, 29

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"creatingStdvLogNormalFrame"
	.size	.L.str.18, 27

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"copy New frame up"
	.size	.L.str.19, 18

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"copy black and white frame down"
	.size	.L.str.20, 32

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22creatingMeanPixelFramePfPiii"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z23creatingLogNormalFramesPfPiS_ii"
	.size	.L__unnamed_2, 36

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z26creatingMeanLogNormalFramePfS_ii"
	.size	.L__unnamed_3, 37

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z28creatingMedianLogNormalFramePfS_ii"
	.size	.L__unnamed_4, 39

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z26creatingStdvLogNormalFramePfS_S_ii"
	.size	.L__unnamed_5, 39

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z24CreateBlackAndWHiteFramePiS_PfS0_i"
	.size	.L__unnamed_6, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr.2,@object                 # @str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
	.asciz	"\n"
	.size	.Lstr.2, 2

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\n DONE "
	.size	.Lstr.3, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__creatingMeanPixelFramePfPiii
	.addrsig_sym _Z38__device_stub__creatingLogNormalFramesPfPiS_ii
	.addrsig_sym _Z41__device_stub__creatingMeanLogNormalFramePfS_ii
	.addrsig_sym _Z43__device_stub__creatingMedianLogNormalFramePfS_ii
	.addrsig_sym _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
	.addrsig_sym _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym BlockOfFrames_GPU
	.addrsig_sym MeanFrame_GPU
	.addrsig_sym BlockOfLogNormalFrames_GPU
	.addrsig_sym MeanLogNormalFrame_GPU
	.addrsig_sym MedianLogNormalFrame_GPU
	.addrsig_sym StdvLogNormalFrame_GPU
	.addrsig_sym NewFrame_GPU
	.addrsig_sym BlackAndWhiteFrame_GPU
	.addrsig_sym _Z22creatingMeanPixelFramePfPiii
	.addrsig_sym _Z23creatingLogNormalFramesPfPiS_ii
	.addrsig_sym _Z26creatingMeanLogNormalFramePfS_ii
	.addrsig_sym _Z28creatingMedianLogNormalFramePfS_ii
	.addrsig_sym _Z26creatingStdvLogNormalFramePfS_S_ii
	.addrsig_sym _Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22creatingMeanPixelFramePfPiii ; -- Begin function _Z22creatingMeanPixelFramePfPiii
	.globl	_Z22creatingMeanPixelFramePfPiii
	.p2align	8
	.type	_Z22creatingMeanPixelFramePfPiii,@function
_Z22creatingMeanPixelFramePfPiii:       ; @_Z22creatingMeanPixelFramePfPiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v2, 0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v1
	s_mov_b32 s6, s5
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s6, s6, -1
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_nc_u32_e32 v4, s4, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	global_load_b32 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_i32_e32 v[5:6], v0
	v_add_f64 v[2:3], v[2:3], v[5:6]
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
.LBB0_5:                                ; %Flow34
	v_cvt_f32_i32_e32 v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v0
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[10:11], v[8:9]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
	v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v3, v[2:3]
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22creatingMeanPixelFramePfPiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22creatingMeanPixelFramePfPiii, .Lfunc_end0-_Z22creatingMeanPixelFramePfPiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23creatingLogNormalFramesPfPiS_ii ; -- Begin function _Z23creatingLogNormalFramesPfPiS_ii
	.globl	_Z23creatingLogNormalFramesPfPiS_ii
	.p2align	8
	.type	_Z23creatingLogNormalFramesPfPiS_ii,@function
_Z23creatingLogNormalFramesPfPiS_ii:    ; @_Z23creatingLogNormalFramesPfPiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_cmp_gt_i32 s3, 0
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_b32 s4, vcc_lo, s4
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s3, 0
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v0, v[7:8], off
	global_load_b32 v2, v[3:4], off
	s_waitcnt vmcnt(1)
	v_cvt_f32_i32_e32 v0, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v2
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v0, 0x358637bd, |v0|, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
	v_mul_f32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x3f317217, v0
	v_fma_f32 v7, 0x3f317217, v0, -v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, 0x3377d1cf, v0
	v_add_f32_e32 v2, v2, v7
	v_cndmask_b32_e64 v7, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_sub_f32_e32 v0, v0, v7
	global_store_b32 v[5:6], v0, off
	s_cbranch_scc1 .LBB1_2
.LBB1_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23creatingLogNormalFramesPfPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z23creatingLogNormalFramesPfPiS_ii, .Lfunc_end1-_Z23creatingLogNormalFramesPfPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 368
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26creatingMeanLogNormalFramePfS_ii ; -- Begin function _Z26creatingMeanLogNormalFramePfS_ii
	.globl	_Z26creatingMeanLogNormalFramePfS_ii
	.p2align	8
	.type	_Z26creatingMeanLogNormalFramePfS_ii,@function
_Z26creatingMeanLogNormalFramePfS_ii:   ; @_Z26creatingMeanLogNormalFramePfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB2_6
; %bb.1:                                ; %.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB2_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v2, 0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v1
	s_mov_b32 s6, s5
.LBB2_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s6, s6, -1
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_nc_u32_e32 v4, s4, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	global_load_b32 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_add_f64 v[2:3], v[2:3], v[5:6]
	s_cbranch_scc0 .LBB2_3
	s_branch .LBB2_5
.LBB2_4:
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
.LBB2_5:                                ; %Flow34
	v_cvt_f32_i32_e32 v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v0
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[10:11], v[8:9]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
	v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v3, v[2:3]
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB2_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26creatingMeanLogNormalFramePfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z26creatingMeanLogNormalFramePfS_ii, .Lfunc_end2-_Z26creatingMeanLogNormalFramePfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
	v_mov_b32_e32 v5, v0
	v_mbcnt_lo_u32_b32 v2, -1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_mov_b32 s8, 0
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s0, -1
	s_cbranch_scc0 .LBB3_87
; %bb.1:
	v_dual_mov_b32 v31, 0 :: v_dual_and_b32 v0, -3, v5
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	v_dual_mov_b32 v33, s1 :: v_dual_mov_b32 v32, s0
	v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
	s_mov_b32 s9, 0
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_5 Depth 2
                                        ;     Child Loop BB3_13 Depth 2
                                        ;     Child Loop BB3_21 Depth 2
                                        ;     Child Loop BB3_29 Depth 2
                                        ;     Child Loop BB3_37 Depth 2
                                        ;     Child Loop BB3_45 Depth 2
                                        ;     Child Loop BB3_53 Depth 2
                                        ;     Child Loop BB3_61 Depth 2
                                        ;     Child Loop BB3_69 Depth 2
                                        ;     Child Loop BB3_75 Depth 2
                                        ;     Child Loop BB3_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[3:4]
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v35, 0, v4 :: v_dual_cndmask_b32 v34, 56, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v34
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB3_8
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v34
	s_cbranch_execz .LBB3_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v12, 0
	v_lshlrev_b64 v[6:7], 3, v[34:35]
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, v32
	v_mov_b32_e32 v15, v33
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB3_5:                                ; %.preheader31
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v[14:15], off
	v_mov_b32_e32 v17, s8
	v_add_co_u32 v14, vcc_lo, v14, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v16, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[16:17], s4, v[16:17]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v6
	v_or_b32_e32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v12, v16, v12
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_5
; %bb.6:                                ; %Flow163
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_7:                                ; %Flow165
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB3_8:                                ; %Flow167
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_mov_b32_e32 v6, v32
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v7, v33
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_10
; %bb.9:                                ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[12:13], v[32:33], off
	v_add_co_u32 v6, vcc_lo, v32, 8
	v_add_nc_u32_e32 v0, -8, v34
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v33, vcc_lo
.LBB3_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB3_16
; %bb.11:                               ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB3_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s10, 0
	s_mov_b64 s[4:5], 0
.LBB3_13:                               ; %.preheader29
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v16, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v7, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v16, v[16:17], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v17, s8 :: v_dual_and_b32 v16, 0xffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], s0, v[16:17]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s10, vcc_lo, s10
	v_or_b32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v16, v14
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB3_13
; %bb.14:                               ; %Flow158
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB3_15:                               ; %Flow160
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB3_16:                               ; %Flow162
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v18, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_18
; %bb.17:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[14:15], v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_nc_u32_e32 v18, -8, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB3_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v18
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB3_24
; %bb.19:                               ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v18
	s_cbranch_execz .LBB3_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s10, 0
	s_mov_b64 s[4:5], 0
.LBB3_21:                               ; %.preheader27
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v19, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v7, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v18
	global_load_u8 v0, v[19:20], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v20, s8 :: v_dual_and_b32 v19, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s10, vcc_lo, s10
	v_or_b32_e32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v19, v16
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB3_21
; %bb.22:                               ; %Flow153
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB3_23:                               ; %Flow155
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr18
.LBB3_24:                               ; %Flow157
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v0, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_26
; %bb.25:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[16:17], v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_nc_u32_e32 v0, -8, v18
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB3_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB3_32
; %bb.27:                               ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB3_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s10, 0
	s_mov_b64 s[4:5], 0
.LBB3_29:                               ; %.preheader25
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v7, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v20, v[20:21], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v21, s8 :: v_dual_and_b32 v20, 0xffff, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s10, vcc_lo, s10
	v_or_b32_e32 v19, v21, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v20, v18
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB3_29
; %bb.30:                               ; %Flow148
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB3_31:                               ; %Flow150
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB3_32:                               ; %Flow152
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v22, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_34
; %bb.33:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[18:19], v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_nc_u32_e32 v22, -8, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB3_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v22
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB3_40
; %bb.35:                               ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v22
	s_cbranch_execz .LBB3_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s10, 0
	s_mov_b64 s[4:5], 0
.LBB3_37:                               ; %.preheader23
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v23, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v7, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v22
	global_load_u8 v0, v[23:24], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v24, s8 :: v_dual_and_b32 v23, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], s0, v[23:24]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s10, vcc_lo, s10
	v_or_b32_e32 v21, v24, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v23, v20
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB3_37
; %bb.38:                               ; %Flow143
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB3_39:                               ; %Flow145
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr22
.LBB3_40:                               ; %Flow147
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v0, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_42
; %bb.41:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[20:21], v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_nc_u32_e32 v0, -8, v22
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB3_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB3_48
; %bb.43:                               ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB3_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s10, 0
	s_mov_b64 s[4:5], 0
.LBB3_45:                               ; %.preheader21
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v24, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v7, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v24, v[24:25], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v25, s8 :: v_dual_and_b32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], s0, v[24:25]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s10, vcc_lo, s10
	v_or_b32_e32 v23, v25, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v24, v22
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB3_45
; %bb.46:                               ; %Flow138
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB3_47:                               ; %Flow140
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB3_48:                               ; %Flow142
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v26, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_50
; %bb.49:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[22:23], v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_nc_u32_e32 v26, -8, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB3_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v26
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB3_56
; %bb.51:                               ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v26
	s_cbranch_execz .LBB3_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB3_53:                               ; %.preheader
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v[6:7], off
	v_mov_b32_e32 v28, s8
	v_add_nc_u32_e32 v26, -1, v26
	v_add_co_u32 v6, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v26
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v0
	v_lshlrev_b64 v[27:28], s0, v[27:28]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v25, v28, v25
	v_or_b32_e32 v24, v27, v24
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB3_53
; %bb.54:                               ; %Flow133
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_55:                               ; %Flow135
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr6_vgpr7
.LBB3_56:                               ; %Flow137
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB3_58
; %bb.57:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[24:25], v[6:7], off
.LBB3_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v30, v2
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v30
	v_cmp_eq_u32_e64 s0, s0, v30
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_64
; %bb.59:                               ;   in Loop: Header=BB3_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v31, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[6:7], v31, s[2:3] offset:40
	global_load_b64 v[26:27], v31, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v7, v29
	v_and_b32_e32 v6, v6, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v7, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v7, v0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v26, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v27, v0, vcc_lo
	global_load_b64 v[26:27], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v31, v[26:29], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[28:29]
	s_cbranch_execz .LBB3_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s5, 0
.LBB3_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[26:27], v31, s[2:3] offset:40
	global_load_b64 v[36:37], v31, s[2:3]
	v_dual_mov_b32 v29, v7 :: v_dual_mov_b32 v28, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, v26, v28
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v0, 24, v[36:37]
	v_and_b32_e32 v36, v27, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v7
	v_mad_u64_u32 v[26:27], null, v36, 24, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v26
	global_load_b64 v[26:27], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v31, v[26:29], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[28:29]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB3_61
; %bb.62:                               ; %Flow130
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_63:                               ; %Flow132
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB3_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[36:37], v31, s[2:3] offset:40
	global_load_b128 v[26:29], v31, s[2:3]
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v36
	v_readfirstlane_b32 s7, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s10, s6, 24
	s_mul_i32 s11, s6, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB3_66
; %bb.65:                               ;   in Loop: Header=BB3_2 Depth=1
	s_add_i32 s14, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v36, vcc_lo, v26, s11
	v_add_co_ci_u32_e32 v37, vcc_lo, s14, v27, vcc_lo
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, v31
	global_store_b128 v[36:37], v[6:9], off offset:8
.LBB3_66:                               ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_cmp_lt_u64_e32 vcc_lo, 56, v[3:4]
	v_or_b32_e32 v0, 2, v10
	v_lshl_add_u32 v6, v34, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	v_and_b32_e32 v10, 0x1e0, v6
	v_lshlrev_b64 v[6:7], 6, v[30:31]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v28, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v29, vcc_lo, s7, v29, vcc_lo
	v_and_or_b32 v10, 0xffffff1f, v0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v28, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v29, v7, vcc_lo
	s_clause 0x3
	global_store_b128 v[6:7], v[10:13], off
	global_store_b128 v[6:7], v[14:17], off offset:16
	global_store_b128 v[6:7], v[18:21], off offset:32
	global_store_b128 v[6:7], v[22:25], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB3_74
; %bb.67:                               ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v31, s[2:3] offset:32 glc
	global_load_b64 v[10:11], v31, s[2:3] offset:40
	v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v17, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v10
	v_readfirstlane_b32 s13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s7, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v14, vcc_lo, v26, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v27, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[14:15], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v31, v[16:19], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[18:19]
	s_cbranch_execz .LBB3_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s12, 0
.LBB3_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
	s_sleep 1
	global_store_b64 v[14:15], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v31, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB3_69
.LBB3_70:                               ; %Flow128
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[10:11], v31, s[2:3] offset:16
	s_mov_b32 s12, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s12, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_72
; %bb.71:                               ;   in Loop: Header=BB3_2 Depth=1
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v30, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[10:11], v[30:31], off offset:8
.LBB3_72:                               ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[10:11], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB3_74
; %bb.73:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b32 v30, v[10:11], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v30
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[30:31], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_74:                               ; %Flow129
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v26, s11
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
.LBB3_75:                               ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_77
; %bb.76:                               ;   in Loop: Header=BB3_75 Depth=2
	global_load_b32 v0, v[10:11], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB3_77:                               ;   in Loop: Header=BB3_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_79
; %bb.78:                               ;   in Loop: Header=BB3_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_80
.LBB3_79:                               ;   in Loop: Header=BB3_75 Depth=2
	s_mov_b32 s1, -1
.LBB3_80:                               ; %Flow123
                                        ;   in Loop: Header=BB3_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_75
; %bb.81:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b128 v[10:13], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_85
; %bb.82:                               ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x2
	global_load_b64 v[6:7], v31, s[2:3] offset:40
	global_load_b64 v[16:17], v31, s[2:3] offset:24 glc
	global_load_b64 v[14:15], v31, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v0
	v_and_b32_e32 v0, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v12, v6
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v0, v7, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v14, v6
	v_mov_b32_e32 v14, v16
	v_add_co_ci_u32_e32 v7, vcc_lo, v15, v0, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[6:7], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v31, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, 0
.LBB3_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v31, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_84
.LBB3_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v3, vcc_lo, v3, v34
	v_sub_co_ci_u32_e32 v4, vcc_lo, v4, v35, vcc_lo
	v_add_co_u32 v32, s0, v32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v33, s0, v33, v35, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_2
; %bb.86:                               ; %Flow168
	s_or_b32 exec_lo, exec_lo, s9
	s_mov_b32 s0, 0
.LBB3_87:                               ; %Flow184
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB3_116
; %bb.88:
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[6:7], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v8
	v_and_b32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	global_load_b64 v[6:7], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[10:11], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[10:11], v[8:9]
	s_cbranch_execz .LBB3_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s5, 0
.LBB3_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[6:7], v0, s[2:3]
	v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v3, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[10:11], null, v3, 24, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v11 :: v_dual_and_b32 v4, v4, v9
	v_mad_u64_u32 v[6:7], null, v4, 24, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v11, v6
	global_load_b64 v[6:7], v[10:11], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[10:11], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB3_91
; %bb.92:                               ; %Flow181
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_93:                               ; %Flow183
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB3_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v10
	v_readfirstlane_b32 s5, v11
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[12:13], v3, s[2:3] offset:40
	global_load_b128 v[6:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v12
	v_readfirstlane_b32 s7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB3_96
; %bb.95:
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v14, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v15, vcc_lo, s12, v7, vcc_lo
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, v3
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[14:15], v[10:13], off offset:8
.LBB3_96:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[10:11], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v10
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v5, 34
	v_add_co_ci_u32_e32 v5, vcc_lo, v8, v11, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[4:5], v[0:3], off
	global_store_b128 v[4:5], v[8:11], off offset:16
	global_store_b128 v[4:5], v[8:11], off offset:32
	global_store_b128 v[4:5], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB3_104
; %bb.97:
	v_mov_b32_e32 v8, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	v_dual_mov_b32 v9, s4 :: v_dual_mov_b32 v10, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v4, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v1, vcc_lo
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB3_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s10, 0
.LBB3_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB3_99
.LBB3_100:                              ; %Flow179
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB3_102
; %bb.101:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB3_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB3_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_104:                              ; %Flow180
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_107
; %bb.106:                              ;   in Loop: Header=BB3_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_107:                              ;   in Loop: Header=BB3_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_109
; %bb.108:                              ;   in Loop: Header=BB3_105 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_110
.LBB3_109:                              ;   in Loop: Header=BB3_105 Depth=1
	s_mov_b32 s1, -1
.LBB3_110:                              ; %Flow174
                                        ;   in Loop: Header=BB3_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_105
; %bb.111:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_115
; %bb.112:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB3_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_114
.LBB3_115:                              ; %Flow172
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_116:                              ; %.loopexit33
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end3:
	.size	__ockl_printf_append_string_n, .Lfunc_end3-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 4424
; NumSgprs: 34
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z28creatingMedianLogNormalFramePfS_ii ; -- Begin function _Z28creatingMedianLogNormalFramePfS_ii
	.globl	_Z28creatingMedianLogNormalFramePfS_ii
	.p2align	8
	.type	_Z28creatingMedianLogNormalFramePfS_ii,@function
_Z28creatingMedianLogNormalFramePfS_ii: ; @_Z28creatingMedianLogNormalFramePfS_ii
; %bb.0:
	s_mov_b64 s[16:17], s[0:1]
	s_load_b32 s0, s[0:1], 0x24
	s_load_b64 s[18:19], s[16:17], 0x10
	s_add_u32 s26, s16, 24
	s_addc_u32 s27, s17, 0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[50:51], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s18, v50
	s_cbranch_execz .LBB4_85
; %bb.1:                                ; %.preheader108
	s_cmp_gt_i32 s19, 0
	s_cselect_b32 s25, -1, 0
	s_cmp_lt_i32 s19, 1
	s_cbranch_scc1 .LBB4_4
; %bb.2:                                ; %.lr.ph.preheader
	s_mov_b64 s[0:1], 0
                                        ; implicit-def: $sgpr20
.LBB4_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 4
	s_cselect_b32 s24, s24, 0
	s_cmp_lg_u32 s0, 3
	s_cselect_b32 s23, s23, 0
	s_cmp_lg_u32 s0, 2
	s_cselect_b32 s22, s22, 0
	s_cmp_lg_u32 s0, 1
	s_cselect_b32 s21, s21, 0
	s_cmp_lg_u32 s0, 0
	s_cselect_b32 s20, s20, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s19, s0
	s_cbranch_scc0 .LBB4_3
	s_branch .LBB4_5
.LBB4_4:
                                        ; implicit-def: $sgpr20_sgpr21_sgpr22_sgpr23_sgpr24
.LBB4_5:                                ; %._crit_edge
	s_load_b128 s[36:39], s[16:17], 0x0
	s_bitcmp1_b32 s19, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB4_44
; %bb.6:
	v_mov_b32_e32 v52, 0
	s_cmp_lt_i32 s19, -1
	s_cbranch_scc1 .LBB4_43
; %bb.7:                                ; %.preheader107.lr.ph
	v_mov_b32_e32 v45, 0
	s_lshr_b32 s2, s19, 31
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_add_i32 s2, s19, s2
	v_dual_mov_b32 v51, -1 :: v_dual_mov_b32 v42, s24
	s_ashr_i32 s33, s2, 1
	v_dual_mov_b32 v41, s23 :: v_dual_mov_b32 v38, s20
	v_dual_mov_b32 v40, s22 :: v_dual_mov_b32 v39, s21
	v_mov_b32_e32 v48, 2
	v_mbcnt_lo_u32_b32 v53, -1, 0
	v_dual_mov_b32 v49, 1 :: v_dual_mov_b32 v52, v45
	v_mov_b32_e32 v43, 33
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s28, 0
	s_cselect_b32 s34, 23, 0
	s_mov_b32 s35, 0
.LBB4_8:                                ; %.preheader107
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_10 Depth 2
                                        ;     Child Loop BB4_15 Depth 2
                                        ;     Child Loop BB4_23 Depth 2
                                        ;     Child Loop BB4_29 Depth 2
                                        ;     Child Loop BB4_38 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB4_11
; %bb.9:                                ; %.lr.ph117.preheader
                                        ;   in Loop: Header=BB4_8 Depth=1
	v_mov_b32_e32 v2, 0x4b189680
	v_mov_b32_e32 v0, v50
	s_mov_b64 s[2:3], 0
.LBB4_10:                               ; %.lr.ph117
                                        ;   Parent Loop BB4_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_cmp_eq_u32 s2, 1
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v0, s18, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s38, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s39, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	global_load_b32 v1, v[3:4], off
	v_cndmask_b32_e32 v3, v38, v39, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v40, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e32 v3, v3, v41, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v42, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e64 s0, v1, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v2, v2, v1, vcc_lo
	v_cndmask_b32_e64 v51, v51, s2, vcc_lo
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s19, s2
	s_cbranch_scc0 .LBB4_10
.LBB4_11:                               ; %Flow227
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_mov_b32 s40, exec_lo
	v_cmpx_eq_u32_e32 -1, v51
	s_cbranch_execz .LBB4_40
; %bb.12:                               ;   in Loop: Header=BB4_8 Depth=1
	s_load_b64 s[2:3], s[26:27], 0x50
	v_mov_b32_e32 v44, v53
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v44
	v_cmp_eq_u32_e64 s0, s0, v44
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_18
; %bb.13:                               ;   in Loop: Header=BB4_8 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v45, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[2:3] offset:40
	global_load_b64 v[4:5], v45, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB4_17
; %bb.14:                               ; %.preheader3.i.i.i99.preheader
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_mov_b32 s5, 0
.LBB4_15:                               ; %.preheader3.i.i.i99
                                        ;   Parent Loop BB4_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[2:3] offset:40
	global_load_b64 v[6:7], v45, s[2:3]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_15
; %bb.16:                               ; %Flow222
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_17:                               ; %Flow224
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_18:                               ; %.loopexit4.i.i.i94
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v45, s[2:3] offset:40
	global_load_b128 v[0:3], v45, s[2:3]
	v_readfirstlane_b32 s4, v4
	v_readfirstlane_b32 s5, v5
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v6
	v_readfirstlane_b32 s7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB4_20
; %bb.19:                               ;   in Loop: Header=BB4_8 Depth=1
	v_dual_mov_b32 v46, s10 :: v_dual_mov_b32 v47, v45
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	global_store_b128 v[4:5], v[46:49], off offset:8
.LBB4_20:                               ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[44:45]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v44, v45
	v_mov_b32_e32 v46, v45
	v_dual_mov_b32 v2, s28 :: v_dual_mov_b32 v5, s31
	v_dual_mov_b32 v3, s29 :: v_dual_mov_b32 v4, s30
	s_clause 0x3
	global_store_b128 v[6:7], v[43:46], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_28
; %bb.21:                               ;   in Loop: Header=BB4_8 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v45, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v45, s[2:3] offset:40
	s_mov_b32 s7, exec_lo
	v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v45, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB4_24
; %bb.22:                               ; %.preheader1.i.i.i97.preheader
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_mov_b32 s10, 0
.LBB4_23:                               ; %.preheader1.i.i.i97
                                        ;   Parent Loop BB4_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v45, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB4_23
.LBB4_24:                               ; %Flow220
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[2:3], v45, s[2:3] offset:16
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB4_26
; %bb.25:                               ;   in Loop: Header=BB4_8 Depth=1
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v44, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[44:45], off offset:8
.LBB4_26:                               ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB4_28
; %bb.27:                               ;   in Loop: Header=BB4_8 Depth=1
	global_load_b32 v44, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v44
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[44:45], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_28:                               ; %Flow221
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_29:                               ;   Parent Loop BB4_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_31
; %bb.30:                               ;   in Loop: Header=BB4_29 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_31:                               ;   in Loop: Header=BB4_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_33
; %bb.32:                               ;   in Loop: Header=BB4_29 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_34
.LBB4_33:                               ;   in Loop: Header=BB4_29 Depth=2
	s_mov_b32 s1, -1
.LBB4_34:                               ; %Flow215
                                        ;   in Loop: Header=BB4_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_29
; %bb.35:                               ;   in Loop: Header=BB4_8 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_39
; %bb.36:                               ;   in Loop: Header=BB4_8 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v45, s[2:3] offset:40
	global_load_b64 v[8:9], v45, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v45, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v45, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_39
; %bb.37:                               ; %.preheader.i.i.i96.preheader
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_mov_b32 s0, 0
.LBB4_38:                               ; %.preheader.i.i.i96
                                        ;   Parent Loop BB4_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v45, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_38
.LBB4_39:                               ; %__ockl_printf_begin.exit100
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, s34 :: v_dual_mov_b32 v3, 0
	s_add_u32 s8, s16, 24
	s_addc_u32 s9, s17, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
.LBB4_40:                               ; %Flow225
                                        ;   in Loop: Header=BB4_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s40
	s_cmp_eq_u32 s35, s33
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s35, s33
	s_cbranch_scc1 .LBB4_42
; %bb.41:                               ;   in Loop: Header=BB4_8 Depth=1
	v_mad_u64_u32 v[0:1], null, v51, s18, v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s39, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v52, v52, v0
.LBB4_42:                               ;   in Loop: Header=BB4_8 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 4, v51
	s_add_i32 s35, s35, 1
	v_cndmask_b32_e32 v42, 1, v42, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v51
	v_cndmask_b32_e32 v41, 1, v41, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v51
	v_cndmask_b32_e32 v40, 1, v40, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v51
	v_cndmask_b32_e32 v39, 1, v39, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v51
	v_cndmask_b32_e32 v38, 1, v38, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB4_8
.LBB4_43:                               ; %Flow229
	s_mov_b32 s0, 0
	s_branch .LBB4_45
.LBB4_44:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr52
.LBB4_45:                               ; %Flow249
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB4_84
; %bb.46:
	v_mov_b32_e32 v52, 0
	s_ashr_i32 s33, s19, 1
	s_mov_b32 s28, 0
	s_cmp_lt_i32 s33, 0
	s_cbranch_scc1 .LBB4_84
; %bb.47:                               ; %.preheader105.lr.ph
	v_mov_b32_e32 v45, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_dual_mov_b32 v51, -1 :: v_dual_mov_b32 v42, s24
	s_add_i32 s34, s33, -1
	v_dual_mov_b32 v41, s23 :: v_dual_mov_b32 v38, s20
	v_dual_mov_b32 v40, s22 :: v_dual_mov_b32 v39, s21
	v_mov_b32_e32 v48, 2
	v_mbcnt_lo_u32_b32 v52, -1, 0
	v_mov_b32_e32 v49, 1
	v_mov_b32_e32 v43, 33
	v_mov_b32_e32 v53, v45
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s21, 0
	s_cselect_b32 s20, 23, 0
.LBB4_48:                               ; %.preheader105
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_50 Depth 2
                                        ;     Child Loop BB4_55 Depth 2
                                        ;     Child Loop BB4_63 Depth 2
                                        ;     Child Loop BB4_69 Depth 2
                                        ;     Child Loop BB4_78 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB4_51
; %bb.49:                               ; %.lr.ph129.preheader
                                        ;   in Loop: Header=BB4_48 Depth=1
	v_mov_b32_e32 v2, 0x4b189680
	v_mov_b32_e32 v0, v50
	s_mov_b64 s[2:3], 0
.LBB4_50:                               ; %.lr.ph129
                                        ;   Parent Loop BB4_48 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_cmp_eq_u32 s2, 1
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v0, s18, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s38, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s39, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	global_load_b32 v1, v[3:4], off
	v_cndmask_b32_e32 v3, v38, v39, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v40, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e32 v3, v3, v41, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v42, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e64 s0, v1, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v2, v2, v1, vcc_lo
	v_cndmask_b32_e64 v51, v51, s2, vcc_lo
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s19, s2
	s_cbranch_scc0 .LBB4_50
.LBB4_51:                               ; %Flow246
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_mov_b32 s22, exec_lo
	v_cmpx_eq_u32_e32 -1, v51
	s_cbranch_execz .LBB4_80
; %bb.52:                               ;   in Loop: Header=BB4_48 Depth=1
	s_load_b64 s[2:3], s[26:27], 0x50
	v_mov_b32_e32 v44, v52
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v44
	v_cmp_eq_u32_e64 s0, s0, v44
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_58
; %bb.53:                               ;   in Loop: Header=BB4_48 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v45, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[2:3] offset:40
	global_load_b64 v[4:5], v45, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB4_57
; %bb.54:                               ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_mov_b32 s5, 0
.LBB4_55:                               ; %.preheader3.i.i.i
                                        ;   Parent Loop BB4_48 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[2:3] offset:40
	global_load_b64 v[6:7], v45, s[2:3]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_55
; %bb.56:                               ; %Flow241
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_57:                               ; %Flow243
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_58:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v45, s[2:3] offset:40
	global_load_b128 v[0:3], v45, s[2:3]
	v_readfirstlane_b32 s4, v4
	v_readfirstlane_b32 s5, v5
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v6
	v_readfirstlane_b32 s7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB4_60
; %bb.59:                               ;   in Loop: Header=BB4_48 Depth=1
	v_dual_mov_b32 v46, s10 :: v_dual_mov_b32 v47, v45
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	global_store_b128 v[4:5], v[46:49], off offset:8
.LBB4_60:                               ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[44:45]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v44, v45
	v_mov_b32_e32 v46, v45
	v_dual_mov_b32 v2, s28 :: v_dual_mov_b32 v5, s31
	v_dual_mov_b32 v3, s29 :: v_dual_mov_b32 v4, s30
	s_clause 0x3
	global_store_b128 v[6:7], v[43:46], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_68
; %bb.61:                               ;   in Loop: Header=BB4_48 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v45, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v45, s[2:3] offset:40
	s_mov_b32 s7, exec_lo
	v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v45, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB4_64
; %bb.62:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_mov_b32 s10, 0
.LBB4_63:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB4_48 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v45, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB4_63
.LBB4_64:                               ; %Flow239
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[2:3], v45, s[2:3] offset:16
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB4_66
; %bb.65:                               ;   in Loop: Header=BB4_48 Depth=1
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v44, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[44:45], off offset:8
.LBB4_66:                               ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB4_68
; %bb.67:                               ;   in Loop: Header=BB4_48 Depth=1
	global_load_b32 v44, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v44
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[44:45], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_68:                               ; %Flow240
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_69:                               ;   Parent Loop BB4_48 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_71
; %bb.70:                               ;   in Loop: Header=BB4_69 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_71:                               ;   in Loop: Header=BB4_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_73
; %bb.72:                               ;   in Loop: Header=BB4_69 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_74
.LBB4_73:                               ;   in Loop: Header=BB4_69 Depth=2
	s_mov_b32 s1, -1
.LBB4_74:                               ; %Flow234
                                        ;   in Loop: Header=BB4_69 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_69
; %bb.75:                               ;   in Loop: Header=BB4_48 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_79
; %bb.76:                               ;   in Loop: Header=BB4_48 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v45, s[2:3] offset:40
	global_load_b64 v[8:9], v45, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v45, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v45, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_79
; %bb.77:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_mov_b32 s0, 0
.LBB4_78:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB4_48 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v45, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_78
.LBB4_79:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, 0
	s_add_u32 s8, s16, 24
	s_addc_u32 s9, s17, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
.LBB4_80:                               ; %Flow244
                                        ;   in Loop: Header=BB4_48 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_cmp_lg_u32 s21, s34
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s21, s33
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s21, s33
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_82
; %bb.81:                               ;   in Loop: Header=BB4_48 Depth=1
	v_mad_u64_u32 v[0:1], null, v51, s18, v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s39, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v53, v53, v0
.LBB4_82:                               ;   in Loop: Header=BB4_48 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 4, v51
	s_add_i32 s21, s21, 1
	v_cndmask_b32_e32 v42, 1, v42, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v51
	v_cndmask_b32_e32 v41, 1, v41, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v51
	v_cndmask_b32_e32 v40, 1, v40, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v51
	v_cndmask_b32_e32 v39, 1, v39, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v51
	v_cndmask_b32_e32 v38, 1, v38, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB4_48
; %bb.83:                               ; %._crit_edge137.loopexit
	v_mul_f32_e32 v52, 0.5, v53
.LBB4_84:                               ; %.loopexit
	v_ashrrev_i32_e32 v51, 31, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[50:51]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s36, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s37, v1, vcc_lo
	global_store_b32 v[0:1], v52, off
.LBB4_85:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28creatingMedianLogNormalFramePfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 54
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z28creatingMedianLogNormalFramePfS_ii, .Lfunc_end4-_Z28creatingMedianLogNormalFramePfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3944
; NumSgprs: 43
; NumVgprs: 54
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 54
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26creatingStdvLogNormalFramePfS_S_ii ; -- Begin function _Z26creatingStdvLogNormalFramePfS_S_ii
	.globl	_Z26creatingStdvLogNormalFramePfS_S_ii
	.p2align	8
	.type	_Z26creatingStdvLogNormalFramePfS_S_ii,@function
_Z26creatingStdvLogNormalFramePfS_S_ii: ; @_Z26creatingStdvLogNormalFramePfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB5_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v3, 31, v2
	s_cmp_lt_i32 s3, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_cbranch_scc1 .LBB5_4
; %bb.2:                                ; %.lr.ph
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s8, s3
	global_load_b32 v6, v[3:4], off
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
.LBB5_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s8, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s8, 0
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_load_b32 v3, v[7:8], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v3, v3
	v_cvt_f64_f32_e32 v[7:8], v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[7:8]
	s_cbranch_scc0 .LBB5_3
	s_branch .LBB5_5
.LBB5_4:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
.LBB5_5:                                ; %Flow42
	s_waitcnt lgkmcnt(0)
	s_add_i32 s0, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, s0
	v_cvt_f64_f32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
	v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[2:3], v[4:5]
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v4, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v5, s0
	v_mul_f32_e32 v4, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB5_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26creatingStdvLogNormalFramePfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z26creatingStdvLogNormalFramePfS_S_ii, .Lfunc_end5-_Z26creatingStdvLogNormalFramePfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24CreateBlackAndWHiteFramePiS_PfS0_i ; -- Begin function _Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.globl	_Z24CreateBlackAndWHiteFramePiS_PfS0_i
	.p2align	8
	.type	_Z24CreateBlackAndWHiteFramePiS_PfS0_i,@function
_Z24CreateBlackAndWHiteFramePiS_PfS0_i: ; @_Z24CreateBlackAndWHiteFramePiS_PfS0_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB6_6
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v3
	v_cndmask_b32_e64 v5, 1.0, 0x4f800000, vcc_lo
	s_waitcnt vmcnt(1)
	v_dual_add_f32 v4, v4, v4 :: v_dual_mul_f32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v6, 0x4f800000, v4
	v_cmp_gt_f32_e64 s0, 0xf800000, v4
	v_log_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v6, s0
	v_sqrt_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x3f317217, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3f317217, v3, -v6
	v_add_nc_u32_e32 v7, -1, v5
	v_dual_fmamk_f32 v9, v3, 0x3377d1cf, v9 :: v_dual_add_nc_u32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v7, v5, v4
	v_fma_f32 v11, -v8, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v10
	v_cndmask_b32_e64 v5, v5, v7, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cmp_lt_f32_e64 s1, 0, v11
	v_cndmask_b32_e64 v7, 0, 0x41b17218, vcc_lo
	v_add_f32_e32 v6, v6, v9
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
	v_cndmask_b32_e64 v5, v5, v8, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	v_dual_mul_f32 v6, 0x37800000, v5 :: v_dual_sub_f32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v6, s0
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v2, v3, v2 :: v_dual_cndmask_b32 v3, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v4, null, v3, v3, v2
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v2, v3, v2
	v_mul_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v7, v6
	v_fmac_f32_e32 v7, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v7, v6
	v_div_fmas_f32 v4, v4, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v4, v3, v2
                                        ; implicit-def: $vgpr3
	v_cmp_nlt_f32_e64 s0, |v2|, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB6_3
; %bb.2:
	s_mov_b32 s1, 0x378e98ab
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, |v2|, s1, 0xb9c68948
	v_fma_f32 v3, |v2|, v3, 0x3b7cd369
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, |v2|, v3, 0xbcc618b2
	v_fma_f32 v3, |v2|, v3, 0x3dda74e4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, |v2|, v3, 0x3f228afd
	v_fma_f32 v3, |v2|, v3, 0x3e03c728
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, |v2|, v3, |v2|
	v_mul_f32_e32 v4, 0xbfb8aa3b, v3
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0xbfb8aa3b, v3, -v4
	v_rndne_f32_e32 v6, v4
	v_dual_fmamk_f32 v5, v3, 0xb2a5705f, v5 :: v_dual_sub_f32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v5
	v_cvt_i32_f32_e32 v5, v6
	v_exp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v3
	v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v3, 1.0, v3
.LBB6_3:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
; %bb.4:
	v_mul_f32_e32 v3, v2, v2
	s_mov_b32 s1, 0xba1345e1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fmaak_f32 v4, s1, v3, 0x3ba10414
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v3, v4, 0xbcdac9b8
	v_fmaak_f32 v4, v3, v4, 0x3de703be
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v3, v4, 0xbec09330
	v_fmaak_f32 v3, v3, v4, 0x3e0375d0
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v3, |v2|, v3, |v2|
; %bb.5:                                ; %_ZL4erfff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v3, v2
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_fma_f32 v2, v2, 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 2.0, v2
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB6_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24CreateBlackAndWHiteFramePiS_PfS0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z24CreateBlackAndWHiteFramePiS_PfS0_i, .Lfunc_end6-_Z24CreateBlackAndWHiteFramePiS_PfS0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 916
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"\nError no index found\n"
	.size	.str, 23

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22creatingMeanPixelFramePfPiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22creatingMeanPixelFramePfPiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23creatingLogNormalFramesPfPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23creatingLogNormalFramesPfPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26creatingMeanLogNormalFramePfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26creatingMeanLogNormalFramePfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         104
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28creatingMedianLogNormalFramePfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     43
    .sgpr_spill_count: 0
    .symbol:         _Z28creatingMedianLogNormalFramePfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     54
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
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      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26creatingStdvLogNormalFramePfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26creatingStdvLogNormalFramePfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
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      - .offset:         52
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        .value_kind:     hidden_group_size_z
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        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
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        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24CreateBlackAndWHiteFramePiS_PfS0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24CreateBlackAndWHiteFramePiS_PfS0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
