//MatrixMult.cu
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>

__global__ void gpu_sort(int *a,int *b,int *c, int N) {
	int tid = threadIdx.x + blockDim.x * blockIdx.x; 
	int count = 0;
	int d;
		for(d=0;d<N;d++) {
			if(a[d] < a[tid]) {
				count++;
			}
		}
		c[count] = a[tid];
	
}


int main(int argc, char *argv[])  {
	int i, j; 							// loop counters
	int Grid_Dim_x=1, Grid_Dim_y=1;		//Grid structure values
	int Block_Dim_x=1, Block_Dim_y=1;		//Block structure values
	int noThreads_x, noThreads_y;			// number of threads available in device, each dimension
	int noThreads_block;					// number of threads in a block
	int N = 10;  						// size of array in each dimension
	int B;
	int T;
	int *a,*b,*c,*d;
	int *dev_a, *dev_b, *dev_c;
	int size;							// number of bytes in arrays
	cudaEvent_t start, stop;     				// using cuda events to measure time
	float elapsed_time_ms;       			// which is applicable for asynchronous code also
	cudaEventCreate(&start);		
	cudaEventCreate(&stop);


/* --------------------ENTER INPUT PARAMETERS AND ALLOCATE DATA -----------------------*/
							// keyboard input

	printf("Enter the value for N: ");
	scanf("%d", &N);
//takes in input
	int valid = 0;
	while(valid == 0) {

		printf("Enter the number of blocks: ");
		scanf("%d", &B);

		printf("Enter the number of threads: ");
		scanf("%d", &T);

		if(B > 1024 || T > 1024 || B*T < N) {
			printf("Invlaid input entered.\n");
		} else {
			valid = 1;
			Grid_Dim_x = B;
			Block_Dim_x = T;		//puts the size of blocks and thread in for the dim3
		}
	}


	
	dim3 Grid(Grid_Dim_x, Grid_Dim_x);	//Grid structure
	dim3 Block(Block_Dim_x,Block_Dim_y);	//Block structure, threads/block limited by specific device
	size = N * N * sizeof(int);				// number of bytes in total in arrays

	a = (int*) malloc(size);					//dynamically allocated memory for arrays on host
	b = (int*) malloc(size);
	c = (int*) malloc(size);					// results from GPU
	d = (int*) malloc(size);				// results from CPU
							// load arrays with some numbers

	srand(3); //initialize random number generator
	
	for (i=0; i < N; i++) { //load array with numbers
		a[i] = (int)rand(); 
	}


	cudaMalloc((void**)&dev_a, size);			// allocate memory on device
	cudaMalloc((void**)&dev_b, size);
	cudaMalloc((void**)&dev_c, size);

	cudaMemcpy(dev_a, a , size ,cudaMemcpyHostToDevice);
	cudaMemcpy(dev_b, b , size ,cudaMemcpyHostToDevice);

	cudaEventRecord(start, 0); 			// here start time, after memcpy

	gpu_sort<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
	cudaMemcpy(c, dev_c, size , cudaMemcpyDeviceToHost);

	cudaEventRecord(stop, 0);     			// measuse end time
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsed_time_ms, start, stop );

	printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms);
	double gpuTime = elapsed_time_ms; 

/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/

	cudaEventRecord(start, 0);			// use same timing*

	//cpu_matrixmult(a,b,d,N);				// do calculation on host
//sequential rank sort
	int k;
	for(k=0;k<N;k++) {
		int count = 0;
		int d;
		for(d=0;d<N;d++) {
			if(a[d] < a[k]) {
				count++;
			}
		}
		b[count] = a[k];
		count = 0;
	}


	cudaEventRecord(stop, 0);     		// measure end time
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsed_time_ms, start, stop );

	printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms);  // exe. time
	double cpuTime = elapsed_time_ms;

/* ------------------- check device creates correct results -----------------*/
/*
	printf("Initial Array: \n");
	int h;
	for(h=0;h<N;h++) {
		printf("%d ", a[h]);
	}

	printf("\n");
/*
	printf("Sequential Rank Sort: \n");
	
	for(k=0;k<N;k++) {
		int count = 0;
		int d;
		for(d=0;d<N;d++) {
			if(a[d] < a[k]) {
				count++;
			}
		}
		b[count] = a[k];
		count = 0;
	}

	for(h=0;h<N;h++) {
		printf("%d ", b[h]);
	}

printf("Parallel Rank Sort\n");
	for(h=0;h<N;h++) {
		printf("%d ", c[h]);
	}
*/

int error = 0;
int r;
for(r=0;r<N;r++) {
	if(b[r] != c[r]) {
		error = 1;
		break;
	}
}
if(error == 1) {
	printf("Parallel and sequential do not match.\n");
} else {
	printf("Seqential and parallel match.\n");
}
	printf("Speedup Factor: %lf\n", cpuTime/gpuTime);


/* --------------------- repeat program  ----------------------------------------*/
 								//  while loop to repeat calc with different parameters
/* --------------  clean up  ---------------------------------------*/
	free(a); free(b); free(c);
	cudaFree(dev_a);
	cudaFree(dev_b);
	cudaFree(dev_c);
	cudaEventDestroy(start);
	cudaEventDestroy(stop);
	return 0;
}


	.file	"tmpxft_0028ee0c_00000000-6_RS.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i
	.type	_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8gpu_sortPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i
	.globl	_Z8gpu_sortPiS_S_i
	.type	_Z8gpu_sortPiS_S_i, @function
_Z8gpu_sortPiS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2053:
	.size	_Z8gpu_sortPiS_S_i, .-_Z8gpu_sortPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter the value for N: "
.LC1:
	.string	"%d"
.LC2:
	.string	"Enter the number of blocks: "
.LC3:
	.string	"Enter the number of threads: "
.LC4:
	.string	"Invlaid input entered.\n"
.LC5:
	.string	"Time to calculate results on GPU: %f ms.\n"
.LC6:
	.string	"Time to calculate results on CPU: %f ms.\n"
.LC7:
	.string	"Speedup Factor: %lf\n"
.LC8:
	.string	"Parallel and sequential do not match.\n"
.LC9:
	.string	"Seqential and parallel match.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	leaq	.LC2(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	leaq	.LC1(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	64(%rsp), %rdi
	movl	$10, 24(%rsp)
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	24(%rsp), %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
.L11:
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	28(%rsp), %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	32(%rsp), %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	28(%rsp), %eax
	cmpl	$1024, %eax
	jg	.L9
	movl	32(%rsp), %edx
	cmpl	$1024, %edx
	jg	.L9
	movl	%eax, %ecx
	movl	24(%rsp), %ebx
	imull	%edx, %ecx
	cmpl	%ebx, %ecx
	jge	.L10
.L9:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L11
.L10:
	imull	%ebx, %ebx
	movl	%eax, 80(%rsp)
	xorl	%r14d, %r14d
	movl	%eax, 84(%rsp)
	movabsq	$4294967297, %rax
	movl	%edx, 92(%rsp)
	sall	$2, %ebx
	movl	$1, 88(%rsp)
	movslq	%ebx, %rbx
	movq	%rax, 96(%rsp)
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$3, %edi
	movq	%rax, %r13
	call	srand@PLT
.L22:
	cmpl	%r14d, 24(%rsp)
	jle	.L30
	call	rand@PLT
	movl	%eax, 0(%rbp,%r14,4)
	incq	%r14
	jmp	.L22
.L30:
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movl	24(%rsp), %ecx
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z32__device_stub__Z8gpu_sortPiS_S_iPiS_S_i
.L13:
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	leaq	36(%rsp), %rbx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	cvtss2sd	36(%rsp), %xmm1
	movsd	%xmm1, 8(%rsp)
	call	cudaEventRecord@PLT
	movl	24(%rsp), %esi
	xorl	%edx, %edx
.L14:
	cmpl	%edx, %esi
	jle	.L31
	movl	0(%rbp,%rdx,4), %edi
	xorl	%ecx, %ecx
	xorl	%eax, %eax
.L16:
	cmpl	%edi, 0(%rbp,%rcx,4)
	jge	.L15
	incl	%eax
.L15:
	incq	%rcx
	cmpl	%ecx, %esi
	jg	.L16
	cltq
	incq	%rdx
	movl	%edi, (%r12,%rax,4)
	jmp	.L14
.L31:
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	24(%rsp), %edx
	xorl	%eax, %eax
	cvtss2sd	36(%rsp), %xmm2
	movq	%xmm2, %rbx
.L18:
	cmpl	%eax, %edx
	jle	.L32
	movl	(%r12,%rax,4), %ecx
	incq	%rax
	cmpl	-4(%r13,%rax,4), %ecx
	je	.L18
	leaq	.LC8(%rip), %rsi
	jmp	.L29
.L32:
	leaq	.LC9(%rip), %rsi
.L29:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movq	%rbx, %xmm0
	divsd	8(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	72(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$112, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z8gpu_sortPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8gpu_sortPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//MatrixMult.cu
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>

__global__ void gpu_sort(int *a,int *b,int *c, int N) {
	int tid = threadIdx.x + blockDim.x * blockIdx.x; 
	int count = 0;
	int d;
		for(d=0;d<N;d++) {
			if(a[d] < a[tid]) {
				count++;
			}
		}
		c[count] = a[tid];
	
}


int main(int argc, char *argv[])  {
	int i, j; 							// loop counters
	int Grid_Dim_x=1, Grid_Dim_y=1;		//Grid structure values
	int Block_Dim_x=1, Block_Dim_y=1;		//Block structure values
	int noThreads_x, noThreads_y;			// number of threads available in device, each dimension
	int noThreads_block;					// number of threads in a block
	int N = 10;  						// size of array in each dimension
	int B;
	int T;
	int *a,*b,*c,*d;
	int *dev_a, *dev_b, *dev_c;
	int size;							// number of bytes in arrays
	hipEvent_t start, stop;     				// using cuda events to measure time
	float elapsed_time_ms;       			// which is applicable for asynchronous code also
	hipEventCreate(&start);		
	hipEventCreate(&stop);


/* --------------------ENTER INPUT PARAMETERS AND ALLOCATE DATA -----------------------*/
							// keyboard input

	printf("Enter the value for N: ");
	scanf("%d", &N);
//takes in input
	int valid = 0;
	while(valid == 0) {

		printf("Enter the number of blocks: ");
		scanf("%d", &B);

		printf("Enter the number of threads: ");
		scanf("%d", &T);

		if(B > 1024 || T > 1024 || B*T < N) {
			printf("Invlaid input entered.\n");
		} else {
			valid = 1;
			Grid_Dim_x = B;
			Block_Dim_x = T;		//puts the size of blocks and thread in for the dim3
		}
	}


	
	dim3 Grid(Grid_Dim_x, Grid_Dim_x);	//Grid structure
	dim3 Block(Block_Dim_x,Block_Dim_y);	//Block structure, threads/block limited by specific device
	size = N * N * sizeof(int);				// number of bytes in total in arrays

	a = (int*) malloc(size);					//dynamically allocated memory for arrays on host
	b = (int*) malloc(size);
	c = (int*) malloc(size);					// results from GPU
	d = (int*) malloc(size);				// results from CPU
							// load arrays with some numbers

	srand(3); //initialize random number generator
	
	for (i=0; i < N; i++) { //load array with numbers
		a[i] = (int)rand(); 
	}


	hipMalloc((void**)&dev_a, size);			// allocate memory on device
	hipMalloc((void**)&dev_b, size);
	hipMalloc((void**)&dev_c, size);

	hipMemcpy(dev_a, a , size ,hipMemcpyHostToDevice);
	hipMemcpy(dev_b, b , size ,hipMemcpyHostToDevice);

	hipEventRecord(start, 0); 			// here start time, after memcpy

	gpu_sort<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
	hipMemcpy(c, dev_c, size , hipMemcpyDeviceToHost);

	hipEventRecord(stop, 0);     			// measuse end time
	hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsed_time_ms, start, stop );

	printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms);
	double gpuTime = elapsed_time_ms; 

/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/

	hipEventRecord(start, 0);			// use same timing*

	//cpu_matrixmult(a,b,d,N);				// do calculation on host
//sequential rank sort
	int k;
	for(k=0;k<N;k++) {
		int count = 0;
		int d;
		for(d=0;d<N;d++) {
			if(a[d] < a[k]) {
				count++;
			}
		}
		b[count] = a[k];
		count = 0;
	}


	hipEventRecord(stop, 0);     		// measure end time
	hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsed_time_ms, start, stop );

	printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms);  // exe. time
	double cpuTime = elapsed_time_ms;

/* ------------------- check device creates correct results -----------------*/
/*
	printf("Initial Array: \n");
	int h;
	for(h=0;h<N;h++) {
		printf("%d ", a[h]);
	}

	printf("\n");
/*
	printf("Sequential Rank Sort: \n");
	
	for(k=0;k<N;k++) {
		int count = 0;
		int d;
		for(d=0;d<N;d++) {
			if(a[d] < a[k]) {
				count++;
			}
		}
		b[count] = a[k];
		count = 0;
	}

	for(h=0;h<N;h++) {
		printf("%d ", b[h]);
	}

printf("Parallel Rank Sort\n");
	for(h=0;h<N;h++) {
		printf("%d ", c[h]);
	}
*/

int error = 0;
int r;
for(r=0;r<N;r++) {
	if(b[r] != c[r]) {
		error = 1;
		break;
	}
}
if(error == 1) {
	printf("Parallel and sequential do not match.\n");
} else {
	printf("Seqential and parallel match.\n");
}
	printf("Speedup Factor: %lf\n", cpuTime/gpuTime);


/* --------------------- repeat program  ----------------------------------------*/
 								//  while loop to repeat calc with different parameters
/* --------------  clean up  ---------------------------------------*/
	free(a); free(b); free(c);
	hipFree(dev_a);
	hipFree(dev_b);
	hipFree(dev_c);
	hipEventDestroy(start);
	hipEventDestroy(stop);
	return 0;
}


	.text
	.file	"RS.hip"
	.globl	_Z23__device_stub__gpu_sortPiS_S_i # -- Begin function _Z23__device_stub__gpu_sortPiS_S_i
	.type	_Z23__device_stub__gpu_sortPiS_S_i,@function
_Z23__device_stub__gpu_sortPiS_S_i:     # @_Z23__device_stub__gpu_sortPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8gpu_sortPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__gpu_sortPiS_S_i, .Lfunc_end0-_Z23__device_stub__gpu_sortPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	12(%rsp), %rbx
	movl	$10, (%rbx)
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	leaq	68(%rsp), %rbx
	leaq	64(%rsp), %r14
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	68(%rsp), %r12d
	cmpl	$1024, %r12d                    # imm = 0x400
	jg	.LBB1_4
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movl	64(%rsp), %ebp
	cmpl	$1024, %ebp                     # imm = 0x400
	jg	.LBB1_4
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	movl	%r12d, %eax
	imull	%ebp, %eax
	cmpl	12(%rsp), %eax
	jge	.LBB1_5
.LBB1_4:                                #   in Loop: Header=BB1_1 Depth=1
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	jmp	.LBB1_1
.LBB1_5:
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	$1, %rax
	imulq	%rax, %r12
	btsq	$32, %rbp
	movl	12(%rsp), %eax
	imull	%eax, %eax
	shll	$2, %eax
	movslq	%eax, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$3, %edi
	callq	srand
	cmpl	$0, 12(%rsp)
	jle	.LBB1_8
# %bb.6:                                # %.lr.ph.preheader
	xorl	%r15d, %r15d
.LBB1_7:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movl	%eax, (%rbx,%r15,4)
	incq	%r15
	movslq	12(%rsp), %rax
	cmpq	%rax, %r15
	jl	.LBB1_7
.LBB1_8:                                # %._crit_edge
	leaq	40(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	72(%rsp), %r15
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	40(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	12(%rsp), %ecx
	callq	_Z23__device_stub__gpu_sortPiS_S_i
.LBB1_10:
	movq	32(%rsp), %rsi
	movq	80(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	60(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	movss	(%r12), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 56(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB1_15
# %bb.11:                               # %.preheader.lr.ph
	xorl	%ecx, %ecx
.LBB1_12:                               # %.lr.ph76
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_13 Depth 2
	movl	(%rbx,%rcx,4), %edx
	xorl	%edi, %edi
	xorl	%esi, %esi
.LBB1_13:                               #   Parent Loop BB1_12 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorl	%r8d, %r8d
	cmpl	%edx, (%rbx,%rdi,4)
	setl	%r8b
	addl	%r8d, %esi
	incq	%rdi
	cmpq	%rdi, %rax
	jne	.LBB1_13
# %bb.14:                               # %._crit_edge77
                                        #   in Loop: Header=BB1_12 Depth=1
	movl	%esi, %esi
	movl	%edx, (%r14,%rsi,4)
	incq	%rcx
	cmpq	%rax, %rcx
	jne	.LBB1_12
.LBB1_15:                               # %._crit_edge79
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	60(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movss	(%r12), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 52(%rsp)                 # 4-byte Spill
	movl	12(%rsp), %eax
	movl	$.Lstr, %edi
	testl	%eax, %eax
	jle	.LBB1_20
# %bb.16:                               # %.lr.ph82.preheader
	xorl	%ecx, %ecx
.LBB1_18:                               # %.lr.ph82
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rcx,4), %edx
	cmpl	(%r15,%rcx,4), %edx
	jne	.LBB1_19
# %bb.17:                               #   in Loop: Header=BB1_18 Depth=1
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_18
	jmp	.LBB1_20
.LBB1_19:
	movl	$.Lstr.1, %edi
.LBB1_20:                               # %.critedge
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	52(%rsp), %xmm0                 # 4-byte Folded Reload
	cvtss2sd	56(%rsp), %xmm1                 # 4-byte Folded Reload
	divsd	%xmm1, %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8gpu_sortPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8gpu_sortPiS_S_i,@object      # @_Z8gpu_sortPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z8gpu_sortPiS_S_i
	.p2align	3, 0x0
_Z8gpu_sortPiS_S_i:
	.quad	_Z23__device_stub__gpu_sortPiS_S_i
	.size	_Z8gpu_sortPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Enter the value for N: "
	.size	.L.str, 24

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Enter the number of blocks: "
	.size	.L.str.2, 29

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Enter the number of threads: "
	.size	.L.str.3, 30

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Time to calculate results on GPU: %f ms.\n"
	.size	.L.str.5, 42

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Time to calculate results on CPU: %f ms.\n"
	.size	.L.str.6, 42

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Speedup Factor: %lf\n"
	.size	.L.str.9, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8gpu_sortPiS_S_i"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Seqential and parallel match."
	.size	.Lstr, 30

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Parallel and sequential do not match."
	.size	.Lstr.1, 38

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Invlaid input entered."
	.size	.Lstr.2, 23

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__gpu_sortPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8gpu_sortPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8gpu_sortPiS_S_i      ; -- Begin function _Z8gpu_sortPiS_S_i
	.globl	_Z8gpu_sortPiS_S_i
	.p2align	8
	.type	_Z8gpu_sortPiS_S_i,@function
_Z8gpu_sortPiS_S_i:                     ; @_Z8gpu_sortPiS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_load_b32 s4, s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_cmp_lt_i32 s4, 1
	global_load_b32 v2, v[0:1], off
	s_cbranch_scc1 .LBB0_4
; %bb.1:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v0, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s5, s[2:3], 0x0
	s_add_i32 s4, s4, -1
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s4, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, s5, v2
	v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	s_cbranch_scc1 .LBB0_2
; %bb.3:                                ; %._crit_edge.loopexit
	v_mov_b32_e32 v1, 0
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
.LBB0_5:                                ; %._crit_edge
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8gpu_sortPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8gpu_sortPiS_S_i, .Lfunc_end0-_Z8gpu_sortPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 220
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8gpu_sortPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8gpu_sortPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
