//------------------------------------------------------------------------------
//
// Name:       vadd.cu
//
// Purpose:    CUDA implementation of VADD
//
// HISTORY:    Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------

#include <stdio.h>
#include <cuda.h>

#define TOL (0.001)   // tolerance used in floating point comparisons
#define LENGTH (1024) // length of vectors a, b, and c

/*************************************************************************************
 * CUDA kernel
 ************************************************************************************/

__global__ void vadd(const float* a, const float* b, float* c, const unsigned int count)
{
    int i = blockDim.x * blockIdx.x + threadIdx.x;
    if (i < count)
    {
        c[i] = a[i] + b[i];
    }
}

int main()
{
    float h_a[LENGTH];      // a vector
    float h_b[LENGTH];      // b vector
    float h_c[LENGTH];      // c vector (a+b) returned from the compute device
    float *d_a, *d_b, *d_c; // CUDA memory
    unsigned int correct;   // number of correct results

    // Fill vectors a and b with random float values
    int i = 0;
    int count = LENGTH;
    for (i = 0; i < count; i++)
    {
        h_a[i] = rand() / (float)RAND_MAX;
        h_b[i] = rand() / (float)RAND_MAX;
    }

    // Allocate CUDA memory
    cudaMalloc(&d_a, sizeof(float) * LENGTH);
    cudaMalloc(&d_b, sizeof(float) * LENGTH);
    cudaMalloc(&d_c, sizeof(float) * LENGTH);

    // Write buffers a and b to GPU memory
    cudaMemcpy(d_a, h_a, sizeof(float) * LENGTH, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, sizeof(float) * LENGTH, cudaMemcpyHostToDevice);

    dim3 numBlocks(LENGTH);
    dim3 numThreads(1);
    vadd<<<numBlocks, numThreads>>>(d_a, d_b, d_c, LENGTH);

    // Copy result array back to host memory
    cudaMemcpy(h_c, d_c, sizeof(float) * LENGTH, cudaMemcpyDeviceToHost);

    // Test the results
    correct = 0;
    float tmp;

    for (i = 0; i < count; i++)
    {
        tmp = h_a[i] + h_b[i];     // assign element i of a+b to tmp
        tmp -= h_c[i];             // compute deviation of expected and output result
        if (tmp * tmp < TOL * TOL) // correct if square deviation is less than tolerance squared
            correct++;
        else
        {
            printf(" tmp %f h_a %f h_b %f h_c %f \n", tmp, h_a[i], h_b[i], h_c[i]);
        }
    }

    // summarize results
    printf("C = A+B:  %d out of %d results were correct.\n", correct, count);

    return EXIT_SUCCESS;
}

	.file	"tmpxft_00320a0e_00000000-6_vadd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj
	.type	_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj, @function
_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4vaddPKfS0_Pfj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj, .-_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj
	.globl	_Z4vaddPKfS0_Pfj
	.type	_Z4vaddPKfS0_Pfj, @function
_Z4vaddPKfS0_Pfj:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj
	.cfi_endproc
.LFE2053:
	.size	_Z4vaddPKfS0_Pfj, .-_Z4vaddPKfS0_Pfj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	" tmp %f h_a %f h_b %f h_c %f \n"
.LC3:
	.string	"C = A+B:  %d out of %d results were correct.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$4096, %rsp
	.cfi_def_cfa_offset 4144
	orq	$0, (%rsp)
	subq	$4096, %rsp
	.cfi_def_cfa_offset 8240
	orq	$0, (%rsp)
	subq	$4096, %rsp
	.cfi_def_cfa_offset 12336
	orq	$0, (%rsp)
	subq	$64, %rsp
	.cfi_def_cfa_offset 12400
	xorl	%ebx, %ebx
	movq	%fs:40, %rax
	movq	%rax, 12344(%rsp)
	xorl	%eax, %eax
.L9:
	call	rand@PLT
	leaq	56(%rsp), %rbp
	leaq	4152(%rsp), %r12
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, 56(%rsp,%rbx)
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, 4152(%rsp,%rbx)
	addq	$4, %rbx
	cmpq	$4096, %rbx
	jne	.L9
	leaq	8(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movl	$4194305, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdi
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	movl	$1, %esi
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1024, %ecx
	movq	8(%rsp), %rdi
	call	_Z30__device_stub__Z4vaddPKfS0_PfjPKfS0_Pfj
.L10:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
	leaq	8248(%rsp), %r13
	movl	$4096, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
.L14:
	movss	0(%rbp,%rbx), %xmm1
	movss	(%r12,%rbx), %xmm2
	movss	0(%r13,%rbx), %xmm3
	movsd	.LC1(%rip), %xmm5
	movaps	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	subss	%xmm3, %xmm0
	movaps	%xmm0, %xmm4
	mulss	%xmm0, %xmm4
	cvtss2sd	%xmm4, %xmm4
	comisd	%xmm4, %xmm5
	jbe	.L19
	incl	%r14d
	jmp	.L13
.L19:
	movl	$2, %edi
	movb	$4, %al
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm3, %xmm3
	leaq	.LC2(%rip), %rsi
	cvtss2sd	%xmm2, %xmm2
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
.L13:
	addq	$4, %rbx
	cmpq	$4096, %rbx
	jne	.L14
	xorl	%eax, %eax
	movl	$1024, %ecx
	movl	%r14d, %edx
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
	movq	12344(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$12352, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z4vaddPKfS0_Pfj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4vaddPKfS0_Pfj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	-1598689907
	.long	1051772663
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//------------------------------------------------------------------------------
//
// Name:       vadd.cu
//
// Purpose:    CUDA implementation of VADD
//
// HISTORY:    Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------

#include <stdio.h>
#include <hip/hip_runtime.h>

#define TOL (0.001)   // tolerance used in floating point comparisons
#define LENGTH (1024) // length of vectors a, b, and c

/*************************************************************************************
 * CUDA kernel
 ************************************************************************************/

__global__ void vadd(const float* a, const float* b, float* c, const unsigned int count)
{
    int i = blockDim.x * blockIdx.x + threadIdx.x;
    if (i < count)
    {
        c[i] = a[i] + b[i];
    }
}

int main()
{
    float h_a[LENGTH];      // a vector
    float h_b[LENGTH];      // b vector
    float h_c[LENGTH];      // c vector (a+b) returned from the compute device
    float *d_a, *d_b, *d_c; // CUDA memory
    unsigned int correct;   // number of correct results

    // Fill vectors a and b with random float values
    int i = 0;
    int count = LENGTH;
    for (i = 0; i < count; i++)
    {
        h_a[i] = rand() / (float)RAND_MAX;
        h_b[i] = rand() / (float)RAND_MAX;
    }

    // Allocate CUDA memory
    hipMalloc(&d_a, sizeof(float) * LENGTH);
    hipMalloc(&d_b, sizeof(float) * LENGTH);
    hipMalloc(&d_c, sizeof(float) * LENGTH);

    // Write buffers a and b to GPU memory
    hipMemcpy(d_a, h_a, sizeof(float) * LENGTH, hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b, sizeof(float) * LENGTH, hipMemcpyHostToDevice);

    dim3 numBlocks(LENGTH);
    dim3 numThreads(1);
    vadd<<<numBlocks, numThreads>>>(d_a, d_b, d_c, LENGTH);

    // Copy result array back to host memory
    hipMemcpy(h_c, d_c, sizeof(float) * LENGTH, hipMemcpyDeviceToHost);

    // Test the results
    correct = 0;
    float tmp;

    for (i = 0; i < count; i++)
    {
        tmp = h_a[i] + h_b[i];     // assign element i of a+b to tmp
        tmp -= h_c[i];             // compute deviation of expected and output result
        if (tmp * tmp < TOL * TOL) // correct if square deviation is less than tolerance squared
            correct++;
        else
        {
            printf(" tmp %f h_a %f h_b %f h_c %f \n", tmp, h_a[i], h_b[i], h_c[i]);
        }
    }

    // summarize results
    printf("C = A+B:  %d out of %d results were correct.\n", correct, count);

    return EXIT_SUCCESS;
}

	.text
	.file	"vadd.hip"
	.globl	_Z19__device_stub__vaddPKfS0_Pfj # -- Begin function _Z19__device_stub__vaddPKfS0_Pfj
	.type	_Z19__device_stub__vaddPKfS0_Pfj,@function
_Z19__device_stub__vaddPKfS0_Pfj:       # @_Z19__device_stub__vaddPKfS0_Pfj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4vaddPKfS0_Pfj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__vaddPKfS0_Pfj, .Lfunc_end0-_Z19__device_stub__vaddPKfS0_Pfj
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x30000000                      # float 4.65661287E-10
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_1:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$12328, %rsp                    # imm = 0x3028
	.cfi_def_cfa_offset 12352
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	xorl	%ebx, %ebx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm0
	movss	%xmm0, 4128(%rsp,%rbx,4)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, 32(%rsp,%rbx,4)
	incq	%rbx
	cmpq	$1024, %rbx                     # imm = 0x400
	jne	.LBB1_1
# %bb.2:
	leaq	24(%rsp), %rbx
	movl	$4096, %esi                     # imm = 0x1000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r14
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	4128(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	leaq	32(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	leaq	1023(%rdx), %rdi
	xorl	%ebx, %ebx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z19__device_stub__vaddPKfS0_Pfj
.LBB1_4:
	movq	8(%rsp), %rsi
	leaq	8224(%rsp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$2, %ecx
	callq	hipMemcpy
	movsd	.LCPI1_1(%rip), %xmm5           # xmm5 = mem[0],zero
	xorl	%r14d, %r14d
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	movss	4128(%rsp,%r14,4), %xmm1        # xmm1 = mem[0],zero,zero,zero
	movss	32(%rsp,%r14,4), %xmm2          # xmm2 = mem[0],zero,zero,zero
	movaps	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	movss	8224(%rsp,%r14,4), %xmm3        # xmm3 = mem[0],zero,zero,zero
	subss	%xmm3, %xmm0
	movaps	%xmm0, %xmm4
	mulss	%xmm0, %xmm4
	cvtss2sd	%xmm4, %xmm4
	ucomisd	%xmm4, %xmm5
	jbe	.LBB1_7
# %bb.6:                                #   in Loop: Header=BB1_5 Depth=1
	incl	%ebx
	jmp	.LBB1_8
.LBB1_7:                                #   in Loop: Header=BB1_5 Depth=1
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm3
	movl	$.L.str, %edi
	movb	$4, %al
	callq	printf
	movsd	.LCPI1_1(%rip), %xmm5           # xmm5 = mem[0],zero
.LBB1_8:                                #   in Loop: Header=BB1_5 Depth=1
	incq	%r14
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB1_5
# %bb.9:
	movl	$.L.str.1, %edi
	movl	%ebx, %esi
	movl	$1024, %edx                     # imm = 0x400
	xorl	%eax, %eax
	callq	printf
	xorl	%eax, %eax
	addq	$12328, %rsp                    # imm = 0x3028
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4vaddPKfS0_Pfj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4vaddPKfS0_Pfj,@object        # @_Z4vaddPKfS0_Pfj
	.section	.rodata,"a",@progbits
	.globl	_Z4vaddPKfS0_Pfj
	.p2align	3, 0x0
_Z4vaddPKfS0_Pfj:
	.quad	_Z19__device_stub__vaddPKfS0_Pfj
	.size	_Z4vaddPKfS0_Pfj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" tmp %f h_a %f h_b %f h_c %f \n"
	.size	.L.str, 31

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"C = A+B:  %d out of %d results were correct.\n"
	.size	.L.str.1, 46

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4vaddPKfS0_Pfj"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__vaddPKfS0_Pfj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4vaddPKfS0_Pfj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4vaddPKfS0_Pfj        ; -- Begin function _Z4vaddPKfS0_Pfj
	.globl	_Z4vaddPKfS0_Pfj
	.p2align	8
	.type	_Z4vaddPKfS0_Pfj,@function
_Z4vaddPKfS0_Pfj:                       ; @_Z4vaddPKfS0_Pfj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4vaddPKfS0_Pfj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4vaddPKfS0_Pfj, .Lfunc_end0-_Z4vaddPKfS0_Pfj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4vaddPKfS0_Pfj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4vaddPKfS0_Pfj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
