#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda_runtime.h>

typedef struct
{
	int len;
	// host 
	float *h_input, *h_output;
	// device 
	float *d_input, *d_output;
	// cuda stream
	cudaStream_t stream;

} MGPUdata;


__global__ void testKernel(float*x, float*y, int len)
{
	int tid = threadIdx.x + blockIdx.x * blockDim.x;

	if(tid < len) {
		float sum = x[tid];
		int iter = 0;

		while(iter++ < len) {
			sum += 1;
		}
		y[tid] = sum;
	}

}

int main(int argc, char **argv)
{
	int GpuNum = 1;
	cudaGetDeviceCount(&GpuNum);
	printf("CUDA device = %i\n", GpuNum);

	const int N = 100000; // 100K
	MGPUdata mgpu[GpuNum];

	for(int i=0; i<GpuNum; i++) {
		mgpu[i].len	= N;
	}

	// set up for each gpu
	for(int i=0; i<GpuNum; i++) {
		cudaSetDevice(i); // NOTE: needed for each device

		// create streams for each gpu
		cudaStreamCreate(&mgpu[i].stream);
		// host
		cudaMallocHost(&mgpu[i].h_input,  sizeof(float) * mgpu[i].len);
		cudaMallocHost(&mgpu[i].h_output, sizeof(float) * mgpu[i].len);
		// device
		cudaMalloc(&mgpu[i].d_input,  sizeof(float) * mgpu[i].len);
		cudaMalloc(&mgpu[i].d_output, sizeof(float) * mgpu[i].len);
		// initialize
		for (int j=0; j<mgpu[i].len; j++)
		{
			mgpu[i].h_input[j] = 0.; 
		}

	}

	dim3 block = dim3(128, 1, 1);
	dim3 grid  = dim3((N + block.x - 1)/ block.x, 1, 1);

	// data transfer  + kernel
	for(int i=0; i<GpuNum; i++)
	{
		cudaSetDevice(i);
		// h2d
		cudaMemcpyAsync(mgpu[i].d_input, mgpu[i].h_input, mgpu[i].len * sizeof(float), cudaMemcpyHostToDevice, mgpu[i].stream);
		// kernel
		testKernel <<< grid, block, 0, mgpu[i].stream >>>(mgpu[i].d_input, mgpu[i].d_output, mgpu[i].len);
		// d2h
		cudaMemcpyAsync(mgpu[i].h_output, mgpu[i].d_output,mgpu[i].len * sizeof(float), cudaMemcpyDeviceToHost, mgpu[i].stream);
	}



	// cleanup
	for(int i=0; i<GpuNum; i++) {
		cudaSetDevice(i);
		cudaStreamSynchronize(mgpu[i].stream);

		cudaFreeHost(mgpu[i].h_input);
		cudaFreeHost(mgpu[i].h_output);
		cudaFree(mgpu[i].d_input);
		cudaFree(mgpu[i].d_output);
		cudaStreamDestroy(mgpu[i].stream);
	}


	return 0;
}

	.file	"tmpxft_0027ece4_00000000-6_stream_multiGPU.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z10testKernelPfS_iPfS_i
	.type	_Z33__device_stub__Z10testKernelPfS_iPfS_i, @function
_Z33__device_stub__Z10testKernelPfS_iPfS_i:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10testKernelPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z33__device_stub__Z10testKernelPfS_iPfS_i, .-_Z33__device_stub__Z10testKernelPfS_iPfS_i
	.globl	_Z10testKernelPfS_i
	.type	_Z10testKernelPfS_i, @function
_Z10testKernelPfS_i:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10testKernelPfS_iPfS_i
	.cfi_endproc
.LFE3661:
	.size	_Z10testKernelPfS_i, .-_Z10testKernelPfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA device = %i\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r14
	pushq	%r13
	leaq	-68(%rbp), %rdi
	pushq	%r12
	pushq	%rbx
	subq	$48, %rsp
	.cfi_offset 14, -24
	.cfi_offset 13, -32
	.cfi_offset 12, -40
	.cfi_offset 3, -48
	movq	%fs:40, %rax
	movq	%rax, -40(%rbp)
	xorl	%eax, %eax
	movl	$1, -68(%rbp)
	call	cudaGetDeviceCount@PLT
	movl	-68(%rbp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC0(%rip), %rsi
	call	__printf_chk@PLT
	movslq	-68(%rbp), %rax
	movq	%rsp, %rcx
	movq	%rax, %rdx
	imulq	$48, %rax, %rax
	movq	%rax, %rsi
	andq	$-4096, %rsi
	subq	%rsi, %rcx
.L9:
	cmpq	%rcx, %rsp
	je	.L10
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L9
.L10:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L11
	orq	$0, -8(%rsp,%rax)
.L11:
	movq	%rsp, %rbx
	xorl	%eax, %eax
.L12:
	cmpl	%eax, %edx
	jle	.L28
	imulq	$48, %rax, %rcx
	incq	%rax
	movl	$100000, (%rbx,%rcx)
	jmp	.L12
.L28:
	leaq	8(%rbx), %r13
	xorl	%r14d, %r14d
	movq	%r13, %r12
.L14:
	cmpl	%r14d, -68(%rbp)
	jle	.L29
	movl	%r14d, %edi
	call	cudaSetDevice@PLT
	leaq	32(%r12), %rdi
	call	cudaStreamCreate@PLT
	movslq	-8(%r12), %rsi
	xorl	%edx, %edx
	movq	%r12, %rdi
	salq	$2, %rsi
	call	cudaHostAlloc@PLT
	movslq	-8(%r12), %rsi
	xorl	%edx, %edx
	leaq	8(%r12), %rdi
	salq	$2, %rsi
	call	cudaHostAlloc@PLT
	movslq	-8(%r12), %rsi
	leaq	16(%r12), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	-8(%r12), %rsi
	leaq	24(%r12), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	-8(%r12), %edx
	xorl	%eax, %eax
.L15:
	cmpl	%eax, %edx
	jle	.L30
	movq	(%r12), %rcx
	movl	$0x00000000, (%rcx,%rax,4)
	incq	%rax
	jmp	.L15
.L30:
	incl	%r14d
	addq	$48, %r12
	jmp	.L14
.L29:
	movabsq	$4294967297, %rax
	movl	$1, -44(%rbp)
	xorl	%r12d, %r12d
	movq	%rax, -60(%rbp)
	addq	$781, %rax
	movq	%rax, -52(%rbp)
.L18:
	cmpl	%r12d, -68(%rbp)
	jle	.L31
	movl	%r12d, %edi
	call	cudaSetDevice@PLT
	movslq	(%rbx), %rdx
	movq	8(%rbx), %rsi
	movl	$1, %ecx
	movq	24(%rbx), %rdi
	movq	40(%rbx), %r8
	salq	$2, %rdx
	call	cudaMemcpyAsync@PLT
	movl	-56(%rbp), %ecx
	movq	40(%rbx), %r9
	xorl	%r8d, %r8d
	movq	-52(%rbp), %rdi
	movl	-44(%rbp), %esi
	movl	$128, -64(%rbp)
	movq	-64(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	32(%rbx), %rsi
	movq	24(%rbx), %rdi
	movl	(%rbx), %edx
	call	_Z33__device_stub__Z10testKernelPfS_iPfS_i
.L19:
	movslq	(%rbx), %rdx
	movq	32(%rbx), %rsi
	movl	$2, %ecx
	incl	%r12d
	movq	16(%rbx), %rdi
	movq	40(%rbx), %r8
	addq	$48, %rbx
	salq	$2, %rdx
	call	cudaMemcpyAsync@PLT
	jmp	.L18
.L31:
	xorl	%ebx, %ebx
.L21:
	cmpl	%ebx, -68(%rbp)
	jle	.L32
	movl	%ebx, %edi
	addq	$48, %r13
	incl	%ebx
	call	cudaSetDevice@PLT
	movq	-16(%r13), %rdi
	call	cudaStreamSynchronize@PLT
	movq	-48(%r13), %rdi
	call	cudaFreeHost@PLT
	movq	-40(%r13), %rdi
	call	cudaFreeHost@PLT
	movq	-32(%r13), %rdi
	call	cudaFree@PLT
	movq	-24(%r13), %rdi
	call	cudaFree@PLT
	movq	-16(%r13), %rdi
	call	cudaStreamDestroy@PLT
	jmp	.L21
.L32:
	movq	-40(%rbp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	leaq	-32(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z10testKernelPfS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10testKernelPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>

typedef struct
{
	int len;
	// host 
	float *h_input, *h_output;
	// device 
	float *d_input, *d_output;
	// cuda stream
	hipStream_t stream;

} MGPUdata;


__global__ void testKernel(float*x, float*y, int len)
{
	int tid = threadIdx.x + blockIdx.x * blockDim.x;

	if(tid < len) {
		float sum = x[tid];
		int iter = 0;

		while(iter++ < len) {
			sum += 1;
		}
		y[tid] = sum;
	}

}

int main(int argc, char **argv)
{
	int GpuNum = 1;
	hipGetDeviceCount(&GpuNum);
	printf("CUDA device = %i\n", GpuNum);

	const int N = 100000; // 100K
	MGPUdata mgpu[GpuNum];

	for(int i=0; i<GpuNum; i++) {
		mgpu[i].len	= N;
	}

	// set up for each gpu
	for(int i=0; i<GpuNum; i++) {
		hipSetDevice(i); // NOTE: needed for each device

		// create streams for each gpu
		hipStreamCreate(&mgpu[i].stream);
		// host
		hipHostMalloc(&mgpu[i].h_input,  sizeof(float) * mgpu[i].len, hipHostMallocDefault);
		hipHostMalloc(&mgpu[i].h_output, sizeof(float) * mgpu[i].len, hipHostMallocDefault);
		// device
		hipMalloc(&mgpu[i].d_input,  sizeof(float) * mgpu[i].len);
		hipMalloc(&mgpu[i].d_output, sizeof(float) * mgpu[i].len);
		// initialize
		for (int j=0; j<mgpu[i].len; j++)
		{
			mgpu[i].h_input[j] = 0.; 
		}

	}

	dim3 block = dim3(128, 1, 1);
	dim3 grid  = dim3((N + block.x - 1)/ block.x, 1, 1);

	// data transfer  + kernel
	for(int i=0; i<GpuNum; i++)
	{
		hipSetDevice(i);
		// h2d
		hipMemcpyAsync(mgpu[i].d_input, mgpu[i].h_input, mgpu[i].len * sizeof(float), hipMemcpyHostToDevice, mgpu[i].stream);
		// kernel
		testKernel <<< grid, block, 0, mgpu[i].stream >>>(mgpu[i].d_input, mgpu[i].d_output, mgpu[i].len);
		// d2h
		hipMemcpyAsync(mgpu[i].h_output, mgpu[i].d_output,mgpu[i].len * sizeof(float), hipMemcpyDeviceToHost, mgpu[i].stream);
	}



	// cleanup
	for(int i=0; i<GpuNum; i++) {
		hipSetDevice(i);
		hipStreamSynchronize(mgpu[i].stream);

		hipHostFree(mgpu[i].h_input);
		hipHostFree(mgpu[i].h_output);
		hipFree(mgpu[i].d_input);
		hipFree(mgpu[i].d_output);
		hipStreamDestroy(mgpu[i].stream);
	}


	return 0;
}

	.text
	.file	"stream_multiGPU.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__testKernelPfS_i # -- Begin function _Z25__device_stub__testKernelPfS_i
	.type	_Z25__device_stub__testKernelPfS_i,@function
_Z25__device_stub__testKernelPfS_i:     # @_Z25__device_stub__testKernelPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10testKernelPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__testKernelPfS_i, .Lfunc_end0-_Z25__device_stub__testKernelPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	leaq	-44(%rbp), %rbx
	movl	$1, (%rbx)
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	movl	(%rbx), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rsp, %r12
	movl	(%rbx), %eax
	movq	%rsp, %r13
	shlq	$4, %rax
	leaq	(%rax,%rax,2), %rax
	subq	%rax, %r13
	movq	%r13, %rsp
	movl	(%rbx), %eax
	testl	%eax, %eax
	jle	.LBB1_16
# %bb.1:                                # %.lr.ph.preheader
	movq	%rax, %rcx
	shlq	$4, %rcx
	leaq	(%rcx,%rcx,2), %rcx
	xorl	%edx, %edx
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$100000, (%r13,%rdx)            # imm = 0x186A0
	addq	$48, %rdx
	cmpq	%rdx, %rcx
	jne	.LBB1_2
# %bb.3:                                # %.preheader58
	testl	%eax, %eax
	jle	.LBB1_16
# %bb.4:                                # %.lr.ph63.preheader
	leaq	24(%r13), %rbx
	xorl	%r14d, %r14d
.LBB1_5:                                # %.lr.ph63
                                        # =>This Inner Loop Header: Depth=1
	movl	%r14d, %edi
	callq	hipSetDevice
	leaq	16(%rbx), %rdi
	callq	hipStreamCreate
	leaq	-16(%rbx), %r15
	movslq	-24(%rbx), %rsi
	shlq	$2, %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	-8(%rbx), %rdi
	movslq	-24(%rbx), %rsi
	shlq	$2, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	-24(%rbx), %rsi
	shlq	$2, %rsi
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	8(%rbx), %rdi
	movslq	-24(%rbx), %rsi
	shlq	$2, %rsi
	callq	hipMalloc
	movl	-24(%rbx), %edx
	testl	%edx, %edx
	jle	.LBB1_7
# %bb.6:                                # %.lr.ph61
                                        #   in Loop: Header=BB1_5 Depth=1
	movq	(%r15), %rdi
	shlq	$2, %rdx
	xorl	%esi, %esi
	callq	memset@PLT
.LBB1_7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_5 Depth=1
	incq	%r14
	movslq	-44(%rbp), %rax
	addq	$48, %rbx
	cmpq	%rax, %r14
	jl	.LBB1_5
# %bb.8:                                # %.preheader57
	testl	%eax, %eax
	jle	.LBB1_16
# %bb.9:                                # %.lr.ph65.preheader
	movq	%r12, -56(%rbp)                 # 8-byte Spill
	movabsq	$4294967424, %rbx               # imm = 0x100000080
	leaq	40(%r13), %r12
	xorl	%r14d, %r14d
	leaq	654(%rbx), %r15
.LBB1_10:                               # %.lr.ph65
                                        # =>This Inner Loop Header: Depth=1
	movl	%r14d, %edi
	callq	hipSetDevice
	movq	-32(%r12), %rsi
	movq	-16(%r12), %rdi
	movslq	-40(%r12), %rdx
	shlq	$2, %rdx
	movq	(%r12), %r8
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%r12), %r9
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.11:                               #   in Loop: Header=BB1_10 Depth=1
	movq	-16(%r12), %rdi
	movq	-8(%r12), %rsi
	movl	-40(%r12), %edx
	callq	_Z25__device_stub__testKernelPfS_i
.LBB1_12:                               #   in Loop: Header=BB1_10 Depth=1
	movq	-24(%r12), %rdi
	movq	-8(%r12), %rsi
	movslq	-40(%r12), %rdx
	shlq	$2, %rdx
	movq	(%r12), %r8
	movl	$2, %ecx
	callq	hipMemcpyAsync
	incq	%r14
	movslq	-44(%rbp), %rax
	addq	$48, %r12
	cmpq	%rax, %r14
	jl	.LBB1_10
# %bb.13:                               # %.preheader
	testl	%eax, %eax
	movq	-56(%rbp), %r12                 # 8-byte Reload
	jle	.LBB1_16
# %bb.14:                               # %.lr.ph67.preheader
	addq	$40, %r13
	xorl	%ebx, %ebx
.LBB1_15:                               # %.lr.ph67
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	hipSetDevice
	movq	(%r13), %rdi
	callq	hipStreamSynchronize
	movq	-32(%r13), %rdi
	callq	hipHostFree
	movq	-24(%r13), %rdi
	callq	hipHostFree
	movq	-16(%r13), %rdi
	callq	hipFree
	movq	-8(%r13), %rdi
	callq	hipFree
	movq	(%r13), %rdi
	callq	hipStreamDestroy
	incq	%rbx
	movslq	-44(%rbp), %rax
	addq	$48, %r13
	cmpq	%rax, %rbx
	jl	.LBB1_15
.LBB1_16:                               # %._crit_edge68
	movq	%r12, %rsp
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10testKernelPfS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10testKernelPfS_i,@object     # @_Z10testKernelPfS_i
	.section	.rodata,"a",@progbits
	.globl	_Z10testKernelPfS_i
	.p2align	3, 0x0
_Z10testKernelPfS_i:
	.quad	_Z25__device_stub__testKernelPfS_i
	.size	_Z10testKernelPfS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA device = %i\n"
	.size	.L.str, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10testKernelPfS_i"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__testKernelPfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10testKernelPfS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10testKernelPfS_i     ; -- Begin function _Z10testKernelPfS_i
	.globl	_Z10testKernelPfS_i
	.p2align	8
	.type	_Z10testKernelPfS_i,@function
_Z10testKernelPfS_i:                    ; @_Z10testKernelPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_lt_i32 s4, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_cbranch_scc1 .LBB0_3
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, 1.0, v2
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, 0
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10testKernelPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10testKernelPfS_i, .Lfunc_end0-_Z10testKernelPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10testKernelPfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10testKernelPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
