#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>

#define TILE_SIZE 16

// buffers for gpu processing
unsigned char *d_input;
unsigned char *d_output_blur;
unsigned char *d_output_sobel;
unsigned char *d_output_nms;
unsigned char *d_output_thresh;
unsigned char *d_output;
double *d_edge_direction;
float *d_edge_magnitude;
float *d_sobel_mask_x;
float *d_sobel_mask_y;
float *d_filter;

inline cudaError_t checkCuda(cudaError_t result) {
	#if defined(DEBUG) || defined(_DEBUG)
		if (result != cudaSuccess) {
			fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
			exit(-1);
		}
	#endif
		return result;
}

__global__ void gaussianBlur(unsigned char *input,
			     			 unsigned char *output,
			     			 unsigned int rows,
			     			 unsigned int cols,
			     			 float *filter,
			     			 int filter_width) {
	
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x > cols || y > rows)
		return;
	int index = y * cols + x;
	
	// Blur algorthm using weighted average
	float result = 0.0;
	for (int r = -filter_width / 2; r < filter_width / 2; r++) {
		for (int c = -filter_width / 2; c < filter_width / 2; c++) {
			int cur_row = r + y; 
			int cur_col = c + x;
			
			if ((cur_row > -1) && (cur_row < rows) &&
				(cur_col > -1) && (cur_col < cols)) { 
				int filter_id = (r + filter_width / 2) * filter_width + (c + filter_width / 2);	
				result += input[cur_row * cols + cur_col] * filter[filter_id]; 
			}
		}
	}
	output[index] = result;
}

__global__ void medianFilter(unsigned char *input,
			     			 unsigned char *output,
			     			 unsigned int rows,
			     			 unsigned int cols){
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols - 1 || y >= rows - 1 || x == 0 || y == 0)
		return;
	int index = y * cols + x;

	// Array of pixels to sort
	float pixels[9];
	pixels[0] = input[y * cols + (x + 1)];
	pixels[1] = input[y * cols + (x - 1)];
	pixels[2] = input[(y + 1) * cols + (x - 1)];
	pixels[3] = input[(y - 1) * cols + (x + 1)];
	pixels[4] = input[(y + 1) * cols + x];
	pixels[5] = input[(y - 1) * cols + x];
	pixels[6] = input[(y - 1) * cols + (x - 1)];
	pixels[7] = input[(y + 1) * cols + (x + 1)];
	pixels[8] = input[index];

	// sort pixel values with insertion sort
	int i, j;
	float temp;
	for (i = 0; i < 9; i++) {
		temp = pixels[i];
		for (j = i - 1; j >= 0 && temp < pixels[j]; j--) {
			pixels[j + 1] = pixels[j];
		}
		pixels[j + 1] = temp;
	}	

	// Assign output pixel to median pixel value
	output[index] = pixels[4];
}

__global__ void sobelFilter(unsigned char *input, 
			    			unsigned char *output, 
			    			float *edge_magnitude,
			    			double *edge_direction,
			    			float *sobel_mask_x,
			    			float *sobel_mask_y,
			    			unsigned int rows,
			    			unsigned int cols){
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols || y >= rows)
		return;
	int index = y * cols + x;

	// magnitude calculation
	float value_x = 0, value_y = 0, angle = 0;
	for (int k = 0; k < 3; k++) {
		for (int l = 0; l < 3; l++) {
			value_x += sobel_mask_x[l * 3 + k] * input[((y + 1) + (1 - l)) * cols + ((x + 1) + (1 - k))];
			value_y += sobel_mask_y[l * 3 + k] * input[((y + 1) + (1 - l)) * cols + ((x + 1) + (1 - k))];
		}
	}
	edge_magnitude[index] = sqrt(value_x * value_x + value_y * value_y);
	//if (x == 0) printf("edge_magnitude: %f\n", edge_magnitude[index]);
	output[index] = edge_magnitude[index];
	
	// angle direction calculation
	if ((value_x != 0) || (value_y != 0)) {
		angle = atan2(value_y, value_x) * 180.0 / 3.14159;
	} else {
		angle = 0.0;
	}
	if (((angle > -22.5) && (angle <= 22.5)) ||//0
	    ((angle > 157.5) && (angle <= 202.5))||//180
		((angle > -202.5) && (angle <= -157.7))) {//-180
		edge_direction[index] = 0.0;
	} else if (((angle > 22.5) && (angle <= 67.5)) ||//45
	          ((angle > -157.5) && (angle <= -112.5))) {//-135
		edge_direction[index] = 45.0;
	} else if (((angle > 67.5) && (angle <= 112.5)) ||//90
	           ((angle > -112.5) && (angle <= -67.5))) {//-90
		edge_direction[index] = 90.0;
	} else if (((angle > 112.5) && (angle <= 157.5)) ||//135
	           ((angle > -67.5) && (angle <= -22.5))) {//-45
		edge_direction[index] = 135.0;
	}
}

__global__ void nonMaxSuppression(unsigned char *input,
				  				  unsigned char *output,
				  				  double *edge_direction,
				  				  unsigned int rows,
				  				  unsigned int cols) {
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols - 1 || y >= rows - 1 || x == 0 || y == 0)
		return;
	int index = y * cols + x;
	
	float pixel_1 = 255, pixel_2 = 255;
	
	if (edge_direction[index] == 0) {
		pixel_1 = input[y * cols + (x + 1)];
		pixel_2 = input[y * cols + (x - 1)];			
	} else if (edge_direction[index] == 45) {
		pixel_1 = input[(y + 1) * cols + (x - 1)];
		pixel_2 = input[(y - 1) * cols + (x + 1)];
	} else if (edge_direction[index] == 90) {
		pixel_1 = input[(y + 1) * cols + x];
		pixel_2 = input[(y - 1) * cols + x];
	} else if (edge_direction[index] == 135) {
		pixel_1 = input[(y - 1) * cols + (x - 1)];
		pixel_2 = input[(y + 1) * cols + (x + 1)];
	}
	
	if ((input[index] >= pixel_1) && (input[index] >= pixel_2)) {
		output[index] = input[index];
	} else {
		output[index] = 0;
	}
}

__global__ void doubleThreshold(unsigned char *input,
								unsigned char *output,
								unsigned int rows,
								unsigned int cols) {
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols || y >= rows)
		return;
	int index = y * cols + x;

	float high = 70, low = 20, weak = 50, strong = 255;
	
	if (input[index] >= high) { //strong
		output[index] = strong;
	} else if (input[index] <= high && input[index] >= low) { //weak
		output[index] = weak;
	} else { //non-relevent
		output[index] = 0;
	}
}

__global__ void histeresis(unsigned char *input, 
			  			   unsigned char *output,
			  			   unsigned int rows,
			  			   unsigned int cols) {
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols - 1 || y >= rows - 1 || x == 0 || y == 0)
		return;
	int index = y * cols + x;
	
	float weak = 50, strong = 255;
	
	if (input[index] == weak) { // if current pixel is weak
		if ((input[y * cols + (x + 1)] == strong) || 
			(input[y * cols + (x - 1)] == strong) || 
			(input[(y + 1) * cols + (x - 1)] == strong) || 
			(input[(y - 1) * cols + (x + 1)] == strong) ||
			(input[(y + 1) * cols + x] == strong) || 
			(input[(y - 1) * cols + x] == strong) ||
			(input[(y - 1) * cols + (x - 1)] == strong) || 
			(input[(y + 1) * cols + (x + 1)] == strong)) // if a surrounding pixel is strong
			output[index] = strong; // set the weak pixel to strong
	} else {
		output[index] = input[index];
	}
}

void edgeDetector (unsigned char* h_input,
		  	 	   unsigned char* h_output,
		   		   unsigned int rows,
		   		   unsigned int cols,
		   		   float* h_filter,
		   		   int filter_width,
		   		   float *h_sobel_mask_x,
		   		   float *h_sobel_mask_y) {

	// block and grid size
	int gridX = 1 + ((cols - 1) / TILE_SIZE);
	int gridY = 1 + ((rows - 1) / TILE_SIZE);
	dim3 dimGrid(gridX, gridY);
	dim3 dimBlock(TILE_SIZE, TILE_SIZE);

	// allocate memory
	int size = rows * cols;
	checkCuda(cudaMalloc((void**)&d_input, size * sizeof(unsigned char)));
	checkCuda(cudaMalloc((void**)&d_output_blur, size * sizeof(unsigned char)));
	checkCuda(cudaMalloc((void**)&d_output_sobel, size * sizeof(unsigned char)));
	checkCuda(cudaMalloc((void**)&d_output_nms, size * sizeof(unsigned char)));
	checkCuda(cudaMalloc((void**)&d_output_thresh, size * sizeof(unsigned char)));
	checkCuda(cudaMalloc((void**)&d_edge_direction, size * sizeof(double)));
	checkCuda(cudaMalloc((void**)&d_edge_magnitude, size * sizeof(float)));
	checkCuda(cudaMalloc((void**)&d_sobel_mask_x, filter_width * sizeof(double)));
	checkCuda(cudaMalloc((void**)&d_sobel_mask_y, filter_width * sizeof(double)));
	checkCuda(cudaMalloc((void**)&d_filter, filter_width * filter_width * sizeof(float)));
	checkCuda(cudaMalloc((void**)&d_output, size * sizeof(unsigned char)));

	checkCuda(cudaMemset(d_output, 0, size * sizeof(unsigned char)));
	checkCuda(cudaMemset(d_output_blur, 0, size * sizeof(unsigned char)));
	checkCuda(cudaMemset(d_output_nms, 0, size * sizeof(unsigned char)));
	checkCuda(cudaMemset(d_edge_direction, 0, size * sizeof(double)));
	checkCuda(cudaMemset(d_output_sobel, 0, size * sizeof(unsigned char)));
	checkCuda(cudaMemset(d_output_thresh, 0, size * sizeof(unsigned char)));
	checkCuda(cudaMemset(d_edge_magnitude, 0, size * sizeof(float)));

	// copy to GPU with streams
	cudaStream_t s1, s2, s3, s4;
	cudaStreamCreate(&s1);
	cudaStreamCreate(&s2);
	cudaStreamCreate(&s3);
	cudaStreamCreate(&s4);

	checkCuda(cudaMemcpyAsync(d_input, h_input, size * sizeof(unsigned char), cudaMemcpyHostToDevice, s1));
	checkCuda(cudaMemcpyAsync(d_sobel_mask_x, h_sobel_mask_x, filter_width * sizeof(float), cudaMemcpyHostToDevice, s2));	
	checkCuda(cudaMemcpyAsync(d_sobel_mask_y, h_sobel_mask_y, filter_width * sizeof(float), cudaMemcpyHostToDevice, s2));
	checkCuda(cudaMemcpyAsync(d_filter, h_filter, filter_width * filter_width * sizeof(float), cudaMemcpyHostToDevice, s2));
	cudaDeviceSynchronize();

	// destroy streams
	cudaStreamDestroy(s1);
	cudaStreamDestroy(s2);
	cudaStreamDestroy(s3);
	cudaStreamDestroy(s4);

	printf("The image has: rows= %d cols= %d\nKernels grid dimensions: gridx=" 
			"%d gridy= %d\nKernels block dimensions: blockx= %d blocky= %d\n", 
			rows, cols, gridX, gridY, TILE_SIZE, TILE_SIZE);
	
	//*** Canny Edge Detector Algorithm ***//

	// 1) Noise Reduction with Gaussian Blur
	gaussianBlur<<<dimGrid, dimBlock>>>(d_input, d_output_blur, rows, cols, d_filter, filter_width);
	cudaDeviceSynchronize();

	// Alternative noise reduction algorithm for ultra sound images
	//medianFilter<<<dimGrid, dimBlock>>>(d_input, d_output, rows, cols);

	// 2) Gradient Calulation with Sobel Filter
	sobelFilter<<<dimGrid, dimBlock>>>(d_output_blur, d_output_sobel, d_edge_magnitude, d_edge_direction, d_sobel_mask_x, d_sobel_mask_y, rows, cols);
	cudaDeviceSynchronize();

	// 3) Non-Maximum Suppression
	nonMaxSuppression<<<dimGrid, dimBlock>>>(d_output_sobel, d_output_nms, d_edge_direction, rows, cols);
	cudaDeviceSynchronize();

	// 4) Double threshold
	doubleThreshold<<<dimGrid, dimBlock>>>(d_output_nms, d_output_thresh, rows, cols);
	cudaDeviceSynchronize();

	// 5) Hysteresis (only call if needed)
	histeresis<<<dimGrid, dimBlock>>>(d_output_thresh, d_output, rows, cols);
	cudaDeviceSynchronize();

	//*** Edge Detection Finished ***//

	// copy final output image to host (use correct output)
	checkCuda(cudaMemcpy(h_output, d_output, size * sizeof(unsigned char), cudaMemcpyDeviceToHost));

	// free memory
	checkCuda(cudaFree(d_input));
	checkCuda(cudaFree(d_output_blur));
	checkCuda(cudaFree(d_output_nms));
	checkCuda(cudaFree(d_output_sobel));
	checkCuda(cudaFree(d_output_thresh));
	checkCuda(cudaFree(d_output));
	checkCuda(cudaFree(d_edge_magnitude));
	checkCuda(cudaFree(d_edge_direction));
	checkCuda(cudaFree(d_sobel_mask_x));
	checkCuda(cudaFree(d_sobel_mask_y));
}

	.file	"tmpxft_00309979_00000000-6_edge_detector.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi
	.type	_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi, @function
_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12gaussianBlurPhS_jjPfi(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi, .-_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi
	.globl	_Z12gaussianBlurPhS_jjPfi
	.type	_Z12gaussianBlurPhS_jjPfi, @function
_Z12gaussianBlurPhS_jjPfi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi
	.cfi_endproc
.LFE2054:
	.size	_Z12gaussianBlurPhS_jjPfi, .-_Z12gaussianBlurPhS_jjPfi
	.globl	_Z36__device_stub__Z12medianFilterPhS_jjPhS_jj
	.type	_Z36__device_stub__Z12medianFilterPhS_jjPhS_jj, @function
_Z36__device_stub__Z12medianFilterPhS_jjPhS_jj:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12medianFilterPhS_jj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z36__device_stub__Z12medianFilterPhS_jjPhS_jj, .-_Z36__device_stub__Z12medianFilterPhS_jjPhS_jj
	.globl	_Z12medianFilterPhS_jj
	.type	_Z12medianFilterPhS_jj, @function
_Z12medianFilterPhS_jj:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12medianFilterPhS_jjPhS_jj
	.cfi_endproc
.LFE2056:
	.size	_Z12medianFilterPhS_jj, .-_Z12medianFilterPhS_jj
	.globl	_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj
	.type	_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj, @function
_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11sobelFilterPhS_PfPdS0_S0_jj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L13:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj, .-_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj
	.globl	_Z11sobelFilterPhS_PfPdS0_S0_jj
	.type	_Z11sobelFilterPhS_PfPdS0_S0_jj, @function
_Z11sobelFilterPhS_PfPdS0_S0_jj:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj
	.cfi_endproc
.LFE2058:
	.size	_Z11sobelFilterPhS_PfPdS0_S0_jj, .-_Z11sobelFilterPhS_PfPdS0_S0_jj
	.globl	_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj
	.type	_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj, @function
_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17nonMaxSuppressionPhS_Pdjj(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj, .-_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj
	.globl	_Z17nonMaxSuppressionPhS_Pdjj
	.type	_Z17nonMaxSuppressionPhS_Pdjj, @function
_Z17nonMaxSuppressionPhS_Pdjj:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj
	.cfi_endproc
.LFE2060:
	.size	_Z17nonMaxSuppressionPhS_Pdjj, .-_Z17nonMaxSuppressionPhS_Pdjj
	.globl	_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj
	.type	_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj, @function
_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15doubleThresholdPhS_jj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj, .-_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj
	.globl	_Z15doubleThresholdPhS_jj
	.type	_Z15doubleThresholdPhS_jj, @function
_Z15doubleThresholdPhS_jj:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj
	.cfi_endproc
.LFE2062:
	.size	_Z15doubleThresholdPhS_jj, .-_Z15doubleThresholdPhS_jj
	.globl	_Z34__device_stub__Z10histeresisPhS_jjPhS_jj
	.type	_Z34__device_stub__Z10histeresisPhS_jjPhS_jj, @function
_Z34__device_stub__Z10histeresisPhS_jjPhS_jj:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10histeresisPhS_jj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L28:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z34__device_stub__Z10histeresisPhS_jjPhS_jj, .-_Z34__device_stub__Z10histeresisPhS_jjPhS_jj
	.globl	_Z10histeresisPhS_jj
	.type	_Z10histeresisPhS_jj, @function
_Z10histeresisPhS_jj:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10histeresisPhS_jjPhS_jj
	.cfi_endproc
.LFE2064:
	.size	_Z10histeresisPhS_jj, .-_Z10histeresisPhS_jj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"The image has: rows= %d cols= %d\nKernels grid dimensions: gridx=%d gridy= %d\nKernels block dimensions: blockx= %d blocky= %d\n"
	.text
	.globl	_Z12edgeDetectorPhS_jjPfiS0_S0_
	.type	_Z12edgeDetectorPhS_jjPfiS0_S0_, @function
_Z12edgeDetectorPhS_jjPfiS0_S0_:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%r9d, %r15
	leal	-1(%rdx), %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leal	-1(%rcx), %r14d
	shrl	$4, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	shrl	$4, %r14d
	incl	%r9d
	movq	%r15, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	incl	%r14d
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	imull	%edx, %ebx
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%r8, 48(%rsp)
	movslq	%ebx, %rbx
	movq	%rdi, 32(%rsp)
	leaq	d_input(%rip), %rdi
	movq	%rax, 56(%rsp)
	movq	216(%rsp), %rax
	movq	%rsi, 40(%rsp)
	movq	%rbx, %rsi
	movq	%rax, 64(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	movl	%r9d, 116(%rsp)
	movabsq	$68719476752, %rax
	movl	%r9d, 76(%rsp)
	movl	%r14d, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	d_output_blur(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	d_output_sobel(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	d_output_nms(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	d_output_thresh(%rip), %rdi
	call	cudaMalloc@PLT
	leaq	0(,%rbx,8), %rax
	leaq	d_edge_direction(%rip), %rdi
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	leaq	0(,%rbx,4), %rax
	leaq	d_edge_magnitude(%rip), %rdi
	movq	%rax, %rsi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	leaq	0(,%r15,8), %rsi
	leaq	d_sobel_mask_x(%rip), %rdi
	movq	%rsi, 8(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	d_sobel_mask_y(%rip), %rdi
	call	cudaMalloc@PLT
	movl	%r15d, %eax
	leaq	d_filter(%rip), %rdi
	imull	%r15d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	d_output(%rip), %rdi
	call	cudaMalloc@PLT
	movq	d_output(%rip), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	call	cudaMemset@PLT
	movq	d_output_blur(%rip), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	call	cudaMemset@PLT
	movq	d_output_nms(%rip), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	call	cudaMemset@PLT
	movq	16(%rsp), %rdx
	movq	d_edge_direction(%rip), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	d_output_sobel(%rip), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	call	cudaMemset@PLT
	movq	d_output_thresh(%rip), %rdi
	movq	%rbx, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	24(%rsp), %rdx
	movq	d_edge_magnitude(%rip), %rdi
	xorl	%esi, %esi
	salq	$2, %r15
	call	cudaMemset@PLT
	leaq	80(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	104(%rsp), %rdi
	call	cudaStreamCreate@PLT
	movq	80(%rsp), %r8
	movq	32(%rsp), %rsi
	movq	%rbx, %rdx
	movq	d_input(%rip), %rdi
	movl	$1, %ecx
	call	cudaMemcpyAsync@PLT
	movq	88(%rsp), %r8
	movq	56(%rsp), %rsi
	movq	%r15, %rdx
	movq	d_sobel_mask_x(%rip), %rdi
	movl	$1, %ecx
	call	cudaMemcpyAsync@PLT
	movq	88(%rsp), %r8
	movq	64(%rsp), %rsi
	movq	%r15, %rdx
	movq	d_sobel_mask_y(%rip), %rdi
	movl	$1, %ecx
	call	cudaMemcpyAsync@PLT
	movq	88(%rsp), %r8
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	48(%rsp), %rsi
	movq	d_filter(%rip), %rdi
	call	cudaMemcpyAsync@PLT
	call	cudaDeviceSynchronize@PLT
	movq	80(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	88(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	96(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	104(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	pushq	$16
	.cfi_def_cfa_offset 216
	movl	%r14d, %r8d
	movl	%r12d, %ecx
	pushq	$16
	.cfi_def_cfa_offset 224
	movl	92(%rsp), %r9d
	movl	%ebp, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	popq	%rcx
	.cfi_def_cfa_offset 216
	popq	%rsi
	.cfi_def_cfa_offset 208
	xorl	%r9d, %r9d
	movl	132(%rsp), %ecx
	movq	124(%rsp), %rdx
	xorl	%r8d, %r8d
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	d_filter(%rip), %r8
	movl	%r13d, %r9d
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movq	d_output_blur(%rip), %rsi
	movq	d_input(%rip), %rdi
	call	_Z39__device_stub__Z12gaussianBlurPhS_jjPfiPhS_jjPfi
.L34:
	call	cudaDeviceSynchronize@PLT
	movq	124(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	132(%rsp), %ecx
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	d_edge_magnitude(%rip), %rdx
	movq	d_sobel_mask_y(%rip), %r9
	pushq	%r12
	.cfi_def_cfa_offset 216
	movq	d_sobel_mask_x(%rip), %r8
	movq	d_edge_direction(%rip), %rcx
	pushq	%rbp
	.cfi_def_cfa_offset 224
	movq	d_output_sobel(%rip), %rsi
	movq	d_output_blur(%rip), %rdi
	call	_Z45__device_stub__Z11sobelFilterPhS_PfPdS0_S0_jjPhS_PfPdS0_S0_jj
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L35:
	call	cudaDeviceSynchronize@PLT
	movq	124(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	132(%rsp), %ecx
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	d_edge_direction(%rip), %rdx
	movq	d_output_nms(%rip), %rsi
	movl	%r12d, %r8d
	movl	%ebp, %ecx
	movq	d_output_sobel(%rip), %rdi
	call	_Z43__device_stub__Z17nonMaxSuppressionPhS_PdjjPhS_Pdjj
.L36:
	call	cudaDeviceSynchronize@PLT
	movq	124(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	132(%rsp), %ecx
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	d_output_thresh(%rip), %rsi
	movq	d_output_nms(%rip), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z39__device_stub__Z15doubleThresholdPhS_jjPhS_jj
.L37:
	call	cudaDeviceSynchronize@PLT
	movq	124(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	132(%rsp), %ecx
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	d_output(%rip), %rsi
	movq	d_output_thresh(%rip), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z34__device_stub__Z10histeresisPhS_jjPhS_jj
.L38:
	call	cudaDeviceSynchronize@PLT
	movq	d_output(%rip), %rsi
	movq	40(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	d_input(%rip), %rdi
	call	cudaFree@PLT
	movq	d_output_blur(%rip), %rdi
	call	cudaFree@PLT
	movq	d_output_nms(%rip), %rdi
	call	cudaFree@PLT
	movq	d_output_sobel(%rip), %rdi
	call	cudaFree@PLT
	movq	d_output_thresh(%rip), %rdi
	call	cudaFree@PLT
	movq	d_output(%rip), %rdi
	call	cudaFree@PLT
	movq	d_edge_magnitude(%rip), %rdi
	call	cudaFree@PLT
	movq	d_edge_direction(%rip), %rdi
	call	cudaFree@PLT
	movq	d_sobel_mask_x(%rip), %rdi
	call	cudaFree@PLT
	movq	d_sobel_mask_y(%rip), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z12edgeDetectorPhS_jjPfiS0_S0_, .-_Z12edgeDetectorPhS_jjPfiS0_S0_
	.section	.rodata.str1.1
.LC1:
	.string	"_Z10histeresisPhS_jj"
.LC2:
	.string	"_Z15doubleThresholdPhS_jj"
.LC3:
	.string	"_Z17nonMaxSuppressionPhS_Pdjj"
.LC4:
	.string	"_Z11sobelFilterPhS_PfPdS0_S0_jj"
.LC5:
	.string	"_Z12medianFilterPhS_jj"
.LC6:
	.string	"_Z12gaussianBlurPhS_jjPfi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10histeresisPhS_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15doubleThresholdPhS_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17nonMaxSuppressionPhS_Pdjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11sobelFilterPhS_PfPdS0_S0_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12medianFilterPhS_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12gaussianBlurPhS_jjPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2066:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	d_filter
	.bss
	.align 8
	.type	d_filter, @object
	.size	d_filter, 8
d_filter:
	.zero	8
	.globl	d_sobel_mask_y
	.align 8
	.type	d_sobel_mask_y, @object
	.size	d_sobel_mask_y, 8
d_sobel_mask_y:
	.zero	8
	.globl	d_sobel_mask_x
	.align 8
	.type	d_sobel_mask_x, @object
	.size	d_sobel_mask_x, 8
d_sobel_mask_x:
	.zero	8
	.globl	d_edge_magnitude
	.align 8
	.type	d_edge_magnitude, @object
	.size	d_edge_magnitude, 8
d_edge_magnitude:
	.zero	8
	.globl	d_edge_direction
	.align 8
	.type	d_edge_direction, @object
	.size	d_edge_direction, 8
d_edge_direction:
	.zero	8
	.globl	d_output
	.align 8
	.type	d_output, @object
	.size	d_output, 8
d_output:
	.zero	8
	.globl	d_output_thresh
	.align 8
	.type	d_output_thresh, @object
	.size	d_output_thresh, 8
d_output_thresh:
	.zero	8
	.globl	d_output_nms
	.align 8
	.type	d_output_nms, @object
	.size	d_output_nms, 8
d_output_nms:
	.zero	8
	.globl	d_output_sobel
	.align 8
	.type	d_output_sobel, @object
	.size	d_output_sobel, 8
d_output_sobel:
	.zero	8
	.globl	d_output_blur
	.align 8
	.type	d_output_blur, @object
	.size	d_output_blur, 8
d_output_blur:
	.zero	8
	.globl	d_input
	.align 8
	.type	d_input, @object
	.size	d_input, 8
d_input:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>

#define TILE_SIZE 16

// buffers for gpu processing
unsigned char *d_input;
unsigned char *d_output_blur;
unsigned char *d_output_sobel;
unsigned char *d_output_nms;
unsigned char *d_output_thresh;
unsigned char *d_output;
double *d_edge_direction;
float *d_edge_magnitude;
float *d_sobel_mask_x;
float *d_sobel_mask_y;
float *d_filter;

inline hipError_t checkCuda(hipError_t result) {
	#if defined(DEBUG) || defined(_DEBUG)
		if (result != hipSuccess) {
			fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
			exit(-1);
		}
	#endif
		return result;
}

__global__ void gaussianBlur(unsigned char *input,
			     			 unsigned char *output,
			     			 unsigned int rows,
			     			 unsigned int cols,
			     			 float *filter,
			     			 int filter_width) {
	
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x > cols || y > rows)
		return;
	int index = y * cols + x;
	
	// Blur algorthm using weighted average
	float result = 0.0;
	for (int r = -filter_width / 2; r < filter_width / 2; r++) {
		for (int c = -filter_width / 2; c < filter_width / 2; c++) {
			int cur_row = r + y; 
			int cur_col = c + x;
			
			if ((cur_row > -1) && (cur_row < rows) &&
				(cur_col > -1) && (cur_col < cols)) { 
				int filter_id = (r + filter_width / 2) * filter_width + (c + filter_width / 2);	
				result += input[cur_row * cols + cur_col] * filter[filter_id]; 
			}
		}
	}
	output[index] = result;
}

__global__ void medianFilter(unsigned char *input,
			     			 unsigned char *output,
			     			 unsigned int rows,
			     			 unsigned int cols){
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols - 1 || y >= rows - 1 || x == 0 || y == 0)
		return;
	int index = y * cols + x;

	// Array of pixels to sort
	float pixels[9];
	pixels[0] = input[y * cols + (x + 1)];
	pixels[1] = input[y * cols + (x - 1)];
	pixels[2] = input[(y + 1) * cols + (x - 1)];
	pixels[3] = input[(y - 1) * cols + (x + 1)];
	pixels[4] = input[(y + 1) * cols + x];
	pixels[5] = input[(y - 1) * cols + x];
	pixels[6] = input[(y - 1) * cols + (x - 1)];
	pixels[7] = input[(y + 1) * cols + (x + 1)];
	pixels[8] = input[index];

	// sort pixel values with insertion sort
	int i, j;
	float temp;
	for (i = 0; i < 9; i++) {
		temp = pixels[i];
		for (j = i - 1; j >= 0 && temp < pixels[j]; j--) {
			pixels[j + 1] = pixels[j];
		}
		pixels[j + 1] = temp;
	}	

	// Assign output pixel to median pixel value
	output[index] = pixels[4];
}

__global__ void sobelFilter(unsigned char *input, 
			    			unsigned char *output, 
			    			float *edge_magnitude,
			    			double *edge_direction,
			    			float *sobel_mask_x,
			    			float *sobel_mask_y,
			    			unsigned int rows,
			    			unsigned int cols){
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols || y >= rows)
		return;
	int index = y * cols + x;

	// magnitude calculation
	float value_x = 0, value_y = 0, angle = 0;
	for (int k = 0; k < 3; k++) {
		for (int l = 0; l < 3; l++) {
			value_x += sobel_mask_x[l * 3 + k] * input[((y + 1) + (1 - l)) * cols + ((x + 1) + (1 - k))];
			value_y += sobel_mask_y[l * 3 + k] * input[((y + 1) + (1 - l)) * cols + ((x + 1) + (1 - k))];
		}
	}
	edge_magnitude[index] = sqrt(value_x * value_x + value_y * value_y);
	//if (x == 0) printf("edge_magnitude: %f\n", edge_magnitude[index]);
	output[index] = edge_magnitude[index];
	
	// angle direction calculation
	if ((value_x != 0) || (value_y != 0)) {
		angle = atan2(value_y, value_x) * 180.0 / 3.14159;
	} else {
		angle = 0.0;
	}
	if (((angle > -22.5) && (angle <= 22.5)) ||//0
	    ((angle > 157.5) && (angle <= 202.5))||//180
		((angle > -202.5) && (angle <= -157.7))) {//-180
		edge_direction[index] = 0.0;
	} else if (((angle > 22.5) && (angle <= 67.5)) ||//45
	          ((angle > -157.5) && (angle <= -112.5))) {//-135
		edge_direction[index] = 45.0;
	} else if (((angle > 67.5) && (angle <= 112.5)) ||//90
	           ((angle > -112.5) && (angle <= -67.5))) {//-90
		edge_direction[index] = 90.0;
	} else if (((angle > 112.5) && (angle <= 157.5)) ||//135
	           ((angle > -67.5) && (angle <= -22.5))) {//-45
		edge_direction[index] = 135.0;
	}
}

__global__ void nonMaxSuppression(unsigned char *input,
				  				  unsigned char *output,
				  				  double *edge_direction,
				  				  unsigned int rows,
				  				  unsigned int cols) {
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols - 1 || y >= rows - 1 || x == 0 || y == 0)
		return;
	int index = y * cols + x;
	
	float pixel_1 = 255, pixel_2 = 255;
	
	if (edge_direction[index] == 0) {
		pixel_1 = input[y * cols + (x + 1)];
		pixel_2 = input[y * cols + (x - 1)];			
	} else if (edge_direction[index] == 45) {
		pixel_1 = input[(y + 1) * cols + (x - 1)];
		pixel_2 = input[(y - 1) * cols + (x + 1)];
	} else if (edge_direction[index] == 90) {
		pixel_1 = input[(y + 1) * cols + x];
		pixel_2 = input[(y - 1) * cols + x];
	} else if (edge_direction[index] == 135) {
		pixel_1 = input[(y - 1) * cols + (x - 1)];
		pixel_2 = input[(y + 1) * cols + (x + 1)];
	}
	
	if ((input[index] >= pixel_1) && (input[index] >= pixel_2)) {
		output[index] = input[index];
	} else {
		output[index] = 0;
	}
}

__global__ void doubleThreshold(unsigned char *input,
								unsigned char *output,
								unsigned int rows,
								unsigned int cols) {
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols || y >= rows)
		return;
	int index = y * cols + x;

	float high = 70, low = 20, weak = 50, strong = 255;
	
	if (input[index] >= high) { //strong
		output[index] = strong;
	} else if (input[index] <= high && input[index] >= low) { //weak
		output[index] = weak;
	} else { //non-relevent
		output[index] = 0;
	}
}

__global__ void histeresis(unsigned char *input, 
			  			   unsigned char *output,
			  			   unsigned int rows,
			  			   unsigned int cols) {
	int x = blockIdx.x * TILE_SIZE + threadIdx.x;
	int y = blockIdx.y * TILE_SIZE + threadIdx.y;
	if (x >= cols - 1 || y >= rows - 1 || x == 0 || y == 0)
		return;
	int index = y * cols + x;
	
	float weak = 50, strong = 255;
	
	if (input[index] == weak) { // if current pixel is weak
		if ((input[y * cols + (x + 1)] == strong) || 
			(input[y * cols + (x - 1)] == strong) || 
			(input[(y + 1) * cols + (x - 1)] == strong) || 
			(input[(y - 1) * cols + (x + 1)] == strong) ||
			(input[(y + 1) * cols + x] == strong) || 
			(input[(y - 1) * cols + x] == strong) ||
			(input[(y - 1) * cols + (x - 1)] == strong) || 
			(input[(y + 1) * cols + (x + 1)] == strong)) // if a surrounding pixel is strong
			output[index] = strong; // set the weak pixel to strong
	} else {
		output[index] = input[index];
	}
}

void edgeDetector (unsigned char* h_input,
		  	 	   unsigned char* h_output,
		   		   unsigned int rows,
		   		   unsigned int cols,
		   		   float* h_filter,
		   		   int filter_width,
		   		   float *h_sobel_mask_x,
		   		   float *h_sobel_mask_y) {

	// block and grid size
	int gridX = 1 + ((cols - 1) / TILE_SIZE);
	int gridY = 1 + ((rows - 1) / TILE_SIZE);
	dim3 dimGrid(gridX, gridY);
	dim3 dimBlock(TILE_SIZE, TILE_SIZE);

	// allocate memory
	int size = rows * cols;
	checkCuda(hipMalloc((void**)&d_input, size * sizeof(unsigned char)));
	checkCuda(hipMalloc((void**)&d_output_blur, size * sizeof(unsigned char)));
	checkCuda(hipMalloc((void**)&d_output_sobel, size * sizeof(unsigned char)));
	checkCuda(hipMalloc((void**)&d_output_nms, size * sizeof(unsigned char)));
	checkCuda(hipMalloc((void**)&d_output_thresh, size * sizeof(unsigned char)));
	checkCuda(hipMalloc((void**)&d_edge_direction, size * sizeof(double)));
	checkCuda(hipMalloc((void**)&d_edge_magnitude, size * sizeof(float)));
	checkCuda(hipMalloc((void**)&d_sobel_mask_x, filter_width * sizeof(double)));
	checkCuda(hipMalloc((void**)&d_sobel_mask_y, filter_width * sizeof(double)));
	checkCuda(hipMalloc((void**)&d_filter, filter_width * filter_width * sizeof(float)));
	checkCuda(hipMalloc((void**)&d_output, size * sizeof(unsigned char)));

	checkCuda(hipMemset(d_output, 0, size * sizeof(unsigned char)));
	checkCuda(hipMemset(d_output_blur, 0, size * sizeof(unsigned char)));
	checkCuda(hipMemset(d_output_nms, 0, size * sizeof(unsigned char)));
	checkCuda(hipMemset(d_edge_direction, 0, size * sizeof(double)));
	checkCuda(hipMemset(d_output_sobel, 0, size * sizeof(unsigned char)));
	checkCuda(hipMemset(d_output_thresh, 0, size * sizeof(unsigned char)));
	checkCuda(hipMemset(d_edge_magnitude, 0, size * sizeof(float)));

	// copy to GPU with streams
	hipStream_t s1, s2, s3, s4;
	hipStreamCreate(&s1);
	hipStreamCreate(&s2);
	hipStreamCreate(&s3);
	hipStreamCreate(&s4);

	checkCuda(hipMemcpyAsync(d_input, h_input, size * sizeof(unsigned char), hipMemcpyHostToDevice, s1));
	checkCuda(hipMemcpyAsync(d_sobel_mask_x, h_sobel_mask_x, filter_width * sizeof(float), hipMemcpyHostToDevice, s2));	
	checkCuda(hipMemcpyAsync(d_sobel_mask_y, h_sobel_mask_y, filter_width * sizeof(float), hipMemcpyHostToDevice, s2));
	checkCuda(hipMemcpyAsync(d_filter, h_filter, filter_width * filter_width * sizeof(float), hipMemcpyHostToDevice, s2));
	hipDeviceSynchronize();

	// destroy streams
	hipStreamDestroy(s1);
	hipStreamDestroy(s2);
	hipStreamDestroy(s3);
	hipStreamDestroy(s4);

	printf("The image has: rows= %d cols= %d\nKernels grid dimensions: gridx=" 
			"%d gridy= %d\nKernels block dimensions: blockx= %d blocky= %d\n", 
			rows, cols, gridX, gridY, TILE_SIZE, TILE_SIZE);
	
	//*** Canny Edge Detector Algorithm ***//

	// 1) Noise Reduction with Gaussian Blur
	gaussianBlur<<<dimGrid, dimBlock>>>(d_input, d_output_blur, rows, cols, d_filter, filter_width);
	hipDeviceSynchronize();

	// Alternative noise reduction algorithm for ultra sound images
	//medianFilter<<<dimGrid, dimBlock>>>(d_input, d_output, rows, cols);

	// 2) Gradient Calulation with Sobel Filter
	sobelFilter<<<dimGrid, dimBlock>>>(d_output_blur, d_output_sobel, d_edge_magnitude, d_edge_direction, d_sobel_mask_x, d_sobel_mask_y, rows, cols);
	hipDeviceSynchronize();

	// 3) Non-Maximum Suppression
	nonMaxSuppression<<<dimGrid, dimBlock>>>(d_output_sobel, d_output_nms, d_edge_direction, rows, cols);
	hipDeviceSynchronize();

	// 4) Double threshold
	doubleThreshold<<<dimGrid, dimBlock>>>(d_output_nms, d_output_thresh, rows, cols);
	hipDeviceSynchronize();

	// 5) Hysteresis (only call if needed)
	histeresis<<<dimGrid, dimBlock>>>(d_output_thresh, d_output, rows, cols);
	hipDeviceSynchronize();

	//*** Edge Detection Finished ***//

	// copy final output image to host (use correct output)
	checkCuda(hipMemcpy(h_output, d_output, size * sizeof(unsigned char), hipMemcpyDeviceToHost));

	// free memory
	checkCuda(hipFree(d_input));
	checkCuda(hipFree(d_output_blur));
	checkCuda(hipFree(d_output_nms));
	checkCuda(hipFree(d_output_sobel));
	checkCuda(hipFree(d_output_thresh));
	checkCuda(hipFree(d_output));
	checkCuda(hipFree(d_edge_magnitude));
	checkCuda(hipFree(d_edge_direction));
	checkCuda(hipFree(d_sobel_mask_x));
	checkCuda(hipFree(d_sobel_mask_y));
}

	.text
	.file	"edge_detector.hip"
	.globl	_Z27__device_stub__gaussianBlurPhS_jjPfi # -- Begin function _Z27__device_stub__gaussianBlurPhS_jjPfi
	.type	_Z27__device_stub__gaussianBlurPhS_jjPfi,@function
_Z27__device_stub__gaussianBlurPhS_jjPfi: # @_Z27__device_stub__gaussianBlurPhS_jjPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12gaussianBlurPhS_jjPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__gaussianBlurPhS_jjPfi, .Lfunc_end0-_Z27__device_stub__gaussianBlurPhS_jjPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__medianFilterPhS_jj # -- Begin function _Z27__device_stub__medianFilterPhS_jj
	.type	_Z27__device_stub__medianFilterPhS_jj,@function
_Z27__device_stub__medianFilterPhS_jj:  # @_Z27__device_stub__medianFilterPhS_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12medianFilterPhS_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__medianFilterPhS_jj, .Lfunc_end1-_Z27__device_stub__medianFilterPhS_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj # -- Begin function _Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj
	.type	_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj,@function
_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj: # @_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11sobelFilterPhS_PfPdS0_S0_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj, .Lfunc_end2-_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__nonMaxSuppressionPhS_Pdjj # -- Begin function _Z32__device_stub__nonMaxSuppressionPhS_Pdjj
	.type	_Z32__device_stub__nonMaxSuppressionPhS_Pdjj,@function
_Z32__device_stub__nonMaxSuppressionPhS_Pdjj: # @_Z32__device_stub__nonMaxSuppressionPhS_Pdjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17nonMaxSuppressionPhS_Pdjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z32__device_stub__nonMaxSuppressionPhS_Pdjj, .Lfunc_end3-_Z32__device_stub__nonMaxSuppressionPhS_Pdjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__doubleThresholdPhS_jj # -- Begin function _Z30__device_stub__doubleThresholdPhS_jj
	.type	_Z30__device_stub__doubleThresholdPhS_jj,@function
_Z30__device_stub__doubleThresholdPhS_jj: # @_Z30__device_stub__doubleThresholdPhS_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15doubleThresholdPhS_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z30__device_stub__doubleThresholdPhS_jj, .Lfunc_end4-_Z30__device_stub__doubleThresholdPhS_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__histeresisPhS_jj # -- Begin function _Z25__device_stub__histeresisPhS_jj
	.type	_Z25__device_stub__histeresisPhS_jj,@function
_Z25__device_stub__histeresisPhS_jj:    # @_Z25__device_stub__histeresisPhS_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10histeresisPhS_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z25__device_stub__histeresisPhS_jj, .Lfunc_end5-_Z25__device_stub__histeresisPhS_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z12edgeDetectorPhS_jjPfiS0_S0_ # -- Begin function _Z12edgeDetectorPhS_jjPfiS0_S0_
	.type	_Z12edgeDetectorPhS_jjPfiS0_S0_,@function
_Z12edgeDetectorPhS_jjPfiS0_S0_:        # @_Z12edgeDetectorPhS_jjPfiS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movq	%r8, 40(%rsp)                   # 8-byte Spill
                                        # kill: def $ecx killed $ecx def $rcx
                                        # kill: def $edx killed $edx def $rdx
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	leal	-1(%rcx), %eax
	movq	%rcx, %rsi
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	shrl	$4, %eax
	incl	%eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	leal	-1(%rdx), %ebp
	shrl	$4, %ebp
	incl	%ebp
	movq	%rbp, %rcx
	shlq	$32, %rcx
	orq	%rax, %rcx
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movl	%esi, %eax
	imull	%edx, %eax
	movslq	%eax, %r12
	movl	$d_input, %edi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$d_output_blur, %edi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$d_output_sobel, %edi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$d_output_nms, %edi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$d_output_thresh, %edi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	(,%r12,8), %r13
	movl	$d_edge_direction, %edi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	(,%r12,4), %rbx
	movl	$d_edge_magnitude, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	%r14d, 12(%rsp)                 # 4-byte Spill
	movslq	%r14d, %r15
	leaq	(,%r15,8), %r14
	movl	$d_sobel_mask_x, %edi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$d_sobel_mask_y, %edi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%r15d, %r14d
	imull	%r14d, %r14d
	shlq	$2, %r14
	movl	$d_filter, %edi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$d_output, %edi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	d_output(%rip), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movq	d_output_blur(%rip), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movq	d_output_nms(%rip), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movq	d_edge_direction(%rip), %rdi
	xorl	%esi, %esi
	movq	%r13, %rdx
	callq	hipMemset
	movq	d_output_sobel(%rip), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movq	d_output_thresh(%rip), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movq	d_edge_magnitude(%rip), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	hipMemset
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipStreamCreate
	leaq	88(%rsp), %r13
	movq	%r13, %rdi
	callq	hipStreamCreate
	leaq	80(%rsp), %rdi
	callq	hipStreamCreate
	leaq	72(%rsp), %rdi
	callq	hipStreamCreate
	movq	d_input(%rip), %rdi
	movq	(%rbx), %r8
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	d_sobel_mask_x(%rip), %rdi
	shlq	$2, %r15
	movq	(%r13), %r8
	movq	160(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	d_sobel_mask_y(%rip), %rdi
	movq	(%r13), %r8
	movq	168(%rsp), %rsi
	movq	%r15, %rdx
	movabsq	$68719476752, %r15              # imm = 0x1000000010
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	d_filter(%rip), %rdi
	movq	(%r13), %r8
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movq	24(%rsp), %r14                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpyAsync
	callq	hipDeviceSynchronize
	movq	(%rbx), %rdi
	movq	32(%rsp), %rbx                  # 8-byte Reload
	callq	hipStreamDestroy
	movq	(%r13), %rdi
	callq	hipStreamDestroy
	leaq	80(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipStreamDestroy
	leaq	72(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipStreamDestroy
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$.L.str, %edi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movq	56(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%ebp, %r8d
	movq	64(%rsp), %r13                  # 8-byte Reload
	movl	$16, %r9d
	xorl	%eax, %eax
	pushq	$16
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	d_input(%rip), %rdi
	movq	d_output_blur(%rip), %rsi
	movq	d_filter(%rip), %r8
	movl	%r14d, %edx
	movl	%ebx, %ecx
	movl	12(%rsp), %r9d                  # 4-byte Reload
	callq	_Z27__device_stub__gaussianBlurPhS_jjPfi
.LBB6_2:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_4
# %bb.3:
	movq	d_output_blur(%rip), %rdi
	movq	d_output_sobel(%rip), %rsi
	movq	d_edge_magnitude(%rip), %rdx
	movq	d_edge_direction(%rip), %rcx
	movq	d_sobel_mask_x(%rip), %r8
	movq	d_sobel_mask_y(%rip), %r9
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB6_4:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_6
# %bb.5:
	movq	d_output_sobel(%rip), %rdi
	movq	d_output_nms(%rip), %rsi
	movq	d_edge_direction(%rip), %rdx
	movl	%r14d, %ecx
	movl	%ebx, %r8d
	callq	_Z32__device_stub__nonMaxSuppressionPhS_Pdjj
.LBB6_6:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_8
# %bb.7:
	movq	d_output_nms(%rip), %rdi
	movq	d_output_thresh(%rip), %rsi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	callq	_Z30__device_stub__doubleThresholdPhS_jj
.LBB6_8:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_10
# %bb.9:
	movq	d_output_thresh(%rip), %rdi
	movq	d_output(%rip), %rsi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	callq	_Z25__device_stub__histeresisPhS_jj
.LBB6_10:
	callq	hipDeviceSynchronize
	movq	d_output(%rip), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	d_input(%rip), %rdi
	callq	hipFree
	movq	d_output_blur(%rip), %rdi
	callq	hipFree
	movq	d_output_nms(%rip), %rdi
	callq	hipFree
	movq	d_output_sobel(%rip), %rdi
	callq	hipFree
	movq	d_output_thresh(%rip), %rdi
	callq	hipFree
	movq	d_output(%rip), %rdi
	callq	hipFree
	movq	d_edge_magnitude(%rip), %rdi
	callq	hipFree
	movq	d_edge_direction(%rip), %rdi
	callq	hipFree
	movq	d_sobel_mask_x(%rip), %rdi
	callq	hipFree
	movq	d_sobel_mask_y(%rip), %rdi
	callq	hipFree
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z12edgeDetectorPhS_jjPfiS0_S0_, .Lfunc_end6-_Z12edgeDetectorPhS_jjPfiS0_S0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12gaussianBlurPhS_jjPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12medianFilterPhS_jj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11sobelFilterPhS_PfPdS0_S0_jj, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17nonMaxSuppressionPhS_Pdjj, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15doubleThresholdPhS_jj, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10histeresisPhS_jj, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_input,@object                 # @d_input
	.bss
	.globl	d_input
	.p2align	3, 0x0
d_input:
	.quad	0
	.size	d_input, 8

	.type	d_output_blur,@object           # @d_output_blur
	.globl	d_output_blur
	.p2align	3, 0x0
d_output_blur:
	.quad	0
	.size	d_output_blur, 8

	.type	d_output_sobel,@object          # @d_output_sobel
	.globl	d_output_sobel
	.p2align	3, 0x0
d_output_sobel:
	.quad	0
	.size	d_output_sobel, 8

	.type	d_output_nms,@object            # @d_output_nms
	.globl	d_output_nms
	.p2align	3, 0x0
d_output_nms:
	.quad	0
	.size	d_output_nms, 8

	.type	d_output_thresh,@object         # @d_output_thresh
	.globl	d_output_thresh
	.p2align	3, 0x0
d_output_thresh:
	.quad	0
	.size	d_output_thresh, 8

	.type	d_output,@object                # @d_output
	.globl	d_output
	.p2align	3, 0x0
d_output:
	.quad	0
	.size	d_output, 8

	.type	d_edge_direction,@object        # @d_edge_direction
	.globl	d_edge_direction
	.p2align	3, 0x0
d_edge_direction:
	.quad	0
	.size	d_edge_direction, 8

	.type	d_edge_magnitude,@object        # @d_edge_magnitude
	.globl	d_edge_magnitude
	.p2align	3, 0x0
d_edge_magnitude:
	.quad	0
	.size	d_edge_magnitude, 8

	.type	d_sobel_mask_x,@object          # @d_sobel_mask_x
	.globl	d_sobel_mask_x
	.p2align	3, 0x0
d_sobel_mask_x:
	.quad	0
	.size	d_sobel_mask_x, 8

	.type	d_sobel_mask_y,@object          # @d_sobel_mask_y
	.globl	d_sobel_mask_y
	.p2align	3, 0x0
d_sobel_mask_y:
	.quad	0
	.size	d_sobel_mask_y, 8

	.type	d_filter,@object                # @d_filter
	.globl	d_filter
	.p2align	3, 0x0
d_filter:
	.quad	0
	.size	d_filter, 8

	.type	_Z12gaussianBlurPhS_jjPfi,@object # @_Z12gaussianBlurPhS_jjPfi
	.section	.rodata,"a",@progbits
	.globl	_Z12gaussianBlurPhS_jjPfi
	.p2align	3, 0x0
_Z12gaussianBlurPhS_jjPfi:
	.quad	_Z27__device_stub__gaussianBlurPhS_jjPfi
	.size	_Z12gaussianBlurPhS_jjPfi, 8

	.type	_Z12medianFilterPhS_jj,@object  # @_Z12medianFilterPhS_jj
	.globl	_Z12medianFilterPhS_jj
	.p2align	3, 0x0
_Z12medianFilterPhS_jj:
	.quad	_Z27__device_stub__medianFilterPhS_jj
	.size	_Z12medianFilterPhS_jj, 8

	.type	_Z11sobelFilterPhS_PfPdS0_S0_jj,@object # @_Z11sobelFilterPhS_PfPdS0_S0_jj
	.globl	_Z11sobelFilterPhS_PfPdS0_S0_jj
	.p2align	3, 0x0
_Z11sobelFilterPhS_PfPdS0_S0_jj:
	.quad	_Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj
	.size	_Z11sobelFilterPhS_PfPdS0_S0_jj, 8

	.type	_Z17nonMaxSuppressionPhS_Pdjj,@object # @_Z17nonMaxSuppressionPhS_Pdjj
	.globl	_Z17nonMaxSuppressionPhS_Pdjj
	.p2align	3, 0x0
_Z17nonMaxSuppressionPhS_Pdjj:
	.quad	_Z32__device_stub__nonMaxSuppressionPhS_Pdjj
	.size	_Z17nonMaxSuppressionPhS_Pdjj, 8

	.type	_Z15doubleThresholdPhS_jj,@object # @_Z15doubleThresholdPhS_jj
	.globl	_Z15doubleThresholdPhS_jj
	.p2align	3, 0x0
_Z15doubleThresholdPhS_jj:
	.quad	_Z30__device_stub__doubleThresholdPhS_jj
	.size	_Z15doubleThresholdPhS_jj, 8

	.type	_Z10histeresisPhS_jj,@object    # @_Z10histeresisPhS_jj
	.globl	_Z10histeresisPhS_jj
	.p2align	3, 0x0
_Z10histeresisPhS_jj:
	.quad	_Z25__device_stub__histeresisPhS_jj
	.size	_Z10histeresisPhS_jj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"The image has: rows= %d cols= %d\nKernels grid dimensions: gridx=%d gridy= %d\nKernels block dimensions: blockx= %d blocky= %d\n"
	.size	.L.str, 126

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12gaussianBlurPhS_jjPfi"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12medianFilterPhS_jj"
	.size	.L__unnamed_2, 23

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11sobelFilterPhS_PfPdS0_S0_jj"
	.size	.L__unnamed_3, 32

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z17nonMaxSuppressionPhS_Pdjj"
	.size	.L__unnamed_4, 30

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z15doubleThresholdPhS_jj"
	.size	.L__unnamed_5, 26

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z10histeresisPhS_jj"
	.size	.L__unnamed_6, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__gaussianBlurPhS_jjPfi
	.addrsig_sym _Z27__device_stub__medianFilterPhS_jj
	.addrsig_sym _Z26__device_stub__sobelFilterPhS_PfPdS0_S0_jj
	.addrsig_sym _Z32__device_stub__nonMaxSuppressionPhS_Pdjj
	.addrsig_sym _Z30__device_stub__doubleThresholdPhS_jj
	.addrsig_sym _Z25__device_stub__histeresisPhS_jj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_input
	.addrsig_sym d_output_blur
	.addrsig_sym d_output_sobel
	.addrsig_sym d_output_nms
	.addrsig_sym d_output_thresh
	.addrsig_sym d_output
	.addrsig_sym d_edge_direction
	.addrsig_sym d_edge_magnitude
	.addrsig_sym d_sobel_mask_x
	.addrsig_sym d_sobel_mask_y
	.addrsig_sym d_filter
	.addrsig_sym _Z12gaussianBlurPhS_jjPfi
	.addrsig_sym _Z12medianFilterPhS_jj
	.addrsig_sym _Z11sobelFilterPhS_PfPdS0_S0_jj
	.addrsig_sym _Z17nonMaxSuppressionPhS_Pdjj
	.addrsig_sym _Z15doubleThresholdPhS_jj
	.addrsig_sym _Z10histeresisPhS_jj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12gaussianBlurPhS_jjPfi ; -- Begin function _Z12gaussianBlurPhS_jjPfi
	.globl	_Z12gaussianBlurPhS_jjPfi
	.p2align	8
	.type	_Z12gaussianBlurPhS_jjPfi,@function
_Z12gaussianBlurPhS_jjPfi:              ; @_Z12gaussianBlurPhS_jjPfi
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	s_lshl_b32 s15, s15, 4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 4, v2
	v_add_nc_u32_e32 v3, s15, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, s9, v0
	v_cmp_ge_u32_e64 s2, s8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_12
; %bb.1:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x20
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s3, s2
	s_ashr_i32 s11, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s10, 0, s11
	s_cmp_ge_i32 s10, s11
	s_cbranch_scc1 .LBB0_11
; %bb.2:                                ; %.preheader.preheader
	s_load_b64 s[12:13], s[0:1], 0x18
	v_add3_u32 v4, s15, s10, v1
	s_add_i32 s0, s10, s11
	s_mov_b32 s15, s10
	s_mul_i32 s0, s3, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s9, v4, s[10:11]
	v_mov_b32_e32 v2, 0
	s_add_i32 s14, s11, s0
.LBB0_3:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	v_add_nc_u32_e32 v4, s15, v3
	s_mov_b32 s16, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_u32_e64 s0, s8, v4
	v_mov_b32_e32 v4, v1
.LBB0_4:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v5, s16, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s1, -1, v5
	v_cmp_gt_u32_e64 s2, s9, v5
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v5, v0, v4
	s_add_i32 s18, s14, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s19, s18, 31
	s_lshl_b64 s[18:19], s[18:19], 2
	global_load_u8 v5, v5, s[4:5]
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s12, s18
	s_addc_u32 s19, s13, s19
	s_load_b32 s2, s[18:19], 0x0
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v5, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, s2, v5
.LBB0_7:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s17
	v_add_nc_u32_e32 v4, 1, v4
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s16, s11
	s_cbranch_scc0 .LBB0_4
; %bb.9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v1, s9, v1
	s_add_i32 s15, s15, 1
	s_add_i32 s14, s14, s3
	s_cmp_ge_i32 s15, s11
	s_cbranch_scc0 .LBB0_3
; %bb.10:                               ; %._crit_edge58.loopexit
	v_cvt_i32_f32_e32 v2, v2
.LBB0_11:                               ; %._crit_edge58
	v_mad_u64_u32 v[4:5], null, v3, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v4
	v_add_co_u32 v0, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b8 v[0:1], v2, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12gaussianBlurPhS_jjPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12gaussianBlurPhS_jjPfi, .Lfunc_end0-_Z12gaussianBlurPhS_jjPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 444
; NumSgprs: 22
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12medianFilterPhS_jj  ; -- Begin function _Z12medianFilterPhS_jj
	.globl	_Z12medianFilterPhS_jj
	.p2align	8
	.type	_Z12medianFilterPhS_jj,@function
_Z12medianFilterPhS_jj:                 ; @_Z12medianFilterPhS_jj
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v1, s14, 4, v1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_13
; %bb.1:
	v_bfe_u32 v0, v0, 10, 10
	s_add_i32 s3, s4, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, s15, 4, v0
	v_cmp_ne_u32_e64 s2, 0, v0
	v_cmp_gt_u32_e64 s3, s3, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_13
; %bb.2:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_lo_u32 v0, v0, s5
	v_add_nc_u32_e32 v2, 1, v1
	v_add_nc_u32_e32 v3, -1, v1
	s_lshl_b32 s4, s5, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v4, s5, v0
	v_add_nc_u32_e32 v20, v0, v1
	v_add_nc_u32_e32 v5, v0, v2
	v_add_nc_u32_e32 v6, v0, v3
	v_subrev_nc_u32_e32 v0, s4, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v21, 31, v20
	v_add_nc_u32_e32 v7, v4, v3
	v_add_nc_u32_e32 v8, v4, v1
	v_add_nc_u32_e32 v4, v4, v2
	v_add_nc_u32_e32 v2, v0, v2
	v_add_nc_u32_e32 v9, v0, v1
	v_add_nc_u32_e32 v3, v0, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v20
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v21, vcc_lo
	s_clause 0x8
	global_load_u8 v5, v5, s[0:1]
	global_load_u8 v6, v6, s[0:1]
	global_load_u8 v7, v7, s[0:1]
	global_load_u8 v10, v2, s[0:1]
	global_load_u8 v8, v8, s[0:1]
	global_load_u8 v9, v9, s[0:1]
	global_load_u8 v11, v3, s[0:1]
	global_load_u8 v12, v4, s[0:1]
	global_load_u8 v13, v[0:1], off
	s_mov_b64 s[0:1], 0
	s_waitcnt vmcnt(8)
	v_cvt_f32_ubyte0_e32 v0, v5
	s_waitcnt vmcnt(7)
	v_cvt_f32_ubyte0_e32 v1, v6
	s_waitcnt vmcnt(6)
	v_cvt_f32_ubyte0_e32 v2, v7
	s_waitcnt vmcnt(5)
	v_cvt_f32_ubyte0_e32 v3, v10
	s_waitcnt vmcnt(4)
	v_cvt_f32_ubyte0_e32 v4, v8
	s_waitcnt vmcnt(3)
	v_cvt_f32_ubyte0_e32 v5, v9
	s_waitcnt vmcnt(2)
	v_cvt_f32_ubyte0_e32 v6, v11
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v7, v12
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v8, v13
.LBB1_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
	s_mov_b32 m0, s0
	v_mov_b32_e32 v23, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_movrels_b32_e32 v22, v0
	s_cmp_eq_u32 s0, 0
	s_mov_b32 s8, 0
	s_cbranch_scc1 .LBB1_11
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b64 s[4:5], s[0:1]
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr10
.LBB1_5:                                ; %.lr.ph
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
	v_mov_b32_e32 v9, v0
	s_add_i32 m0, s4, -1
	v_dual_mov_b32 v15, v6 :: v_dual_mov_b32 v14, v5
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	v_dual_mov_b32 v11, v2 :: v_dual_mov_b32 v10, v1
	v_movrels_b32_e32 v18, v9
	s_or_b32 s10, s10, exec_lo
	s_or_b32 s11, s11, exec_lo
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $sgpr6_sgpr7
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
                                        ; implicit-def: $sgpr12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 v22, v18
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=2
	s_add_u32 s6, s4, -1
	s_addc_u32 s7, s5, -1
	s_cmp_lt_i32 s4, 2
	v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
	s_cselect_b32 s14, -1, 0
	s_and_not1_b32 s11, s11, exec_lo
	s_and_b32 s14, s14, exec_lo
	s_mov_b32 s12, 0
	s_mov_b32 m0, s4
	s_and_not1_b32 s10, s10, exec_lo
	s_or_b32 s11, s11, s14
	v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
	v_dual_mov_b32 v4, v13 :: v_dual_mov_b32 v5, v14
	v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v7, v16
	v_mov_b32_e32 v8, v17
	v_movreld_b32_e32 v0, v18
.LBB1_7:                                ; %Flow95
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s13, exec_lo, s11
	v_mov_b32_e32 v19, s5
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v18, s4
	s_or_b32 s8, s13, s8
	s_and_not1_b32 s4, s9, exec_lo
	s_and_b32 s5, s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s9, s4, s5
	s_mov_b64 s[4:5], s[6:7]
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_5
; %bb.8:                                ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_and_saveexec_b32 s4, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
; %bb.9:                                ; %.lr.ph..critedge.loopexit_crit_edge
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
	v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
	v_dual_mov_b32 v4, v13 :: v_dual_mov_b32 v5, v14
	v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v7, v16
	v_dual_mov_b32 v8, v17 :: v_dual_mov_b32 v23, v18
; %bb.10:                               ; %Flow
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_11:                               ; %.critedge
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 8, v23
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 9
	v_cndmask_b32_e32 v8, v8, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v23
	v_cndmask_b32_e32 v7, v7, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v23
	v_cndmask_b32_e32 v6, v6, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v23
	v_cndmask_b32_e32 v5, v5, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v23
	v_cndmask_b32_e32 v4, v4, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v23
	v_cndmask_b32_e32 v3, v3, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v23
	v_cndmask_b32_e32 v2, v2, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v23
	v_cndmask_b32_e32 v1, v1, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v23
	v_cndmask_b32_e32 v0, v0, v22, vcc_lo
	s_cbranch_scc1 .LBB1_3
; %bb.12:
	v_add_co_u32 v0, vcc_lo, s2, v20
	v_cvt_i32_f32_e32 v2, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v21, vcc_lo
	global_store_b8 v[0:1], v2, off
.LBB1_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12medianFilterPhS_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12medianFilterPhS_jj, .Lfunc_end1-_Z12medianFilterPhS_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11sobelFilterPhS_PfPdS0_S0_jj ; -- Begin function _Z11sobelFilterPhS_PfPdS0_S0_jj
	.globl	_Z11sobelFilterPhS_PfPdS0_S0_jj
	.p2align	8
	.type	_Z11sobelFilterPhS_PfPdS0_S0_jj,@function
_Z11sobelFilterPhS_PfPdS0_S0_jj:        ; @_Z11sobelFilterPhS_PfPdS0_S0_jj
; %bb.0:
	s_load_b64 s[12:13], s[0:1], 0x30
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_lshl_b32 s14, s14, 4
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s14, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v3, s15, 4, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s13, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s12, v3
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_25
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x20
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v0, 2, v3
	v_mov_b32_e32 v6, 0
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s13, v0, v[1:2]
	v_add3_u32 v0, v4, s14, 2
.LBB2_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v0
	s_mov_b64 s[14:15], 0
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_u8 v4, v1, s[4:5]
	s_add_u32 s16, s0, s14
	s_addc_u32 s17, s1, s15
	s_add_u32 s18, s2, s14
	s_addc_u32 s19, s3, s15
	s_load_b32 s16, s[16:17], 0x0
	s_load_b32 s17, s[18:19], 0x0
	v_subrev_nc_u32_e32 v1, s13, v1
	s_add_u32 s14, s14, 12
	s_addc_u32 s15, s15, 0
	s_cmp_eq_u32 s14, 36
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v4, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, s16, v4
	v_fmac_f32_e32 v6, s17, v4
	s_cbranch_scc0 .LBB2_3
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s12, s12, 1
	s_add_u32 s0, s0, 4
	v_add_nc_u32_e32 v0, -1, v0
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s12, 3
	s_cbranch_scc0 .LBB2_2
; %bb.5:
	v_mul_f32_e32 v0, v6, v6
	s_mov_b32 s2, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v7, v7
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, v0, v1, vcc_lo
	v_sqrt_f32_e32 v0, v8
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v1, -1, v0
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_class_f32_e64 s1, v8, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, -v1, v0, v8
	v_fma_f32 v9, -v4, v0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v5
	v_cndmask_b32_e64 v5, v0, v1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s0, 0, v9
	v_mad_u64_u32 v[0:1], null, v3, s13, v[2:3]
	v_cndmask_b32_e64 v2, v5, v4, s0
	v_cmp_neq_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	v_mul_f32_e32 v3, 0x37800000, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_dual_cndmask_b32 v9, v2, v3 :: v_dual_mov_b32 v2, 0
	v_mov_b32_e32 v3, 0
	v_cmp_neq_f32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v9, v8, s1
	v_add_co_u32 v8, s1, s8, v4
	v_add_co_ci_u32_e64 v9, s1, s9, v5, s1
	v_add_co_u32 v10, s1, s6, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f32_e32 v13, v12
	v_add_co_ci_u32_e64 v11, s1, s7, v1, s1
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s0, s0, vcc_lo
	global_store_b32 v[8:9], v12, off
	global_store_b8 v[10:11], v13, off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_7
; %bb.6:
	v_max_f32_e64 v4, |v6|, |v6|
	v_max_f32_e64 v5, |v7|, |v7|
	s_mov_b32 s0, 0x3b2d2a58
	v_cmp_gt_f32_e64 vcc_lo, |v6|, |v7|
	v_cmp_class_f32_e64 s3, v6, 0x204
	s_mov_b32 s4, 0xf01b866e
	v_max_f32_e32 v8, v5, v4
	v_min_f32_e32 v4, v5, v4
	s_mov_b32 s5, 0x400921f9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v9, v8
	v_frexp_exp_i32_f32_e32 v8, v8
	v_rcp_f32_e32 v5, v9
	v_frexp_exp_i32_f32_e32 v9, v4
	v_frexp_mant_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v9, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, v4, v5
	v_ldexp_f32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v4, v4
	v_fmaak_f32 v8, s0, v5, 0xbc7a590c
	v_cmp_gt_i32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v8, v5, v8, 0x3d29fb3f
	v_cndmask_b32_e64 v9, 0, 0x40490fdb, s0
	v_cmp_class_f32_e64 s0, v7, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v5, v8, 0xbd97d4d7
	v_fmaak_f32 v8, v5, v8, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v5, v8, 0xbe1160e6
	v_fmaak_f32 v8, v5, v8, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v5, v8, 0xbeaaaa62
	v_dual_mul_f32 v5, v5, v8 :: v_dual_mov_b32 v8, 0x4016cbe4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v4, v5
	v_sub_f32_e32 v5, 0x3fc90fdb, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	v_sub_f32_e32 v5, 0x40490fdb, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cndmask_b32_e32 v5, 0x3f490fdb, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e32 v4, v4, v9, vcc_lo
	s_and_b32 vcc_lo, s0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v6
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v4, 0x7fffffff, v4, v6
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], 0x40668000, v[4:5]
	v_div_scale_f64 v[6:7], null, s[4:5], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_div_scale_f64 v[10:11], vcc_lo, v[4:5], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[10:11], v[8:9]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
	v_div_fixup_f64 v[4:5], v[6:7], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v4, v[4:5]
	v_cvt_f64_f32_e32 v[4:5], v4
.LBB2_7:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0xc0368000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0x40368000, v[4:5]
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_23
; %bb.8:
	v_cmp_nlt_f64_e32 vcc_lo, 0x4063b000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0x40695000, v[4:5]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s2, s0, -1
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB2_22
; %bb.9:
	s_mov_b32 s4, 0x66666666
	s_mov_b32 s5, 0xc063b666
	v_cmp_nlt_f64_e32 vcc_lo, 0xc0695000, v[4:5]
	v_cmp_nge_f64_e64 s0, s[4:5], v[4:5]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s4, s0, -1
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB2_21
; %bb.10:
	v_cmp_nlt_f64_e32 vcc_lo, 0x40368000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0x4050e000, v[4:5]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0x40468000
	s_delay_alu instid0(VALU_DEP_3)
	s_or_b32 s7, vcc_lo, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s6, s7
	s_cbranch_execz .LBB2_20
; %bb.11:
	v_cmp_nlt_f64_e32 vcc_lo, 0xc063b000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0xc05c2000, v[4:5]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0x40468000
	s_mov_b32 s12, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s7, s0, -1
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB2_19
; %bb.12:
	v_cmp_nlt_f64_e32 vcc_lo, 0x4050e000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0x405c2000, v[4:5]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0x40568000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_18
; %bb.13:
	v_cmp_nlt_f64_e32 vcc_lo, 0xc05c2000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0xc050e000, v[4:5]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0x40568000
	s_mov_b32 s14, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s12, s0, -1
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB2_17
; %bb.14:
	v_cmp_nlt_f64_e32 vcc_lo, 0x405c2000, v[4:5]
	v_cmp_nge_f64_e64 s0, 0x4063b000, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s15, s0
; %bb.15:
	v_cmp_lt_f64_e32 vcc_lo, 0xc050e000, v[4:5]
	v_cmp_ge_f64_e64 s0, 0xc0368000, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_or_not1_b32 s14, s0, exec_lo
; %bb.16:                               ; %Flow150
	s_or_b32 exec_lo, exec_lo, s15
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0x4060e000
	s_and_not1_b32 s0, s12, exec_lo
	s_and_b32 s12, s14, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s12, s0, s12
.LBB2_17:                               ; %Flow149
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s12, s12, exec_lo
.LBB2_18:                               ; %Flow148
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s7, exec_lo
	s_and_b32 s7, s12, exec_lo
	s_or_b32 s7, s0, s7
.LBB2_19:                               ; %Flow147
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s7, exec_lo
.LBB2_20:                               ; %Flow146
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s4, s4, s0
.LBB2_21:                               ; %Flow145
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s2, s4, exec_lo
	s_or_b32 s2, s0, s2
.LBB2_22:                               ; %Flow144
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s2, s2, exec_lo
.LBB2_23:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_25
; %bb.24:                               ; %.sink.split
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB2_25:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11sobelFilterPhS_PfPdS0_S0_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11sobelFilterPhS_PfPdS0_S0_jj, .Lfunc_end2-_Z11sobelFilterPhS_PfPdS0_S0_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1640
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z17nonMaxSuppressionPhS_Pdjj ; -- Begin function _Z17nonMaxSuppressionPhS_Pdjj
	.globl	_Z17nonMaxSuppressionPhS_Pdjj
	.p2align	8
	.type	_Z17nonMaxSuppressionPhS_Pdjj,@function
_Z17nonMaxSuppressionPhS_Pdjj:          ; @_Z17nonMaxSuppressionPhS_Pdjj
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v6, s14, 4, v1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v6
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_19
; %bb.1:
	v_bfe_u32 v0, v0, 10, 10
	s_add_i32 s3, s4, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v8, s15, 4, v0
	v_cmp_ne_u32_e64 s2, 0, v8
	v_cmp_gt_u32_e64 s3, s3, v8
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_19
; %bb.2:
	v_mul_lo_u32 v9, v8, s5
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $sgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v9, v6
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_load_b128 s[0:3], s[0:1], 0x0
	global_load_b64 v[4:5], v[2:3], off
                                        ; implicit-def: $vgpr2_vgpr3
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f64_e32 0, v[4:5]
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB3_14
; %bb.3:
	s_mov_b32 s8, 0
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $sgpr6
	v_cmpx_neq_f64_e32 0x40468000, v[4:5]
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB3_11
; %bb.4:
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $sgpr6
	v_cmpx_neq_f64_e32 0x40568000, v[4:5]
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB3_8
; %bb.5:
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr7
	v_cmpx_eq_f64_e32 0x4060e000, v[4:5]
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB3_7
; %bb.6:
	v_add_nc_u32_e32 v2, -1, v8
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s5
	v_add3_u32 v3, v6, v2, -1
	v_lshl_add_u32 v4, s5, 1, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s10, s0, v3
	v_add_co_ci_u32_e64 v3, null, s1, 0, s10
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v7, v6, v4, 1
.LBB3_7:                                ; %Flow94
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s6, 0x437f0000
	s_and_b32 s8, s8, exec_lo
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr6
.LBB3_8:                                ; %Flow93
	s_and_not1_saveexec_b32 s9, s9
	s_cbranch_execz .LBB3_10
; %bb.9:
	v_add_nc_u32_e32 v2, s5, v9
	s_lshl_b32 s10, s5, 1
	s_or_b32 s8, s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v2, v6
	v_subrev_nc_u32_e32 v4, s10, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, s10, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s10
	v_add_nc_u32_e32 v7, v4, v6
.LBB3_10:                               ; %Flow95
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s8, s8, exec_lo
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr6
.LBB3_11:                               ; %Flow92
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB3_13
; %bb.12:
	v_add_nc_u32_e32 v2, s5, v9
	s_lshl_b32 s5, s5, 1
	s_or_b32 s8, s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v6, v2, -1
	v_subrev_nc_u32_e32 v4, s5, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, s5, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s5
	v_add3_u32 v7, v6, v4, 1
.LBB3_13:                               ; %Flow96
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s7, s8, exec_lo
.LBB3_14:                               ; %Flow
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB3_16
; %bb.15:
	v_add_nc_u32_e32 v2, 1, v0
	v_add_nc_u32_e32 v7, -1, v0
	s_or_b32 s7, s7, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s5, s0, v2
	v_add_co_ci_u32_e64 v3, null, s1, 0, s5
.LBB3_16:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s4
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s6
	s_and_saveexec_b32 s4, s7
	s_cbranch_execz .LBB3_18
; %bb.17:                               ; %.sink.split
	global_load_u8 v2, v[2:3], off
	s_waitcnt lgkmcnt(0)
	global_load_u8 v3, v7, s[0:1]
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v4, v2
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v5, v3
.LBB3_18:                               ; %.sink.split74
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, v4, v3
	v_cmp_nle_f32_e64 s0, v5, v3
	s_or_b32 s0, vcc_lo, s0
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_cndmask_b32_e64 v2, v2, 0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b8 v[0:1], v2, off
.LBB3_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17nonMaxSuppressionPhS_Pdjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z17nonMaxSuppressionPhS_Pdjj, .Lfunc_end3-_Z17nonMaxSuppressionPhS_Pdjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 724
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15doubleThresholdPhS_jj ; -- Begin function _Z15doubleThresholdPhS_jj
	.globl	_Z15doubleThresholdPhS_jj
	.p2align	8
	.type	_Z15doubleThresholdPhS_jj,@function
_Z15doubleThresholdPhS_jj:              ; @_Z15doubleThresholdPhS_jj
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, s14, 4, v1
	v_lshl_add_u32 v3, s15, 4, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e32 vcc_lo, s5, v2
	v_cmp_gt_u32_e64 s2, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_9
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[0:1], null, v3, s5, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_u16_e32 0x46, v2
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB4_7
; %bb.2:
	v_add_co_u32 v0, s0, s2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u16_e32 20, v2
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB4_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	global_store_b8 v[0:1], v2, off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB4_4:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB4_6
; %bb.5:
	v_mov_b32_e32 v2, 50
	global_store_b8 v[0:1], v2, off
.LBB4_6:                                ; %Flow40
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB4_7:                                ; %Flow41
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB4_9
; %bb.8:
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_mov_b32_e32 v2, 0xff
	global_store_b8 v[0:1], v2, off
.LBB4_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15doubleThresholdPhS_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z15doubleThresholdPhS_jj, .Lfunc_end4-_Z15doubleThresholdPhS_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10histeresisPhS_jj    ; -- Begin function _Z10histeresisPhS_jj
	.globl	_Z10histeresisPhS_jj
	.p2align	8
	.type	_Z10histeresisPhS_jj,@function
_Z10histeresisPhS_jj:                   ; @_Z10histeresisPhS_jj
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, s14, 4, v1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s9, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB5_20
; %bb.1:
	v_bfe_u32 v0, v0, 10, 10
	s_add_i32 s3, s8, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, s15, 4, v0
	v_cmp_ne_u32_e64 s2, 0, v0
	v_cmp_gt_u32_e64 s3, s3, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB5_20
; %bb.2:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v5, v0, s9
	s_mov_b32 s0, -1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v5, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	global_load_u8 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 50, v3
	s_cbranch_execz .LBB5_18
; %bb.3:
	v_add_nc_u32_e32 v3, 1, v2
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v5, v3
	global_load_u8 v4, v4, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0xff, v4
	v_cmpx_ne_u16_e32 0xff, v4
	s_cbranch_execz .LBB5_17
; %bb.4:
	v_add_nc_u32_e32 v4, -1, v2
	s_mov_b32 s1, -1
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v5, v4
	global_load_u8 v6, v6, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0xff, v6
	s_cbranch_execz .LBB5_16
; %bb.5:
	v_add_nc_u32_e32 v5, s9, v5
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v5, v4
	global_load_u8 v6, v6, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e64 s0, 0xff, v6
	v_cmpx_ne_u16_e32 0xff, v6
	s_cbranch_execz .LBB5_15
; %bb.6:
	s_lshl_b32 s1, s9, 1
	s_mov_b32 s2, -1
	v_subrev_nc_u32_e32 v6, s1, v5
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v6, v3
	global_load_u8 v7, v7, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0xff, v7
	s_cbranch_execz .LBB5_14
; %bb.7:
	v_add_nc_u32_e32 v7, v5, v2
	s_mov_b32 s12, exec_lo
	global_load_u8 v7, v7, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e64 s1, 0xff, v7
	v_cmpx_ne_u16_e32 0xff, v7
	s_cbranch_execz .LBB5_13
; %bb.8:
	v_add_nc_u32_e32 v2, v6, v2
	s_mov_b32 s14, -1
	s_mov_b32 s13, exec_lo
	global_load_u8 v2, v2, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0xff, v2
	s_cbranch_execz .LBB5_12
; %bb.9:
	v_add_nc_u32_e32 v2, v6, v4
	s_mov_b32 s15, exec_lo
	global_load_u8 v2, v2, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e64 s14, 0xff, v2
	v_cmpx_ne_u16_e32 0xff, v2
	s_cbranch_execz .LBB5_11
; %bb.10:
	v_add_nc_u32_e32 v2, v5, v3
	global_load_u8 v2, v2, s[4:5]
	s_and_not1_b32 s4, s14, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e64 s2, 0xff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s14, s4, s2
.LBB5_11:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_not1_b32 s14, s14, exec_lo
.LBB5_12:                               ; %Flow87
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s2, s14, exec_lo
	s_or_b32 s1, s1, s2
.LBB5_13:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_not1_b32 s2, s1, exec_lo
.LBB5_14:                               ; %Flow85
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s1, s2, exec_lo
	s_or_b32 s0, s0, s1
.LBB5_15:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_not1_b32 s1, s0, exec_lo
.LBB5_16:                               ; %Flow83
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, vcc_lo, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 vcc_lo, s0, s1
.LBB5_17:                               ; %Flow82
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v3, 0xff
	s_or_not1_b32 s0, vcc_lo, exec_lo
.LBB5_18:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB5_20
; %bb.19:                               ; %.sink.split
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b8 v[0:1], v3, off
.LBB5_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10histeresisPhS_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z10histeresisPhS_jj, .Lfunc_end5-_Z10histeresisPhS_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 720
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12gaussianBlurPhS_jjPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z12gaussianBlurPhS_jjPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12medianFilterPhS_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12medianFilterPhS_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11sobelFilterPhS_PfPdS0_S0_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z11sobelFilterPhS_PfPdS0_S0_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17nonMaxSuppressionPhS_Pdjj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17nonMaxSuppressionPhS_Pdjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15doubleThresholdPhS_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15doubleThresholdPhS_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10histeresisPhS_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10histeresisPhS_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
