#include<stdio.h>
#define iteration_max 100
#define CEIL(a, b) (((a) + (b) - 1)/(b))

// Function using of the internet
////////////////////////////////////////////////////////////////////////////////
// These are CUDA Helper functions

// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err)           __checkCudaErrors (err, __FILE__, __LINE__)

inline void __checkCudaErrors( cudaError err, const char *file, const int line )
{
	if( cudaSuccess != err) {
		fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
				file, line, (int)err, cudaGetErrorString( err ) );
		exit(-1);

	}
}
/* Traz a GLOBAL para cá */
/* Calc_mandelbrot NVIDIA_CUDA */
__global__ void kernel(int width, int height, float min_real, float min_imag, float max_real, float max_imag, int *buffer){
	int index_vector = (blockIdx.x * blockDim.x) + threadIdx.x;
	int val_for_cal = buffer[index_vector];
	int i = val_for_cal / width;
	int j = val_for_cal % width;
	float del_x = (max_real - min_real)/width;
	float del_y= (max_imag - min_imag)/height;
	int iteration = 0;
	float x_point = min_real + del_x * i;
	float y_point = max_imag - del_y * j;
	float z_y = y_point;
	float z_x = x_point;
	float z_x2 = z_x * z_x;
	float z_y2 = z_y * z_y;

	for(iteration = 0; iteration < iteration_max && ((z_x2 + z_y2) <= 4); iteration++){
		z_y = (2.0 * z_x * z_y)+ y_point;
		z_x = z_x2 - z_y2 + x_point;
		z_x2 = z_x * z_x;
		z_y2 = z_y * z_y;
	}
	buffer[index_vector] = iteration;
};


extern "C" void invoke_cuda(int tam_vetor, int width, int height, float *min_real, float *min_imag, float *max_real, float *max_imag, int threads, int *vetor){
	int *d_vetor;
	
	/* Aloco na placa de video */
	checkCudaErrors(cudaMalloc(&d_vetor, tam_vetor*sizeof(int)));


	checkCudaErrors(cudaMemcpy(d_vetor, vetor, tam_vetor*sizeof(int), cudaMemcpyHostToDevice));
	
	/* Setar os bocos para trabalhar na placa de video */
	int threads_per_block = threads;
	int num_blocks = CEIL((tam_vetor), threads_per_block);
		
	kernel<<<num_blocks, threads_per_block>>>(width, height, *min_real, *min_imag, *max_real, *max_imag, d_vetor);

	checkCudaErrors(cudaDeviceSynchronize());
        
	/* Pego o buffer da Placa de video e trago para o PC */
	checkCudaErrors(cudaMemcpy(vetor, d_vetor, tam_vetor*sizeof(int), cudaMemcpyDeviceToHost));
	checkCudaErrors(cudaFree(d_vetor));
}

	.file	"tmpxft_00300492_00000000-6_so_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z17__checkCudaErrors9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%s(%i) : CUDA Runtime API error %d: %s.\n"
	.section	.text._Z17__checkCudaErrors9cudaErrorPKci,"axG",@progbits,_Z17__checkCudaErrors9cudaErrorPKci,comdat
	.weak	_Z17__checkCudaErrors9cudaErrorPKci
	.type	_Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movl	%edx, 12(%rsp)
	movl	%edi, 8(%rsp)
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	movl	$2, %esi
	pushq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC0(%rip), %rdx
	pushq	%rax
	.cfi_def_cfa_offset 48
	movl	24(%rsp), %r9d
	xorl	%eax, %eax
	movl	28(%rsp), %r8d
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
	.text
	.globl	_Z31__device_stub__Z6kerneliiffffPiiiffffPi
	.type	_Z31__device_stub__Z6kerneliiffffPiiiffffPi, @function
_Z31__device_stub__Z6kerneliiffffPiiiffffPi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	32(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movss	%xmm3, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z6kerneliiffffPi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z31__device_stub__Z6kerneliiffffPiiiffffPi, .-_Z31__device_stub__Z6kerneliiffffPiiiffffPi
	.globl	_Z6kerneliiffffPi
	.type	_Z6kerneliiffffPi, @function
_Z6kerneliiffffPi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z6kerneliiffffPiiiffffPi
	.cfi_endproc
.LFE2054:
	.size	_Z6kerneliiffffPi, .-_Z6kerneliiffffPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/SouzaGuilherme/IntroductionParallelUSP/master/EP3/so_cuda.cu"
	.text
	.globl	invoke_cuda
	.type	invoke_cuda, @function
invoke_cuda:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r8, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	160(%rsp), %rax
	movl	%esi, 24(%rsp)
	movl	%edx, 28(%rsp)
	movl	152(%rsp), %ebx
	movq	%rax, 16(%rsp)
	movq	144(%rsp), %r13
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movslq	%edi, %rax
	leaq	40(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	$52, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$55, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	leal	-1(%rbp,%rbx), %eax
	movl	%ebx, 60(%rsp)
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rcx
	cltd
	xorl	%r8d, %r8d
	idivl	%ebx
	movq	%rcx, 52(%rsp)
	movl	56(%rsp), %esi
	movq	%rcx, 64(%rsp)
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	movl	%eax, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	40(%rsp), %rdx
	movss	0(%r13), %xmm3
	movss	(%r12), %xmm2
	movss	(%r15), %xmm1
	movss	(%r14), %xmm0
	movl	28(%rsp), %esi
	movl	24(%rsp), %edi
	call	_Z31__device_stub__Z6kerneliiffffPiiiffffPi
.L14:
	call	cudaDeviceSynchronize@PLT
	movl	$63, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$66, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movl	$67, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	invoke_cuda, .-invoke_cuda
	.section	.rodata.str1.1
.LC2:
	.string	"_Z6kerneliiffffPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kerneliiffffPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#define iteration_max 100
#define CEIL(a, b) (((a) + (b) - 1)/(b))

// Function using of the internet
////////////////////////////////////////////////////////////////////////////////
// These are CUDA Helper functions

// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err)           __checkCudaErrors (err, __FILE__, __LINE__)

inline void __checkCudaErrors( hipError_t err, const char *file, const int line )
{
	if( hipSuccess != err) {
		fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
				file, line, (int)err, hipGetErrorString( err ) );
		exit(-1);

	}
}
/* Traz a GLOBAL para cá */
/* Calc_mandelbrot NVIDIA_CUDA */
__global__ void kernel(int width, int height, float min_real, float min_imag, float max_real, float max_imag, int *buffer){
	int index_vector = (blockIdx.x * blockDim.x) + threadIdx.x;
	int val_for_cal = buffer[index_vector];
	int i = val_for_cal / width;
	int j = val_for_cal % width;
	float del_x = (max_real - min_real)/width;
	float del_y= (max_imag - min_imag)/height;
	int iteration = 0;
	float x_point = min_real + del_x * i;
	float y_point = max_imag - del_y * j;
	float z_y = y_point;
	float z_x = x_point;
	float z_x2 = z_x * z_x;
	float z_y2 = z_y * z_y;

	for(iteration = 0; iteration < iteration_max && ((z_x2 + z_y2) <= 4); iteration++){
		z_y = (2.0 * z_x * z_y)+ y_point;
		z_x = z_x2 - z_y2 + x_point;
		z_x2 = z_x * z_x;
		z_y2 = z_y * z_y;
	}
	buffer[index_vector] = iteration;
};


extern "C" void invoke_cuda(int tam_vetor, int width, int height, float *min_real, float *min_imag, float *max_real, float *max_imag, int threads, int *vetor){
	int *d_vetor;
	
	/* Aloco na placa de video */
	checkCudaErrors(hipMalloc(&d_vetor, tam_vetor*sizeof(int)));


	checkCudaErrors(hipMemcpy(d_vetor, vetor, tam_vetor*sizeof(int), hipMemcpyHostToDevice));
	
	/* Setar os bocos para trabalhar na placa de video */
	int threads_per_block = threads;
	int num_blocks = CEIL((tam_vetor), threads_per_block);
		
	kernel<<<num_blocks, threads_per_block>>>(width, height, *min_real, *min_imag, *max_real, *max_imag, d_vetor);

	checkCudaErrors(hipDeviceSynchronize());
        
	/* Pego o buffer da Placa de video e trago para o PC */
	checkCudaErrors(hipMemcpy(vetor, d_vetor, tam_vetor*sizeof(int), hipMemcpyDeviceToHost));
	checkCudaErrors(hipFree(d_vetor));
}

	.text
	.file	"so_cuda.hip"
	.globl	_Z21__device_stub__kerneliiffffPi # -- Begin function _Z21__device_stub__kerneliiffffPi
	.type	_Z21__device_stub__kerneliiffffPi,@function
_Z21__device_stub__kerneliiffffPi:      # @_Z21__device_stub__kerneliiffffPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	12(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	8(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	4(%rsp), %r8
	movss	%xmm2, (%r8)
	movq	%rsp, %r9
	movss	%xmm3, (%r9)
	leaq	40(%rsp), %r10
	movq	%rdx, (%r10)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdi, 24(%rbx)
	movq	%r8, 32(%rbx)
	movq	%r9, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kerneliiffffPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kerneliiffffPi, .Lfunc_end0-_Z21__device_stub__kerneliiffffPi
	.cfi_endproc
                                        # -- End function
	.globl	invoke_cuda                     # -- Begin function invoke_cuda
	.type	invoke_cuda,@function
invoke_cuda:                            # @invoke_cuda
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movq	%r8, %r13
	movq	%rcx, %rbp
	movl	%edx, 12(%rsp)                  # 4-byte Spill
	movl	%esi, 8(%rsp)                   # 4-byte Spill
	movl	%edi, %r15d
	movslq	%edi, %rbx
	shlq	$2, %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.2:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit
	movq	96(%rsp), %r14
	movq	(%rsp), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.4:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit19
	movl	88(%rsp), %ecx
	leal	(%r15,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	btsq	$32, %rax
	movl	%ecx, %edx
	btsq	$32, %rdx
	movq	%rax, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	80(%rsp), %rax
	movss	(%rbp), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	(%r13), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movss	(%rcx), %xmm2                   # xmm2 = mem[0],zero,zero,zero
	movss	(%rax), %xmm3                   # xmm3 = mem[0],zero,zero,zero
	movq	(%rsp), %rdx
	movl	8(%rsp), %edi                   # 4-byte Reload
	movl	12(%rsp), %esi                  # 4-byte Reload
	callq	_Z21__device_stub__kerneliiffffPi
.LBB1_6:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.8:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit21
	movq	(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.12:                               # %_Z17__checkCudaErrors10hipError_tPKci.exit23
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.14:                               # %_Z17__checkCudaErrors10hipError_tPKci.exit25
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 80
	movl	%eax, %r14d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$54, %ecx
	movl	%r14d, %r8d
	jmp	.LBB1_11
.LBB1_3:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$57, %ecx
	movl	%r12d, %r8d
	jmp	.LBB1_11
.LBB1_7:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$65, %ecx
	movl	%ebp, %r8d
	jmp	.LBB1_11
.LBB1_9:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %edx
	movq	%r14, %rdi
	movl	$68, %ecx
	jmp	.LBB1_10
.LBB1_13:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %edx
	movq	%r14, %rdi
	movl	$69, %ecx
.LBB1_10:
	movl	%ebx, %r8d
.LBB1_11:
	movq	%rax, %r9
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	invoke_cuda, .Lfunc_end1-invoke_cuda
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kerneliiffffPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kerneliiffffPi,@object       # @_Z6kerneliiffffPi
	.section	.rodata,"a",@progbits
	.globl	_Z6kerneliiffffPi
	.p2align	3, 0x0
_Z6kerneliiffffPi:
	.quad	_Z21__device_stub__kerneliiffffPi
	.size	_Z6kerneliiffffPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/SouzaGuilherme/IntroductionParallelUSP/master/EP3/so_cuda.hip"
	.size	.L.str, 124

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%s(%i) : CUDA Runtime API error %d: %s.\n"
	.size	.L.str.1, 41

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kerneliiffffPi"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kerneliiffffPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kerneliiffffPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kerneliiffffPi       ; -- Begin function _Z6kerneliiffffPi
	.globl	_Z6kerneliiffffPi
	.p2align	8
	.type	_Z6kerneliiffffPi,@function
_Z6kerneliiffffPi:                      ; @_Z6kerneliiffffPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_ashr_i32 s2, s4, 31
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_add_i32 s0, s4, s2
	v_sub_f32_e64 v8, s9, s7
	s_xor_b32 s3, s0, s2
	v_cvt_f32_i32_e32 v9, s5
	v_cvt_f32_u32_e32 v3, s3
	s_sub_i32 s0, 0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_cvt_f32_i32_e32 v7, s4
	v_div_scale_f32 v11, null, v9, v9, v8
	v_rcp_iflag_f32_e32 v3, v3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v11
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v11, v14, 1.0
	global_load_b32 v2, v[0:1], off
	v_fmac_f32_e32 v14, v17, v14
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v6, v2, v5
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s0, v3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v3, v4
	v_xor_b32_e32 v4, v6, v5
	v_sub_f32_e64 v6, s8, s6
	v_xor_b32_e32 v5, s2, v5
	v_mul_hi_u32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v10, null, v7, v7, v6
	v_rcp_f32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v12, v3, s3
	v_add_nc_u32_e32 v15, 1, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v10, v13, 1.0
	v_sub_nc_u32_e32 v4, v4, v12
	v_div_scale_f32 v12, vcc_lo, v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v18, s3, v4
	v_cmp_le_u32_e64 s0, s3, v4
	v_cndmask_b32_e64 v3, v3, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v18, s0
	v_fmac_f32_e32 v13, v16, v13
	v_div_scale_f32 v15, s1, v8, v9, v8
	v_add_nc_u32_e32 v16, 1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s0, s3, v4
	v_dual_mul_f32 v17, v12, v13 :: v_dual_mul_f32 v4, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v16, s0
	v_fma_f32 v16, -v10, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v11, v4, v15
	s_mov_b32 s0, exec_lo
	v_xor_b32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v17, v16, v13 :: v_dual_fmac_f32 v4, v18, v14
	v_sub_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, -v10, v17, v12
	v_fma_f32 v11, -v11, v4, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v3, s4
	v_div_fmas_f32 v5, v5, v13, v17
	s_mov_b32 vcc_lo, s1
	v_cvt_f32_i32_e32 v3, v3
	v_div_fmas_f32 v4, v11, v14, v4
	s_mov_b32 s1, 0
	v_div_fixup_f32 v6, v5, v7, v6
	v_sub_nc_u32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v4, v4, v9, v8
	v_mov_b32_e32 v9, 0
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v4, v2, s9
	v_fma_f32 v4, v6, v3, s6
	v_mul_f32_e32 v6, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v4, v4, v6
	v_cmpx_ge_f32_e32 4.0, v2
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph
	v_cvt_f64_f32_e32 v[2:3], v5
	v_mul_f32_e32 v8, v4, v4
	v_mov_b32_e32 v7, v4
	s_mov_b32 s2, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[9:10], v7
	v_cvt_f64_f32_e32 v[11:12], v5
	s_add_i32 s3, s2, 1
	v_sub_f32_e32 v6, v8, v6
	s_cmpk_gt_u32 s2, 0x62
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], v[9:10]
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v5, v[9:10]
	v_mov_b32_e32 v9, s3
	v_dual_add_f32 v7, v4, v6 :: v_dual_mul_f32 v6, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v7, v7, v6
	v_cmp_nge_f32_e32 vcc_lo, 4.0, v8
	v_mul_f32_e32 v8, v7, v7
	s_or_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s1, s2, s1
	s_mov_b32 s2, s3
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_4:                                ; %Flow70
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	global_store_b32 v[0:1], v9, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kerneliiffffPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kerneliiffffPi, .Lfunc_end0-_Z6kerneliiffffPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 716
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kerneliiffffPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kerneliiffffPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
