#define DEBUG
#ifdef DEBUG
#include    <stdio.h>
#endif
#include    <time.h>        // for rand()

#define BLOCKDIM    8

#define WIDTH       10
#define HEIGHT      10
#define RADIUS      BLOCKDIM-2

__global__ void shared1D(int * in, int * out, int radius, int n) {
    extern __shared__ int smem[];

    int tx = threadIdx.x;
    int bx = blockIdx.x;
    int dx = blockDim.x;
    int xIndex = tx + bx*dx;
    int index = xIndex;

#define SMEM(txOffset)    smem[tx + txOffset]

    if (xIndex < n)
        SMEM(radius) = in[index];
    else
        SMEM(radius) = in[n - 1];

    if (tx < radius) {
        if (xIndex - radius >= 0) {
            SMEM(0) = in[index - radius];
        } else {
            SMEM(0) = in[0];
        }

        if (xIndex + dx < n) {
            SMEM(dx + radius) = in[index + dx];
        } else {
            SMEM(dx + radius) = in[n - 1];
        }
    }

    __syncthreads();

    if (xIndex >= n)
        return ;

    tx += radius;
    out[index] = SMEM(RADIUS-1);
#undef SMEM
}

__global__ void horizShared2D(int * in, int * out, int radius, int width, int height) {
    extern __shared__ int smem[];

    int tx = threadIdx.x,   ty = threadIdx.y;
    int bx = blockIdx.x,    by = blockIdx.y;
    int dx = blockDim.x,    dy = blockDim.y;
    int xIndex = tx + bx*dx;
    int yIndex = ty + by*dy;
    int index = xIndex + yIndex*width;

    if (yIndex >= height)
        return ;

#define SMEM(txOffset, tyOffset)    smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]

    if (xIndex < width)
        SMEM(radius, 0) = in[index];
    else
        SMEM(radius, 0) = in[(yIndex+1)*width - 1];

    if (tx < radius) {
        if (xIndex - radius >= 0) {
            SMEM(0, 0) = in[index - radius];
        } else {
            SMEM(0, 0) = in[yIndex*width];
        }

        if (xIndex + dx < width) {
            SMEM(dx + radius, 0) = in[index + dx];
        } else {
            SMEM(dx + radius, 0) = in[(yIndex + 1)*width - 1];
        }
    }

    __syncthreads();

    if (xIndex >= width)
        return ;

    tx += radius;
    out[index] = SMEM(RADIUS-1, 0);
#undef SMEM
}

__global__ void vertShared2D(int * in, int * out, int radius, int width, int height) {
    extern __shared__ int smem[];

    int tx = threadIdx.x,   ty = threadIdx.y;
    int bx = blockIdx.x,    by = blockIdx.y;
    int dx = blockDim.x,    dy = blockDim.y;
    int xIndex = tx + bx*dx;
    int yIndex = ty + by*dy;
    int index = xIndex + yIndex*width;

    if (xIndex >= width)
        return ;

#define SMEM(txOffset, tyOffset)    smem[tx + txOffset + (ty+(tyOffset))*dx]

    if (yIndex < height)
        SMEM(0, radius) = in[index];
    else
        SMEM(0, radius) = in[(height-1)*width + xIndex];

    if (ty < radius) {
        if (yIndex - radius >= 0) {
            SMEM(0, 0) = in[index - radius*width];
        } else {
            SMEM(0, 0) = in[xIndex];
        }

        if (yIndex + dy < height) {
            SMEM(0, dy + radius) = in[index + dy*width];
        } else { 
            SMEM(0, dy + radius) = in[(height - 1)*width + xIndex];
        }
    }

    __syncthreads();

    if (yIndex >= height)
        return ;

    ty += radius;
    out[index] = SMEM(0, RADIUS-1);
#undef SMEM
}

__global__ void shared2D(int * in, int * out, int radius, int width, int height) {
    extern __shared__ int smem[];

    int tx = threadIdx.x,   ty = threadIdx.y;
    int bx = blockIdx.x,    by = blockIdx.y;
    int dx = blockDim.x,    dy = blockDim.y;
    int xIndex = tx + bx*dx;
    int yIndex = ty + by*dy;
    int index = xIndex + yIndex*width;

#define SMEM(txOffset, tyOffset)    smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
    
    if (xIndex < width && yIndex < height) {
        SMEM(radius, radius) = in[index];
    } else if (xIndex < width) {
        SMEM(radius, radius) = in[(height - 1)*width + xIndex];
    } else if (yIndex < height) {
        SMEM(radius, radius) = in[(yIndex + 1)*width - 1];
    } else {
        SMEM(radius, radius) = in[height*width - 1];
    }

    if (tx < radius) {
        if (xIndex - radius >= 0) {
            if (yIndex < height) {
                SMEM(0, radius) = in[index - radius];
            } else {
                SMEM(0, radius) = in[(height - 1)*width + xIndex - radius];
            }
        } else {
            if (yIndex < height) {
                SMEM(0, radius) = in[yIndex*width];
            } else {
                SMEM(0, radius) = in[(height - 1)*width];
            }
        }

        if (xIndex + dx < width) {
            if (yIndex < height) {
                SMEM(dx+radius, radius) = in[index + dx];
            } else {
                SMEM(dx+radius, radius) = in[(height - 1)*width + xIndex + dx];
            }
        } else {
            if (yIndex < height) {
                SMEM(dx+radius, radius) = in[(yIndex + 1)*width - 1];
            } else {
                SMEM(dx+radius, radius) = in[height*width - 1];
            }
        }
    }

    if (ty < radius) {
        if (yIndex - radius >= 0) {
            if (xIndex < width) {
                SMEM(radius, 0) = in[index - width*radius];
            } else {
                SMEM(radius, 0) = in[(yIndex - radius)*width];
            }
        } else {
            if (xIndex < width) {
                SMEM(radius, 0) = in[xIndex];
            } else {
                SMEM(radius, 0) = in[0];
            }
        }

        if (yIndex + dy < width) {
            if (xIndex < width) {
                SMEM(radius, dy + radius) = in[index + dy*width];
            } else {
                SMEM(radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
            }
        } else {
            if (xIndex < width) {
                SMEM(radius, dy + radius) = in[(height - 1)*width + xIndex];
            } else {
                SMEM(radius, dy + radius) = in[height*width - 1];
            }
        }
    }

    
    if (tx < radius && ty < radius) {
        // top left corner
        if (xIndex - radius >= 0) {
            if (yIndex - radius >= 0)
                SMEM(0, 0) = in[index - radius*(width + 1)];
            else
                SMEM(0, 0) = in[xIndex - radius];
        } else {
            if (yIndex - radius >= 0)
                SMEM(0, 0) = in[(yIndex - radius)*width];
            else
                SMEM(0, 0) = in[0];
        }

        // bottom left corner
        if (xIndex - radius >= 0) {
            if (yIndex + dy < height)
                SMEM(0, dy + radius) = in[index - radius + dx*width];
            else 
                SMEM(0, dy + radius) = in[xIndex - radius + (height - 1)*width];
        } else {
            if (yIndex + dy < height)
                SMEM(0, dy + radius) = in[(yIndex + dy)*width];
            else 
                SMEM(0, dy + radius) = in[(height - 1)*width];
        }


        // top right corner
        if (xIndex + dx < width) {
            if (yIndex - radius >= 0)
                SMEM(dx + radius, 0) = in[index + dx - radius*width];
            else
                SMEM(dx + radius, 0) = in[xIndex + dx];
        } else {
            if (yIndex - radius >= 0)
                SMEM(dx + radius, 0) = in[(yIndex - radius + 1)*width - 1];
            else
                SMEM(dx + radius, 0) = in[width - 1];
        }

        // bottom right corner
        if (xIndex + dx < width) {
            if (yIndex + dy < height)
                SMEM(dx + radius, dy + radius) = in[index + dy*(width + 1)];
            else
                SMEM(dx + radius, dy + radius) = in[xIndex + dx + (height - 1)*width];
        } else {
            if (yIndex + dy < height)
                SMEM(dx + radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
            else
                SMEM(dx + radius, dy + radius) = in[height*width - 1];
        }

        SMEM(0, 0) = 11;
        SMEM(dx + radius, 0) = 33;
        SMEM(0, dy + radius) = 88;
        SMEM(dx + radius, dy + radius) = 99;
    }

    if (xIndex >= width || yIndex >= height)
        return ;

    tx += radius;
    ty += radius;
    out[index] = SMEM(4, 4);
#undef SMEM
}

__host__ void init(int * list, int width, int height) {
    int ii, jj;
    for (ii = 0; ii < height; ii++) {
        for (jj = 0; jj < width; jj++) {
            list[ii*width + jj] = ii;
        }
    }
}

int main( ) {
    int * in, * d_in;
    int * out, * d_out;
    int width, height, radius;
    int sharedMemSize;
#ifdef DEBUG
    int ii, jj;
#endif

    width = WIDTH;
    height = HEIGHT;
    radius = RADIUS;

    in = (int *) malloc(width*height*sizeof(int));
    out = (int *) malloc(width*height*sizeof(int));

    init(in, width, height);

    cudaMalloc((void **) &d_in, width*height*sizeof(int));
    cudaMalloc((void **) &d_out, width*height*sizeof(int));

    cudaMemcpy(d_in, in, width*height*sizeof(int), cudaMemcpyHostToDevice);
    
    dim3 blockDim(BLOCKDIM,BLOCKDIM);
    dim3 gridDim((width + BLOCKDIM - 1)/BLOCKDIM, (height + BLOCKDIM -1)/BLOCKDIM);
    
    sharedMemSize = BLOCKDIM*(BLOCKDIM+2*RADIUS)*sizeof(int)*sizeof(int);

    shared2D<<<gridDim, blockDim, sharedMemSize>>>(d_in, d_out, radius, width, height);
    cudaMemcpy(out, d_out, width*height*sizeof(int), cudaMemcpyDeviceToHost);

#ifdef NDEBUG
    for (jj = 0; jj < height; jj++) {
        for (ii = 0; ii < width; ii++) {
            if (out[jj*width + ii] != in[jj*width + (ii + RADIUS)%WIDTH]) {
                 printf("foo");
            }
        }
    }
#endif

#ifdef DEBUG
    for (jj = 0; jj < height; jj++) {
        for (ii = 0; ii < width; ii++) {
            printf("%d ", out[jj*width + ii]);
        }
        printf("\n");
    }
#endif

    free(in);
    free(out);
    cudaFree(d_in);
    cudaFree(d_out);
    return 0;
}

	.file	"tmpxft_002c7d85_00000000-6_sharedMemory.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4initPiii
	.type	_Z4initPiii, @function
_Z4initPiii:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
.L3:
	cmpl	%edx, %ecx
	jge	.L2
	movslq	%r8d, %rax
	leaq	(%rdi,%rax,4), %r9
	xorl	%eax, %eax
.L6:
	cmpl	%eax, %esi
	jle	.L8
	movl	%ecx, (%r9,%rax,4)
	incq	%rax
	jmp	.L6
.L8:
	incl	%ecx
	addl	%esi, %r8d
	jmp	.L3
.L2:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z4initPiii, .-_Z4initPiii
	.globl	_Z31__device_stub__Z8shared1DPiS_iiPiS_ii
	.type	_Z31__device_stub__Z8shared1DPiS_iiPiS_ii, @function
_Z31__device_stub__Z8shared1DPiS_iiPiS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8shared1DPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z31__device_stub__Z8shared1DPiS_iiPiS_ii, .-_Z31__device_stub__Z8shared1DPiS_iiPiS_ii
	.globl	_Z8shared1DPiS_ii
	.type	_Z8shared1DPiS_ii, @function
_Z8shared1DPiS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z8shared1DPiS_iiPiS_ii
	.cfi_endproc
.LFE2054:
	.size	_Z8shared1DPiS_ii, .-_Z8shared1DPiS_ii
	.globl	_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
	.type	_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii, @function
_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13horizShared2DPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L14:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii, .-_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
	.globl	_Z13horizShared2DPiS_iii
	.type	_Z13horizShared2DPiS_iii, @function
_Z13horizShared2DPiS_iii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
	.cfi_endproc
.LFE2056:
	.size	_Z13horizShared2DPiS_iii, .-_Z13horizShared2DPiS_iii
	.globl	_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
	.type	_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii, @function
_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12vertShared2DPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L19:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii, .-_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
	.globl	_Z12vertShared2DPiS_iii
	.type	_Z12vertShared2DPiS_iii, @function
_Z12vertShared2DPiS_iii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
	.cfi_endproc
.LFE2058:
	.size	_Z12vertShared2DPiS_iii, .-_Z12vertShared2DPiS_iii
	.globl	_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
	.type	_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii, @function
_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8shared2DPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L24:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii, .-_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
	.globl	_Z8shared2DPiS_iii
	.type	_Z8shared2DPiS_iii, @function
_Z8shared2DPiS_iii:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
	.cfi_endproc
.LFE2060:
	.size	_Z8shared2DPiS_iii, .-_Z8shared2DPiS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"foo"
.LC1:
	.string	"%d "
.LC2:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$400, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$400, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$10, %edx
	movl	$10, %esi
	movq	%rbp, %rdi
	movq	%rax, %rbx
	call	_Z4initPiii
	movq	%rsp, %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$400, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movl	$2816, %r8d
	movabsq	$34359738376, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$8589934594, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$10, %r8d
	movl	$10, %ecx
	movl	$6, %edx
	call	_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
.L30:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movq	%rbx, %r15
	movl	$400, %edx
	xorl	%r14d, %r14d
	leaq	.LC0(%rip), %r13
	call	cudaMemcpy@PLT
.L31:
	xorl	%r12d, %r12d
.L33:
	leal	6(%r12), %eax
	movl	$10, %ecx
	cltd
	idivl	%ecx
	addl	%r14d, %edx
	movslq	%edx, %rdx
	movl	0(%rbp,%rdx,4), %eax
	cmpl	%eax, (%r15,%r12,4)
	je	.L32
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L32:
	incq	%r12
	cmpq	$10, %r12
	jne	.L33
	addl	$10, %r14d
	addq	$40, %r15
	cmpl	$100, %r14d
	jne	.L31
	xorl	%r13d, %r13d
	leaq	.LC1(%rip), %r15
.L34:
	imulq	$40, %r13, %r14
	xorl	%r12d, %r12d
	addq	%rbx, %r14
.L35:
	movl	(%r14,%r12,4), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	cmpq	$10, %r12
	jne	.L35
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$10, %r13
	jne	.L34
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z8shared2DPiS_iii"
.LC4:
	.string	"_Z12vertShared2DPiS_iii"
.LC5:
	.string	"_Z13horizShared2DPiS_iii"
.LC6:
	.string	"_Z8shared1DPiS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8shared2DPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12vertShared2DPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13horizShared2DPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8shared1DPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#define DEBUG
#ifdef DEBUG

#include <hip/hip_runtime.h>
#include    <stdio.h>
#endif
#include    <time.h>        // for rand()

#define BLOCKDIM    8

#define WIDTH       10
#define HEIGHT      10
#define RADIUS      BLOCKDIM-2

__global__ void shared1D(int * in, int * out, int radius, int n) {
    extern __shared__ int smem[];

    int tx = threadIdx.x;
    int bx = blockIdx.x;
    int dx = blockDim.x;
    int xIndex = tx + bx*dx;
    int index = xIndex;

#define SMEM(txOffset)    smem[tx + txOffset]

    if (xIndex < n)
        SMEM(radius) = in[index];
    else
        SMEM(radius) = in[n - 1];

    if (tx < radius) {
        if (xIndex - radius >= 0) {
            SMEM(0) = in[index - radius];
        } else {
            SMEM(0) = in[0];
        }

        if (xIndex + dx < n) {
            SMEM(dx + radius) = in[index + dx];
        } else {
            SMEM(dx + radius) = in[n - 1];
        }
    }

    __syncthreads();

    if (xIndex >= n)
        return ;

    tx += radius;
    out[index] = SMEM(RADIUS-1);
#undef SMEM
}

__global__ void horizShared2D(int * in, int * out, int radius, int width, int height) {
    extern __shared__ int smem[];

    int tx = threadIdx.x,   ty = threadIdx.y;
    int bx = blockIdx.x,    by = blockIdx.y;
    int dx = blockDim.x,    dy = blockDim.y;
    int xIndex = tx + bx*dx;
    int yIndex = ty + by*dy;
    int index = xIndex + yIndex*width;

    if (yIndex >= height)
        return ;

#define SMEM(txOffset, tyOffset)    smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]

    if (xIndex < width)
        SMEM(radius, 0) = in[index];
    else
        SMEM(radius, 0) = in[(yIndex+1)*width - 1];

    if (tx < radius) {
        if (xIndex - radius >= 0) {
            SMEM(0, 0) = in[index - radius];
        } else {
            SMEM(0, 0) = in[yIndex*width];
        }

        if (xIndex + dx < width) {
            SMEM(dx + radius, 0) = in[index + dx];
        } else {
            SMEM(dx + radius, 0) = in[(yIndex + 1)*width - 1];
        }
    }

    __syncthreads();

    if (xIndex >= width)
        return ;

    tx += radius;
    out[index] = SMEM(RADIUS-1, 0);
#undef SMEM
}

__global__ void vertShared2D(int * in, int * out, int radius, int width, int height) {
    extern __shared__ int smem[];

    int tx = threadIdx.x,   ty = threadIdx.y;
    int bx = blockIdx.x,    by = blockIdx.y;
    int dx = blockDim.x,    dy = blockDim.y;
    int xIndex = tx + bx*dx;
    int yIndex = ty + by*dy;
    int index = xIndex + yIndex*width;

    if (xIndex >= width)
        return ;

#define SMEM(txOffset, tyOffset)    smem[tx + txOffset + (ty+(tyOffset))*dx]

    if (yIndex < height)
        SMEM(0, radius) = in[index];
    else
        SMEM(0, radius) = in[(height-1)*width + xIndex];

    if (ty < radius) {
        if (yIndex - radius >= 0) {
            SMEM(0, 0) = in[index - radius*width];
        } else {
            SMEM(0, 0) = in[xIndex];
        }

        if (yIndex + dy < height) {
            SMEM(0, dy + radius) = in[index + dy*width];
        } else { 
            SMEM(0, dy + radius) = in[(height - 1)*width + xIndex];
        }
    }

    __syncthreads();

    if (yIndex >= height)
        return ;

    ty += radius;
    out[index] = SMEM(0, RADIUS-1);
#undef SMEM
}

__global__ void shared2D(int * in, int * out, int radius, int width, int height) {
    extern __shared__ int smem[];

    int tx = threadIdx.x,   ty = threadIdx.y;
    int bx = blockIdx.x,    by = blockIdx.y;
    int dx = blockDim.x,    dy = blockDim.y;
    int xIndex = tx + bx*dx;
    int yIndex = ty + by*dy;
    int index = xIndex + yIndex*width;

#define SMEM(txOffset, tyOffset)    smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
    
    if (xIndex < width && yIndex < height) {
        SMEM(radius, radius) = in[index];
    } else if (xIndex < width) {
        SMEM(radius, radius) = in[(height - 1)*width + xIndex];
    } else if (yIndex < height) {
        SMEM(radius, radius) = in[(yIndex + 1)*width - 1];
    } else {
        SMEM(radius, radius) = in[height*width - 1];
    }

    if (tx < radius) {
        if (xIndex - radius >= 0) {
            if (yIndex < height) {
                SMEM(0, radius) = in[index - radius];
            } else {
                SMEM(0, radius) = in[(height - 1)*width + xIndex - radius];
            }
        } else {
            if (yIndex < height) {
                SMEM(0, radius) = in[yIndex*width];
            } else {
                SMEM(0, radius) = in[(height - 1)*width];
            }
        }

        if (xIndex + dx < width) {
            if (yIndex < height) {
                SMEM(dx+radius, radius) = in[index + dx];
            } else {
                SMEM(dx+radius, radius) = in[(height - 1)*width + xIndex + dx];
            }
        } else {
            if (yIndex < height) {
                SMEM(dx+radius, radius) = in[(yIndex + 1)*width - 1];
            } else {
                SMEM(dx+radius, radius) = in[height*width - 1];
            }
        }
    }

    if (ty < radius) {
        if (yIndex - radius >= 0) {
            if (xIndex < width) {
                SMEM(radius, 0) = in[index - width*radius];
            } else {
                SMEM(radius, 0) = in[(yIndex - radius)*width];
            }
        } else {
            if (xIndex < width) {
                SMEM(radius, 0) = in[xIndex];
            } else {
                SMEM(radius, 0) = in[0];
            }
        }

        if (yIndex + dy < width) {
            if (xIndex < width) {
                SMEM(radius, dy + radius) = in[index + dy*width];
            } else {
                SMEM(radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
            }
        } else {
            if (xIndex < width) {
                SMEM(radius, dy + radius) = in[(height - 1)*width + xIndex];
            } else {
                SMEM(radius, dy + radius) = in[height*width - 1];
            }
        }
    }

    
    if (tx < radius && ty < radius) {
        // top left corner
        if (xIndex - radius >= 0) {
            if (yIndex - radius >= 0)
                SMEM(0, 0) = in[index - radius*(width + 1)];
            else
                SMEM(0, 0) = in[xIndex - radius];
        } else {
            if (yIndex - radius >= 0)
                SMEM(0, 0) = in[(yIndex - radius)*width];
            else
                SMEM(0, 0) = in[0];
        }

        // bottom left corner
        if (xIndex - radius >= 0) {
            if (yIndex + dy < height)
                SMEM(0, dy + radius) = in[index - radius + dx*width];
            else 
                SMEM(0, dy + radius) = in[xIndex - radius + (height - 1)*width];
        } else {
            if (yIndex + dy < height)
                SMEM(0, dy + radius) = in[(yIndex + dy)*width];
            else 
                SMEM(0, dy + radius) = in[(height - 1)*width];
        }


        // top right corner
        if (xIndex + dx < width) {
            if (yIndex - radius >= 0)
                SMEM(dx + radius, 0) = in[index + dx - radius*width];
            else
                SMEM(dx + radius, 0) = in[xIndex + dx];
        } else {
            if (yIndex - radius >= 0)
                SMEM(dx + radius, 0) = in[(yIndex - radius + 1)*width - 1];
            else
                SMEM(dx + radius, 0) = in[width - 1];
        }

        // bottom right corner
        if (xIndex + dx < width) {
            if (yIndex + dy < height)
                SMEM(dx + radius, dy + radius) = in[index + dy*(width + 1)];
            else
                SMEM(dx + radius, dy + radius) = in[xIndex + dx + (height - 1)*width];
        } else {
            if (yIndex + dy < height)
                SMEM(dx + radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
            else
                SMEM(dx + radius, dy + radius) = in[height*width - 1];
        }

        SMEM(0, 0) = 11;
        SMEM(dx + radius, 0) = 33;
        SMEM(0, dy + radius) = 88;
        SMEM(dx + radius, dy + radius) = 99;
    }

    if (xIndex >= width || yIndex >= height)
        return ;

    tx += radius;
    ty += radius;
    out[index] = SMEM(4, 4);
#undef SMEM
}

__host__ void init(int * list, int width, int height) {
    int ii, jj;
    for (ii = 0; ii < height; ii++) {
        for (jj = 0; jj < width; jj++) {
            list[ii*width + jj] = ii;
        }
    }
}

int main( ) {
    int * in, * d_in;
    int * out, * d_out;
    int width, height, radius;
    int sharedMemSize;
#ifdef DEBUG
    int ii, jj;
#endif

    width = WIDTH;
    height = HEIGHT;
    radius = RADIUS;

    in = (int *) malloc(width*height*sizeof(int));
    out = (int *) malloc(width*height*sizeof(int));

    init(in, width, height);

    hipMalloc((void **) &d_in, width*height*sizeof(int));
    hipMalloc((void **) &d_out, width*height*sizeof(int));

    hipMemcpy(d_in, in, width*height*sizeof(int), hipMemcpyHostToDevice);
    
    dim3 blockDim(BLOCKDIM,BLOCKDIM);
    dim3 gridDim((width + BLOCKDIM - 1)/BLOCKDIM, (height + BLOCKDIM -1)/BLOCKDIM);
    
    sharedMemSize = BLOCKDIM*(BLOCKDIM+2*RADIUS)*sizeof(int)*sizeof(int);

    shared2D<<<gridDim, blockDim, sharedMemSize>>>(d_in, d_out, radius, width, height);
    hipMemcpy(out, d_out, width*height*sizeof(int), hipMemcpyDeviceToHost);

#ifdef NDEBUG
    for (jj = 0; jj < height; jj++) {
        for (ii = 0; ii < width; ii++) {
            if (out[jj*width + ii] != in[jj*width + (ii + RADIUS)%WIDTH]) {
                 printf("foo");
            }
        }
    }
#endif

#ifdef DEBUG
    for (jj = 0; jj < height; jj++) {
        for (ii = 0; ii < width; ii++) {
            printf("%d ", out[jj*width + ii]);
        }
        printf("\n");
    }
#endif

    free(in);
    free(out);
    hipFree(d_in);
    hipFree(d_out);
    return 0;
}

	.text
	.file	"sharedMemory.hip"
	.globl	_Z23__device_stub__shared1DPiS_ii # -- Begin function _Z23__device_stub__shared1DPiS_ii
	.type	_Z23__device_stub__shared1DPiS_ii,@function
_Z23__device_stub__shared1DPiS_ii:      # @_Z23__device_stub__shared1DPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8shared1DPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__shared1DPiS_ii, .Lfunc_end0-_Z23__device_stub__shared1DPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__horizShared2DPiS_iii # -- Begin function _Z28__device_stub__horizShared2DPiS_iii
	.type	_Z28__device_stub__horizShared2DPiS_iii,@function
_Z28__device_stub__horizShared2DPiS_iii: # @_Z28__device_stub__horizShared2DPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13horizShared2DPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__horizShared2DPiS_iii, .Lfunc_end1-_Z28__device_stub__horizShared2DPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__vertShared2DPiS_iii # -- Begin function _Z27__device_stub__vertShared2DPiS_iii
	.type	_Z27__device_stub__vertShared2DPiS_iii,@function
_Z27__device_stub__vertShared2DPiS_iii: # @_Z27__device_stub__vertShared2DPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12vertShared2DPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z27__device_stub__vertShared2DPiS_iii, .Lfunc_end2-_Z27__device_stub__vertShared2DPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__shared2DPiS_iii # -- Begin function _Z23__device_stub__shared2DPiS_iii
	.type	_Z23__device_stub__shared2DPiS_iii,@function
_Z23__device_stub__shared2DPiS_iii:     # @_Z23__device_stub__shared2DPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8shared2DPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__shared2DPiS_iii, .Lfunc_end3-_Z23__device_stub__shared2DPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z4initPiii                     # -- Begin function _Z4initPiii
	.type	_Z4initPiii,@function
_Z4initPiii:                            # @_Z4initPiii
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB4_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%edx, %eax
	movl	%esi, %ecx
	xorl	%edx, %edx
	xorl	%r8d, %r8d
.LBB4_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_4 Depth 2
	testl	%esi, %esi
	jle	.LBB4_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB4_2 Depth=1
	movl	%edx, %r9d
	leaq	(%rdi,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB4_4:                                #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r8d, (%r9,%r10,4)
	incq	%r10
	cmpq	%r10, %rcx
	jne	.LBB4_4
.LBB4_5:                                # %._crit_edge
                                        #   in Loop: Header=BB4_2 Depth=1
	incq	%r8
	addl	%esi, %edx
	cmpq	%rax, %r8
	jne	.LBB4_2
.LBB4_6:                                # %._crit_edge14
	retq
.Lfunc_end4:
	.size	_Z4initPiii, .Lfunc_end4-_Z4initPiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %rbx
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %r14
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB5_1:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_2 Depth 2
	xorl	%edx, %edx
.LBB5_2:                                #   Parent Loop BB5_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%eax, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$10, %rdx
	jne	.LBB5_2
# %bb.3:                                # %._crit_edge.i
                                        #   in Loop: Header=BB5_1 Depth=1
	incq	%rax
	addq	$40, %rcx
	cmpq	$10, %rax
	jne	.LBB5_1
# %bb.4:                                # %_Z4initPiii.exit
	leaq	16(%rsp), %r15
	movl	$400, %esi                      # imm = 0x190
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$2816, %r8d                     # imm = 0xB00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$6, %edx
	movl	$10, %ecx
	movl	$10, %r8d
	callq	_Z23__device_stub__shared2DPiS_iii
.LBB5_6:
	movq	8(%rsp), %rsi
	movl	$400, %edx                      # imm = 0x190
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
.LBB5_7:                                # %.preheader60
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_8 Depth 2
	movq	%r15, %r13
	xorl	%ebp, %ebp
.LBB5_8:                                #   Parent Loop BB5_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r14,%r13,4), %eax
	leal	-4(%r13), %ecx
	leal	6(%r13), %edx
	cmpq	$4, %rbp
	cmovael	%ecx, %edx
	cmpl	(%rbx,%rdx,4), %eax
	je	.LBB5_10
# %bb.9:                                #   in Loop: Header=BB5_8 Depth=2
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
.LBB5_10:                               #   in Loop: Header=BB5_8 Depth=2
	incq	%rbp
	incq	%r13
	cmpq	$10, %rbp
	jne	.LBB5_8
# %bb.11:                               #   in Loop: Header=BB5_7 Depth=1
	incq	%r12
	addq	$10, %r15
	cmpq	$10, %r12
	jne	.LBB5_7
# %bb.12:                               # %.preheader.preheader
	movq	%r14, %r15
	xorl	%r12d, %r12d
.LBB5_13:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_14 Depth 2
	xorl	%r13d, %r13d
.LBB5_14:                               #   Parent Loop BB5_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r15,%r13,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r13
	cmpq	$10, %r13
	jne	.LBB5_14
# %bb.15:                               #   in Loop: Header=BB5_13 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r12
	addq	$40, %r15
	cmpq	$10, %r12
	jne	.LBB5_13
# %bb.16:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8shared1DPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13horizShared2DPiS_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12vertShared2DPiS_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8shared2DPiS_iii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8shared1DPiS_ii,@object       # @_Z8shared1DPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z8shared1DPiS_ii
	.p2align	3, 0x0
_Z8shared1DPiS_ii:
	.quad	_Z23__device_stub__shared1DPiS_ii
	.size	_Z8shared1DPiS_ii, 8

	.type	_Z13horizShared2DPiS_iii,@object # @_Z13horizShared2DPiS_iii
	.globl	_Z13horizShared2DPiS_iii
	.p2align	3, 0x0
_Z13horizShared2DPiS_iii:
	.quad	_Z28__device_stub__horizShared2DPiS_iii
	.size	_Z13horizShared2DPiS_iii, 8

	.type	_Z12vertShared2DPiS_iii,@object # @_Z12vertShared2DPiS_iii
	.globl	_Z12vertShared2DPiS_iii
	.p2align	3, 0x0
_Z12vertShared2DPiS_iii:
	.quad	_Z27__device_stub__vertShared2DPiS_iii
	.size	_Z12vertShared2DPiS_iii, 8

	.type	_Z8shared2DPiS_iii,@object      # @_Z8shared2DPiS_iii
	.globl	_Z8shared2DPiS_iii
	.p2align	3, 0x0
_Z8shared2DPiS_iii:
	.quad	_Z23__device_stub__shared2DPiS_iii
	.size	_Z8shared2DPiS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"foo"
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8shared1DPiS_ii"
	.size	.L__unnamed_1, 18

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13horizShared2DPiS_iii"
	.size	.L__unnamed_2, 25

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z12vertShared2DPiS_iii"
	.size	.L__unnamed_3, 24

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z8shared2DPiS_iii"
	.size	.L__unnamed_4, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__shared1DPiS_ii
	.addrsig_sym _Z28__device_stub__horizShared2DPiS_iii
	.addrsig_sym _Z27__device_stub__vertShared2DPiS_iii
	.addrsig_sym _Z23__device_stub__shared2DPiS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8shared1DPiS_ii
	.addrsig_sym _Z13horizShared2DPiS_iii
	.addrsig_sym _Z12vertShared2DPiS_iii
	.addrsig_sym _Z8shared2DPiS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8shared1DPiS_ii       ; -- Begin function _Z8shared1DPiS_ii
	.globl	_Z8shared1DPiS_ii
	.p2align	8
	.type	_Z8shared1DPiS_ii,@function
_Z8shared1DPiS_ii:                      ; @_Z8shared1DPiS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s8, 0xffff
	s_ashr_i32 s9, s3, 31
	v_mad_u64_u32 v[3:4], null, s15, s1, v[0:1]
	s_mov_b32 s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
	s_add_u32 s0, s4, s8
	s_addc_u32 s9, s5, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_u32 s8, s0, -4
	s_addc_u32 s9, s9, -1
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	v_add_nc_u32_e32 v4, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v4, v4, 2, 0
	v_add_co_u32 v5, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v3
	v_cndmask_b32_e32 v8, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v7, s8, v5, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v7
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %.sink.split
	v_subrev_nc_u32_e32 v7, s2, v3
	v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v3, s1, v3
	s_lshl_b32 s2, s1, 2
	v_lshl_add_u32 v0, v0, 2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_max_i32_e32 v7, 0, v7
	v_add_co_u32 v10, s0, v5, s2
	v_add_co_ci_u32_e64 v9, s0, 0, v6, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[7:8]
	v_cmp_gt_i32_e64 s0, s3, v3
	v_cndmask_b32_e64 v7, s9, v9, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, s4, v5
	v_add_co_ci_u32_e64 v9, s1, s5, v6, s1
	v_cndmask_b32_e64 v6, s8, v10, s0
	global_load_b32 v3, v[8:9], off
	global_load_b32 v5, v[6:7], off
	v_add_nc_u32_e32 v6, s2, v4
	s_waitcnt vmcnt(1)
	ds_store_b32 v0, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	ds_load_b32 v3, v4 offset:20
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8shared1DPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8shared1DPiS_ii, .Lfunc_end0-_Z8shared1DPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13horizShared2DPiS_iii ; -- Begin function _Z13horizShared2DPiS_iii
	.globl	_Z13horizShared2DPiS_iii
	.p2align	8
	.type	_Z13horizShared2DPiS_iii,@function
_Z13horizShared2DPiS_iii:               ; @_Z13horizShared2DPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[8:11], s[0:1], 0x10
	v_bfe_u32 v5, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[5:6]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB1_13
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s1, s2, 0xffff
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s14, s1, v[2:3]
	v_mul_lo_u32 v4, v1, s9
	v_cmp_gt_i32_e32 vcc_lo, s9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v4, v3
	v_cmpx_le_i32_e64 s9, v3
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_mov_b32 s0, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s9, v1, s[0:1]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, s0, s4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	v_add_co_u32 v6, s0, v1, -4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, -1, v7, s0
.LBB1_3:                                ; %Flow124
	s_or_saveexec_b32 s2, s2
	v_ashrrev_i32_e32 v1, 31, v0
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s0, s4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
.LBB1_5:
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v7, v[6:7], off
	s_lshl_b32 s0, s8, 1
	s_mov_b32 s2, exec_lo
	s_add_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, s0, v5
	v_add3_u32 v5, v2, s8, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v5, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v7
	v_cmpx_gt_i32_e64 s8, v2
	s_cbranch_execz .LBB1_11
; %bb.6:
	v_subrev_nc_u32_e32 v7, s8, v0
	v_cmp_gt_i32_e64 s0, s8, v3
	v_add_nc_u32_e32 v2, v6, v2
	v_add_nc_u32_e32 v3, s1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v4, s0
	v_lshl_add_u32 v2, v2, 2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s4, v7
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	v_cmp_le_i32_e64 s0, s9, v3
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v7
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
; %bb.7:
	v_add_nc_u32_e32 v2, s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s4, v2
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, v2, -4
	v_add_co_ci_u32_e64 v3, s0, -1, v3, s0
; %bb.8:                                ; %Flow122
	s_and_not1_saveexec_b32 s3, s3
; %bb.9:
	v_add_nc_u32_e32 v2, s1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s4, v2
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
; %bb.10:                               ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v2, v[2:3], off
	v_lshl_add_u32 v3, s1, 2, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v2
.LBB1_11:                               ; %Flow123
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_13
; %bb.12:
	ds_load_b32 v2, v5 offset:20
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13horizShared2DPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13horizShared2DPiS_iii, .Lfunc_end1-_Z13horizShared2DPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 692
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12vertShared2DPiS_iii ; -- Begin function _Z12vertShared2DPiS_iii
	.globl	_Z12vertShared2DPiS_iii
	.p2align	8
	.type	_Z12vertShared2DPiS_iii,@function
_Z12vertShared2DPiS_iii:                ; @_Z12vertShared2DPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[8:11], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, s14, s3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v5
	v_cmpx_gt_i32_e64 s9, v5
	s_cbranch_execz .LBB2_9
; %bb.1:
	v_bfe_u32 v3, v0, 10, 10
	s_lshr_b32 s11, s2, 16
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s15, s11, v[3:4]
	v_mad_u64_u32 v[0:1], null, v6, s9, v[5:6]
	v_cmp_gt_i32_e32 vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v0
	v_cmpx_le_i32_e64 s10, v6
; %bb.2:
	s_add_i32 s2, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[7:8], null, s2, s9, v[5:6]
; %bb.3:
	s_or_b32 exec_lo, exec_lo, s4
	s_load_b128 s[4:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	s_mov_b32 s1, exec_lo
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s4, v7
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	global_load_b32 v10, v[7:8], off
	v_add_nc_u32_e32 v7, s8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v7, s3, v[2:3]
	v_lshl_add_u32 v1, v8, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v10
	v_cmpx_gt_i32_e64 s8, v3
	s_cbranch_execz .LBB2_7
; %bb.4:
	s_mov_b32 s2, exec_lo
	v_cmpx_le_i32_e64 s8, v6
; %bb.5:
	s_mul_i32 s0, s9, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_subrev_nc_u32_e32 v4, s0, v0
; %bb.6:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v6, s11, v6
	v_dual_mov_b32 v8, s11 :: v_dual_add_nc_u32 v7, s11, v7
	s_add_i32 s2, s10, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s10, v6
	v_cndmask_b32_e64 v6, s2, v8, s0
	v_cndmask_b32_e64 v5, v5, v0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v6, s9, v[5:6]
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v4, s0, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, s4, v8
	v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
	s_clause 0x1
	global_load_b32 v6, v[4:5], off
	global_load_b32 v8, v[8:9], off
	v_mad_u64_u32 v[4:5], null, v7, s3, v[2:3]
	v_mad_u32_u24 v2, v3, s3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v2, v2, 2, 0
	v_lshl_add_u32 v3, v4, 2, 0
	s_waitcnt vmcnt(1)
	ds_store_b32 v2, v6
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v8
.LBB2_7:                                ; %Flow117
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_9
; %bb.8:
	v_mad_u64_u32 v[2:3], null, s3, 20, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	ds_load_b32 v2, v2
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB2_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12vertShared2DPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z12vertShared2DPiS_iii, .Lfunc_end2-_Z12vertShared2DPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8shared2DPiS_iii      ; -- Begin function _Z8shared2DPiS_iii
	.globl	_Z8shared2DPiS_iii
	.p2align	8
	.type	_Z8shared2DPiS_iii,@function
_Z8shared2DPiS_iii:                     ; @_Z8shared2DPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v7, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
                                        ; implicit-def: $vgpr9_vgpr10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s16, s2, 16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s15, s16, v[7:8]
	s_and_b32 s15, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, s14, s15, v[2:3]
	v_mul_lo_u32 v8, v4, s9
	v_cmp_gt_i32_e64 s0, s10, v4
	v_cmp_le_i32_e64 s2, s10, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s1, s9, v5
	v_cmp_le_i32_e32 vcc_lo, s9, v5
	v_add_nc_u32_e32 v0, v8, v5
	s_and_b32 s11, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s11, -1
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB3_10
; %bb.1:
                                        ; implicit-def: $vgpr9_vgpr10
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s0
	s_cbranch_execz .LBB3_7
; %bb.2:
                                        ; implicit-def: $sgpr12_sgpr13
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
; %bb.3:
	s_mul_i32 s12, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s12, 31
	s_lshl_b64 s[12:13], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
	s_add_u32 s12, s12, -4
	s_addc_u32 s13, s13, -1
; %bb.4:                                ; %Flow626
	s_or_saveexec_b32 s17, s0
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
	s_xor_b32 exec_lo, exec_lo, s17
; %bb.5:
	s_mov_b32 s0, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, s9, v4, s[0:1]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v1, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s0, s5, v10, s0
	v_add_co_u32 v9, s0, v1, -4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, -1, v3, s0
; %bb.6:                                ; %Flow627
	s_or_b32 exec_lo, exec_lo, s17
.LBB3_7:                                ; %Flow628
	s_and_not1_saveexec_b32 s12, s14
; %bb.8:
	s_add_i32 s0, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, s0, s9, v[5:6]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
; %bb.9:                                ; %Flow629
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_10:                               ; %Flow630
	s_or_saveexec_b32 s3, s3
	v_ashrrev_i32_e32 v1, 31, v0
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.11:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[0:1]
	v_add_co_u32 v9, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
; %bb.12:
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v9, v[9:10], off
	v_add_nc_u32_e32 v11, s8, v7
	s_lshl_b32 s14, s8, 1
	v_add_nc_u32_e32 v3, s8, v2
	s_add_i32 s14, s14, s15
	v_cmp_le_i32_e64 s0, s8, v2
	v_mul_lo_u32 v6, s14, v11
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v3, v6
	v_lshl_add_u32 v10, v10, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v9
	v_cmpx_gt_i32_e64 s8, v2
	s_cbranch_execz .LBB3_36
; %bb.13:
	v_cmp_le_i32_e64 s3, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s3
	s_xor_b32 s3, exec_lo, s12
	s_cbranch_execz .LBB3_19
; %bb.14:
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s12, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
; %bb.15:
	s_add_i32 s13, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s13, s13, s9
	s_sub_i32 s13, s13, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v8, s13, v5
; %bb.16:                               ; %Flow620
	s_and_not1_saveexec_b32 s12, s12
; %bb.17:
	v_subrev_nc_u32_e32 v8, s8, v0
; %bb.18:                               ; %Flow621
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_19:                               ; %Flow623
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB3_23
; %bb.20:
	s_and_saveexec_b32 s12, s2
; %bb.21:
	s_add_i32 s13, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s13, s13, s9
	v_mov_b32_e32 v8, s13
; %bb.22:                               ; %Flow622
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_23:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_ashrrev_i32_e32 v9, 31, v8
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s3, s4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v9, s3, s5, v9, s3
	global_load_b32 v8, v[8:9], off
	v_add_nc_u32_e32 v9, v6, v2
	v_add_nc_u32_e32 v6, s15, v5
	v_lshl_add_u32 v9, v9, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v8
                                        ; implicit-def: $vgpr8_vgpr9
	v_cmpx_le_i32_e64 s9, v6
	s_xor_b32 s18, exec_lo, s12
	s_cbranch_execz .LBB3_29
; %bb.24:
                                        ; implicit-def: $sgpr12_sgpr13
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
; %bb.25:
	s_mul_i32 s12, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s12, 31
	s_lshl_b64 s[12:13], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
	s_add_u32 s12, s12, -4
	s_addc_u32 s13, s13, -1
; %bb.26:                               ; %Flow614
	s_or_saveexec_b32 s19, s3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	s_xor_b32 exec_lo, exec_lo, s19
; %bb.27:
	s_mov_b32 s12, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s9, v4, s[12:13]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v6, s3, s4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v9, s3, s5, v9, s3
	v_add_co_u32 v8, s3, v6, -4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s3, -1, v9, s3
; %bb.28:                               ; %Flow615
	s_or_b32 exec_lo, exec_lo, s19
                                        ; implicit-def: $vgpr6
.LBB3_29:                               ; %Flow619
	s_and_not1_saveexec_b32 s3, s18
	s_cbranch_execz .LBB3_35
; %bb.30:
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s12, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
; %bb.31:
	s_add_i32 s2, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s2, s9, v[6:7]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s2, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
; %bb.32:                               ; %Flow616
	s_and_not1_saveexec_b32 s12, s12
; %bb.33:
	v_add_nc_u32_e32 v8, s15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s2, s4, v8
	v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
; %bb.34:                               ; %Flow617
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_35:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v6, v[8:9], off
	v_lshl_add_u32 v8, s15, 2, v10
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v6
.LBB3_36:                               ; %Flow625
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_le_i32_e64 s2, s8, v7
	v_subrev_nc_u32_e32 v12, s8, v4
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_i32_e64 s8, v7
	s_cbranch_execz .LBB3_60
; %bb.37:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s3, 0, v12
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s12, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s12
	s_cbranch_execz .LBB3_41
; %bb.38:
	v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
	s_and_saveexec_b32 s12, s1
; %bb.39:
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	v_add_co_u32 v8, s1, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
; %bb.40:                               ; %Flow606
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_41:                               ; %Flow610
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB3_47
; %bb.42:
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s1
; %bb.43:
	v_mul_lo_u32 v8, v12, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, s4, v8
	v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
; %bb.44:                               ; %Flow607
	s_and_not1_saveexec_b32 s12, s12
; %bb.45:
	s_mul_i32 s1, s9, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v8, s1, v0
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s1, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
; %bb.46:                               ; %Flow608
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_47:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v10, v[8:9], off
	v_mad_u64_u32 v[8:9], null, s14, v7, v[3:4]
	v_add_nc_u32_e32 v6, s16, v4
	s_mov_b32 s3, exec_lo
	v_lshl_add_u32 v8, v8, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v10
                                        ; implicit-def: $vgpr8_vgpr9
	v_cmpx_le_i32_e64 s9, v6
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB3_53
; %bb.48:
                                        ; implicit-def: $sgpr12_sgpr13
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
; %bb.49:
	s_mul_i32 s12, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s12, 31
	s_lshl_b64 s[12:13], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
	s_add_u32 s12, s12, -4
	s_addc_u32 s13, s13, -1
; %bb.50:                               ; %Flow600
	s_or_saveexec_b32 s18, s1
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	s_xor_b32 exec_lo, exec_lo, s18
; %bb.51:
	s_add_i32 s1, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s1, s9, v[5:6]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s1, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
; %bb.52:                               ; %Flow601
	s_or_b32 exec_lo, exec_lo, s18
                                        ; implicit-def: $vgpr6
.LBB3_53:                               ; %Flow605
	s_and_not1_saveexec_b32 s1, s3
	s_cbranch_execz .LBB3_59
; %bb.54:
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
; %bb.55:
	s_mov_b32 s12, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s9, v6, s[12:13]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v6, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, v6, -4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, -1, v9, vcc_lo
; %bb.56:                               ; %Flow602
	s_and_not1_saveexec_b32 s3, s3
; %bb.57:
	v_mad_u64_u32 v[8:9], null, s16, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
; %bb.58:                               ; %Flow603
	s_or_b32 exec_lo, exec_lo, s3
.LBB3_59:                               ; %.sink.split539
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v6, v[8:9], off
	v_add_nc_u32_e32 v10, s16, v11
	v_mad_u64_u32 v[8:9], null, v10, s14, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v8, v8, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v6
.LBB3_60:                               ; %Flow612
	s_or_b32 exec_lo, exec_lo, s17
	s_or_b32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB3_108
; %bb.61:
	v_subrev_nc_u32_e32 v8, s8, v5
                                        ; implicit-def: $vgpr9_vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, 0, v8
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB3_65
; %bb.62:
	v_dual_mov_b32 v10, s5 :: v_dual_mov_b32 v9, s4
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 -1, v12
; %bb.63:
	v_mul_lo_u32 v9, v12, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
; %bb.64:                               ; %Flow595
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_65:                               ; %Flow598
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB3_71
; %bb.66:
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr9_vgpr10
	v_cmpx_le_i32_e64 s8, v4
	s_xor_b32 s2, exec_lo, s2
; %bb.67:
	s_not_b32 s3, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, s3, s8, v[0:1]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
; %bb.68:                               ; %Flow596
	s_and_not1_saveexec_b32 s2, s2
; %bb.69:
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[8:9]
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
; %bb.70:                               ; %Flow597
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_71:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v6, v[9:10], off
	v_mul_lo_u32 v14, s14, v7
	v_add_nc_u32_e32 v10, s16, v4
	v_cmp_le_i32_e32 vcc_lo, s10, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v14, v2
	v_lshl_add_u32 v9, v7, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v6
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB3_77
; %bb.72:
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_74
; %bb.73:
	s_add_i32 s2, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s2, s9
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_load_b32 s2, s[2:3], 0x0
	v_add_nc_u32_e32 v8, s16, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, s14, v[2:3]
	v_lshl_add_u32 v6, v6, 2, 0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v7, s2
	ds_store_b32 v6, v7
.LBB3_74:                               ; %Flow590
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB3_76
; %bb.75:
	v_mul_lo_u32 v6, v10, s9
	v_add_nc_u32_e32 v13, s16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s4, v6
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	global_load_b32 v8, v[6:7], off
	v_mad_u64_u32 v[6:7], null, v13, s14, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v6, v6, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v8
.LBB3_76:                               ; %Flow591
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr8
.LBB3_77:                               ; %Flow594
	s_or_saveexec_b32 s1, s1
	v_add_nc_u32_e32 v13, s16, v11
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB3_83
; %bb.78:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v13, s14, v[2:3]
	v_lshl_add_u32 v6, v6, 2, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB3_80
; %bb.79:
	s_add_i32 s0, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, s0, s9, v[8:9]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[15:16]
	v_add_co_u32 v7, s0, s4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
                                        ; implicit-def: $vgpr6
.LBB3_80:                               ; %Flow592
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_82
; %bb.81:
	s_mul_i32 s0, s15, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s0, s8
	v_add_nc_u32_e32 v7, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s4, v7
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
.LBB3_82:                               ; %Flow593
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_83:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v6, s15, v5
                                        ; implicit-def: $vgpr7_vgpr8
	v_cmp_le_i32_e64 s0, s9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s13, exec_lo, s1
	s_cbranch_execz .LBB3_89
; %bb.84:
	v_cmp_gt_i32_e64 s1, 0, v12
                                        ; implicit-def: $sgpr2_sgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s17, s1
	s_xor_b32 s1, exec_lo, s17
; %bb.85:
	s_ashr_i32 s3, s9, 31
	s_mov_b32 s2, s9
                                        ; implicit-def: $vgpr12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_add_u32 s2, s2, -4
	s_addc_u32 s3, s3, -1
; %bb.86:                               ; %Flow585
	s_or_saveexec_b32 s17, s1
	v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v7, s2
	s_xor_b32 exec_lo, exec_lo, s17
; %bb.87:
	s_mov_b32 s2, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s9, v12, s[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, s1, s4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v5, s1, s5, v5, s1
	v_add_co_u32 v7, s1, v4, -4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s1, -1, v5, s1
; %bb.88:                               ; %Flow586
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr4_vgpr5
.LBB3_89:                               ; %Flow589
	s_and_not1_saveexec_b32 s2, s13
	s_cbranch_execz .LBB3_95
; %bb.90:
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	v_cmpx_le_i32_e64 s8, v4
	s_xor_b32 s3, exec_lo, s3
; %bb.91:
	v_add_nc_u32_e32 v4, s15, v0
	s_mul_i32 s1, s9, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_subrev_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s1, s4, v4
	v_add_co_ci_u32_e64 v8, s1, s5, v5, s1
; %bb.92:                               ; %Flow587
	s_and_not1_saveexec_b32 s3, s3
; %bb.93:
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_co_u32 v7, s1, s4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s1, s5, v5, s1
; %bb.94:                               ; %Flow588
	s_or_b32 exec_lo, exec_lo, s3
.LBB3_95:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v5, v[7:8], off
	v_add_nc_u32_e32 v8, s15, v3
                                        ; implicit-def: $vgpr7
	v_add_nc_u32_e32 v4, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v4, v4, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB3_101
; %bb.96:
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_98
; %bb.97:
	s_mul_i32 s2, s10, s9
	v_mul_lo_u32 v7, v13, s14
	s_ashr_i32 s3, s2, 31
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_add_u32 s2, s2, -4
	s_addc_u32 s3, s3, -1
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v8, s2 :: v_dual_add_nc_u32 v5, v8, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v6, v5, 2, 0
	ds_store_b32 v6, v8
                                        ; implicit-def: $vgpr8
.LBB3_98:                               ; %Flow
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB3_100
; %bb.99:
	s_mov_b32 s0, s9
	v_mul_lo_u32 v7, v13, s14
	v_mad_u64_u32 v[5:6], null, s9, v10, s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s4, v5
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	global_load_b32 v6, v[5:6], off offset:-4
	v_add_nc_u32_e32 v5, v8, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v8, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v6
.LBB3_100:                              ; %Flow579
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr6
.LBB3_101:                              ; %Flow583
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_107
; %bb.102:
	v_mul_lo_u32 v7, v13, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v8, v7
	v_lshl_add_u32 v8, v5, 2, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB3_104
; %bb.103:
	s_add_i32 s2, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, s2, s9, v[6:7]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	global_load_b32 v6, v[12:13], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v6
                                        ; implicit-def: $vgpr8
.LBB3_104:                              ; %Flow580
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB3_106
; %bb.105:
	s_add_i32 s2, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, s2, s16, v[0:1]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	global_load_b32 v6, v[12:13], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v6
.LBB3_106:                              ; %Flow581
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_107:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v7, 33 :: v_dual_add_nc_u32 v2, v7, v2
	v_mov_b32_e32 v6, 11
	v_mov_b32_e32 v8, 0x58
	v_lshl_add_u32 v5, v5, 2, 0
	v_lshl_add_u32 v2, v2, 2, 0
	v_mov_b32_e32 v10, 0x63
	ds_store_b32 v9, v6
	ds_store_b32 v4, v7
	ds_store_b32 v2, v8
	ds_store_b32 v5, v10
.LBB3_108:                              ; %Flow599
	s_or_b32 exec_lo, exec_lo, s12
	s_and_saveexec_b32 s0, s11
	s_cbranch_execz .LBB3_110
; %bb.109:
	v_add_nc_u32_e32 v2, 4, v11
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s14, v2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_lshl_add_u32 v2, v4, 2, 0
	ds_load_b32 v2, v2 offset:16
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB3_110:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8shared2DPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z8shared2DPiS_iii, .Lfunc_end3-_Z8shared2DPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3240
; NumSgprs: 22
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8shared1DPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8shared1DPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13horizShared2DPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13horizShared2DPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12vertShared2DPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12vertShared2DPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8shared2DPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z8shared2DPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
