#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <string.h>


#define TIMER_CREATE(t)             \
        cudaEvent_t t##_start, t##_end;     \
        cudaEventCreate(&t##_start);        \
        cudaEventCreate(&t##_end);


#define TIMER_START(t)                \
        cudaEventRecord(t##_start);         \
        cudaEventSynchronize(t##_start);    \


#define TIMER_END(t)                             \
        cudaEventRecord(t##_end);                      \
        cudaEventSynchronize(t##_end);                 \
        cudaEventElapsedTime(&t, t##_start, t##_end);  \
        cudaEventDestroy(t##_start);                   \
        cudaEventDestroy(t##_end);


//Function to check for errors
inline cudaError_t checkCuda(cudaError_t result) 
{
	#if defined(DEBUG) || defined(_DEBUG)
		if (result != cudaSuccess) {
			fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
			exit(-1);
		}
	#endif
	return result;
}

//Number of vertices
#define vertices 5000 

//Number of edges per vertex
#define Edge_per_node 4999

//Used to define weights on each edge.
#define Maximum_weight 5

//Value for infinity
#define infinity 10000000

//Kernel call to inititialize all node weights to infinity except for the source node. We mark the source node as settled after this point
__global__ void Initializing(int *node_weight_array, int *mask_array, int Source) // CUDA kernel
{
	int id = blockIdx.x*blockDim.x+threadIdx.x; // Get global thread ID
	if(id<vertices)
	{
		if(id==Source)
		{
			node_weight_array[id]=0;
			mask_array[id]=1;
		}
		else
		{
			node_weight_array[id]=infinity;
			mask_array[id]=0;
		}
	}
}


//Kernel Call to choose a a node which is relaxed and settled and to relax the outgoing edges of each settled node.
__global__ void Minimum(int *mask_array,int *vertex_array,int *vertex_array_copy, int *node_weight_array, int *edge_array, int *edge_weight_array, int *min)
{
	int id = blockIdx.x*blockDim.x+threadIdx.x; // Get global thread ID
	//Iterative variables
	int i,n,t;	
	if(id<vertices)
	{
		if(mask_array[id]==1)
		{
			t=vertex_array_copy[id];	
			for(i=t*Edge_per_node;i<t*Edge_per_node+Edge_per_node;i++)
			{
				n=edge_array[i];
				if(mask_array[n]!=1)
				{
					atomicMin(&node_weight_array[n],node_weight_array[id]+edge_weight_array[i]);
					atomicMin(&min[0],node_weight_array[n]);
					vertex_array_copy[id]=n;
					break;
				}
			}
		}
	}		
}

//Kernel call to mark all the settled nodes
__global__ void Relax(int *mask_array,int *node_weight_array,int *min)
{
	int id = blockIdx.x*blockDim.x+threadIdx.x; // Get global thread ID
	if(id<vertices)
	{
		if(mask_array[id]!=1 && node_weight_array[id]==min[0])
		{
			mask_array[id]=1;
		}
	}	
}

int main( int argc, char* argv[] )
{

	//Size of the Vertex array
	size_t vertex_array_size = vertices*sizeof(int);
	
	//Size of the edge array and edge_weight array
	size_t edge_array_size = vertices*Edge_per_node*sizeof(int);

	//Intializing the vertex array
	int *vertex_array = (int*)malloc(vertex_array_size); 

	//Intializing the vertex array
	int *vertex_array_copy = (int*)malloc(vertex_array_size); 

	//Initializing a copy of the vertex array
	int *vertex_copy = (int*)malloc(vertex_array_size); 

	//Intializing the edge array
	int *edge_array=(int*)malloc(edge_array_size);

	//Initializing edge_weight_array which stores the weights of each edge
	int *edge_weight_array = (int*)malloc(edge_array_size);

	//Initializing Node weight array which stores the value for the current weight to reach the node
	int *node_weight_array = (int*)malloc(vertex_array_size);

	//Array to mark if a node is settled or not
	int *mask_array = (int*)malloc(vertex_array_size);

	//Iterative operator
	int i,j,k;  

	printf("Populating Vertex Array....\n");

	//Setting node number in vertex_array
	for(i=0;i<vertices;i++)
	{
		vertex_array[i]=i;
	}
	
	//Setting the seed of the RNG to system clock
	srand(time(NULL));

	//temp variable
	int temp;

	//Adding random edges to each node while avoiding self edge
	memcpy(vertex_copy,vertex_array,vertex_array_size);
	memcpy(vertex_array_copy,vertex_array,vertex_array_size);

	printf("Populating Edge Array....\n");

	//We give each node random edges and store them in the increasing order of weights in the edge array.
	for(i=0;i<vertices;i++)
	{
		//Function to jumble the nodes in the vertex array and assign them to each node
		for(j=vertices-1;j>0;j--)
		{		
			k=rand()%(j+1);
			temp = vertex_copy[j];
			vertex_copy[j]=vertex_copy[k];
			vertex_copy[k]=temp;
		}

		for(j=0;j<Edge_per_node;j++)
		{
			if(vertex_copy[j]==i)
			{
				j=j+1;
				edge_array[i*Edge_per_node+(j-1)]= vertex_copy[j];			
			}
			else
			{
				edge_array[i*Edge_per_node+j]= vertex_copy[j];			
			}
		}

	}

/*	
	//Can be uncommented to see the edges of each node
	printf("=== Initial edges===\n");
	for(i=0;i<vertices*Edge_per_node;i++)
	{
		printf("E[%d]= %d\n",i,edge_array[i]);
	}
*/	

	printf("Adding Weights to each edge...\n");

	//Adding weights to the edge_weight array
	for(i=0;i<vertices;i++)
	{
		int a = rand()%Maximum_weight+1;
		int b = rand()%Maximum_weight+1;
		for(j=0;j<Edge_per_node;j++)
		{
			edge_weight_array[i*Edge_per_node+j]=a+j*b;
		}
	}

/*	
	//Can be uncommented to see the edge weight of each edge
	printf("=== Initial edge weight weight===\n");
	for(i=0;i<vertices*Edge_per_node;i++)
	{
		printf("W[%d]= %d\n",i,edge_weight_array[i]);
	}
*/

	//Initializing gpu variables
	int *gpu_vertex_array;
	int *gpu_vertex_array_copy;
	int *gpu_edge_array;
	int *gpu_edge_weight_array;
	int *gpu_node_weight_array;
	int *gpu_mask_array;

	//Allocating memory to the gpu variables
	checkCuda(cudaMalloc((void**)&gpu_vertex_array,vertex_array_size));
	checkCuda(cudaMalloc((void**)&gpu_vertex_array_copy,vertex_array_size));
	checkCuda(cudaMalloc((void**)&gpu_node_weight_array,vertex_array_size));
	checkCuda(cudaMalloc((void**)&gpu_mask_array,vertex_array_size));
	checkCuda(cudaMalloc((void**)&gpu_edge_array,edge_array_size));
	checkCuda(cudaMalloc((void**)&gpu_edge_weight_array,edge_array_size));

	//Copying memory from Host to Device	
	checkCuda(cudaMemcpy(gpu_vertex_array,vertex_array,vertex_array_size,cudaMemcpyHostToDevice));
	checkCuda(cudaMemcpy(gpu_vertex_array_copy,vertex_array_copy,vertex_array_size,cudaMemcpyHostToDevice));
	checkCuda(cudaMemcpy(gpu_node_weight_array,node_weight_array,vertex_array_size,cudaMemcpyHostToDevice));
	checkCuda(cudaMemcpy(gpu_mask_array,mask_array,vertex_array_size,cudaMemcpyHostToDevice));
	checkCuda(cudaMemcpy(gpu_edge_array,edge_array,edge_array_size,cudaMemcpyHostToDevice));
	checkCuda(cudaMemcpy(gpu_edge_weight_array,edge_weight_array,edge_array_size,cudaMemcpyHostToDevice));

	//Setting the Block and Grid Size
	int blockSize, gridSize;
	blockSize=1024;
	gridSize = (int)ceil((float)vertices/blockSize); // Number of thread blocks in grid

	printf("Beginning Optimized Djikstra Algorithm\n");

	//Starting timer
	float start_time;
	TIMER_CREATE(start_time);
	TIMER_START(start_time);

	//Kernel call to initialize all the node weights. We provide the source node 0 
	Initializing<<<gridSize, blockSize>>>(gpu_node_weight_array,gpu_mask_array, 0);
	cudaError_t err = cudaGetLastError();
	/*	
	if (err != cudaSuccess) checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
	{
		printf("Error: %s\n", cudaGetErrorString(err));
	}
	*/

/*
	//Can be uncommented to see the initial weights of each node
	checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));	
	printf("=== Initial node weight===\n");
	for(i=0;i<vertices;i++)
	{
		printf("NW[%d]= %d\n ",i,node_weight_array[i]);
	}
*/

	//Variable min used to store the minimum node wieght of the relaxed nodes and use this node to relax all of its edges
	int *min=(int*)malloc(2*sizeof(int));
	min[0]=0;
	min[1]=0;

	//GPU variable to store min value
	int *gpu_min;
	checkCuda(cudaMalloc((void**)&gpu_min,2*sizeof(int)));

	//Begin the relax calls of the algorithm
	while(min[0]<infinity)
	{
		min[0] = infinity;
		checkCuda(cudaMemcpy(gpu_min,min,sizeof(int),cudaMemcpyHostToDevice));

		Minimum<<<gridSize, blockSize>>>(gpu_mask_array,gpu_vertex_array,gpu_vertex_array_copy,gpu_node_weight_array,gpu_edge_array,gpu_edge_weight_array,gpu_min);
		/*
		if (err != cudaSuccess) checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
		{
			printf("Error: %s\n", cudaGetErrorString(err));
		}
		*/
		Relax<<<gridSize, blockSize>>>(gpu_mask_array,gpu_node_weight_array,gpu_min);
		/*	
		if (err != cudaSuccess) checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
		{
			printf("Error: %s\n", cudaGetErrorString(err));
		}
		*/

/*
		//Can be uncommented to see the node weight and Dijkistra's Algorithm being performed ste by step
		checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
		for(i=0;i<vertices;i++)
		{
			printf("NW[%d]= %d\n ",i,node_weight_array[i]);
		}
*/

		checkCuda(cudaMemcpy(min,gpu_min,2*sizeof(int),cudaMemcpyDeviceToHost));	
	}

	//End timer
	TIMER_END(start_time);
	printf("Kernel Execution Time: %f ms\n",start_time);


	//Coppying the the final node weights from the Device to Host
	checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));


/*
	//Can be uncommented to see the final shortes distance of all node from Source Node
	printf("=== Final node weight===\n");
	for(i=0;i<vertices;i++)
	{
		printf("NW[%d]= %d\n ",i,node_weight_array[i]);
	}
*/

	cudaFree(gpu_vertex_array);
	cudaFree(gpu_node_weight_array);
	cudaFree(gpu_edge_array);
	cudaFree(gpu_edge_weight_array);
	cudaFree(gpu_mask_array);

	free(vertex_array);
	free(node_weight_array);
	free(edge_array);
	free(edge_weight_array);
	free(mask_array);

	return 0;
}

	.file	"tmpxft_002cf4de_00000000-6_code2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z12InitializingPiS_iPiS_i
	.type	_Z35__device_stub__Z12InitializingPiS_iPiS_i, @function
_Z35__device_stub__Z12InitializingPiS_iPiS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12InitializingPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z35__device_stub__Z12InitializingPiS_iPiS_i, .-_Z35__device_stub__Z12InitializingPiS_iPiS_i
	.globl	_Z12InitializingPiS_i
	.type	_Z12InitializingPiS_i, @function
_Z12InitializingPiS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z12InitializingPiS_iPiS_i
	.cfi_endproc
.LFE2054:
	.size	_Z12InitializingPiS_i, .-_Z12InitializingPiS_i
	.globl	_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.type	_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_, @function
_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z7MinimumPiS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_, .-_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.globl	_Z7MinimumPiS_S_S_S_S_S_
	.type	_Z7MinimumPiS_S_S_S_S_S_, @function
_Z7MinimumPiS_S_S_S_S_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.cfi_endproc
.LFE2056:
	.size	_Z7MinimumPiS_S_S_S_S_S_, .-_Z7MinimumPiS_S_S_S_S_S_
	.globl	_Z28__device_stub__Z5RelaxPiS_S_PiS_S_
	.type	_Z28__device_stub__Z5RelaxPiS_S_PiS_S_, @function
_Z28__device_stub__Z5RelaxPiS_S_PiS_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5RelaxPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z28__device_stub__Z5RelaxPiS_S_PiS_S_, .-_Z28__device_stub__Z5RelaxPiS_S_PiS_S_
	.globl	_Z5RelaxPiS_S_
	.type	_Z5RelaxPiS_S_, @function
_Z5RelaxPiS_S_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5RelaxPiS_S_PiS_S_
	.cfi_endproc
.LFE2058:
	.size	_Z5RelaxPiS_S_, .-_Z5RelaxPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Populating Vertex Array....\n"
.LC1:
	.string	"Populating Edge Array....\n"
.LC2:
	.string	"Adding Weights to each edge...\n"
.LC3:
	.string	"Beginning Optimized Djikstra Algorithm\n"
.LC4:
	.string	"Kernel Execution Time: %f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$20000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$20000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$20000, %edi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	$99980000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$99980000, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$20000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$20000, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	movl	%r14d, (%rbx,%r14,4)
	incq	%r14
	cmpq	$5000, %r14
	jne	.L19
	xorl	%edi, %edi
	xorl	%r15d, %r15d
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movq	%rbp, %rdi
	movq	%rbx, %rsi
	movq	%r14, %rcx
	rep movsl
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rcx
	rep movsl
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L20:
	movl	$4999, %r14d
.L21:
	call	rand@PLT
	leal	1(%r14), %r8d
	movl	0(%rbp,%r14,4), %edi
	cltd
	idivl	%r8d
	movslq	%edx, %rdx
	leaq	0(%rbp,%rdx,4), %rax
	movl	(%rax), %edx
	movl	%edx, 0(%rbp,%r14,4)
	movl	%edi, (%rax)
	decq	%r14
	jne	.L21
	imull	$4999, %r15d, %edi
	xorl	%eax, %eax
.L23:
	movslq	%eax, %rdx
	leal	(%rdi,%rax), %ecx
	leaq	0(,%rdx,4), %r8
	movl	0(%rbp,%rdx,4), %edx
	movslq	%ecx, %rcx
	leaq	0(%r13,%rcx,4), %rcx
	cmpl	%r15d, %edx
	jne	.L22
	movl	4(%rbp,%r8), %edx
	incl	%eax
.L22:
	incl	%eax
	movl	%edx, (%rcx)
	cmpl	$4998, %eax
	jle	.L23
	incl	%r15d
	cmpl	$5000, %r15d
	jne	.L20
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	movl	$5, %r14d
.L26:
	call	rand@PLT
	movl	%eax, %r15d
	call	rand@PLT
	imulq	$19996, %rbp, %r8
	cltd
	idivl	%r14d
	movl	%r15d, %eax
	addq	%r12, %r8
	leal	1(%rdx), %edi
	cltd
	idivl	%r14d
	xorl	%eax, %eax
	incl	%edx
.L25:
	movl	%edx, (%r8,%rax,4)
	incq	%rax
	addl	%edi, %edx
	cmpq	$4999, %rax
	jne	.L25
	incq	%rbp
	cmpq	$5000, %rbp
	jne	.L26
	leaq	40(%rsp), %rdi
	movl	$20000, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$20000, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$20000, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$20000, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$99980000, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$99980000, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$20000, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movl	$20000, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movl	$20000, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movl	$20000, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$99980000, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$99980000, %edx
	call	cudaMemcpy@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movabsq	$4294967301, %rdi
	movl	$1, %esi
	movq	%rdx, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	xorl	%edx, %edx
	call	_Z35__device_stub__Z12InitializingPiS_iPiS_i
.L27:
	call	cudaGetLastError@PLT
	movl	$8, %edi
	movabsq	$4294968320, %r15
	call	malloc@PLT
	xorl	%esi, %esi
	leaq	104(%rsp), %rdi
	movq	%rsi, (%rax)
	movl	$8, %esi
	movq	%rax, %rbp
	call	cudaMalloc@PLT
.L28:
	cmpl	$9999999, 0(%rbp)
	jg	.L39
	movl	$10000000, 0(%rbp)
	movq	104(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967301, %rdi
	movq	%r15, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	%rax
	.cfi_def_cfa_offset 216
	pushq	112(%rsp)
	.cfi_def_cfa_offset 224
	movq	80(%rsp), %r9
	movq	72(%rsp), %r8
	movq	88(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	96(%rsp), %rdi
	call	_Z38__device_stub__Z7MinimumPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	popq	%rdx
	.cfi_def_cfa_offset 216
	popq	%rcx
	.cfi_def_cfa_offset 208
.L29:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movl	$1, %ecx
	movabsq	$4294967301, %rdi
	movl	$1, %esi
	movq	%r15, 124(%rsp)
	movl	$1, 132(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$1, 120(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	104(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	80(%rsp), %rdi
	call	_Z28__device_stub__Z5RelaxPiS_S_PiS_S_
.L30:
	movq	104(%rsp), %rsi
	movl	$2, %ecx
	movl	$8, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	jmp	.L28
.L39:
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	96(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	96(%rsp), %rdx
	movq	88(%rsp), %rsi
	leaq	124(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	88(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	96(%rsp), %rdi
	call	cudaEventDestroy@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	124(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	72(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$20000, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z5RelaxPiS_S_"
.LC6:
	.string	"_Z7MinimumPiS_S_S_S_S_S_"
.LC7:
	.string	"_Z12InitializingPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5RelaxPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7MinimumPiS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12InitializingPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <string.h>


#define TIMER_CREATE(t)             \
        hipEvent_t t##_start, t##_end;     \
        hipEventCreate(&t##_start);        \
        hipEventCreate(&t##_end);


#define TIMER_START(t)                \
        hipEventRecord(t##_start);         \
        hipEventSynchronize(t##_start);    \


#define TIMER_END(t)                             \
        hipEventRecord(t##_end);                      \
        hipEventSynchronize(t##_end);                 \
        hipEventElapsedTime(&t, t##_start, t##_end);  \
        hipEventDestroy(t##_start);                   \
        hipEventDestroy(t##_end);


//Function to check for errors
inline hipError_t checkCuda(hipError_t result) 
{
	#if defined(DEBUG) || defined(_DEBUG)
		if (result != hipSuccess) {
			fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
			exit(-1);
		}
	#endif
	return result;
}

//Number of vertices
#define vertices 5000 

//Number of edges per vertex
#define Edge_per_node 4999

//Used to define weights on each edge.
#define Maximum_weight 5

//Value for infinity
#define infinity 10000000

//Kernel call to inititialize all node weights to infinity except for the source node. We mark the source node as settled after this point
__global__ void Initializing(int *node_weight_array, int *mask_array, int Source) // CUDA kernel
{
	int id = blockIdx.x*blockDim.x+threadIdx.x; // Get global thread ID
	if(id<vertices)
	{
		if(id==Source)
		{
			node_weight_array[id]=0;
			mask_array[id]=1;
		}
		else
		{
			node_weight_array[id]=infinity;
			mask_array[id]=0;
		}
	}
}


//Kernel Call to choose a a node which is relaxed and settled and to relax the outgoing edges of each settled node.
__global__ void Minimum(int *mask_array,int *vertex_array,int *vertex_array_copy, int *node_weight_array, int *edge_array, int *edge_weight_array, int *min)
{
	int id = blockIdx.x*blockDim.x+threadIdx.x; // Get global thread ID
	//Iterative variables
	int i,n,t;	
	if(id<vertices)
	{
		if(mask_array[id]==1)
		{
			t=vertex_array_copy[id];	
			for(i=t*Edge_per_node;i<t*Edge_per_node+Edge_per_node;i++)
			{
				n=edge_array[i];
				if(mask_array[n]!=1)
				{
					atomicMin(&node_weight_array[n],node_weight_array[id]+edge_weight_array[i]);
					atomicMin(&min[0],node_weight_array[n]);
					vertex_array_copy[id]=n;
					break;
				}
			}
		}
	}		
}

//Kernel call to mark all the settled nodes
__global__ void Relax(int *mask_array,int *node_weight_array,int *min)
{
	int id = blockIdx.x*blockDim.x+threadIdx.x; // Get global thread ID
	if(id<vertices)
	{
		if(mask_array[id]!=1 && node_weight_array[id]==min[0])
		{
			mask_array[id]=1;
		}
	}	
}

int main( int argc, char* argv[] )
{

	//Size of the Vertex array
	size_t vertex_array_size = vertices*sizeof(int);
	
	//Size of the edge array and edge_weight array
	size_t edge_array_size = vertices*Edge_per_node*sizeof(int);

	//Intializing the vertex array
	int *vertex_array = (int*)malloc(vertex_array_size); 

	//Intializing the vertex array
	int *vertex_array_copy = (int*)malloc(vertex_array_size); 

	//Initializing a copy of the vertex array
	int *vertex_copy = (int*)malloc(vertex_array_size); 

	//Intializing the edge array
	int *edge_array=(int*)malloc(edge_array_size);

	//Initializing edge_weight_array which stores the weights of each edge
	int *edge_weight_array = (int*)malloc(edge_array_size);

	//Initializing Node weight array which stores the value for the current weight to reach the node
	int *node_weight_array = (int*)malloc(vertex_array_size);

	//Array to mark if a node is settled or not
	int *mask_array = (int*)malloc(vertex_array_size);

	//Iterative operator
	int i,j,k;  

	printf("Populating Vertex Array....\n");

	//Setting node number in vertex_array
	for(i=0;i<vertices;i++)
	{
		vertex_array[i]=i;
	}
	
	//Setting the seed of the RNG to system clock
	srand(time(NULL));

	//temp variable
	int temp;

	//Adding random edges to each node while avoiding self edge
	memcpy(vertex_copy,vertex_array,vertex_array_size);
	memcpy(vertex_array_copy,vertex_array,vertex_array_size);

	printf("Populating Edge Array....\n");

	//We give each node random edges and store them in the increasing order of weights in the edge array.
	for(i=0;i<vertices;i++)
	{
		//Function to jumble the nodes in the vertex array and assign them to each node
		for(j=vertices-1;j>0;j--)
		{		
			k=rand()%(j+1);
			temp = vertex_copy[j];
			vertex_copy[j]=vertex_copy[k];
			vertex_copy[k]=temp;
		}

		for(j=0;j<Edge_per_node;j++)
		{
			if(vertex_copy[j]==i)
			{
				j=j+1;
				edge_array[i*Edge_per_node+(j-1)]= vertex_copy[j];			
			}
			else
			{
				edge_array[i*Edge_per_node+j]= vertex_copy[j];			
			}
		}

	}

/*	
	//Can be uncommented to see the edges of each node
	printf("=== Initial edges===\n");
	for(i=0;i<vertices*Edge_per_node;i++)
	{
		printf("E[%d]= %d\n",i,edge_array[i]);
	}
*/	

	printf("Adding Weights to each edge...\n");

	//Adding weights to the edge_weight array
	for(i=0;i<vertices;i++)
	{
		int a = rand()%Maximum_weight+1;
		int b = rand()%Maximum_weight+1;
		for(j=0;j<Edge_per_node;j++)
		{
			edge_weight_array[i*Edge_per_node+j]=a+j*b;
		}
	}

/*	
	//Can be uncommented to see the edge weight of each edge
	printf("=== Initial edge weight weight===\n");
	for(i=0;i<vertices*Edge_per_node;i++)
	{
		printf("W[%d]= %d\n",i,edge_weight_array[i]);
	}
*/

	//Initializing gpu variables
	int *gpu_vertex_array;
	int *gpu_vertex_array_copy;
	int *gpu_edge_array;
	int *gpu_edge_weight_array;
	int *gpu_node_weight_array;
	int *gpu_mask_array;

	//Allocating memory to the gpu variables
	checkCuda(hipMalloc((void**)&gpu_vertex_array,vertex_array_size));
	checkCuda(hipMalloc((void**)&gpu_vertex_array_copy,vertex_array_size));
	checkCuda(hipMalloc((void**)&gpu_node_weight_array,vertex_array_size));
	checkCuda(hipMalloc((void**)&gpu_mask_array,vertex_array_size));
	checkCuda(hipMalloc((void**)&gpu_edge_array,edge_array_size));
	checkCuda(hipMalloc((void**)&gpu_edge_weight_array,edge_array_size));

	//Copying memory from Host to Device	
	checkCuda(hipMemcpy(gpu_vertex_array,vertex_array,vertex_array_size,hipMemcpyHostToDevice));
	checkCuda(hipMemcpy(gpu_vertex_array_copy,vertex_array_copy,vertex_array_size,hipMemcpyHostToDevice));
	checkCuda(hipMemcpy(gpu_node_weight_array,node_weight_array,vertex_array_size,hipMemcpyHostToDevice));
	checkCuda(hipMemcpy(gpu_mask_array,mask_array,vertex_array_size,hipMemcpyHostToDevice));
	checkCuda(hipMemcpy(gpu_edge_array,edge_array,edge_array_size,hipMemcpyHostToDevice));
	checkCuda(hipMemcpy(gpu_edge_weight_array,edge_weight_array,edge_array_size,hipMemcpyHostToDevice));

	//Setting the Block and Grid Size
	int blockSize, gridSize;
	blockSize=1024;
	gridSize = (int)ceil((float)vertices/blockSize); // Number of thread blocks in grid

	printf("Beginning Optimized Djikstra Algorithm\n");

	//Starting timer
	float start_time;
	TIMER_CREATE(start_time);
	TIMER_START(start_time);

	//Kernel call to initialize all the node weights. We provide the source node 0 
	Initializing<<<gridSize, blockSize>>>(gpu_node_weight_array,gpu_mask_array, 0);
	hipError_t err = hipGetLastError();
	/*	
	if (err != cudaSuccess) checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
	{
		printf("Error: %s\n", cudaGetErrorString(err));
	}
	*/

/*
	//Can be uncommented to see the initial weights of each node
	checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));	
	printf("=== Initial node weight===\n");
	for(i=0;i<vertices;i++)
	{
		printf("NW[%d]= %d\n ",i,node_weight_array[i]);
	}
*/

	//Variable min used to store the minimum node wieght of the relaxed nodes and use this node to relax all of its edges
	int *min=(int*)malloc(2*sizeof(int));
	min[0]=0;
	min[1]=0;

	//GPU variable to store min value
	int *gpu_min;
	checkCuda(hipMalloc((void**)&gpu_min,2*sizeof(int)));

	//Begin the relax calls of the algorithm
	while(min[0]<infinity)
	{
		min[0] = infinity;
		checkCuda(hipMemcpy(gpu_min,min,sizeof(int),hipMemcpyHostToDevice));

		Minimum<<<gridSize, blockSize>>>(gpu_mask_array,gpu_vertex_array,gpu_vertex_array_copy,gpu_node_weight_array,gpu_edge_array,gpu_edge_weight_array,gpu_min);
		/*
		if (err != cudaSuccess) checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
		{
			printf("Error: %s\n", cudaGetErrorString(err));
		}
		*/
		Relax<<<gridSize, blockSize>>>(gpu_mask_array,gpu_node_weight_array,gpu_min);
		/*	
		if (err != cudaSuccess) checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
		{
			printf("Error: %s\n", cudaGetErrorString(err));
		}
		*/

/*
		//Can be uncommented to see the node weight and Dijkistra's Algorithm being performed ste by step
		checkCuda(cudaMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,cudaMemcpyDeviceToHost));
		for(i=0;i<vertices;i++)
		{
			printf("NW[%d]= %d\n ",i,node_weight_array[i]);
		}
*/

		checkCuda(hipMemcpy(min,gpu_min,2*sizeof(int),hipMemcpyDeviceToHost));	
	}

	//End timer
	TIMER_END(start_time);
	printf("Kernel Execution Time: %f ms\n",start_time);


	//Coppying the the final node weights from the Device to Host
	checkCuda(hipMemcpy(node_weight_array,gpu_node_weight_array,vertex_array_size,hipMemcpyDeviceToHost));


/*
	//Can be uncommented to see the final shortes distance of all node from Source Node
	printf("=== Final node weight===\n");
	for(i=0;i<vertices;i++)
	{
		printf("NW[%d]= %d\n ",i,node_weight_array[i]);
	}
*/

	hipFree(gpu_vertex_array);
	hipFree(gpu_node_weight_array);
	hipFree(gpu_edge_array);
	hipFree(gpu_edge_weight_array);
	hipFree(gpu_mask_array);

	free(vertex_array);
	free(node_weight_array);
	free(edge_array);
	free(edge_weight_array);
	free(mask_array);

	return 0;
}

	.text
	.file	"code2.hip"
	.globl	_Z27__device_stub__InitializingPiS_i # -- Begin function _Z27__device_stub__InitializingPiS_i
	.type	_Z27__device_stub__InitializingPiS_i,@function
_Z27__device_stub__InitializingPiS_i:   # @_Z27__device_stub__InitializingPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12InitializingPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__InitializingPiS_i, .Lfunc_end0-_Z27__device_stub__InitializingPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__MinimumPiS_S_S_S_S_S_ # -- Begin function _Z22__device_stub__MinimumPiS_S_S_S_S_S_
	.type	_Z22__device_stub__MinimumPiS_S_S_S_S_S_,@function
_Z22__device_stub__MinimumPiS_S_S_S_S_S_: # @_Z22__device_stub__MinimumPiS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7MinimumPiS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__MinimumPiS_S_S_S_S_S_, .Lfunc_end1-_Z22__device_stub__MinimumPiS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__RelaxPiS_S_  # -- Begin function _Z20__device_stub__RelaxPiS_S_
	.type	_Z20__device_stub__RelaxPiS_S_,@function
_Z20__device_stub__RelaxPiS_S_:         # @_Z20__device_stub__RelaxPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5RelaxPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__RelaxPiS_S_, .Lfunc_end2-_Z20__device_stub__RelaxPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$20000, %edi                    # imm = 0x4E20
	callq	malloc
	movq	%rax, %rbx
	movl	$20000, %edi                    # imm = 0x4E20
	callq	malloc
	movq	%rax, %rbp
	movl	$20000, %edi                    # imm = 0x4E20
	callq	malloc
	movq	%rax, %r12
	movl	$99980000, %edi                 # imm = 0x5F592E0
	callq	malloc
	movq	%rax, %r14
	movl	$99980000, %edi                 # imm = 0x5F592E0
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	$20000, %edi                    # imm = 0x4E20
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$20000, %edi                    # imm = 0x4E20
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%eax, %eax
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rbx,%rax,4)
	incq	%rax
	cmpq	$5000, %rax                     # imm = 0x1388
	jne	.LBB3_1
# %bb.2:
	xorl	%r15d, %r15d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$20000, %edx                    # imm = 0x4E20
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	memcpy@PLT
	movl	$20000, %edx                    # imm = 0x4E20
	movq	%rbp, %rdi
	movq	%rbx, %rsi
	callq	memcpy@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB3_3:                                # %.preheader129
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
                                        #     Child Loop BB3_6 Depth 2
	movl	$5000, %r13d                    # imm = 0x1388
.LBB3_4:                                #   Parent Loop BB3_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltd
	idivl	%r13d
	movl	-4(%r12,%r13,4), %eax
	movslq	%edx, %rcx
	movl	(%r12,%rcx,4), %edx
	movl	%edx, -4(%r12,%r13,4)
	movl	%eax, (%r12,%rcx,4)
	decq	%r13
	cmpq	$1, %r13
	ja	.LBB3_4
# %bb.5:                                # %.preheader
                                        #   in Loop: Header=BB3_3 Depth=1
	imull	$4999, %r15d, %eax              # imm = 0x1387
	xorl	%ecx, %ecx
.LBB3_6:                                #   Parent Loop BB3_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	%ecx, %rdi
	movl	(%r12,%rdi,4), %esi
	movl	%ecx, %edx
	cmpl	%r15d, %esi
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_6 Depth=2
	leal	1(%rdi), %edx
	movl	4(%r12,%rdi,4), %esi
.LBB3_8:                                #   in Loop: Header=BB3_6 Depth=2
	addl	%eax, %ecx
	movslq	%ecx, %rcx
	movl	%esi, (%r14,%rcx,4)
	leal	1(%rdx), %ecx
	cmpl	$4998, %edx                     # imm = 0x1386
	jl	.LBB3_6
# %bb.9:                                #   in Loop: Header=BB3_3 Depth=1
	incl	%r15d
	cmpl	$5000, %r15d                    # imm = 0x1388
	jne	.LBB3_3
# %bb.10:
	movq	%rbp, 96(%rsp)                  # 8-byte Spill
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%r15d, %r15d
	movq	40(%rsp), %r12                  # 8-byte Reload
.LBB3_11:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_12 Depth 2
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	leal	(%rax,%rcx), %ebp
	incl	%ebp
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	xorl	%ecx, %ecx
.LBB3_12:                               #   Parent Loop BB3_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ebp, (%r12,%rcx,4)
	incq	%rcx
	addl	%eax, %ebp
	cmpq	$4999, %rcx                     # imm = 0x1387
	jne	.LBB3_12
# %bb.13:                               #   in Loop: Header=BB3_11 Depth=1
	incq	%r15
	addq	$19996, %r12                    # imm = 0x4E1C
	cmpq	$5000, %r15                     # imm = 0x1388
	jne	.LBB3_11
# %bb.14:
	movabsq	$4294967301, %r12               # imm = 0x100000005
	leaq	88(%rsp), %rbp
	movl	$20000, %esi                    # imm = 0x4E20
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	104(%rsp), %r13
	movl	$20000, %esi                    # imm = 0x4E20
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$20000, %esi                    # imm = 0x4E20
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$20000, %esi                    # imm = 0x4E20
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$99980000, %esi                 # imm = 0x5F592E0
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$99980000, %esi                 # imm = 0x5F592E0
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$20000, %edx                    # imm = 0x4E20
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$20000, %edx                    # imm = 0x4E20
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$20000, %edx                    # imm = 0x4E20
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$20000, %edx                    # imm = 0x4E20
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rax
	movq	(%rax), %rdi
	movl	$99980000, %edx                 # imm = 0x5F592E0
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	movl	$99980000, %edx                 # imm = 0x5F592E0
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	leaq	80(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r15), %rdi
	callq	hipEventSynchronize
	leaq	1019(%r12), %rbp
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_16
# %bb.15:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	xorl	%edx, %edx
	callq	_Z27__device_stub__InitializingPiS_i
.LBB3_16:                               # %.lr.ph.preheader
	callq	hipGetLastError
	movl	$8, %edi
	callq	malloc
	movq	%rax, %r15
	movq	$0, (%rax)
	leaq	24(%rsp), %rdi
	movl	$8, %esi
	callq	hipMalloc
.LBB3_17:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$10000000, (%r15)               # imm = 0x989680
	movq	24(%rsp), %rdi
	movl	$4, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_19
# %bb.18:                               #   in Loop: Header=BB3_17 Depth=1
	movq	8(%rsp), %rdi
	movq	88(%rsp), %rsi
	movq	104(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	56(%rsp), %r8
	movq	48(%rsp), %r9
	movq	24(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z22__device_stub__MinimumPiS_S_S_S_S_S_
.LBB3_19:                               #   in Loop: Header=BB3_17 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_21
# %bb.20:                               #   in Loop: Header=BB3_17 Depth=1
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdx
	callq	_Z20__device_stub__RelaxPiS_S_
.LBB3_21:                               #   in Loop: Header=BB3_17 Depth=1
	movq	24(%rsp), %rsi
	movl	$8, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$10000000, (%r15)               # imm = 0x989680
	jl	.LBB3_17
# %bb.22:                               # %._crit_edge
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rdi
	callq	hipEventSynchronize
	movq	80(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	116(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movq	80(%rsp), %rdi
	callq	hipEventDestroy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rsi
	movl	$20000, %edx                    # imm = 0x4E20
	movq	64(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12InitializingPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7MinimumPiS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5RelaxPiS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12InitializingPiS_i,@object   # @_Z12InitializingPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z12InitializingPiS_i
	.p2align	3, 0x0
_Z12InitializingPiS_i:
	.quad	_Z27__device_stub__InitializingPiS_i
	.size	_Z12InitializingPiS_i, 8

	.type	_Z7MinimumPiS_S_S_S_S_S_,@object # @_Z7MinimumPiS_S_S_S_S_S_
	.globl	_Z7MinimumPiS_S_S_S_S_S_
	.p2align	3, 0x0
_Z7MinimumPiS_S_S_S_S_S_:
	.quad	_Z22__device_stub__MinimumPiS_S_S_S_S_S_
	.size	_Z7MinimumPiS_S_S_S_S_S_, 8

	.type	_Z5RelaxPiS_S_,@object          # @_Z5RelaxPiS_S_
	.globl	_Z5RelaxPiS_S_
	.p2align	3, 0x0
_Z5RelaxPiS_S_:
	.quad	_Z20__device_stub__RelaxPiS_S_
	.size	_Z5RelaxPiS_S_, 8

	.type	.L.str.4,@object                # @.str.4
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.4:
	.asciz	"Kernel Execution Time: %f ms\n"
	.size	.L.str.4, 30

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12InitializingPiS_i"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7MinimumPiS_S_S_S_S_S_"
	.size	.L__unnamed_2, 25

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z5RelaxPiS_S_"
	.size	.L__unnamed_3, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Populating Vertex Array...."
	.size	.Lstr, 28

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Populating Edge Array...."
	.size	.Lstr.1, 26

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Adding Weights to each edge..."
	.size	.Lstr.2, 31

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Beginning Optimized Djikstra Algorithm"
	.size	.Lstr.3, 39

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__InitializingPiS_i
	.addrsig_sym _Z22__device_stub__MinimumPiS_S_S_S_S_S_
	.addrsig_sym _Z20__device_stub__RelaxPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12InitializingPiS_i
	.addrsig_sym _Z7MinimumPiS_S_S_S_S_S_
	.addrsig_sym _Z5RelaxPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12InitializingPiS_i   ; -- Begin function _Z12InitializingPiS_i
	.globl	_Z12InitializingPiS_i
	.p2align	8
	.type	_Z12InitializingPiS_i,@function
_Z12InitializingPiS_i:                  ; @_Z12InitializingPiS_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x1388, v1
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %.sink.split
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s4, v1
	v_add_co_u32 v0, s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s1, v3, s0
	v_cndmask_b32_e64 v4, 0x989680, 0, vcc_lo
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
	global_store_b32 v[2:3], v5, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12InitializingPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12InitializingPiS_i, .Lfunc_end0-_Z12InitializingPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7MinimumPiS_S_S_S_S_S_ ; -- Begin function _Z7MinimumPiS_S_S_S_S_S_
	.globl	_Z7MinimumPiS_S_S_S_S_S_
	.p2align	8
	.type	_Z7MinimumPiS_S_S_S_S_S_,@function
_Z7MinimumPiS_S_S_S_S_S_:               ; @_Z7MinimumPiS_S_S_S_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x1388, v1
	s_cbranch_execz .LBB1_12
; %bb.1:
	s_load_b64 s[12:13], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_12
; %bb.2:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x30
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr5
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v7, 0x1387, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v13, 0x1386, v7
	v_add_nc_u32_e32 v14, -1, v7
	v_lshlrev_b64 v[4:5], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v5, vcc_lo
                                        ; implicit-def: $sgpr8
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[9:10], off
	s_or_b32 s5, s5, exec_lo
	s_or_b32 s8, s8, exec_lo
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_co_u32 v11, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v6, vcc_lo
	global_load_b32 v15, v[11:12], off
	v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
                                        ; implicit-def: $vgpr7_vgpr8
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 1, v15
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v14, 1, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v14, v13
	v_add_co_u32 v9, s0, v9, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
	s_and_not1_b32 s0, s8, exec_lo
	s_and_b32 s8, vcc_lo, exec_lo
	s_and_not1_b32 s5, s5, exec_lo
	s_or_b32 s8, s0, s8
; %bb.5:                                ; %Flow87
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s8
	s_or_b32 s1, s0, s1
	s_and_not1_b32 s0, s4, exec_lo
	s_and_b32 s4, s5, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s0, s4
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_3
; %bb.6:                                ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_12
; %bb.7:
	v_lshlrev_b64 v[7:8], 2, v[11:12]
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	s_brev_b32 s1, -2
	global_load_b32 v9, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v7, v9
	global_atomic_min_i32 v[2:3], v5, off
	global_load_b32 v2, v[2:3], off
.LBB1_8:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s4, s0
	s_waitcnt vmcnt(0)
	v_readlane_b32 s5, v2, s4
	s_lshl_b32 s4, 1, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s0, s0, s4
	s_min_i32 s1, s1, s5
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB1_8
; %bb.9:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v2, exec_lo, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s1
	global_atomic_min_i32 v2, v3, s[2:3]
.LBB1_11:
	s_or_b32 exec_lo, exec_lo, s0
	global_store_b32 v[0:1], v4, off
.LBB1_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7MinimumPiS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7MinimumPiS_S_S_S_S_S_, .Lfunc_end1-_Z7MinimumPiS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 628
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5RelaxPiS_S_          ; -- Begin function _Z5RelaxPiS_S_
	.globl	_Z5RelaxPiS_S_
	.p2align	8
	.type	_Z5RelaxPiS_S_,@function
_Z5RelaxPiS_S_:                         ; @_Z5RelaxPiS_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x1388, v1
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.2:
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_load_b64 s[0:1], s[0:1], 0x10
	global_load_b32 v2, v[2:3], off
	s_waitcnt lgkmcnt(0)
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5RelaxPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z5RelaxPiS_S_, .Lfunc_end2-_Z5RelaxPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12InitializingPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12InitializingPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7MinimumPiS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7MinimumPiS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5RelaxPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5RelaxPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
