#include <math.h>
#include <stdio.h>

#define SHAREDSIZE 8000  /* Should be changed to dynamically detect shared
                             memory size if at all possible.  */

//Forward declarations
__global__ void GPUMerge(float *d_list, int len, int stepSize,
                         int eltsPerThread);

/* Mergesort definition.  Takes a pointer to a list of floats.
 * the length of the list, the number of threads per block, and 
 * the number of blocks on which to execute.  
 * Puts the list into sorted order in-place.*/
void MergeSort(float *h_list, int len, int threadsPerBlock, int blocks) {

    float *d_list;
    if ( (cudaMalloc((void **) &d_list, len*sizeof(float))) == 
         cudaErrorMemoryAllocation) {
        printf("Error:  Insufficient device memory at line %d\n", __LINE__);
        return;
    }

    cudaMemcpy(d_list, h_list, len*sizeof(float), cudaMemcpyHostToDevice);

    int stepSize = ceil(len/float(threadsPerBlock*blocks));
    int eltsPerThread = ceil(stepSize/threadsPerBlock);
    int maxStep = SHAREDSIZE/sizeof(float);

    if (maxStep < stepSize) {
        stepSize = maxStep;
    }

    GPUMerge<<<blocks, threadsPerBlock>>>(d_list, len, stepSize,
                                          eltsPerThread);

    cudaMemcpy(h_list, d_list, len*sizeof(float), cudaMemcpyDeviceToHost);

}

/* Mergesort definition.  Takes a pointer to a list of floats, the length
 * of the list, and the number of list elements given to each thread.
 * Puts the list into sorted order in-place.*/
__global__ void GPUMerge(float *d_list, int len, int stepSize,
                         int eltsPerThread){

    int my_start, my_end; //indices of each thread's start/end

    //Declare counters requierd for recursive mergesort
    int l_start, r_start; //Start index of the two lists being merged
    int old_l_start;
    int l_end, r_end; //End index of the two lists being merged
    int headLoc; //current location of the write head on the newList
    short curList = 0; /* Will be used to determine which of two lists is the
                        * most up-to-date, since merge sort is not an in-place
                        * sorting algorithm. */

    //Attempt to allocate enough shared memory for this block's list...
    //Note that mergesort is not an in-place sort, so we need double memory.
    __shared__ float subList[2][SHAREDSIZE/sizeof(float)];

    //Load memory
    int index = blockIdx.x*blockDim.x + threadIdx.x;
    for (int i = 0; i < eltsPerThread; i++){
        if (index + i < len){
            subList[curList][eltsPerThread*threadIdx.x + i]=d_list[index + i];
        }
    }

    //Wait until all memory has been loaded
    __syncthreads();
    
    //Merge the left and right lists.
    for (int walkLen = 1; walkLen < len; walkLen *= 2) { 
        //Set up start and end indices.
        my_start = eltsPerThread*threadIdx.x;
        my_end = my_start + eltsPerThread;
        l_start = my_start;

        while (l_start < my_end) { 
            old_l_start = l_start; //l_start will be getting incremented soon.
            //If this happens, we are done.
            if (l_start > my_end){
                l_start = len;
                break;
            }
            
            l_end = l_start + walkLen;
            if (l_end > my_end) {
                l_end = len;
            }
            
            r_start = l_end;
            if (r_start > my_end) {
                r_end = len;
            }
            
            r_end = r_start + walkLen;
            if (r_end > my_end) {
                r_end = len;
            }
            
            for (int i = 0; i < walkLen; i++){
                if (subList[curList][l_start] < subList[curList][r_start]) {
                    subList[!curList][headLoc] = subList[curList][l_start];
                    l_start++;
                    headLoc++;
                    //Check if l is now empty
                    if (l_start == l_end) {
                        for (int j = r_start; j < r_end; j++){
                            subList[!curList][headLoc] = 
                                subList[curList][r_start];
                            r_start++;
                            headLoc++;
                    }
                    } 
                }
                else {
                    subList[!curList][headLoc] = subList[curList][r_start];
                    r_start++;
                    //Check if r is now empty
                    if (r_start == r_end) {
                        for (int j = l_start; j < l_end; j++){
                            subList[!curList][headLoc] = 
                                subList[curList][r_start];
                            r_start++;
                            headLoc++;
                        }
                    } 
                }
            }

            l_start = old_l_start + 2*walkLen;
            curList = !curList;
        }
    }
    
    return;

    //subList[blockIdx

    //...otherwise, we use global memory...
    /*
    if ( (subList = cudaMalloc(stepsize*sizeof(float)) != NULL ) {
            //   do some shit.
            
        }    
    */

    //...otherwise, we give up.

}

int main(int argc, char *argv[]){
    
    int len;
    float *h_list;

    if (argc != 2) {
        printf("Invalid argument count.  %s requires exactly 1 argument, \
%d given",
               argv[0], argc);
        return -1;
    }
    
    FILE *fin = fopen(argv[1], "r");
    
    if (fin == NULL){
        printf("Could not open file: %s", argv[1]);
        return -2;
    }

    fscanf(fin, "%d", &len);

    h_list = (float *)malloc(len*sizeof(float));
    if (h_list == NULL){
        printf("Insufficient host memory to allocate at %d", __LINE__);
        return -3;
    }

    for (int i = 0; i < len; i++){
        fscanf(fin, "%f ", &h_list[i]);
    }

    for (int i = 0; i < len; i++){
        printf("%f\n", h_list[i]);
    }

    MergeSort(h_list, len, 8, 512);

    return 0;
}

	.file	"tmpxft_002ecfc7_00000000-6_mergesort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z8GPUMergePfiiiPfiii
	.type	_Z30__device_stub__Z8GPUMergePfiiiPfiii, @function
_Z30__device_stub__Z8GPUMergePfiiiPfiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8GPUMergePfiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z30__device_stub__Z8GPUMergePfiiiPfiii, .-_Z30__device_stub__Z8GPUMergePfiiiPfiii
	.globl	_Z8GPUMergePfiii
	.type	_Z8GPUMergePfiii, @function
_Z8GPUMergePfiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8GPUMergePfiiiPfiii
	.cfi_endproc
.LFE2054:
	.size	_Z8GPUMergePfiii, .-_Z8GPUMergePfiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Error:  Insufficient device memory at line %d\n"
	.text
	.globl	_Z9MergeSortPfiii
	.type	_Z9MergeSortPfiii, @function
_Z9MergeSortPfiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%ecx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movslq	%esi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rbp, %r12
	salq	$2, %rbp
	movl	%edx, %ebx
	movq	%rbp, %rsi
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	cmpl	$2, %eax
	jne	.L9
	movl	$20, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L8
.L9:
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	movl	%ebx, 28(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	%r14d, 16(%rsp)
	movq	%rax, 32(%rsp)
	movl	36(%rsp), %ecx
	movq	%rax, 20(%rsp)
	movq	28(%rsp), %rdx
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	imull	%ebx, %r14d
	cvtsi2ssl	%r12d, %xmm0
	cvtsi2ssl	%r14d, %xmm1
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movq	8(%rsp), %rdi
	cvttss2sil	%xmm0, %esi
	movl	%esi, %eax
	cltd
	idivl	%ebx
	movl	$2000, %edx
	cmpl	%edx, %esi
	cmovle	%esi, %edx
	movl	%r12d, %esi
	movl	%eax, %ecx
	call	_Z30__device_stub__Z8GPUMergePfiiiPfiii
.L11:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
.L8:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9MergeSortPfiii, .-_Z9MergeSortPfiii
	.section	.rodata.str1.1
.LC1:
	.string	"Invalid argument count.  %s requires exactly 1 argument, %d given"
.LC2:
	.string	"r"
.LC3:
	.string	"Could not open file: %s"
.LC4:
	.string	"%d"
.LC5:
	.string	"Insufficient host memory to allocate at %d"
.LC6:
	.string	"%f "
.LC7:
	.string	"%f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rsi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	je	.L15
	movq	(%rsi), %rdx
	movl	%edi, %ecx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L14
.L15:
	movq	8(%rsi), %rdi
	leaq	.LC2(%rip), %rsi
	call	fopen@PLT
	movq	%rax, %rbp
	testq	%rax, %rax
	jne	.L17
	movq	8(%rbx), %rdx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$-2, %eax
	jmp	.L14
.L17:
	movq	%rax, %rdi
	leaq	4(%rsp), %rdx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movslq	4(%rsp), %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L18
	movq	%rax, %r13
	xorl	%r12d, %r12d
	leaq	.LC6(%rip), %r14
	jmp	.L19
.L18:
	movl	$177, %edx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$-3, %eax
	jmp	.L14
.L19:
	cmpl	%r12d, 4(%rsp)
	jle	.L25
	movq	%r13, %rdx
	movq	%r14, %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	incl	%r12d
	addq	$4, %r13
	jmp	.L19
.L25:
	xorl	%ebp, %ebp
	leaq	.LC7(%rip), %r12
.L21:
	movl	4(%rsp), %esi
	cmpl	%ebp, %esi
	jle	.L26
	movq	%r12, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbp
	jmp	.L21
.L26:
	movl	$512, %ecx
	movl	$8, %edx
	movq	%rbx, %rdi
	call	_Z9MergeSortPfiii
	xorl	%eax, %eax
.L14:
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z8GPUMergePfiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8GPUMergePfiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>

#define SHAREDSIZE 8000  /* Should be changed to dynamically detect shared
                             memory size if at all possible.  */

//Forward declarations
__global__ void GPUMerge(float *d_list, int len, int stepSize,
                         int eltsPerThread);

/* Mergesort definition.  Takes a pointer to a list of floats.
 * the length of the list, the number of threads per block, and 
 * the number of blocks on which to execute.  
 * Puts the list into sorted order in-place.*/
void MergeSort(float *h_list, int len, int threadsPerBlock, int blocks) {

    float *d_list;
    if ( (hipMalloc((void **) &d_list, len*sizeof(float))) == 
         hipErrorOutOfMemory) {
        printf("Error:  Insufficient device memory at line %d\n", __LINE__);
        return;
    }

    hipMemcpy(d_list, h_list, len*sizeof(float), hipMemcpyHostToDevice);

    int stepSize = ceil(len/float(threadsPerBlock*blocks));
    int eltsPerThread = ceil(stepSize/threadsPerBlock);
    int maxStep = SHAREDSIZE/sizeof(float);

    if (maxStep < stepSize) {
        stepSize = maxStep;
    }

    GPUMerge<<<blocks, threadsPerBlock>>>(d_list, len, stepSize,
                                          eltsPerThread);

    hipMemcpy(h_list, d_list, len*sizeof(float), hipMemcpyDeviceToHost);

}

/* Mergesort definition.  Takes a pointer to a list of floats, the length
 * of the list, and the number of list elements given to each thread.
 * Puts the list into sorted order in-place.*/
__global__ void GPUMerge(float *d_list, int len, int stepSize,
                         int eltsPerThread){

    int my_start, my_end; //indices of each thread's start/end

    //Declare counters requierd for recursive mergesort
    int l_start, r_start; //Start index of the two lists being merged
    int old_l_start;
    int l_end, r_end; //End index of the two lists being merged
    int headLoc; //current location of the write head on the newList
    short curList = 0; /* Will be used to determine which of two lists is the
                        * most up-to-date, since merge sort is not an in-place
                        * sorting algorithm. */

    //Attempt to allocate enough shared memory for this block's list...
    //Note that mergesort is not an in-place sort, so we need double memory.
    __shared__ float subList[2][SHAREDSIZE/sizeof(float)];

    //Load memory
    int index = blockIdx.x*blockDim.x + threadIdx.x;
    for (int i = 0; i < eltsPerThread; i++){
        if (index + i < len){
            subList[curList][eltsPerThread*threadIdx.x + i]=d_list[index + i];
        }
    }

    //Wait until all memory has been loaded
    __syncthreads();
    
    //Merge the left and right lists.
    for (int walkLen = 1; walkLen < len; walkLen *= 2) { 
        //Set up start and end indices.
        my_start = eltsPerThread*threadIdx.x;
        my_end = my_start + eltsPerThread;
        l_start = my_start;

        while (l_start < my_end) { 
            old_l_start = l_start; //l_start will be getting incremented soon.
            //If this happens, we are done.
            if (l_start > my_end){
                l_start = len;
                break;
            }
            
            l_end = l_start + walkLen;
            if (l_end > my_end) {
                l_end = len;
            }
            
            r_start = l_end;
            if (r_start > my_end) {
                r_end = len;
            }
            
            r_end = r_start + walkLen;
            if (r_end > my_end) {
                r_end = len;
            }
            
            for (int i = 0; i < walkLen; i++){
                if (subList[curList][l_start] < subList[curList][r_start]) {
                    subList[!curList][headLoc] = subList[curList][l_start];
                    l_start++;
                    headLoc++;
                    //Check if l is now empty
                    if (l_start == l_end) {
                        for (int j = r_start; j < r_end; j++){
                            subList[!curList][headLoc] = 
                                subList[curList][r_start];
                            r_start++;
                            headLoc++;
                    }
                    } 
                }
                else {
                    subList[!curList][headLoc] = subList[curList][r_start];
                    r_start++;
                    //Check if r is now empty
                    if (r_start == r_end) {
                        for (int j = l_start; j < l_end; j++){
                            subList[!curList][headLoc] = 
                                subList[curList][r_start];
                            r_start++;
                            headLoc++;
                        }
                    } 
                }
            }

            l_start = old_l_start + 2*walkLen;
            curList = !curList;
        }
    }
    
    return;

    //subList[blockIdx

    //...otherwise, we use global memory...
    /*
    if ( (subList = cudaMalloc(stepsize*sizeof(float)) != NULL ) {
            //   do some shit.
            
        }    
    */

    //...otherwise, we give up.

}

int main(int argc, char *argv[]){
    
    int len;
    float *h_list;

    if (argc != 2) {
        printf("Invalid argument count.  %s requires exactly 1 argument, \
%d given",
               argv[0], argc);
        return -1;
    }
    
    FILE *fin = fopen(argv[1], "r");
    
    if (fin == NULL){
        printf("Could not open file: %s", argv[1]);
        return -2;
    }

    fscanf(fin, "%d", &len);

    h_list = (float *)malloc(len*sizeof(float));
    if (h_list == NULL){
        printf("Insufficient host memory to allocate at %d", __LINE__);
        return -3;
    }

    for (int i = 0; i < len; i++){
        fscanf(fin, "%f ", &h_list[i]);
    }

    for (int i = 0; i < len; i++){
        printf("%f\n", h_list[i]);
    }

    MergeSort(h_list, len, 8, 512);

    return 0;
}

	.text
	.file	"mergesort.hip"
	.globl	_Z9MergeSortPfiii               # -- Begin function _Z9MergeSortPfiii
	.type	_Z9MergeSortPfiii,@function
_Z9MergeSortPfiii:                      # @_Z9MergeSortPfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r12d
	movl	%edx, %r15d
	movl	%esi, %ebp
	movq	%rdi, %r14
	movslq	%esi, %rbx
	shlq	$2, %rbx
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	cmpl	$2, %eax
	jne	.LBB0_2
# %bb.1:
	movl	$.L.str, %edi
	movl	$22, %esi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB0_5
.LBB0_2:
	movq	8(%rsp), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r12d, %edi
	btsq	$32, %rdi
	movl	%r15d, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	cvtsi2ss	%ebp, %xmm0
	imull	%r15d, %r12d
	cvtsi2ss	%r12d, %xmm1
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %eax
	movl	$2000, %ecx                     # imm = 0x7D0
	cmpl	%ecx, %eax
	cmovll	%eax, %ecx
	cltd
	idivl	%r15d
	movq	8(%rsp), %rdi
	movl	%ebp, %esi
	movl	%ecx, %edx
	movl	%eax, %ecx
	callq	_Z23__device_stub__GPUMergePfiii
.LBB0_4:
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
.LBB0_5:
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z9MergeSortPfiii, .Lfunc_end0-_Z9MergeSortPfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__GPUMergePfiii # -- Begin function _Z23__device_stub__GPUMergePfiii
	.type	_Z23__device_stub__GPUMergePfiii,@function
_Z23__device_stub__GPUMergePfiii:       # @_Z23__device_stub__GPUMergePfiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8GPUMergePfiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__GPUMergePfiii, .Lfunc_end1-_Z23__device_stub__GPUMergePfiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	cmpl	$2, %edi
	jne	.LBB2_1
# %bb.2:
	movq	8(%rbx), %rdi
	movl	$.L.str.2, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB2_3
# %bb.4:
	movq	%rax, %r14
	leaq	12(%rsp), %rbx
	movl	$.L.str.4, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	(%rbx), %r15
	leaq	(,%r15,4), %rdi
	callq	malloc
	testq	%rax, %rax
	je	.LBB2_12
# %bb.5:                                # %.preheader24
	movq	%rax, %rbx
	testl	%r15d, %r15d
	jle	.LBB2_11
# %bb.6:                                # %.lr.ph.preheader
	movq	%rbx, %r12
	xorl	%r13d, %r13d
.LBB2_7:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.6, %esi
	movq	%r14, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incq	%r13
	movslq	12(%rsp), %r15
	addq	$4, %r12
	cmpq	%r15, %r13
	jl	.LBB2_7
# %bb.8:                                # %.preheader
	testl	%r15d, %r15d
	jle	.LBB2_11
# %bb.9:                                # %.lr.ph27.preheader
	xorl	%r14d, %r14d
.LBB2_10:                               # %.lr.ph27
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r14,4), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	movslq	12(%rsp), %r15
	cmpq	%r15, %r14
	jl	.LBB2_10
.LBB2_11:                               # %._crit_edge
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	$8, %edx
	movl	$512, %ecx                      # imm = 0x200
	callq	_Z9MergeSortPfiii
	xorl	%eax, %eax
	jmp	.LBB2_13
.LBB2_1:
	movl	%edi, %edx
	movq	(%rbx), %rsi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %eax
	jmp	.LBB2_13
.LBB2_3:
	movq	8(%rbx), %rsi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$-2, %eax
	jmp	.LBB2_13
.LBB2_12:
	movl	$.L.str.5, %edi
	movl	$179, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$-3, %eax
.LBB2_13:
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8GPUMergePfiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error:  Insufficient device memory at line %d\n"
	.size	.L.str, 47

	.type	_Z8GPUMergePfiii,@object        # @_Z8GPUMergePfiii
	.section	.rodata,"a",@progbits
	.globl	_Z8GPUMergePfiii
	.p2align	3, 0x0
_Z8GPUMergePfiii:
	.quad	_Z23__device_stub__GPUMergePfiii
	.size	_Z8GPUMergePfiii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Invalid argument count.  %s requires exactly 1 argument, %d given"
	.size	.L.str.1, 66

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"r"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Could not open file: %s"
	.size	.L.str.3, 24

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d"
	.size	.L.str.4, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Insufficient host memory to allocate at %d"
	.size	.L.str.5, 43

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%f "
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%f\n"
	.size	.L.str.7, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8GPUMergePfiii"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__GPUMergePfiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8GPUMergePfiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8GPUMergePfiii        ; -- Begin function _Z8GPUMergePfiii
	.globl	_Z8GPUMergePfiii
	.p2align	8
	.type	_Z8GPUMergePfiii,@function
_Z8GPUMergePfiii:                       ; @_Z8GPUMergePfiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v3, v0, s4
	s_cmp_lt_i32 s4, 1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_5
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x24
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_lo_u32 v4, v0, s4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
	v_lshlrev_b32_e32 v0, 2, v4
	s_mov_b32 s5, s4
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v0, 4, v0
	v_add_nc_u32_e32 v1, 1, v1
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_cmp_lt_i32 s2, 2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_30
; %bb.6:                                ; %.lr.ph149
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s4, v3
	s_mov_b32 s1, 1
                                        ; implicit-def: $vgpr2
.LBB0_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_12 Depth 2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
                                        ;         Child Loop BB0_23 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_9
; %bb.8:                                ; %.._crit_edge142_crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_lshl_b32 s4, s1, 1
	s_mov_b32 s0, 0
	s_branch .LBB0_10
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr4
.LBB0_10:                               ; %Flow209
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_29
; %bb.11:                               ; %.lr.ph141
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_mov_b32_e32 v6, v3
	s_cmp_gt_i32 s1, 0
	s_mov_b32 s6, 0
	s_cselect_b32 s5, -1, 0
	s_lshl_b32 s4, s1, 1
.LBB0_12:                               ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
                                        ;         Child Loop BB0_23 Depth 4
	v_add_nc_u32_e32 v4, s1, v6
	v_cmp_eq_u16_e64 s0, 0, v1
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_27
; %bb.13:                               ; %.lr.ph134
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, v4, v0
	v_cndmask_b32_e64 v7, 0, 1, s0
	s_mov_b32 s7, 0
	v_cndmask_b32_e64 v5, v4, s2, vcc_lo
	v_and_b32_e32 v9, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_u32_u24_e32 v10, 0x1f40, v7
	v_mov_b32_e32 v14, v5
	v_add_nc_u32_e32 v8, s1, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_u32_u24_e32 v11, 0x1f40, v9
	v_or_b32_e32 v12, 4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, v8, v0
	v_cndmask_b32_e64 v8, v8, s2, vcc_lo
	v_lshlrev_b32_e32 v13, 2, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v13, 0x1f40, v9, v13
.LBB0_14:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_12 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_17 Depth 4
                                        ;         Child Loop BB0_23 Depth 4
	v_lshlrev_b32_e32 v15, 2, v6
	v_lshlrev_b32_e32 v16, 2, v14
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u32_u24 v15, 0x1f40, v9, v15
	v_mad_u32_u24 v16, 0x1f40, v9, v16
	ds_load_b32 v17, v15
	ds_load_b32 v18, v16
	v_lshlrev_b32_e32 v15, 2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v16, 0x1f40, v7, v15
                                        ; implicit-def: $vgpr15
	s_waitcnt lgkmcnt(0)
	v_cmpx_nlt_f32_e32 v17, v18
	s_xor_b32 s8, exec_lo, s0
	s_cbranch_execz .LBB0_20
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=3
	v_add_nc_u32_e32 v14, 1, v14
	v_cmp_lt_i32_e64 s0, v6, v5
	ds_store_b32 v16, v18
	v_cmp_eq_u32_e32 vcc_lo, v14, v8
	s_and_b32 s9, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB0_19
; %bb.16:                               ; %.lr.ph121.preheader
                                        ;   in Loop: Header=BB0_14 Depth=3
	v_lshl_add_u32 v15, v2, 2, v10
	v_mov_b32_e32 v16, v13
	s_mov_b32 s9, 0
	s_mov_b32 s10, 0
.LBB0_17:                               ; %.lr.ph121
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_12 Depth=2
                                        ;       Parent Loop BB0_14 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	ds_load_b32 v18, v16
	s_add_i32 s10, s10, 1
	v_add_nc_u32_e32 v16, 4, v16
	v_add_nc_u32_e32 v17, s10, v6
	v_add_nc_u32_e32 v14, s10, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ge_i32_e32 vcc_lo, v17, v5
	v_add_nc_u32_e32 v17, s10, v2
	s_or_b32 s9, vcc_lo, s9
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v15, v18
	v_add_nc_u32_e32 v15, 4, v15
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %Flow
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v2, v17
.LBB0_19:                               ; %Flow202
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v15, v2
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr2
.LBB0_20:                               ; %Flow205
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB0_26
; %bb.21:                               ;   in Loop: Header=BB0_14 Depth=3
	v_add_nc_u32_e32 v6, 1, v6
	v_cmp_lt_i32_e64 s0, v14, v8
	v_add_nc_u32_e32 v15, 1, v2
	ds_store_b32 v16, v17
	v_cmp_eq_u32_e32 vcc_lo, v6, v5
	s_and_b32 s9, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB0_25
; %bb.22:                               ; %.lr.ph126.preheader
                                        ;   in Loop: Header=BB0_14 Depth=3
	v_lshl_add_u32 v6, v14, 2, v11
	v_lshl_add_u32 v2, v2, 2, v12
	s_mov_b32 s9, 0
.LBB0_23:                               ; %.lr.ph126
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_12 Depth=2
                                        ;       Parent Loop BB0_14 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	ds_load_b32 v16, v6
	v_add_nc_u32_e32 v14, 1, v14
	v_add_nc_u32_e32 v15, 1, v15
	v_add_nc_u32_e32 v6, 4, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ge_i32_e32 vcc_lo, v14, v8
	s_or_b32 s9, vcc_lo, s9
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v2, v16
	v_add_nc_u32_e32 v2, 4, v2
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_23
; %bb.24:                               ; %Flow203
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v6, v5
	v_mov_b32_e32 v14, v8
.LBB0_25:                               ; %Flow204
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_26:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v2, v15
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, s1
	s_cbranch_scc0 .LBB0_14
.LBB0_27:                               ; %Flow207
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, s1, v4
	v_cmp_eq_u16_e64 s0, 0, v1
	v_cmp_ge_i32_e32 vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v1, 0, 1, s0
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_12
; %bb.28:                               ; %Flow208
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_29:                               ; %._crit_edge142
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_cmp_ge_i32 s4, s2
	s_mov_b32 s1, s4
	s_cbranch_scc0 .LBB0_7
.LBB0_30:                               ; %._crit_edge150
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8GPUMergePfiii
		.amdhsa_group_segment_fixed_size 16000
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8GPUMergePfiii, .Lfunc_end0-_Z8GPUMergePfiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16000 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16000
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8GPUMergePfiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8GPUMergePfiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
