#include "includes.h"
/*!
* Copyright (c) 2017 Microsoft
* Licensed under The MIT License [see LICENSE for details]
* \file deformable_psroi_pooling.cu
* \brief
* \author Yi Li, Guodong Zhang, Jifeng Dai
*/
/***************** Adapted by Charles Shang *********************/

#define CUDA_KERNEL_LOOP(i, n)                        \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n);                                       \
i += blockDim.x * gridDim.x)

const int CUDA_NUM_THREADS = 1024;
__device__ float bilinear_interp( const float *data, const float x, const float y, const int width, const int height)
{
int x1 = floor(x);
int x2 = ceil(x);
int y1 = floor(y);
int y2 = ceil(y);
float dist_x = (float)(x - x1);
float dist_y = (float)(y - y1);
float value11 = data[y1 * width + x1];
float value12 = data[y2 * width + x1];
float value21 = data[y1 * width + x2];
float value22 = data[y2 * width + x2];
float value = (1 - dist_x) * (1 - dist_y) * value11 + (1 - dist_x) * dist_y * value12 + dist_x * (1 - dist_y) * value21 + dist_x * dist_y * value22;
return value;
}
__device__ double bilinear_interp( const double *data, const double x, const double y, const int width, const int height)
{
int x1 = floor(x);
int x2 = ceil(x);
int y1 = floor(y);
int y2 = ceil(y);
double dist_x = (double)(x - x1);
double dist_y = (double)(y - y1);
double value11 = data[y1 * width + x1];
double value12 = data[y2 * width + x1];
double value21 = data[y1 * width + x2];
double value22 = data[y2 * width + x2];
double value = (1 - dist_x) * (1 - dist_y) * value11 + (1 - dist_x) * dist_y * value12 + dist_x * (1 - dist_y) * value21 + dist_x * dist_y * value22;
return value;
}
__global__ void DeformablePSROIPoolForwardKernel( const int count, const double *bottom_data, const double spatial_scale, const int channels, const int height, const int width, const int pooled_height, const int pooled_width, const double *bottom_rois, const double *bottom_trans, const int no_trans, const double trans_std, const int sample_per_part, const int output_dim, const int group_size, const int part_size, const int num_classes, const int channels_each_class, double *top_data, double *top_count)
{
CUDA_KERNEL_LOOP(index, count)
{
// The output is in order (n, ctop, ph, pw)
int pw = index % pooled_width;
int ph = (index / pooled_width) % pooled_height;
int ctop = (index / pooled_width / pooled_height) % output_dim;
int n = index / pooled_width / pooled_height / output_dim;

// [start, end) interval for spatial sampling
const double *offset_bottom_rois = bottom_rois + n * 5;
int roi_batch_ind = offset_bottom_rois[0];
double roi_start_w = (double)(round(offset_bottom_rois[1])) * spatial_scale - 0.5;
double roi_start_h = (double)(round(offset_bottom_rois[2])) * spatial_scale - 0.5;
double roi_end_w = (double)(round(offset_bottom_rois[3]) + 1.) * spatial_scale - 0.5;
double roi_end_h = (double)(round(offset_bottom_rois[4]) + 1.) * spatial_scale - 0.5;

// Force too small ROIs to be 1x1
double roi_width = max(roi_end_w - roi_start_w, 0.1); //avoid 0
double roi_height = max(roi_end_h - roi_start_h, 0.1);

// Compute w and h at bottom
double bin_size_h = roi_height / (double)(pooled_height);
double bin_size_w = roi_width / (double)(pooled_width);

double sub_bin_size_h = bin_size_h / (double)(sample_per_part);
double sub_bin_size_w = bin_size_w / (double)(sample_per_part);

int part_h = floor((double)(ph) / pooled_height * part_size);
int part_w = floor((double)(pw) / pooled_width * part_size);
int class_id = ctop / channels_each_class;
double trans_x = no_trans ? (double)(0) : bottom_trans[(((n * num_classes + class_id) * 2) * part_size + part_h) * part_size + part_w] * trans_std;
double trans_y = no_trans ? (double)(0) : bottom_trans[(((n * num_classes + class_id) * 2 + 1) * part_size + part_h) * part_size + part_w] * trans_std;

double wstart = (double)(pw)*bin_size_w + roi_start_w;
wstart += trans_x * roi_width;
double hstart = (double)(ph)*bin_size_h + roi_start_h;
hstart += trans_y * roi_height;

double sum = 0;
int count = 0;
int gw = floor((double)(pw)*group_size / pooled_width);
int gh = floor((double)(ph)*group_size / pooled_height);
gw = min(max(gw, 0), group_size - 1);
gh = min(max(gh, 0), group_size - 1);

const double *offset_bottom_data = bottom_data + (roi_batch_ind * channels) * height * width;
for (int ih = 0; ih < sample_per_part; ih++)
{
for (int iw = 0; iw < sample_per_part; iw++)
{
double w = wstart + iw * sub_bin_size_w;
double h = hstart + ih * sub_bin_size_h;
// bilinear interpolation
if (w < -0.5 || w > width - 0.5 || h < -0.5 || h > height - 0.5)
{
continue;
}
w = min(max(w, 0.), width - 1.);
h = min(max(h, 0.), height - 1.);
int c = (ctop * group_size + gh) * group_size + gw;
double val = bilinear_interp(offset_bottom_data + c * height * width, w, h, width, height);
sum += val;
count++;
}
}
top_data[index] = count == 0 ? (double)(0) : sum / count;
top_count[index] = count;
}
}
	.file	"tmpxft_0037b8b1_00000000-6_DeformablePSROIPoolForwardKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15bilinear_interpPKfffii
	.type	_Z15bilinear_interpPKfffii, @function
_Z15bilinear_interpPKfffii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z15bilinear_interpPKfffii, .-_Z15bilinear_interpPKfffii
	.globl	_Z15bilinear_interpPKdddii
	.type	_Z15bilinear_interpPKdddii, @function
_Z15bilinear_interpPKdddii:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z15bilinear_interpPKdddii, .-_Z15bilinear_interpPKdddii
	.globl	_Z79__device_stub__Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_iPKddiiiiiS0_S0_idiiiiiiPdS1_
	.type	_Z79__device_stub__Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_iPKddiiiiiS0_S0_idiiiiiiPdS1_, @function
_Z79__device_stub__Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_iPKddiiiiiS0_S0_idiiiiiiPdS1_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	344(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	352(%rsp), %rax
	movl	%edx, 72(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	416(%rsp), %rax
	movl	%ecx, 52(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	424(%rsp), %rax
	movl	%r8d, 48(%rsp)
	movl	%r9d, 44(%rsp)
	movq	%rax, (%rsp)
	movsd	%xmm0, 56(%rsp)
	movsd	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	%rsp, %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	96(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 352
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L6:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z79__device_stub__Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_iPKddiiiiiS0_S0_idiiiiiiPdS1_, .-_Z79__device_stub__Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_iPKddiiiiiS0_S0_idiiiiiiPdS1_
	.globl	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.type	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, @function
_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_iPKddiiiiiS0_S0_idiiiiiiPdS1_
	.cfi_endproc
.LFE2035:
	.size	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, .-_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/*!
* Copyright (c) 2017 Microsoft
* Licensed under The MIT License [see LICENSE for details]
* \file deformable_psroi_pooling.cu
* \brief
* \author Yi Li, Guodong Zhang, Jifeng Dai
*/
/***************** Adapted by Charles Shang *********************/

#define CUDA_KERNEL_LOOP(i, n)                        \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n);                                       \
i += blockDim.x * gridDim.x)

const int CUDA_NUM_THREADS = 1024;
__device__ float bilinear_interp( const float *data, const float x, const float y, const int width, const int height)
{
int x1 = floor(x);
int x2 = ceil(x);
int y1 = floor(y);
int y2 = ceil(y);
float dist_x = (float)(x - x1);
float dist_y = (float)(y - y1);
float value11 = data[y1 * width + x1];
float value12 = data[y2 * width + x1];
float value21 = data[y1 * width + x2];
float value22 = data[y2 * width + x2];
float value = (1 - dist_x) * (1 - dist_y) * value11 + (1 - dist_x) * dist_y * value12 + dist_x * (1 - dist_y) * value21 + dist_x * dist_y * value22;
return value;
}
__device__ double bilinear_interp( const double *data, const double x, const double y, const int width, const int height)
{
int x1 = floor(x);
int x2 = ceil(x);
int y1 = floor(y);
int y2 = ceil(y);
double dist_x = (double)(x - x1);
double dist_y = (double)(y - y1);
double value11 = data[y1 * width + x1];
double value12 = data[y2 * width + x1];
double value21 = data[y1 * width + x2];
double value22 = data[y2 * width + x2];
double value = (1 - dist_x) * (1 - dist_y) * value11 + (1 - dist_x) * dist_y * value12 + dist_x * (1 - dist_y) * value21 + dist_x * dist_y * value22;
return value;
}
__global__ void DeformablePSROIPoolForwardKernel( const int count, const double *bottom_data, const double spatial_scale, const int channels, const int height, const int width, const int pooled_height, const int pooled_width, const double *bottom_rois, const double *bottom_trans, const int no_trans, const double trans_std, const int sample_per_part, const int output_dim, const int group_size, const int part_size, const int num_classes, const int channels_each_class, double *top_data, double *top_count)
{
CUDA_KERNEL_LOOP(index, count)
{
// The output is in order (n, ctop, ph, pw)
int pw = index % pooled_width;
int ph = (index / pooled_width) % pooled_height;
int ctop = (index / pooled_width / pooled_height) % output_dim;
int n = index / pooled_width / pooled_height / output_dim;

// [start, end) interval for spatial sampling
const double *offset_bottom_rois = bottom_rois + n * 5;
int roi_batch_ind = offset_bottom_rois[0];
double roi_start_w = (double)(round(offset_bottom_rois[1])) * spatial_scale - 0.5;
double roi_start_h = (double)(round(offset_bottom_rois[2])) * spatial_scale - 0.5;
double roi_end_w = (double)(round(offset_bottom_rois[3]) + 1.) * spatial_scale - 0.5;
double roi_end_h = (double)(round(offset_bottom_rois[4]) + 1.) * spatial_scale - 0.5;

// Force too small ROIs to be 1x1
double roi_width = max(roi_end_w - roi_start_w, 0.1); //avoid 0
double roi_height = max(roi_end_h - roi_start_h, 0.1);

// Compute w and h at bottom
double bin_size_h = roi_height / (double)(pooled_height);
double bin_size_w = roi_width / (double)(pooled_width);

double sub_bin_size_h = bin_size_h / (double)(sample_per_part);
double sub_bin_size_w = bin_size_w / (double)(sample_per_part);

int part_h = floor((double)(ph) / pooled_height * part_size);
int part_w = floor((double)(pw) / pooled_width * part_size);
int class_id = ctop / channels_each_class;
double trans_x = no_trans ? (double)(0) : bottom_trans[(((n * num_classes + class_id) * 2) * part_size + part_h) * part_size + part_w] * trans_std;
double trans_y = no_trans ? (double)(0) : bottom_trans[(((n * num_classes + class_id) * 2 + 1) * part_size + part_h) * part_size + part_w] * trans_std;

double wstart = (double)(pw)*bin_size_w + roi_start_w;
wstart += trans_x * roi_width;
double hstart = (double)(ph)*bin_size_h + roi_start_h;
hstart += trans_y * roi_height;

double sum = 0;
int count = 0;
int gw = floor((double)(pw)*group_size / pooled_width);
int gh = floor((double)(ph)*group_size / pooled_height);
gw = min(max(gw, 0), group_size - 1);
gh = min(max(gh, 0), group_size - 1);

const double *offset_bottom_data = bottom_data + (roi_batch_ind * channels) * height * width;
for (int ih = 0; ih < sample_per_part; ih++)
{
for (int iw = 0; iw < sample_per_part; iw++)
{
double w = wstart + iw * sub_bin_size_w;
double h = hstart + ih * sub_bin_size_h;
// bilinear interpolation
if (w < -0.5 || w > width - 0.5 || h < -0.5 || h > height - 0.5)
{
continue;
}
w = min(max(w, 0.), width - 1.);
h = min(max(h, 0.), height - 1.);
int c = (ctop * group_size + gh) * group_size + gw;
double val = bilinear_interp(offset_bottom_data + c * height * width, w, h, width, height);
sum += val;
count++;
}
}
top_data[index] = count == 0 ? (double)(0) : sum / count;
top_count[index] = count;
}
}
	.text
	.file	"DeformablePSROIPoolForwardKernel.hip"
	.globl	_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_ # -- Begin function _Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.type	_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_,@function
_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_: # @_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movsd	%xmm0, (%rsi)
	leaq	16(%rsp), %r10
	movl	%edx, (%r10)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm1, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, .Lfunc_end0-_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_,@object # @_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.section	.rodata,"a",@progbits
	.globl	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.p2align	3, 0x0
_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_:
	.quad	_Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.size	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_"
	.size	.L__unnamed_1, 66

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z47__device_stub__DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_ ; -- Begin function _Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.globl	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
	.p2align	8
	.type	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_,@function
_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_: ; @_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x84
	s_load_b32 s30, s[0:1], 0x0
	s_add_u32 s2, s0, 0x78
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s44, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[8:9], null, s15, s44, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s30, v8
	s_cbranch_execz .LBB0_15
; %bb.1:                                ; %.lr.ph166
	s_clause 0x6
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s20, s[0:1], 0x40
	s_load_b128 s[12:15], s[0:1], 0x50
	s_load_b32 s31, s[0:1], 0x28
	s_load_b64 s[24:25], s[0:1], 0x60
	s_load_b128 s[16:19], s[0:1], 0x30
	s_load_b64 s[26:27], s[0:1], 0x48
	s_mov_b32 s28, 0x9999999a
	s_mov_b32 s29, 0x3fb99999
	v_mov_b32_e32 v28, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[0:1], s10
	v_cvt_f64_i32_e32 v[2:3], s9
	s_cmp_eq_u32 s20, 0
	v_cvt_f64_i32_e32 v[10:11], s11
	s_cselect_b32 s33, -1, 0
	s_lshl_b32 s34, s15, 1
	s_add_i32 s35, s14, -1
	s_cmp_gt_i32 s12, 0
	v_cvt_f64_i32_e32 v[12:13], s31
	s_cselect_b32 s36, -1, 0
	s_ashr_i32 s37, s31, 31
	s_ashr_i32 s38, s11, 31
	s_add_i32 s20, s31, s37
	s_ashr_i32 s39, s13, 31
	s_ashr_i32 s40, s25, 31
	s_add_i32 s21, s11, s38
	s_xor_b32 s41, s20, s37
	s_xor_b32 s42, s21, s38
	v_cvt_f32_u32_e32 v4, s41
	s_add_i32 s20, s13, s39
	s_add_i32 s21, s25, s40
	v_cvt_f32_u32_e32 v5, s42
	s_xor_b32 s25, s20, s39
	s_xor_b32 s43, s21, s40
	v_cvt_f32_u32_e32 v6, s25
	v_cvt_f32_u32_e32 v7, s43
	v_rcp_iflag_f32_e32 v4, v4
	v_rcp_iflag_f32_e32 v5, v5
	v_cvt_f64_i32_e32 v[14:15], s12
	v_rcp_iflag_f32_e32 v6, v6
	v_rcp_iflag_f32_e32 v7, v7
	v_cvt_f64_i32_e32 v[16:17], s15
	v_cvt_f64_i32_e32 v[18:19], s14
	s_sub_i32 s20, 0, s41
	s_sub_i32 s21, 0, s43
	s_delay_alu instid0(TRANS32_DEP_3)
	v_dual_mul_f32 v4, 0x4f7ffffe, v4 :: v_dual_mul_f32 v5, 0x4f7ffffe, v5
	v_add_f64 v[20:21], v[0:1], -0.5
	v_add_f64 v[22:23], v[2:3], -0.5
	v_add_f64 v[24:25], v[0:1], -1.0
	v_add_f64 v[26:27], v[2:3], -1.0
	v_dual_mul_f32 v1, 0x4f7ffffe, v6 :: v_dual_mul_f32 v2, 0x4f7ffffe, v7
	v_cvt_u32_f32_e32 v0, v4
	v_cvt_u32_f32_e32 v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v4, s20, v0
	s_sub_i32 s20, 0, s42
	v_mul_lo_u32 v5, s20, v3
	s_sub_i32 s20, 0, s25
	v_mul_lo_u32 v7, s21, v2
	v_mul_lo_u32 v6, s20, v1
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[20:23], s[0:1], 0x68
	v_mul_hi_u32 v4, v0, v4
	s_mul_i32 s3, s10, s9
	s_mov_b32 s9, 0
	v_mul_hi_u32 v5, v3, v5
	s_mul_i32 s8, s3, s8
	v_mul_hi_u32 v7, v2, v7
	v_mul_hi_u32 v6, v1, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v43, v0, v4
	v_add_nc_u32_e32 v44, v3, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v46, v2, v7
	v_add_nc_u32_e32 v45, v1, v6
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s44, s2, s44
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;       Child Loop BB0_9 Depth 3
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v8, v9
	v_xor_b32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v43
	v_mul_lo_u32 v2, v1, s41
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v2
	v_add_nc_u32_e32 v2, 1, v1
	v_subrev_nc_u32_e32 v3, s41, v0
	v_cmp_le_u32_e32 vcc_lo, s41, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v2 :: v_dual_cndmask_b32 v0, v0, v3
	v_xor_b32_e32 v3, s37, v9
	v_add_nc_u32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s41, v0
	v_cndmask_b32_e32 v0, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v3
	v_sub_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v2, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v1
	v_xor_b32_e32 v1, s38, v1
	v_mul_hi_u32 v3, v2, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s42
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s42, v2
	v_cmp_le_u32_e32 vcc_lo, s42, v2
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s42, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v3, v4, vcc_lo
	v_xor_b32_e32 v2, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v29, v2, v1
	v_mul_lo_u32 v2, v0, s31
	v_mul_lo_u32 v1, v29, s11
	v_ashrrev_i32_e32 v38, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v39, v29, v38
	v_sub_nc_u32_e32 v0, v0, v1
	v_sub_nc_u32_e32 v1, v8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v39, v39, v38
	v_cvt_f64_i32_e32 v[30:31], v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[32:33], v1
	v_mul_hi_u32 v42, v39, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v47, v42, s25
	v_div_scale_f64 v[34:35], null, v[10:11], v[10:11], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[32:33]
	v_rcp_f64_e32 v[0:1], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[2:3], v[36:37]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[4:5], -v[34:35], v[0:1], 1.0
	v_fma_f64 v[6:7], -v[36:37], v[2:3], 1.0
	v_fma_f64 v[40:41], v[0:1], v[4:5], v[0:1]
	v_sub_nc_u32_e32 v0, v39, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[48:49], v[2:3], v[6:7], v[2:3]
	v_add_nc_u32_e32 v1, 1, v42
	v_xor_b32_e32 v3, s39, v38
	v_subrev_nc_u32_e32 v2, s25, v0
	v_cmp_le_u32_e32 vcc_lo, s25, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v42, v1 :: v_dual_cndmask_b32 v0, v0, v2
	v_add_nc_u32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s25, v0
	v_cndmask_b32_e32 v0, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v3
	v_sub_nc_u32_e32 v47, v0, v3
	v_fma_f64 v[50:51], -v[34:35], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, v47, 2, v47
	v_fma_f64 v[52:53], -v[36:37], v[48:49], 1.0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	s_clause 0x2
	global_load_b64 v[38:39], v[0:1], off offset:32
	global_load_b128 v[4:7], v[0:1], off offset:16
	global_load_b128 v[0:3], v[0:1], off
	v_div_scale_f64 v[54:55], vcc_lo, v[30:31], v[10:11], v[30:31]
	v_fma_f64 v[40:41], v[40:41], v[50:51], v[40:41]
	v_div_scale_f64 v[50:51], s0, v[32:33], v[12:13], v[32:33]
	v_fma_f64 v[48:49], v[48:49], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[52:53], v[54:55], v[40:41]
	v_mul_f64 v[56:57], v[50:51], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], -v[34:35], v[52:53], v[54:55]
	v_fma_f64 v[36:37], -v[36:37], v[56:57], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[34:35], v[34:35], v[40:41], v[52:53]
	s_mov_b32 vcc_lo, s0
	v_mul_lo_u32 v40, v47, s13
	v_div_fmas_f64 v[36:37], v[36:37], v[48:49], v[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v42, v29, v40
	v_ashrrev_i32_e32 v41, 31, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v42, v41
	v_xor_b32_e32 v48, v29, v41
	v_xor_b32_e32 v41, s40, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v49, v48, v46
	v_mul_lo_u32 v50, v49, s43
	v_div_fixup_f64 v[34:35], v[34:35], v[10:11], v[30:31]
	v_div_fixup_f64 v[36:37], v[36:37], v[12:13], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[34:35], v[34:35], v[16:17]
	v_mul_f64 v[36:37], v[36:37], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f64_e32 v[34:35], v[34:35]
	v_floor_f64_e32 v[36:37], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v40, v[34:35]
	v_add_nc_u32_e32 v35, 1, v49
	v_cvt_i32_f64_e32 v29, v[36:37]
	v_sub_nc_u32_e32 v34, v48, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v36, s43, v34
	v_cmp_le_u32_e32 vcc_lo, s43, v34
	v_dual_cndmask_b32 v35, v49, v35 :: v_dual_cndmask_b32 v34, v34, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v36, 1, v35
	v_cmp_le_u32_e32 vcc_lo, s43, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v34, v35, v36, vcc_lo
	v_mov_b32_e32 v36, 0
	v_mov_b32_e32 v37, 0
	s_and_not1_b32 vcc_lo, exec_lo, s33
	v_xor_b32_e32 v34, v34, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v41, v34, v41
	v_dual_mov_b32 v34, v36 :: v_dual_mov_b32 v35, v37
	s_cbranch_vccnz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, v47, s24, v[41:42]
	v_mad_u64_u32 v[48:49], null, s34, v34, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, v48, s15, v[29:30]
	v_ashrrev_i32_e32 v35, 31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[34:35], 3, v[34:35]
	v_add_co_u32 v34, vcc_lo, s18, v34
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v35, vcc_lo, s19, v35, vcc_lo
	global_load_b64 v[34:35], v[34:35], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[34:35], v[34:35], s[26:27]
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[36:37], null, v47, s24, v[41:42]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v41, v36, 1, 1
	v_mad_u64_u32 v[36:37], null, v41, s15, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[40:41], null, v36, s15, v[29:30]
	v_ashrrev_i32_e32 v41, 31, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[36:37], 3, v[40:41]
	v_add_co_u32 v36, vcc_lo, s18, v36
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v37, vcc_lo, s19, v37, vcc_lo
	global_load_b64 v[36:37], v[36:37], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[36:37], v[36:37], s[26:27]
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s36
	s_cbranch_vccnz .LBB0_13
; %bb.7:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_trunc_f64_e32 v[40:41], v[2:3]
	v_trunc_f64_e32 v[47:48], v[4:5]
	v_trunc_f64_e32 v[49:50], v[6:7]
	v_trunc_f64_e32 v[51:52], v[38:39]
	s_mov_b32 s45, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[53:54], v[2:3], -v[40:41]
	v_add_f64 v[55:56], v[4:5], -v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[57:58], v[6:7], -v[49:50]
	v_add_f64 v[59:60], v[38:39], -v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f64_e64 s0, |v[53:54]|, 0.5
	v_cndmask_b32_e64 v2, 0, 0x3ff00000, s0
	v_cmp_ge_f64_e64 s0, |v[55:56]|, 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v29, 0x7fffffff, v2, v3
	v_add_f64 v[2:3], v[40:41], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 0, 0x3ff00000, s0
	v_cmp_ge_f64_e64 s0, |v[57:58]|, 0.5
	v_bfi_b32 v29, 0x7fffffff, v4, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[2:3], s[6:7], -0.5
	v_add_f64 v[4:5], v[47:48], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, 0, 0x3ff00000, s0
	v_cmp_ge_f64_e64 s0, |v[59:60]|, 0.5
	v_bfi_b32 v29, 0x7fffffff, v6, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[4:5], s[6:7], -0.5
	v_add_f64 v[6:7], v[49:50], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v38, 0, 0x3ff00000, s0
	v_bfi_b32 v29, 0x7fffffff, v38, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], 1.0
	v_add_f64 v[38:39], v[51:52], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[6:7], s[6:7], -0.5
	v_add_f64 v[38:39], v[38:39], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[2:3]
	v_fma_f64 v[38:39], v[38:39], s[6:7], -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f64 v[6:7], v[6:7], s[28:29]
	v_add_f64 v[38:39], v[38:39], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[47:48], null, v[12:13], v[12:13], v[6:7]
	v_max_f64 v[38:39], v[38:39], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[51:52], v[47:48]
	v_div_scale_f64 v[40:41], null, v[10:11], v[10:11], v[38:39]
	v_div_scale_f64 v[57:58], vcc_lo, v[38:39], v[10:11], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[49:50], v[40:41]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[55:56], -v[47:48], v[51:52], 1.0
	v_fma_f64 v[51:52], v[51:52], v[55:56], v[51:52]
	v_fma_f64 v[53:54], -v[40:41], v[49:50], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[55:56], -v[47:48], v[51:52], 1.0
	v_fma_f64 v[49:50], v[49:50], v[53:54], v[49:50]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[51:52], v[51:52], v[55:56], v[51:52]
	v_fma_f64 v[53:54], -v[40:41], v[49:50], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[49:50], v[49:50], v[53:54], v[49:50]
	v_div_scale_f64 v[53:54], s0, v[6:7], v[12:13], v[6:7]
	v_mul_f64 v[55:56], v[57:58], v[49:50]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[59:60], v[53:54], v[51:52]
	v_fma_f64 v[40:41], -v[40:41], v[55:56], v[57:58]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[47:48], -v[47:48], v[59:60], v[53:54]
	v_div_fmas_f64 v[40:41], v[40:41], v[49:50], v[55:56]
	s_mov_b32 vcc_lo, s0
	v_mul_f64 v[49:50], v[18:19], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[47:48], v[47:48], v[51:52], v[59:60]
	v_mul_f64 v[51:52], v[18:19], v[32:33]
	v_div_fixup_f64 v[40:41], v[40:41], v[10:11], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[57:58], null, v[10:11], v[10:11], v[49:50]
	v_div_fixup_f64 v[47:48], v[47:48], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[59:60], null, v[12:13], v[12:13], v[51:52]
	v_div_scale_f64 v[53:54], null, v[14:15], v[14:15], v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_rcp_f64_e32 v[65:66], v[57:58]
	v_div_scale_f64 v[77:78], vcc_lo, v[40:41], v[14:15], v[40:41]
	v_div_scale_f64 v[55:56], null, v[14:15], v[14:15], v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[67:68], v[59:60]
	v_fma_f64 v[4:5], v[40:41], v[30:31], v[4:5]
	v_fma_f64 v[2:3], v[47:48], v[32:33], v[2:3]
	v_cvt_i32_f64_e32 v33, v[0:1]
	v_rcp_f64_e32 v[61:62], v[53:54]
	v_fma_f64 v[73:74], -v[57:58], v[65:66], 1.0
	v_rcp_f64_e32 v[63:64], v[55:56]
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[75:76], -v[59:60], v[67:68], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[69:70], -v[53:54], v[61:62], 1.0
	v_fma_f64 v[65:66], v[65:66], v[73:74], v[65:66]
	v_fma_f64 v[71:72], -v[55:56], v[63:64], 1.0
	v_fma_f64 v[67:68], v[67:68], v[75:76], v[67:68]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[61:62], v[61:62], v[69:70], v[61:62]
	v_fma_f64 v[73:74], -v[57:58], v[65:66], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[63:64], v[63:64], v[71:72], v[63:64]
	v_fma_f64 v[75:76], -v[59:60], v[67:68], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[69:70], -v[53:54], v[61:62], 1.0
	v_fma_f64 v[65:66], v[65:66], v[73:74], v[65:66]
	v_div_scale_f64 v[73:74], s2, v[51:52], v[12:13], v[51:52]
	v_fma_f64 v[71:72], -v[55:56], v[63:64], 1.0
	v_fma_f64 v[67:68], v[67:68], v[75:76], v[67:68]
	v_fma_f64 v[61:62], v[61:62], v[69:70], v[61:62]
	v_div_scale_f64 v[69:70], s0, v[47:48], v[14:15], v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[63:64], v[63:64], v[71:72], v[63:64]
	v_div_scale_f64 v[71:72], s1, v[49:50], v[10:11], v[49:50]
	v_mul_f64 v[83:84], v[73:74], v[67:68]
	v_mul_f64 v[75:76], v[77:78], v[61:62]
	v_mul_f64 v[79:80], v[69:70], v[63:64]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[81:82], v[71:72], v[65:66]
	v_fma_f64 v[59:60], -v[59:60], v[83:84], v[73:74]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[53:54], -v[53:54], v[75:76], v[77:78]
	v_fma_f64 v[55:56], -v[55:56], v[79:80], v[69:70]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[57:58], -v[57:58], v[81:82], v[71:72]
	v_div_fmas_f64 v[53:54], v[53:54], v[61:62], v[75:76]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[55:56], v[55:56], v[63:64], v[79:80]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[57:58], v[57:58], v[65:66], v[81:82]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[59:60], v[59:60], v[67:68], v[83:84]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[49:50], v[57:58], v[10:11], v[49:50]
	v_div_fixup_f64 v[51:52], v[59:60], v[12:13], v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f64_e32 v[49:50], v[49:50]
	v_floor_f64_e32 v[51:52], v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v29, v[49:50]
	v_cvt_i32_f64_e32 v30, v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_maxmin_i32 v0, v29, 0, s35
	v_mad_u64_u32 v[31:32], null, v42, s14, v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_maxmin_i32 v32, v30, 0, s35
	v_fma_f64 v[0:1], v[38:39], v[36:37], v[4:5]
	v_fma_f64 v[4:5], v[6:7], v[34:35], v[2:3]
	v_div_fixup_f64 v[6:7], v[53:54], v[14:15], v[40:41]
	v_div_fixup_f64 v[29:30], v[55:56], v[14:15], v[47:48]
	v_mov_b32_e32 v47, 0
	v_mad_u64_u32 v[2:3], null, v31, s14, v[32:33]
	v_mul_lo_u32 v31, s8, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s3, v2
	v_ashrrev_i32_e32 v32, 31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[33:34], 3, v[31:32]
	v_ashrrev_i32_e32 v3, 31, v2
	v_mov_b32_e32 v31, 0
	v_mov_b32_e32 v32, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v35, vcc_lo, s4, v33
	v_add_co_ci_u32_e32 v36, vcc_lo, s5, v34, vcc_lo
	v_dual_mov_b32 v34, v32 :: v_dual_mov_b32 v33, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v48, vcc_lo, v35, v2
	v_add_co_ci_u32_e32 v49, vcc_lo, v36, v3, vcc_lo
	v_dual_mov_b32 v2, v31 :: v_dual_mov_b32 v3, v32
.LBB0_8:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_9 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[37:38], v[6:7], v[33:34], v[0:1]
	v_max_f64 v[39:40], v[26:27], v[26:27]
	s_mov_b32 s46, s12
	v_max_f64 v[35:36], v[37:38], 0
	v_cmp_gt_f64_e32 vcc_lo, -0.5, v[37:38]
	v_cmp_gt_f64_e64 s0, v[37:38], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f64 v[35:36], v[35:36], v[39:40]
	v_floor_f64_e32 v[39:40], v[35:36]
	v_ceil_f64_e32 v[41:42], v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v50, v[39:40]
	v_cvt_f64_i32_e32 v[39:40], v50
	v_mul_lo_u32 v50, v50, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[35:36], -v[39:40]
	v_cvt_i32_f64_e32 v39, v[41:42]
	v_add_f64 v[37:38], -v[35:36], 1.0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v51, v39, s10
	v_dual_mov_b32 v40, v32 :: v_dual_mov_b32 v39, v31
.LBB0_9:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_8 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[41:42], v[29:30], v[39:40], v[4:5]
	v_cmp_gt_f64_e64 s1, -0.5, v[41:42]
	v_cmp_gt_f64_e64 s2, v[41:42], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_or_b32 s1, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s0
	s_xor_b32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=3
	v_max_f64 v[41:42], v[41:42], v[41:42]
	v_max_f64 v[52:53], v[24:25], v[24:25]
	v_add_nc_u32_e32 v47, 1, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f64 v[41:42], v[41:42], 0
	v_min_f64 v[41:42], v[41:42], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f64_e32 v[52:53], v[41:42]
	v_cvt_i32_f64_e32 v60, v[52:53]
	v_ceil_f64_e32 v[52:53], v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v54, v51, v60
	v_cvt_i32_f64_e32 v58, v[52:53]
	v_add_nc_u32_e32 v56, v50, v60
	v_cvt_f64_i32_e32 v[60:61], v60
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v55, 31, v54
	v_ashrrev_i32_e32 v57, 31, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 3, v[54:55]
	v_lshlrev_b64 v[52:53], 3, v[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s1, v48, v54
	v_add_co_ci_u32_e64 v55, s1, v49, v55, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v52, s1, v48, v52
	v_add_co_ci_u32_e64 v53, s1, v49, v53, s1
	global_load_b64 v[54:55], v[54:55], off
	v_add_nc_u32_e32 v56, v50, v58
	v_add_nc_u32_e32 v58, v51, v58
	v_add_f64 v[41:42], v[41:42], -v[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v57, 31, v56
	v_ashrrev_i32_e32 v59, 31, v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[56:57], 3, v[56:57]
	v_lshlrev_b64 v[58:59], 3, v[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s1, v48, v56
	v_add_co_ci_u32_e64 v57, s1, v49, v57, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v58, s1, v48, v58
	v_add_co_ci_u32_e64 v59, s1, v49, v59, s1
	s_clause 0x2
	global_load_b64 v[56:57], v[56:57], off
	global_load_b64 v[58:59], v[58:59], off
	global_load_b64 v[52:53], v[52:53], off
	v_add_f64 v[60:61], -v[41:42], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f64 v[62:63], v[35:36], v[60:61]
	v_mul_f64 v[60:61], v[37:38], v[60:61]
	s_waitcnt vmcnt(3)
	v_mul_f64 v[54:55], v[62:63], v[54:55]
	v_mul_f64 v[62:63], v[37:38], v[41:42]
	v_mul_f64 v[41:42], v[35:36], v[41:42]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[60:61], v[52:53], v[54:55]
	v_fma_f64 v[52:53], v[62:63], v[56:57], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[41:42], v[41:42], v[58:59], v[52:53]
	v_add_f64 v[2:3], v[2:3], v[41:42]
.LBB0_11:                               ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	v_add_f64 v[39:40], v[39:40], 1.0
	s_add_i32 s46, s46, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s46, 0
	s_cbranch_scc0 .LBB0_9
; %bb.12:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_8 Depth=2
	v_add_f64 v[33:34], v[33:34], 1.0
	s_add_i32 s45, s45, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s45, s12
	s_cbranch_scc0 .LBB0_8
	s_branch .LBB0_14
.LBB0_13:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v47, 0
	v_mov_b32_e32 v3, 0
.LBB0_14:                               ; %._crit_edge161
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[0:1], v47
	v_cmp_ne_u32_e64 s0, 0, v47
	v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3]
	v_div_scale_f64 v[31:32], vcc_lo, v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[29:30], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[29:30], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[29:30], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[29:30], v[31:32], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[29:30], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[29:30]
	v_div_fixup_f64 v[2:3], v[4:5], v[0:1], v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[8:9]
	v_add_nc_u32_e32 v8, s44, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s30, v8
	v_add_co_u32 v6, s1, s20, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s1, s21, v5, s1
	s_or_b32 s9, vcc_lo, s9
	v_cndmask_b32_e64 v3, 0, v3, s0
	v_cndmask_b32_e64 v2, 0, v2, s0
	v_add_co_u32 v4, s0, s22, v4
	v_add_co_ci_u32_e64 v5, s0, s23, v5, s0
	global_store_b64 v[6:7], v[2:3], off
	global_store_b64 v[4:5], v[0:1], off
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_2
.LBB0_15:                               ; %Flow233
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 85
		.amdhsa_next_free_sgpr 47
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_, .Lfunc_end0-_Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3560
; NumSgprs: 49
; NumVgprs: 85
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 49
; NumVGPRsForWavesPerEU: 85
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         124
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         132
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         134
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         136
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         138
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         140
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         142
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         184
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 376
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_
    .private_segment_fixed_size: 0
    .sgpr_count:     49
    .sgpr_spill_count: 0
    .symbol:         _Z32DeformablePSROIPoolForwardKerneliPKddiiiiiS0_S0_idiiiiiiPdS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     85
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
