﻿#include <cuda.h>

#define KERNEL_SIZE 3
#define BLOCK_SIZE  512

typedef signed int pixel_channel;
typedef unsigned long resolution;

__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = 		{ -1, -1, -1,
								  -1,  9, -1, 
								  -1, -1, -1 };


__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
    __shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];

    for(long line = 1; line < lineQuantity; line++)
    {
        long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;

        sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
        sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
        sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];

        if(threadIdx.x == 0)
        {
			if(blockIdx.x != 0)
				temp--;
            sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
            sharedMemory [1][0] = channel_cuda[temp + width * line];
            sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
        }

        if(threadIdx.x == (BLOCK_SIZE - 1))
        {
            temp++;
            sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
            sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
            sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
        }
        __syncthreads();

        long Sum = 0;

        for (int i = 0; i < KERNEL_SIZE; i++)
            for (int j = 0; j < KERNEL_SIZE; j++)
                Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];

        if (Sum < 0)
            Sum = 0;
        if (Sum > 255)
            Sum = 255;

		__syncthreads();
		
		if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
			continue;
        
		rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
    }
	__syncthreads();

    return;
}

extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
    pixel_channel **channel_cuda;
    channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));

    pixel_channel **rezult_cuda;
    rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));

    resolution size = width * height;

    cudaHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
    cudaHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
    cudaHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);

    cudaMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
    cudaMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
    cudaMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));

    cudaMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
    cudaMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
    cudaMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));

    cudaMemcpyToSymbol(kernel_cuda, kernel_host, 9 * sizeof(pixel_channel), 0, cudaMemcpyHostToDevice);

    resolution block_count = 0;
    if(((width - 2)%BLOCK_SIZE) == 0)
        block_count = (width - 2)/BLOCK_SIZE;
    else
        block_count = (width - 2)/BLOCK_SIZE + 1;

    dim3 gridSize = dim3(block_count, 1, 1);
    dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);

    cudaStream_t stream[3];

    for(int i = 0; i < 3; i++)
    {
	cudaStreamCreate(&stream[i]);
        cudaMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), cudaMemcpyHostToDevice, stream[i]);
        Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
        cudaMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), cudaMemcpyDeviceToHost,stream[i]);
	cudaStreamDestroy(stream[i]);
    }

    for(int i=0;i<3;i++)
    {
        cudaFree(rezult_cuda[i]);
        cudaFree(channel_cuda[i]);
    }

    cudaDeviceReset();

    return image;
}

	.file	"tmpxft_0034e5aa_00000000-6_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
	.type	_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm, @function
_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24Pixel_Shared_ConvolutionPiS_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm, .-_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
	.globl	_Z24Pixel_Shared_ConvolutionPiS_mm
	.type	_Z24Pixel_Shared_ConvolutionPiS_mm, @function
_Z24Pixel_Shared_ConvolutionPiS_mm:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
	.cfi_endproc
.LFE2034:
	.size	_Z24Pixel_Shared_ConvolutionPiS_mm, .-_Z24Pixel_Shared_ConvolutionPiS_mm
	.globl	asyncConvolution
	.type	asyncConvolution, @function
asyncConvolution:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	movl	$24, %edi
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdx, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$24, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	(%rbx), %rdi
	movl	$2, %edx
	movq	%rax, %r12
	movq	8(%rsp), %rax
	imulq	%r14, %rax
	leaq	2048(,%rax,4), %r13
	movq	%r13, %rsi
	call	cudaHostRegister@PLT
	movq	8(%rbx), %rdi
	movq	%r13, %rsi
	movl	$2, %edx
	call	cudaHostRegister@PLT
	movq	16(%rbx), %rdi
	movl	$2, %edx
	movq	%r13, %rsi
	call	cudaHostRegister@PLT
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	8(%r12), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	16(%r12), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	movq	%rbp, %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	8(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	16(%rbp), %rdi
	call	cudaMalloc@PLT
	xorl	%ecx, %ecx
	movl	$36, %edx
	movl	$1, %r8d
	leaq	kernel_host(%rip), %rsi
	leaq	_ZL11kernel_cuda(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	leaq	-2(%r14), %rax
	movl	$1, 44(%rsp)
	movq	%rax, %rdx
	andl	$511, %eax
	shrq	$9, %rdx
	cmpq	$1, %rax
	movabsq	$4294967297, %rax
	sbbq	$-1, %rdx
	movq	%rax, 28(%rsp)
	addq	$511, %rax
	xorl	%r15d, %r15d
	movq	%rax, 36(%rsp)
	leaq	-2048(%r13), %rax
	leaq	48(%rsp), %r13
	movl	%edx, 24(%rsp)
	movq	%rax, (%rsp)
.L11:
	movq	%r13, %rdi
	call	cudaStreamCreate@PLT
	movq	(%rbx,%r15), %rsi
	movq	0(%rbp,%r15), %rdi
	movl	$1, %ecx
	movq	0(%r13), %r8
	movq	(%rsp), %rdx
	call	cudaMemcpyAsync@PLT
	movl	44(%rsp), %ecx
	movq	0(%r13), %r9
	xorl	%r8d, %r8d
	movq	36(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	(%r12,%r15), %rsi
	movq	0(%rbp,%r15), %rdi
	movq	%r14, %rdx
	movq	8(%rsp), %rcx
	call	_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
.L10:
	movq	(%r12,%r15), %rsi
	movq	(%rbx,%r15), %rdi
	movl	$2, %ecx
	addq	$8, %r15
	movq	0(%r13), %r8
	movq	(%rsp), %rdx
	addq	$8, %r13
	call	cudaMemcpyAsync@PLT
	movq	-8(%r13), %rdi
	call	cudaStreamDestroy@PLT
	cmpq	$24, %r15
	jne	.L11
	xorl	%r13d, %r13d
.L12:
	movq	(%r12,%r13), %rdi
	call	cudaFree@PLT
	movq	0(%rbp,%r13), %rdi
	addq	$8, %r13
	call	cudaFree@PLT
	cmpq	$24, %r13
	jne	.L12
	call	cudaDeviceReset@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	asyncConvolution, .-asyncConvolution
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24Pixel_Shared_ConvolutionPiS_mm"
.LC1:
	.string	"kernel_cuda"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24Pixel_Shared_ConvolutionPiS_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$36, %r9d
	leaq	_ZL11kernel_cuda(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	kernel_host
	.data
	.align 32
	.type	kernel_host, @object
	.size	kernel_host, 36
kernel_host:
	.long	-1
	.long	-1
	.long	-1
	.long	-1
	.long	9
	.long	-1
	.long	-1
	.long	-1
	.long	-1
	.local	_ZL11kernel_cuda
	.comm	_ZL11kernel_cuda,36,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

﻿#include <hip/hip_runtime.h>

#define KERNEL_SIZE 3
#define BLOCK_SIZE  512

typedef signed int pixel_channel;
typedef unsigned long resolution;

__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = 		{ -1, -1, -1,
								  -1,  9, -1, 
								  -1, -1, -1 };


__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
    __shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];

    for(long line = 1; line < lineQuantity; line++)
    {
        long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;

        sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
        sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
        sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];

        if(threadIdx.x == 0)
        {
			if(blockIdx.x != 0)
				temp--;
            sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
            sharedMemory [1][0] = channel_cuda[temp + width * line];
            sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
        }

        if(threadIdx.x == (BLOCK_SIZE - 1))
        {
            temp++;
            sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
            sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
            sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
        }
        __syncthreads();

        long Sum = 0;

        for (int i = 0; i < KERNEL_SIZE; i++)
            for (int j = 0; j < KERNEL_SIZE; j++)
                Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];

        if (Sum < 0)
            Sum = 0;
        if (Sum > 255)
            Sum = 255;

		__syncthreads();
		
		if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
			continue;
        
		rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
    }
	__syncthreads();

    return;
}

extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
    pixel_channel **channel_cuda;
    channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));

    pixel_channel **rezult_cuda;
    rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));

    resolution size = width * height;

    hipHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
    hipHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
    hipHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);

    hipMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
    hipMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
    hipMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));

    hipMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
    hipMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
    hipMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));

    hipMemcpyToSymbol(HIP_SYMBOL(kernel_cuda), kernel_host, 9 * sizeof(pixel_channel), 0, hipMemcpyHostToDevice);

    resolution block_count = 0;
    if(((width - 2)%BLOCK_SIZE) == 0)
        block_count = (width - 2)/BLOCK_SIZE;
    else
        block_count = (width - 2)/BLOCK_SIZE + 1;

    dim3 gridSize = dim3(block_count, 1, 1);
    dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);

    hipStream_t stream[3];

    for(int i = 0; i < 3; i++)
    {
	hipStreamCreate(&stream[i]);
        hipMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), hipMemcpyHostToDevice, stream[i]);
        Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
        hipMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), hipMemcpyDeviceToHost,stream[i]);
	hipStreamDestroy(stream[i]);
    }

    for(int i=0;i<3;i++)
    {
        hipFree(rezult_cuda[i]);
        hipFree(channel_cuda[i]);
    }

    hipDeviceReset();

    return image;
}

	.text
	.file	"cuda.hip"
	.globl	_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm # -- Begin function _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
	.type	_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm,@function
_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm: # @_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24Pixel_Shared_ConvolutionPiS_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm, .Lfunc_end0-_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
	.cfi_endproc
                                        # -- End function
	.globl	asyncConvolution                # -- Begin function asyncConvolution
	.type	asyncConvolution,@function
asyncConvolution:                       # @asyncConvolution
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %rbx
	movq	%rsi, %r13
	movq	%rsi, (%rsp)                    # 8-byte Spill
	movq	%rdi, %rbp
	movabsq	$4294967296, %rax               # imm = 0x100000000
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movl	$24, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$24, %edi
	callq	malloc
	movq	%rax, %r15
	movq	(%rbp), %rdi
	movq	%rbx, 16(%rsp)                  # 8-byte Spill
	imulq	%rbx, %r13
	leaq	2048(,%r13,4), %r12
	shlq	$2, %r13
	movq	%r12, %rsi
	movl	$2, %edx
	callq	hipHostRegister
	movq	8(%rbp), %rdi
	movq	%r12, %rsi
	movl	$2, %edx
	callq	hipHostRegister
	movq	16(%rbp), %rdi
	movq	%r12, %rsi
	movl	$2, %edx
	callq	hipHostRegister
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%r15), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%r15, %rdi
	addq	$16, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%r14), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%r14, %rdi
	addq	$16, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	xorl	%ebx, %ebx
	movl	$kernel_cuda, %edi
	movl	$kernel_host, %esi
	movl	$36, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movq	(%rsp), %rax                    # 8-byte Reload
	leaq	-2(%rax), %rcx
	movl	%ecx, %eax
	andl	$511, %eax                      # imm = 0x1FF
	shrq	$9, %rcx
	cmpq	$1, %rax
	sbbl	$-1, %ecx
	btsq	$32, %rcx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	addq	$512, 8(%rsp)                   # 8-byte Folded Spill
                                        # imm = 0x200
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rbp, %r12
	leaq	(%rsp,%rbx), %rbp
	addq	$32, %rbp
	movq	%rbp, %rdi
	callq	hipStreamCreate
	movq	(%r14,%rbx), %rdi
	movq	(%r12,%rbx), %rsi
	movq	(%rbp), %r8
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%rbp), %r9
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	(%r14,%rbx), %rdi
	movq	(%r15,%rbx), %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movq	16(%rsp), %rcx                  # 8-byte Reload
	callq	_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	movq	(%r12,%rbx), %rdi
	movq	(%r15,%rbx), %rsi
	movq	32(%rsp,%rbx), %r8
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	32(%rsp,%rbx), %rdi
	callq	hipStreamDestroy
	addq	$8, %rbx
	cmpq	$24, %rbx
	movq	%r12, %rbp
	jne	.LBB1_1
# %bb.4:                                # %.preheader.preheader
	xorl	%ebx, %ebx
.LBB1_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	(%r15,%rbx,8), %rdi
	callq	hipFree
	movq	(%r14,%rbx,8), %rdi
	callq	hipFree
	incq	%rbx
	cmpq	$3, %rbx
	jne	.LBB1_5
# %bb.6:
	callq	hipDeviceReset
	movq	%rbp, %rax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	asyncConvolution, .Lfunc_end1-asyncConvolution
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24Pixel_Shared_ConvolutionPiS_mm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$kernel_cuda, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	kernel_cuda,@object             # @kernel_cuda
	.local	kernel_cuda
	.comm	kernel_cuda,36,16
	.type	kernel_host,@object             # @kernel_host
	.data
	.globl	kernel_host
	.p2align	4, 0x0
kernel_host:
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.long	9                               # 0x9
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.size	kernel_host, 36

	.type	_Z24Pixel_Shared_ConvolutionPiS_mm,@object # @_Z24Pixel_Shared_ConvolutionPiS_mm
	.section	.rodata,"a",@progbits
	.globl	_Z24Pixel_Shared_ConvolutionPiS_mm
	.p2align	3, 0x0
_Z24Pixel_Shared_ConvolutionPiS_mm:
	.quad	_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
	.size	_Z24Pixel_Shared_ConvolutionPiS_mm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24Pixel_Shared_ConvolutionPiS_mm"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"kernel_cuda"
	.size	.L__unnamed_2, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym kernel_cuda
	.addrsig_sym kernel_host
	.addrsig_sym _Z24Pixel_Shared_ConvolutionPiS_mm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24Pixel_Shared_ConvolutionPiS_mm ; -- Begin function _Z24Pixel_Shared_ConvolutionPiS_mm
	.globl	_Z24Pixel_Shared_ConvolutionPiS_mm
	.p2align	8
	.type	_Z24Pixel_Shared_ConvolutionPiS_mm,@function
_Z24Pixel_Shared_ConvolutionPiS_mm:     ; @_Z24Pixel_Shared_ConvolutionPiS_mm
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_u64_e64 s0, s[10:11], 2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_13
; %bb.1:                                ; %.lr.ph
	s_cmp_lg_u32 s15, 0
	v_lshl_add_u32 v1, s15, 9, v0
	s_cselect_b32 s0, -1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
	v_cndmask_b32_e64 v3, 0, -1, s0
	v_cndmask_b32_e64 v14, 0, 1, s0
	s_lshl_b64 s[12:13], s[8:9], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_dual_mov_b32 v4, v3 :: v_dual_add_nc_u32 v11, 0x1010, v7
	v_cmp_ge_u64_e64 s1, s[8:9], v[1:2]
	v_add_nc_u32_e32 v10, 0x808, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s4, v5
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v6, vcc_lo
	v_sub_co_u32 v3, s0, v1, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v4, null, 0, 0, s0
	v_add_co_u32 v12, s0, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, v9, v13, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cmp_eq_u32_e64 s0, 0x1ff, v0
	v_add_co_u32 v0, s2, s6, v5
	v_add_co_ci_u32_e64 v14, s2, s7, v6, s2
	s_mov_b64 s[6:7], 1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_8 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s6, -1
	s_addc_u32 s15, s7, -1
	s_mul_i32 s3, s2, s9
	s_mul_hi_u32 s14, s2, s8
	s_mul_i32 s15, s15, s8
	s_add_i32 s3, s14, s3
	s_mul_i32 s14, s6, s9
	s_mul_hi_u32 s16, s6, s8
	s_add_i32 s3, s3, s15
	s_add_i32 s14, s16, s14
	s_mul_i32 s15, s7, s8
	s_mul_i32 s2, s2, s8
	s_add_i32 s15, s14, s15
	s_mul_i32 s14, s6, s8
	s_lshl_b64 s[16:17], s[2:3], 2
	s_lshl_b64 s[14:15], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s2, v8, s14
	v_add_co_ci_u32_e64 v6, s2, s15, v9, s2
	v_add_co_u32 v15, s2, v8, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v16, s2, s17, v9, s2
	v_add_co_u32 v17, s2, v5, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v18, s2, s13, v6, s2
	s_clause 0x2
	global_load_b32 v19, v[5:6], off
	global_load_b32 v15, v[15:16], off
	global_load_b32 v16, v[17:18], off
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	s_waitcnt vmcnt(2)
	ds_store_b32 v10, v19 offset:4
	s_waitcnt vmcnt(1)
	ds_store_b32 v7, v15 offset:4
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v16 offset:4
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v5, s2, v12, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, s15, v13, s2
	v_add_co_u32 v15, s2, v12, s16
	v_add_co_ci_u32_e64 v16, s2, s17, v13, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s2, v5, s12
	v_add_co_ci_u32_e64 v18, s2, s13, v6, s2
	s_clause 0x2
	global_load_b32 v15, v[15:16], off
	global_load_b32 v16, v[5:6], off
	global_load_b32 v17, v[17:18], off
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_waitcnt vmcnt(2)
	ds_store_b32 v2, v15
	s_waitcnt vmcnt(1)
	ds_store_b32 v2, v16 offset:2056
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v17 offset:4112
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s2, s4, v5
	v_add_co_ci_u32_e64 v16, s2, s5, v6, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s2, v15, s14
	v_add_co_ci_u32_e64 v6, s2, s15, v16, s2
	v_add_co_u32 v15, s2, v15, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v16, s2, s17, v16, s2
	v_add_co_u32 v17, s2, v5, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v18, s2, s13, v6, s2
	s_clause 0x2
	global_load_b32 v15, v[15:16], off offset:4
	global_load_b32 v5, v[5:6], off offset:4
	global_load_b32 v6, v[17:18], off offset:4
	s_waitcnt vmcnt(2)
	ds_store_b32 v2, v15 offset:2052
	s_waitcnt vmcnt(1)
	ds_store_b32 v2, v5 offset:4108
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v6 offset:6164
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v5, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v15, v7
	s_mov_b32 s3, 0
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, kernel_cuda@rel32@lo+4
	s_addc_u32 s17, s17, kernel_cuda@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_8 Depth 3
	v_mov_b32_e32 v16, v15
	s_mov_b64 s[18:19], 0
.LBB0_8:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s16, s18
	s_addc_u32 s21, s17, s19
	ds_load_b32 v17, v16
	s_load_b32 s2, s[20:21], 0x0
	v_add_nc_u32_e32 v16, 0x808, v16
	s_add_u32 s18, s18, 4
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s18, 12
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v17, s2, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v5, s2, v5, v17
	v_add_co_ci_u32_e64 v6, s2, v6, v18, s2
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=2
	s_add_i32 s3, s3, 1
	v_add_nc_u32_e32 v15, 4, v15
	s_add_u32 s16, s16, 12
	s_addc_u32 s17, s17, 0
	s_cmp_eq_u32 s3, 3
	s_cbranch_scc0 .LBB0_7
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_lt_i64_e64 s2, 0, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, 0, v6, s2
	v_cndmask_b32_e64 v5, 0, v5, s2
	v_add_co_u32 v15, s2, v0, s14
	v_add_co_ci_u32_e64 v16, s2, s15, v14, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s2, 0xff, v[5:6]
	v_cndmask_b32_e64 v5, 0xff, v5, s2
	global_store_b32 v[15:16], v5, off
.LBB0_12:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[6:7], s[10:11]
	s_cbranch_scc0 .LBB0_2
.LBB0_13:                               ; %._crit_edge
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24Pixel_Shared_ConvolutionPiS_mm
		.amdhsa_group_segment_fixed_size 6168
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24Pixel_Shared_ConvolutionPiS_mm, .Lfunc_end0-_Z24Pixel_Shared_ConvolutionPiS_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1040
; NumSgprs: 24
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 6168 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	kernel_cuda             ; @kernel_cuda
	.type	kernel_cuda,@object
	.section	.bss,"aw",@nobits
	.globl	kernel_cuda
	.p2align	4, 0x0
kernel_cuda:
	.zero	36
	.size	kernel_cuda, 36

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym kernel_cuda
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 6168
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24Pixel_Shared_ConvolutionPiS_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z24Pixel_Shared_ConvolutionPiS_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
