#include <stdio.h>
#include <math.h>
#include <stdlib.h>

//Note that any functions that want to be called from the kernel must be preceeded with __device__

//Function we are integrating
__device__ float myFunction(float x){
  return pow(x,4);
}

//Trapezoidal rule calculation
__device__ float trapezoidal(float a, float b){
	return (b-a)*((myFunction(a)+myFunction(b))/2);
}

//Composite trap rule calculation
__device__ float composite_trapezoidal(float a, float b, int n){
	float h=(b-a)/(n);
	float total=0;
	int i;
	for (i=0;i<n;i++){
		total=total+trapezoidal(a+i*h,a+(i+1)*h); 
	}
	return total;
}

//This section runs on the GPUs
__global__ void kernel(float* arr, float A, float B, int P, int N){
	//Who am I?
	int id = blockIdx.x * blockDim.x + threadIdx.x;
	
	//calculate number of intervals, where they start, and where they end, and what interval this processor will use
	float intervalWidth = (B-A)/(P);
	float intervalStart = A+(intervalWidth)*(id);
	float intervalEnd = intervalStart+intervalWidth;

	//calculate the partial sum of this interval
	arr[id] = composite_trapezoidal(intervalStart,intervalEnd,N);
}

int main(int argc, char** argv){
	//Process input from command line
	if (argc<3){
		printf("Please enter a,b,N\n");
		return 1;
	}
	
	float A=atof(argv[1]);
	float B=atof(argv[2]);
	int N=atoi(argv[3]);
	
	printf("Integrating x^4 from %.3f to %.3f with %d points\n", A, B, N);
	
	//How many threads will we use and how much data is in each thread?
	int elements = 512;
	int bytes = elements * sizeof(float);

	//Create pointers to host and device arrays
	float *hostArray = 0;
	float *deviceArray = 0;

	//Create the array on the host and on the GPU
	hostArray = (float*) malloc(bytes);
	cudaMalloc((void**)&deviceArray, bytes);

	int blockSize = 128;
	int gridSize = elements / blockSize;

	//Instruct each GPU core to run its kernel section
	kernel<<<gridSize,blockSize>>>(deviceArray, A, B, elements, N);

	//Gather all the partial sums
	cudaMemcpy(hostArray, deviceArray, bytes, cudaMemcpyDeviceToHost);

	//Reduce the partial sums to a single integral
	float sum = 0;
	for(int i=0; i < elements; ++i){
		sum += hostArray[i];
	}
	
	//Print result
	printf("Integrating x^4 from %.3f to %.3f with %d points is: %.3f\n", A, B, N, sum);

	//Deallocate the two arrays
	free(hostArray);
	cudaFree(deviceArray);
	
	//Exit from the calling program
	return 0;
}
	.file	"tmpxft_0028c0d0_00000000-6_cuda_int.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10myFunctionf
	.type	_Z10myFunctionf, @function
_Z10myFunctionf:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10myFunctionf, .-_Z10myFunctionf
	.globl	_Z11trapezoidalff
	.type	_Z11trapezoidalff, @function
_Z11trapezoidalff:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z11trapezoidalff, .-_Z11trapezoidalff
	.globl	_Z21composite_trapezoidalffi
	.type	_Z21composite_trapezoidalffi, @function
_Z21composite_trapezoidalffi:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z21composite_trapezoidalffi, .-_Z21composite_trapezoidalffi
	.globl	_Z29__device_stub__Z6kernelPfffiiPfffii
	.type	_Z29__device_stub__Z6kernelPfffiiPfffii, @function
_Z29__device_stub__Z6kernelPfffiiPfffii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 12(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6kernelPfffii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z29__device_stub__Z6kernelPfffiiPfffii, .-_Z29__device_stub__Z6kernelPfffiiPfffii
	.globl	_Z6kernelPfffii
	.type	_Z6kernelPfffii, @function
_Z6kernelPfffii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6kernelPfffiiPfffii
	.cfi_endproc
.LFE2056:
	.size	_Z6kernelPfffii, .-_Z6kernelPfffii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Please enter a,b,N\n"
.LC2:
	.string	"Integrating x^4 from %.3f to %.3f with %d points\n"
.LC3:
	.string	"Integrating x^4 from %.3f to %.3f with %d points is: %.3f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	jg	.L15
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L14
.L15:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	atof@PLT
	movq	16(%rbx), %rdi
	cvtsd2ss	%xmm0, %xmm3
	movd	%xmm3, %r12d
	call	atof@PLT
	movq	24(%rbx), %rdi
	cvtsd2ss	%xmm0, %xmm4
	movd	%xmm4, %r13d
	call	atoi@PLT
	movd	%r13d, %xmm3
	movd	%r12d, %xmm7
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edx
	cvtss2sd	%xmm3, %xmm5
	cvtss2sd	%xmm7, %xmm6
	movaps	%xmm5, %xmm1
	movaps	%xmm6, %xmm0
	movl	$2, %edi
	movq	%xmm5, %r14
	movl	%eax, %ebp
	movb	$2, %al
	movq	%xmm6, %r15
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$2048, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$2048, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1073741825, %edi
	salq	$7, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$2, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	8(%rsp), %rdi
	movl	%ebp, %edx
	movl	$512, %esi
	movd	%r13d, %xmm1
	movd	%r12d, %xmm0
	call	_Z29__device_stub__Z6kernelPfffiiPfffii
.L17:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$2048, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	xorps	%xmm2, %xmm2
.L18:
	addss	(%rbx,%rax,4), %xmm2
	incq	%rax
	cmpq	$512, %rax
	jne	.L18
	movl	%ebp, %edx
	movq	%r14, %xmm1
	movq	%r15, %xmm0
	movb	$3, %al
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L14:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z6kernelPfffii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelPfffii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>

//Note that any functions that want to be called from the kernel must be preceeded with __device__

//Function we are integrating
__device__ float myFunction(float x){
  return pow(x,4);
}

//Trapezoidal rule calculation
__device__ float trapezoidal(float a, float b){
	return (b-a)*((myFunction(a)+myFunction(b))/2);
}

//Composite trap rule calculation
__device__ float composite_trapezoidal(float a, float b, int n){
	float h=(b-a)/(n);
	float total=0;
	int i;
	for (i=0;i<n;i++){
		total=total+trapezoidal(a+i*h,a+(i+1)*h); 
	}
	return total;
}

//This section runs on the GPUs
__global__ void kernel(float* arr, float A, float B, int P, int N){
	//Who am I?
	int id = blockIdx.x * blockDim.x + threadIdx.x;
	
	//calculate number of intervals, where they start, and where they end, and what interval this processor will use
	float intervalWidth = (B-A)/(P);
	float intervalStart = A+(intervalWidth)*(id);
	float intervalEnd = intervalStart+intervalWidth;

	//calculate the partial sum of this interval
	arr[id] = composite_trapezoidal(intervalStart,intervalEnd,N);
}

int main(int argc, char** argv){
	//Process input from command line
	if (argc<3){
		printf("Please enter a,b,N\n");
		return 1;
	}
	
	float A=atof(argv[1]);
	float B=atof(argv[2]);
	int N=atoi(argv[3]);
	
	printf("Integrating x^4 from %.3f to %.3f with %d points\n", A, B, N);
	
	//How many threads will we use and how much data is in each thread?
	int elements = 512;
	int bytes = elements * sizeof(float);

	//Create pointers to host and device arrays
	float *hostArray = 0;
	float *deviceArray = 0;

	//Create the array on the host and on the GPU
	hostArray = (float*) malloc(bytes);
	hipMalloc((void**)&deviceArray, bytes);

	int blockSize = 128;
	int gridSize = elements / blockSize;

	//Instruct each GPU core to run its kernel section
	kernel<<<gridSize,blockSize>>>(deviceArray, A, B, elements, N);

	//Gather all the partial sums
	hipMemcpy(hostArray, deviceArray, bytes, hipMemcpyDeviceToHost);

	//Reduce the partial sums to a single integral
	float sum = 0;
	for(int i=0; i < elements; ++i){
		sum += hostArray[i];
	}
	
	//Print result
	printf("Integrating x^4 from %.3f to %.3f with %d points is: %.3f\n", A, B, N, sum);

	//Deallocate the two arrays
	free(hostArray);
	hipFree(deviceArray);
	
	//Exit from the calling program
	return 0;
}
	.text
	.file	"cuda_int.hip"
	.globl	_Z21__device_stub__kernelPfffii # -- Begin function _Z21__device_stub__kernelPfffii
	.type	_Z21__device_stub__kernelPfffii,@function
_Z21__device_stub__kernelPfffii:        # @_Z21__device_stub__kernelPfffii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	16(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	12(%rsp), %r8
	movl	%esi, (%r8)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rsi, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPfffii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPfffii, .Lfunc_end0-_Z21__device_stub__kernelPfffii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	cmpl	$2, %edi
	jg	.LBB1_2
# %bb.1:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %eax
	jmp	.LBB1_7
.LBB1_2:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	16(%rbx), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebx
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	cvtss2sd	(%rsp), %xmm1                   # 4-byte Folded Reload
	movl	$.L.str.1, %edi
	movsd	%xmm0, 24(%rsp)                 # 8-byte Spill
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	movl	%eax, %esi
	movb	$2, %al
	callq	printf
	leaq	8(%rsp), %r15
	movq	$0, (%r15)
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %r14
	movl	$2048, %esi                     # imm = 0x800
	movq	%r15, %rdi
	callq	hipMalloc
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	leaq	124(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	8(%rsp), %rdi
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	(%rsp), %xmm1                   # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movl	$512, %esi                      # imm = 0x200
	movl	%ebx, %edx
	callq	_Z21__device_stub__kernelPfffii
.LBB1_4:
	movq	8(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	addss	(%r14,%rax,4), %xmm0
	incq	%rax
	cmpq	$512, %rax                      # imm = 0x200
	jne	.LBB1_5
# %bb.6:
	cvtss2sd	%xmm0, %xmm2
	movl	$.L.str.2, %edi
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	16(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movl	%ebx, %esi
	movb	$3, %al
	callq	printf
	movq	%r14, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
.LBB1_7:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPfffii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPfffii,@object         # @_Z6kernelPfffii
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPfffii
	.p2align	3, 0x0
_Z6kernelPfffii:
	.quad	_Z21__device_stub__kernelPfffii
	.size	_Z6kernelPfffii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Integrating x^4 from %.3f to %.3f with %d points\n"
	.size	.L.str.1, 50

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Integrating x^4 from %.3f to %.3f with %d points is: %.3f\n"
	.size	.L.str.2, 59

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelPfffii"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Please enter a,b,N"
	.size	.Lstr, 19

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPfffii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPfffii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPfffii         ; -- Begin function _Z6kernelPfffii
	.globl	_Z6kernelPfffii
	.p2align	8
	.type	_Z6kernelPfffii,@function
_Z6kernelPfffii:                        ; @_Z6kernelPfffii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lt_i32 s7, 1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.i.preheader
	v_sub_f32_e64 v0, s5, s4
	v_cvt_f32_i32_e32 v2, s6
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v2, v2, v0
	v_div_scale_f32 v6, vcc_lo, v0, v2, v0
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v5, v6
	v_div_fmas_f32 v3, v3, v4, v5
	v_cvt_f32_i32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v2, v3, v2, v0
	v_cvt_f32_i32_e32 v3, s7
	v_fma_f32 v0, v2, v4, s4
	s_mov_b32 s4, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v0
	v_sub_f32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v3, v3, v2
	v_div_scale_f32 v7, vcc_lo, v2, v3, v2
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v6, v7
	v_div_fmas_f32 v4, v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v2, v4, v3, v2
	v_mov_b32_e32 v3, 0
.LBB0_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_i32_e32 v4, s3
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v5, s3
	s_cmp_lg_u32 s7, s3
	v_fma_f32 v4, v2, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v2, v5, v0
	v_frexp_mant_f32_e64 v6, |v4|
	v_frexp_exp_i32_f32_e32 v7, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e64 v8, |v5|
	v_frexp_exp_i32_f32_e32 v9, v5
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v6
	v_cmp_neq_f32_e64 s5, 0x7f800000, |v5|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v8
	v_cndmask_b32_e64 v10, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_cndmask_b32_e64 v11, 0, 1, s2
	v_subrev_co_ci_u32_e64 v9, vcc_lo, 0, v9, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v6, v6, v10
	v_cvt_f32_i32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v8, v8, v11
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, 1.0, v6
	v_dual_add_f32 v10, -1.0, v6 :: v_dual_add_f32 v13, 1.0, v8
	v_add_f32_e32 v12, -1.0, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v16, 0x3f317218, v7 :: v_dual_mul_f32 v19, 0x3f317218, v9
	v_rcp_f32_e32 v15, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_add_f32 v14, -1.0, v11 :: v_dual_add_f32 v17, -1.0, v13
	v_rcp_f32_e32 v18, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v20, v10, v15
	v_sub_f32_e32 v8, v8, v17
	v_fma_f32 v17, 0x3f317218, v9, -v19
	v_sub_f32_e32 v6, v6, v14
	v_fma_f32 v14, 0x3f317218, v7, -v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v17, 0xb102e308, v9 :: v_dual_fmac_f32 v14, 0xb102e308, v7
	v_mul_f32_e32 v7, v12, v18
	v_mul_f32_e32 v9, v11, v20
	v_add_f32_e32 v23, v19, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v21, v16, v14 :: v_dual_mul_f32 v22, v13, v7
	v_fma_f32 v11, v20, v11, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v19, v23, v19 :: v_dual_sub_f32 v16, v21, v16
	v_fma_f32 v13, v7, v13, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v11, v20, v6 :: v_dual_sub_f32 v6, v14, v16
	v_dual_fmac_f32 v13, v7, v8 :: v_dual_sub_f32 v8, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v22, v13
	v_dual_add_f32 v14, v9, v11 :: v_dual_sub_f32 v19, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v14, v9
	v_dual_sub_f32 v9, v9, v11 :: v_dual_sub_f32 v22, v16, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v12, v19 :: v_dual_sub_f32 v12, v22, v13
	v_sub_f32_e32 v11, v11, v16
	v_sub_f32_e32 v17, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v17
	v_sub_f32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v9, v10 :: v_dual_add_f32 v10, v12, v11
	v_add_f32_e32 v9, v17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v15, v9
	v_dual_add_f32 v10, v19, v10 :: v_dual_add_f32 v11, v20, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, v18, v10 :: v_dual_sub_f32 v13, v11, v20
	v_add_f32_e32 v12, v7, v10
	v_mul_f32_e32 v14, v11, v11
	v_ldexp_f32 v15, v11, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v16, v12, v12 :: v_dual_sub_f32 v9, v9, v13
	v_sub_f32_e32 v7, v12, v7
	v_fma_f32 v13, v11, v11, -v14
	v_ldexp_f32 v17, v12, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v18, v9, v9 :: v_dual_sub_f32 v7, v10, v7
	v_fma_f32 v10, v12, v12, -v16
	v_ldexp_f32 v19, v9, 1
	v_fmac_f32_e32 v13, v11, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v14, v13
	v_sub_f32_e32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v20, v7, v7 :: v_dual_sub_f32 v13, v13, v14
	v_fmac_f32_e32 v10, v12, v20
	v_ldexp_f32 v22, v7, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v16, v10
	v_dual_mul_f32 v27, v12, v20 :: v_dual_fmaak_f32 v24, s4, v18, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v25, v11, v18 :: v_dual_fmaak_f32 v24, v18, v24, 0x3ecccdef
	v_fma_f32 v28, v18, v11, -v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v28, v18, v9
	v_mul_f32_e32 v9, v18, v24
	v_fmaak_f32 v26, s4, v20, 0x3e91f4c4
	v_sub_f32_e32 v16, v20, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v28, v13, v11
	v_fmaak_f32 v14, v20, v26, 0x3ecccdef
	v_fma_f32 v26, v20, v12, -v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v10, v16
	v_fmac_f32_e32 v26, v20, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v20, v14
	v_fma_f32 v11, v18, v24, -v9
	v_fmac_f32_e32 v26, v10, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v12, v20, v14, -v7
	v_fmac_f32_e32 v11, v13, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v27, v26
	v_fmac_f32_e32 v12, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v7, v12
	v_sub_f32_e32 v7, v20, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v12, v7
	v_add_f32_e32 v7, 0x31739010, v7
	v_add_f32_e32 v14, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v14, v9 :: v_dual_add_f32 v24, 0x3f2aaaaa, v14
	v_sub_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, 0xbf2aaaaa, v24
	v_dual_add_f32 v16, v25, v28 :: v_dual_add_f32 v9, 0x31739010, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v16, v25 :: v_dual_add_f32 v25, 0x3f2aaaaa, v20
	v_add_f32_e32 v12, 0xbf2aaaaa, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v20, v12
	v_add_f32_e32 v7, v7, v12
	v_sub_f32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v11
	v_dual_sub_f32 v18, v13, v27 :: v_dual_add_f32 v11, v24, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v24, v11
	v_mul_f32_e32 v20, v16, v11
	v_add_f32_e32 v12, v25, v7
	v_sub_f32_e32 v10, v28, v10
	v_add_f32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, v16, v11, -v20
	v_sub_f32_e32 v24, v25, v12
	v_dual_mul_f32 v25, v13, v12 :: v_dual_sub_f32 v18, v26, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v16, v9 :: v_dual_add_f32 v7, v7, v24
	v_fma_f32 v24, v13, v12, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v10, v11
	v_dual_fmac_f32 v24, v13, v7 :: v_dual_add_f32 v7, v20, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, v18, v12
	v_sub_f32_e32 v11, v7, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v25, v24
	v_sub_f32_e32 v13, v9, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v13, v24, v13
	v_dual_add_f32 v12, v17, v9 :: v_dual_sub_f32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v22, v13
	v_dual_add_f32 v11, v19, v11 :: v_dual_sub_f32 v14, v12, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v9, v14 :: v_dual_add_f32 v10, v15, v7
	v_add_f32_e32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v10, v15
	v_add_f32_e32 v13, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v7, v15 :: v_dual_sub_f32 v12, v13, v12
	v_add_f32_e32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v12
	v_add_f32_e32 v11, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v21, v11
	v_sub_f32_e32 v10, v11, v10
	v_dual_sub_f32 v16, v14, v21 :: v_dual_sub_f32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v15, v23, v13 :: v_dual_sub_f32 v12, v14, v16
	v_dual_sub_f32 v11, v11, v16 :: v_dual_add_f32 v16, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v15, v23
	v_dual_sub_f32 v12, v21, v12 :: v_dual_sub_f32 v17, v15, v10
	v_dual_sub_f32 v10, v13, v10 :: v_dual_add_f32 v13, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v18, v16, v6 :: v_dual_sub_f32 v17, v23, v17
	v_sub_f32_e32 v19, v13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v11, v11, v12 :: v_dual_sub_f32 v12, v16, v18
	v_dual_sub_f32 v7, v7, v18 :: v_dual_add_f32 v10, v10, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v13, v19
	v_dual_add_f32 v11, v16, v11 :: v_dual_sub_f32 v6, v6, v12
	v_sub_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v10, v13, v10
	v_sub_f32_e32 v8, v8, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v14, v11
	v_add_f32_e32 v6, v7, v6
	v_dual_add_f32 v7, v15, v10 :: v_dual_add_f32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v12, v14
	v_sub_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v7, v15 :: v_dual_add_f32 v6, v6, v9
	v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v9, v12, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v8, v10 :: v_dual_sub_f32 v11, v9, v12
	v_dual_add_f32 v10, v7, v8 :: v_dual_mul_f32 v13, 0, v9
	v_mul_f32_e32 v12, 4.0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v6, v11
	v_sub_f32_e32 v7, v10, v7
	v_mul_f32_e32 v15, 0, v10
	v_mul_f32_e32 v14, 4.0, v10
	v_fma_f32 v9, v9, 4.0, -v12
	v_cmp_class_f32_e64 vcc_lo, v12, 0x204
	v_sub_f32_e32 v7, v8, v7
	v_fmac_f32_e32 v13, 4.0, v6
	v_fma_f32 v8, v10, 4.0, -v14
	v_cmp_class_f32_e64 s2, v14, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v15, 4.0, v7 :: v_dual_add_f32 v6, v9, v13
	v_add_f32_e32 v7, v8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v12, v6
	v_cndmask_b32_e32 v10, v8, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_sub_f32_e32 v16, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v14, v7 :: v_dual_mul_f32 v18, 0x3fb8aa3b, v16
	v_cndmask_b32_e64 v11, v9, v14, s2
	v_dual_sub_f32 v9, v9, v14 :: v_dual_sub_f32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v20, 0x3fb8aa3b, v16, -v18
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v7, v7, v9
	v_rndne_f32_e32 v21, v18
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v11|
	v_fmac_f32_e32 v20, 0x32a5705f, v16
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_sub_f32_e32 v18, v18, v21
	v_cndmask_b32_e64 v7, 0, v7, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v6, v6, v8 :: v_dual_sub_f32 v17, v11, v15
	v_cvt_i32_f32_e32 v9, v21
	v_dual_add_f32 v18, v18, v20 :: v_dual_add_f32 v7, v15, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v6, 0, v6 :: v_dual_mul_f32 v19, 0x3fb8aa3b, v17
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	v_exp_f32_e32 v8, v18
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v13, v6
	v_fma_f32 v22, 0x3fb8aa3b, v17, -v19
	v_rndne_f32_e32 v23, v19
	v_dual_fmac_f32 v22, 0x32a5705f, v17 :: v_dual_sub_f32 v19, v19, v23
	v_cvt_i32_f32_e32 v10, v23
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v8, v8, v9
	v_dual_add_f32 v19, v19, v22 :: v_dual_cndmask_b32 v8, 0, v8
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v12, v19
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v8, v6, v8
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v9, v12, v10
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_cndmask_b32_e64 v9, 0, v9, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v17
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0x7f800000, v9, s2
	v_fma_f32 v7, v9, v7, v9
	v_cmp_eq_f32_e64 s2, 0x7f800000, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v9, s2
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v4|
	v_sub_f32_e32 v4, v5, v4
	v_cndmask_b32_e64 v7, 0x7f800000, |v7|, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, 0x7f800000, |v6|, s2
	v_cmp_neq_f32_e64 s2, 0, v5
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0, v7, s2
	v_add_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0.5, v6
	v_fmac_f32_e32 v3, v4, v5
	s_cbranch_scc1 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_mov_b32_e32 v3, 0
.LBB0_4:                                ; %_Z21composite_trapezoidalffi.exit
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPfffii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPfffii, .Lfunc_end0-_Z6kernelPfffii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2220
; NumSgprs: 18
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPfffii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPfffii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
