//x: Pointer to matrix
//N: Size of each row
//NPow2: Size of each row rounded up to nearest power of 2
__global__ void bitonicSort(float* X, int N, int NPow2)
{
    extern __shared__ float x[];
    int N2 = NPow2 >> 1;
    int offset = blockIdx.x*N;
    int jump = N2;
    int k, i, i1, i2;
    float min, max;
    int size = 2;
    int stride;
    //Step 0: Figure out K (number of batches per block)
    int K = N2 >> 9;
    if (K == 0) {
        K = 1;
    }
    //Step 0.1: Figure out the thread jump
    if (jump > 512) {
        jump = 512;
    }

    //Step 1: Copy row corresponding to this block into shared memory
    //bearing in mind that for bitonic sort there are half
    //as many threads as there are numbers in each row
    for (k = 0; k < (K << 1); k++) {
        i1 = k*jump + threadIdx.x;
        if (i1 < N) {
            x[i1] = X[offset + i1];
        }
        else if (i1 < NPow2) {
            //NOTE: Assuming all numbers are nonnegative
            //so these dummy padding values will go first
            x[i1] = -1;
        }
    }
    __syncthreads();

    //Step 2: Perform bitonic sort
    while (size < NPow2 << 1) {
        stride = size >> 1;
        while (stride > 0) {
            for (k = 0; k < K; k++) {
                i = k*jump + threadIdx.x;
                i1 = stride*2*(i/stride) + i%stride;
                i2 = i1 + stride;
                if (x[i1] < x[i2]) {
                    min = x[i1];
                    max = x[i2];
                }
                else {
                    min = x[i2];
                    max = x[i1];
                }
                if (i/(size/2)%2 > 0) {
                    x[i1] = min;
                    x[i2] = max;
                }
                else {
                    x[i1] = max;
                    x[i2] = min;
                }
            }
            stride = stride >> 1;
            __syncthreads();
        }
        size = size << 1;
    }

    //Step 3: Copy Result Back
    for (k = 0; k < (K << 1); k++) {
        i1 = k*jump + threadIdx.x;
        if (i1 >= N) {
            break;
        }
        X[offset + (N-1-i1)] = x[i1];
    }
    __syncthreads();
}

	.file	"tmpxft_002bc0c9_00000000-6_bitonicSort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z11bitonicSortPfiiPfii
	.type	_Z33__device_stub__Z11bitonicSortPfiiPfii, @function
_Z33__device_stub__Z11bitonicSortPfiiPfii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11bitonicSortPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z33__device_stub__Z11bitonicSortPfiiPfii, .-_Z33__device_stub__Z11bitonicSortPfiiPfii
	.globl	_Z11bitonicSortPfii
	.type	_Z11bitonicSortPfii, @function
_Z11bitonicSortPfii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z11bitonicSortPfiiPfii
	.cfi_endproc
.LFE2033:
	.size	_Z11bitonicSortPfii, .-_Z11bitonicSortPfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11bitonicSortPfii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11bitonicSortPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//x: Pointer to matrix
//N: Size of each row
//NPow2: Size of each row rounded up to nearest power of 2
__global__ void bitonicSort(float* X, int N, int NPow2)
{
    extern __shared__ float x[];
    int N2 = NPow2 >> 1;
    int offset = blockIdx.x*N;
    int jump = N2;
    int k, i, i1, i2;
    float min, max;
    int size = 2;
    int stride;
    //Step 0: Figure out K (number of batches per block)
    int K = N2 >> 9;
    if (K == 0) {
        K = 1;
    }
    //Step 0.1: Figure out the thread jump
    if (jump > 512) {
        jump = 512;
    }

    //Step 1: Copy row corresponding to this block into shared memory
    //bearing in mind that for bitonic sort there are half
    //as many threads as there are numbers in each row
    for (k = 0; k < (K << 1); k++) {
        i1 = k*jump + threadIdx.x;
        if (i1 < N) {
            x[i1] = X[offset + i1];
        }
        else if (i1 < NPow2) {
            //NOTE: Assuming all numbers are nonnegative
            //so these dummy padding values will go first
            x[i1] = -1;
        }
    }
    __syncthreads();

    //Step 2: Perform bitonic sort
    while (size < NPow2 << 1) {
        stride = size >> 1;
        while (stride > 0) {
            for (k = 0; k < K; k++) {
                i = k*jump + threadIdx.x;
                i1 = stride*2*(i/stride) + i%stride;
                i2 = i1 + stride;
                if (x[i1] < x[i2]) {
                    min = x[i1];
                    max = x[i2];
                }
                else {
                    min = x[i2];
                    max = x[i1];
                }
                if (i/(size/2)%2 > 0) {
                    x[i1] = min;
                    x[i2] = max;
                }
                else {
                    x[i1] = max;
                    x[i2] = min;
                }
            }
            stride = stride >> 1;
            __syncthreads();
        }
        size = size << 1;
    }

    //Step 3: Copy Result Back
    for (k = 0; k < (K << 1); k++) {
        i1 = k*jump + threadIdx.x;
        if (i1 >= N) {
            break;
        }
        X[offset + (N-1-i1)] = x[i1];
    }
    __syncthreads();
}

	.text
	.file	"bitonicSort.hip"
	.globl	_Z26__device_stub__bitonicSortPfii # -- Begin function _Z26__device_stub__bitonicSortPfii
	.type	_Z26__device_stub__bitonicSortPfii,@function
_Z26__device_stub__bitonicSortPfii:     # @_Z26__device_stub__bitonicSortPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11bitonicSortPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__bitonicSortPfii, .Lfunc_end0-_Z26__device_stub__bitonicSortPfii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11bitonicSortPfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11bitonicSortPfii,@object     # @_Z11bitonicSortPfii
	.section	.rodata,"a",@progbits
	.globl	_Z11bitonicSortPfii
	.p2align	3, 0x0
_Z11bitonicSortPfii:
	.quad	_Z26__device_stub__bitonicSortPfii
	.size	_Z11bitonicSortPfii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11bitonicSortPfii"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__bitonicSortPfii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11bitonicSortPfii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11bitonicSortPfii     ; -- Begin function _Z11bitonicSortPfii
	.globl	_Z11bitonicSortPfii
	.p2align	8
	.type	_Z11bitonicSortPfii,@function
_Z11bitonicSortPfii:                    ; @_Z11bitonicSortPfii
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v3, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s3, 1
	s_ashr_i32 s5, s3, 10
	s_cmpk_gt_u32 s3, 0x3ff
	s_cselect_b32 s6, s5, 1
	s_min_i32 s4, s4, 0x200
	s_lshl_b32 s5, s6, 1
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s7, -1, 0
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_lshl_add_u32 v1, v0, 2, 0
	v_mov_b32_e32 v2, v0
	s_mul_i32 s8, s15, s2
	s_lshl_b32 s9, s4, 2
	s_mov_b32 s10, s5
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s11, 0
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $sgpr13
	v_cmpx_le_i32_e64 s2, v2
	s_xor_b32 s12, exec_lo, s12
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s3, v2
	s_mov_b32 s13, -1.0
	s_and_b32 s11, vcc_lo, exec_lo
; %bb.4:                                ; %Flow132
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s12, s12
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, s13
	s_xor_b32 exec_lo, exec_lo, s12
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v4, s8, v2
	s_or_b32 s11, s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
.LBB0_6:                                ; %Flow133
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_and_saveexec_b32 s12, s11
	s_cbranch_execz .LBB0_8
; %bb.7:                                ; %.sink.split
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v4
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v1, s9, v1
	v_add_nc_u32_e32 v2, s4, v2
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_cbranch_scc1 .LBB0_2
.LBB0_9:                                ; %._crit_edge
	s_lshl_b32 s3, s3, 1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_cmp_lt_i32 s3, 3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_18
; %bb.10:                               ; %.lr.ph91
	s_mov_b32 s8, 2
.LBB0_11:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
                                        ;       Child Loop BB0_15 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s9, s8, 1
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_17
; %bb.12:                               ; %.preheader82.preheader
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_ashr_i32 s10, s9, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s11, s9, s10
	s_xor_b32 s11, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s12, 0, s11
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
.LBB0_13:                               ; %.preheader82
                                        ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_15 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_16
; %bb.14:                               ; %.lr.ph85
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_ashr_i32 s12, s9, 31
	s_mov_b32 s16, s6
	s_add_i32 s13, s9, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s13, s13, s12
	v_cvt_f32_u32_e32 v2, s13
	s_sub_i32 s14, 0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s14, v2
	s_lshl_b32 s14, s9, 1
	v_mul_hi_u32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v4
	v_mov_b32_e32 v4, v0
.LBB0_15:                               ;   Parent Loop BB0_11 Depth=1
                                        ;     Parent Loop BB0_13 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v8, 31, v4
	s_add_i32 s16, s16, -1
	s_cmp_lg_u32 s16, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v4, v8
	v_xor_b32_e32 v7, s12, v8
	v_xor_b32_e32 v9, v5, v8
	v_xor_b32_e32 v8, s10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v9, v2
	v_mul_lo_u32 v6, v5, s13
	v_add_nc_u32_e32 v10, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v9, v6
	v_subrev_nc_u32_e32 v11, s13, v6
	v_cmp_le_u32_e32 vcc_lo, s13, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v6, v6, v11
	v_mul_hi_u32 v11, v9, v1
	v_add_nc_u32_e32 v10, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s13, v6
	v_mul_lo_u32 v12, v11, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v10, vcc_lo
	v_add_nc_u32_e32 v13, 1, v11
	v_xor_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v5, v7
	v_mul_lo_u32 v5, v10, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v4, v5
	v_add_nc_u32_e32 v4, s4, v4
	v_mad_u64_u32 v[6:7], null, s14, v10, v[5:6]
	v_sub_nc_u32_e32 v5, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v7, s11, v5
	v_cmp_le_u32_e32 vcc_lo, s11, v5
	v_lshl_add_u32 v6, v6, 2, 0
	v_cndmask_b32_e32 v9, v11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_lshl_add_u32 v10, s9, 2, v6
	ds_load_b32 v11, v6
	ds_load_b32 v12, v10
	v_add_nc_u32_e32 v7, 1, v9
	v_cmp_le_u32_e32 vcc_lo, s11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v9, v7, vcc_lo
	v_xor_b32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v11, v12
	v_and_b32_e32 v5, 0x80000001, v5
	v_dual_cndmask_b32 v7, v12, v11 :: v_dual_cndmask_b32 v8, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	v_cndmask_b32_e32 v5, v8, v7, vcc_lo
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	ds_store_b32 v6, v5
	ds_store_b32 v10, v7
	s_cbranch_scc1 .LBB0_15
.LBB0_16:                               ; %._crit_edge86
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_lshr_b32 s12, s9, 1
	s_cmp_gt_u32 s9, 1
	s_mov_b32 s9, s12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_13
.LBB0_17:                               ; %._crit_edge88
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_lshl_b32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s8, s3
	s_cbranch_scc0 .LBB0_11
.LBB0_18:                               ; %.preheader
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_24
; %bb.19:                               ; %.lr.ph93
	s_add_i32 s15, s15, 1
	s_lshl_b32 s6, s4, 2
	s_mul_i32 s3, s2, s15
                                        ; implicit-def: $sgpr7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_xad_u32 v1, v0, -1, s3
	v_subrev_nc_u32_e32 v0, s4, v0
	s_mov_b32 s3, 0
.LBB0_20:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s4, v0
	s_or_b32 s7, s7, exec_lo
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=1
	ds_load_b32 v6, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s5, s5, -1
	v_add_nc_u32_e32 v3, s6, v3
	s_cmp_eq_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_cselect_b32 s9, -1, 0
	v_subrev_nc_u32_e32 v1, s4, v1
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s9, s9, exec_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_or_b32 s7, s7, s9
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[4:5], v6, off
.LBB0_22:                               ; %Flow
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s8, exec_lo, s7
	s_or_b32 s3, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_20
; %bb.23:                               ; %Flow124
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_24:                               ; %._crit_edge94
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11bitonicSortPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11bitonicSortPfii, .Lfunc_end0-_Z11bitonicSortPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1024
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11bitonicSortPfii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z11bitonicSortPfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
