#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1

__global__ void _auto_kernel_2(int a[5][5],int b[5][5],int i)
{
  int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
  int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
  if (thread_x_id && thread_y_id) 
    if (thread_x_id <= 5 && thread_y_id <= 5) {
      b[i][1 * thread_y_id + -1] = a[i][1 * thread_y_id + -1];
    }
}

__global__ void _auto_kernel_1(int b[5][5],int i)
{
  int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
  if (thread_x_id) 
    if (thread_x_id <= 5) {
      b[i][0] = 1;
    }
}

__global__ void _auto_kernel_0(int a[5][5])
{
  int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
  if (thread_x_id) 
    if (thread_x_id <= 5) {
      a[1 * thread_x_id + -1][1 * thread_x_id + -1] = 1;
    }
}

int main()
{
  int j;
  int i_nom_2;
  int i_nom_1;
  int i;
  int a[5][5];
  int b[5][5];
  int y;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
      typedef int _narray_a[5];
      _narray_a *d_a;
    cudaMalloc((void **) &d_a, sizeof(int ) * 5 * 5);
    cudaMemcpy(d_a, a, sizeof(int ) * 5 * 5, cudaMemcpyHostToDevice);
      int CUDA_GRID_X;
    CUDA_GRID_X = (5 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
      int CUDA_GRID_Y;
    CUDA_GRID_Y = (5 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
      int CUDA_GRID_Z;
    CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
    const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
    const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
    _auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
    cudaMemcpy(a, d_a, sizeof(int ) * 5 * 5, cudaMemcpyDeviceToHost);
    }
{
/* Auto-generated code for call to _auto_kernel_1 */
      typedef int _narray_b[5];
      _narray_b *d_b;
    cudaMalloc((void **) &d_b, sizeof(int ) * 5 * 5);
    cudaMemcpy(d_b, b, sizeof(int ) * 5 * 5, cudaMemcpyHostToDevice);
      int CUDA_GRID_X;
    CUDA_GRID_X = (5 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
      int CUDA_GRID_Y;
    CUDA_GRID_Y = (5 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
      int CUDA_GRID_Z;
    CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
    const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
    const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
    _auto_kernel_1<<<CUDA_gridSize,CUDA_blockSize>>>(d_b, i);
    cudaMemcpy(b, d_b, sizeof(int ) * 5 * 5, cudaMemcpyDeviceToHost);
    }
{
/* Auto-generated code for call to _auto_kernel_2 */
      typedef int _narray_a[5];
      _narray_a *d_a;
    cudaMalloc((void **) &d_a, sizeof(int ) * 5 * 5);
    cudaMemcpy(d_a, a, sizeof(int ) * 5 * 5, cudaMemcpyHostToDevice);
      typedef int _narray_b[5];
      _narray_b *d_b;
    cudaMalloc((void **) &d_b, sizeof(int ) * 5 * 5);
    cudaMemcpy(d_b, b, sizeof(int ) * 5 * 5, cudaMemcpyHostToDevice);
      int CUDA_GRID_X;
    CUDA_GRID_X = (5 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
      int CUDA_GRID_Y;
    CUDA_GRID_Y = (5 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
      int CUDA_GRID_Z;
    CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
    const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
    const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
    _auto_kernel_2<<<CUDA_gridSize,CUDA_blockSize>>>(d_a, d_b, i);
    cudaMemcpy(a, d_a, sizeof(int ) * 5 * 5, cudaMemcpyDeviceToHost);
    cudaMemcpy(b, d_b, sizeof(int ) * 5 * 5, cudaMemcpyDeviceToHost);
    }
  }
/* This should NOT be convertible */
  for (int i = 0; i < 5; i++) {
    a[i][i] = b[i][i];
    for (int j = 0; j < 5; j++) 
      b[i][j] = a[i][j];
  }
  return 0;
}

	.file	"tmpxft_0031e8c1_00000000-6_imperf1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i
	.type	_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i, @function
_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14_auto_kernel_2PA5_iS0_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i, .-_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i
	.globl	_Z14_auto_kernel_2PA5_iS0_i
	.type	_Z14_auto_kernel_2PA5_iS0_i, @function
_Z14_auto_kernel_2PA5_iS0_i:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i
	.cfi_endproc
.LFE2034:
	.size	_Z14_auto_kernel_2PA5_iS0_i, .-_Z14_auto_kernel_2PA5_iS0_i
	.globl	_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii
	.type	_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii, @function
_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14_auto_kernel_1PA5_ii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii, .-_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii
	.globl	_Z14_auto_kernel_1PA5_ii
	.type	_Z14_auto_kernel_1PA5_ii, @function
_Z14_auto_kernel_1PA5_ii:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii
	.cfi_endproc
.LFE2036:
	.size	_Z14_auto_kernel_1PA5_ii, .-_Z14_auto_kernel_1PA5_ii
	.globl	_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i
	.type	_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i, @function
_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z14_auto_kernel_0PA5_i(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L13:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i, .-_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i
	.globl	_Z14_auto_kernel_0PA5_i
	.type	_Z14_auto_kernel_0PA5_i, @function
_Z14_auto_kernel_0PA5_i:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i
	.cfi_endproc
.LFE2038:
	.size	_Z14_auto_kernel_0PA5_i, .-_Z14_auto_kernel_0PA5_i
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$100, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$256, %rsp
	.cfi_def_cfa_offset 288
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %r12
	leaq	48(%rsp), %rbp
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$100, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$21474836481, %rdi
	movl	$1, %esi
	movq	%rdx, 24(%rsp)
	movl	$1, 32(%rsp)
	movq	%rdi, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	16(%rsp), %rdi
	call	_Z37__device_stub__Z14_auto_kernel_0PA5_iPA5_i
.L19:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$100, %edx
	movq	%rbp, %rdi
	leaq	148(%rsp), %rbx
	call	cudaMemcpy@PLT
	movl	$100, %esi
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$100, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$21474836481, %rdi
	movl	$1, %esi
	movq	%rdx, 24(%rsp)
	movl	$1, 32(%rsp)
	movq	%rdi, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	_Z38__device_stub__Z14_auto_kernel_1PA5_iiPA5_ii
.L20:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$100, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	movl	$100, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$100, %edx
	call	cudaMemcpy@PLT
	movl	$100, %esi
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$100, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$21474836481, %rdi
	movl	$1, %esi
	movq	%rdx, 24(%rsp)
	movl	$1, 32(%rsp)
	movq	%rdi, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	xorl	%edx, %edx
	call	_Z41__device_stub__Z14_auto_kernel_2PA5_iS0_iPA5_iS0_i
.L21:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$100, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$100, %edx
	call	cudaMemcpy@PLT
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$256, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14_auto_kernel_0PA5_i"
.LC1:
	.string	"_Z14_auto_kernel_1PA5_ii"
.LC2:
	.string	"_Z14_auto_kernel_2PA5_iS0_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14_auto_kernel_0PA5_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14_auto_kernel_1PA5_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14_auto_kernel_2PA5_iS0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1

__global__ void _auto_kernel_2(int a[5][5],int b[5][5],int i)
{
  int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
  int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
  if (thread_x_id && thread_y_id) 
    if (thread_x_id <= 5 && thread_y_id <= 5) {
      b[i][1 * thread_y_id + -1] = a[i][1 * thread_y_id + -1];
    }
}

__global__ void _auto_kernel_1(int b[5][5],int i)
{
  int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
  if (thread_x_id) 
    if (thread_x_id <= 5) {
      b[i][0] = 1;
    }
}

__global__ void _auto_kernel_0(int a[5][5])
{
  int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
  if (thread_x_id) 
    if (thread_x_id <= 5) {
      a[1 * thread_x_id + -1][1 * thread_x_id + -1] = 1;
    }
}

int main()
{
  int j;
  int i_nom_2;
  int i_nom_1;
  int i;
  int a[5][5];
  int b[5][5];
  int y;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
      typedef int _narray_a[5];
      _narray_a *d_a;
    hipMalloc((void **) &d_a, sizeof(int ) * 5 * 5);
    hipMemcpy(d_a, a, sizeof(int ) * 5 * 5, hipMemcpyHostToDevice);
      int CUDA_GRID_X;
    CUDA_GRID_X = (5 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
      int CUDA_GRID_Y;
    CUDA_GRID_Y = (5 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
      int CUDA_GRID_Z;
    CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
    const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
    const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
    _auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
    hipMemcpy(a, d_a, sizeof(int ) * 5 * 5, hipMemcpyDeviceToHost);
    }
{
/* Auto-generated code for call to _auto_kernel_1 */
      typedef int _narray_b[5];
      _narray_b *d_b;
    hipMalloc((void **) &d_b, sizeof(int ) * 5 * 5);
    hipMemcpy(d_b, b, sizeof(int ) * 5 * 5, hipMemcpyHostToDevice);
      int CUDA_GRID_X;
    CUDA_GRID_X = (5 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
      int CUDA_GRID_Y;
    CUDA_GRID_Y = (5 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
      int CUDA_GRID_Z;
    CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
    const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
    const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
    _auto_kernel_1<<<CUDA_gridSize,CUDA_blockSize>>>(d_b, i);
    hipMemcpy(b, d_b, sizeof(int ) * 5 * 5, hipMemcpyDeviceToHost);
    }
{
/* Auto-generated code for call to _auto_kernel_2 */
      typedef int _narray_a[5];
      _narray_a *d_a;
    hipMalloc((void **) &d_a, sizeof(int ) * 5 * 5);
    hipMemcpy(d_a, a, sizeof(int ) * 5 * 5, hipMemcpyHostToDevice);
      typedef int _narray_b[5];
      _narray_b *d_b;
    hipMalloc((void **) &d_b, sizeof(int ) * 5 * 5);
    hipMemcpy(d_b, b, sizeof(int ) * 5 * 5, hipMemcpyHostToDevice);
      int CUDA_GRID_X;
    CUDA_GRID_X = (5 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
      int CUDA_GRID_Y;
    CUDA_GRID_Y = (5 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
      int CUDA_GRID_Z;
    CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
    const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
    const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
    _auto_kernel_2<<<CUDA_gridSize,CUDA_blockSize>>>(d_a, d_b, i);
    hipMemcpy(a, d_a, sizeof(int ) * 5 * 5, hipMemcpyDeviceToHost);
    hipMemcpy(b, d_b, sizeof(int ) * 5 * 5, hipMemcpyDeviceToHost);
    }
  }
/* This should NOT be convertible */
  for (int i = 0; i < 5; i++) {
    a[i][i] = b[i][i];
    for (int j = 0; j < 5; j++) 
      b[i][j] = a[i][j];
  }
  return 0;
}

	.text
	.file	"imperf1.hip"
	.globl	_Z29__device_stub___auto_kernel_2PA5_iS0_i # -- Begin function _Z29__device_stub___auto_kernel_2PA5_iS0_i
	.type	_Z29__device_stub___auto_kernel_2PA5_iS0_i,@function
_Z29__device_stub___auto_kernel_2PA5_iS0_i: # @_Z29__device_stub___auto_kernel_2PA5_iS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14_auto_kernel_2PA5_iS0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub___auto_kernel_2PA5_iS0_i, .Lfunc_end0-_Z29__device_stub___auto_kernel_2PA5_iS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub___auto_kernel_1PA5_ii # -- Begin function _Z29__device_stub___auto_kernel_1PA5_ii
	.type	_Z29__device_stub___auto_kernel_1PA5_ii,@function
_Z29__device_stub___auto_kernel_1PA5_ii: # @_Z29__device_stub___auto_kernel_1PA5_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14_auto_kernel_1PA5_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub___auto_kernel_1PA5_ii, .Lfunc_end1-_Z29__device_stub___auto_kernel_1PA5_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub___auto_kernel_0PA5_i # -- Begin function _Z29__device_stub___auto_kernel_0PA5_i
	.type	_Z29__device_stub___auto_kernel_0PA5_i,@function
_Z29__device_stub___auto_kernel_0PA5_i: # @_Z29__device_stub___auto_kernel_0PA5_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14_auto_kernel_0PA5_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub___auto_kernel_0PA5_i, .Lfunc_end2-_Z29__device_stub___auto_kernel_0PA5_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$232, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$21474836481, %r14              # imm = 0x500000001
	movabsq	$4294967424, %rbx               # imm = 0x100000080
	leaq	16(%rsp), %r15
	movl	$100, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	leaq	128(%rsp), %rsi
	movl	$100, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	16(%rsp), %rdi
	callq	_Z29__device_stub___auto_kernel_0PA5_i
.LBB3_2:
	leaq	16(%rsp), %r15
	movq	(%r15), %rsi
	leaq	128(%rsp), %rdi
	movl	$100, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rsp, %r12
	movl	$100, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$100, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	(%rsp), %rdi
	callq	_Z29__device_stub___auto_kernel_1PA5_ii
.LBB3_4:
	movq	%rsp, %r12
	movq	(%r12), %rsi
	leaq	16(%rsp), %r15
	movl	$100, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$100, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	leaq	128(%rsp), %rsi
	movl	$100, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %r12
	movl	$100, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$100, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z29__device_stub___auto_kernel_2PA5_iS0_i
.LBB3_6:
	movq	(%rsp), %rsi
	leaq	128(%rsp), %rdi
	movl	$100, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$100, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB3_7:                                # =>This Inner Loop Header: Depth=1
	movl	16(%rsp,%rcx), %edx
	movl	%edx, 128(%rsp,%rcx)
	movups	128(%rsp,%rax), %xmm0
	movups	%xmm0, 16(%rsp,%rax)
	movl	144(%rsp,%rax), %edx
	movl	%edx, 32(%rsp,%rax)
	addq	$24, %rcx
	addq	$20, %rax
	cmpq	$100, %rax
	jne	.LBB3_7
# %bb.8:
	xorl	%eax, %eax
	addq	$232, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14_auto_kernel_2PA5_iS0_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14_auto_kernel_1PA5_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14_auto_kernel_0PA5_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14_auto_kernel_2PA5_iS0_i,@object # @_Z14_auto_kernel_2PA5_iS0_i
	.section	.rodata,"a",@progbits
	.globl	_Z14_auto_kernel_2PA5_iS0_i
	.p2align	3, 0x0
_Z14_auto_kernel_2PA5_iS0_i:
	.quad	_Z29__device_stub___auto_kernel_2PA5_iS0_i
	.size	_Z14_auto_kernel_2PA5_iS0_i, 8

	.type	_Z14_auto_kernel_1PA5_ii,@object # @_Z14_auto_kernel_1PA5_ii
	.globl	_Z14_auto_kernel_1PA5_ii
	.p2align	3, 0x0
_Z14_auto_kernel_1PA5_ii:
	.quad	_Z29__device_stub___auto_kernel_1PA5_ii
	.size	_Z14_auto_kernel_1PA5_ii, 8

	.type	_Z14_auto_kernel_0PA5_i,@object # @_Z14_auto_kernel_0PA5_i
	.globl	_Z14_auto_kernel_0PA5_i
	.p2align	3, 0x0
_Z14_auto_kernel_0PA5_i:
	.quad	_Z29__device_stub___auto_kernel_0PA5_i
	.size	_Z14_auto_kernel_0PA5_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14_auto_kernel_2PA5_iS0_i"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14_auto_kernel_1PA5_ii"
	.size	.L__unnamed_2, 25

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14_auto_kernel_0PA5_i"
	.size	.L__unnamed_3, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub___auto_kernel_2PA5_iS0_i
	.addrsig_sym _Z29__device_stub___auto_kernel_1PA5_ii
	.addrsig_sym _Z29__device_stub___auto_kernel_0PA5_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14_auto_kernel_2PA5_iS0_i
	.addrsig_sym _Z14_auto_kernel_1PA5_ii
	.addrsig_sym _Z14_auto_kernel_0PA5_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14_auto_kernel_2PA5_iS0_i ; -- Begin function _Z14_auto_kernel_2PA5_iS0_i
	.globl	_Z14_auto_kernel_2PA5_iS0_i
	.p2align	8
	.type	_Z14_auto_kernel_2PA5_iS0_i,@function
_Z14_auto_kernel_2PA5_iS0_i:            ; @_Z14_auto_kernel_2PA5_iS0_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s14, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_max_i32_e32 v1, v3, v0
	v_cmp_ne_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, 6, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s4, 20
	s_mul_hi_i32 s4, s4, 20
	s_add_u32 s2, s2, s5
	s_addc_u32 s3, s3, s4
	s_add_u32 s0, s0, s5
	s_addc_u32 s1, s1, s4
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off offset:-4
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14_auto_kernel_2PA5_iS0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14_auto_kernel_2PA5_iS0_i, .Lfunc_end0-_Z14_auto_kernel_2PA5_iS0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z14_auto_kernel_1PA5_ii ; -- Begin function _Z14_auto_kernel_1PA5_ii
	.globl	_Z14_auto_kernel_1PA5_ii
	.p2align	8
	.type	_Z14_auto_kernel_1PA5_ii,@function
_Z14_auto_kernel_1PA5_ii:               ; @_Z14_auto_kernel_1PA5_ii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_cmp_gt_i32_e64 s2, 6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s2, 20
	s_mul_hi_i32 s2, s2, 20
	s_add_u32 s0, s0, s3
	s_addc_u32 s1, s1, s2
	global_store_b32 v0, v1, s[0:1]
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14_auto_kernel_1PA5_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14_auto_kernel_1PA5_ii, .Lfunc_end1-_Z14_auto_kernel_1PA5_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 128
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14_auto_kernel_0PA5_i ; -- Begin function _Z14_auto_kernel_0PA5_i
	.globl	_Z14_auto_kernel_0PA5_i
	.p2align	8
	.type	_Z14_auto_kernel_0PA5_i,@function
_Z14_auto_kernel_0PA5_i:                ; @_Z14_auto_kernel_0PA5_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_cmp_gt_i32_e64 s2, 6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[3:4], null, v1, 20, s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 1
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	global_store_b32 v[0:1], v2, off offset:-24
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14_auto_kernel_0PA5_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z14_auto_kernel_0PA5_i, .Lfunc_end2-_Z14_auto_kernel_0PA5_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 136
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14_auto_kernel_2PA5_iS0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14_auto_kernel_2PA5_iS0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14_auto_kernel_1PA5_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14_auto_kernel_1PA5_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14_auto_kernel_0PA5_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14_auto_kernel_0PA5_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
