/*

BGR0 to YUV converter
I have artifacts and changing md5sum now.

*/

// System includes
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <stdint.h>

// CUDA runtime
#include <cuda_runtime.h>

// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

__global__ void bgr0_to_nv12_pixel(unsigned char *dinput, unsigned char *doutput, int cols, int rows) {
        //int i = threadIdx.x;
        //int j = threadIdx.y;
        //char pixel_data[4];
       
        int col_num = blockIdx.x*blockDim.x+threadIdx.x;
        int row_num = blockIdx.y*blockDim.y+threadIdx.y;
       
        if ((row_num < rows) && (col_num < cols))
    {
       
                //int global_offset = blockIdx.x*blockDim.x*blockDim.y + threadIdx.y*blockDim.x + threadIdx.x;
                int global_offset = row_num*cols+col_num;
                //char pixel_data[4];
                //memcpy(&pixel_data,dinput+global_offset*4,4);
                int r,g,b;
                r = dinput[global_offset*4+2];
                g = dinput[global_offset*4+1];
                b = dinput[global_offset*4+0];
                //r = pixel_data[2];
                //g = pixel_data[1];
                //b = pixel_data[0];
                doutput[global_offset] = ((66*r + 129*g + 25*b) >> 8) + 16;
                if(((threadIdx.x % 2) == 0)  and ((threadIdx.y % 2) == 0)){
                        doutput[cols*rows+row_num*cols/2+col_num+1] = ((112*r + -94*g + -18*b) >> 8) + 128;
                        doutput[cols*rows+row_num*cols/2+col_num] = ((-38*r + -74*g + 112*b) >> 8) + 128;
                }
       
        }
}

__global__ void bgr0_to_nv12_pixel_uint(unsigned char *dinput, unsigned char *doutput, int cols, int rows) { 
    
    int col_num = blockIdx.x*blockDim.x+threadIdx.x;
    int row_num = blockIdx.y*blockDim.y+threadIdx.y;
    
    if ((row_num < rows) && (col_num < cols)) 
    {
    
        //int global_offset = blockIdx.x*blockDim.x*blockDim.y + threadIdx.y*blockDim.x + threadIdx.x;
        int global_offset = row_num*cols+col_num; 
        uint32_t a = *((uint32_t *)&dinput[global_offset*4]);
        int r,g,b;
        
        r = a & 0xff;
        g = ( a >> 8 ) & 0xff;
        b = ( a >> 16 ) & 0xff;
        
        
        doutput[global_offset] = ((66*r + 129*g + 25*b) >> 8) + 16;
        if(((threadIdx.x & 1) == 0)  and ((threadIdx.y & 1) == 0)){
            int uv_offset = cols*rows+((row_num*cols)>>1)+col_num;
            doutput[uv_offset] = ((112*r + -94*g + -18*b) >> 8) + 128;
            doutput[uv_offset+1] = ((-38*r + -74*g + 112*b) >> 8) + 128;
        }
    
    }
}

struct cuda_memory_struct
{
   uint8_t *dinput;
   uint8_t *doutput;
};


extern "C" void * cuda_memory_init(int width,int height){
    int pan_size = width*height*4;
    int pan_size_nv12 = width*height/2*3;
    cuda_memory_struct * cuda_memory_ptr = (cuda_memory_struct * )malloc(sizeof(cuda_memory_struct));
    //cuda_memory_ptr.dinput = 
    clock_t end, start;
    float seconds;
    start = clock();
    cudaMalloc((void **)&cuda_memory_ptr->dinput, sizeof(char)*pan_size );
    cudaMalloc((void **)&cuda_memory_ptr->doutput, sizeof(char)*pan_size_nv12 );
    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Device malloc: %fs\n",seconds);
    return cuda_memory_ptr;
}

extern "C" int cuda_br0_to_nv12(cuda_memory_struct * cuda_memory_ptr,uint8_t * bgr0,uint8_t * nv12, int width, int height)
{
    int pan_size = width*height*4;
    int pan_size_nv12 = width*height/2*3;
    clock_t end, start;
    float seconds;

    uint8_t *dinput = NULL;
    uint8_t *doutput = NULL;
    dinput = cuda_memory_ptr->dinput;
    doutput = cuda_memory_ptr->doutput;

    start = clock();

    cudaMemcpy(dinput, bgr0, sizeof(unsigned char)*pan_size, cudaMemcpyHostToDevice);
    
    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Memory to device copy took: %fs\n",seconds);

    int block_width = 32;
    int block_height = 8;
    int x = width/block_width;
    int y = height/block_height;
    const dim3 numBlocks (x, y, 1);                                // number of blocks 
    const dim3 threadsPerBlock(block_width, block_height, 1);  

    start = clock();

    bgr0_to_nv12_pixel_uint<<<numBlocks, threadsPerBlock>>>(dinput, doutput, width, height);
    gpuErrchk( cudaPeekAtLastError() );
    cudaDeviceSynchronize();

    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Convertation using uint took: %fs\n",seconds);
   
    start = clock();

    cudaMemcpy( nv12, doutput, sizeof(unsigned char)*pan_size_nv12, cudaMemcpyDeviceToHost);
    
    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Memory to host copy took: %fs\n",seconds);
    
    return 0;
    
}






	.file	"tmpxft_0026ae3d_00000000-6_gpu_convert.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Device malloc: %fs\n"
	.text
	.globl	cuda_memory_init
	.type	cuda_memory_init, @function
cuda_memory_init:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%edi, %ebx
	movl	$16, %edi
	imull	%esi, %ebx
	call	malloc@PLT
	movq	%rax, %rbp
	call	clock@PLT
	leal	0(,%rbx,4), %esi
	movq	%rbp, %rdi
	movslq	%esi, %rsi
	movq	%rax, %r12
	call	cudaMalloc@PLT
	movl	%ebx, %eax
	movl	$2, %ecx
	leaq	8(%rbp), %rdi
	cltd
	idivl	%ecx
	leal	(%rax,%rax,2), %eax
	movslq	%eax, %rsi
	call	cudaMalloc@PLT
	call	clock@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	subq	%r12, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	cuda_memory_init, .-cuda_memory_init
	.globl	_Z42__device_stub__Z18bgr0_to_nv12_pixelPhS_iiPhS_ii
	.type	_Z42__device_stub__Z18bgr0_to_nv12_pixelPhS_iiPhS_ii, @function
_Z42__device_stub__Z18bgr0_to_nv12_pixelPhS_iiPhS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18bgr0_to_nv12_pixelPhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z42__device_stub__Z18bgr0_to_nv12_pixelPhS_iiPhS_ii, .-_Z42__device_stub__Z18bgr0_to_nv12_pixelPhS_iiPhS_ii
	.globl	_Z18bgr0_to_nv12_pixelPhS_ii
	.type	_Z18bgr0_to_nv12_pixelPhS_ii, @function
_Z18bgr0_to_nv12_pixelPhS_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18bgr0_to_nv12_pixelPhS_iiPhS_ii
	.cfi_endproc
.LFE2055:
	.size	_Z18bgr0_to_nv12_pixelPhS_ii, .-_Z18bgr0_to_nv12_pixelPhS_ii
	.globl	_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii
	.type	_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii, @function
_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z23bgr0_to_nv12_pixel_uintPhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii, .-_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii
	.globl	_Z23bgr0_to_nv12_pixel_uintPhS_ii
	.type	_Z23bgr0_to_nv12_pixel_uintPhS_ii, @function
_Z23bgr0_to_nv12_pixel_uintPhS_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii
	.cfi_endproc
.LFE2057:
	.size	_Z23bgr0_to_nv12_pixel_uintPhS_ii, .-_Z23bgr0_to_nv12_pixel_uintPhS_ii
	.section	.rodata.str1.1
.LC2:
	.string	"Memory to device copy took: %fs\n"
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/volvofixthis/cuda_bgr0_to_nv12_v4/master/gpu_convert.cu"
.LC4:
	.string	"GPUassert: %s %s %d\n"
.LC5:
	.string	"Convertation using uint took: %fs\n"
.LC6:
	.string	"Memory to host copy took: %fs\n"
	.text
	.globl	cuda_br0_to_nv12
	.type	cuda_br0_to_nv12, @function
cuda_br0_to_nv12:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	movl	$2, %ecx
	imull	%r8d, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	(%rdi), %r15
	movl	%ebx, %eax
	movq	%rdx, 16(%rsp)
	cltd
	movq	%rsi, 24(%rsp)
	idivl	%ecx
	leal	(%rax,%rax,2), %r13d
	movq	8(%rdi), %rax
	movq	%rax, 8(%rsp)
	call	clock@PLT
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	%r15, %rdi
	leal	0(,%rbx,4), %edx
	movq	%rax, %r14
	movslq	%edx, %rdx
	call	cudaMemcpy@PLT
	call	clock@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	subq	%r14, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	%ebp, %eax
	movl	$32, %ecx
	movl	$1, 48(%rsp)
	cltd
	movl	$1, 60(%rsp)
	idivl	%ecx
	movl	$8, %ecx
	movl	%eax, 40(%rsp)
	movl	%r12d, %eax
	cltd
	idivl	%ecx
	movl	%eax, 44(%rsp)
	movl	$1073741825, %eax
	salq	$5, %rax
	movq	%rax, 52(%rsp)
	call	clock@PLT
	movl	60(%rsp), %ecx
	movl	48(%rsp), %esi
	xorl	%r9d, %r9d
	movq	52(%rsp), %rdx
	movq	40(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %rbx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	8(%rsp), %rsi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movq	%r15, %rdi
	call	_Z47__device_stub__Z23bgr0_to_nv12_pixel_uintPhS_iiPhS_ii
.L16:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L17
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$143, %r9d
	movq	stderr(%rip), %rdi
	leaq	.LC3(%rip), %r8
	movq	%rax, %rcx
	leaq	.LC4(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	%ebp, %edi
	call	exit@PLT
.L17:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	subq	%rbx, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	call	clock@PLT
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movslq	%r13d, %rdx
	movl	$2, %ecx
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	call	clock@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	subq	%rbx, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	cuda_br0_to_nv12, .-cuda_br0_to_nv12
	.section	.rodata.str1.1
.LC7:
	.string	"_Z23bgr0_to_nv12_pixel_uintPhS_ii"
.LC8:
	.string	"_Z18bgr0_to_nv12_pixelPhS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23bgr0_to_nv12_pixel_uintPhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18bgr0_to_nv12_pixelPhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*

BGR0 to YUV converter
I have artifacts and changing md5sum now.

*/

// System includes
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <stdint.h>

// CUDA runtime
#include <hip/hip_runtime.h>

// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

__global__ void bgr0_to_nv12_pixel(unsigned char *dinput, unsigned char *doutput, int cols, int rows) {
        //int i = threadIdx.x;
        //int j = threadIdx.y;
        //char pixel_data[4];
       
        int col_num = blockIdx.x*blockDim.x+threadIdx.x;
        int row_num = blockIdx.y*blockDim.y+threadIdx.y;
       
        if ((row_num < rows) && (col_num < cols))
    {
       
                //int global_offset = blockIdx.x*blockDim.x*blockDim.y + threadIdx.y*blockDim.x + threadIdx.x;
                int global_offset = row_num*cols+col_num;
                //char pixel_data[4];
                //memcpy(&pixel_data,dinput+global_offset*4,4);
                int r,g,b;
                r = dinput[global_offset*4+2];
                g = dinput[global_offset*4+1];
                b = dinput[global_offset*4+0];
                //r = pixel_data[2];
                //g = pixel_data[1];
                //b = pixel_data[0];
                doutput[global_offset] = ((66*r + 129*g + 25*b) >> 8) + 16;
                if(((threadIdx.x % 2) == 0)  and ((threadIdx.y % 2) == 0)){
                        doutput[cols*rows+row_num*cols/2+col_num+1] = ((112*r + -94*g + -18*b) >> 8) + 128;
                        doutput[cols*rows+row_num*cols/2+col_num] = ((-38*r + -74*g + 112*b) >> 8) + 128;
                }
       
        }
}

__global__ void bgr0_to_nv12_pixel_uint(unsigned char *dinput, unsigned char *doutput, int cols, int rows) { 
    
    int col_num = blockIdx.x*blockDim.x+threadIdx.x;
    int row_num = blockIdx.y*blockDim.y+threadIdx.y;
    
    if ((row_num < rows) && (col_num < cols)) 
    {
    
        //int global_offset = blockIdx.x*blockDim.x*blockDim.y + threadIdx.y*blockDim.x + threadIdx.x;
        int global_offset = row_num*cols+col_num; 
        uint32_t a = *((uint32_t *)&dinput[global_offset*4]);
        int r,g,b;
        
        r = a & 0xff;
        g = ( a >> 8 ) & 0xff;
        b = ( a >> 16 ) & 0xff;
        
        
        doutput[global_offset] = ((66*r + 129*g + 25*b) >> 8) + 16;
        if(((threadIdx.x & 1) == 0)  and ((threadIdx.y & 1) == 0)){
            int uv_offset = cols*rows+((row_num*cols)>>1)+col_num;
            doutput[uv_offset] = ((112*r + -94*g + -18*b) >> 8) + 128;
            doutput[uv_offset+1] = ((-38*r + -74*g + 112*b) >> 8) + 128;
        }
    
    }
}

struct cuda_memory_struct
{
   uint8_t *dinput;
   uint8_t *doutput;
};


extern "C" void * cuda_memory_init(int width,int height){
    int pan_size = width*height*4;
    int pan_size_nv12 = width*height/2*3;
    cuda_memory_struct * cuda_memory_ptr = (cuda_memory_struct * )malloc(sizeof(cuda_memory_struct));
    //cuda_memory_ptr.dinput = 
    clock_t end, start;
    float seconds;
    start = clock();
    hipMalloc((void **)&cuda_memory_ptr->dinput, sizeof(char)*pan_size );
    hipMalloc((void **)&cuda_memory_ptr->doutput, sizeof(char)*pan_size_nv12 );
    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Device malloc: %fs\n",seconds);
    return cuda_memory_ptr;
}

extern "C" int cuda_br0_to_nv12(cuda_memory_struct * cuda_memory_ptr,uint8_t * bgr0,uint8_t * nv12, int width, int height)
{
    int pan_size = width*height*4;
    int pan_size_nv12 = width*height/2*3;
    clock_t end, start;
    float seconds;

    uint8_t *dinput = NULL;
    uint8_t *doutput = NULL;
    dinput = cuda_memory_ptr->dinput;
    doutput = cuda_memory_ptr->doutput;

    start = clock();

    hipMemcpy(dinput, bgr0, sizeof(unsigned char)*pan_size, hipMemcpyHostToDevice);
    
    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Memory to device copy took: %fs\n",seconds);

    int block_width = 32;
    int block_height = 8;
    int x = width/block_width;
    int y = height/block_height;
    const dim3 numBlocks (x, y, 1);                                // number of blocks 
    const dim3 threadsPerBlock(block_width, block_height, 1);  

    start = clock();

    bgr0_to_nv12_pixel_uint<<<numBlocks, threadsPerBlock>>>(dinput, doutput, width, height);
    gpuErrchk( hipPeekAtLastError() );
    hipDeviceSynchronize();

    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Convertation using uint took: %fs\n",seconds);
   
    start = clock();

    hipMemcpy( nv12, doutput, sizeof(unsigned char)*pan_size_nv12, hipMemcpyDeviceToHost);
    
    end = clock();
    seconds = (float)(end - start) / CLOCKS_PER_SEC;
    printf("Memory to host copy took: %fs\n",seconds);
    
    return 0;
    
}






	.text
	.file	"gpu_convert.hip"
	.globl	_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii # -- Begin function _Z33__device_stub__bgr0_to_nv12_pixelPhS_ii
	.type	_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii,@function
_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii: # @_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18bgr0_to_nv12_pixelPhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii, .Lfunc_end0-_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii # -- Begin function _Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii
	.type	_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii,@function
_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii: # @_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23bgr0_to_nv12_pixel_uintPhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii, .Lfunc_end1-_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function cuda_memory_init
.LCPI2_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	cuda_memory_init
	.type	cuda_memory_init,@function
cuda_memory_init:                       # @cuda_memory_init
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $edi killed $edi def $rdi
	imull	%esi, %edi
	leal	(,%rdi,4), %ebp
	movl	%edi, %eax
	shrl	$31, %eax
	addl	%edi, %eax
	sarl	%eax
	leal	(%rax,%rax,2), %r15d
	movl	$16, %edi
	callq	malloc
	movq	%rax, %rbx
	callq	clock
	movq	%rax, %r14
	movslq	%ebp, %rsi
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	8(%rbx), %rdi
	movslq	%r15d, %rsi
	callq	hipMalloc
	callq	clock
	subq	%r14, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI2_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	cuda_memory_init, .Lfunc_end2-cuda_memory_init
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function cuda_br0_to_nv12
.LCPI3_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	cuda_br0_to_nv12
	.type	cuda_br0_to_nv12,@function
cuda_br0_to_nv12:                       # @cuda_br0_to_nv12
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r15d
	movl	%ecx, %r12d
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movl	%r8d, %ebp
	imull	%ecx, %ebp
	leal	(,%rbp,4), %r14d
	movq	(%rdi), %r13
	movq	8(%rdi), %rax
	movq	%rax, (%rsp)                    # 8-byte Spill
	callq	clock
	movq	%rax, %rbx
	movslq	%r14d, %rdx
	movq	%r15, %r14
	movq	%r13, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	callq	clock
	subq	%rbx, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	leal	31(%r12), %eax
	testl	%r12d, %r12d
	cmovnsl	%r12d, %eax
	sarl	$5, %eax
	leal	7(%r15), %ebx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ebx
	sarl	$3, %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	callq	clock
	movq	%rax, %r15
	movabsq	$34359738400, %rdx              # imm = 0x800000020
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	%r13, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%r12d, %edx
	movl	%r14d, %ecx
	callq	_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii
.LBB3_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movl	%ebp, %eax
	shrl	$31, %eax
	addl	%ebp, %eax
	sarl	%eax
	leal	(%rax,%rax,2), %r14d
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r15, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	callq	clock
	movq	%rax, %rbx
	movslq	%r14d, %rdx
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_4:
	.cfi_def_cfa_offset 80
	movl	%eax, %r14d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str.2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$143, %r8d
	xorl	%eax, %eax
	callq	fprintf
	movl	%r14d, %edi
	callq	exit
.Lfunc_end3:
	.size	cuda_br0_to_nv12, .Lfunc_end3-cuda_br0_to_nv12
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18bgr0_to_nv12_pixelPhS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23bgr0_to_nv12_pixel_uintPhS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18bgr0_to_nv12_pixelPhS_ii,@object # @_Z18bgr0_to_nv12_pixelPhS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z18bgr0_to_nv12_pixelPhS_ii
	.p2align	3, 0x0
_Z18bgr0_to_nv12_pixelPhS_ii:
	.quad	_Z33__device_stub__bgr0_to_nv12_pixelPhS_ii
	.size	_Z18bgr0_to_nv12_pixelPhS_ii, 8

	.type	_Z23bgr0_to_nv12_pixel_uintPhS_ii,@object # @_Z23bgr0_to_nv12_pixel_uintPhS_ii
	.globl	_Z23bgr0_to_nv12_pixel_uintPhS_ii
	.p2align	3, 0x0
_Z23bgr0_to_nv12_pixel_uintPhS_ii:
	.quad	_Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii
	.size	_Z23bgr0_to_nv12_pixel_uintPhS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Device malloc: %fs\n"
	.size	.L.str, 20

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Memory to device copy took: %fs\n"
	.size	.L.str.1, 33

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/volvofixthis/cuda_bgr0_to_nv12_v4/master/gpu_convert.hip"
	.size	.L.str.2, 119

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Convertation using uint took: %fs\n"
	.size	.L.str.3, 35

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Memory to host copy took: %fs\n"
	.size	.L.str.4, 31

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.5, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18bgr0_to_nv12_pixelPhS_ii"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z23bgr0_to_nv12_pixel_uintPhS_ii"
	.size	.L__unnamed_2, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__bgr0_to_nv12_pixelPhS_ii
	.addrsig_sym _Z38__device_stub__bgr0_to_nv12_pixel_uintPhS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18bgr0_to_nv12_pixelPhS_ii
	.addrsig_sym _Z23bgr0_to_nv12_pixel_uintPhS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18bgr0_to_nv12_pixelPhS_ii ; -- Begin function _Z18bgr0_to_nv12_pixelPhS_ii
	.globl	_Z18bgr0_to_nv12_pixelPhS_ii
	.p2align	8
	.type	_Z18bgr0_to_nv12_pixelPhS_ii,@function
_Z18bgr0_to_nv12_pixelPhS_ii:           ; @_Z18bgr0_to_nv12_pixelPhS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_3
; %bb.1:
	v_mul_lo_u32 v1, v4, s4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_or_b32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v1, v0
	v_lshlrev_b32_e32 v4, 2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_clause 0x1
	global_load_u16 v6, v[4:5], off
	global_load_u8 v4, v[4:5], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v5, 8, v6
	v_and_b32_e32 v6, 0xff, v6
	s_waitcnt vmcnt(0)
	v_mul_u32_u24_e32 v8, 0x42, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_u32_u24_e32 v9, 0x81, v5
	v_mul_u32_u24_e32 v10, 25, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v8, v9, v8, v10
	v_ashrrev_i32_e32 v9, 31, v7
	v_lshrrev_b32_e32 v3, 8, v8
	v_and_b32_e32 v8, 1, v2
	v_add_co_u32 v2, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u16 v10, v3, 16
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	global_store_b8 v[2:3], v10, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mul_u32_u24_e32 v2, 0x70, v4
	v_mul_u32_u24_e32 v3, 0xffa2, v5
	v_mul_u32_u24_e32 v7, 0xffee, v6
	v_lshrrev_b32_e32 v8, 31, v1
	v_mul_u32_u24_e32 v4, 0xffda, v4
	v_mul_u32_u24_e32 v5, 0xffb6, v5
	v_mul_u32_u24_e32 v6, 0x70, v6
	v_add3_u32 v2, v3, v2, v7
	v_add_nc_u32_e32 v1, v1, v8
	s_mul_i32 s0, s5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v3, v5, v4, v6
	v_lshrrev_b32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 1, v1
	v_lshrrev_b32_e32 v3, 8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v0, v0, s0, v1
	v_xor_b32_e32 v1, 0x80, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, 0x80, v3
	v_ashrrev_i32_e32 v3, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b16 v4, 8, v1
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_and_b32_e32 v2, 0xff, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	v_or_b32_e32 v2, v2, v4
	global_store_b16 v[0:1], v2, off
.LBB0_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18bgr0_to_nv12_pixelPhS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18bgr0_to_nv12_pixelPhS_ii, .Lfunc_end0-_Z18bgr0_to_nv12_pixelPhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z23bgr0_to_nv12_pixel_uintPhS_ii ; -- Begin function _Z23bgr0_to_nv12_pixel_uintPhS_ii
	.globl	_Z23bgr0_to_nv12_pixel_uintPhS_ii
	.p2align	8
	.type	_Z23bgr0_to_nv12_pixel_uintPhS_ii,@function
_Z23bgr0_to_nv12_pixel_uintPhS_ii:      ; @_Z23bgr0_to_nv12_pixel_uintPhS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_3
; %bb.1:
	v_mul_lo_u32 v1, v4, s4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_or_b32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v1, v0
	v_lshlrev_b32_e32 v4, 2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xff, v4
	v_bfe_u32 v6, v4, 8, 8
	v_bfe_u32 v4, v4, 16, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_u32_u24_e32 v8, 0x42, v5
	v_mul_u32_u24_e32 v9, 0x81, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v10, 25, v4
	v_add3_u32 v8, v9, v8, v10
	v_ashrrev_i32_e32 v9, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 8, v8
	v_and_b32_e32 v8, 1, v2
	v_add_co_u32 v2, vcc_lo, s2, v7
	v_add_nc_u16 v10, v3, 16
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	global_store_b8 v[2:3], v10, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mul_u32_u24_e32 v2, 0x70, v5
	v_mul_u32_u24_e32 v3, 0xffa2, v6
	v_mul_u32_u24_e32 v5, 0xffda, v5
	v_mul_u32_u24_e32 v6, 0xffb6, v6
	v_mul_u32_u24_e32 v7, 0x70, v4
	v_mul_u32_u24_e32 v4, 0xffee, v4
	v_ashrrev_i32_e32 v1, 1, v1
	s_mul_i32 s0, s5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v5, v6, v5, v7
	v_add3_u32 v2, v3, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v0, v0, s0, v1
	v_lshrrev_b32_e32 v3, 8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v2, 8, v2
	v_xor_b32_e32 v1, 0x80, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, 0x80, v2
	v_ashrrev_i32_e32 v3, 31, v0
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_lshlrev_b16 v4, 8, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v2, 0xff, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v2, v2, v4
	global_store_b16 v[0:1], v2, off
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23bgr0_to_nv12_pixel_uintPhS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z23bgr0_to_nv12_pixel_uintPhS_ii, .Lfunc_end1-_Z23bgr0_to_nv12_pixel_uintPhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18bgr0_to_nv12_pixelPhS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18bgr0_to_nv12_pixelPhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23bgr0_to_nv12_pixel_uintPhS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23bgr0_to_nv12_pixel_uintPhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
