#include <stdio.h>

#define MAXN 2003

__device__ __host__ int CeilDiv(int a, int b) { return (a-1)/b + 1; }

__device__ int neighbor(int index, int n, char* cuT){
	int num;
	num = cuT[index-n-1] + cuT[index-n-0] + cuT[index-n+1]
		+ cuT[index-0-1] 				  + cuT[index-0+1]
		+ cuT[index+n-1] + cuT[index+n-0] + cuT[index+n+1];
	return num;
}

__global__ void myGOL( char *cuT, int W, int N){
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	if (tid >= N*N) return;

	int n = N + 2;
	int x = tid / N + 1, y = tid % N + 1;
	int R = W ^ 1;
	int Rindex = x*n+y + R*n*n;
	int Windex = x*n+y + W*n*n;

	int num = neighbor( Rindex, n, cuT );
	cuT[Windex] = cuT[Rindex]? num==2 || num==3: num==3;
}

int main(){
	int N, M;
	static char T[MAXN*MAXN] = {0};
	char *cuT;

	scanf("%d %d", &N, &M);
	int n = N + 2;
	for (int i=1; i<=N; i++)
		scanf("%s", T+i*n+1);
	for (int i=0; i<n; i++)
		for (int j=0; j<n; j++)
			T[i*n+j] = T[i*n+j]=='1'? 1: 0;

	cudaMalloc( &cuT, sizeof(char)*n*n*2 );
	cudaMemset( cuT, 0, sizeof(char)*n*n*2 );
	cudaMemcpy( cuT, T, sizeof(char)*n*n, cudaMemcpyHostToDevice );

	int flag = 0;
	dim3 grid(CeilDiv(N*N, 256)), block(256);
	for (int i=0; i<M; i++){
		flag ^= 1;
		myGOL<<< grid, block >>>( cuT, flag, N );
	}

	cudaMemcpy( T, cuT + flag*n*n, sizeof(char)*n*n, cudaMemcpyDeviceToHost );
	cudaFree(cuT);

	static char out[MAXN*MAXN];
	int length = 0;
	for (int i=1; i<=N; i++){
		for (int j=1; j<=N; j++)
			out[length++] = T[i*n+j] + '0';
		out[length++] = '\n';
	}
	out[--length] = '\0';
	puts(out);
	return 0;
}

	.file	"tmpxft_00246b9e_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7CeilDivii
	.type	_Z7CeilDivii, @function
_Z7CeilDivii:
.LFB2027:
	.cfi_startproc
	endbr64
	leal	-1(%rdi), %eax
	cltd
	idivl	%esi
	incl	%eax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7CeilDivii, .-_Z7CeilDivii
	.globl	_Z8neighboriiPc
	.type	_Z8neighboriiPc, @function
_Z8neighboriiPc:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z8neighboriiPc, .-_Z8neighboriiPc
	.globl	_Z26__device_stub__Z5myGOLPciiPcii
	.type	_Z26__device_stub__Z5myGOLPciiPcii, @function
_Z26__device_stub__Z5myGOLPciiPcii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L5
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5myGOLPcii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L5:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L7
	call	__stack_chk_fail@PLT
.L7:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z26__device_stub__Z5myGOLPciiPcii, .-_Z26__device_stub__Z5myGOLPciiPcii
	.globl	_Z5myGOLPcii
	.type	_Z5myGOLPcii, @function
_Z5myGOLPcii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z5myGOLPciiPcii
	.cfi_endproc
.LFE2055:
	.size	_Z5myGOLPcii, .-_Z5myGOLPcii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d %d"
.LC1:
	.string	"%s"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rdi
	leaq	.LC1(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	_ZZ4mainE1T(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$1, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdx
	movq	%rsp, %rsi
	call	__isoc23_scanf@PLT
	movl	(%rsp), %eax
	leal	2(%rax), %r14d
	movslq	%r14d, %r12
	leaq	1(%rbp,%r12), %r13
.L12:
	cmpl	%ebx, (%rsp)
	jl	.L27
	movq	%r13, %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	incl	%ebx
	call	__isoc23_scanf@PLT
	addq	%r12, %r13
	jmp	.L12
.L27:
	leaq	_ZZ4mainE1T(%rip), %rcx
	xorl	%edx, %edx
.L14:
	cmpl	%r14d, %edx
	jge	.L28
	movq	%rcx, %rax
	xorl	%esi, %esi
.L15:
	cmpb	$49, (%rax)
	sete	(%rax)
	incl	%esi
	incq	%rax
	cmpl	%esi, %r14d
	jg	.L15
	incl	%edx
	addq	%r12, %rcx
	jmp	.L14
.L28:
	movq	%r12, %r13
	leaq	8(%rsp), %rdi
	xorl	%r15d, %r15d
	imulq	%r12, %r13
	leaq	0(%r13,%r13), %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	call	cudaMemset@PLT
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	(%rsp), %eax
	movl	$256, %ecx
	movl	$1, 36(%rsp)
	imull	%eax, %eax
	decl	%eax
	cltd
	idivl	%ecx
	incl	%eax
	movl	%eax, 16(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	addq	$255, %rax
	movq	%rax, 28(%rsp)
.L16:
	cmpl	%r15d, 4(%rsp)
	jle	.L29
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	xorl	$1, %ebx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movl	(%rsp), %edx
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z26__device_stub__Z5myGOLPciiPcii
.L17:
	incl	%r15d
	jmp	.L16
.L29:
	imull	%r14d, %ebx
	movl	$2, %ecx
	movq	%rbp, %rdi
	movq	%r13, %rdx
	addq	%r12, %rbp
	movl	%ebx, %esi
	imull	%r14d, %esi
	movslq	%esi, %rsi
	addq	8(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	(%rsp), %ecx
	movl	$1, %esi
	xorl	%eax, %eax
	leaq	_ZZ4mainE3out(%rip), %rdi
	leal	-1(%rcx), %r10d
.L19:
	cmpl	%esi, %ecx
	jl	.L30
	movslq	%eax, %r8
	movl	$1, %edx
	addq	%rdi, %r8
.L20:
	movb	0(%rbp,%rdx), %bl
	leal	48(%rbx), %r9d
	movb	%r9b, -1(%r8,%rdx)
	incq	%rdx
	cmpl	%edx, %ecx
	jge	.L20
	movl	%eax, %edx
	incl	%esi
	leal	2(%rax,%r10), %eax
	addq	%r12, %rbp
	addl	%ecx, %edx
	movslq	%edx, %rdx
	movb	$10, (%rdi,%rdx)
	jmp	.L19
.L30:
	decl	%eax
	cltq
	movb	$0, (%rdi,%rax)
	call	puts@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z5myGOLPcii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5myGOLPcii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ4mainE3out
	.comm	_ZZ4mainE3out,4012009,32
	.local	_ZZ4mainE1T
	.comm	_ZZ4mainE1T,4012009,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

#define MAXN 2003

__device__ __host__ int CeilDiv(int a, int b) { return (a-1)/b + 1; }

__device__ int neighbor(int index, int n, char* cuT){
	int num;
	num = cuT[index-n-1] + cuT[index-n-0] + cuT[index-n+1]
		+ cuT[index-0-1] 				  + cuT[index-0+1]
		+ cuT[index+n-1] + cuT[index+n-0] + cuT[index+n+1];
	return num;
}

__global__ void myGOL( char *cuT, int W, int N){
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	if (tid >= N*N) return;

	int n = N + 2;
	int x = tid / N + 1, y = tid % N + 1;
	int R = W ^ 1;
	int Rindex = x*n+y + R*n*n;
	int Windex = x*n+y + W*n*n;

	int num = neighbor( Rindex, n, cuT );
	cuT[Windex] = cuT[Rindex]? num==2 || num==3: num==3;
}

int main(){
	int N, M;
	static char T[MAXN*MAXN] = {0};
	char *cuT;

	scanf("%d %d", &N, &M);
	int n = N + 2;
	for (int i=1; i<=N; i++)
		scanf("%s", T+i*n+1);
	for (int i=0; i<n; i++)
		for (int j=0; j<n; j++)
			T[i*n+j] = T[i*n+j]=='1'? 1: 0;

	hipMalloc( &cuT, sizeof(char)*n*n*2 );
	hipMemset( cuT, 0, sizeof(char)*n*n*2 );
	hipMemcpy( cuT, T, sizeof(char)*n*n, hipMemcpyHostToDevice );

	int flag = 0;
	dim3 grid(CeilDiv(N*N, 256)), block(256);
	for (int i=0; i<M; i++){
		flag ^= 1;
		myGOL<<< grid, block >>>( cuT, flag, N );
	}

	hipMemcpy( T, cuT + flag*n*n, sizeof(char)*n*n, hipMemcpyDeviceToHost );
	hipFree(cuT);

	static char out[MAXN*MAXN];
	int length = 0;
	for (int i=1; i<=N; i++){
		for (int j=1; j<=N; j++)
			out[length++] = T[i*n+j] + '0';
		out[length++] = '\n';
	}
	out[--length] = '\0';
	puts(out);
	return 0;
}

	.text
	.file	"main.hip"
	.globl	_Z7CeilDivii                    # -- Begin function _Z7CeilDivii
	.type	_Z7CeilDivii,@function
_Z7CeilDivii:                           # @_Z7CeilDivii
	.cfi_startproc
# %bb.0:
                                        # kill: def $edi killed $edi def $rdi
	leal	-1(%rdi), %eax
	cltd
	idivl	%esi
	incl	%eax
	retq
.Lfunc_end0:
	.size	_Z7CeilDivii, .Lfunc_end0-_Z7CeilDivii
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__myGOLPcii    # -- Begin function _Z20__device_stub__myGOLPcii
	.type	_Z20__device_stub__myGOLPcii,@function
_Z20__device_stub__myGOLPcii:           # @_Z20__device_stub__myGOLPcii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5myGOLPcii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__myGOLPcii, .Lfunc_end1-_Z20__device_stub__myGOLPcii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	8(%rsp), %rbx
	leaq	12(%rsp), %rdx
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%rbx), %r14d
	leal	2(%r14), %ebp
	movslq	%ebp, %r13
	testl	%r14d, %r14d
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	leaq	_ZZ4mainE1T+1(%r13), %rbx
	xorl	%r15d, %r15d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	8(%rsp), %rax
	incq	%r15
	addq	%r13, %rbx
	cmpq	%rax, %r15
	jl	.LBB2_2
.LBB2_3:                                # %.preheader62
	cmpl	$-2, %r14d
	movl	%ebp, 28(%rsp)                  # 4-byte Spill
	jle	.LBB2_8
# %bb.4:                                # %.preheader61.lr.ph
	cmpl	$2, %ebp
	movl	$1, %eax
	cmovgel	%ebp, %eax
	movslq	%ebp, %r13
	movl	$_ZZ4mainE1T, %ecx
	xorl	%edx, %edx
.LBB2_5:                                # %.lr.ph66
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	xorl	%esi, %esi
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpb	$49, (%rcx,%rsi)
	sete	(%rcx,%rsi)
	incq	%rsi
	cmpq	%rsi, %rax
	jne	.LBB2_6
# %bb.7:                                # %._crit_edge
                                        #   in Loop: Header=BB2_5 Depth=1
	incq	%rdx
	addq	%r13, %rcx
	cmpq	%rax, %rdx
	jne	.LBB2_5
.LBB2_8:                                # %._crit_edge68
	movabsq	$4294967296, %rbp               # imm = 0x100000000
	movq	%r13, %rbx
	imulq	%r13, %rbx
	leaq	(%rbx,%rbx), %r15
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	movq	%r15, %rdx
	callq	hipMemset
	movq	(%r12), %rdi
	movl	$_ZZ4mainE1T, %esi
	movq	%rbx, 32(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	8(%rsp), %r15d
	imull	%r15d, %r15d
	leal	-1(%r15), %eax
	addl	$254, %r15d
	testl	%eax, %eax
	cmovnsl	%eax, %r15d
	cmpl	$0, 12(%rsp)
	jle	.LBB2_13
# %bb.9:                                # %.lr.ph72.preheader
	sarl	$8, %r15d
	incl	%r15d
	btsq	$32, %r15
	xorl	%r14d, %r14d
	leaq	256(%rbp), %r12
	xorl	%ebx, %ebx
.LBB2_10:                               # %.lr.ph72
                                        # =>This Inner Loop Header: Depth=1
	xorl	$1, %r14d
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.11:                               #   in Loop: Header=BB2_10 Depth=1
	movq	16(%rsp), %rdi
	movl	8(%rsp), %edx
	movl	%r14d, %esi
	callq	_Z20__device_stub__myGOLPcii
.LBB2_12:                               #   in Loop: Header=BB2_10 Depth=1
	incl	%ebx
	cmpl	12(%rsp), %ebx
	jl	.LBB2_10
.LBB2_13:                               # %._crit_edge73
	movl	28(%rsp), %eax                  # 4-byte Reload
	imull	%eax, %eax
	imull	%r14d, %eax
	movslq	%eax, %rsi
	addq	16(%rsp), %rsi
	movl	$_ZZ4mainE1T, %edi
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	8(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB2_14
# %bb.16:                               # %.preheader.lr.ph
	incq	%rax
	leaq	_ZZ4mainE1T(%r13), %rcx
	movl	$1, %edx
	xorl	%esi, %esi
.LBB2_17:                               # %.lr.ph77
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_18 Depth 2
	movq	%rsi, %rdi
	shlq	$32, %rdi
	movslq	%esi, %rsi
	incq	%rsi
	movl	$1, %r8d
.LBB2_18:                               #   Parent Loop BB2_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movb	(%rcx,%r8), %r9b
	addb	$48, %r9b
	movb	%r9b, _ZZ4mainE3out-1(%rsi)
	incq	%r8
	incq	%rsi
	addq	%rbp, %rdi
	cmpq	%r8, %rax
	jne	.LBB2_18
# %bb.19:                               # %._crit_edge78
                                        #   in Loop: Header=BB2_17 Depth=1
	sarq	$32, %rdi
	movb	$10, _ZZ4mainE3out(%rdi)
	incq	%rdx
	addq	%r13, %rcx
	cmpq	%rax, %rdx
	jne	.LBB2_17
	jmp	.LBB2_15
.LBB2_14:
	movq	$-1, %rdi
.LBB2_15:                               # %._crit_edge83
	movb	$0, _ZZ4mainE3out(%rdi)
	movl	$_ZZ4mainE3out, %edi
	callq	puts
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5myGOLPcii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5myGOLPcii,@object            # @_Z5myGOLPcii
	.section	.rodata,"a",@progbits
	.globl	_Z5myGOLPcii
	.p2align	3, 0x0
_Z5myGOLPcii:
	.quad	_Z20__device_stub__myGOLPcii
	.size	_Z5myGOLPcii, 8

	.type	_ZZ4mainE1T,@object             # @_ZZ4mainE1T
	.local	_ZZ4mainE1T
	.comm	_ZZ4mainE1T,4012009,16
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d %d"
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%s"
	.size	.L.str.1, 3

	.type	_ZZ4mainE3out,@object           # @_ZZ4mainE3out
	.local	_ZZ4mainE3out
	.comm	_ZZ4mainE3out,4012009,16
	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5myGOLPcii"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__myGOLPcii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5myGOLPcii
	.addrsig_sym _ZZ4mainE1T
	.addrsig_sym _ZZ4mainE3out
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5myGOLPcii            ; -- Begin function _Z5myGOLPcii
	.globl	_Z5myGOLPcii
	.p2align	8
	.type	_Z5myGOLPcii,@function
_Z5myGOLPcii:                           ; @_Z5myGOLPcii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mul_i32 s4, s3, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_ashr_i32 s5, s3, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s4, s3, s5
	s_load_b64 s[0:1], s[0:1], 0x0
	s_xor_b32 s4, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s4
	s_sub_i32 s6, 0, s4
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s5, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s6, v0
	s_xor_b32 s6, s2, 1
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v0, s4
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v5, s4, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v2
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s4, v2
	s_add_i32 s4, s3, 2
	s_mul_i32 s7, s4, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_mul_i32 s6, s7, s6
	s_mul_i32 s7, s7, s2
	s_ashr_i32 s8, s6, 31
	s_ashr_i32 s2, s7, 31
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_mul_lo_u32 v4, v0, s3
	v_mad_u64_u32 v[2:3], null, s4, v0, s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v1, v4
	v_ashrrev_i32_e32 v1, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v0
	v_add_co_u32 v6, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v6, s6
	s_ashr_i32 s6, s4, 31
	v_add_co_ci_u32_e32 v3, vcc_lo, s8, v7, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	v_sub_co_u32 v4, vcc_lo, v2, s4
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s6, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, v0, s3
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_clause 0x5
	global_load_u16 v8, v[2:3], off offset:2
	global_load_u16 v9, v[0:1], off
	global_load_u16 v10, v[4:5], off
	global_load_i8 v4, v[4:5], off offset:2
	global_load_i8 v0, v[0:1], off offset:2
	global_load_i8 v1, v[2:3], off offset:4
	s_add_u32 s0, s0, s7
	s_addc_u32 s1, s1, s2
	s_waitcnt vmcnt(4)
	v_bfe_i32 v5, v9, 0, 8
	s_waitcnt vmcnt(3)
	v_bfe_i32 v2, v10, 0, 8
	v_bfe_i32 v3, v10, 8, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	v_bfe_i32 v3, v8, 0, 8
	s_waitcnt vmcnt(2)
	v_add3_u32 v2, v2, v4, v5
	v_bfe_i32 v4, v8, 8, 8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v2, v0, v3
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v0, v4, v1
	v_lshrrev_b32_e32 v1, 8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, -2, v0
	v_and_b32_e32 v1, 0xff, v1
	v_cmp_eq_u32_e32 vcc_lo, 3, v0
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 2, v2
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_cmp_eq_u16_e32 vcc_lo, 0, v1
	v_cndmask_b32_e32 v0, v2, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v2, 1, v0
	v_add_co_u32 v0, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
	global_store_b8 v[0:1], v2, off offset:1
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5myGOLPcii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5myGOLPcii, .Lfunc_end0-_Z5myGOLPcii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 660
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5myGOLPcii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5myGOLPcii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
