#include <stdlib.h>
#include <stdio.h>
#include <math.h>

#define A1 0.31938153
#define A2 -0.356563782
#define A3 1.781477937
#define A4 -1.821255978
#define A5 1.330274429
#define RSQRT2PI 0.3989422804

__device__ double cndGPU(double d)
{
    double
        K = 1.0 / (1.0 + 0.2316419 * fabs(d));

    double
        cnd = RSQRT2PI * exp(- 0.5 * d * d) * 
        (K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));

    if(d > 0)
        cnd = 1.0 - cnd;

    return cnd;
}


///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ void BlackScholesBodyGPU
(
    double& CallResult,
    double& PutResult,
    double S, //Stock price
    double X, //Option strike
    double T, //Option years
    double R, //Riskless rate
    double V  //Volatility rate
)
{
    double sqrtT, expRT;
    double d1, d2, CNDD1, CNDD2;

    sqrtT = sqrt(T);
    d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
    d2 = d1 - V * sqrtT;


    CNDD1 = cndGPU(d1);
    CNDD2 = cndGPU(d2);
    //printf("%.15f,", CNDD1);

    //Calculate Call and Put simultaneously
    expRT = exp(- R * T);
    CallResult = S * CNDD1 - X * expRT * CNDD2;
    PutResult  = X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1);
}


////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
    double *d_CallResult,
    double *d_PutResult,
    double *d_StockPrice,
    double *d_OptionStrike,
    double *d_OptionYears,
    double Riskfree,
    double Volatility,
    int optN
)
{
    //Thread index
    const int      tid = blockDim.x * blockIdx.x + threadIdx.x;
    //Total number of threads in execution grid
    const int THREAD_N = blockDim.x * gridDim.x;

    //No matter how small is execution grid or how large OptN is,
    //exactly OptN indices will be processed with perfect memory coalescing
    for(int opt = tid; opt < optN; opt += THREAD_N)
        BlackScholesBodyGPU(
            d_CallResult[opt],
            d_PutResult[opt],
            d_StockPrice[opt],
            d_OptionStrike[opt],
            d_OptionYears[opt],
            Riskfree,
            Volatility
        );
}


double RandDouble(double low, double high){
    double t = (double)rand() / (double)RAND_MAX;
    return (1.0 - t) * low + t * high;
}

#define OPT_N  400000


const int  NUM_ITERATIONS = 512;


const int          OPT_SZ = OPT_N * sizeof(double);
const double      RISKFREE = 0.02;
const double    VOLATILITY = 0.30;


int main()
{
    double * h_CallResultGPU = (double *)malloc(OPT_SZ);
    double * h_PutResultGPU  = (double *)malloc(OPT_SZ);
    double * h_StockPrice    = (double *)malloc(OPT_SZ);
    double * h_OptionStrike  = (double *)malloc(OPT_SZ);
    double * h_OptionYears   = (double *)malloc(OPT_SZ);


    double
        //Results calculated by GPU
        *d_CallResult,
        *d_PutResult,
        //GPU instance of input data
        *d_StockPrice,
        *d_OptionStrike,
        *d_OptionYears;

    cudaMalloc((void **)&d_CallResult,   OPT_SZ);
    cudaMalloc((void **)&d_PutResult,    OPT_SZ);
    cudaMalloc((void **)&d_StockPrice,   OPT_SZ);
    cudaMalloc((void **)&d_OptionStrike, OPT_SZ);
    cudaMalloc((void **)&d_OptionYears,  OPT_SZ);   

    srand(5347);

    //Generate options set
    int i;
    for(i = 0; i < OPT_N; i++)
    {
        h_CallResultGPU[i] = 0.0;
        h_PutResultGPU[i]  = -1.0;
        h_StockPrice[i]    = RandDouble(5.0, 30.0);
        h_OptionStrike[i]  = RandDouble(1.0, 100.0);
        h_OptionYears[i]   = RandDouble(0.25, 10.0);
    }

    cudaMemcpy(d_StockPrice,  h_StockPrice,   OPT_SZ, cudaMemcpyHostToDevice);
    cudaMemcpy(d_OptionStrike, h_OptionStrike,  OPT_SZ, cudaMemcpyHostToDevice);
    cudaMemcpy(d_OptionYears,  h_OptionYears,   OPT_SZ, cudaMemcpyHostToDevice);  

    for(i = 0; i < NUM_ITERATIONS; i++){
        BlackScholesGPU<<<256, 128>>>(
            d_CallResult,
            d_PutResult,
            d_OptionStrike,
            d_StockPrice,
            d_OptionYears,
            RISKFREE,
            VOLATILITY,
            OPT_N
        );      
    }

    cudaMemcpy(h_CallResultGPU, d_CallResult, OPT_SZ, cudaMemcpyDeviceToHost);
    cudaMemcpy(h_PutResultGPU,  d_PutResult,  OPT_SZ, cudaMemcpyDeviceToHost);   

    //for(i = 0; i < OPT_N; i++)
    //    printf("%.15f,", h_CallResultGPU[i]);

  return 0;
}
	.file	"tmpxft_002a39e0_00000000-6_black_scholes.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6cndGPUd
	.type	_Z6cndGPUd, @function
_Z6cndGPUd:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z6cndGPUd, .-_Z6cndGPUd
	.globl	_Z19BlackScholesBodyGPURdS_ddddd
	.type	_Z19BlackScholesBodyGPURdS_ddddd, @function
_Z19BlackScholesBodyGPURdS_ddddd:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z19BlackScholesBodyGPURdS_ddddd, .-_Z19BlackScholesBodyGPURdS_ddddd
	.globl	_Z10RandDoubledd
	.type	_Z10RandDoubledd, @function
_Z10RandDoubledd:
.LFB2029:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movsd	%xmm0, (%rsp)
	movsd	%xmm1, 8(%rsp)
	call	rand@PLT
	movsd	.LC1(%rip), %xmm0
	cvtsi2sdl	%eax, %xmm1
	divsd	.LC0(%rip), %xmm1
	subsd	%xmm1, %xmm0
	mulsd	8(%rsp), %xmm1
	mulsd	(%rsp), %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	addsd	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z10RandDoubledd, .-_Z10RandDoubledd
	.globl	_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi
	.type	_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi, @function
_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z15BlackScholesGPUPdS_S_S_S_ddi(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi, .-_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi
	.globl	_Z15BlackScholesGPUPdS_S_S_S_ddi
	.type	_Z15BlackScholesGPUPdS_S_S_S_ddi, @function
_Z15BlackScholesGPUPdS_S_S_S_ddi:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi
	.cfi_endproc
.LFE2056:
	.size	_Z15BlackScholesGPUPdS_S_S_S_ddi, .-_Z15BlackScholesGPUPdS_S_S_S_ddi
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$3200000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$3200000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$3200000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$3200000, %edi
	movq	%rax, %r15
	call	malloc@PLT
	movl	$3200000, %edi
	movq	%rax, %r14
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$3200000, %esi
	movq	%rax, %r13
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$3200000, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$3200000, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$3200000, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$3200000, %esi
	call	cudaMalloc@PLT
	movl	$5347, %edi
	call	srand@PLT
.L15:
	movq	.LC3(%rip), %rax
	movq	$0x000000000, (%r12,%rbx)
	movsd	.LC4(%rip), %xmm1
	movsd	.LC5(%rip), %xmm0
	movq	%rax, 0(%rbp,%rbx)
	call	_Z10RandDoubledd
	movsd	.LC6(%rip), %xmm1
	movsd	%xmm0, (%r15,%rbx)
	movsd	.LC1(%rip), %xmm0
	call	_Z10RandDoubledd
	movsd	.LC7(%rip), %xmm1
	movsd	%xmm0, (%r14,%rbx)
	movsd	.LC8(%rip), %xmm0
	call	_Z10RandDoubledd
	movsd	%xmm0, 0(%r13,%rbx)
	addq	$8, %rbx
	cmpq	$3200000, %rbx
	jne	.L15
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$3200000, %edx
	movq	%r15, %rsi
	movl	$512, %ebx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$3200000, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	movabsq	$4294967424, %r13
	movl	$3200000, %edx
	call	cudaMemcpy@PLT
.L17:
	movl	$16777217, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	salq	$8, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	40(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	$400000, %r9d
	movsd	.LC9(%rip), %xmm1
	movsd	.LC10(%rip), %xmm0
	movq	32(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z46__device_stub__Z15BlackScholesGPUPdS_S_S_S_ddiPdS_S_S_S_ddi
.L16:
	decl	%ebx
	jne	.L17
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$3200000, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$3200000, %edx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC11:
	.string	"_Z15BlackScholesGPUPdS_S_S_S_ddi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15BlackScholesGPUPdS_S_S_S_ddi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	-4194304
	.long	1105199103
	.align 8
.LC1:
	.long	0
	.long	1072693248
	.align 8
.LC3:
	.long	0
	.long	-1074790400
	.align 8
.LC4:
	.long	0
	.long	1077805056
	.align 8
.LC5:
	.long	0
	.long	1075052544
	.align 8
.LC6:
	.long	0
	.long	1079574528
	.align 8
.LC7:
	.long	0
	.long	1076101120
	.align 8
.LC8:
	.long	0
	.long	1070596096
	.align 8
.LC9:
	.long	858993459
	.long	1070805811
	.align 8
.LC10:
	.long	1202590843
	.long	1066695393
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>

#define A1 0.31938153
#define A2 -0.356563782
#define A3 1.781477937
#define A4 -1.821255978
#define A5 1.330274429
#define RSQRT2PI 0.3989422804

__device__ double cndGPU(double d)
{
    double
        K = 1.0 / (1.0 + 0.2316419 * fabs(d));

    double
        cnd = RSQRT2PI * exp(- 0.5 * d * d) * 
        (K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));

    if(d > 0)
        cnd = 1.0 - cnd;

    return cnd;
}


///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ void BlackScholesBodyGPU
(
    double& CallResult,
    double& PutResult,
    double S, //Stock price
    double X, //Option strike
    double T, //Option years
    double R, //Riskless rate
    double V  //Volatility rate
)
{
    double sqrtT, expRT;
    double d1, d2, CNDD1, CNDD2;

    sqrtT = sqrt(T);
    d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
    d2 = d1 - V * sqrtT;


    CNDD1 = cndGPU(d1);
    CNDD2 = cndGPU(d2);
    //printf("%.15f,", CNDD1);

    //Calculate Call and Put simultaneously
    expRT = exp(- R * T);
    CallResult = S * CNDD1 - X * expRT * CNDD2;
    PutResult  = X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1);
}


////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
    double *d_CallResult,
    double *d_PutResult,
    double *d_StockPrice,
    double *d_OptionStrike,
    double *d_OptionYears,
    double Riskfree,
    double Volatility,
    int optN
)
{
    //Thread index
    const int      tid = blockDim.x * blockIdx.x + threadIdx.x;
    //Total number of threads in execution grid
    const int THREAD_N = blockDim.x * gridDim.x;

    //No matter how small is execution grid or how large OptN is,
    //exactly OptN indices will be processed with perfect memory coalescing
    for(int opt = tid; opt < optN; opt += THREAD_N)
        BlackScholesBodyGPU(
            d_CallResult[opt],
            d_PutResult[opt],
            d_StockPrice[opt],
            d_OptionStrike[opt],
            d_OptionYears[opt],
            Riskfree,
            Volatility
        );
}


double RandDouble(double low, double high){
    double t = (double)rand() / (double)RAND_MAX;
    return (1.0 - t) * low + t * high;
}

#define OPT_N  400000


const int  NUM_ITERATIONS = 512;


const int          OPT_SZ = OPT_N * sizeof(double);
const double      RISKFREE = 0.02;
const double    VOLATILITY = 0.30;


int main()
{
    double * h_CallResultGPU = (double *)malloc(OPT_SZ);
    double * h_PutResultGPU  = (double *)malloc(OPT_SZ);
    double * h_StockPrice    = (double *)malloc(OPT_SZ);
    double * h_OptionStrike  = (double *)malloc(OPT_SZ);
    double * h_OptionYears   = (double *)malloc(OPT_SZ);


    double
        //Results calculated by GPU
        *d_CallResult,
        *d_PutResult,
        //GPU instance of input data
        *d_StockPrice,
        *d_OptionStrike,
        *d_OptionYears;

    hipMalloc((void **)&d_CallResult,   OPT_SZ);
    hipMalloc((void **)&d_PutResult,    OPT_SZ);
    hipMalloc((void **)&d_StockPrice,   OPT_SZ);
    hipMalloc((void **)&d_OptionStrike, OPT_SZ);
    hipMalloc((void **)&d_OptionYears,  OPT_SZ);   

    srand(5347);

    //Generate options set
    int i;
    for(i = 0; i < OPT_N; i++)
    {
        h_CallResultGPU[i] = 0.0;
        h_PutResultGPU[i]  = -1.0;
        h_StockPrice[i]    = RandDouble(5.0, 30.0);
        h_OptionStrike[i]  = RandDouble(1.0, 100.0);
        h_OptionYears[i]   = RandDouble(0.25, 10.0);
    }

    hipMemcpy(d_StockPrice,  h_StockPrice,   OPT_SZ, hipMemcpyHostToDevice);
    hipMemcpy(d_OptionStrike, h_OptionStrike,  OPT_SZ, hipMemcpyHostToDevice);
    hipMemcpy(d_OptionYears,  h_OptionYears,   OPT_SZ, hipMemcpyHostToDevice);  

    for(i = 0; i < NUM_ITERATIONS; i++){
        BlackScholesGPU<<<256, 128>>>(
            d_CallResult,
            d_PutResult,
            d_OptionStrike,
            d_StockPrice,
            d_OptionYears,
            RISKFREE,
            VOLATILITY,
            OPT_N
        );      
    }

    hipMemcpy(h_CallResultGPU, d_CallResult, OPT_SZ, hipMemcpyDeviceToHost);
    hipMemcpy(h_PutResultGPU,  d_PutResult,  OPT_SZ, hipMemcpyDeviceToHost);   

    //for(i = 0; i < OPT_N; i++)
    //    printf("%.15f,", h_CallResultGPU[i]);

  return 0;
}
	.text
	.file	"black_scholes.hip"
	.globl	_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi # -- Begin function _Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi
	.type	_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi,@function
_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi: # @_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15BlackScholesGPUPdS_S_S_S_ddi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi, .Lfunc_end0-_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z10RandDoubledd
.LCPI1_0:
	.quad	0x41dfffffffc00000              # double 2147483647
.LCPI1_1:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z10RandDoubledd
	.type	_Z10RandDoubledd,@function
_Z10RandDoubledd:                       # @_Z10RandDoubledd
	.cfi_startproc
# %bb.0:
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movsd	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	mulsd	8(%rsp), %xmm1                  # 8-byte Folded Reload
	mulsd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	addsd	%xmm1, %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z10RandDoubledd, .Lfunc_end1-_Z10RandDoubledd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x41dfffffffc00000              # double 2147483647
.LCPI2_1:
	.quad	0x3ff0000000000000              # double 1
.LCPI2_2:
	.quad	0x4014000000000000              # double 5
.LCPI2_3:
	.quad	0x403e000000000000              # double 30
.LCPI2_4:
	.quad	0x4059000000000000              # double 100
.LCPI2_5:
	.quad	0x3fd0000000000000              # double 0.25
.LCPI2_6:
	.quad	0x4024000000000000              # double 10
.LCPI2_7:
	.quad	0x3f947ae147ae147b              # double 0.02
.LCPI2_8:
	.quad	0x3fd3333333333333              # double 0.29999999999999999
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$3200000, %edi                  # imm = 0x30D400
	callq	malloc
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movl	$3200000, %edi                  # imm = 0x30D400
	callq	malloc
	movq	%rax, %r14
	movl	$3200000, %edi                  # imm = 0x30D400
	callq	malloc
	movq	%rax, %r13
	movl	$3200000, %edi                  # imm = 0x30D400
	callq	malloc
	movq	%rax, %r12
	movl	$3200000, %edi                  # imm = 0x30D400
	callq	malloc
	movq	%rax, %r15
	leaq	48(%rsp), %rdi
	movl	$3200000, %esi                  # imm = 0x30D400
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$3200000, %esi                  # imm = 0x30D400
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$3200000, %esi                  # imm = 0x30D400
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$3200000, %esi                  # imm = 0x30D400
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$3200000, %esi                  # imm = 0x30D400
	callq	hipMalloc
	movl	$5347, %edi                     # imm = 0x14E3
	callq	srand
	xorl	%ebp, %ebp
	movabsq	$-4616189618054758400, %rbx     # imm = 0xBFF0000000000000
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rax                   # 8-byte Reload
	movq	$0, (%rax,%rbp,8)
	movq	%rbx, (%r14,%rbp,8)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm1, %xmm0
	movsd	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	mulsd	.LCPI2_2(%rip), %xmm1
	mulsd	.LCPI2_3(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movsd	%xmm0, (%r13,%rbp,8)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movsd	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	mulsd	.LCPI2_4(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movsd	%xmm0, (%r12,%rbp,8)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movsd	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	mulsd	.LCPI2_5(%rip), %xmm1
	mulsd	.LCPI2_6(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movsd	%xmm0, (%r15,%rbp,8)
	incq	%rbp
	cmpq	$400000, %rbp                   # imm = 0x61A80
	jne	.LBB2_1
# %bb.2:
	movabsq	$4294967424, %rbp               # imm = 0x100000080
	movq	32(%rsp), %rdi
	movl	$3200000, %edx                  # imm = 0x30D400
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$3200000, %edx                  # imm = 0x30D400
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$3200000, %edx                  # imm = 0x30D400
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$512, %ebx                      # imm = 0x200
	leaq	128(%rbp), %r15
	movq	8(%rsp), %r12                   # 8-byte Reload
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	16(%rsp), %r8
	movsd	.LCPI2_7(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI2_8(%rip), %xmm1           # xmm1 = mem[0],zero
	movl	$400000, %r9d                   # imm = 0x61A80
	callq	_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	decl	%ebx
	jne	.LBB2_3
# %bb.6:
	movq	48(%rsp), %rsi
	movl	$3200000, %edx                  # imm = 0x30D400
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movl	$3200000, %edx                  # imm = 0x30D400
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15BlackScholesGPUPdS_S_S_S_ddi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15BlackScholesGPUPdS_S_S_S_ddi,@object # @_Z15BlackScholesGPUPdS_S_S_S_ddi
	.section	.rodata,"a",@progbits
	.globl	_Z15BlackScholesGPUPdS_S_S_S_ddi
	.p2align	3, 0x0
_Z15BlackScholesGPUPdS_S_S_S_ddi:
	.quad	_Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi
	.size	_Z15BlackScholesGPUPdS_S_S_S_ddi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15BlackScholesGPUPdS_S_S_S_ddi"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__BlackScholesGPUPdS_S_S_S_ddi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15BlackScholesGPUPdS_S_S_S_ddi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15BlackScholesGPUPdS_S_S_S_ddi ; -- Begin function _Z15BlackScholesGPUPdS_S_S_S_ddi
	.globl	_Z15BlackScholesGPUPdS_S_S_S_ddi
	.p2align	8
	.type	_Z15BlackScholesGPUPdS_S_S_S_ddi,@function
_Z15BlackScholesGPUPdS_S_S_S_ddi:       ; @_Z15BlackScholesGPUPdS_S_S_S_ddi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b32 s33, s[0:1], 0x38
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e64 s33, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x20
	s_load_b256 s[16:23], s[0:1], 0x0
	s_load_b32 s0, s[2:3], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s6, 0x55555555
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s14, 0x6b47b09a
	s_mov_b32 s24, 0xbf559e2b
	s_mov_b32 s26, 0xd7f4df2e
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_mov_b32 s28, 0x16291751
	s_mov_b32 s30, 0x9b27acf1
	s_mov_b32 s34, 0x998ef7b6
	s_mov_b32 s36, 0xfefa39ef
	s_mov_b32 s38, 0x3b39803f
	s_mov_b32 s42, 0x1871100e
	s_mov_b32 s46, 0x652b82fe
	s_mov_b32 s48, 0xfca7ab0c
	s_mov_b32 s50, 0x6a5dcb37
	s_mov_b32 s52, 0x623fde64
	s_mov_b32 s54, 0x7c89e6b0
	s_mov_b32 s56, 0x14761f6e
	v_mul_f64 v[4:5], s[12:13], 0.5
	s_mul_i32 s40, s0, s4
	s_mov_b32 s58, 0x1852b7b0
	s_ashr_i32 s41, s40, 31
	s_mov_b32 s60, 0x11122322
	s_mov_b32 s62, 0x555502a1
	s_mov_b32 s64, 0x55555511
	s_mov_b32 s66, 11
	s_mov_b32 s68, 0x33d3d180
	s_mov_b32 s70, 0x4ef278d0
	s_mov_b32 s72, 0xd6f42943
	s_mov_b32 s74, 0x25f5e68
	s_mov_b32 s76, 0xe5a8325b
	s_mov_b32 s78, 0x3a92f8ec
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s15, 0x3fc38538
	s_mov_b32 s25, 0x3fc3ab76
	s_mov_b32 s27, 0x3fc7474d
	s_mov_b32 s29, 0x3fcc71c0
	s_mov_b32 s31, 0x3fd24924
	s_mov_b32 s35, 0x3fd99999
	s_mov_b32 s37, 0x3fe62e42
	s_mov_b32 s39, 0x3c7abc9e
	s_mov_b32 s43, 0x3fcda671
	s_lshl_b64 s[44:45], s[40:41], 3
	s_mov_b32 s47, 0x3ff71547
	s_mov_b32 s49, 0x3e928af3
	s_mov_b32 s51, 0x3e5ade15
	s_mov_b32 s53, 0x3ec71dee
	s_mov_b32 s55, 0x3efa0199
	s_mov_b32 s57, 0x3f2a01a0
	s_mov_b32 s59, 0x3f56c16c
	s_mov_b32 s61, 0x3f811111
	s_mov_b32 s63, 0x3fa55555
	s_mov_b32 s65, 0x3fc55555
	s_mov_b32 s67, 0x3fe00000
	s_mov_b32 s69, 0x3fd98845
	s_mov_b32 s71, 0xbffd23dd
	v_fma_f64 v[4:5], v[4:5], s[12:13], s[10:11]
	s_mov_b32 s73, 0x3ff548cd
	s_mov_b32 s75, 0x3ffc80ef
	s_mov_b32 s77, 0xbfd6d1f0
	s_mov_b32 s79, 0x3fd470bf
	s_mov_b32 s41, 0
	s_mov_b32 s80, 0x55555780
	s_mov_b32 s5, 0xbfe62e42
	s_mov_b32 s83, 0xbc7abc9e
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v6, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v2
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v3, vcc_lo
	s_mov_b32 s81, s7
	s_mov_b32 s4, s36
	s_mov_b32 s82, s38
	global_load_b64 v[10:11], v[10:11], off
	v_add_nc_u32_e32 v1, s40, v1
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[6:7]
	v_div_scale_f64 v[14:15], vcc_lo, v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[14:15], v[16:17]
	v_fma_f64 v[12:13], -v[12:13], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[18:19]
	v_div_fixup_f64 v[12:13], v[12:13], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e32 v[14:15], v[12:13]
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[14:15]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[14:15], v[14:15], v0
	v_frexp_exp_i32_f64_e32 v0, v[12:13]
	v_add_f64 v[16:17], v[14:15], 1.0
	v_add_f64 v[18:19], v[14:15], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[10:11]
	v_rcp_f64_e32 v[20:21], v[16:17]
	v_add_f64 v[22:23], v[16:17], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[16:17], v[20:21], 1.0
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], -v[16:17], v[20:21], 1.0
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[18:19], v[20:21]
	v_mul_f64 v[24:25], v[16:17], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[22:23], v[16:17], -v[24:25]
	v_fma_f64 v[14:15], v[22:23], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[24:25], v[14:15]
	v_add_f64 v[26:27], v[18:19], -v[16:17]
	v_add_f64 v[24:25], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_add_f64 v[14:15], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[26:27], v[14:15]
	v_mul_f64 v[14:15], v[20:21], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[22:23], v[14:15]
	v_mul_f64 v[18:19], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[14:15]
	v_mul_f64 v[24:25], v[16:17], v[18:19]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[28:29]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[34:35]
	v_fma_f64 v[18:19], v[18:19], v[20:21], s[80:81]
	v_ldexp_f64 v[20:21], v[16:17], 1
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[18:19], v[24:25], v[18:19]
	v_cvt_f64_i32_e32 v[24:25], v0
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v0, 8, v0
	v_ldexp_f64 v[30:31], v[10:11], v0
	v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
	v_add_f64 v[22:23], v[20:21], v[18:19]
	v_mul_f64 v[26:27], v[24:25], s[36:37]
	v_ldexp_f64 v[14:15], v[14:15], 1
	v_rsq_f64_e32 v[34:35], v[30:31]
	v_cmp_class_f64_e64 s0, v[30:31], 0x260
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[22:23], -v[20:21]
	v_fma_f64 v[20:21], v[24:25], s[36:37], -v[26:27]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[36:37], v[30:31], v[34:35]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[24:25], s[38:39], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], v[16:17]
	v_add_f64 v[16:17], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[22:23], v[14:15]
	v_add_f64 v[26:27], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[16:17], v[20:21]
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[16:17]
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	v_mul_f64 v[22:23], v[34:35], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[32:33], v[24:25], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	v_add_f64 v[26:27], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[32:33]
	v_add_f64 v[28:29], v[26:27], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[20:21], v[16:17]
	v_fma_f64 v[20:21], -v[22:23], v[36:37], 0.5
	v_add_f64 v[14:15], v[14:15], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[26:27], v[16:17]
	v_fma_f64 v[32:33], v[36:37], v[20:21], v[36:37]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_add_f64 v[22:23], v[26:27], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[24:25], v[16:17]
	v_fma_f64 v[34:35], -v[32:33], v[32:33], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[26:27], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[34:35], v[20:21], v[32:33]
	v_add_f64 v[14:15], v[14:15], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_fma_f64 v[18:19], -v[24:25], v[24:25], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], v[16:17]
	v_fma_f64 v[16:17], v[18:19], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[26:27], v[14:15]
	v_ldexp_f64 v[16:17], v[16:17], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v14, v12, vcc_lo
	v_cndmask_b32_e64 v17, v17, v31, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, v30, s0
	v_cndmask_b32_e32 v14, v15, v13, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[12:13]
	v_cmp_ngt_f64_e64 s0, 0, v[12:13]
	v_mul_f64 v[18:19], v[16:17], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, 0x7ff80000, v14, s0
	v_cndmask_b32_e32 v14, 0, v0, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[12:13]
	v_cndmask_b32_e32 v15, 0xfff00000, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[4:5], v[10:11], v[14:15]
	v_mul_f64 v[10:11], v[10:11], -s[10:11]
	v_div_scale_f64 v[14:15], null, v[18:19], v[18:19], v[12:13]
	v_div_scale_f64 v[24:25], vcc_lo, v[12:13], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f64 v[28:29], v[10:11], s[46:47]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[10:11]
	v_rcp_f64_e32 v[20:21], v[14:15]
	v_rndne_f64_e32 v[28:29], v[28:29]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
	v_fma_f64 v[42:43], v[28:29], s[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
	v_fma_f64 v[42:43], v[28:29], s[82:83], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
	v_fma_f64 v[50:51], v[42:43], s[50:51], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
	v_mul_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[14:15], v[22:23], v[24:25]
	v_div_fmas_f64 v[14:15], v[14:15], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[12:13], v[14:15], v[18:19], v[12:13]
	v_mul_f64 v[14:15], v[12:13], -0.5
	v_fma_f64 v[16:17], -v[16:17], s[12:13], v[12:13]
	v_fma_f64 v[24:25], |v[12:13]|, s[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[12:13], v[14:15]
	v_mul_f64 v[18:19], v[16:17], -0.5
	v_fma_f64 v[32:33], |v[16:17]|, s[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[30:31], null, v[24:25], v[24:25], 1.0
	v_mul_f64 v[20:21], v[14:15], s[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[18:19], v[16:17], v[18:19]
	v_div_scale_f64 v[38:39], null, v[32:33], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[36:37], v[30:31]
	v_rndne_f64_e32 v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[22:23], v[18:19], s[46:47]
	v_rcp_f64_e32 v[46:47], v[38:39]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[48:49], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[26:27], v[20:21], s[4:5], v[14:15]
	v_rndne_f64_e32 v[22:23], v[22:23]
	v_cvt_i32_f64_e32 v0, v[20:21]
	v_fma_f64 v[52:53], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[36:37], v[36:37], v[48:49], v[36:37]
	v_fma_f64 v[48:49], v[42:43], v[50:51], s[52:53]
	v_fma_f64 v[26:27], v[20:21], s[82:83], v[26:27]
	v_fma_f64 v[34:35], v[22:23], s[4:5], v[18:19]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[18:19]
	v_fma_f64 v[46:47], v[46:47], v[52:53], v[46:47]
	v_div_scale_f64 v[52:53], vcc_lo, 1.0, v[24:25], 1.0
	v_fma_f64 v[50:51], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[54:55]
	v_fma_f64 v[40:41], v[26:27], s[50:51], s[48:49]
	v_fma_f64 v[34:35], v[22:23], s[82:83], v[34:35]
	v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[36:37], v[36:37], v[50:51], v[36:37]
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[56:57]
	v_div_scale_f64 v[50:51], s0, 1.0, v[32:33], 1.0
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[52:53]
	v_fma_f64 v[44:45], v[34:35], s[50:51], s[48:49]
	v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47]
	v_mul_f64 v[54:55], v[52:53], v[36:37]
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[58:59]
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[54:55]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[52:53]
	v_mul_f64 v[56:57], v[50:51], v[46:47]
	v_fma_f64 v[30:31], -v[30:31], v[54:55], v[52:53]
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[60:61]
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[56:57]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[54:55]
	v_fma_f64 v[38:39], -v[38:39], v[56:57], v[50:51]
	v_div_fmas_f64 v[30:31], v[30:31], v[36:37], v[54:55]
	s_mov_b32 vcc_lo, s0
	v_fma_f64 v[36:37], v[42:43], v[48:49], s[62:63]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[14:15]
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[58:59]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[56:57]
	v_div_fmas_f64 v[38:39], v[38:39], v[46:47], v[56:57]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[14:15]
	v_div_fixup_f64 v[24:25], v[30:31], v[24:25], 1.0
	v_fma_f64 v[30:31], v[42:43], v[36:37], s[64:65]
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[60:61]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[58:59]
	v_div_fixup_f64 v[32:33], v[38:39], v[32:33], 1.0
	v_fma_f64 v[38:39], v[24:25], s[72:73], s[70:71]
	v_fma_f64 v[30:31], v[42:43], v[30:31], s[66:67]
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[62:63]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[38:39], v[24:25], v[38:39], s[74:75]
	v_fma_f64 v[30:31], v[42:43], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[64:65]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[62:63]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[40:41], v[26:27], v[40:41], s[66:67]
	v_fma_f64 v[44:45], v[34:35], v[44:45], s[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[40:41], v[26:27], v[40:41], 1.0
	v_fma_f64 v[36:37], v[34:35], v[44:45], s[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[26:27], v[40:41], 1.0
	v_fma_f64 v[20:21], v[34:35], v[36:37], 1.0
	v_fma_f64 v[36:37], v[32:33], s[72:73], s[70:71]
	v_cvt_i32_f64_e32 v40, v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[22:23], v[26:27], v0
	v_fma_f64 v[20:21], v[34:35], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[26:27], v[32:33], v[36:37], s[74:75]
	v_fma_f64 v[34:35], v[24:25], v[38:39], s[76:77]
	v_cvt_i32_f64_e32 v0, v[28:29]
	v_fma_f64 v[28:29], v[42:43], v[30:31], 1.0
	v_mul_f64 v[22:23], v[22:23], s[68:69]
	v_ldexp_f64 v[20:21], v[20:21], v40
	v_fma_f64 v[26:27], v[32:33], v[26:27], s[76:77]
	v_fma_f64 v[30:31], v[24:25], v[34:35], s[78:79]
	v_ldexp_f64 v[28:29], v[28:29], v0
	v_cndmask_b32_e32 v0, 0x7ff00000, v23, vcc_lo
	v_mul_f64 v[20:21], v[20:21], s[68:69]
	v_fma_f64 v[14:15], v[32:33], v[26:27], s[78:79]
	v_mul_f64 v[23:24], v[24:25], v[30:31]
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e64 v11, 0, v0, s0
	v_cndmask_b32_e32 v10, 0, v22, vcc_lo
	v_cmp_lt_f64_e32 vcc_lo, 0, v[12:13]
	s_and_b32 s0, s2, s1
	v_cndmask_b32_e64 v25, 0x7ff00000, v29, s1
	v_cndmask_b32_e64 v12, 0, v28, s0
	s_and_b32 s0, s4, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, v25, s2
	v_mul_f64 v[8:9], v[8:9], v[12:13]
	v_cndmask_b32_e64 v0, 0x7ff00000, v21, s3
	v_mul_f64 v[14:15], v[32:33], v[14:15]
	v_mul_f64 v[18:19], v[23:24], v[10:11]
	v_fma_f64 v[10:11], -v[23:24], v[10:11], 1.0
	v_cndmask_b32_e64 v20, 0, v20, s0
	v_cndmask_b32_e64 v21, 0, v0, s4
	v_cmp_lt_f64_e64 s0, 0, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[14:15], v[20:21]
	v_fma_f64 v[14:15], -v[14:15], v[20:21], 1.0
	v_dual_cndmask_b32 v11, v19, v11 :: v_dual_cndmask_b32 v10, v18, v10
	v_add_f64 v[12:13], -v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v23, v15, s0
	v_cndmask_b32_e64 v14, v22, v14, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[16:17], v[8:9], v[14:15]
	v_add_f64 v[14:15], -v[14:15], 1.0
	v_mul_f64 v[12:13], v[6:7], v[12:13]
	v_fma_f64 v[6:7], v[6:7], v[10:11], -v[16:17]
	v_add_co_u32 v10, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[14:15], -v[12:13]
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v12, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s19, v3, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s33, v1
	v_add_co_u32 v2, s0, v2, s44
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s45, v3, s0
	s_or_b32 s41, vcc_lo, s41
	global_store_b64 v[10:11], v[6:7], off
	global_store_b64 v[12:13], v[8:9], off
	s_and_not1_b32 exec_lo, exec_lo, s41
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow48
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15BlackScholesGPUPdS_S_S_S_ddi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 84
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15BlackScholesGPUPdS_S_S_S_ddi, .Lfunc_end0-_Z15BlackScholesGPUPdS_S_S_S_ddi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3000
; NumSgprs: 86
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 86
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15BlackScholesGPUPdS_S_S_S_ddi
    .private_segment_fixed_size: 0
    .sgpr_count:     86
    .sgpr_spill_count: 0
    .symbol:         _Z15BlackScholesGPUPdS_S_S_S_ddi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
