#include <cuda.h>

/*Lx2Cuda performs the 2-D convolution of matrices A and row vector B*/
__global__ void Lx2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
        d_out[Col*numRows+Row]=mask[0]*d_in[Col*numRows+Row]+
                mask[1]*(d_in[(Col-1)*numRows+Row]+d_in[(Col+1)*numRows+Row])+
                mask[2]*(d_in[(Col-2)*numRows+Row]+d_in[(Col+2)*numRows+Row])+
                mask[3]*(d_in[(Col-3)*numRows+Row]+d_in[(Col+3)*numRows+Row])+
                mask[4]*(d_in[(Col-4)*numRows+Row]+d_in[(Col+4)*numRows+Row])+
                mask[5]*(d_in[(Col-5)*numRows+Row]+d_in[(Col+5)*numRows+Row]);
    }
}

/*Lz2 performs the 2-D convolution of matrices A and column vector B*/
__global__ void Lz2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
   
    // each thread computes one elements 
    if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
        int Loc = Col*numRows+Row;
        d_out[Loc]=mask[0]*d_in[Loc]+
                mask[1]*(d_in[Loc-1]+d_in[Loc+1])+
                mask[2]*(d_in[Loc-2]+d_in[Loc+2])+
                mask[3]*(d_in[Loc-3]+d_in[Loc+3])+
                mask[4]*(d_in[Loc-4]+d_in[Loc+4])+
                mask[5]*(d_in[Loc-5]+d_in[Loc+5]);
    }
}

/*Lz1 performs the 2-D convolution of matrices A and column vector C1*/
__global__ void Lz1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        int Loc = Col*numRows+Row;
        d_out[Loc]=
                mask[0]*(d_in[Loc+1]-d_in[Loc-1])+
                mask[1]*(d_in[Loc+2]-d_in[Loc-2])+
                mask[2]*(d_in[Loc+3]-d_in[Loc-3])+
                mask[3]*(d_in[Loc+4]-d_in[Loc-4])+
                mask[4]*(d_in[Loc+5]-d_in[Loc-5])+
                mask[5]*(d_in[Loc+6]-d_in[Loc-6]);
    }
}

/*Lx1 performs the 2-D convolution of matrices A and row vector C1*/
__global__ void Lx1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
                mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
                mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
                mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
                mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
                mask[5]*(d_in[(Col+6)*numRows+Row]-d_in[(Col-6)*numRows+Row]);
    }

}

/*sbLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sbLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-0)*numRows+Row])+
                mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
                mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
                mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
                mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
                mask[5]*(d_in[(Col+6)*numRows+Row]+d_in[(Col-5)*numRows+Row]);
    }

}

/*sfLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sfLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[(Col+0)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
                mask[1]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
                mask[2]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
                mask[3]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
                mask[4]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
                mask[5]*(d_in[(Col+5)*numRows+Row]+d_in[(Col-6)*numRows+Row]);
    }
}
/*sbLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sbLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;

    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        int Loc = Col*numRows+Row;
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[Loc+1]-d_in[Loc-0])+
                mask[1]*(d_in[Loc+2]-d_in[Loc-1])+
                mask[2]*(d_in[Loc+3]-d_in[Loc-2])+
                mask[3]*(d_in[Loc+4]-d_in[Loc-3])+
                mask[4]*(d_in[Loc+5]-d_in[Loc-4])+
                mask[5]*(d_in[Loc+6]+d_in[Loc-5]);
    }

}
/*sfLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sfLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        int Loc = Col*numRows+Row;
        d_out[Loc]=
                mask[0]*(d_in[Loc+0]-d_in[Loc-1])+
                mask[1]*(d_in[Loc+1]-d_in[Loc-2])+
                mask[2]*(d_in[Loc+2]-d_in[Loc-3])+
                mask[3]*(d_in[Loc+3]-d_in[Loc-4])+
                mask[4]*(d_in[Loc+4]-d_in[Loc-5])+
                mask[5]*(d_in[Loc+5]+d_in[Loc-6]);
    }

}
/*rsgffd performs the 2-D forward rotated staggered-grid finite difference*/
__global__ void rsgffd(const float *d_in,float *d_outx,float *d_outz,const int numRows,int numCols,float *mask)
{
    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){

        d_outx[Col*numRows+Row]=
                    mask[0]*(d_in[(Col+1)*numRows+Row-0]-d_in[(Col-0)*numRows+Row+1])+
                    mask[1]*(d_in[(Col+2)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+2])+
                    mask[2]*(d_in[(Col+3)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+3])+
                    mask[3]*(d_in[(Col+4)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+4])+
                    mask[4]*(d_in[(Col+5)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+5])+
                    mask[5]*(d_in[(Col+6)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+6]);
        d_outz[Col*numRows+Row]=
                    mask[0]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-0)*numRows+Row-0])+
                    mask[1]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-1)*numRows+Row-1])+
                    mask[2]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-2)*numRows+Row-2])+
                    mask[3]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-3)*numRows+Row-3])+
                    mask[4]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-4)*numRows+Row-4])+
                    mask[5]*(d_in[(Col+6)*numRows+Row+6]-d_in[(Col-5)*numRows+Row-5]);
    }
}

/*rsgbfd performs the 2-D backward rotated staggered-grid finite difference*/
__global__ void rsgbfd(const float *d_in,float *d_outx,float *d_outz,int numRows,int numCols,float *mask)
{
    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_outx[Col*numRows+Row]= 
                    mask[0]*(d_in[(Col+0)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+0])+
                    mask[1]*(d_in[(Col+1)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+1])+
                    mask[2]*(d_in[(Col+2)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+2])+
                    mask[3]*(d_in[(Col+3)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+3])+
                    mask[4]*(d_in[(Col+4)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+4])+
                    mask[5]*(d_in[(Col+5)*numRows+Row-6]-d_in[(Col-6)*numRows+Row+5]);
        d_outz[Col*numRows+Row]= 
                    mask[0]*(d_in[(Col+0)*numRows+Row+0]-d_in[(Col-1)*numRows+Row-1])+
                    mask[1]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-2)*numRows+Row-2])+
                    mask[2]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-3)*numRows+Row-3])+
                    mask[3]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-4)*numRows+Row-4])+
                    mask[4]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-5)*numRows+Row-5])+
                    mask[5]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-6)*numRows+Row-6]);
    }
}





	.file	"tmpxft_002b0110_00000000-6_gfconvn.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
	.type	_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3Lx2PKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
	.globl	_Z3Lx2PKfPfiiS1_
	.type	_Z3Lx2PKfPfiiS1_, @function
_Z3Lx2PKfPfiiS1_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2033:
	.size	_Z3Lx2PKfPfiiS1_, .-_Z3Lx2PKfPfiiS1_
	.globl	_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
	.type	_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3Lz2PKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
	.globl	_Z3Lz2PKfPfiiS1_
	.type	_Z3Lz2PKfPfiiS1_, @function
_Z3Lz2PKfPfiiS1_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2035:
	.size	_Z3Lz2PKfPfiiS1_, .-_Z3Lz2PKfPfiiS1_
	.globl	_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
	.type	_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3Lz1PKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
	.globl	_Z3Lz1PKfPfiiS1_
	.type	_Z3Lz1PKfPfiiS1_, @function
_Z3Lz1PKfPfiiS1_:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2037:
	.size	_Z3Lz1PKfPfiiS1_, .-_Z3Lz1PKfPfiiS1_
	.globl	_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
	.type	_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3Lx1PKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
	.globl	_Z3Lx1PKfPfiiS1_
	.type	_Z3Lx1PKfPfiiS1_, @function
_Z3Lx1PKfPfiiS1_:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2039:
	.size	_Z3Lx1PKfPfiiS1_, .-_Z3Lx1PKfPfiiS1_
	.globl	_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
	.type	_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4sbLxPKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
	.globl	_Z4sbLxPKfPfiiS1_
	.type	_Z4sbLxPKfPfiiS1_, @function
_Z4sbLxPKfPfiiS1_:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2041:
	.size	_Z4sbLxPKfPfiiS1_, .-_Z4sbLxPKfPfiiS1_
	.globl	_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
	.type	_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4sfLxPKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L28:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
	.globl	_Z4sfLxPKfPfiiS1_
	.type	_Z4sfLxPKfPfiiS1_, @function
_Z4sfLxPKfPfiiS1_:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2043:
	.size	_Z4sfLxPKfPfiiS1_, .-_Z4sfLxPKfPfiiS1_
	.globl	_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
	.type	_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4sbLzPKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
	.globl	_Z4sbLzPKfPfiiS1_
	.type	_Z4sbLzPKfPfiiS1_, @function
_Z4sbLzPKfPfiiS1_:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2045:
	.size	_Z4sbLzPKfPfiiS1_, .-_Z4sbLzPKfPfiiS1_
	.globl	_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
	.type	_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4sfLzPKfPfiiS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L38:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
	.globl	_Z4sfLzPKfPfiiS1_
	.type	_Z4sfLzPKfPfiiS1_, @function
_Z4sfLzPKfPfiiS1_:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
	.cfi_endproc
.LFE2047:
	.size	_Z4sfLzPKfPfiiS1_, .-_Z4sfLzPKfPfiiS1_
	.globl	_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
	.type	_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_, @function
_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_:
.LFB2048:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z6rsgffdPKfPfS1_iiS1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L43:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_, .-_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
	.globl	_Z6rsgffdPKfPfS1_iiS1_
	.type	_Z6rsgffdPKfPfS1_iiS1_, @function
_Z6rsgffdPKfPfS1_iiS1_:
.LFB2049:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
	.cfi_endproc
.LFE2049:
	.size	_Z6rsgffdPKfPfS1_iiS1_, .-_Z6rsgffdPKfPfS1_iiS1_
	.globl	_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
	.type	_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_, @function
_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_:
.LFB2050:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z6rsgbfdPKfPfS1_iiS1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L48:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_, .-_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
	.globl	_Z6rsgbfdPKfPfS1_iiS1_
	.type	_Z6rsgbfdPKfPfS1_iiS1_, @function
_Z6rsgbfdPKfPfS1_iiS1_:
.LFB2051:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
	.cfi_endproc
.LFE2051:
	.size	_Z6rsgbfdPKfPfS1_iiS1_, .-_Z6rsgbfdPKfPfS1_iiS1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6rsgbfdPKfPfS1_iiS1_"
.LC1:
	.string	"_Z6rsgffdPKfPfS1_iiS1_"
.LC2:
	.string	"_Z4sfLzPKfPfiiS1_"
.LC3:
	.string	"_Z4sbLzPKfPfiiS1_"
.LC4:
	.string	"_Z4sfLxPKfPfiiS1_"
.LC5:
	.string	"_Z4sbLxPKfPfiiS1_"
.LC6:
	.string	"_Z3Lx1PKfPfiiS1_"
.LC7:
	.string	"_Z3Lz1PKfPfiiS1_"
.LC8:
	.string	"_Z3Lz2PKfPfiiS1_"
.LC9:
	.string	"_Z3Lx2PKfPfiiS1_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6rsgbfdPKfPfS1_iiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6rsgffdPKfPfS1_iiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z4sfLzPKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z4sbLzPKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z4sfLxPKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z4sbLxPKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z3Lx1PKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z3Lz1PKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z3Lz2PKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3Lx2PKfPfiiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2053:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>

/*Lx2Cuda performs the 2-D convolution of matrices A and row vector B*/
__global__ void Lx2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
        d_out[Col*numRows+Row]=mask[0]*d_in[Col*numRows+Row]+
                mask[1]*(d_in[(Col-1)*numRows+Row]+d_in[(Col+1)*numRows+Row])+
                mask[2]*(d_in[(Col-2)*numRows+Row]+d_in[(Col+2)*numRows+Row])+
                mask[3]*(d_in[(Col-3)*numRows+Row]+d_in[(Col+3)*numRows+Row])+
                mask[4]*(d_in[(Col-4)*numRows+Row]+d_in[(Col+4)*numRows+Row])+
                mask[5]*(d_in[(Col-5)*numRows+Row]+d_in[(Col+5)*numRows+Row]);
    }
}

/*Lz2 performs the 2-D convolution of matrices A and column vector B*/
__global__ void Lz2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
   
    // each thread computes one elements 
    if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
        int Loc = Col*numRows+Row;
        d_out[Loc]=mask[0]*d_in[Loc]+
                mask[1]*(d_in[Loc-1]+d_in[Loc+1])+
                mask[2]*(d_in[Loc-2]+d_in[Loc+2])+
                mask[3]*(d_in[Loc-3]+d_in[Loc+3])+
                mask[4]*(d_in[Loc-4]+d_in[Loc+4])+
                mask[5]*(d_in[Loc-5]+d_in[Loc+5]);
    }
}

/*Lz1 performs the 2-D convolution of matrices A and column vector C1*/
__global__ void Lz1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        int Loc = Col*numRows+Row;
        d_out[Loc]=
                mask[0]*(d_in[Loc+1]-d_in[Loc-1])+
                mask[1]*(d_in[Loc+2]-d_in[Loc-2])+
                mask[2]*(d_in[Loc+3]-d_in[Loc-3])+
                mask[3]*(d_in[Loc+4]-d_in[Loc-4])+
                mask[4]*(d_in[Loc+5]-d_in[Loc-5])+
                mask[5]*(d_in[Loc+6]-d_in[Loc-6]);
    }
}

/*Lx1 performs the 2-D convolution of matrices A and row vector C1*/
__global__ void Lx1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
                mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
                mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
                mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
                mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
                mask[5]*(d_in[(Col+6)*numRows+Row]-d_in[(Col-6)*numRows+Row]);
    }

}

/*sbLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sbLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-0)*numRows+Row])+
                mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
                mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
                mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
                mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
                mask[5]*(d_in[(Col+6)*numRows+Row]+d_in[(Col-5)*numRows+Row]);
    }

}

/*sfLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sfLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[(Col+0)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
                mask[1]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
                mask[2]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
                mask[3]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
                mask[4]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
                mask[5]*(d_in[(Col+5)*numRows+Row]+d_in[(Col-6)*numRows+Row]);
    }
}
/*sbLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sbLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;

    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        int Loc = Col*numRows+Row;
        d_out[Col*numRows+Row]=
                mask[0]*(d_in[Loc+1]-d_in[Loc-0])+
                mask[1]*(d_in[Loc+2]-d_in[Loc-1])+
                mask[2]*(d_in[Loc+3]-d_in[Loc-2])+
                mask[3]*(d_in[Loc+4]-d_in[Loc-3])+
                mask[4]*(d_in[Loc+5]-d_in[Loc-4])+
                mask[5]*(d_in[Loc+6]+d_in[Loc-5]);
    }

}
/*sfLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sfLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{

    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        int Loc = Col*numRows+Row;
        d_out[Loc]=
                mask[0]*(d_in[Loc+0]-d_in[Loc-1])+
                mask[1]*(d_in[Loc+1]-d_in[Loc-2])+
                mask[2]*(d_in[Loc+2]-d_in[Loc-3])+
                mask[3]*(d_in[Loc+3]-d_in[Loc-4])+
                mask[4]*(d_in[Loc+4]-d_in[Loc-5])+
                mask[5]*(d_in[Loc+5]+d_in[Loc-6]);
    }

}
/*rsgffd performs the 2-D forward rotated staggered-grid finite difference*/
__global__ void rsgffd(const float *d_in,float *d_outx,float *d_outz,const int numRows,int numCols,float *mask)
{
    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){

        d_outx[Col*numRows+Row]=
                    mask[0]*(d_in[(Col+1)*numRows+Row-0]-d_in[(Col-0)*numRows+Row+1])+
                    mask[1]*(d_in[(Col+2)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+2])+
                    mask[2]*(d_in[(Col+3)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+3])+
                    mask[3]*(d_in[(Col+4)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+4])+
                    mask[4]*(d_in[(Col+5)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+5])+
                    mask[5]*(d_in[(Col+6)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+6]);
        d_outz[Col*numRows+Row]=
                    mask[0]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-0)*numRows+Row-0])+
                    mask[1]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-1)*numRows+Row-1])+
                    mask[2]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-2)*numRows+Row-2])+
                    mask[3]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-3)*numRows+Row-3])+
                    mask[4]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-4)*numRows+Row-4])+
                    mask[5]*(d_in[(Col+6)*numRows+Row+6]-d_in[(Col-5)*numRows+Row-5]);
    }
}

/*rsgbfd performs the 2-D backward rotated staggered-grid finite difference*/
__global__ void rsgbfd(const float *d_in,float *d_outx,float *d_outz,int numRows,int numCols,float *mask)
{
    //Calculate the row # of the d_in and d_out element to process
    int Col = blockIdx.y*blockDim.y + threadIdx.y;
    
    //Calculate the column # of the d_in and d_out element to process
    int Row = blockIdx.x*blockDim.x + threadIdx.x;
    
    // each thread computes one elements 
    if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
        d_outx[Col*numRows+Row]= 
                    mask[0]*(d_in[(Col+0)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+0])+
                    mask[1]*(d_in[(Col+1)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+1])+
                    mask[2]*(d_in[(Col+2)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+2])+
                    mask[3]*(d_in[(Col+3)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+3])+
                    mask[4]*(d_in[(Col+4)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+4])+
                    mask[5]*(d_in[(Col+5)*numRows+Row-6]-d_in[(Col-6)*numRows+Row+5]);
        d_outz[Col*numRows+Row]= 
                    mask[0]*(d_in[(Col+0)*numRows+Row+0]-d_in[(Col-1)*numRows+Row-1])+
                    mask[1]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-2)*numRows+Row-2])+
                    mask[2]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-3)*numRows+Row-3])+
                    mask[3]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-4)*numRows+Row-4])+
                    mask[4]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-5)*numRows+Row-5])+
                    mask[5]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-6)*numRows+Row-6]);
    }
}





	.text
	.file	"gfconvn.hip"
	.globl	_Z18__device_stub__Lx2PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lx2PKfPfiiS1_
	.type	_Z18__device_stub__Lx2PKfPfiiS1_,@function
_Z18__device_stub__Lx2PKfPfiiS1_:       # @_Z18__device_stub__Lx2PKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3Lx2PKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__Lx2PKfPfiiS1_, .Lfunc_end0-_Z18__device_stub__Lx2PKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__Lz2PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lz2PKfPfiiS1_
	.type	_Z18__device_stub__Lz2PKfPfiiS1_,@function
_Z18__device_stub__Lz2PKfPfiiS1_:       # @_Z18__device_stub__Lz2PKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3Lz2PKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__Lz2PKfPfiiS1_, .Lfunc_end1-_Z18__device_stub__Lz2PKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__Lz1PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lz1PKfPfiiS1_
	.type	_Z18__device_stub__Lz1PKfPfiiS1_,@function
_Z18__device_stub__Lz1PKfPfiiS1_:       # @_Z18__device_stub__Lz1PKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3Lz1PKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z18__device_stub__Lz1PKfPfiiS1_, .Lfunc_end2-_Z18__device_stub__Lz1PKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__Lx1PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lx1PKfPfiiS1_
	.type	_Z18__device_stub__Lx1PKfPfiiS1_,@function
_Z18__device_stub__Lx1PKfPfiiS1_:       # @_Z18__device_stub__Lx1PKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3Lx1PKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z18__device_stub__Lx1PKfPfiiS1_, .Lfunc_end3-_Z18__device_stub__Lx1PKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__sbLxPKfPfiiS1_ # -- Begin function _Z19__device_stub__sbLxPKfPfiiS1_
	.type	_Z19__device_stub__sbLxPKfPfiiS1_,@function
_Z19__device_stub__sbLxPKfPfiiS1_:      # @_Z19__device_stub__sbLxPKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4sbLxPKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z19__device_stub__sbLxPKfPfiiS1_, .Lfunc_end4-_Z19__device_stub__sbLxPKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__sfLxPKfPfiiS1_ # -- Begin function _Z19__device_stub__sfLxPKfPfiiS1_
	.type	_Z19__device_stub__sfLxPKfPfiiS1_,@function
_Z19__device_stub__sfLxPKfPfiiS1_:      # @_Z19__device_stub__sfLxPKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4sfLxPKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z19__device_stub__sfLxPKfPfiiS1_, .Lfunc_end5-_Z19__device_stub__sfLxPKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__sbLzPKfPfiiS1_ # -- Begin function _Z19__device_stub__sbLzPKfPfiiS1_
	.type	_Z19__device_stub__sbLzPKfPfiiS1_,@function
_Z19__device_stub__sbLzPKfPfiiS1_:      # @_Z19__device_stub__sbLzPKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4sbLzPKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z19__device_stub__sbLzPKfPfiiS1_, .Lfunc_end6-_Z19__device_stub__sbLzPKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__sfLzPKfPfiiS1_ # -- Begin function _Z19__device_stub__sfLzPKfPfiiS1_
	.type	_Z19__device_stub__sfLzPKfPfiiS1_,@function
_Z19__device_stub__sfLzPKfPfiiS1_:      # @_Z19__device_stub__sfLzPKfPfiiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4sfLzPKfPfiiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z19__device_stub__sfLzPKfPfiiS1_, .Lfunc_end7-_Z19__device_stub__sfLzPKfPfiiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__rsgffdPKfPfS1_iiS1_ # -- Begin function _Z21__device_stub__rsgffdPKfPfS1_iiS1_
	.type	_Z21__device_stub__rsgffdPKfPfS1_iiS1_,@function
_Z21__device_stub__rsgffdPKfPfS1_iiS1_: # @_Z21__device_stub__rsgffdPKfPfS1_iiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6rsgffdPKfPfS1_iiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z21__device_stub__rsgffdPKfPfS1_iiS1_, .Lfunc_end8-_Z21__device_stub__rsgffdPKfPfS1_iiS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__rsgbfdPKfPfS1_iiS1_ # -- Begin function _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
	.type	_Z21__device_stub__rsgbfdPKfPfS1_iiS1_,@function
_Z21__device_stub__rsgbfdPKfPfS1_iiS1_: # @_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6rsgbfdPKfPfS1_iiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z21__device_stub__rsgbfdPKfPfS1_iiS1_, .Lfunc_end9-_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3Lx2PKfPfiiS1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3Lz2PKfPfiiS1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3Lz1PKfPfiiS1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3Lx1PKfPfiiS1_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4sbLxPKfPfiiS1_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4sfLxPKfPfiiS1_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4sbLzPKfPfiiS1_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4sfLzPKfPfiiS1_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6rsgffdPKfPfS1_iiS1_, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6rsgbfdPKfPfS1_iiS1_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3Lx2PKfPfiiS1_,@object        # @_Z3Lx2PKfPfiiS1_
	.section	.rodata,"a",@progbits
	.globl	_Z3Lx2PKfPfiiS1_
	.p2align	3, 0x0
_Z3Lx2PKfPfiiS1_:
	.quad	_Z18__device_stub__Lx2PKfPfiiS1_
	.size	_Z3Lx2PKfPfiiS1_, 8

	.type	_Z3Lz2PKfPfiiS1_,@object        # @_Z3Lz2PKfPfiiS1_
	.globl	_Z3Lz2PKfPfiiS1_
	.p2align	3, 0x0
_Z3Lz2PKfPfiiS1_:
	.quad	_Z18__device_stub__Lz2PKfPfiiS1_
	.size	_Z3Lz2PKfPfiiS1_, 8

	.type	_Z3Lz1PKfPfiiS1_,@object        # @_Z3Lz1PKfPfiiS1_
	.globl	_Z3Lz1PKfPfiiS1_
	.p2align	3, 0x0
_Z3Lz1PKfPfiiS1_:
	.quad	_Z18__device_stub__Lz1PKfPfiiS1_
	.size	_Z3Lz1PKfPfiiS1_, 8

	.type	_Z3Lx1PKfPfiiS1_,@object        # @_Z3Lx1PKfPfiiS1_
	.globl	_Z3Lx1PKfPfiiS1_
	.p2align	3, 0x0
_Z3Lx1PKfPfiiS1_:
	.quad	_Z18__device_stub__Lx1PKfPfiiS1_
	.size	_Z3Lx1PKfPfiiS1_, 8

	.type	_Z4sbLxPKfPfiiS1_,@object       # @_Z4sbLxPKfPfiiS1_
	.globl	_Z4sbLxPKfPfiiS1_
	.p2align	3, 0x0
_Z4sbLxPKfPfiiS1_:
	.quad	_Z19__device_stub__sbLxPKfPfiiS1_
	.size	_Z4sbLxPKfPfiiS1_, 8

	.type	_Z4sfLxPKfPfiiS1_,@object       # @_Z4sfLxPKfPfiiS1_
	.globl	_Z4sfLxPKfPfiiS1_
	.p2align	3, 0x0
_Z4sfLxPKfPfiiS1_:
	.quad	_Z19__device_stub__sfLxPKfPfiiS1_
	.size	_Z4sfLxPKfPfiiS1_, 8

	.type	_Z4sbLzPKfPfiiS1_,@object       # @_Z4sbLzPKfPfiiS1_
	.globl	_Z4sbLzPKfPfiiS1_
	.p2align	3, 0x0
_Z4sbLzPKfPfiiS1_:
	.quad	_Z19__device_stub__sbLzPKfPfiiS1_
	.size	_Z4sbLzPKfPfiiS1_, 8

	.type	_Z4sfLzPKfPfiiS1_,@object       # @_Z4sfLzPKfPfiiS1_
	.globl	_Z4sfLzPKfPfiiS1_
	.p2align	3, 0x0
_Z4sfLzPKfPfiiS1_:
	.quad	_Z19__device_stub__sfLzPKfPfiiS1_
	.size	_Z4sfLzPKfPfiiS1_, 8

	.type	_Z6rsgffdPKfPfS1_iiS1_,@object  # @_Z6rsgffdPKfPfS1_iiS1_
	.globl	_Z6rsgffdPKfPfS1_iiS1_
	.p2align	3, 0x0
_Z6rsgffdPKfPfS1_iiS1_:
	.quad	_Z21__device_stub__rsgffdPKfPfS1_iiS1_
	.size	_Z6rsgffdPKfPfS1_iiS1_, 8

	.type	_Z6rsgbfdPKfPfS1_iiS1_,@object  # @_Z6rsgbfdPKfPfS1_iiS1_
	.globl	_Z6rsgbfdPKfPfS1_iiS1_
	.p2align	3, 0x0
_Z6rsgbfdPKfPfS1_iiS1_:
	.quad	_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
	.size	_Z6rsgbfdPKfPfS1_iiS1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z3Lx2PKfPfiiS1_"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z3Lz2PKfPfiiS1_"
	.size	.L__unnamed_2, 17

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z3Lz1PKfPfiiS1_"
	.size	.L__unnamed_3, 17

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z3Lx1PKfPfiiS1_"
	.size	.L__unnamed_4, 17

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z4sbLxPKfPfiiS1_"
	.size	.L__unnamed_5, 18

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z4sfLxPKfPfiiS1_"
	.size	.L__unnamed_6, 18

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z4sbLzPKfPfiiS1_"
	.size	.L__unnamed_7, 18

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z4sfLzPKfPfiiS1_"
	.size	.L__unnamed_8, 18

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z6rsgffdPKfPfS1_iiS1_"
	.size	.L__unnamed_9, 23

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z6rsgbfdPKfPfS1_iiS1_"
	.size	.L__unnamed_10, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__Lx2PKfPfiiS1_
	.addrsig_sym _Z18__device_stub__Lz2PKfPfiiS1_
	.addrsig_sym _Z18__device_stub__Lz1PKfPfiiS1_
	.addrsig_sym _Z18__device_stub__Lx1PKfPfiiS1_
	.addrsig_sym _Z19__device_stub__sbLxPKfPfiiS1_
	.addrsig_sym _Z19__device_stub__sfLxPKfPfiiS1_
	.addrsig_sym _Z19__device_stub__sbLzPKfPfiiS1_
	.addrsig_sym _Z19__device_stub__sfLzPKfPfiiS1_
	.addrsig_sym _Z21__device_stub__rsgffdPKfPfS1_iiS1_
	.addrsig_sym _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3Lx2PKfPfiiS1_
	.addrsig_sym _Z3Lz2PKfPfiiS1_
	.addrsig_sym _Z3Lz1PKfPfiiS1_
	.addrsig_sym _Z3Lx1PKfPfiiS1_
	.addrsig_sym _Z4sbLxPKfPfiiS1_
	.addrsig_sym _Z4sfLxPKfPfiiS1_
	.addrsig_sym _Z4sbLzPKfPfiiS1_
	.addrsig_sym _Z4sfLzPKfPfiiS1_
	.addrsig_sym _Z6rsgffdPKfPfS1_iiS1_
	.addrsig_sym _Z6rsgbfdPKfPfS1_iiS1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3Lx2PKfPfiiS1_        ; -- Begin function _Z3Lx2PKfPfiiS1_
	.globl	_Z3Lx2PKfPfiiS1_
	.p2align	8
	.type	_Z3Lx2PKfPfiiS1_,@function
_Z3Lx2PKfPfiiS1_:                       ; @_Z3Lx2PKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s8, -5
	s_add_i32 s3, s9, -5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 4, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mul_lo_u32 v2, v1, s8
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[10:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v1, s8, v2
	v_add_nc_u32_e32 v11, v2, v0
	v_add_nc_u32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshl_add_u32 v3, s8, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v15, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, s8, -3, v[3:4]
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_lshl_add_u32 v7, s8, 2, v5
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v8, 31, v7
	s_clause 0x2
	global_load_b32 v19, v[15:16], off
	global_load_b32 v20, v[0:1], off
	global_load_b32 v21, v[2:3], off
	v_ashrrev_i32_e32 v6, 31, v5
	v_mad_u64_u32 v[9:10], null, s8, -5, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_lshlrev_b64 v[0:1], 2, v[7:8]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_mad_u64_u32 v[13:14], null, s8, 6, v[9:10]
	v_lshlrev_b64 v[6:7], 2, v[9:10]
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_mad_u64_u32 v[17:18], null, s8, -7, v[13:14]
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_lshl_add_u32 v2, s8, 3, v17
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 2, v[17:18]
	v_mad_u64_u32 v[8:9], null, s8, -9, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[17:18], null, s8, 10, v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_clause 0x5
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[0:1], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[13:14], off
	global_load_b32 v10, v[15:16], off
	global_load_b32 v13, v[2:3], off
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v2, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[17:18]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_clause 0x1
	s_load_b128 s[0:3], s[10:11], 0x0
	s_load_b64 s[4:5], s[10:11], 0x10
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v1, v20, v21 :: v_dual_add_f32 v0, v2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, s1, v1
	v_add_f32_e32 v1, v4, v5
	v_fmac_f32_e32 v3, s0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, s2, v1
	v_add_f32_e32 v1, v6, v7
	v_fmac_f32_e32 v3, s3, v1
	v_add_f32_e32 v1, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, s4, v1
	v_fmac_f32_e32 v3, s5, v0
	v_add_co_u32 v0, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v12, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3Lx2PKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3Lx2PKfPfiiS1_, .Lfunc_end0-_Z3Lx2PKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 816
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3Lz2PKfPfiiS1_        ; -- Begin function _Z3Lz2PKfPfiiS1_
	.globl	_Z3Lz2PKfPfiiS1_
	.p2align	8
	.type	_Z3Lz2PKfPfiiS1_,@function
_Z3Lz2PKfPfiiS1_:                       ; @_Z3Lz2PKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[6:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s6, -5
	s_add_i32 s3, s7, -5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 4, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v12, vcc_lo
	s_clause 0x2
	global_load_b128 v[0:3], v[8:9], off offset:-4
	global_load_b128 v[4:7], v[8:9], off offset:-20
	global_load_b96 v[8:10], v[8:9], off offset:12
	s_clause 0x1
	s_load_b128 s[0:3], s[4:5], 0x0
	s_load_b64 s[4:5], s[4:5], 0x10
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v0, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, s1, v0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v7, v3
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v2, s0, v1 :: v_dual_add_f32 v1, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, s2, v0
	v_add_f32_e32 v0, v5, v9
	v_dual_fmac_f32 v2, s3, v1 :: v_dual_add_f32 v1, v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, s4, v0
	v_add_co_u32 v0, vcc_lo, s10, v11
	v_fmac_f32_e32 v2, s5, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v12, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3Lz2PKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z3Lz2PKfPfiiS1_, .Lfunc_end1-_Z3Lz2PKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3Lz1PKfPfiiS1_        ; -- Begin function _Z3Lz1PKfPfiiS1_
	.globl	_Z3Lz1PKfPfiiS1_
	.p2align	8
	.type	_Z3Lz1PKfPfiiS1_,@function
_Z3Lz1PKfPfiiS1_:                       ; @_Z3Lz1PKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[6:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s6, -6
	s_add_i32 s3, s7, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v9, vcc_lo
	s_clause 0x3
	global_load_b128 v[0:3], v[10:11], off offset:4
	global_load_b64 v[12:13], v[10:11], off offset:-8
	global_load_b128 v[4:7], v[10:11], off offset:-24
	global_load_b64 v[10:11], v[10:11], off offset:20
	s_clause 0x1
	s_load_b128 s[0:3], s[4:5], 0x0
	s_load_b64 s[4:5], s[4:5], 0x10
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v1, v1, v12 :: v_dual_sub_f32 v0, v0, v13
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v12, s1, v1 :: v_dual_sub_f32 v1, v2, v7
	v_fmac_f32_e32 v12, s0, v0
	v_sub_f32_e32 v0, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, s2, v1
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v1, v10, v5 :: v_dual_fmac_f32 v12, s3, v0
	v_sub_f32_e32 v0, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, s4, v1
	v_fmac_f32_e32 v12, s5, v0
	v_add_co_u32 v0, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v9, vcc_lo
	global_store_b32 v[0:1], v12, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3Lz1PKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z3Lz1PKfPfiiS1_, .Lfunc_end2-_Z3Lz1PKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 368
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3Lx1PKfPfiiS1_        ; -- Begin function _Z3Lx1PKfPfiiS1_
	.globl	_Z3Lx1PKfPfiiS1_
	.p2align	8
	.type	_Z3Lx1PKfPfiiS1_,@function
_Z3Lx1PKfPfiiS1_:                       ; @_Z3Lx1PKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s8, -6
	s_add_i32 s3, s9, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_mul_lo_u32 v21, v1, s8
	s_lshl_b32 s2, s8, 1
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, s8, v21
	v_subrev_nc_u32_e32 v1, s2, v7
	s_lshl_b32 s2, s8, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s8, 3, v[1:2]
	v_add_nc_u32_e32 v8, v1, v0
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v3, s2, v2
	s_lshl_b32 s2, s8, 3
	v_add_nc_u32_e32 v1, v2, v0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, s8, 5, v[3:4]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_mad_u64_u32 v[5:6], null, s8, -6, v[4:5]
	v_add_nc_u32_e32 v6, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_mad_u64_u32 v[10:11], null, s8, 7, v[5:6]
	v_add_nc_u32_e32 v11, v3, v0
	v_add_nc_u32_e32 v3, v4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v17, v5, v0
	v_ashrrev_i32_e32 v4, 31, v3
	v_subrev_nc_u32_e32 v12, s2, v10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_add_nc_u32_e32 v13, v12, v0
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[15:16], null, s8, 9, v[13:14]
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_nc_u32_e32 v5, v10, v0
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	v_ashrrev_i32_e32 v18, 31, v17
	v_ashrrev_i32_e32 v16, 31, v15
	s_clause 0x3
	global_load_b32 v22, v[6:7], off
	global_load_b32 v23, v[8:9], off
	global_load_b32 v24, v[1:2], off
	global_load_b32 v25, v[11:12], off
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[1:2], 2, v[17:18]
	v_mad_u64_u32 v[19:20], null, s8, -10, v[15:16]
	v_lshlrev_b64 v[9:10], 2, v[13:14]
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	v_ashrrev_i32_e32 v20, 31, v19
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[7:8], null, s8, 11, v[19:20]
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_lshlrev_b64 v[11:12], 2, v[15:16]
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[13:14], 2, v[19:20]
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[15:16], null, s8, -12, v[7:8]
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	v_ashrrev_i32_e32 v16, 31, v15
	s_clause 0x5
	global_load_b32 v17, v[3:4], off
	global_load_b32 v18, v[1:2], off
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[9:10], off
	global_load_b32 v9, v[11:12], off
	global_load_b32 v10, v[13:14], off
	v_add_nc_u32_e32 v0, v21, v0
	v_add_co_u32 v3, vcc_lo, s4, v7
	v_lshlrev_b64 v[1:2], 2, v[15:16]
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt vmcnt(8)
	v_dual_sub_f32 v4, v22, v23 :: v_dual_sub_f32 v1, v24, v25
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, s9, v1
	v_fmac_f32_e32 v7, s8, v4
	s_waitcnt vmcnt(6)
	v_sub_f32_e32 v1, v17, v18
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v9, v10 :: v_dual_fmac_f32 v7, s10, v1
	v_sub_f32_e32 v1, v5, v6
	v_fmac_f32_e32 v7, s11, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, s0, v4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_fmac_f32_e32 v7, s1, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v7, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3Lx1PKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z3Lx1PKfPfiiS1_, .Lfunc_end3-_Z3Lx1PKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 18
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z4sbLxPKfPfiiS1_       ; -- Begin function _Z4sbLxPKfPfiiS1_
	.globl	_Z4sbLxPKfPfiiS1_
	.p2align	8
	.type	_Z4sbLxPKfPfiiS1_,@function
_Z4sbLxPKfPfiiS1_:                      ; @_Z4sbLxPKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s8, -6
	s_add_i32 s3, s9, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, s8, 1, v2
	v_add_nc_u32_e32 v10, s8, v2
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, s8, -3, v[0:1]
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s8, 2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_mad_u64_u32 v[8:9], null, s8, -5, v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_mad_u64_u32 v[12:13], null, s8, 6, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_mad_u64_u32 v[14:15], null, s8, -7, v[12:13]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v15, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v17, s8, 3, v14
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[19:20], null, s8, -9, v[17:18]
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_clause 0x3
	global_load_b32 v21, v[10:11], off
	global_load_b32 v22, v[15:16], off
	global_load_b32 v23, v[0:1], off
	global_load_b32 v24, v[4:5], off
	v_lshlrev_b64 v[4:5], 2, v[8:9]
	v_add_co_u32 v0, vcc_lo, s4, v6
	v_ashrrev_i32_e32 v20, 31, v19
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[8:9], null, s8, 10, v[19:20]
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_lshlrev_b64 v[10:11], 2, v[14:15]
	v_lshlrev_b64 v[12:13], 2, v[17:18]
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, s8, -11, v[8:9]
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_lshlrev_b64 v[14:15], 2, v[19:20]
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	s_clause 0x5
	global_load_b32 v18, v[0:1], off
	global_load_b32 v19, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[10:11], off
	global_load_b32 v10, v[12:13], off
	global_load_b32 v11, v[14:15], off
	v_lshlrev_b64 v[0:1], 2, v[16:17]
	v_add_co_u32 v4, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v0, v[0:1], off
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt vmcnt(8)
	v_sub_f32_e32 v1, v23, v24
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v21, v22 :: v_dual_mul_f32 v8, s9, v1
	s_waitcnt vmcnt(6)
	v_dual_fmac_f32 v8, s8, v5 :: v_dual_sub_f32 v1, v18, v19
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, s10, v1 :: v_dual_sub_f32 v1, v6, v7
	s_waitcnt vmcnt(2)
	v_dual_fmac_f32 v8, s11, v1 :: v_dual_sub_f32 v1, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, s0, v1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v4, v0
	v_fmac_f32_e32 v8, s1, v0
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
	global_store_b32 v[0:1], v8, off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4sbLxPKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z4sbLxPKfPfiiS1_, .Lfunc_end4-_Z4sbLxPKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z4sfLxPKfPfiiS1_       ; -- Begin function _Z4sfLxPKfPfiiS1_
	.globl	_Z4sfLxPKfPfiiS1_
	.p2align	8
	.type	_Z4sfLxPKfPfiiS1_,@function
_Z4sfLxPKfPfiiS1_:                      ; @_Z4sfLxPKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s8, -6
	s_add_i32 s3, s9, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_mul_lo_u32 v2, v1, s8
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v1, s8, v2
	v_add_nc_u32_e32 v11, v2, v0
	v_add_nc_u32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshl_add_u32 v3, s8, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v15, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, s8, -3, v[3:4]
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_lshl_add_u32 v7, s8, 2, v5
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, s8, -5, v[7:8]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_clause 0x3
	global_load_b32 v22, v[15:16], off
	global_load_b32 v23, v[0:1], off
	global_load_b32 v24, v[2:3], off
	global_load_b32 v25, v[4:5], off
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, s8, 6, v[9:10]
	v_lshlrev_b64 v[2:3], 2, v[9:10]
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, s8, -7, v[13:14]
	v_lshlrev_b64 v[18:19], 2, v[7:8]
	v_lshlrev_b64 v[4:5], 2, v[13:14]
	v_add_co_u32 v0, vcc_lo, s4, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v6, s8, 3, v17
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[13:14], 2, v[17:18]
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_mad_u64_u32 v[20:21], null, s8, -9, v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	v_ashrrev_i32_e32 v21, 31, v20
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, s8, 10, v[20:21]
	v_lshlrev_b64 v[15:16], 2, v[20:21]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[17:18], null, s8, -11, v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_clause 0x5
	global_load_b32 v10, v[0:1], off
	global_load_b32 v19, v[2:3], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[13:14], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[15:16], off
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v2, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[17:18]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v1, v24, v25 :: v_dual_add_f32 v0, v2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v8, s9, v1 :: v_dual_sub_f32 v1, v10, v19
	v_sub_f32_e32 v3, v22, v23
	v_fmac_f32_e32 v8, s8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, s10, v1
	v_sub_f32_e32 v1, v4, v5
	v_dual_fmac_f32 v8, s11, v1 :: v_dual_sub_f32 v1, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, s0, v1
	v_fmac_f32_e32 v8, s1, v0
	v_add_co_u32 v0, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v12, vcc_lo
	global_store_b32 v[0:1], v8, off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4sfLxPKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z4sfLxPKfPfiiS1_, .Lfunc_end5-_Z4sfLxPKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 852
; NumSgprs: 18
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z4sbLzPKfPfiiS1_       ; -- Begin function _Z4sbLzPKfPfiiS1_
	.globl	_Z4sbLzPKfPfiiS1_
	.p2align	8
	.type	_Z4sbLzPKfPfiiS1_,@function
_Z4sbLzPKfPfiiS1_:                      ; @_Z4sbLzPKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[6:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s6, -6
	s_add_i32 s3, s7, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[12:13], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v13, vcc_lo
	s_clause 0x2
	global_load_b128 v[0:3], v[8:9], off offset:-4
	global_load_b128 v[4:7], v[8:9], off offset:-20
	global_load_b128 v[8:11], v[8:9], off offset:12
	s_clause 0x1
	s_load_b128 s[0:3], s[4:5], 0x0
	s_load_b64 s[4:5], s[4:5], 0x10
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v0, v3, v0 :: v_dual_sub_f32 v1, v2, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, s1, v0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v8, v7
	v_dual_fmac_f32 v2, s0, v1 :: v_dual_sub_f32 v1, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, s2, v0
	v_sub_f32_e32 v0, v10, v5
	v_dual_fmac_f32 v2, s3, v1 :: v_dual_add_f32 v1, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, s4, v0
	v_add_co_u32 v0, vcc_lo, s10, v12
	v_fmac_f32_e32 v2, s5, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v13, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4sbLzPKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z4sbLzPKfPfiiS1_, .Lfunc_end6-_Z4sbLzPKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z4sfLzPKfPfiiS1_       ; -- Begin function _Z4sfLzPKfPfiiS1_
	.globl	_Z4sfLzPKfPfiiS1_
	.p2align	8
	.type	_Z4sfLzPKfPfiiS1_,@function
_Z4sfLzPKfPfiiS1_:                      ; @_Z4sfLzPKfPfiiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[6:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s6, -6
	s_add_i32 s3, s7, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[12:13], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v13, vcc_lo
	s_clause 0x2
	global_load_b128 v[0:3], v[8:9], off offset:-8
	global_load_b128 v[4:7], v[8:9], off offset:-24
	global_load_b128 v[8:11], v[8:9], off offset:8
	s_clause 0x1
	s_load_b128 s[0:3], s[4:5], 0x0
	s_load_b64 s[4:5], s[4:5], 0x10
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v0, v3, v0 :: v_dual_sub_f32 v1, v2, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, s1, v0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v8, v7
	v_dual_fmac_f32 v2, s0, v1 :: v_dual_sub_f32 v1, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, s2, v0
	v_sub_f32_e32 v0, v10, v5
	v_dual_fmac_f32 v2, s3, v1 :: v_dual_add_f32 v1, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, s4, v0
	v_add_co_u32 v0, vcc_lo, s10, v12
	v_fmac_f32_e32 v2, s5, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v13, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4sfLzPKfPfiiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z4sfLzPKfPfiiS1_, .Lfunc_end7-_Z4sfLzPKfPfiiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6rsgffdPKfPfS1_iiS1_  ; -- Begin function _Z6rsgffdPKfPfS1_iiS1_
	.globl	_Z6rsgffdPKfPfS1_iiS1_
	.p2align	8
	.type	_Z6rsgffdPKfPfS1_iiS1_,@function
_Z6rsgffdPKfPfS1_iiS1_:                 ; @_Z6rsgffdPKfPfS1_iiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s8, -6
	s_add_i32 s3, s9, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB8_2
; %bb.1:
	v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, s8, 1, v2
	v_add_nc_u32_e32 v10, s8, v2
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[14:15], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, s8, -3, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v15, vcc_lo
	v_lshl_add_u32 v6, s8, 2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[8:9], null, s8, -5, v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_clause 0x3
	global_load_b32 v26, v[2:3], off
	global_load_b32 v27, v[16:17], off offset:4
	global_load_b32 v28, v[0:1], off offset:-4
	global_load_b32 v29, v[4:5], off offset:8
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, s8, 6, v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, s8, -7, v[12:13]
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v18, s8, 3, v10
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, s8, -9, v[18:19]
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	v_mad_u64_u32 v[22:23], null, s8, 10, v[20:21]
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v23, 31, v22
	v_add_co_u32 v20, vcc_lo, s4, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_mad_u64_u32 v[24:25], null, s8, -11, v[22:23]
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	s_clause 0x5
	global_load_b32 v30, v[6:7], off offset:-8
	global_load_b32 v31, v[8:9], off offset:12
	global_load_b32 v32, v[12:13], off offset:-12
	global_load_b32 v33, v[10:11], off offset:16
	global_load_b32 v34, v[18:19], off offset:-16
	global_load_b32 v35, v[20:21], off offset:20
	v_ashrrev_i32_e32 v25, 31, v24
	v_add_co_u32 v22, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	v_add_co_u32 v24, vcc_lo, s4, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
	s_clause 0x1
	global_load_b32 v36, v[22:23], off offset:-20
	global_load_b32 v37, v[24:25], off offset:24
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt vmcnt(10)
	v_sub_f32_e32 v26, v26, v27
	s_waitcnt vmcnt(8)
	v_sub_f32_e32 v28, v28, v29
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, s9, v28
	v_fmac_f32_e32 v28, s8, v26
	s_waitcnt vmcnt(6)
	v_sub_f32_e32 v26, v30, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, s10, v26
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v26, v32, v33
	v_fmac_f32_e32 v28, s11, v26
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v26, v34, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, s4, v26
	v_add_co_u32 v26, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v27, vcc_lo, s7, v15, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v29, v36, v37
	v_dual_fmac_f32 v28, s5, v29 :: v_dual_mov_b32 v29, 0
	global_store_b32 v[26:27], v28, off
	s_clause 0x3
	global_load_b32 v26, v[0:1], off offset:8
	global_load_b32 v27, v[4:5], off offset:-4
	global_load_b32 v28, v[2:3], off offset:4
	global_load_b32 v16, v[16:17], off
	global_load_b128 v[0:3], v29, s[0:1]
	s_clause 0x7
	global_load_b32 v6, v[6:7], off offset:12
	global_load_b32 v7, v[8:9], off offset:-8
	global_load_b32 v8, v[12:13], off offset:16
	global_load_b32 v9, v[10:11], off offset:-12
	global_load_b32 v10, v[18:19], off offset:20
	global_load_b32 v11, v[20:21], off offset:-16
	global_load_b32 v12, v[22:23], off offset:24
	global_load_b32 v13, v[24:25], off offset:-20
	global_load_b64 v[4:5], v29, s[0:1] offset:16
	s_waitcnt vmcnt(10)
	v_dual_sub_f32 v17, v26, v27 :: v_dual_sub_f32 v16, v28, v16
	s_waitcnt vmcnt(9)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v1, v17
	s_waitcnt vmcnt(7)
	v_sub_f32_e32 v1, v6, v7
	v_fmac_f32_e32 v17, v0, v16
	s_waitcnt vmcnt(5)
	v_sub_f32_e32 v0, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v2, v1
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v1, v10, v11
	s_waitcnt vmcnt(1)
	v_dual_fmac_f32 v17, v3, v0 :: v_dual_sub_f32 v0, v12, v13
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v4, v1
	v_fmac_f32_e32 v17, v5, v0
	v_add_co_u32 v0, vcc_lo, s2, v14
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v15, vcc_lo
	global_store_b32 v[0:1], v17, off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6rsgffdPKfPfS1_iiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z6rsgffdPKfPfS1_iiS1_, .Lfunc_end8-_Z6rsgffdPKfPfS1_iiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1108
; NumSgprs: 18
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6rsgbfdPKfPfS1_iiS1_  ; -- Begin function _Z6rsgbfdPKfPfS1_iiS1_
	.globl	_Z6rsgbfdPKfPfS1_iiS1_
	.p2align	8
	.type	_Z6rsgbfdPKfPfS1_iiS1_,@function
_Z6rsgbfdPKfPfS1_iiS1_:                 ; @_Z6rsgbfdPKfPfS1_iiS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s2, s8, -6
	s_add_i32 s3, s9, -6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 5, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	v_cmp_lt_i32_e64 s3, 5, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB9_2
; %bb.1:
	v_mul_lo_u32 v2, v1, s8
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v1, s8, v2
	v_add_nc_u32_e32 v11, v2, v0
	v_add_nc_u32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshl_add_u32 v3, s8, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v15, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, s8, -3, v[3:4]
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_lshl_add_u32 v7, s8, 2, v5
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, s8, -5, v[7:8]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_clause 0x3
	global_load_b32 v28, v[15:16], off offset:-4
	global_load_b32 v29, v[0:1], off
	global_load_b32 v30, v[2:3], off offset:-8
	global_load_b32 v31, v[4:5], off offset:4
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, s8, 6, v[9:10]
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[17:18], null, s8, -7, v[13:14]
	v_lshlrev_b64 v[18:19], 2, v[7:8]
	v_lshlrev_b64 v[8:9], 2, v[9:10]
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v22, vcc_lo, s4, v18
	v_lshl_add_u32 v6, s8, 3, v17
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v8, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v13, vcc_lo, s4, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[20:21], null, s8, -9, v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	v_add_co_u32 v17, vcc_lo, s4, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
	v_ashrrev_i32_e32 v21, 31, v20
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[24:25], null, s8, 10, v[20:21]
	v_lshlrev_b64 v[19:20], 2, v[20:21]
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v19, vcc_lo, s4, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[26:27], null, s8, -11, v[24:25]
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	s_clause 0x5
	global_load_b32 v10, v[22:23], off offset:-12
	global_load_b32 v21, v[8:9], off offset:8
	global_load_b32 v32, v[13:14], off offset:-16
	global_load_b32 v33, v[17:18], off offset:12
	global_load_b32 v34, v[6:7], off offset:-20
	global_load_b32 v35, v[19:20], off offset:16
	v_ashrrev_i32_e32 v27, 31, v26
	v_add_co_u32 v24, vcc_lo, s4, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_add_co_u32 v26, vcc_lo, s4, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v27, vcc_lo
	s_clause 0x1
	global_load_b32 v36, v[24:25], off offset:-24
	global_load_b32 v37, v[26:27], off offset:20
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt vmcnt(10)
	v_sub_f32_e32 v28, v28, v29
	s_waitcnt vmcnt(8)
	v_sub_f32_e32 v30, v30, v31
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v30, s9, v30
	v_fmac_f32_e32 v30, s8, v28
	v_add_co_u32 v28, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v29, vcc_lo, s7, v12, vcc_lo
	s_waitcnt vmcnt(6)
	v_sub_f32_e32 v10, v10, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, s10, v10
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v10, v32, v33
	v_fmac_f32_e32 v30, s11, v10
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v10, v34, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, s4, v10
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v36, v37
	v_fmac_f32_e32 v30, s5, v10
	v_mov_b32_e32 v10, 0
	global_store_b32 v[28:29], v30, off
	s_clause 0x3
	global_load_b32 v21, v[2:3], off offset:4
	global_load_b32 v28, v[4:5], off offset:-8
	global_load_b32 v15, v[15:16], off
	global_load_b32 v16, v[0:1], off offset:-4
	global_load_b128 v[0:3], v10, s[0:1]
	s_clause 0x7
	global_load_b32 v22, v[22:23], off offset:8
	global_load_b32 v8, v[8:9], off offset:-12
	global_load_b32 v9, v[13:14], off offset:12
	global_load_b32 v13, v[17:18], off offset:-16
	global_load_b32 v6, v[6:7], off offset:16
	global_load_b32 v7, v[19:20], off offset:-20
	global_load_b32 v14, v[24:25], off offset:20
	global_load_b32 v17, v[26:27], off offset:-24
	global_load_b64 v[4:5], v10, s[0:1] offset:16
	s_waitcnt vmcnt(12)
	v_sub_f32_e32 v10, v21, v28
	s_waitcnt vmcnt(9)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v15, v16 :: v_dual_mul_f32 v10, v1, v10
	s_waitcnt vmcnt(7)
	v_dual_sub_f32 v1, v22, v8 :: v_dual_fmac_f32 v10, v0, v15
	s_waitcnt vmcnt(5)
	v_sub_f32_e32 v0, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v2, v1
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v1, v6, v7 :: v_dual_fmac_f32 v10, v3, v0
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v0, v14, v17
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v4, v1
	v_fmac_f32_e32 v10, v5, v0
	v_add_co_u32 v0, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v12, vcc_lo
	global_store_b32 v[0:1], v10, off
.LBB9_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6rsgbfdPKfPfS1_iiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z6rsgbfdPKfPfS1_iiS1_, .Lfunc_end9-_Z6rsgbfdPKfPfS1_iiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1112
; NumSgprs: 18
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
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    .max_flat_workgroup_size: 1024
    .name:           _Z6rsgffdPKfPfS1_iiS1_
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    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6rsgffdPKfPfS1_iiS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .offset:         0
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        .value_kind:     global_buffer
      - .address_space:  global
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    .name:           _Z6rsgbfdPKfPfS1_iiS1_
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    .symbol:         _Z6rsgbfdPKfPfS1_iiS1_.kd
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
