#include <stdio.h>
#include <stdlib.h>
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>

using namespace std;

__global__ void smallSimplex(double* job, int width, int height)
{
  extern __shared__ double shared[];
  double* pivotColumn = &shared[0];
  double* pivotRow = &shared[height];
  double* ratioColumn = &shared[width];


  __shared__ double smallestObj;
  __shared__ int pivotColIndx;
  __shared__ int pivotRowIndx;

  smallestObj = 10^20;
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  while(true)
  {
    //  STEP 1
    if(threadIdx.x == 0)
    {
      for(int i = 0; i < width; i++)
      {
        if(smallestObj > job[(height-1)*width+i])
        {
          smallestObj = job[(height-1)*width+i];
          pivotColIndx = i;
        }
      }
    }
    __syncthreads();
    if(smallestObj >= 0){break;}
    // printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);

    for(int i = index; i < height; i+=stride)
    {
        pivotColumn[i] = job[pivotColIndx + i*width];
        ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
    }

    // printf("The ratio column is:\n");
    // for(int i = 0; i < height; i++)
    // {
    //   printf("%f\n",ratioColumn[i]);
    // }
  //  STEP 2
    smallestObj = 10^20;
    if(threadIdx.x == 0)
    {
      for(int i = 0; i < height-1; i++)
      {
        if(smallestObj > ratioColumn[i])
        {
          smallestObj = ratioColumn[i];
          pivotRowIndx = i;
        }
      }
    }
    __syncthreads();
    // printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
    for(int i = index; i < width; i+=stride)
    {
      job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
      pivotRow[i] = job[width*pivotRowIndx + i];
    }
  //  STEP 3
    for (int i = index; i < height; i+= stride)
    {
      if(i == pivotRowIndx){continue;}
      for (int j = 0; j < width; j++)
      {
        job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
      }
    }
  }

}

int main(int argc, char const *argv[])
{
  double* simplexTable;
  cudaMallocManaged(&simplexTable, sizeof(double)*18);
  // simplexTable[0] = 3.;
  // simplexTable[1] = 4.;
  // simplexTable[2] = 1.;
  // simplexTable[3] = 0.;
  // simplexTable[4] = 0.;
  // simplexTable[5] = 24.;
  //
  // simplexTable[6] = 7.;
  // simplexTable[7] = -4.;
  // simplexTable[8] = 0.;
  // simplexTable[9] = 1.;
  // simplexTable[10] = 0.;
  // simplexTable[11] = 16.;
  //
  // simplexTable[12] = -2.;
  // simplexTable[13] = 3.;
  // simplexTable[14] = 0.;
  // simplexTable[15] = 0.;
  // simplexTable[16] = 1.;
  // simplexTable[17] = 0.;

  simplexTable[0] = 10.;
  simplexTable[1] = 7.;
  simplexTable[2] = 1.;
  simplexTable[3] = 0.;
  simplexTable[4] = 0.;
  simplexTable[5] = 40.;

  simplexTable[6] = 1.;
  simplexTable[7] = 1.;
  simplexTable[8] = 0.;
  simplexTable[9] = 1.;
  simplexTable[10] = 0.;
  simplexTable[11] = 5.;

  simplexTable[12] = -17.;
  simplexTable[13] = -12.;
  simplexTable[14] = 0.;
  simplexTable[15] = 0.;
  simplexTable[16] = 1.;
  simplexTable[17] = 0.;
  int height = 3;
  int width = 6;
  int sharedMemory = sizeof(double)*(height*2 + width);
  smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
  cudaDeviceSynchronize();
  for(int i = 0; i <18; i++)
  {
    cout<<simplexTable[i]<<" "<<"|"<<" ";
    if(i%6 == 5){cout<<endl;}
  }
  return 0;
}

	.file	"tmpxft_0031f90d_00000000-6_testSmallSimplex.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3852:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3852:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z12smallSimplexPdiiPdii
	.type	_Z34__device_stub__Z12smallSimplexPdiiPdii, @function
_Z34__device_stub__Z12smallSimplexPdiiPdii:
.LFB3874:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12smallSimplexPdii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3874:
	.size	_Z34__device_stub__Z12smallSimplexPdiiPdii, .-_Z34__device_stub__Z12smallSimplexPdiiPdii
	.globl	_Z12smallSimplexPdii
	.type	_Z12smallSimplexPdii, @function
_Z12smallSimplexPdii:
.LFB3875:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z12smallSimplexPdiiPdii
	.cfi_endproc
.LFE3875:
	.size	_Z12smallSimplexPdii, .-_Z12smallSimplexPdii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC8:
	.string	" "
.LC9:
	.string	"|"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1, %edx
	movl	$144, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rax
	xorl	%r9d, %r9d
	movq	.LC0(%rip), %rcx
	movq	.LC4(%rip), %rbx
	movl	$96, %r8d
	movq	.LC7(%rip), %rdx
	movabsq	$4294967297, %rdi
	movq	%rcx, (%rax)
	movq	.LC1(%rip), %rcx
	movl	$1, %esi
	movq	%rbx, 40(%rax)
	movq	.LC6(%rip), %rbx
	movq	%rcx, 8(%rax)
	movq	.LC5(%rip), %rcx
	movsd	.LC2(%rip), %xmm0
	movq	%rdx, 104(%rax)
	movl	$16777217, %edx
	movq	%rcx, 88(%rax)
	salq	$8, %rdx
	movl	$1, %ecx
	movq	$0x000000000, 24(%rax)
	movq	$0x000000000, 32(%rax)
	movq	$0x000000000, 64(%rax)
	movq	$0x000000000, 80(%rax)
	movq	%rbx, 96(%rax)
	movq	$0x000000000, 112(%rax)
	movq	$0x000000000, 120(%rax)
	movq	$0x000000000, 136(%rax)
	movsd	%xmm0, 16(%rax)
	movsd	%xmm0, 48(%rax)
	movsd	%xmm0, 56(%rax)
	movsd	%xmm0, 72(%rax)
	movsd	%xmm0, 128(%rax)
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rdi
	movl	$3, %edx
	movl	$6, %esi
	call	_Z34__device_stub__Z12smallSimplexPdiiPdii
.L9:
	call	cudaDeviceSynchronize@PLT
	xorl	%ebx, %ebx
	leaq	_ZSt4cout(%rip), %rbp
.L11:
	movq	8(%rsp), %rax
	movq	%rbp, %rdi
	leaq	.LC8(%rip), %r12
	movsd	(%rax,%rbx,8), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %eax
	movl	$6, %ecx
	cltd
	idivl	%ecx
	cmpl	$5, %edx
	jne	.L10
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L10:
	incq	%rbx
	cmpq	$18, %rbx
	jne	.L11
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z12smallSimplexPdii"
.LC11:
	.string	"precalc_xorwow_matrix"
.LC12:
	.string	"precalc_xorwow_offset_matrix"
.LC13:
	.string	"mrg32k3aM1"
.LC14:
	.string	"mrg32k3aM2"
.LC15:
	.string	"mrg32k3aM1SubSeq"
.LC16:
	.string	"mrg32k3aM2SubSeq"
.LC17:
	.string	"mrg32k3aM1Seq"
.LC18:
	.string	"mrg32k3aM2Seq"
.LC19:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3877:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12smallSimplexPdii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3877:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1076101120
	.align 8
.LC1:
	.long	0
	.long	1075576832
	.align 8
.LC2:
	.long	0
	.long	1072693248
	.align 8
.LC4:
	.long	0
	.long	1078198272
	.align 8
.LC5:
	.long	0
	.long	1075052544
	.align 8
.LC6:
	.long	0
	.long	-1070530560
	.align 8
.LC7:
	.long	0
	.long	-1071120384
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>

using namespace std;

__global__ void smallSimplex(double* job, int width, int height)
{
  extern __shared__ double shared[];
  double* pivotColumn = &shared[0];
  double* pivotRow = &shared[height];
  double* ratioColumn = &shared[width];


  __shared__ double smallestObj;
  __shared__ int pivotColIndx;
  __shared__ int pivotRowIndx;

  smallestObj = 10^20;
  int index = blockDim.x * blockIdx.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  while(true)
  {
    //  STEP 1
    if(threadIdx.x == 0)
    {
      for(int i = 0; i < width; i++)
      {
        if(smallestObj > job[(height-1)*width+i])
        {
          smallestObj = job[(height-1)*width+i];
          pivotColIndx = i;
        }
      }
    }
    __syncthreads();
    if(smallestObj >= 0){break;}
    // printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);

    for(int i = index; i < height; i+=stride)
    {
        pivotColumn[i] = job[pivotColIndx + i*width];
        ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
    }

    // printf("The ratio column is:\n");
    // for(int i = 0; i < height; i++)
    // {
    //   printf("%f\n",ratioColumn[i]);
    // }
  //  STEP 2
    smallestObj = 10^20;
    if(threadIdx.x == 0)
    {
      for(int i = 0; i < height-1; i++)
      {
        if(smallestObj > ratioColumn[i])
        {
          smallestObj = ratioColumn[i];
          pivotRowIndx = i;
        }
      }
    }
    __syncthreads();
    // printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
    for(int i = index; i < width; i+=stride)
    {
      job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
      pivotRow[i] = job[width*pivotRowIndx + i];
    }
  //  STEP 3
    for (int i = index; i < height; i+= stride)
    {
      if(i == pivotRowIndx){continue;}
      for (int j = 0; j < width; j++)
      {
        job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
      }
    }
  }

}

int main(int argc, char const *argv[])
{
  double* simplexTable;
  hipMallocManaged(&simplexTable, sizeof(double)*18);
  // simplexTable[0] = 3.;
  // simplexTable[1] = 4.;
  // simplexTable[2] = 1.;
  // simplexTable[3] = 0.;
  // simplexTable[4] = 0.;
  // simplexTable[5] = 24.;
  //
  // simplexTable[6] = 7.;
  // simplexTable[7] = -4.;
  // simplexTable[8] = 0.;
  // simplexTable[9] = 1.;
  // simplexTable[10] = 0.;
  // simplexTable[11] = 16.;
  //
  // simplexTable[12] = -2.;
  // simplexTable[13] = 3.;
  // simplexTable[14] = 0.;
  // simplexTable[15] = 0.;
  // simplexTable[16] = 1.;
  // simplexTable[17] = 0.;

  simplexTable[0] = 10.;
  simplexTable[1] = 7.;
  simplexTable[2] = 1.;
  simplexTable[3] = 0.;
  simplexTable[4] = 0.;
  simplexTable[5] = 40.;

  simplexTable[6] = 1.;
  simplexTable[7] = 1.;
  simplexTable[8] = 0.;
  simplexTable[9] = 1.;
  simplexTable[10] = 0.;
  simplexTable[11] = 5.;

  simplexTable[12] = -17.;
  simplexTable[13] = -12.;
  simplexTable[14] = 0.;
  simplexTable[15] = 0.;
  simplexTable[16] = 1.;
  simplexTable[17] = 0.;
  int height = 3;
  int width = 6;
  int sharedMemory = sizeof(double)*(height*2 + width);
  smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
  hipDeviceSynchronize();
  for(int i = 0; i <18; i++)
  {
    cout<<simplexTable[i]<<" "<<"|"<<" ";
    if(i%6 == 5){cout<<endl;}
  }
  return 0;
}

	.text
	.file	"testSmallSimplex.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__smallSimplexPdii # -- Begin function _Z27__device_stub__smallSimplexPdii
	.type	_Z27__device_stub__smallSimplexPdii,@function
_Z27__device_stub__smallSimplexPdii:    # @_Z27__device_stub__smallSimplexPdii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12smallSimplexPdii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__smallSimplexPdii, .Lfunc_end0-_Z27__device_stub__smallSimplexPdii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	8(%rsp), %rbx
	movl	$144, %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbx), %rax
	movabsq	$4621819117588971520, %rcx      # imm = 0x4024000000000000
	movq	%rcx, (%rax)
	movabsq	$4619567317775286272, %rcx      # imm = 0x401C000000000000
	movq	%rcx, 8(%rax)
	movabsq	$4607182418800017408, %rcx      # imm = 0x3FF0000000000000
	movq	%rcx, 16(%rax)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 24(%rax)
	movabsq	$4630826316843712512, %rdx      # imm = 0x4044000000000000
	movq	%rdx, 40(%rax)
	movq	%rcx, 48(%rax)
	movq	%rcx, 56(%rax)
	xorl	%edx, %edx
	movq	%rdx, 64(%rax)
	movq	%rcx, 72(%rax)
	movq	%rdx, 80(%rax)
	movabsq	$4617315517961601024, %rsi      # imm = 0x4014000000000000
	movq	%rsi, 88(%rax)
	movabsq	$-4597893744568565760, %rsi     # imm = 0xC031000000000000
	movq	%rsi, 96(%rax)
	movabsq	$-4600427019358961664, %rsi     # imm = 0xC028000000000000
	movq	%rsi, 104(%rax)
	movups	%xmm0, 112(%rax)
	movq	%rcx, 128(%rax)
	movq	%rdx, 136(%rax)
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	255(%rdi), %rdx
	movl	$96, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	8(%rsp), %rdi
	movl	$6, %esi
	movl	$3, %edx
	callq	_Z27__device_stub__smallSimplexPdii
.LBB1_2:
	callq	hipDeviceSynchronize
	movb	$5, %bpl
	xorl	%r14d, %r14d
	movl	$_ZSt4cout, %r15d
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movzbl	%r14b, %eax
	imull	$171, %eax, %eax
	shrl	$9, %eax
	andl	$-2, %eax
	leal	(%rax,%rax,2), %r12d
	movq	8(%rsp), %rax
	movsd	(%rax,%r14,8), %xmm0            # xmm0 = mem[0],zero
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rbx, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rbx, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	addb	%bpl, %r12b
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	incq	%r14
	decb	%bpl
	cmpq	$18, %r14
	jne	.LBB1_3
# %bb.6:
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12smallSimplexPdii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12smallSimplexPdii,@object    # @_Z12smallSimplexPdii
	.section	.rodata,"a",@progbits
	.globl	_Z12smallSimplexPdii
	.p2align	3, 0x0
_Z12smallSimplexPdii:
	.quad	_Z27__device_stub__smallSimplexPdii
	.size	_Z12smallSimplexPdii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" "
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"|"
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12smallSimplexPdii"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__smallSimplexPdii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12smallSimplexPdii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12smallSimplexPdii    ; -- Begin function _Z12smallSimplexPdii
	.globl	_Z12smallSimplexPdii
	.p2align	8
	.type	_Z12smallSimplexPdii,@function
_Z12smallSimplexPdii:                   ; @_Z12smallSimplexPdii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s0, s[0:1], 0x10
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0x403e0000
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	ds_store_b64 v1, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s7, 3
	s_lshl_b32 s14, s6, 3
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s16, s1, 16
	s_add_i32 s17, s14, 16
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_cmp_lt_i32 s6, 1
	s_mul_i32 s8, s0, s2
	s_cselect_b32 s24, -1, 0
	s_cmp_gt_i32 s6, 0
	s_mul_i32 s15, s8, s6
	s_cselect_b32 s3, -1, 0
	s_add_i32 s18, s7, -1
	s_cmp_gt_i32 s7, 1
	v_mul_lo_u32 v0, s6, v3
	s_cselect_b32 s9, -1, 0
	s_mul_i32 s2, s18, s6
	s_and_b32 s19, vcc_lo, s3
	s_and_b32 s20, vcc_lo, s9
	v_lshlrev_b32_e32 v4, 3, v3
	s_add_u32 s21, s4, -8
	s_addc_u32 s22, s5, -1
	s_ashr_i32 s3, s2, 31
	v_cmp_gt_i32_e64 s0, s7, v3
	s_lshl_b64 s[2:3], s[2:3], 3
	v_cmp_gt_i32_e64 s1, s6, v3
	v_add_nc_u32_e32 v10, 16, v4
	v_add_nc_u32_e32 v11, s16, v4
	s_add_u32 s10, s4, s2
	v_add_nc_u32_e32 v12, s6, v0
	s_addc_u32 s11, s5, s3
	s_ashr_i32 s9, s8, 31
	s_lshl_b32 s23, s8, 3
	s_lshl_b64 s[12:13], s[8:9], 3
	s_xor_b32 s9, s24, -1
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_9 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
                                        ;     Child Loop BB0_17 Depth 2
                                        ;     Child Loop BB0_20 Depth 2
                                        ;       Child Loop BB0_22 Depth 3
	s_and_saveexec_b32 s24, s19
	s_cbranch_execz .LBB0_6
; %bb.2:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	ds_load_b64 v[4:5], v1
	s_mov_b32 s25, 0
	s_mov_b64 s[2:3], s[10:11]
.LBB0_3:                                ; %.lr.ph
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[6:7], v1, s[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[4:5], v[6:7]
	s_cbranch_vccnz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_mov_b32_e32 v4, v6
	v_dual_mov_b32 v8, s25 :: v_dual_mov_b32 v5, v7
	ds_store_b64 v1, v[6:7]
	ds_store_b32 v1, v8 offset:8
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s25, s25, 1
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s6, s25
	s_cbranch_scc1 .LBB0_3
.LBB0_6:                                ; %Flow154
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[4:5], v1
	s_mov_b32 s2, -1
	s_waitcnt lgkmcnt(0)
	v_cmp_le_f64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_25
; %bb.7:                                ; %.preheader90
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_10
; %bb.8:                                ; %.lr.ph95
                                        ;   in Loop: Header=BB0_1 Depth=1
	ds_load_b32 v5, v1 offset:8
	v_mov_b32_e32 v4, v10
	v_mov_b32_e32 v6, v3
	s_mov_b32 s3, 0
	s_mov_b32 s24, 0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, v0, v5
.LBB0_9:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v7, s24, v5
	v_add_nc_u32_e32 v13, s24, v12
	v_add_nc_u32_e32 v6, s8, v6
	v_add_nc_u32_e32 v9, s14, v4
	s_add_i32 s24, s24, s15
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s21, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s22, v14, vcc_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[13:14], v[13:14], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v4, v[7:8]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[15:16], null, v[7:8], v[7:8], v[13:14]
	v_div_scale_f64 v[21:22], vcc_lo, v[13:14], v[7:8], v[13:14]
	v_add_nc_u32_e32 v4, s23, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
	v_cmp_le_i32_e32 vcc_lo, s7, v6
	s_or_b32 s3, vcc_lo, s3
	v_div_fixup_f64 v[13:14], v[15:16], v[7:8], v[13:14]
	ds_store_b64 v9, v[13:14]
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_9
.LBB0_10:                               ; %Flow152
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	ds_store_b64 v1, v[1:2]
	s_and_saveexec_b32 s2, s20
	s_cbranch_execz .LBB0_15
; %bb.11:                               ; %.lr.ph98.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0x403e0000
	s_mov_b32 s3, 0
	s_mov_b32 s24, s17
.LBB0_12:                               ; %.lr.ph98
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s24
	ds_load_b64 v[6:7], v6
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[4:5], v[6:7]
	s_cbranch_vccnz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=2
	v_mov_b32_e32 v4, v6
	v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v5, v7
	ds_store_b64 v1, v[6:7]
	ds_store_b32 v1, v8 offset:12
.LBB0_14:                               ;   in Loop: Header=BB0_12 Depth=2
	s_add_i32 s3, s3, 1
	s_add_i32 s24, s24, 8
	s_cmp_lg_u32 s18, s3
	s_cbranch_scc1 .LBB0_12
.LBB0_15:                               ; %Flow150
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_18
; %bb.16:                               ; %.lr.ph101
                                        ;   in Loop: Header=BB0_1 Depth=1
	ds_load_b32 v6, v1 offset:12
	s_mov_b32 s24, 0
	v_mov_b32_e32 v8, v3
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[4:5], null, v6, s6, v[3:4]
	v_dual_mov_b32 v6, v11 :: v_dual_lshlrev_b32 v7, 3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 16, v7
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_17:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[13:14], v[4:5], off
	ds_load_b64 v[15:16], v7
	v_add_nc_u32_e32 v8, s8, v8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f64 v[17:18], null, v[15:16], v[15:16], v[13:14]
	v_div_scale_f64 v[23:24], vcc_lo, v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[23:24], v[19:20]
	v_fma_f64 v[17:18], -v[17:18], v[21:22], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[21:22]
	v_cmp_le_i32_e32 vcc_lo, s6, v8
	s_or_b32 s24, vcc_lo, s24
	v_div_fixup_f64 v[13:14], v[17:18], v[15:16], v[13:14]
	global_store_b64 v[4:5], v[13:14], off
	v_add_co_u32 v4, s2, v4, s12
	ds_store_b64 v6, v[13:14]
	v_add_co_ci_u32_e64 v5, s2, s13, v5, s2
	v_add_nc_u32_e32 v6, s23, v6
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_17
.LBB0_18:                               ; %Flow148
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ; %.lr.ph106
                                        ;   in Loop: Header=BB0_1 Depth=1
	ds_load_b32 v13, v1 offset:12
	v_mov_b32_e32 v4, v0
	v_mov_b32_e32 v14, v3
	s_mov_b32 s3, 0
.LBB0_20:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_22 Depth 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, v14, v13
	s_and_b32 s25, vcc_lo, s9
	s_and_saveexec_b32 s24, s25
	s_cbranch_execz .LBB0_23
; %bb.21:                               ; %.lr.ph103
                                        ;   in Loop: Header=BB0_20 Depth=2
	v_lshl_add_u32 v5, v14, 3, 16
	s_mov_b32 s25, s16
	s_mov_b32 s26, s6
	ds_load_b64 v[6:7], v5
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
.LBB0_22:                               ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_20 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b64 v[15:16], v[8:9], off
	v_mov_b32_e32 v5, s25
	s_add_i32 s26, s26, -1
	s_add_i32 s25, s25, 8
	s_cmp_lg_u32 s26, 0
	ds_load_b64 v[17:18], v5
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[15:16], -v[6:7], v[17:18], v[15:16]
	global_store_b64 v[8:9], v[15:16], off
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_cbranch_scc1 .LBB0_22
.LBB0_23:                               ; %Flow144
                                        ;   in Loop: Header=BB0_20 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_add_nc_u32_e32 v14, s8, v14
	v_add_nc_u32_e32 v4, s15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s7, v14
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_20
.LBB0_24:                               ; %Flow146
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, 0
.LBB0_25:                               ; %Flow155
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_1
; %bb.26:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12smallSimplexPdii
		.amdhsa_group_segment_fixed_size 16
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12smallSimplexPdii, .Lfunc_end0-_Z12smallSimplexPdii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1288
; NumSgprs: 29
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 16
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12smallSimplexPdii
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z12smallSimplexPdii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
