#define WINDOWS 1

#ifdef WINDOWS
// Import these libraries if using MS Visual Studio for development.
// They are needed by nvcc to interface with MS Visual Studio.
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#endif // !WINDOWS

#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define SIZE 1024       // DEFAULT values for a, b and c
#define DATATYPE int    // datatype used. For getting GFLOPS use float.
#define MAX_RANDOM 20   // Random limit
#define BLOCK_SIZE 32   // DEFAULT block size

/**
 * Kernel for multiplication of matrices
 * Each thread calculates the element of the resultant matrix
 * The thread decides the element using block_index and thread_index values
 * Since it calculates the resultant with help of grid, I did not need a call to __syncThreads()
 */
__global__ 
void multiply(DATATYPE *p, DATATYPE *q, DATATYPE *r, int a, int b, int c) {
    int row = blockDim.y * blockIdx.y + threadIdx.y;    // get the row index for resultant matrix
    int col = blockDim.x * blockIdx.x + threadIdx.x;    // get the column index for column matrix
    int sum = 0, i = 0;
    if (row < a && col < c) {
        for (i = 0; i < b; ++i) {
            sum += p[row * b + i] * q[i * c + col];
        }
        r[row * c + col] = sum;
    }
    
}

int main(int argc, char *argv[]) {
    // declarations
    int a = SIZE, b = SIZE, c = SIZE;
    DATATYPE *p, *q, *r, *hr;
    int i, j, k;
    float time_elapsed = 0;

    DATATYPE *d_p, *d_q, *d_r;
    int N_BLOCKS = BLOCK_SIZE, N_THREADS;

    cudaEvent_t start, stop;

    // read from command line if possible
    if (argc == 4) {
        a = atoi(argv[1]);
        b = atoi(argv[2]);
        c = atoi(argv[3]);
        printf("Reading values of a, b and c\na = %d, b = %d, c = %d\n", a, b, c);
    } else { // otherwise proceed with default values
        fprintf(stderr, "proceeding with default values of a, b and c (1024)\n");
        fprintf(stderr, "usage: kernel a b c\n");
    }
    
    // get number of blocks and threads to use from user
    printf("Enter N_BLOCKS: ");
    scanf("%d", &N_BLOCKS);
    printf("Enter N_THREADS: ");
    scanf("%d", &N_THREADS);

    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    // Allocate memory using unified memory model
    cudaMallocHost((void**) &p, sizeof(DATATYPE) * a * b);
    cudaMallocHost((void**) &q, sizeof(DATATYPE) * b * c);
    cudaMallocHost((void**) &r, sizeof(DATATYPE) * a * c);

    // create random variable using seed and initialize matrices
    // Initialize matrix c to 0
    srand(time(NULL));
    for (i = 0; i < a; ++i) {
        for (j = 0; j < b; ++j) {
            p[i * b + j] = rand() % MAX_RANDOM;
        }
    }
    for (i = 0; i < b; ++i) {
        for (j = 0; j < c; ++j) {
            q[i * c + j] = rand() % MAX_RANDOM;
        }
    }
    for (i = 0; i < a; ++i) {
        for (j = 0; j < b; ++j) {
            r[i * c + j] = 0;
        }
    }

    // find the optimal configuration of number of threads
    // create a dim3 structure for it
    unsigned int rows = (a + N_BLOCKS - 1) / N_BLOCKS;
    unsigned int cols = (c + N_BLOCKS - 1) / N_BLOCKS;
    dim3 dimGrid(cols, rows);
    dim3 dimBlock(N_BLOCKS, N_BLOCKS);

    // start the clock
    cudaEventRecord(start);
    // allocate device memory
    cudaMalloc((void **) &d_p, sizeof(DATATYPE) * a * b);
    cudaMalloc((void **) &d_q, sizeof(DATATYPE) * b * c);
    cudaMalloc((void **) &d_r, sizeof(DATATYPE) * a * c);

    // copy the contents from host to device
    cudaMemcpy(d_p, p, sizeof(DATATYPE) * a * b, cudaMemcpyHostToDevice);
    cudaMemcpy(d_q, q, sizeof(DATATYPE) * b * c, cudaMemcpyHostToDevice);
    cudaMemcpy(d_r, r, sizeof(DATATYPE) * a * c, cudaMemcpyHostToDevice);

    // call kernel
    multiply <<< dimGrid, dimBlock >>> (d_p, d_q, d_r, a, b, c);
    
    // copy the results back and let all threads sync
    cudaMemcpy(r, d_r, sizeof(DATATYPE) * a * c, cudaMemcpyDeviceToHost);
    cudaThreadSynchronize();

    //stop clock and free memory
    cudaFree(d_p);
    cudaFree(d_q);
    cudaFree(d_r);
    cudaEventRecord(stop);
    cudaEventSynchronize(stop);

    // find the time taken
    cudaEventElapsedTime(&time_elapsed, start, stop);
    // and print it
    printf("Time: %f msecs\n", time_elapsed);

    // free host memory
    cudaFreeHost(p);
    cudaFreeHost(q);
    cudaFreeHost(r);

    return 0;
}

	.file	"tmpxft_00274654_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii
	.type	_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii, @function
_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8multiplyPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii, .-_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii
	.globl	_Z8multiplyPiS_S_iii
	.type	_Z8multiplyPiS_S_iii, @function
_Z8multiplyPiS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z8multiplyPiS_S_iii, .-_Z8multiplyPiS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Reading values of a, b and c\na = %d, b = %d, c = %d\n"
.LC2:
	.string	"proceeding with default values of a, b and c (1024)\n"
.LC3:
	.string	"usage: kernel a b c\n"
.LC4:
	.string	"Enter N_BLOCKS: "
.LC5:
	.string	"%d"
.LC6:
	.string	"Enter N_THREADS: "
.LC7:
	.string	"Time: %f msecs\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	movl	$32, 40(%rsp)
	cmpl	$4, %edi
	jne	.L9
	movq	8(%rsi), %rdi
	movq	%rsi, %rbp
	call	atoi@PLT
	movq	16(%rbp), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	movq	24(%rbp), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movl	%ebx, %ecx
	movl	%r12d, %edx
	movl	$2, %edi
	movl	%eax, %ebp
	movl	%eax, %r8d
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L10
.L9:
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	movl	$1024, %ebp
	movl	$1024, %ebx
	movl	$1024, %r12d
	call	__fprintf_chk@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
.L10:
	leaq	.LC5(%rip), %r13
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r13, %rdi
	leaq	40(%rsp), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	%r12d, %r15
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rsi
	movq	%r15, %r14
	call	__printf_chk@PLT
	movq	%r13, %rdi
	movslq	%ebx, %r13
	leaq	44(%rsp), %rsi
	imulq	%r13, %r14
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	96(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	104(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	0(,%r14,4), %rax
	movslq	%ebp, %r14
	leaq	48(%rsp), %rdi
	imulq	%r14, %r13
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMallocHost@PLT
	imulq	%r14, %r15
	leaq	56(%rsp), %rdi
	leaq	0(,%r13,4), %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMallocHost@PLT
	leaq	0(,%r15,4), %rax
	leaq	64(%rsp), %rdi
	xorl	%r15d, %r15d
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMallocHost@PLT
	xorl	%edi, %edi
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	xorl	%r8d, %r8d
.L11:
	cmpl	%r8d, %r12d
	jle	.L13
	movslq	%r15d, %rcx
	xorl	%r13d, %r13d
	leaq	0(,%rcx,4), %r14
.L14:
	cmpl	%r13d, %ebx
	jle	.L26
	movl	%r8d, 28(%rsp)
	incl	%r13d
	call	rand@PLT
	movl	$20, %ecx
	movl	28(%rsp), %r8d
	cltd
	idivl	%ecx
	movq	48(%rsp), %rax
	movl	%edx, (%rax,%r14)
	addq	$4, %r14
	jmp	.L14
.L26:
	incl	%r8d
	addl	%ebx, %r15d
	jmp	.L11
.L13:
	xorl	%r15d, %r15d
	xorl	%r8d, %r8d
.L15:
	cmpl	%r8d, %ebx
	jle	.L17
	movslq	%r15d, %rcx
	xorl	%r13d, %r13d
	leaq	0(,%rcx,4), %r14
.L18:
	cmpl	%r13d, %ebp
	jle	.L27
	movl	%r8d, 28(%rsp)
	incl	%r13d
	call	rand@PLT
	movl	$20, %ecx
	movl	28(%rsp), %r8d
	cltd
	idivl	%ecx
	movq	56(%rsp), %rax
	movl	%edx, (%rax,%r14)
	addq	$4, %r14
	jmp	.L18
.L27:
	incl	%r8d
	addl	%ebp, %r15d
	jmp	.L15
.L17:
	movq	64(%rsp), %rdi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
.L19:
	cmpl	%ecx, %r12d
	jle	.L21
	movslq	%edx, %rax
	leaq	(%rdi,%rax,4), %rsi
	xorl	%eax, %eax
.L22:
	cmpl	%eax, %ebx
	jle	.L28
	xorl	%r8d, %r8d
	movl	%r8d, (%rsi,%rax,4)
	incq	%rax
	jmp	.L22
.L28:
	incl	%ecx
	addl	%ebp, %edx
	jmp	.L19
.L21:
	movl	40(%rsp), %ecx
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	movl	$1, 120(%rsp)
	movl	$1, 132(%rsp)
	leal	-1(%rcx,%rbp), %eax
	movl	%ecx, 124(%rsp)
	cltd
	movl	%ecx, 128(%rsp)
	idivl	%ecx
	movl	%eax, 112(%rsp)
	leal	-1(%rcx,%r12), %eax
	cltd
	idivl	%ecx
	movl	%eax, 116(%rsp)
	call	cudaEventRecord@PLT
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$1, %ecx
	movq	88(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	124(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	132(%rsp), %ecx
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	%ebp, %r9d
	movl	%ebx, %r8d
	movq	72(%rsp), %rdi
	movl	%r12d, %ecx
	call	_Z34__device_stub__Z8multiplyPiS_S_iiiPiS_S_iii
.L23:
	movq	(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	104(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	48(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	56(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	64(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z8multiplyPiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8multiplyPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#define WINDOWS 1

#ifdef WINDOWS
// Import these libraries if using MS Visual Studio for development.
// They are needed by nvcc to interface with MS Visual Studio.
#include "hip/hip_runtime.h"

#endif // !WINDOWS

#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define SIZE 1024       // DEFAULT values for a, b and c
#define DATATYPE int    // datatype used. For getting GFLOPS use float.
#define MAX_RANDOM 20   // Random limit
#define BLOCK_SIZE 32   // DEFAULT block size

/**
 * Kernel for multiplication of matrices
 * Each thread calculates the element of the resultant matrix
 * The thread decides the element using block_index and thread_index values
 * Since it calculates the resultant with help of grid, I did not need a call to __syncThreads()
 */
__global__ 
void multiply(DATATYPE *p, DATATYPE *q, DATATYPE *r, int a, int b, int c) {
    int row = blockDim.y * blockIdx.y + threadIdx.y;    // get the row index for resultant matrix
    int col = blockDim.x * blockIdx.x + threadIdx.x;    // get the column index for column matrix
    int sum = 0, i = 0;
    if (row < a && col < c) {
        for (i = 0; i < b; ++i) {
            sum += p[row * b + i] * q[i * c + col];
        }
        r[row * c + col] = sum;
    }
    
}

int main(int argc, char *argv[]) {
    // declarations
    int a = SIZE, b = SIZE, c = SIZE;
    DATATYPE *p, *q, *r, *hr;
    int i, j, k;
    float time_elapsed = 0;

    DATATYPE *d_p, *d_q, *d_r;
    int N_BLOCKS = BLOCK_SIZE, N_THREADS;

    hipEvent_t start, stop;

    // read from command line if possible
    if (argc == 4) {
        a = atoi(argv[1]);
        b = atoi(argv[2]);
        c = atoi(argv[3]);
        printf("Reading values of a, b and c\na = %d, b = %d, c = %d\n", a, b, c);
    } else { // otherwise proceed with default values
        fprintf(stderr, "proceeding with default values of a, b and c (1024)\n");
        fprintf(stderr, "usage: kernel a b c\n");
    }
    
    // get number of blocks and threads to use from user
    printf("Enter N_BLOCKS: ");
    scanf("%d", &N_BLOCKS);
    printf("Enter N_THREADS: ");
    scanf("%d", &N_THREADS);

    hipEventCreate(&start);
    hipEventCreate(&stop);

    // Allocate memory using unified memory model
    hipHostMalloc((void**) &p, sizeof(DATATYPE) * a * b, hipHostMallocDefault);
    hipHostMalloc((void**) &q, sizeof(DATATYPE) * b * c, hipHostMallocDefault);
    hipHostMalloc((void**) &r, sizeof(DATATYPE) * a * c, hipHostMallocDefault);

    // create random variable using seed and initialize matrices
    // Initialize matrix c to 0
    srand(time(NULL));
    for (i = 0; i < a; ++i) {
        for (j = 0; j < b; ++j) {
            p[i * b + j] = rand() % MAX_RANDOM;
        }
    }
    for (i = 0; i < b; ++i) {
        for (j = 0; j < c; ++j) {
            q[i * c + j] = rand() % MAX_RANDOM;
        }
    }
    for (i = 0; i < a; ++i) {
        for (j = 0; j < b; ++j) {
            r[i * c + j] = 0;
        }
    }

    // find the optimal configuration of number of threads
    // create a dim3 structure for it
    unsigned int rows = (a + N_BLOCKS - 1) / N_BLOCKS;
    unsigned int cols = (c + N_BLOCKS - 1) / N_BLOCKS;
    dim3 dimGrid(cols, rows);
    dim3 dimBlock(N_BLOCKS, N_BLOCKS);

    // start the clock
    hipEventRecord(start);
    // allocate device memory
    hipMalloc((void **) &d_p, sizeof(DATATYPE) * a * b);
    hipMalloc((void **) &d_q, sizeof(DATATYPE) * b * c);
    hipMalloc((void **) &d_r, sizeof(DATATYPE) * a * c);

    // copy the contents from host to device
    hipMemcpy(d_p, p, sizeof(DATATYPE) * a * b, hipMemcpyHostToDevice);
    hipMemcpy(d_q, q, sizeof(DATATYPE) * b * c, hipMemcpyHostToDevice);
    hipMemcpy(d_r, r, sizeof(DATATYPE) * a * c, hipMemcpyHostToDevice);

    // call kernel
    multiply <<< dimGrid, dimBlock >>> (d_p, d_q, d_r, a, b, c);
    
    // copy the results back and let all threads sync
    hipMemcpy(r, d_r, sizeof(DATATYPE) * a * c, hipMemcpyDeviceToHost);
    hipDeviceSynchronize();

    //stop clock and free memory
    hipFree(d_p);
    hipFree(d_q);
    hipFree(d_r);
    hipEventRecord(stop);
    hipEventSynchronize(stop);

    // find the time taken
    hipEventElapsedTime(&time_elapsed, start, stop);
    // and print it
    printf("Time: %f msecs\n", time_elapsed);

    // free host memory
    hipHostFree(p);
    hipHostFree(q);
    hipHostFree(r);

    return 0;
}

	.text
	.file	"kernel.hip"
	.globl	_Z23__device_stub__multiplyPiS_S_iii # -- Begin function _Z23__device_stub__multiplyPiS_S_iii
	.type	_Z23__device_stub__multiplyPiS_S_iii,@function
_Z23__device_stub__multiplyPiS_S_iii:   # @_Z23__device_stub__multiplyPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8multiplyPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__multiplyPiS_S_iii, .Lfunc_end0-_Z23__device_stub__multiplyPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$0, 92(%rsp)
	movl	$32, 20(%rsp)
	cmpl	$4, %edi
	jne	.LBB1_2
# %bb.1:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebx
	movl	$.L.str, %edi
	movl	%r14d, %esi
	movl	%ebp, %r13d
	movl	%ebp, %edx
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB1_3:
	xorl	%r12d, %r12d
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	20(%rsp), %rsi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	148(%rsp), %rsi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	leaq	96(%rsp), %rdi
	callq	hipEventCreate
	leaq	56(%rsp), %rdi
	callq	hipEventCreate
	movslq	%r14d, %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	leaq	(,%rax,4), %r15
	movq	%r14, %rbp
	movslq	%r13d, %r14
	movq	%r15, %rsi
	imulq	%r14, %rsi
	leaq	80(%rsp), %rdi
	movq	%rsi, 112(%rsp)                 # 8-byte Spill
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	%rbx, 24(%rsp)                  # 8-byte Spill
	movslq	%ebx, %rbx
	imulq	%rbx, %r14
	shlq	$2, %r14
	leaq	72(%rsp), %rdi
	movq	%r14, 120(%rsp)                 # 8-byte Spill
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	imulq	%rbx, %r15
	leaq	40(%rsp), %rdi
	movq	%r15, 128(%rsp)                 # 8-byte Spill
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movq	%rbp, 48(%rsp)                  # 8-byte Spill
	movl	%ebp, %r15d
	movl	%r13d, %ebx
	cmpl	$0, 8(%rsp)                     # 4-byte Folded Reload
	movl	%r13d, %eax
	movl	%r13d, 8(%rsp)                  # 4-byte Spill
	jle	.LBB1_8
# %bb.4:                                # %.preheader77.lr.ph
	xorl	%r13d, %r13d
.LBB1_5:                                # %.preheader77
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_6 Depth 2
	movl	%r12d, %r12d
	movq	%rbx, %rbp
	movq	%r12, %r14
	testl	%eax, %eax
	jle	.LBB1_7
.LBB1_6:                                #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$35, %rcx
	addl	%edx, %ecx
	shll	$2, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movq	80(%rsp), %rcx
	movl	%eax, (%rcx,%r14,4)
	incq	%r14
	decq	%rbp
	jne	.LBB1_6
.LBB1_7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_5 Depth=1
	incq	%r13
	movl	8(%rsp), %eax                   # 4-byte Reload
	addl	%eax, %r12d
	cmpq	%r15, %r13
	jne	.LBB1_5
.LBB1_8:                                # %.preheader76
	testl	%eax, %eax
	movq	24(%rsp), %rsi                  # 8-byte Reload
	jle	.LBB1_13
# %bb.9:                                # %.preheader75.lr.ph
	movl	%esi, %eax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	xorl	%r14d, %r14d
	xorl	%ebp, %ebp
.LBB1_10:                               # %.preheader75
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_11 Depth 2
	movl	%r14d, %r14d
	movq	136(%rsp), %r12                 # 8-byte Reload
	movq	%r14, %r13
	testl	%esi, %esi
	jle	.LBB1_12
.LBB1_11:                               #   Parent Loop BB1_10 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$35, %rcx
	addl	%edx, %ecx
	shll	$2, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movq	72(%rsp), %rcx
	movl	%eax, (%rcx,%r13,4)
	incq	%r13
	decq	%r12
	jne	.LBB1_11
.LBB1_12:                               # %._crit_edge82
                                        #   in Loop: Header=BB1_10 Depth=1
	incq	%rbp
	movq	24(%rsp), %rsi                  # 8-byte Reload
	addl	%esi, %r14d
	cmpq	%rbx, %rbp
	jne	.LBB1_10
.LBB1_13:                               # %.preheader74
	cmpl	$0, 48(%rsp)                    # 4-byte Folded Reload
	movl	8(%rsp), %eax                   # 4-byte Reload
	jle	.LBB1_18
# %bb.14:                               # %.preheader.lr.ph
	movq	40(%rsp), %r14
	shlq	$2, %rbx
	xorl	%ebp, %ebp
.LBB1_15:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	testl	%eax, %eax
	jle	.LBB1_17
# %bb.16:                               # %.lr.ph85
                                        #   in Loop: Header=BB1_15 Depth=1
	movslq	%ebp, %rax
	leaq	(%r14,%rax,4), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	memset@PLT
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	8(%rsp), %eax                   # 4-byte Reload
.LBB1_17:                               # %._crit_edge86
                                        #   in Loop: Header=BB1_15 Depth=1
	addl	%esi, %ebp
	decq	%r15
	jne	.LBB1_15
.LBB1_18:                               # %._crit_edge88
	movl	20(%rsp), %ecx
	movq	48(%rsp), %r14                  # 8-byte Reload
	leal	(%r14,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
	movl	%eax, %ebx
	leal	(%rsi,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rbx
	orq	%rax, %rbx
	movq	%rcx, %r13
	shlq	$32, %r13
	orq	%rcx, %r13
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	104(%rsp), %rbp
	movq	%rbp, %rdi
	movq	112(%rsp), %r12                 # 8-byte Reload
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movq	120(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	128(%rsp), %r15                 # 8-byte Reload
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	80(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %rax
	movq	(%rax), %rdi
	movq	72(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_20
# %bb.19:
	movq	104(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	48(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	8(%rsp), %r8d                   # 4-byte Reload
	movq	24(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	callq	_Z23__device_stub__multiplyPiS_S_iii
.LBB1_20:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	56(%rsp), %rdi
	callq	hipEventSynchronize
	movq	96(%rsp), %rsi
	movq	56(%rsp), %rdx
	leaq	92(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movq	80(%rsp), %rdi
	callq	hipHostFree
	movq	72(%rsp), %rdi
	callq	hipHostFree
	movq	40(%rsp), %rdi
	callq	hipHostFree
	xorl	%eax, %eax
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 208
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$52, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
	movl	$20, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$1024, %ebx                     # imm = 0x400
	movl	$1024, %r13d                    # imm = 0x400
	movl	$1024, %r14d                    # imm = 0x400
	jmp	.LBB1_3
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8multiplyPiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8multiplyPiS_S_iii,@object    # @_Z8multiplyPiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z8multiplyPiS_S_iii
	.p2align	3, 0x0
_Z8multiplyPiS_S_iii:
	.quad	_Z23__device_stub__multiplyPiS_S_iii
	.size	_Z8multiplyPiS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Reading values of a, b and c\na = %d, b = %d, c = %d\n"
	.size	.L.str, 53

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"proceeding with default values of a, b and c (1024)\n"
	.size	.L.str.1, 53

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"usage: kernel a b c\n"
	.size	.L.str.2, 21

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Enter N_BLOCKS: "
	.size	.L.str.3, 17

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d"
	.size	.L.str.4, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Enter N_THREADS: "
	.size	.L.str.5, 18

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Time: %f msecs\n"
	.size	.L.str.6, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8multiplyPiS_S_iii"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__multiplyPiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8multiplyPiS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8multiplyPiS_S_iii    ; -- Begin function _Z8multiplyPiS_S_iii
	.globl	_Z8multiplyPiS_S_iii
	.p2align	8
	.type	_Z8multiplyPiS_S_iii,@function
_Z8multiplyPiS_S_iii:                   ; @_Z8multiplyPiS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s6, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v0, s5
	v_mov_b32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_add_i32 s5, s5, -1
	s_cmp_lg_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	global_load_b32 v8, v[3:4], off
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s6, v5
	s_cbranch_scc1 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v2, 0
.LBB0_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v0, s6, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8multiplyPiS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8multiplyPiS_S_iii, .Lfunc_end0-_Z8multiplyPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8multiplyPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8multiplyPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
