/* Written by : Eric Tan
 */

#include <iostream>
#include <cmath>
#include <array>
#include <cuda.h>

#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4


/*-------------------------------------------------------------------------------------------------
 * GLOBAL CONSTANTS
 *-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];


/*-------------------------------------------------------------------------------------------------
 * FORWARD DECLARATION
 *-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);


/*-------------------------------------------------------------------------------------------------
 * MAIN
 *-----------------------------------------------------------------------------------------------*/
int main(void)
{
    const int mask_size = 9;
    const int N_data = 1000;
    const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};

    // Copy to constant memory
    cudaMemcpyToSymbol(mask, mask_kernel.data(), mask_size * sizeof(float));

    float *input = new float[N_data];
    float *cpu_output = new float[N_data];
    float *gpu_output = new float[N_data];

    for (int i = 0; i < N_data; i++)
        input[i] = i + 1.0;

    convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);

    convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
    std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';

    convolution_cache_gpu(input, gpu_output, N_data, mask_size);
    std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';

    delete[] input;
    delete[] cpu_output;
    delete[] gpu_output;
}


/*-------------------------------------------------------------------------------------------------
 * KERNELS
 *-----------------------------------------------------------------------------------------------*/

/* tiled_convolution_kernel()
 * Performs convolution by tiling the input and loading halo elements.
 */
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
    int idx  = blockIdx.x * blockDim.x + threadIdx.x;
    int half = N_mask / 2;
    __shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];

    // Left load
    // Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
    int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
    if (threadIdx.x >= blockDim.x - half)
        tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];

    // Middle load
    tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];

    // Right load
    // Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
    int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
    if (threadIdx.x < half)
        tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];

    __syncthreads();

    // Convolution calculation
    float sum = 0.0;
    for (int i = 0; i < N_mask; i++)
        sum += tile[threadIdx.x + i] * mask[i];

    output[idx] = sum;
}


/* cache_convolution_kernel()
 * Performs convolution by loading multiple tiles of the input data and performing the convolution
 * operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
 * will go to L2 cache to grabe them.
 */
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
    int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
    __shared__ float tile[N_TILE * TILE_SIZE];

    // Load Multiple tiles
    #pragma unroll
    for (int i = 0; i < N_TILE; i++)
        tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];

    __syncthreads();

    int tile_start = N_TILE * blockDim.x * blockIdx.x;
    int tile_end   = N_TILE * blockDim.x * (blockIdx.x + 1);

    #pragma unroll
    for (int i = 0; i < N_TILE; i++) {
        int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
        float sum = 0.0;

        for (int j = 0; j < N_mask; j++) {
            int input_idx = start_point + j;

            if (input_idx >= 0 && input_idx < N_data) {
                // Check if elements needed is in shared memory
                if (input_idx >= tile_start && input_idx < tile_end)
                    sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
                else
                    sum += input[input_idx] * mask[j];

            } // Check if element is outside range of input data
        } // Loop over Mask elements

        output[idx + i * TILE_SIZE] = sum;
    } // Loop over multiple tiles
}


/*-------------------------------------------------------------------------------------------------
 * FUNCTIONS
 *-----------------------------------------------------------------------------------------------*/

/* convolution_tiled_gpu()
 * Driver function for tiled convolution which loads halo elements.
 */
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
    int size = N_data * sizeof(float);
    float *d_input, *d_output;

    cudaMalloc((void**)&d_input, size);
    cudaMalloc((void**)&d_output, size);

    cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);

    int N_thd = TILE_SIZE;
    int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
    dim3 blk_dim(N_thd, 1, 1);
    dim3 grid_dim(N_blk, 1, 1 );

    cudaEvent_t start, stop;

    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    cudaEventRecord(start);

    tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);

    cudaEventRecord(stop);
    cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
    cudaEventSynchronize(stop);

    float time_ms = 0.0;
    cudaEventElapsedTime(&time_ms, start, stop);

    std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";

    cudaFree(d_input);
    cudaFree(d_output);
}


/* convolution_tiled_gpu()
 * Driver function for tiled convolution without loading halo elements.
 */
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
    int size = N_data * sizeof(float);
    float *d_input, *d_output;

    cudaMalloc((void**)&d_input, size);
    cudaMalloc((void**)&d_output, size);

    cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);

    int N_thd = TILE_SIZE;
    int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
    dim3 blk_dim(N_thd, 1, 1);
    dim3 grid_dim(N_blk, 1, 1 );

    cudaEvent_t start, stop;

    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    cudaEventRecord(start);

    cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);

    cudaEventRecord(stop);
    cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
    cudaEventSynchronize(stop);

    float time_ms = 0.0;
    cudaEventElapsedTime(&time_ms, start, stop);

    std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";

    cudaFree(d_input);
    cudaFree(d_output);
}


/* convolution_cpu()
 * CPU based convolution operation. Used to compare GPU implamentations.
 */
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
    int half_point = N_mask / 2;

    for (int i = 0; i < N_data; i++) {
        float sum = 0.0;
        for (int j = 0; j < N_mask; j++) {
            if (i - half_point + j >= 0 && i - half_point + j < N_data)
                sum += input[i - half_point + j] * mask[j];
        }
        output[i] = sum;
    }
}


/* check_convolution()
 * Computes the difference between the two outputs of CPU and GPU convolutions.
 */
double check_convolution(const float *A, const float *B, int N)
{
    float sum = 0.0;

    for (int i = 0; i < N; i++)
        sum += fabs(A[i] - B[i]);

    return sum;
}

	.file	"tmpxft_0030259a_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3683:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3683:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0, @function
_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0:
.LFB4337:
	.cfi_startproc
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	(%rdi), %rax
	movb	%sil, 12(%rsp)
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rdi,%rax)
	je	.L3
	leaq	12(%rsp), %rsi
	movl	$1, %edx
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L2
.L3:
	movsbl	12(%rsp), %esi
	call	_ZNSo3putEc@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4337:
	.size	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0, .-_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	.globl	_Z15convolution_cpuPKfPfS0_ii
	.type	_Z15convolution_cpuPKfPfS0_ii, @function
_Z15convolution_cpuPKfPfS0_ii:
.LFB3679:
	.cfi_startproc
	endbr64
	movl	%r8d, %eax
	movq	%rsi, %r10
	movq	%rdx, %r11
	movl	%ecx, %esi
	cltd
	movl	$2, %ecx
	idivl	%ecx
	xorl	%ecx, %ecx
	movslq	%eax, %rdx
	negl	%eax
	imulq	$-4, %rdx, %rdx
	addq	%rdi, %rdx
	cmpl	%ecx, %esi
	jg	.L18
	ret
.L18:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
.L12:
	movl	%eax, %r9d
	movq	%rdx, %rbx
	xorps	%xmm0, %xmm0
	xorl	%edi, %edi
.L11:
	cmpl	%edi, %r8d
	jle	.L19
	testl	%r9d, %r9d
	js	.L9
	cmpl	%r9d, %esi
	jle	.L9
	movss	(%rbx), %xmm1
	mulss	(%r11,%rdi,4), %xmm1
	addss	%xmm1, %xmm0
.L9:
	incq	%rdi
	addq	$4, %rbx
	incl	%r9d
	jmp	.L11
.L19:
	movss	%xmm0, (%r10,%rcx,4)
	incq	%rcx
	addq	$4, %rdx
	incl	%eax
	cmpl	%ecx, %esi
	jg	.L12
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3679:
	.size	_Z15convolution_cpuPKfPfS0_ii, .-_Z15convolution_cpuPKfPfS0_ii
	.globl	_Z17check_convolutionPKfS0_i
	.type	_Z17check_convolutionPKfS0_i, @function
_Z17check_convolutionPKfS0_i:
.LFB3680:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
	movss	.LC2(%rip), %xmm2
.L21:
	cmpl	%eax, %edx
	jle	.L23
	movss	(%rdi,%rax,4), %xmm1
	subss	(%rsi,%rax,4), %xmm1
	incq	%rax
	andps	%xmm2, %xmm1
	addss	%xmm1, %xmm0
	jmp	.L21
.L23:
	cvtss2sd	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE3680:
	.size	_Z17check_convolutionPKfS0_i, .-_Z17check_convolutionPKfS0_i
	.globl	_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
	.type	_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii, @function
_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii:
.LFB3705:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24tiled_convolution_kernelPKfPfii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L24:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3705:
	.size	_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii, .-_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
	.globl	_Z24tiled_convolution_kernelPKfPfii
	.type	_Z24tiled_convolution_kernelPKfPfii, @function
_Z24tiled_convolution_kernelPKfPfii:
.LFB3706:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
	.cfi_endproc
.LFE3706:
	.size	_Z24tiled_convolution_kernelPKfPfii, .-_Z24tiled_convolution_kernelPKfPfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Convolution with tiling and halo runtime: "
.LC5:
	.string	"ms "
	.text
	.globl	_Z21convolution_tiled_gpuPKfPfii
	.type	_Z21convolution_tiled_gpuPKfPfii, @function
_Z21convolution_tiled_gpuPKfPfii:
.LFB3677:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leal	0(,%rdx,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC3(%rip), %xmm0
	call	ceilf@PLT
	movl	$8388609, %eax
	leaq	32(%rsp), %rdi
	movl	$1, 56(%rsp)
	salq	$9, %rax
	movq	%rax, 48(%rsp)
	cvttss2sil	%xmm0, %eax
	movl	%eax, 60(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%ebp, %edx
	call	_Z49__device_stub__Z24tiled_convolution_kernelPKfPfiiPKfPfii
.L30:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	12(%rsp), %rdi
	movl	$0x00000000, 12(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	12(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	_Z21convolution_tiled_gpuPKfPfii, .-_Z21convolution_tiled_gpuPKfPfii
	.globl	_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
	.type	_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii, @function
_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii:
.LFB3707:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24cache_convolution_kernelPKfPfii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3707:
	.size	_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii, .-_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
	.globl	_Z24cache_convolution_kernelPKfPfii
	.type	_Z24cache_convolution_kernelPKfPfii, @function
_Z24cache_convolution_kernelPKfPfii:
.LFB3708:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
	.cfi_endproc
.LFE3708:
	.size	_Z24cache_convolution_kernelPKfPfii, .-_Z24cache_convolution_kernelPKfPfii
	.section	.rodata.str1.1
.LC7:
	.string	"Convolution with L2 cache use runtime: "
	.text
	.globl	_Z21convolution_cache_gpuPKfPfii
	.type	_Z21convolution_cache_gpuPKfPfii, @function
_Z21convolution_cache_gpuPKfPfii:
.LFB3678:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leal	0(,%rdx,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC6(%rip), %xmm0
	call	ceilf@PLT
	movl	$8388609, %eax
	leaq	32(%rsp), %rdi
	movl	$1, 56(%rsp)
	salq	$9, %rax
	movq	%rax, 48(%rsp)
	cvttss2sil	%xmm0, %eax
	movl	%eax, 60(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%ebp, %edx
	call	_Z49__device_stub__Z24cache_convolution_kernelPKfPfiiPKfPfii
.L39:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	12(%rsp), %rdi
	movl	$0x00000000, 12(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	12(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3678:
	.size	_Z21convolution_cache_gpuPKfPfii, .-_Z21convolution_cache_gpuPKfPfii
	.section	.rodata.str1.1
.LC9:
	.string	" Error = "
	.section	.rodata
	.align 32
.LC0:
	.long	1077936128
	.long	1082130432
	.long	1084227584
	.long	1086324736
	.long	1088421888
	.long	1086324736
	.long	1084227584
	.long	1082130432
	.long	1077936128
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3675:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$9, %ecx
	movl	$36, %edx
	leaq	.LC0(%rip), %rsi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	$1, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdi
	leaq	4(%rsp), %r13
	rep movsl
	movq	%r13, %rsi
	leaq	_ZL4mask(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$4000, %edi
	call	_Znam@PLT
	movl	$4000, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$4000, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movsd	.LC8(%rip), %xmm1
	movq	%rax, %rbx
	xorl	%eax, %eax
.L43:
	cvtsi2sdl	%eax, %xmm0
	addsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$1000, %rax
	jne	.L43
	movl	$9, %r8d
	movq	%r13, %rdx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	movl	$1000, %ecx
	leaq	.LC9(%rip), %r14
	leaq	_ZSt4cout(%rip), %r13
	call	_Z15convolution_cpuPKfPfS0_ii
	movl	$9, %ecx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	movl	$1000, %edx
	call	_Z21convolution_tiled_gpuPKfPfii
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1000, %edx
	movq	%rbx, %rsi
	movq	%r12, %rdi
	movq	%rax, %rcx
	call	_Z17check_convolutionPKfS0_i
	movq	%rcx, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$10, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	movl	$9, %ecx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	movl	$1000, %edx
	call	_Z21convolution_cache_gpuPKfPfii
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1000, %edx
	movq	%rbx, %rsi
	movq	%r12, %rdi
	movq	%rax, %rcx
	call	_Z17check_convolutionPKfS0_i
	movq	%rcx, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$10, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z24cache_convolution_kernelPKfPfii"
.LC12:
	.string	"_Z24tiled_convolution_kernelPKfPfii"
.LC13:
	.string	"mask"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24cache_convolution_kernelPKfPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24tiled_convolution_kernelPKfPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movl	$200, %r9d
	leaq	_ZL4mask(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3710:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL4mask
	.comm	_ZL4mask,200,32
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	989855744
	.align 4
.LC6:
	.long	973078528
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC8:
	.long	0
	.long	1072693248
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Written by : Eric Tan
 */

#include <iostream>
#include <cmath>
#include <array>
#include <hip/hip_runtime.h>

#define MAX_MASK_SIZE 50
#define TILE_SIZE 512
#define N_TILE 4


/*-------------------------------------------------------------------------------------------------
 * GLOBAL CONSTANTS
 *-----------------------------------------------------------------------------------------------*/
__constant__ float mask[MAX_MASK_SIZE];


/*-------------------------------------------------------------------------------------------------
 * FORWARD DECLARATION
 *-----------------------------------------------------------------------------------------------*/
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask);
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask);
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask);
double check_convolution(const float *A, const float *B, int N);


/*-------------------------------------------------------------------------------------------------
 * MAIN
 *-----------------------------------------------------------------------------------------------*/
int main(void)
{
    const int mask_size = 9;
    const int N_data = 1000;
    const std::array<float, mask_size> mask_kernel = {3.0, 4.0, 5.0, 6.0, 7.0, 6.0, 5.0, 4.0, 3.0};

    // Copy to constant memory
    hipMemcpyToSymbol(HIP_SYMBOL(mask), mask_kernel.data(), mask_size * sizeof(float));

    float *input = new float[N_data];
    float *cpu_output = new float[N_data];
    float *gpu_output = new float[N_data];

    for (int i = 0; i < N_data; i++)
        input[i] = i + 1.0;

    convolution_cpu(input, cpu_output, mask_kernel.data(), N_data, mask_size);

    convolution_tiled_gpu(input, gpu_output, N_data, mask_size);
    std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';

    convolution_cache_gpu(input, gpu_output, N_data, mask_size);
    std::cout << " Error = " << check_convolution(cpu_output, gpu_output, N_data) << '\n';

    delete[] input;
    delete[] cpu_output;
    delete[] gpu_output;
}


/*-------------------------------------------------------------------------------------------------
 * KERNELS
 *-----------------------------------------------------------------------------------------------*/

/* tiled_convolution_kernel()
 * Performs convolution by tiling the input and loading halo elements.
 */
__global__ void tiled_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
    int idx  = blockIdx.x * blockDim.x + threadIdx.x;
    int half = N_mask / 2;
    __shared__ float tile[TILE_SIZE + MAX_MASK_SIZE - 1];

    // Left load
    // Maps the last N_mask/2 threads to the previous block (or 0 if at the edge)
    int left_idx = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
    if (threadIdx.x >= blockDim.x - half)
        tile[threadIdx.x + half - blockDim.x] = (left_idx < 0) ? 0 : input[left_idx];

    // Middle load
    tile[half + threadIdx.x] = input[blockIdx.x * blockDim.x + threadIdx.x];

    // Right load
    // Maps the first N_mask/2 threads to the next block (or 0 if at the edge)
    int right_idx = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
    if (threadIdx.x < half)
        tile[threadIdx.x + blockDim.x + half] = (right_idx >= N_data) ? 0 : input[right_idx];

    __syncthreads();

    // Convolution calculation
    float sum = 0.0;
    for (int i = 0; i < N_mask; i++)
        sum += tile[threadIdx.x + i] * mask[i];

    output[idx] = sum;
}


/* cache_convolution_kernel()
 * Performs convolution by loading multiple tiles of the input data and performing the convolution
 * operation. Halo elements are assumed to be loaded in the L2 cache so if theya re needed, we
 * will go to L2 cache to grabe them.
 */
__global__ void cache_convolution_kernel(const float *input, float *output, int N_data, int N_mask)
{
    int idx = (N_TILE * blockDim.x * blockIdx.x) + threadIdx.x;
    __shared__ float tile[N_TILE * TILE_SIZE];

    // Load Multiple tiles
    #pragma unroll
    for (int i = 0; i < N_TILE; i++)
        tile[threadIdx.x + i * TILE_SIZE] = input[idx + i * TILE_SIZE];

    __syncthreads();

    int tile_start = N_TILE * blockDim.x * blockIdx.x;
    int tile_end   = N_TILE * blockDim.x * (blockIdx.x + 1);

    #pragma unroll
    for (int i = 0; i < N_TILE; i++) {
        int start_point = idx + (i * TILE_SIZE) - (N_mask / 2);
        float sum = 0.0;

        for (int j = 0; j < N_mask; j++) {
            int input_idx = start_point + j;

            if (input_idx >= 0 && input_idx < N_data) {
                // Check if elements needed is in shared memory
                if (input_idx >= tile_start && input_idx < tile_end)
                    sum += tile[threadIdx.x + j - (N_mask / 2) + (i * TILE_SIZE)] * mask[j];
                else
                    sum += input[input_idx] * mask[j];

            } // Check if element is outside range of input data
        } // Loop over Mask elements

        output[idx + i * TILE_SIZE] = sum;
    } // Loop over multiple tiles
}


/*-------------------------------------------------------------------------------------------------
 * FUNCTIONS
 *-----------------------------------------------------------------------------------------------*/

/* convolution_tiled_gpu()
 * Driver function for tiled convolution which loads halo elements.
 */
//void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
void convolution_tiled_gpu(const float *input, float *output, int N_data, int N_mask)
{
    int size = N_data * sizeof(float);
    float *d_input, *d_output;

    hipMalloc((void**)&d_input, size);
    hipMalloc((void**)&d_output, size);

    hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);

    int N_thd = TILE_SIZE;
    int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_thd));
    dim3 blk_dim(N_thd, 1, 1);
    dim3 grid_dim(N_blk, 1, 1 );

    hipEvent_t start, stop;

    hipEventCreate(&start);
    hipEventCreate(&stop);
    hipEventRecord(start);

    tiled_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);

    hipEventRecord(stop);
    hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
    hipEventSynchronize(stop);

    float time_ms = 0.0;
    hipEventElapsedTime(&time_ms, start, stop);

    std::cout << "Convolution with tiling and halo runtime: " << time_ms << "ms ";

    hipFree(d_input);
    hipFree(d_output);
}


/* convolution_tiled_gpu()
 * Driver function for tiled convolution without loading halo elements.
 */
void convolution_cache_gpu(const float *input, float *output, int N_data, int N_mask)
{
    int size = N_data * sizeof(float);
    float *d_input, *d_output;

    hipMalloc((void**)&d_input, size);
    hipMalloc((void**)&d_output, size);

    hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);

    int N_thd = TILE_SIZE;
    int N_blk = ceil(static_cast<float>(N_data) / static_cast<float>(N_TILE * N_thd));
    dim3 blk_dim(N_thd, 1, 1);
    dim3 grid_dim(N_blk, 1, 1 );

    hipEvent_t start, stop;

    hipEventCreate(&start);
    hipEventCreate(&stop);
    hipEventRecord(start);

    cache_convolution_kernel<<<grid_dim, blk_dim>>>(d_input, d_output, N_data, N_mask);

    hipEventRecord(stop);
    hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
    hipEventSynchronize(stop);

    float time_ms = 0.0;
    hipEventElapsedTime(&time_ms, start, stop);

    std::cout << "Convolution with L2 cache use runtime: " << time_ms << "ms ";

    hipFree(d_input);
    hipFree(d_output);
}


/* convolution_cpu()
 * CPU based convolution operation. Used to compare GPU implamentations.
 */
void convolution_cpu(const float *input, float *output, const float *mask, int N_data, int N_mask)
{
    int half_point = N_mask / 2;

    for (int i = 0; i < N_data; i++) {
        float sum = 0.0;
        for (int j = 0; j < N_mask; j++) {
            if (i - half_point + j >= 0 && i - half_point + j < N_data)
                sum += input[i - half_point + j] * mask[j];
        }
        output[i] = sum;
    }
}


/* check_convolution()
 * Computes the difference between the two outputs of CPU and GPU convolutions.
 */
double check_convolution(const float *A, const float *B, int N)
{
    float sum = 0.0;

    for (int i = 0; i < N; i++)
        sum += fabs(A[i] - B[i]);

    return sum;
}

	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI0_0:
	.long	0x40400000                      # float 3
	.long	0x40800000                      # float 4
	.long	0x40a00000                      # float 5
	.long	0x40c00000                      # float 6
.LCPI0_1:
	.long	0x40e00000                      # float 7
	.long	0x40c00000                      # float 6
	.long	0x40a00000                      # float 5
	.long	0x40800000                      # float 4
.LCPI0_2:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movaps	.LCPI0_0(%rip), %xmm0           # xmm0 = [3.0E+0,4.0E+0,5.0E+0,6.0E+0]
	leaq	4(%rsp), %rsi
	movups	%xmm0, (%rsi)
	movaps	.LCPI0_1(%rip), %xmm0           # xmm0 = [7.0E+0,6.0E+0,5.0E+0,4.0E+0]
	movups	%xmm0, 16(%rsi)
	movl	$1077936128, 32(%rsi)           # imm = 0x40400000
	xorl	%r12d, %r12d
	movl	$mask, %edi
	movl	$36, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$4000, %edi                     # imm = 0xFA0
	callq	_Znam
	movq	%rax, %rbx
	movl	$4000, %edi                     # imm = 0xFA0
	callq	_Znam
	movq	%rax, %r14
	movl	$4000, %edi                     # imm = 0xFA0
	callq	_Znam
	movq	%rax, %r15
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%r12), %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbx,%r12,4)
	movq	%rax, %r12
	cmpq	$1000, %rax                     # imm = 0x3E8
	jne	.LBB0_1
# %bb.2:                                # %.preheader.i.preheader
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB0_3:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	xorps	%xmm0, %xmm0
	movq	$-4, %rdx
.LBB0_4:                                #   Parent Loop BB0_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rax,%rdx), %esi
	cmpl	$999, %esi                      # imm = 0x3E7
	ja	.LBB0_6
# %bb.5:                                #   in Loop: Header=BB0_4 Depth=2
	movss	(%rcx,%rdx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	20(%rsp,%rdx,4), %xmm1
	addss	%xmm1, %xmm0
.LBB0_6:                                #   in Loop: Header=BB0_4 Depth=2
	incq	%rdx
	cmpq	$5, %rdx
	jne	.LBB0_4
# %bb.7:                                # %._crit_edge.i
                                        #   in Loop: Header=BB0_3 Depth=1
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	addq	$4, %rcx
	cmpq	$1000, %rax                     # imm = 0x3E8
	jne	.LBB0_3
# %bb.8:                                # %_Z15convolution_cpuPKfPfS0_ii.exit
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$9, %ecx
	callq	_Z21convolution_tiled_gpuPKfPfii
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB0_9:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r14,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	subss	(%r15,%rax,4), %xmm1
	andps	.LCPI0_2(%rip), %xmm1
	addss	%xmm1, %xmm0
	incq	%rax
	cmpq	$1000, %rax                     # imm = 0x3E8
	jne	.LBB0_9
# %bb.10:                               # %_Z17check_convolutionPKfS0_i.exit
	cvtss2sd	%xmm0, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movb	$10, 3(%rsp)
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, 16(%rax,%rcx)
	je	.LBB0_12
# %bb.11:
	leaq	3(%rsp), %rsi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB0_13
.LBB0_12:
	movq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNSo3putEc
.LBB0_13:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	$1000, %edx                     # imm = 0x3E8
	movl	$9, %ecx
	callq	_Z21convolution_cache_gpuPKfPfii
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
	movaps	.LCPI0_2(%rip), %xmm2           # xmm2 = [NaN,NaN,NaN,NaN]
.LBB0_14:                               # %.lr.ph.i22
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r14,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	subss	(%r15,%rax,4), %xmm1
	andps	%xmm2, %xmm1
	addss	%xmm1, %xmm0
	incq	%rax
	cmpq	$1000, %rax                     # imm = 0x3E8
	jne	.LBB0_14
# %bb.15:                               # %_Z17check_convolutionPKfS0_i.exit28
	cvtss2sd	%xmm0, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movb	$10, 3(%rsp)
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, 16(%rax,%rcx)
	je	.LBB0_17
# %bb.16:
	leaq	3(%rsp), %rsi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB0_18
.LBB0_17:
	movq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNSo3putEc
.LBB0_18:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit31
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z15convolution_cpuPKfPfS0_ii   # -- Begin function _Z15convolution_cpuPKfPfS0_ii
	.type	_Z15convolution_cpuPKfPfS0_ii,@function
_Z15convolution_cpuPKfPfS0_ii:          # @_Z15convolution_cpuPKfPfS0_ii
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r10d
	shrl	$31, %r10d
	addl	%r8d, %r10d
	sarl	%r10d
	negl	%r10d
	movl	%ecx, %eax
	movl	%r8d, %r9d
	movl	%r10d, %r10d
	xorl	%r11d, %r11d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
	testl	%r8d, %r8d
	jle	.LBB1_3
# %bb.7:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movslq	%r10d, %rbx
	leaq	(%rdi,%rbx,4), %rbx
	xorps	%xmm0, %xmm0
	xorl	%r14d, %r14d
.LBB1_8:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%r10,%r14), %ebp
	cmpl	%ecx, %ebp
	jae	.LBB1_10
# %bb.9:                                #   in Loop: Header=BB1_8 Depth=2
	movss	(%rbx,%r14,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rdx,%r14,4), %xmm1
	addss	%xmm1, %xmm0
.LBB1_10:                               #   in Loop: Header=BB1_8 Depth=2
	incq	%r14
	cmpq	%r14, %r9
	jne	.LBB1_8
	jmp	.LBB1_4
.LBB1_3:                                #   in Loop: Header=BB1_2 Depth=1
	xorps	%xmm0, %xmm0
.LBB1_4:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movss	%xmm0, (%rsi,%r11,4)
	incq	%r11
	incq	%r10
	cmpq	%rax, %r11
	jne	.LBB1_2
# %bb.5:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %rbp
.LBB1_6:                                # %._crit_edge30
	retq
.Lfunc_end1:
	.size	_Z15convolution_cpuPKfPfS0_ii, .Lfunc_end1-_Z15convolution_cpuPKfPfS0_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z21convolution_tiled_gpuPKfPfii
.LCPI2_0:
	.long	0x3b000000                      # float 0.001953125
	.text
	.globl	_Z21convolution_tiled_gpuPKfPfii
	.type	_Z21convolution_tiled_gpuPKfPfii,@function
_Z21convolution_tiled_gpuPKfPfii:       # @_Z21convolution_tiled_gpuPKfPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movq	%rsi, %rbx
	movq	%rdi, %r12
	leal	(,%r15,4), %eax
	movslq	%eax, %r14
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI2_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r12d
	btsq	$32, %r12
	leaq	24(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	callq	_Z39__device_stub__tiled_convolution_kernelPKfPfii
.LBB2_2:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	36(%rsp), %rbx
	movl	$0, (%rbx)
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$42, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21convolution_tiled_gpuPKfPfii, .Lfunc_end2-_Z21convolution_tiled_gpuPKfPfii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z17check_convolutionPKfS0_i
.LCPI3_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	_Z17check_convolutionPKfS0_i
	.type	_Z17check_convolutionPKfS0_i,@function
_Z17check_convolutionPKfS0_i:           # @_Z17check_convolutionPKfS0_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB3_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
	movaps	.LCPI3_0(%rip), %xmm1           # xmm1 = [NaN,NaN,NaN,NaN]
.LBB3_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rdi,%rcx,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%rsi,%rcx,4), %xmm2
	andps	%xmm1, %xmm2
	addss	%xmm2, %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB3_4
# %bb.5:                                # %._crit_edge.loopexit
	cvtss2sd	%xmm0, %xmm0
	retq
.LBB3_1:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end3:
	.size	_Z17check_convolutionPKfS0_i, .Lfunc_end3-_Z17check_convolutionPKfS0_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z21convolution_cache_gpuPKfPfii
.LCPI4_0:
	.long	0x3a000000                      # float 4.8828125E-4
	.text
	.globl	_Z21convolution_cache_gpuPKfPfii
	.type	_Z21convolution_cache_gpuPKfPfii,@function
_Z21convolution_cache_gpuPKfPfii:       # @_Z21convolution_cache_gpuPKfPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movq	%rsi, %rbx
	movq	%rdi, %r12
	leal	(,%r15,4), %eax
	movslq	%eax, %r14
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r12d
	btsq	$32, %r12
	leaq	24(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	callq	_Z39__device_stub__cache_convolution_kernelPKfPfii
.LBB4_2:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	36(%rsp), %rbx
	movl	$0, (%rbx)
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$39, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z21convolution_cache_gpuPKfPfii, .Lfunc_end4-_Z21convolution_cache_gpuPKfPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__tiled_convolution_kernelPKfPfii # -- Begin function _Z39__device_stub__tiled_convolution_kernelPKfPfii
	.type	_Z39__device_stub__tiled_convolution_kernelPKfPfii,@function
_Z39__device_stub__tiled_convolution_kernelPKfPfii: # @_Z39__device_stub__tiled_convolution_kernelPKfPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24tiled_convolution_kernelPKfPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z39__device_stub__tiled_convolution_kernelPKfPfii, .Lfunc_end5-_Z39__device_stub__tiled_convolution_kernelPKfPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__cache_convolution_kernelPKfPfii # -- Begin function _Z39__device_stub__cache_convolution_kernelPKfPfii
	.type	_Z39__device_stub__cache_convolution_kernelPKfPfii,@function
_Z39__device_stub__cache_convolution_kernelPKfPfii: # @_Z39__device_stub__cache_convolution_kernelPKfPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24cache_convolution_kernelPKfPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z39__device_stub__cache_convolution_kernelPKfPfii, .Lfunc_end6-_Z39__device_stub__cache_convolution_kernelPKfPfii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24tiled_convolution_kernelPKfPfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24cache_convolution_kernelPKfPfii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$200, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	mask,@object                    # @mask
	.local	mask
	.comm	mask,200,16
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" Error = "
	.size	.L.str, 10

	.type	_Z24tiled_convolution_kernelPKfPfii,@object # @_Z24tiled_convolution_kernelPKfPfii
	.section	.rodata,"a",@progbits
	.globl	_Z24tiled_convolution_kernelPKfPfii
	.p2align	3, 0x0
_Z24tiled_convolution_kernelPKfPfii:
	.quad	_Z39__device_stub__tiled_convolution_kernelPKfPfii
	.size	_Z24tiled_convolution_kernelPKfPfii, 8

	.type	_Z24cache_convolution_kernelPKfPfii,@object # @_Z24cache_convolution_kernelPKfPfii
	.globl	_Z24cache_convolution_kernelPKfPfii
	.p2align	3, 0x0
_Z24cache_convolution_kernelPKfPfii:
	.quad	_Z39__device_stub__cache_convolution_kernelPKfPfii
	.size	_Z24cache_convolution_kernelPKfPfii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Convolution with tiling and halo runtime: "
	.size	.L.str.1, 43

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"ms "
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Convolution with L2 cache use runtime: "
	.size	.L.str.3, 40

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z24tiled_convolution_kernelPKfPfii"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z24cache_convolution_kernelPKfPfii"
	.size	.L__unnamed_2, 36

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"mask"
	.size	.L__unnamed_3, 5

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__tiled_convolution_kernelPKfPfii
	.addrsig_sym _Z39__device_stub__cache_convolution_kernelPKfPfii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym mask
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z24tiled_convolution_kernelPKfPfii
	.addrsig_sym _Z24cache_convolution_kernelPKfPfii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24tiled_convolution_kernelPKfPfii ; -- Begin function _Z24tiled_convolution_kernelPKfPfii
	.globl	_Z24tiled_convolution_kernelPKfPfii
	.p2align	8
	.type	_Z24tiled_convolution_kernelPKfPfii,@function
_Z24tiled_convolution_kernelPKfPfii:    ; @_Z24tiled_convolution_kernelPKfPfii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b32 s6, s[0:1], 0x24
	s_load_b128 s[0:3], s[0:1], 0x0
                                        ; implicit-def: $vgpr3
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s5, 31
	s_and_b32 s6, s6, 0xffff
	s_add_i32 s7, s5, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s7, s7, 1
	s_sub_i32 s8, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v0
	s_and_saveexec_b32 s8, vcc_lo
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_add_i32 s9, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s9, s6, v[0:1]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s9, exec_lo
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v3, s7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v1, s6, v3
	v_lshlrev_b32_e32 v1, 2, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
.LBB0_4:                                ; %Flow49
	s_and_not1_saveexec_b32 s8, s8
; %bb.5:                                ; %._crit_edge31
	v_add_nc_u32_e32 v3, s7, v0
; %bb.6:
	s_or_b32 exec_lo, exec_lo, s8
	v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s7, v0
	global_load_b32 v4, v[4:5], off
	v_lshlrev_b32_e32 v5, 2, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.7:
	v_add_nc_u32_e32 v3, s6, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v3
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s4
	v_lshl_add_u32 v3, s6, 2, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v2
.LBB0_10:                               ; %Flow48
	s_or_b32 exec_lo, exec_lo, s7
	s_cmp_lt_i32 s5, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_13
; %bb.11:                               ; %.lr.ph.preheader
	v_lshlrev_b32_e32 v2, 2, v0
	v_mov_b32_e32 v0, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, mask@rel32@lo+4
	s_addc_u32 s1, s1, mask@rel32@hi+12
.LBB0_12:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v3, v2
	s_load_b32 s4, s[0:1], 0x0
	s_add_i32 s5, s5, -1
	v_add_nc_u32_e32 v2, 4, v2
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s5, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v0, s4, v3
	s_cbranch_scc0 .LBB0_12
	s_branch .LBB0_14
.LBB0_13:
	v_mov_b32_e32 v0, 0
.LBB0_14:                               ; %Flow47
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24tiled_convolution_kernelPKfPfii
		.amdhsa_group_segment_fixed_size 2244
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24tiled_convolution_kernelPKfPfii, .Lfunc_end0-_Z24tiled_convolution_kernelPKfPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2244 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24cache_convolution_kernelPKfPfii ; -- Begin function _Z24cache_convolution_kernelPKfPfii
	.globl	_Z24cache_convolution_kernelPKfPfii
	.p2align	8
	.type	_Z24cache_convolution_kernelPKfPfii,@function
_Z24cache_convolution_kernelPKfPfii:    ; @_Z24cache_convolution_kernelPKfPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s8, s2, 2
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mul_i32 s10, s8, s15
	v_add_nc_u32_e32 v3, s10, v0
	s_add_i32 s1, s10, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s3, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, 0x1000, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s0, s3, s0
	s_clause 0x3
	global_load_b32 v8, v[4:5], off
	global_load_b32 v4, v[4:5], off offset:2048
	global_load_b32 v9, v[6:7], off
	global_load_b32 v7, v[6:7], off offset:2048
	s_ashr_i32 s11, s0, 1
	v_lshlrev_b32_e32 v5, 2, v0
	v_subrev_nc_u32_e32 v6, s11, v3
	s_cmp_gt_i32 s3, 0
	s_waitcnt vmcnt(2)
	ds_store_2addr_stride64_b32 v5, v8, v4 offset1:8
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v5, v9, v7 offset0:16 offset1:24
	s_cselect_b32 s12, -1, 0
	s_cmp_lt_i32 s3, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_9
; %bb.1:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v6
	s_lshl_b32 s0, s11, 2
	s_mov_b32 s13, s3
	v_subrev_nc_u32_e32 v0, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v4
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, mask@rel32@lo+4
	s_addc_u32 s9, s9, mask@rel32@hi+12
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v3
	v_cmp_gt_i32_e64 s0, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB1_8
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s15, s[8:9], 0x0
	v_cmp_gt_i32_e32 vcc_lo, s10, v3
	v_cmp_le_i32_e64 s0, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s16, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s16
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v7, s15, v8
.LBB1_5:                                ; %Flow104
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_2 Depth=1
	ds_load_b32 v8, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, s15, v8
.LBB1_7:                                ; %Flow105
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s13, s13, -1
	v_add_nc_u32_e32 v3, 1, v3
	v_add_nc_u32_e32 v0, 4, v0
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s13, 0
	s_cbranch_scc0 .LBB1_2
	s_branch .LBB1_10
.LBB1_9:
	v_mov_b32_e32 v7, 0
.LBB1_10:                               ; %._crit_edge
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_cndmask_b32_e64 v4, 0, 1, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s12
	global_store_b32 v[0:1], v7, off
	s_cbranch_vccnz .LBB1_19
; %bb.11:                               ; %.lr.ph.1
	s_lshl_b32 s0, s11, 2
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 0x200, v6
	v_subrev_nc_u32_e32 v7, s0, v5
	s_mov_b32 s8, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, mask@rel32@lo+4
	s_addc_u32 s7, s7, mask@rel32@hi+12
	v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v8, 0x800, v7
.LBB1_12:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_18
; %bb.13:                               ;   in Loop: Header=BB1_12 Depth=1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[6:7], 0x0
	v_cmp_gt_i32_e32 vcc_lo, s10, v2
	v_cmp_le_i32_e64 s0, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s13
	s_cbranch_execz .LBB1_15
; %bb.14:                               ;   in Loop: Header=BB1_12 Depth=1
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v7, s12, v9
.LBB1_15:                               ; %Flow100
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_17
; %bb.16:                               ;   in Loop: Header=BB1_12 Depth=1
	ds_load_b32 v9, v8
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, s12, v9
.LBB1_17:                               ; %Flow101
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_18:                               ;   in Loop: Header=BB1_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v8, 4, v8
	s_add_i32 s8, s8, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB1_12
	s_branch .LBB1_20
.LBB1_19:
	v_mov_b32_e32 v7, 0
.LBB1_20:                               ; %._crit_edge.1
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	global_store_b32 v[0:1], v7, off offset:2048
	s_cbranch_vccnz .LBB1_29
; %bb.21:                               ; %.lr.ph.2
	s_lshl_b32 s0, s11, 2
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 0x400, v6
	v_subrev_nc_u32_e32 v7, s0, v5
	s_mov_b32 s8, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, mask@rel32@lo+4
	s_addc_u32 s7, s7, mask@rel32@hi+12
	v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v8, 0x1000, v7
.LBB1_22:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_28
; %bb.23:                               ;   in Loop: Header=BB1_22 Depth=1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[6:7], 0x0
	v_cmp_gt_i32_e32 vcc_lo, s10, v2
	v_cmp_le_i32_e64 s0, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s13
	s_cbranch_execz .LBB1_25
; %bb.24:                               ;   in Loop: Header=BB1_22 Depth=1
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v7, s12, v9
.LBB1_25:                               ; %Flow96
                                        ;   in Loop: Header=BB1_22 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_22 Depth=1
	ds_load_b32 v9, v8
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, s12, v9
.LBB1_27:                               ; %Flow97
                                        ;   in Loop: Header=BB1_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_28:                               ;   in Loop: Header=BB1_22 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v8, 4, v8
	s_add_i32 s8, s8, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB1_22
	s_branch .LBB1_30
.LBB1_29:
	v_mov_b32_e32 v7, 0
.LBB1_30:                               ; %._crit_edge.2
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	v_add_co_u32 v0, s0, 0x1000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	global_store_b32 v[0:1], v7, off
	s_cbranch_vccnz .LBB1_39
; %bb.31:                               ; %.lr.ph.3
	s_lshl_b32 s0, s11, 2
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 0x600, v6
	v_subrev_nc_u32_e32 v4, s0, v5
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, mask@rel32@lo+4
	s_addc_u32 s7, s7, mask@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v4, v3 :: v_dual_add_nc_u32 v5, 0x1800, v4
.LBB1_32:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB1_38
; %bb.33:                               ;   in Loop: Header=BB1_32 Depth=1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s9, s[6:7], 0x0
	v_cmp_gt_i32_e32 vcc_lo, s10, v2
	v_cmp_le_i32_e64 s0, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s11, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s11
	s_cbranch_execz .LBB1_35
; %bb.34:                               ;   in Loop: Header=BB1_32 Depth=1
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v4, s9, v6
.LBB1_35:                               ; %Flow
                                        ;   in Loop: Header=BB1_32 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_37
; %bb.36:                               ;   in Loop: Header=BB1_32 Depth=1
	ds_load_b32 v6, v5
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v4, s9, v6
.LBB1_37:                               ; %Flow93
                                        ;   in Loop: Header=BB1_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_38:                               ;   in Loop: Header=BB1_32 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v5, 4, v5
	s_add_i32 s3, s3, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s3, 0
	s_cbranch_scc1 .LBB1_32
	s_branch .LBB1_40
.LBB1_39:
	v_mov_b32_e32 v4, 0
.LBB1_40:                               ; %._crit_edge.3
	global_store_b32 v[0:1], v4, off offset:2048
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24cache_convolution_kernelPKfPfii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z24cache_convolution_kernelPKfPfii, .Lfunc_end1-_Z24cache_convolution_kernelPKfPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1308
; NumSgprs: 19
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	mask                    ; @mask
	.type	mask,@object
	.section	.bss,"aw",@nobits
	.globl	mask
	.p2align	4, 0x0
mask:
	.zero	200
	.size	mask, 200

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym mask
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2244
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24tiled_convolution_kernelPKfPfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24tiled_convolution_kernelPKfPfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24cache_convolution_kernelPKfPfii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z24cache_convolution_kernelPKfPfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
