#include <algorithm>
#include <iostream>
#include <vector>


#include <time.h>

typedef unsigned long long data_t;

static inline void check(cudaError_t err, const char* context) {
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << context << ": "
            << cudaGetErrorString(err) << std::endl;
        std::exit(EXIT_FAILURE);
    }
}

#define CHECK(x) check(x, #x)

const int MAX_CONSTANT = 16*1024;
__constant__ unsigned int const_sum[MAX_CONSTANT];


template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, cudaMemcpyKind direction) {
CHECK(cudaMemcpy(target, source, num * sizeof(T), direction));
}

static inline int divup(int a, int b) {
    return (a + b - 1)/b;
  }

// get the 0 bit of each number by bit_shift
// example: number : 10001, bit_shit: 1, One: 1,
// 
// it means check if the second bit is 1 or not.
__global__ void getMask(data_t *d_in, unsigned int *d_out, const int len, const unsigned int n, data_t bit_shift, unsigned int One) {
    unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
    data_t bit = 0;
    data_t one=1;
    data_t shift=one<<bit_shift;
    unsigned int start=index*len;
    if (start>=n) return;
    unsigned int end=start+len;
    for(unsigned int i=start;i<end && i<n; i++ ){
      bit=d_in[i]&shift;
      bit = (bit > 0) ? 1 : 0;
      d_out[i] = (One ? bit : 1 - bit);
    }
}

__global__ void getIndex(unsigned int *d_index, unsigned int *d_sum, unsigned int* d_mask, const int len, const unsigned int n,
    unsigned int total_pre) {
    unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
    
    unsigned int start=index*len;
  
    if (start>=n) return;
    

    unsigned int end=start+len;
    for (unsigned int i=start; i<end && i<n; i++){
      d_index[i]=d_mask[i]?d_sum[i]:i-d_sum[i]+total_pre;
      if(d_index[i]>=n){
        printf(" d_sum[i] : %d, total_pre : %d, d_mask[i] : %d \n", d_sum[i], total_pre, d_mask[i]);
      }
      // if(d_mask[i]==1){
      //   d_index[i]=total_pre+d_sum[i];
      // }
    }
}

__global__ void scatter(data_t *d_in, unsigned int *d_index, data_t *d_out, const int len, const unsigned int n) {
    unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;

    unsigned int start=index*len;
    if (start>=n) return;
    unsigned int end=start+len;

    for(unsigned int i=start;i<end && i<n; i++ ){
      d_out[d_index[i]]=d_in[i];
    }
}






// // pay attention that blockDim.x must be power of 2
// __global__ void blellochScan(unsigned int *out, unsigned int *in,
//                               unsigned int *sum, unsigned int inputSize) {
//   __shared__ unsigned int temp[2 * 256];
//   unsigned int start = blockIdx.x * blockDim.x << 1;
//   unsigned int tx = threadIdx.x;
//   unsigned int index = 0;
//   temp[tx] = (start + tx < inputSize)? in[start+tx]:0;

//   temp[tx+blockDim.x] = (start + tx + blockDim.x < inputSize)? in[start + tx + blockDim.x] : 0;

//   // Blelloch Scan
//   __syncthreads();
//   // reduction step
//   unsigned int stride = 1;
//   while (stride <= blockDim.x) {
//     index = (tx + 1) * (stride << 1) - 1;
//     if (index < (blockDim.x << 1)) {
//       temp[index] += temp[index - stride];
//     }
//     stride <<= 1;
//     __syncthreads();
//   }
//   // first store the reduction sum in sum array
//   // make it zero since it is exclusive scan
//   if (tx == 0) {
//     // sum array contains the prefix sum of each
//     // 2*blockDim blocks of element.
//     if (sum != NULL) {
//       sum[blockIdx.x] = temp[(blockDim.x << 1) - 1];
//     }
//     temp[(blockDim.x << 1) - 1] = 0;
//   }
//   // wait for thread zero to write
//   __syncthreads();
//   // post scan step
//   stride = blockDim.x;
//   index = 0;
//   unsigned int var = 0;
//   while (stride > 0) {
//     index = ((stride << 1) * (tx + 1)) - 1;
//     if (index < (blockDim.x << 1)) {
//       var = temp[index];
//       temp[index] += temp[index - stride];
//       temp[index - stride] = var;
//     }
//     stride >>= 1;
//     __syncthreads();
//   }

//   // now write the temp array to output
//   if (start + tx < inputSize) {
//     out[start + tx] = temp[tx];
//   }
//   if (start + tx + blockDim.x < inputSize) {
//     out[start + tx + blockDim.x] = temp[tx + blockDim.x];
//   }
// }

// /* 
// sum out the blocks' accumulated sums to each element
// */
// __global__ void mergeScanBlocks(unsigned int *sum, unsigned int *output,
//                                 unsigned int opSize) {
//   unsigned int index = (blockDim.x * blockIdx.x << 1) + threadIdx.x;
//   if (index < opSize) {
//     // output[index] += sum[blockIdx.x];
//     output[index] += (opSize > MAX_CONSTANT)? sum[blockIdx.x]:const_sum[blockIdx.x];
//     // output[index] += tex1Dfetch(tex_sum, blockIdx.x);
//   }
//   if (index + blockDim.x < opSize) {
//     // output[index + blockDim.x] += sum[blockIdx.x];
//     output[index + blockDim.x] += (opSize > MAX_CONSTANT)? sum[blockIdx.x]:const_sum[blockIdx.x];
//     // output[index + blockDim.x] += tex1Dfetch(tex_sum, blockIdx.x);
//   }
// }

// /* 
// api for exclusiveScan
// */
// void exclusiveScan(unsigned int *out, unsigned int *in, unsigned int in_size, unsigned int block_size) {
//   unsigned int numBlocks1 = in_size / block_size;
//   if (in_size % block_size) numBlocks1++;
//   unsigned int numBlocks2 = numBlocks1 / 2;
//   if (numBlocks1 % 2) numBlocks2++;
//   dim3 dimThreadBlock;
//   dimThreadBlock.x = block_size;
//   dimThreadBlock.y = 1;
//   dimThreadBlock.z = 1;
//   dim3 dimGrid;
//   dimGrid.x = numBlocks2;
//   dimGrid.y = 1;
//   dimGrid.z = 1;

//   unsigned int *d_sumArr = NULL;
//   if (in_size > (2 * block_size)) {
//     // we need the sum auxilarry  array only if nuFmblocks2 > 1
//     CHECK(cudaMalloc((void **)&d_sumArr, numBlocks2 * sizeof(unsigned int)));
//   }
//   blellochScan<<<dimGrid, dimThreadBlock>>>(out, in, d_sumArr, in_size);

//   if (in_size <= (2 * block_size)) {
//     // out has proper exclusive scan. just return
//     CHECK(cudaDeviceSynchronize());
//     return;
//   } else {
//     // now we need to perform exclusive scan on the auxilliary sum array
//     unsigned int *d_sumArr_scan;
//     CHECK(cudaMalloc((void **)&d_sumArr_scan, numBlocks2 * sizeof(unsigned int)));
//     exclusiveScan(d_sumArr_scan, d_sumArr, numBlocks2, block_size);
//     // d_sumArr_scan now contains the exclusive scan op of individual blocks
//     // now just do a one-one addition of blocks
//     // cudaBindTexture(0, tex_sum, d_sumArr_scan, numBlocks2 * sizeof(unsigned int));
//     if(numBlocks2 <= MAX_CONSTANT) {
//       CHECK(cudaMemcpyToSymbol(const_sum, d_sumArr_scan, numBlocks2 * sizeof(unsigned int), 0, cudaMemcpyDeviceToDevice));
//     }
//     mergeScanBlocks<<<dimGrid, dimThreadBlock>>>(d_sumArr_scan, out, in_size);
//     // cudaUnbindTexture(tex_sum);
    
//     cudaFree(d_sumArr);
//     cudaFree(d_sumArr_scan);
//   }
// }
#define MAX_BLOCK_SZ 128
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5

//#define ZERO_BANK_CONFLICTS

#ifdef ZERO_BANK_CONFLICTS
#define CONFLICT_FREE_OFFSET(n) \
    ((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#else
#define CONFLICT_FREE_OFFSET(n) ((n) >> LOG_NUM_BANKS)
#endif

__global__
void gpu_add_block_sums(unsigned int* const d_out,
    const unsigned int* const d_in,
    unsigned int* const d_block_sums,
    const size_t numElems)
{
    unsigned int d_block_sum_val = d_block_sums[blockIdx.x];

    // Simple implementation's performance is not significantly (if at all)
    //  better than previous verbose implementation
    unsigned int cpy_idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
    if (cpy_idx < numElems)
    {
        d_out[cpy_idx] = d_in[cpy_idx] + d_block_sum_val;
        if (cpy_idx + blockDim.x < numElems)
            d_out[cpy_idx + blockDim.x] = d_in[cpy_idx + blockDim.x] + d_block_sum_val;
    }
}


__global__
void gpu_prescan(unsigned int* const d_out,
    const unsigned int* const d_in,
    unsigned int* const d_block_sums,
    const unsigned int len,
    const unsigned int shmem_sz,
    const unsigned int max_elems_per_block)
{
    // Allocated on invocation
    extern __shared__ unsigned int s_out[];

    int thid = threadIdx.x;
    int ai = thid;
    int bi = thid + blockDim.x;

    // Zero out the shared memory
    // Helpful especially when input size is not power of two
    s_out[thid] = 0;
    s_out[thid + blockDim.x] = 0;
    // If CONFLICT_FREE_OFFSET is used, shared memory size
    //  must be a 2 * blockDim.x + blockDim.x/num_banks
    s_out[thid + blockDim.x + (blockDim.x >> LOG_NUM_BANKS)] = 0;
    
    __syncthreads();
    
    // Copy d_in to shared memory
    // Note that d_in's elements are scattered into shared memory
    //  in light of avoiding bank conflicts
    unsigned int cpy_idx = max_elems_per_block * blockIdx.x + threadIdx.x;
    if (cpy_idx < len)
    {
        s_out[ai + CONFLICT_FREE_OFFSET(ai)] = d_in[cpy_idx];
        if (cpy_idx + blockDim.x < len)
            s_out[bi + CONFLICT_FREE_OFFSET(bi)] = d_in[cpy_idx + blockDim.x];
    }

    // For both upsweep and downsweep:
    // Sequential indices with conflict free padding
    //  Amount of padding = target index / num banks
    //  This "shifts" the target indices by one every multiple
    //   of the num banks
    // offset controls the stride and starting index of 
    //  target elems at every iteration
    // d just controls which threads are active
    // Sweeps are pivoted on the last element of shared memory

    // Upsweep/Reduce step
    int offset = 1;
    for (int d = max_elems_per_block >> 1; d > 0; d >>= 1)
    {
        __syncthreads();

        if (thid < d)
        {
            int ai = offset * ((thid << 1) + 1) - 1;
            int bi = offset * ((thid << 1) + 2) - 1;
            ai += CONFLICT_FREE_OFFSET(ai);
            bi += CONFLICT_FREE_OFFSET(bi);

            s_out[bi] += s_out[ai];
        }
        offset <<= 1;
    }

    // Save the total sum on the global block sums array
    // Then clear the last element on the shared memory
    if (thid == 0) 
    { 
        d_block_sums[blockIdx.x] = s_out[max_elems_per_block - 1 
            + CONFLICT_FREE_OFFSET(max_elems_per_block - 1)];
        s_out[max_elems_per_block - 1 
            + CONFLICT_FREE_OFFSET(max_elems_per_block - 1)] = 0;
    }

    // Downsweep step
    for (int d = 1; d < max_elems_per_block; d <<= 1)
    {
        offset >>= 1;
        __syncthreads();

        if (thid < d)
        {
            int ai = offset * ((thid << 1) + 1) - 1;
            int bi = offset * ((thid << 1) + 2) - 1;
            ai += CONFLICT_FREE_OFFSET(ai);
            bi += CONFLICT_FREE_OFFSET(bi);

            unsigned int temp = s_out[ai];
            s_out[ai] = s_out[bi];
            s_out[bi] += temp;
        }
    }
    __syncthreads();

    // Copy contents of shared memory to global memory
    if (cpy_idx < len)
    {
        d_out[cpy_idx] = s_out[ai + CONFLICT_FREE_OFFSET(ai)];
        if (cpy_idx + blockDim.x < len)
            d_out[cpy_idx + blockDim.x] = s_out[bi + CONFLICT_FREE_OFFSET(bi)];
    }
}
 
void sum_scan_blelloch(unsigned int* const d_out,
    const unsigned int* const d_in,
    const size_t numElems)
{
    // Zero out d_out
    CHECK(cudaMemset(d_out, 0, numElems * sizeof(unsigned int)));

    // Set up number of threads and blocks
    
    unsigned int block_sz = MAX_BLOCK_SZ / 2;
    unsigned int max_elems_per_block = 2 * block_sz; // due to binary tree nature of algorithm

    // If input size is not power of two, the remainder will still need a whole block
    // Thus, number of blocks must be the ceiling of input size / max elems that a block can handle
    //unsigned int grid_sz = (unsigned int) std::ceil((double) numElems / (double) max_elems_per_block);
    // UPDATE: Instead of using ceiling and risking miscalculation due to precision, just automatically  
    //  add 1 to the grid size when the input size cannot be divided cleanly by the block's capacity
    unsigned int grid_sz = numElems / max_elems_per_block;
    // Take advantage of the fact that integer division drops the decimals
    if (numElems % max_elems_per_block != 0) 
        grid_sz += 1;

    // Conflict free padding requires that shared memory be more than 2 * block_sz
    unsigned int shmem_sz = max_elems_per_block + ((max_elems_per_block) >> LOG_NUM_BANKS);

    // Allocate memory for array of total sums produced by each block
    // Array length must be the same as number of blocks
    unsigned int* d_block_sums;
    CHECK(cudaMalloc(&d_block_sums, sizeof(unsigned int) * grid_sz));
    CHECK(cudaMemset(d_block_sums, 0, sizeof(unsigned int) * grid_sz));

    // Sum scan data allocated to each block
    //gpu_sum_scan_blelloch<<<grid_sz, block_sz, sizeof(unsigned int) * max_elems_per_block >>>(d_out, d_in, d_block_sums, numElems);
    gpu_prescan<<<grid_sz, block_sz, sizeof(unsigned int) * shmem_sz>>>(d_out, 
                                                                    d_in, 
                                                                    d_block_sums, 
                                                                    numElems, 
                                                                    shmem_sz,
                                                                    max_elems_per_block);

    // Sum scan total sums produced by each block
    // Use basic implementation if number of total sums is <= 2 * block_sz
    //  (This requires only one block to do the scan)
    if (grid_sz <= max_elems_per_block)
    {
        unsigned int* d_dummy_blocks_sums;
        CHECK(cudaMalloc(&d_dummy_blocks_sums, sizeof(unsigned int)));
        CHECK(cudaMemset(d_dummy_blocks_sums, 0, sizeof(unsigned int)));
        //gpu_sum_scan_blelloch<<<1, block_sz, sizeof(unsigned int) * max_elems_per_block>>>(d_block_sums, d_block_sums, d_dummy_blocks_sums, grid_sz);
        gpu_prescan<<<1, block_sz, sizeof(unsigned int) * shmem_sz>>>(d_block_sums, 
                                                                    d_block_sums, 
                                                                    d_dummy_blocks_sums, 
                                                                    grid_sz, 
                                                                    shmem_sz,
                                                                    max_elems_per_block);
        CHECK(cudaFree(d_dummy_blocks_sums));
    }
    // Else, recurse on this same function as you'll need the full-blown scan
    //  for the block sums
    else
    {
        unsigned int* d_in_block_sums;
        CHECK(cudaMalloc(&d_in_block_sums, sizeof(unsigned int) * grid_sz));
        CHECK(cudaMemcpy(d_in_block_sums, d_block_sums, sizeof(unsigned int) * grid_sz, cudaMemcpyDeviceToDevice));
        sum_scan_blelloch(d_block_sums, d_in_block_sums, grid_sz);
        CHECK(cudaFree(d_in_block_sums));
    }
    
    // Add each block's total sum to its scan output
    // in order to get the final, global scanned array
    gpu_add_block_sums<<<grid_sz, block_sz>>>(d_out, d_out, d_block_sums, numElems);

    CHECK(cudaFree(d_block_sums));
}




// idea to do exclusive prefix is similar to my ppc course https://www.youtube.com/watch?v=HVhCtl96gUs
// I will use y,z,s to specify which step I am in.
// in particular, I split the whole array into multiple smaller array. each small array has [len] numbers
// Thread level y: each thread will do addition sequentially. threads are working independently, dealing with [len] numbers.
// Thread level z: each threads in the same block will do sequentially. threads are working independently, dealing with one block.
// Thread level s: each thread will add the result from its previous thread. threads are working independently, dealing with [len] numbers.
// Block level y: this will get prefix sum in block level. 
// Block level z: only one block and one thread are used here, do addition sequentially.
// Block level s: each threads will add the result from its previous block.
__global__ void prefixsum(unsigned int* mask, unsigned int* output,const int len, const unsigned int n ){
  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  int start=index*len+1;//exclusive
  if (start>n) return; //exclusive, could equal to n
  int end=start+step;
  output[start]=mask[start-1];
  for(unsigned int i=start+1;i<end&&i<n;i++){
    output[i]+=output[i-1]+mask[i-1];//exclusive, therefore mask[i-1]
  }
}


__global__ void serialsum_accrossthread(unsigned int* sum,const int len, const unsigned int n){
  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  int offset=2*step;
  unsigned int start=step*blockDim.x*index+offset;
  unsigned int end=step*blockDim.x*(index+1)+1;
  for(unsigned int i=start;i<end && i<n; i+=step){
    sum[i]+=sum[i-step];
  }
}

__global__ void mergethread(unsigned int* sum,const int len, const unsigned int n){
  if (threadIdx.x==0) return;

  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  unsigned int start=index*step+1;//exclusive
  unsigned int end=start+step-1; // -1 is important, this position has been added in serial sum
  unsigned int base=sum[start-1];

  for(unsigned int i=start; i<end && i<n; i++){
    sum[i]+=base;
  }

}

// void serialsum_accrossblock(unsigned int* sum,const int len, const unsigned int n, const int block_size){
//   int step=len*block_size;//each block has step number
//   int start=2*step;
//   for(unsigned int i=start; i<n; i+=step){
//     sum[i]+=sum[i-step];
//   }
// }



__global__ void serialsum_accrossblock(unsigned int* sum,const int len, const unsigned int n, const int block_size){
  //only one block and one thread
  int step=len*block_size;//each block has step number
  int start=2*step;
  for(unsigned int i=start; i<n; i+=step){
    sum[i]+=sum[i-step];
  }
}

// __global__ void mergeblock(unsigned int* sum,const int len, const unsigned int n){
//   unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
//   if (index==0) return;  //the first block is not needed to merge
//   int step=len*blockDim.x;
//   int start=index*step+1; //exclusive
//   int end=start+step-1;// -1 is important, this position has been added in serial sum
//   int base=sum[start-1];//last element at last block
//   for(int i=start; i<end && i<n; i++){
//     sum[i]+=base;
//   }
// }

__global__ void mergeblock(unsigned int* sum,const int len, const unsigned int n){
  if (blockIdx.x==0) return;//the first block is not needed to merge
  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  unsigned int base_index=blockIdx.x*step*blockDim.x;
  unsigned int base=sum[base_index];
  int start=index*step; //only the first thread in block should excluded the first element
  int end=start+step;
  start=(start==base_index)?start+1:start;
  
  // int base=sum[start-1];//last element at last block
  
  for(int i=start; i<end && i<n; i++){
    sum[i]+=base;
  }
}

void psort(int n, data_t *data) {
  if(n<=0) return;
  // FIXME: Implement a more efficient parallel sorting algorithm for the GPU.

  const int block_size=256;//64 threads per block;
  const int len=2000; // add 1000 prefix sum per thread; 

  data_t *d_temp;
  data_t *d_in=NULL;
  CHECK(cudaMalloc((void**)&d_in,n*sizeof(data_t)));

  data_t *d_out_long=NULL;
  CHECK(cudaMalloc((void**)&d_out_long,n*sizeof(data_t)));
  unsigned int *d_out=NULL;
  CHECK(cudaMalloc((void**)&d_out,n*sizeof(unsigned int)));
  unsigned int *d_sum=NULL;
  CHECK(cudaMalloc((void**)&d_sum,n*sizeof(unsigned int)));
  unsigned int *d_index=NULL;
  CHECK(cudaMalloc((void**)&d_index,n*sizeof(unsigned int)));

  // std::vector<unsigned int> inter_sum(n);
  // unsigned int inter_sum[n];

  cuda_memcpy(d_in,data,n,cudaMemcpyHostToDevice);

  data_t bits=sizeof(data_t)*8;

  // unsigned int out[n];
  // unsigned int sum[n];
  unsigned int total_zeros, mask_last;
  //one pass here
  clock_t test = clock();
  for(data_t i=0; i<bits; i++){
      CHECK(cudaMemset(d_sum,0,n*sizeof(unsigned int)));
      getMask<<<divup(n,block_size*len),block_size>>>(d_in, d_out, len, n, i, 0);
      CHECK(cudaGetLastError());
      // CHECK(cudaMemcpy(out, d_out, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // std::cout<<"out "<<std::endl;
      // for(int j=0;j<n;j++){
      //   std::cout<<out[j]<<" ";
      // }
      // std::cout<<std::endl;


      // //inclusive prefix sum
      // prefixsum<<<divup(n,block_size*len),block_size>>>(d_out,d_sum,len,n);
      // CHECK(cudaGetLastError());
      // serialsum_accrossthread<<<divup(n,block_size*len*block_size),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      // mergethread<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      // serialsum_accrossblock<<<1,1>>>(d_sum, len, n, block_size);
      // CHECK(cudaGetLastError());
      // // CHECK(cudaMemcpy(inter_sum.data(), d_sum, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // // serialsum_accrossblock(inter_sum.data(), len, n, block_size);
      // // CHECK(cudaMemcpy(d_sum, inter_sum.data(),n * sizeof(unsigned int), cudaMemcpyHostToDevice));
      // // CHECK(cudaGetLastError());
      // mergeblock<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      clock_t start = clock();
      sum_scan_blelloch(d_sum, d_out, n);
      std::cout<<"time: "<<double(clock()-start)/CLOCKS_PER_SEC<<std::endl;
      // exclusiveScan(d_sum, d_out, n, block_size);
      // CHECK(cudaMemcpy(sum, d_sum, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // std::cout<<"sum "<<std::endl;
      // for(int j=0;j<n;j++){
      //   std::cout<<sum[j]<<" ";
      // }
      // std::cout<<std::endl;
      CHECK(cudaMemcpy(&total_zeros, d_sum+n-1, sizeof(unsigned int), cudaMemcpyDeviceToHost));
      CHECK(cudaMemcpy(&mask_last, d_out+n-1, sizeof(unsigned int), cudaMemcpyDeviceToHost));

      total_zeros+=(mask_last==1)?1:0;

      getIndex<<<divup(n,block_size*len),block_size>>>(d_index, d_sum, d_out, len, n, total_zeros);
      // std::cout<<"index "<<std::endl;
      // CHECK(cudaMemcpy(sum, d_index, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // for(int j=0;j<n;j++){
      //   std::cout<<sum[j]<<" ";
      // }
      // std::cout<<std::endl;
      CHECK(cudaGetLastError());

      // // get mask for 1 and store in d_out
      // getMask<<<divup(n,block_size*len),block_size>>>(d_in, d_out, len, n, i, 1);

      // CHECK(cudaGetLastError());
      // //inclusive prefix sum
      // CHECK(cudaMemset(d_sum,0,n*sizeof(unsigned int)));
      // prefixsum<<<divup(n,block_size*len),block_size>>>(d_out,d_sum,len,n);
      // CHECK(cudaGetLastError());
      // serialsum_accrossthread<<<divup(n,block_size*len*block_size),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      // mergethread<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());

      // // CHECK(cudaMemcpy(inter_sum.data() , d_sum, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // // serialsum_accrossblock(inter_sum.data(), len, n, block_size);
      // // CHECK(cudaMemcpy(d_sum, inter_sum.data(),n * sizeof(unsigned int), cudaMemcpyHostToDevice));

      // serialsum_accrossblock<<<1,1>>>(d_sum, len, n, block_size);
      // CHECK(cudaGetLastError());
      // mergeblock<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());

      
      // getIndex<<<divup(n,block_size*len),block_size>>>(d_index, d_sum, d_out, len, n, total_zeros);
      // CHECK(cudaGetLastError());


      scatter<<<divup(n,block_size*len),block_size>>>(d_in, d_index, d_out_long, len, n);

      CHECK(cudaGetLastError());
      //must swap pointers
      d_temp = d_in;
      d_in = d_out_long;
      d_out_long = d_temp;
  }
  std::cout<<"total: "<<double(clock()-test)/CLOCKS_PER_SEC<<std::endl;
  cuda_memcpy(data, d_in, n, cudaMemcpyDeviceToHost);
  CHECK(cudaFree(d_in));
  CHECK(cudaFree(d_out_long));
  CHECK(cudaFree(d_out));
  CHECK(cudaFree(d_sum));
  CHECK(cudaFree(d_index));
  // std::sort(data, data + n);
}
	.file	"tmpxft_003ba5ae_00000000-6_so_better_scan.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4259:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4259:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	": "
	.text
	.type	_ZL5check9cudaErrorPKc, @function
_ZL5check9cudaErrorPKc:
.LFB4252:
	.cfi_startproc
	testl	%edi, %edi
	je	.L2
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE4252:
	.size	_ZL5check9cudaErrorPKc, .-_ZL5check9cudaErrorPKc
	.globl	_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj
	.type	_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj, @function
_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj:
.LFB4281:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7getMaskPyPjijyj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4281:
	.size	_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj, .-_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj
	.globl	_Z7getMaskPyPjijyj
	.type	_Z7getMaskPyPjijyj, @function
_Z7getMaskPyPjijyj:
.LFB4282:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj
	.cfi_endproc
.LFE4282:
	.size	_Z7getMaskPyPjijyj, .-_Z7getMaskPyPjijyj
	.globl	_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj
	.type	_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj, @function
_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj:
.LFB4283:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8getIndexPjS_S_ijj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4283:
	.size	_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj, .-_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj
	.globl	_Z8getIndexPjS_S_ijj
	.type	_Z8getIndexPjS_S_ijj, @function
_Z8getIndexPjS_S_ijj:
.LFB4284:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj
	.cfi_endproc
.LFE4284:
	.size	_Z8getIndexPjS_S_ijj, .-_Z8getIndexPjS_S_ijj
	.globl	_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij
	.type	_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij, @function
_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij:
.LFB4285:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7scatterPyPjS_ij(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4285:
	.size	_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij, .-_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij
	.globl	_Z7scatterPyPjS_ij
	.type	_Z7scatterPyPjS_ij, @function
_Z7scatterPyPjS_ij:
.LFB4286:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij
	.cfi_endproc
.LFE4286:
	.size	_Z7scatterPyPjS_ij, .-_Z7scatterPyPjS_ij
	.globl	_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m
	.type	_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m, @function
_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m:
.LFB4287:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18gpu_add_block_sumsPjPKjS_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4287:
	.size	_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m, .-_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m
	.globl	_Z18gpu_add_block_sumsPjPKjS_m
	.type	_Z18gpu_add_block_sumsPjPKjS_m, @function
_Z18gpu_add_block_sumsPjPKjS_m:
.LFB4288:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m
	.cfi_endproc
.LFE4288:
	.size	_Z18gpu_add_block_sumsPjPKjS_m, .-_Z18gpu_add_block_sumsPjPKjS_m
	.globl	_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj
	.type	_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj, @function
_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj:
.LFB4289:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z11gpu_prescanPjPKjS_jjj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L28:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4289:
	.size	_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj, .-_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj
	.globl	_Z11gpu_prescanPjPKjS_jjj
	.type	_Z11gpu_prescanPjPKjS_jjj, @function
_Z11gpu_prescanPjPKjS_jjj:
.LFB4290:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj
	.cfi_endproc
.LFE4290:
	.size	_Z11gpu_prescanPjPKjS_jjj, .-_Z11gpu_prescanPjPKjS_jjj
	.section	.rodata.str1.1
.LC2:
	.string	"cudaMemset(d_out, 0, numElems * sizeof(unsigned int))"
.LC3:
	.string	"cudaMalloc(&d_block_sums, sizeof(unsigned int) * grid_sz)"
.LC4:
	.string	"cudaMemset(d_block_sums, 0, sizeof(unsigned int) * grid_sz)"
.LC5:
	.string	"cudaMalloc(&d_dummy_blocks_sums, sizeof(unsigned int))"
.LC6:
	.string	"cudaMemset(d_dummy_blocks_sums, 0, sizeof(unsigned int))"
.LC7:
	.string	"cudaFree(d_dummy_blocks_sums)"
.LC8:
	.string	"cudaMalloc(&d_in_block_sums, sizeof(unsigned int) * grid_sz)"
.LC9:
	.string	"cudaMemcpy(d_in_block_sums, d_block_sums, sizeof(unsigned int) * grid_sz, cudaMemcpyDeviceToDevice)"
.LC10:
	.string	"cudaFree(d_in_block_sums)"
.LC11:
	.string	"cudaFree(d_block_sums)"
	.text
	.globl	_Z17sum_scan_blellochPjPKjm
	.type	_Z17sum_scan_blellochPjPKjm, @function
_Z17sum_scan_blellochPjPKjm:
.LFB4255:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	xorl	%esi, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdx, %rbx
	salq	$2, %rdx
	movq	%rbx, %rbp
	shrq	$7, %rbp
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	cudaMemset@PLT
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	%rbx, %rax
	leaq	8(%rsp), %rdi
	andl	$127, %eax
	cmpq	$1, %rax
	sbbl	$-1, %ebp
	movl	%ebp, %r14d
	leaq	0(,%r14,4), %r13
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movl	%ebp, 28(%rsp)
	movl	$67108865, %edx
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	28(%rsp), %rdi
	salq	$6, %rdx
	xorl	%r9d, %r9d
	movl	36(%rsp), %esi
	movl	$528, %r8d
	movl	$1, %ecx
	movq	%rdx, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	8(%rsp), %rdx
	movl	$128, %r9d
	movl	%ebx, %ecx
	movq	%r15, %rsi
	movl	$132, %r8d
	movq	%r12, %rdi
	call	_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj
.L35:
	cmpl	$128, %ebp
	ja	.L36
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	16(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	salq	$6, %rdx
	movl	$528, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rdi, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rdx
	movl	$128, %r9d
	movl	%ebp, %ecx
	movl	$132, %r8d
	movq	%rdi, %rsi
	call	_Z39__device_stub__Z11gpu_prescanPjPKjS_jjjPjPKjS_jjj
.L37:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC7(%rip), %rsi
	movl	%eax, %edi
	jmp	.L44
.L36:
	leaq	40(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leaq	.LC8(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	8(%rsp), %rsi
	movq	40(%rsp), %rdi
	movq	%r13, %rdx
	movl	$3, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC9(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movq	%r14, %rdx
	call	_Z17sum_scan_blellochPjPKjm
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
.L44:
	call	_ZL5check9cudaErrorPKc
	movl	%ebp, 28(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$67108865, %edx
	movl	$1, %ecx
	movl	$1, 48(%rsp)
	movq	%rax, 32(%rsp)
	movq	28(%rsp), %rdi
	salq	$6, %rdx
	movl	36(%rsp), %esi
	movq	%rdx, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	8(%rsp), %rdx
	movq	%rbx, %rcx
	movq	%r12, %rsi
	movq	%r12, %rdi
	call	_Z44__device_stub__Z18gpu_add_block_sumsPjPKjS_mPjPKjS_m
.L39:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC11(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4255:
	.size	_Z17sum_scan_blellochPjPKjm, .-_Z17sum_scan_blellochPjPKjm
	.section	.rodata.str1.1
.LC12:
	.string	"cudaMalloc((void**)&d_in,n*sizeof(data_t))"
.LC13:
	.string	"cudaMalloc((void**)&d_out_long,n*sizeof(data_t))"
.LC14:
	.string	"cudaMalloc((void**)&d_out,n*sizeof(unsigned int))"
.LC15:
	.string	"cudaMalloc((void**)&d_sum,n*sizeof(unsigned int))"
.LC16:
	.string	"cudaMalloc((void**)&d_index,n*sizeof(unsigned int))"
.LC17:
	.string	"cudaMemcpy(target, source, num * sizeof(T), direction)"
.LC18:
	.string	"cudaMemset(d_sum,0,n*sizeof(unsigned int))"
.LC19:
	.string	"cudaGetLastError()"
.LC20:
	.string	"time: "
.LC22:
	.string	"cudaMemcpy(&total_zeros, d_sum+n-1, sizeof(unsigned int), cudaMemcpyDeviceToHost)"
.LC23:
	.string	"cudaMemcpy(&mask_last, d_out+n-1, sizeof(unsigned int), cudaMemcpyDeviceToHost)"
.LC24:
	.string	"total: "
.LC25:
	.string	"cudaFree(d_in)"
.LC26:
	.string	"cudaFree(d_out_long)"
.LC27:
	.string	"cudaFree(d_out)"
.LC28:
	.string	"cudaFree(d_sum)"
.LC29:
	.string	"cudaFree(d_index)"
	.text
	.globl	_Z5psortiPy
	.type	_Z5psortiPy, @function
_Z5psortiPy:
.LFB4256:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%rsi, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	testl	%edi, %edi
	jle	.L45
	movslq	%edi, %r14
	xorl	%eax, %eax
	movl	%edi, %ebx
	xorl	%r13d, %r13d
	movq	%rax, 56(%rsp)
	leaq	56(%rsp), %rdi
	leaq	0(,%r14,8), %rax
	movabsq	$4294967552, %r12
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	movabsq	$4294967297, %r15
	call	cudaMalloc@PLT
	leaq	.LC12(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	8(%rsp), %rsi
	xorl	%edx, %edx
	leaq	64(%rsp), %rdi
	movq	%rdx, 64(%rsp)
	call	cudaMalloc@PLT
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	leaq	0(,%r14,4), %rax
	xorl	%ecx, %ecx
	leaq	72(%rsp), %rdi
	movq	%rax, %rsi
	movq	%rcx, 72(%rsp)
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	leaq	.LC14(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	80(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	movq	(%rsp), %rsi
	call	cudaMalloc@PLT
	leaq	.LC15(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	(%rsp), %rsi
	xorl	%edi, %edi
	movq	%rdi, 88(%rsp)
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC16(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC17(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	call	clock@PLT
	movl	$512000, %ecx
	movq	%rax, 24(%rsp)
	leal	511999(%rbx), %eax
	cltd
	idivl	%ecx
	movl	%eax, %ebp
.L50:
	movq	(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	.LC18(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	%r15, 100(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%ebp, 96(%rsp)
	movl	104(%rsp), %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	movq	%r12, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	movq	72(%rsp), %rsi
	movq	56(%rsp), %rdi
	xorl	%r9d, %r9d
	movq	%r13, %r8
	movl	%ebx, %ecx
	movl	$2000, %edx
	call	_Z32__device_stub__Z7getMaskPyPjijyjPyPjijyj
.L47:
	call	cudaGetLastError@PLT
	leaq	.LC19(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	call	clock@PLT
	movq	72(%rsp), %rsi
	movq	80(%rsp), %rdi
	movq	%r14, %rdx
	movq	%rax, 40(%rsp)
	call	_Z17sum_scan_blellochPjPKjm
	leaq	.LC20(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, 32(%rsp)
	call	clock@PLT
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdi
	subq	%rcx, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC21(%rip), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	(%rsp), %rax
	movl	$2, %ecx
	movl	$4, %edx
	leaq	48(%rsp), %rdi
	leaq	-4(%rax), %r8
	movq	%r8, %rsi
	addq	80(%rsp), %rsi
	movq	%r8, 32(%rsp)
	call	cudaMemcpy@PLT
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movl	$2, %ecx
	movl	$4, %edx
	movq	32(%rsp), %rsi
	leaq	52(%rsp), %rdi
	addq	72(%rsp), %rsi
	call	cudaMemcpy@PLT
	leaq	.LC23(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	%r15, 100(%rsp)
	xorl	%eax, %eax
	movl	104(%rsp), %esi
	cmpl	$1, 52(%rsp)
	movl	%ebp, 96(%rsp)
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	sete	%al
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addl	%eax, 48(%rsp)
	movq	%r12, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movl	48(%rsp), %r9d
	movq	72(%rsp), %rdx
	movl	%ebx, %r8d
	movl	$2000, %ecx
	movq	80(%rsp), %rsi
	movq	88(%rsp), %rdi
	call	_Z34__device_stub__Z8getIndexPjS_S_ijjPjS_S_ijj
.L48:
	call	cudaGetLastError@PLT
	leaq	.LC19(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	%r15, 100(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%ebp, 96(%rsp)
	movl	104(%rsp), %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	movq	%r12, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	movq	64(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	%ebx, %r8d
	movl	$2000, %ecx
	movq	56(%rsp), %rdi
	call	_Z32__device_stub__Z7scatterPyPjS_ijPyPjS_ij
.L49:
	call	cudaGetLastError@PLT
	leaq	.LC19(%rip), %rsi
	incq	%r13
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	56(%rsp), %rax
	movq	64(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	%rdx, 56(%rsp)
	cmpq	$64, %r13
	jne	.L50
	leaq	.LC24(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rbx
	call	clock@PLT
	movq	24(%rsp), %rdx
	movq	%rbx, %rdi
	subq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC21(%rip), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC17(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC25(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC26(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC27(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC28(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC29(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
.L45:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4256:
	.size	_Z5psortiPy, .-_Z5psortiPy
	.globl	_Z32__device_stub__Z9prefixsumPjS_ijPjS_ij
	.type	_Z32__device_stub__Z9prefixsumPjS_ijPjS_ij, @function
_Z32__device_stub__Z9prefixsumPjS_ijPjS_ij:
.LFB4291:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9prefixsumPjS_ij(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L54:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4291:
	.size	_Z32__device_stub__Z9prefixsumPjS_ijPjS_ij, .-_Z32__device_stub__Z9prefixsumPjS_ijPjS_ij
	.globl	_Z9prefixsumPjS_ij
	.type	_Z9prefixsumPjS_ij, @function
_Z9prefixsumPjS_ij:
.LFB4292:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9prefixsumPjS_ijPjS_ij
	.cfi_endproc
.LFE4292:
	.size	_Z9prefixsumPjS_ij, .-_Z9prefixsumPjS_ij
	.globl	_Z45__device_stub__Z23serialsum_accrossthreadPjijPjij
	.type	_Z45__device_stub__Z23serialsum_accrossthreadPjijPjij, @function
_Z45__device_stub__Z23serialsum_accrossthreadPjijPjij:
.LFB4293:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z23serialsum_accrossthreadPjij(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4293:
	.size	_Z45__device_stub__Z23serialsum_accrossthreadPjijPjij, .-_Z45__device_stub__Z23serialsum_accrossthreadPjijPjij
	.globl	_Z23serialsum_accrossthreadPjij
	.type	_Z23serialsum_accrossthreadPjij, @function
_Z23serialsum_accrossthreadPjij:
.LFB4294:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z23serialsum_accrossthreadPjijPjij
	.cfi_endproc
.LFE4294:
	.size	_Z23serialsum_accrossthreadPjij, .-_Z23serialsum_accrossthreadPjij
	.globl	_Z33__device_stub__Z11mergethreadPjijPjij
	.type	_Z33__device_stub__Z11mergethreadPjijPjij, @function
_Z33__device_stub__Z11mergethreadPjijPjij:
.LFB4295:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11mergethreadPjij(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L64:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4295:
	.size	_Z33__device_stub__Z11mergethreadPjijPjij, .-_Z33__device_stub__Z11mergethreadPjijPjij
	.globl	_Z11mergethreadPjij
	.type	_Z11mergethreadPjij, @function
_Z11mergethreadPjij:
.LFB4296:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z11mergethreadPjijPjij
	.cfi_endproc
.LFE4296:
	.size	_Z11mergethreadPjij, .-_Z11mergethreadPjij
	.globl	_Z45__device_stub__Z22serialsum_accrossblockPjijiPjiji
	.type	_Z45__device_stub__Z22serialsum_accrossblockPjijiPjiji, @function
_Z45__device_stub__Z22serialsum_accrossblockPjijiPjiji:
.LFB4297:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22serialsum_accrossblockPjiji(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L69:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4297:
	.size	_Z45__device_stub__Z22serialsum_accrossblockPjijiPjiji, .-_Z45__device_stub__Z22serialsum_accrossblockPjijiPjiji
	.globl	_Z22serialsum_accrossblockPjiji
	.type	_Z22serialsum_accrossblockPjiji, @function
_Z22serialsum_accrossblockPjiji:
.LFB4298:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z22serialsum_accrossblockPjijiPjiji
	.cfi_endproc
.LFE4298:
	.size	_Z22serialsum_accrossblockPjiji, .-_Z22serialsum_accrossblockPjiji
	.globl	_Z32__device_stub__Z10mergeblockPjijPjij
	.type	_Z32__device_stub__Z10mergeblockPjijPjij, @function
_Z32__device_stub__Z10mergeblockPjijPjij:
.LFB4299:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10mergeblockPjij(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L74:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4299:
	.size	_Z32__device_stub__Z10mergeblockPjijPjij, .-_Z32__device_stub__Z10mergeblockPjijPjij
	.globl	_Z10mergeblockPjij
	.type	_Z10mergeblockPjij, @function
_Z10mergeblockPjij:
.LFB4300:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10mergeblockPjijPjij
	.cfi_endproc
.LFE4300:
	.size	_Z10mergeblockPjij, .-_Z10mergeblockPjij
	.section	.rodata.str1.1
.LC30:
	.string	"_Z10mergeblockPjij"
.LC31:
	.string	"_Z22serialsum_accrossblockPjiji"
.LC32:
	.string	"_Z11mergethreadPjij"
.LC33:
	.string	"_Z23serialsum_accrossthreadPjij"
.LC34:
	.string	"_Z9prefixsumPjS_ij"
.LC35:
	.string	"_Z11gpu_prescanPjPKjS_jjj"
.LC36:
	.string	"_Z18gpu_add_block_sumsPjPKjS_m"
.LC37:
	.string	"_Z7scatterPyPjS_ij"
.LC38:
	.string	"_Z8getIndexPjS_S_ijj"
.LC39:
	.string	"_Z7getMaskPyPjijyj"
.LC40:
	.string	"const_sum"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4302:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10mergeblockPjij(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z22serialsum_accrossblockPjiji(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC32(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11mergethreadPjij(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z23serialsum_accrossthreadPjij(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9prefixsumPjS_ij(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC35(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11gpu_prescanPjPKjS_jjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18gpu_add_block_sumsPjPKjS_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7scatterPyPjS_ij(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC38(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z8getIndexPjS_S_ijj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7getMaskPyPjijyj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC40(%rip), %rdx
	movl	$65536, %r9d
	leaq	_ZL9const_sum(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4302:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL9const_sum
	.comm	_ZL9const_sum,65536,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC21:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>


#include <time.h>

typedef unsigned long long data_t;

static inline void check(hipError_t err, const char* context) {
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << context << ": "
            << hipGetErrorString(err) << std::endl;
        std::exit(EXIT_FAILURE);
    }
}

#define CHECK(x) check(x, #x)

const int MAX_CONSTANT = 16*1024;
__constant__ unsigned int const_sum[MAX_CONSTANT];


template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}

static inline int divup(int a, int b) {
    return (a + b - 1)/b;
  }

// get the 0 bit of each number by bit_shift
// example: number : 10001, bit_shit: 1, One: 1,
// 
// it means check if the second bit is 1 or not.
__global__ void getMask(data_t *d_in, unsigned int *d_out, const int len, const unsigned int n, data_t bit_shift, unsigned int One) {
    unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
    data_t bit = 0;
    data_t one=1;
    data_t shift=one<<bit_shift;
    unsigned int start=index*len;
    if (start>=n) return;
    unsigned int end=start+len;
    for(unsigned int i=start;i<end && i<n; i++ ){
      bit=d_in[i]&shift;
      bit = (bit > 0) ? 1 : 0;
      d_out[i] = (One ? bit : 1 - bit);
    }
}

__global__ void getIndex(unsigned int *d_index, unsigned int *d_sum, unsigned int* d_mask, const int len, const unsigned int n,
    unsigned int total_pre) {
    unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
    
    unsigned int start=index*len;
  
    if (start>=n) return;
    

    unsigned int end=start+len;
    for (unsigned int i=start; i<end && i<n; i++){
      d_index[i]=d_mask[i]?d_sum[i]:i-d_sum[i]+total_pre;
      if(d_index[i]>=n){
        printf(" d_sum[i] : %d, total_pre : %d, d_mask[i] : %d \n", d_sum[i], total_pre, d_mask[i]);
      }
      // if(d_mask[i]==1){
      //   d_index[i]=total_pre+d_sum[i];
      // }
    }
}

__global__ void scatter(data_t *d_in, unsigned int *d_index, data_t *d_out, const int len, const unsigned int n) {
    unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;

    unsigned int start=index*len;
    if (start>=n) return;
    unsigned int end=start+len;

    for(unsigned int i=start;i<end && i<n; i++ ){
      d_out[d_index[i]]=d_in[i];
    }
}






// // pay attention that blockDim.x must be power of 2
// __global__ void blellochScan(unsigned int *out, unsigned int *in,
//                               unsigned int *sum, unsigned int inputSize) {
//   __shared__ unsigned int temp[2 * 256];
//   unsigned int start = blockIdx.x * blockDim.x << 1;
//   unsigned int tx = threadIdx.x;
//   unsigned int index = 0;
//   temp[tx] = (start + tx < inputSize)? in[start+tx]:0;

//   temp[tx+blockDim.x] = (start + tx + blockDim.x < inputSize)? in[start + tx + blockDim.x] : 0;

//   // Blelloch Scan
//   __syncthreads();
//   // reduction step
//   unsigned int stride = 1;
//   while (stride <= blockDim.x) {
//     index = (tx + 1) * (stride << 1) - 1;
//     if (index < (blockDim.x << 1)) {
//       temp[index] += temp[index - stride];
//     }
//     stride <<= 1;
//     __syncthreads();
//   }
//   // first store the reduction sum in sum array
//   // make it zero since it is exclusive scan
//   if (tx == 0) {
//     // sum array contains the prefix sum of each
//     // 2*blockDim blocks of element.
//     if (sum != NULL) {
//       sum[blockIdx.x] = temp[(blockDim.x << 1) - 1];
//     }
//     temp[(blockDim.x << 1) - 1] = 0;
//   }
//   // wait for thread zero to write
//   __syncthreads();
//   // post scan step
//   stride = blockDim.x;
//   index = 0;
//   unsigned int var = 0;
//   while (stride > 0) {
//     index = ((stride << 1) * (tx + 1)) - 1;
//     if (index < (blockDim.x << 1)) {
//       var = temp[index];
//       temp[index] += temp[index - stride];
//       temp[index - stride] = var;
//     }
//     stride >>= 1;
//     __syncthreads();
//   }

//   // now write the temp array to output
//   if (start + tx < inputSize) {
//     out[start + tx] = temp[tx];
//   }
//   if (start + tx + blockDim.x < inputSize) {
//     out[start + tx + blockDim.x] = temp[tx + blockDim.x];
//   }
// }

// /* 
// sum out the blocks' accumulated sums to each element
// */
// __global__ void mergeScanBlocks(unsigned int *sum, unsigned int *output,
//                                 unsigned int opSize) {
//   unsigned int index = (blockDim.x * blockIdx.x << 1) + threadIdx.x;
//   if (index < opSize) {
//     // output[index] += sum[blockIdx.x];
//     output[index] += (opSize > MAX_CONSTANT)? sum[blockIdx.x]:const_sum[blockIdx.x];
//     // output[index] += tex1Dfetch(tex_sum, blockIdx.x);
//   }
//   if (index + blockDim.x < opSize) {
//     // output[index + blockDim.x] += sum[blockIdx.x];
//     output[index + blockDim.x] += (opSize > MAX_CONSTANT)? sum[blockIdx.x]:const_sum[blockIdx.x];
//     // output[index + blockDim.x] += tex1Dfetch(tex_sum, blockIdx.x);
//   }
// }

// /* 
// api for exclusiveScan
// */
// void exclusiveScan(unsigned int *out, unsigned int *in, unsigned int in_size, unsigned int block_size) {
//   unsigned int numBlocks1 = in_size / block_size;
//   if (in_size % block_size) numBlocks1++;
//   unsigned int numBlocks2 = numBlocks1 / 2;
//   if (numBlocks1 % 2) numBlocks2++;
//   dim3 dimThreadBlock;
//   dimThreadBlock.x = block_size;
//   dimThreadBlock.y = 1;
//   dimThreadBlock.z = 1;
//   dim3 dimGrid;
//   dimGrid.x = numBlocks2;
//   dimGrid.y = 1;
//   dimGrid.z = 1;

//   unsigned int *d_sumArr = NULL;
//   if (in_size > (2 * block_size)) {
//     // we need the sum auxilarry  array only if nuFmblocks2 > 1
//     CHECK(cudaMalloc((void **)&d_sumArr, numBlocks2 * sizeof(unsigned int)));
//   }
//   blellochScan<<<dimGrid, dimThreadBlock>>>(out, in, d_sumArr, in_size);

//   if (in_size <= (2 * block_size)) {
//     // out has proper exclusive scan. just return
//     CHECK(cudaDeviceSynchronize());
//     return;
//   } else {
//     // now we need to perform exclusive scan on the auxilliary sum array
//     unsigned int *d_sumArr_scan;
//     CHECK(cudaMalloc((void **)&d_sumArr_scan, numBlocks2 * sizeof(unsigned int)));
//     exclusiveScan(d_sumArr_scan, d_sumArr, numBlocks2, block_size);
//     // d_sumArr_scan now contains the exclusive scan op of individual blocks
//     // now just do a one-one addition of blocks
//     // cudaBindTexture(0, tex_sum, d_sumArr_scan, numBlocks2 * sizeof(unsigned int));
//     if(numBlocks2 <= MAX_CONSTANT) {
//       CHECK(cudaMemcpyToSymbol(const_sum, d_sumArr_scan, numBlocks2 * sizeof(unsigned int), 0, cudaMemcpyDeviceToDevice));
//     }
//     mergeScanBlocks<<<dimGrid, dimThreadBlock>>>(d_sumArr_scan, out, in_size);
//     // cudaUnbindTexture(tex_sum);
    
//     cudaFree(d_sumArr);
//     cudaFree(d_sumArr_scan);
//   }
// }
#define MAX_BLOCK_SZ 128
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5

//#define ZERO_BANK_CONFLICTS

#ifdef ZERO_BANK_CONFLICTS
#define CONFLICT_FREE_OFFSET(n) \
    ((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#else
#define CONFLICT_FREE_OFFSET(n) ((n) >> LOG_NUM_BANKS)
#endif

__global__
void gpu_add_block_sums(unsigned int* const d_out,
    const unsigned int* const d_in,
    unsigned int* const d_block_sums,
    const size_t numElems)
{
    unsigned int d_block_sum_val = d_block_sums[blockIdx.x];

    // Simple implementation's performance is not significantly (if at all)
    //  better than previous verbose implementation
    unsigned int cpy_idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
    if (cpy_idx < numElems)
    {
        d_out[cpy_idx] = d_in[cpy_idx] + d_block_sum_val;
        if (cpy_idx + blockDim.x < numElems)
            d_out[cpy_idx + blockDim.x] = d_in[cpy_idx + blockDim.x] + d_block_sum_val;
    }
}


__global__
void gpu_prescan(unsigned int* const d_out,
    const unsigned int* const d_in,
    unsigned int* const d_block_sums,
    const unsigned int len,
    const unsigned int shmem_sz,
    const unsigned int max_elems_per_block)
{
    // Allocated on invocation
    extern __shared__ unsigned int s_out[];

    int thid = threadIdx.x;
    int ai = thid;
    int bi = thid + blockDim.x;

    // Zero out the shared memory
    // Helpful especially when input size is not power of two
    s_out[thid] = 0;
    s_out[thid + blockDim.x] = 0;
    // If CONFLICT_FREE_OFFSET is used, shared memory size
    //  must be a 2 * blockDim.x + blockDim.x/num_banks
    s_out[thid + blockDim.x + (blockDim.x >> LOG_NUM_BANKS)] = 0;
    
    __syncthreads();
    
    // Copy d_in to shared memory
    // Note that d_in's elements are scattered into shared memory
    //  in light of avoiding bank conflicts
    unsigned int cpy_idx = max_elems_per_block * blockIdx.x + threadIdx.x;
    if (cpy_idx < len)
    {
        s_out[ai + CONFLICT_FREE_OFFSET(ai)] = d_in[cpy_idx];
        if (cpy_idx + blockDim.x < len)
            s_out[bi + CONFLICT_FREE_OFFSET(bi)] = d_in[cpy_idx + blockDim.x];
    }

    // For both upsweep and downsweep:
    // Sequential indices with conflict free padding
    //  Amount of padding = target index / num banks
    //  This "shifts" the target indices by one every multiple
    //   of the num banks
    // offset controls the stride and starting index of 
    //  target elems at every iteration
    // d just controls which threads are active
    // Sweeps are pivoted on the last element of shared memory

    // Upsweep/Reduce step
    int offset = 1;
    for (int d = max_elems_per_block >> 1; d > 0; d >>= 1)
    {
        __syncthreads();

        if (thid < d)
        {
            int ai = offset * ((thid << 1) + 1) - 1;
            int bi = offset * ((thid << 1) + 2) - 1;
            ai += CONFLICT_FREE_OFFSET(ai);
            bi += CONFLICT_FREE_OFFSET(bi);

            s_out[bi] += s_out[ai];
        }
        offset <<= 1;
    }

    // Save the total sum on the global block sums array
    // Then clear the last element on the shared memory
    if (thid == 0) 
    { 
        d_block_sums[blockIdx.x] = s_out[max_elems_per_block - 1 
            + CONFLICT_FREE_OFFSET(max_elems_per_block - 1)];
        s_out[max_elems_per_block - 1 
            + CONFLICT_FREE_OFFSET(max_elems_per_block - 1)] = 0;
    }

    // Downsweep step
    for (int d = 1; d < max_elems_per_block; d <<= 1)
    {
        offset >>= 1;
        __syncthreads();

        if (thid < d)
        {
            int ai = offset * ((thid << 1) + 1) - 1;
            int bi = offset * ((thid << 1) + 2) - 1;
            ai += CONFLICT_FREE_OFFSET(ai);
            bi += CONFLICT_FREE_OFFSET(bi);

            unsigned int temp = s_out[ai];
            s_out[ai] = s_out[bi];
            s_out[bi] += temp;
        }
    }
    __syncthreads();

    // Copy contents of shared memory to global memory
    if (cpy_idx < len)
    {
        d_out[cpy_idx] = s_out[ai + CONFLICT_FREE_OFFSET(ai)];
        if (cpy_idx + blockDim.x < len)
            d_out[cpy_idx + blockDim.x] = s_out[bi + CONFLICT_FREE_OFFSET(bi)];
    }
}
 
void sum_scan_blelloch(unsigned int* const d_out,
    const unsigned int* const d_in,
    const size_t numElems)
{
    // Zero out d_out
    CHECK(hipMemset(d_out, 0, numElems * sizeof(unsigned int)));

    // Set up number of threads and blocks
    
    unsigned int block_sz = MAX_BLOCK_SZ / 2;
    unsigned int max_elems_per_block = 2 * block_sz; // due to binary tree nature of algorithm

    // If input size is not power of two, the remainder will still need a whole block
    // Thus, number of blocks must be the ceiling of input size / max elems that a block can handle
    //unsigned int grid_sz = (unsigned int) std::ceil((double) numElems / (double) max_elems_per_block);
    // UPDATE: Instead of using ceiling and risking miscalculation due to precision, just automatically  
    //  add 1 to the grid size when the input size cannot be divided cleanly by the block's capacity
    unsigned int grid_sz = numElems / max_elems_per_block;
    // Take advantage of the fact that integer division drops the decimals
    if (numElems % max_elems_per_block != 0) 
        grid_sz += 1;

    // Conflict free padding requires that shared memory be more than 2 * block_sz
    unsigned int shmem_sz = max_elems_per_block + ((max_elems_per_block) >> LOG_NUM_BANKS);

    // Allocate memory for array of total sums produced by each block
    // Array length must be the same as number of blocks
    unsigned int* d_block_sums;
    CHECK(hipMalloc(&d_block_sums, sizeof(unsigned int) * grid_sz));
    CHECK(hipMemset(d_block_sums, 0, sizeof(unsigned int) * grid_sz));

    // Sum scan data allocated to each block
    //gpu_sum_scan_blelloch<<<grid_sz, block_sz, sizeof(unsigned int) * max_elems_per_block >>>(d_out, d_in, d_block_sums, numElems);
    gpu_prescan<<<grid_sz, block_sz, sizeof(unsigned int) * shmem_sz>>>(d_out, 
                                                                    d_in, 
                                                                    d_block_sums, 
                                                                    numElems, 
                                                                    shmem_sz,
                                                                    max_elems_per_block);

    // Sum scan total sums produced by each block
    // Use basic implementation if number of total sums is <= 2 * block_sz
    //  (This requires only one block to do the scan)
    if (grid_sz <= max_elems_per_block)
    {
        unsigned int* d_dummy_blocks_sums;
        CHECK(hipMalloc(&d_dummy_blocks_sums, sizeof(unsigned int)));
        CHECK(hipMemset(d_dummy_blocks_sums, 0, sizeof(unsigned int)));
        //gpu_sum_scan_blelloch<<<1, block_sz, sizeof(unsigned int) * max_elems_per_block>>>(d_block_sums, d_block_sums, d_dummy_blocks_sums, grid_sz);
        gpu_prescan<<<1, block_sz, sizeof(unsigned int) * shmem_sz>>>(d_block_sums, 
                                                                    d_block_sums, 
                                                                    d_dummy_blocks_sums, 
                                                                    grid_sz, 
                                                                    shmem_sz,
                                                                    max_elems_per_block);
        CHECK(hipFree(d_dummy_blocks_sums));
    }
    // Else, recurse on this same function as you'll need the full-blown scan
    //  for the block sums
    else
    {
        unsigned int* d_in_block_sums;
        CHECK(hipMalloc(&d_in_block_sums, sizeof(unsigned int) * grid_sz));
        CHECK(hipMemcpy(d_in_block_sums, d_block_sums, sizeof(unsigned int) * grid_sz, hipMemcpyDeviceToDevice));
        sum_scan_blelloch(d_block_sums, d_in_block_sums, grid_sz);
        CHECK(hipFree(d_in_block_sums));
    }
    
    // Add each block's total sum to its scan output
    // in order to get the final, global scanned array
    gpu_add_block_sums<<<grid_sz, block_sz>>>(d_out, d_out, d_block_sums, numElems);

    CHECK(hipFree(d_block_sums));
}




// idea to do exclusive prefix is similar to my ppc course https://www.youtube.com/watch?v=HVhCtl96gUs
// I will use y,z,s to specify which step I am in.
// in particular, I split the whole array into multiple smaller array. each small array has [len] numbers
// Thread level y: each thread will do addition sequentially. threads are working independently, dealing with [len] numbers.
// Thread level z: each threads in the same block will do sequentially. threads are working independently, dealing with one block.
// Thread level s: each thread will add the result from its previous thread. threads are working independently, dealing with [len] numbers.
// Block level y: this will get prefix sum in block level. 
// Block level z: only one block and one thread are used here, do addition sequentially.
// Block level s: each threads will add the result from its previous block.
__global__ void prefixsum(unsigned int* mask, unsigned int* output,const int len, const unsigned int n ){
  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  int start=index*len+1;//exclusive
  if (start>n) return; //exclusive, could equal to n
  int end=start+step;
  output[start]=mask[start-1];
  for(unsigned int i=start+1;i<end&&i<n;i++){
    output[i]+=output[i-1]+mask[i-1];//exclusive, therefore mask[i-1]
  }
}


__global__ void serialsum_accrossthread(unsigned int* sum,const int len, const unsigned int n){
  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  int offset=2*step;
  unsigned int start=step*blockDim.x*index+offset;
  unsigned int end=step*blockDim.x*(index+1)+1;
  for(unsigned int i=start;i<end && i<n; i+=step){
    sum[i]+=sum[i-step];
  }
}

__global__ void mergethread(unsigned int* sum,const int len, const unsigned int n){
  if (threadIdx.x==0) return;

  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  unsigned int start=index*step+1;//exclusive
  unsigned int end=start+step-1; // -1 is important, this position has been added in serial sum
  unsigned int base=sum[start-1];

  for(unsigned int i=start; i<end && i<n; i++){
    sum[i]+=base;
  }

}

// void serialsum_accrossblock(unsigned int* sum,const int len, const unsigned int n, const int block_size){
//   int step=len*block_size;//each block has step number
//   int start=2*step;
//   for(unsigned int i=start; i<n; i+=step){
//     sum[i]+=sum[i-step];
//   }
// }



__global__ void serialsum_accrossblock(unsigned int* sum,const int len, const unsigned int n, const int block_size){
  //only one block and one thread
  int step=len*block_size;//each block has step number
  int start=2*step;
  for(unsigned int i=start; i<n; i+=step){
    sum[i]+=sum[i-step];
  }
}

// __global__ void mergeblock(unsigned int* sum,const int len, const unsigned int n){
//   unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
//   if (index==0) return;  //the first block is not needed to merge
//   int step=len*blockDim.x;
//   int start=index*step+1; //exclusive
//   int end=start+step-1;// -1 is important, this position has been added in serial sum
//   int base=sum[start-1];//last element at last block
//   for(int i=start; i<end && i<n; i++){
//     sum[i]+=base;
//   }
// }

__global__ void mergeblock(unsigned int* sum,const int len, const unsigned int n){
  if (blockIdx.x==0) return;//the first block is not needed to merge
  unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
  int step=len;
  unsigned int base_index=blockIdx.x*step*blockDim.x;
  unsigned int base=sum[base_index];
  int start=index*step; //only the first thread in block should excluded the first element
  int end=start+step;
  start=(start==base_index)?start+1:start;
  
  // int base=sum[start-1];//last element at last block
  
  for(int i=start; i<end && i<n; i++){
    sum[i]+=base;
  }
}

void psort(int n, data_t *data) {
  if(n<=0) return;
  // FIXME: Implement a more efficient parallel sorting algorithm for the GPU.

  const int block_size=256;//64 threads per block;
  const int len=2000; // add 1000 prefix sum per thread; 

  data_t *d_temp;
  data_t *d_in=NULL;
  CHECK(hipMalloc((void**)&d_in,n*sizeof(data_t)));

  data_t *d_out_long=NULL;
  CHECK(hipMalloc((void**)&d_out_long,n*sizeof(data_t)));
  unsigned int *d_out=NULL;
  CHECK(hipMalloc((void**)&d_out,n*sizeof(unsigned int)));
  unsigned int *d_sum=NULL;
  CHECK(hipMalloc((void**)&d_sum,n*sizeof(unsigned int)));
  unsigned int *d_index=NULL;
  CHECK(hipMalloc((void**)&d_index,n*sizeof(unsigned int)));

  // std::vector<unsigned int> inter_sum(n);
  // unsigned int inter_sum[n];

  cuda_memcpy(d_in,data,n,hipMemcpyHostToDevice);

  data_t bits=sizeof(data_t)*8;

  // unsigned int out[n];
  // unsigned int sum[n];
  unsigned int total_zeros, mask_last;
  //one pass here
  clock_t test = clock();
  for(data_t i=0; i<bits; i++){
      CHECK(hipMemset(d_sum,0,n*sizeof(unsigned int)));
      getMask<<<divup(n,block_size*len),block_size>>>(d_in, d_out, len, n, i, 0);
      CHECK(hipGetLastError());
      // CHECK(cudaMemcpy(out, d_out, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // std::cout<<"out "<<std::endl;
      // for(int j=0;j<n;j++){
      //   std::cout<<out[j]<<" ";
      // }
      // std::cout<<std::endl;


      // //inclusive prefix sum
      // prefixsum<<<divup(n,block_size*len),block_size>>>(d_out,d_sum,len,n);
      // CHECK(cudaGetLastError());
      // serialsum_accrossthread<<<divup(n,block_size*len*block_size),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      // mergethread<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      // serialsum_accrossblock<<<1,1>>>(d_sum, len, n, block_size);
      // CHECK(cudaGetLastError());
      // // CHECK(cudaMemcpy(inter_sum.data(), d_sum, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // // serialsum_accrossblock(inter_sum.data(), len, n, block_size);
      // // CHECK(cudaMemcpy(d_sum, inter_sum.data(),n * sizeof(unsigned int), cudaMemcpyHostToDevice));
      // // CHECK(cudaGetLastError());
      // mergeblock<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      clock_t start = clock();
      sum_scan_blelloch(d_sum, d_out, n);
      std::cout<<"time: "<<double(clock()-start)/CLOCKS_PER_SEC<<std::endl;
      // exclusiveScan(d_sum, d_out, n, block_size);
      // CHECK(cudaMemcpy(sum, d_sum, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // std::cout<<"sum "<<std::endl;
      // for(int j=0;j<n;j++){
      //   std::cout<<sum[j]<<" ";
      // }
      // std::cout<<std::endl;
      CHECK(hipMemcpy(&total_zeros, d_sum+n-1, sizeof(unsigned int), hipMemcpyDeviceToHost));
      CHECK(hipMemcpy(&mask_last, d_out+n-1, sizeof(unsigned int), hipMemcpyDeviceToHost));

      total_zeros+=(mask_last==1)?1:0;

      getIndex<<<divup(n,block_size*len),block_size>>>(d_index, d_sum, d_out, len, n, total_zeros);
      // std::cout<<"index "<<std::endl;
      // CHECK(cudaMemcpy(sum, d_index, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // for(int j=0;j<n;j++){
      //   std::cout<<sum[j]<<" ";
      // }
      // std::cout<<std::endl;
      CHECK(hipGetLastError());

      // // get mask for 1 and store in d_out
      // getMask<<<divup(n,block_size*len),block_size>>>(d_in, d_out, len, n, i, 1);

      // CHECK(cudaGetLastError());
      // //inclusive prefix sum
      // CHECK(cudaMemset(d_sum,0,n*sizeof(unsigned int)));
      // prefixsum<<<divup(n,block_size*len),block_size>>>(d_out,d_sum,len,n);
      // CHECK(cudaGetLastError());
      // serialsum_accrossthread<<<divup(n,block_size*len*block_size),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());
      // mergethread<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());

      // // CHECK(cudaMemcpy(inter_sum.data() , d_sum, n * sizeof(unsigned int), cudaMemcpyDeviceToHost));
      // // serialsum_accrossblock(inter_sum.data(), len, n, block_size);
      // // CHECK(cudaMemcpy(d_sum, inter_sum.data(),n * sizeof(unsigned int), cudaMemcpyHostToDevice));

      // serialsum_accrossblock<<<1,1>>>(d_sum, len, n, block_size);
      // CHECK(cudaGetLastError());
      // mergeblock<<<divup(n,block_size*len),block_size>>>(d_sum,len,n);
      // CHECK(cudaGetLastError());

      
      // getIndex<<<divup(n,block_size*len),block_size>>>(d_index, d_sum, d_out, len, n, total_zeros);
      // CHECK(cudaGetLastError());


      scatter<<<divup(n,block_size*len),block_size>>>(d_in, d_index, d_out_long, len, n);

      CHECK(hipGetLastError());
      //must swap pointers
      d_temp = d_in;
      d_in = d_out_long;
      d_out_long = d_temp;
  }
  std::cout<<"total: "<<double(clock()-test)/CLOCKS_PER_SEC<<std::endl;
  cuda_memcpy(data, d_in, n, hipMemcpyDeviceToHost);
  CHECK(hipFree(d_in));
  CHECK(hipFree(d_out_long));
  CHECK(hipFree(d_out));
  CHECK(hipFree(d_sum));
  CHECK(hipFree(d_index));
  // std::sort(data, data + n);
}
	.text
	.file	"so_better_scan.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__getMaskPyPjijyj # -- Begin function _Z22__device_stub__getMaskPyPjijyj
	.type	_Z22__device_stub__getMaskPyPjijyj,@function
_Z22__device_stub__getMaskPyPjijyj:     # @_Z22__device_stub__getMaskPyPjijyj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7getMaskPyPjijyj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__getMaskPyPjijyj, .Lfunc_end0-_Z22__device_stub__getMaskPyPjijyj
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__getIndexPjS_S_ijj # -- Begin function _Z23__device_stub__getIndexPjS_S_ijj
	.type	_Z23__device_stub__getIndexPjS_S_ijj,@function
_Z23__device_stub__getIndexPjS_S_ijj:   # @_Z23__device_stub__getIndexPjS_S_ijj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8getIndexPjS_S_ijj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__getIndexPjS_S_ijj, .Lfunc_end1-_Z23__device_stub__getIndexPjS_S_ijj
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__scatterPyPjS_ij # -- Begin function _Z22__device_stub__scatterPyPjS_ij
	.type	_Z22__device_stub__scatterPyPjS_ij,@function
_Z22__device_stub__scatterPyPjS_ij:     # @_Z22__device_stub__scatterPyPjS_ij
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7scatterPyPjS_ij, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__scatterPyPjS_ij, .Lfunc_end2-_Z22__device_stub__scatterPyPjS_ij
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__gpu_add_block_sumsPjPKjS_m # -- Begin function _Z33__device_stub__gpu_add_block_sumsPjPKjS_m
	.type	_Z33__device_stub__gpu_add_block_sumsPjPKjS_m,@function
_Z33__device_stub__gpu_add_block_sumsPjPKjS_m: # @_Z33__device_stub__gpu_add_block_sumsPjPKjS_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18gpu_add_block_sumsPjPKjS_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z33__device_stub__gpu_add_block_sumsPjPKjS_m, .Lfunc_end3-_Z33__device_stub__gpu_add_block_sumsPjPKjS_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__gpu_prescanPjPKjS_jjj # -- Begin function _Z26__device_stub__gpu_prescanPjPKjS_jjj
	.type	_Z26__device_stub__gpu_prescanPjPKjS_jjj,@function
_Z26__device_stub__gpu_prescanPjPKjS_jjj: # @_Z26__device_stub__gpu_prescanPjPKjS_jjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11gpu_prescanPjPKjS_jjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z26__device_stub__gpu_prescanPjPKjS_jjj, .Lfunc_end4-_Z26__device_stub__gpu_prescanPjPKjS_jjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z17sum_scan_blellochPjPKjm     # -- Begin function _Z17sum_scan_blellochPjPKjm
	.type	_Z17sum_scan_blellochPjPKjm,@function
_Z17sum_scan_blellochPjPKjm:            # @_Z17sum_scan_blellochPjPKjm
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %rbx
	movq	%rsi, %r14
	leaq	(,%rdx,4), %rdx
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	xorl	%esi, %esi
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB5_1
# %bb.5:                                # %_ZL5check10hipError_tPKc.exit
	movq	%rbx, %r12
	shrq	$7, %r12
	movl	%ebx, %eax
	andl	$127, %eax
	cmpq	$1, %rax
	sbbl	$-1, %r12d
	leaq	(,%r12,4), %rbp
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.8:                                # %_ZL5check10hipError_tPKc.exit48
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rbp, %rdx
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB5_9
# %bb.10:                               # %_ZL5check10hipError_tPKc.exit50
	movabsq	$4294967360, %r15               # imm = 0x100000040
	leaq	(%r12,%r15), %r13
	addq	$-64, %r13
	movl	$528, %r8d                      # imm = 0x210
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_12
# %bb.11:
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rsi
	movl	%ebx, %ecx
	movl	$132, %r8d
	movl	$128, %r9d
	callq	_Z26__device_stub__gpu_prescanPjPKjS_jjj
.LBB5_12:
	movq	%rsp, %rdi
	cmpl	$128, %r12d
	ja	.LBB5_21
# %bb.13:
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_14
# %bb.15:                               # %_ZL5check10hipError_tPKc.exit52
	movq	(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.17:                               # %_ZL5check10hipError_tPKc.exit54
	leaq	-63(%r15), %rdi
	movl	$528, %r8d                      # imm = 0x210
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_19
# %bb.18:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rdx
	movq	%rdi, %rsi
	movl	%r12d, %ecx
	movl	$132, %r8d
	movl	$128, %r9d
	callq	_Z26__device_stub__gpu_prescanPjPKjS_jjj
.LBB5_19:
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	je	.LBB5_27
# %bb.20:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.5, %esi
	jmp	.LBB5_2
.LBB5_21:
	movq	%rbp, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_22
# %bb.23:                               # %_ZL5check10hipError_tPKc.exit58
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_24
# %bb.25:                               # %_ZL5check10hipError_tPKc.exit60
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	%r12, %rdx
	callq	_Z17sum_scan_blellochPjPKjm
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB5_26
.LBB5_27:
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_29
# %bb.28:
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%rdi, %rsi
	movq	%rbx, %rcx
	callq	_Z33__device_stub__gpu_add_block_sumsPjPKjS_m
.LBB5_29:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB5_30
# %bb.31:                               # %_ZL5check10hipError_tPKc.exit64
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_1:
	.cfi_def_cfa_offset 80
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str, %esi
	jmp	.LBB5_2
.LBB5_6:
	movl	%eax, %r15d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	jmp	.LBB5_7
.LBB5_9:
	movl	%eax, %r15d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
.LBB5_7:
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%r15d, %edi
	jmp	.LBB5_3
.LBB5_30:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.9, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	jmp	.LBB5_4
.LBB5_14:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.3, %esi
	jmp	.LBB5_2
.LBB5_22:
	movl	%eax, %r14d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.6, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%r14d, %edi
	jmp	.LBB5_3
.LBB5_16:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.4, %esi
	jmp	.LBB5_2
.LBB5_24:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.7, %esi
	jmp	.LBB5_2
.LBB5_26:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
.LBB5_2:
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%ebp, %edi
.LBB5_3:
	callq	hipGetErrorString
	movq	%rbx, %rdi
.LBB5_4:
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end5:
	.size	_Z17sum_scan_blellochPjPKjm, .Lfunc_end5-_Z17sum_scan_blellochPjPKjm
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__prefixsumPjS_ij # -- Begin function _Z24__device_stub__prefixsumPjS_ij
	.type	_Z24__device_stub__prefixsumPjS_ij,@function
_Z24__device_stub__prefixsumPjS_ij:     # @_Z24__device_stub__prefixsumPjS_ij
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9prefixsumPjS_ij, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z24__device_stub__prefixsumPjS_ij, .Lfunc_end6-_Z24__device_stub__prefixsumPjS_ij
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__serialsum_accrossthreadPjij # -- Begin function _Z38__device_stub__serialsum_accrossthreadPjij
	.type	_Z38__device_stub__serialsum_accrossthreadPjij,@function
_Z38__device_stub__serialsum_accrossthreadPjij: # @_Z38__device_stub__serialsum_accrossthreadPjij
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23serialsum_accrossthreadPjij, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z38__device_stub__serialsum_accrossthreadPjij, .Lfunc_end7-_Z38__device_stub__serialsum_accrossthreadPjij
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__mergethreadPjij # -- Begin function _Z26__device_stub__mergethreadPjij
	.type	_Z26__device_stub__mergethreadPjij,@function
_Z26__device_stub__mergethreadPjij:     # @_Z26__device_stub__mergethreadPjij
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11mergethreadPjij, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z26__device_stub__mergethreadPjij, .Lfunc_end8-_Z26__device_stub__mergethreadPjij
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__serialsum_accrossblockPjiji # -- Begin function _Z37__device_stub__serialsum_accrossblockPjiji
	.type	_Z37__device_stub__serialsum_accrossblockPjiji,@function
_Z37__device_stub__serialsum_accrossblockPjiji: # @_Z37__device_stub__serialsum_accrossblockPjiji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22serialsum_accrossblockPjiji, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z37__device_stub__serialsum_accrossblockPjiji, .Lfunc_end9-_Z37__device_stub__serialsum_accrossblockPjiji
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__mergeblockPjij # -- Begin function _Z25__device_stub__mergeblockPjij
	.type	_Z25__device_stub__mergeblockPjij,@function
_Z25__device_stub__mergeblockPjij:      # @_Z25__device_stub__mergeblockPjij
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10mergeblockPjij, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z25__device_stub__mergeblockPjij, .Lfunc_end10-_Z25__device_stub__mergeblockPjij
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z5psortiPy
.LCPI11_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z5psortiPy
	.type	_Z5psortiPy,@function
_Z5psortiPy:                            # @_Z5psortiPy
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%edi, %edi
	jle	.LBB11_42
# %bb.1:
	movq	%rsi, %r13
	movl	%edi, %r15d
	leaq	8(%rsp), %rdi
	movq	$0, (%rdi)
	movl	%r15d, %r14d
	leaq	(,%r14,8), %r12
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB11_2
# %bb.5:                                # %_ZL5check10hipError_tPKc.exit
	leaq	40(%rsp), %rdi
	movq	$0, (%rdi)
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB11_6
# %bb.7:                                # %_ZL5check10hipError_tPKc.exit40
	leaq	24(%rsp), %rdi
	movq	$0, (%rdi)
	leaq	(,%r14,4), %r12
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB11_8
# %bb.9:                                # %_ZL5check10hipError_tPKc.exit42
	leaq	16(%rsp), %rdi
	movq	$0, (%rdi)
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB11_10
# %bb.11:                               # %_ZL5check10hipError_tPKc.exit44
	leaq	56(%rsp), %rdi
	movq	$0, (%rdi)
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB11_12
# %bb.23:                               # %_ZL5check10hipError_tPKc.exit46
	movabsq	$4294967552, %rbp               # imm = 0x100000100
	movq	8(%rsp), %rdi
	movq	%r13, 80(%rsp)                  # 8-byte Spill
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind
	callq	clock
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	%r15, 48(%rsp)                  # 8-byte Spill
	leal	511999(%r15), %eax
	imulq	$274877907, %rax, %rax          # imm = 0x10624DD3
	shrq	$47, %rax
	leaq	(%rax,%rbp), %r13
	addq	$-256, %r13
	xorl	%ebx, %ebx
.LBB11_24:                              # =>This Inner Loop Header: Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	movq	%r12, %r15
	movq	%r12, %rdx
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB11_25
# %bb.27:                               # %_ZL5check10hipError_tPKc.exit58
                                        #   in Loop: Header=BB11_24 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_29
# %bb.28:                               #   in Loop: Header=BB11_24 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$2000, %edx                     # imm = 0x7D0
	movq	48(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movq	%rbx, %r8
	xorl	%r9d, %r9d
	callq	_Z22__device_stub__getMaskPyPjijyj
.LBB11_29:                              #   in Loop: Header=BB11_24 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB11_30
# %bb.31:                               # %_ZL5check10hipError_tPKc.exit60
                                        #   in Loop: Header=BB11_24 Depth=1
	callq	clock
	movq	%rax, %r12
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	%r14, %rdx
	callq	_Z17sum_scan_blellochPjPKjm
	movl	$_ZSt4cout, %edi
	movl	$.L.str.17, %esi
	movl	$6, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	clock
	subq	%r12, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI11_0(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	16(%rsp), %rax
	leaq	(%rax,%r14,4), %rsi
	addq	$-4, %rsi
	movl	$4, %edx
	leaq	36(%rsp), %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB11_32
# %bb.33:                               # %_ZL5check10hipError_tPKc.exit62
                                        #   in Loop: Header=BB11_24 Depth=1
	movq	24(%rsp), %rax
	leaq	(%rax,%r14,4), %rsi
	addq	$-4, %rsi
	movl	$4, %edx
	leaq	68(%rsp), %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB11_34
# %bb.35:                               # %_ZL5check10hipError_tPKc.exit64
                                        #   in Loop: Header=BB11_24 Depth=1
	xorl	%eax, %eax
	cmpl	$1, 68(%rsp)
	sete	%al
	addl	%eax, 36(%rsp)
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_37
# %bb.36:                               #   in Loop: Header=BB11_24 Depth=1
	movq	56(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	36(%rsp), %r9d
	movl	$2000, %ecx                     # imm = 0x7D0
	movq	48(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z23__device_stub__getIndexPjS_S_ijj
.LBB11_37:                              #   in Loop: Header=BB11_24 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB11_30
# %bb.38:                               # %_ZL5check10hipError_tPKc.exit66
                                        #   in Loop: Header=BB11_24 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_40
# %bb.39:                               #   in Loop: Header=BB11_24 Depth=1
	movq	8(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	$2000, %ecx                     # imm = 0x7D0
	movq	48(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z22__device_stub__scatterPyPjS_ij
.LBB11_40:                              #   in Loop: Header=BB11_24 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB11_30
# %bb.41:                               # %_ZL5check10hipError_tPKc.exit68
                                        #   in Loop: Header=BB11_24 Depth=1
	movq	8(%rsp), %rax
	movq	40(%rsp), %rcx
	movq	%rcx, 8(%rsp)
	movq	%rax, 40(%rsp)
	incq	%rbx
	cmpq	$64, %rbx
	movq	%r15, %r12
	jne	.LBB11_24
# %bb.13:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.20, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	clock
	subq	72(%rsp), %rax                  # 8-byte Folded Reload
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI11_0(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB11_14
# %bb.15:                               # %_ZL5check10hipError_tPKc.exit48
	movq	40(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB11_16
# %bb.17:                               # %_ZL5check10hipError_tPKc.exit50
	movq	24(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB11_18
# %bb.19:                               # %_ZL5check10hipError_tPKc.exit52
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB11_20
# %bb.21:                               # %_ZL5check10hipError_tPKc.exit54
	movq	56(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB11_22
.LBB11_42:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB11_30:
	.cfi_def_cfa_offset 144
	movl	%eax, %r12d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.16, %esi
	jmp	.LBB11_26
.LBB11_34:
	movl	%eax, %r12d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.19, %esi
	jmp	.LBB11_26
.LBB11_32:
	movl	%eax, %r12d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.18, %esi
	jmp	.LBB11_26
.LBB11_25:
	movl	%eax, %r12d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.15, %esi
.LBB11_26:
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%r12d, %edi
	callq	hipGetErrorString
	movq	%rbx, %rdi
.LBB11_4:
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.LBB11_2:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.10, %esi
	jmp	.LBB11_3
.LBB11_6:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.11, %esi
	jmp	.LBB11_3
.LBB11_8:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.12, %esi
	jmp	.LBB11_3
.LBB11_10:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.13, %esi
	jmp	.LBB11_3
.LBB11_12:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.14, %esi
	jmp	.LBB11_3
.LBB11_14:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.21, %esi
	jmp	.LBB11_3
.LBB11_16:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.22, %esi
	jmp	.LBB11_3
.LBB11_18:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.23, %esi
	jmp	.LBB11_3
.LBB11_20:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.24, %esi
	jmp	.LBB11_3
.LBB11_22:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.25, %esi
.LBB11_3:
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	jmp	.LBB11_4
.Lfunc_end11:
	.size	_Z5psortiPy, .Lfunc_end11-_Z5psortiPy
	.cfi_endproc
                                        # -- End function
	.section	.text._Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind,comdat
	.weak	_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind # -- Begin function _Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind
	.type	_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind,@function
_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind: # @_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	shlq	$3, %rdx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB12_2
# %bb.1:                                # %_ZL5check10hipError_tPKc.exit
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB12_2:
	.cfi_def_cfa_offset 32
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.28, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.27, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end12:
	.size	_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind, .Lfunc_end12-_Z11cuda_memcpyIyEvPT_PKS0_m13hipMemcpyKind
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB13_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB13_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7getMaskPyPjijyj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8getIndexPjS_S_ijj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7scatterPyPjS_ij, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18gpu_add_block_sumsPjPKjS_m, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11gpu_prescanPjPKjS_jjj, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9prefixsumPjS_ij, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23serialsum_accrossthreadPjij, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11mergethreadPjij, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22serialsum_accrossblockPjiji, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10mergeblockPjij, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$const_sum, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$65536, %r9d                    # imm = 0x10000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end13:
	.size	__hip_module_ctor, .Lfunc_end13-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB14_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB14_2:
	retq
.Lfunc_end14:
	.size	__hip_module_dtor, .Lfunc_end14-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	const_sum,@object               # @const_sum
	.local	const_sum
	.comm	const_sum,65536,16
	.type	_Z7getMaskPyPjijyj,@object      # @_Z7getMaskPyPjijyj
	.section	.rodata,"a",@progbits
	.globl	_Z7getMaskPyPjijyj
	.p2align	3, 0x0
_Z7getMaskPyPjijyj:
	.quad	_Z22__device_stub__getMaskPyPjijyj
	.size	_Z7getMaskPyPjijyj, 8

	.type	_Z8getIndexPjS_S_ijj,@object    # @_Z8getIndexPjS_S_ijj
	.globl	_Z8getIndexPjS_S_ijj
	.p2align	3, 0x0
_Z8getIndexPjS_S_ijj:
	.quad	_Z23__device_stub__getIndexPjS_S_ijj
	.size	_Z8getIndexPjS_S_ijj, 8

	.type	_Z7scatterPyPjS_ij,@object      # @_Z7scatterPyPjS_ij
	.globl	_Z7scatterPyPjS_ij
	.p2align	3, 0x0
_Z7scatterPyPjS_ij:
	.quad	_Z22__device_stub__scatterPyPjS_ij
	.size	_Z7scatterPyPjS_ij, 8

	.type	_Z18gpu_add_block_sumsPjPKjS_m,@object # @_Z18gpu_add_block_sumsPjPKjS_m
	.globl	_Z18gpu_add_block_sumsPjPKjS_m
	.p2align	3, 0x0
_Z18gpu_add_block_sumsPjPKjS_m:
	.quad	_Z33__device_stub__gpu_add_block_sumsPjPKjS_m
	.size	_Z18gpu_add_block_sumsPjPKjS_m, 8

	.type	_Z11gpu_prescanPjPKjS_jjj,@object # @_Z11gpu_prescanPjPKjS_jjj
	.globl	_Z11gpu_prescanPjPKjS_jjj
	.p2align	3, 0x0
_Z11gpu_prescanPjPKjS_jjj:
	.quad	_Z26__device_stub__gpu_prescanPjPKjS_jjj
	.size	_Z11gpu_prescanPjPKjS_jjj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hipMemset(d_out, 0, numElems * sizeof(unsigned int))"
	.size	.L.str, 53

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"hipMalloc(&d_block_sums, sizeof(unsigned int) * grid_sz)"
	.size	.L.str.1, 57

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"hipMemset(d_block_sums, 0, sizeof(unsigned int) * grid_sz)"
	.size	.L.str.2, 59

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipMalloc(&d_dummy_blocks_sums, sizeof(unsigned int))"
	.size	.L.str.3, 54

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipMemset(d_dummy_blocks_sums, 0, sizeof(unsigned int))"
	.size	.L.str.4, 56

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipFree(d_dummy_blocks_sums)"
	.size	.L.str.5, 29

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipMalloc(&d_in_block_sums, sizeof(unsigned int) * grid_sz)"
	.size	.L.str.6, 60

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"hipMemcpy(d_in_block_sums, d_block_sums, sizeof(unsigned int) * grid_sz, hipMemcpyDeviceToDevice)"
	.size	.L.str.7, 98

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"hipFree(d_in_block_sums)"
	.size	.L.str.8, 25

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipFree(d_block_sums)"
	.size	.L.str.9, 22

	.type	_Z9prefixsumPjS_ij,@object      # @_Z9prefixsumPjS_ij
	.section	.rodata,"a",@progbits
	.globl	_Z9prefixsumPjS_ij
	.p2align	3, 0x0
_Z9prefixsumPjS_ij:
	.quad	_Z24__device_stub__prefixsumPjS_ij
	.size	_Z9prefixsumPjS_ij, 8

	.type	_Z23serialsum_accrossthreadPjij,@object # @_Z23serialsum_accrossthreadPjij
	.globl	_Z23serialsum_accrossthreadPjij
	.p2align	3, 0x0
_Z23serialsum_accrossthreadPjij:
	.quad	_Z38__device_stub__serialsum_accrossthreadPjij
	.size	_Z23serialsum_accrossthreadPjij, 8

	.type	_Z11mergethreadPjij,@object     # @_Z11mergethreadPjij
	.globl	_Z11mergethreadPjij
	.p2align	3, 0x0
_Z11mergethreadPjij:
	.quad	_Z26__device_stub__mergethreadPjij
	.size	_Z11mergethreadPjij, 8

	.type	_Z22serialsum_accrossblockPjiji,@object # @_Z22serialsum_accrossblockPjiji
	.globl	_Z22serialsum_accrossblockPjiji
	.p2align	3, 0x0
_Z22serialsum_accrossblockPjiji:
	.quad	_Z37__device_stub__serialsum_accrossblockPjiji
	.size	_Z22serialsum_accrossblockPjiji, 8

	.type	_Z10mergeblockPjij,@object      # @_Z10mergeblockPjij
	.globl	_Z10mergeblockPjij
	.p2align	3, 0x0
_Z10mergeblockPjij:
	.quad	_Z25__device_stub__mergeblockPjij
	.size	_Z10mergeblockPjij, 8

	.type	.L.str.10,@object               # @.str.10
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.10:
	.asciz	"hipMalloc((void**)&d_in,n*sizeof(data_t))"
	.size	.L.str.10, 42

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"hipMalloc((void**)&d_out_long,n*sizeof(data_t))"
	.size	.L.str.11, 48

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"hipMalloc((void**)&d_out,n*sizeof(unsigned int))"
	.size	.L.str.12, 49

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"hipMalloc((void**)&d_sum,n*sizeof(unsigned int))"
	.size	.L.str.13, 49

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"hipMalloc((void**)&d_index,n*sizeof(unsigned int))"
	.size	.L.str.14, 51

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"hipMemset(d_sum,0,n*sizeof(unsigned int))"
	.size	.L.str.15, 42

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"hipGetLastError()"
	.size	.L.str.16, 18

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"time: "
	.size	.L.str.17, 7

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"hipMemcpy(&total_zeros, d_sum+n-1, sizeof(unsigned int), hipMemcpyDeviceToHost)"
	.size	.L.str.18, 80

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"hipMemcpy(&mask_last, d_out+n-1, sizeof(unsigned int), hipMemcpyDeviceToHost)"
	.size	.L.str.19, 78

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"total: "
	.size	.L.str.20, 8

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"hipFree(d_in)"
	.size	.L.str.21, 14

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"hipFree(d_out_long)"
	.size	.L.str.22, 20

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"hipFree(d_out)"
	.size	.L.str.23, 15

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"hipFree(d_sum)"
	.size	.L.str.24, 15

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"hipFree(d_index)"
	.size	.L.str.25, 17

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	"CUDA error: "
	.size	.L.str.26, 13

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	": "
	.size	.L.str.27, 3

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"hipMemcpy(target, source, num * sizeof(T), direction)"
	.size	.L.str.28, 54

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7getMaskPyPjijyj"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8getIndexPjS_S_ijj"
	.size	.L__unnamed_2, 21

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7scatterPyPjS_ij"
	.size	.L__unnamed_3, 19

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z18gpu_add_block_sumsPjPKjS_m"
	.size	.L__unnamed_4, 31

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z11gpu_prescanPjPKjS_jjj"
	.size	.L__unnamed_5, 26

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z9prefixsumPjS_ij"
	.size	.L__unnamed_6, 19

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z23serialsum_accrossthreadPjij"
	.size	.L__unnamed_7, 32

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z11mergethreadPjij"
	.size	.L__unnamed_8, 20

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z22serialsum_accrossblockPjiji"
	.size	.L__unnamed_9, 32

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z10mergeblockPjij"
	.size	.L__unnamed_10, 19

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"const_sum"
	.size	.L__unnamed_11, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__getMaskPyPjijyj
	.addrsig_sym _Z23__device_stub__getIndexPjS_S_ijj
	.addrsig_sym _Z22__device_stub__scatterPyPjS_ij
	.addrsig_sym _Z33__device_stub__gpu_add_block_sumsPjPKjS_m
	.addrsig_sym _Z26__device_stub__gpu_prescanPjPKjS_jjj
	.addrsig_sym _Z24__device_stub__prefixsumPjS_ij
	.addrsig_sym _Z38__device_stub__serialsum_accrossthreadPjij
	.addrsig_sym _Z26__device_stub__mergethreadPjij
	.addrsig_sym _Z37__device_stub__serialsum_accrossblockPjiji
	.addrsig_sym _Z25__device_stub__mergeblockPjij
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym const_sum
	.addrsig_sym _Z7getMaskPyPjijyj
	.addrsig_sym _Z8getIndexPjS_S_ijj
	.addrsig_sym _Z7scatterPyPjS_ij
	.addrsig_sym _Z18gpu_add_block_sumsPjPKjS_m
	.addrsig_sym _Z11gpu_prescanPjPKjS_jjj
	.addrsig_sym _Z9prefixsumPjS_ij
	.addrsig_sym _Z23serialsum_accrossthreadPjij
	.addrsig_sym _Z11mergethreadPjij
	.addrsig_sym _Z22serialsum_accrossblockPjiji
	.addrsig_sym _Z10mergeblockPjij
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7getMaskPyPjijyj      ; -- Begin function _Z7getMaskPyPjijyj
	.globl	_Z7getMaskPyPjijyj
	.p2align	8
	.type	_Z7getMaskPyPjijyj,@function
_Z7getMaskPyPjijyj:                     ; @_Z7getMaskPyPjijyj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_mul_lo_u32 v0, v1, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s5, v0
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_add_nc_u32_e32 v2, s4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, v2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x20
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_load_b64 s[2:3], s[0:1], 0x18
	v_min_u32_e32 v5, s5, v2
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[0:1]
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s4, 0
	v_add_co_u32 v1, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v4, vcc_lo
	s_cselect_b32 s0, -1, 0
	v_add_co_u32 v3, vcc_lo, s10, v7
	v_cndmask_b32_e64 v6, 0, 1, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v8, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[1:2], off
	v_add_nc_u32_e32 v0, 1, v0
	v_add_co_u32 v1, vcc_lo, v1, 8
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ge_u32_e32 vcc_lo, v0, v5
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	v_lshrrev_b64 v[7:8], s2, v[7:8]
	v_and_b32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v7, v7, v6
	global_store_b32 v[3:4], v7, off
	v_add_co_u32 v3, s0, v3, 4
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_3
.LBB0_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7getMaskPyPjijyj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7getMaskPyPjijyj, .Lfunc_end0-_Z7getMaskPyPjijyj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8getIndexPjS_S_ijj    ; -- Begin function _Z8getIndexPjS_S_ijj
	.globl	_Z8getIndexPjS_S_ijj
	.p2align	8
	.type	_Z8getIndexPjS_S_ijj,@function
_Z8getIndexPjS_S_ijj:                   ; @_Z8getIndexPjS_S_ijj
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
	s_mov_b32 s7, exec_lo
	v_mul_lo_u32 v32, v1, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s5, v32
	s_cbranch_execz .LBB1_230
; %bb.1:
	v_add_nc_u32_e32 v0, s4, v32
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, v0, v32
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_230
; %bb.2:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x10
	v_min_u32_e32 v34, s5, v0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 2
	v_mbcnt_lo_u32_b32 v35, -1, 0
	v_mov_b32_e32 v6, 1
	v_mov_b32_e32 v0, 33
	s_mov_b32 s12, 0
	s_mov_b32 s7, 0
	s_mov_b32 s4, s12
.LBB1_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
                                        ;     Child Loop BB1_15 Depth 2
                                        ;     Child Loop BB1_21 Depth 2
                                        ;     Child Loop BB1_30 Depth 2
                                        ;     Child Loop BB1_33 Depth 2
                                        ;       Child Loop BB1_36 Depth 3
                                        ;       Child Loop BB1_44 Depth 3
                                        ;       Child Loop BB1_52 Depth 3
                                        ;       Child Loop BB1_60 Depth 3
                                        ;       Child Loop BB1_68 Depth 3
                                        ;       Child Loop BB1_76 Depth 3
                                        ;       Child Loop BB1_84 Depth 3
                                        ;       Child Loop BB1_92 Depth 3
                                        ;       Child Loop BB1_100 Depth 3
                                        ;       Child Loop BB1_106 Depth 3
                                        ;       Child Loop BB1_115 Depth 3
                                        ;     Child Loop BB1_123 Depth 2
                                        ;     Child Loop BB1_131 Depth 2
                                        ;     Child Loop BB1_137 Depth 2
                                        ;     Child Loop BB1_146 Depth 2
                                        ;     Child Loop BB1_151 Depth 2
                                        ;     Child Loop BB1_159 Depth 2
                                        ;     Child Loop BB1_165 Depth 2
                                        ;     Child Loop BB1_174 Depth 2
                                        ;     Child Loop BB1_178 Depth 2
                                        ;     Child Loop BB1_186 Depth 2
                                        ;     Child Loop BB1_192 Depth 2
                                        ;     Child Loop BB1_201 Depth 2
                                        ;     Child Loop BB1_205 Depth 2
                                        ;     Child Loop BB1_213 Depth 2
                                        ;     Child Loop BB1_219 Depth 2
                                        ;     Child Loop BB1_228 Depth 2
	v_dual_mov_b32 v33, v2 :: v_dual_add_nc_u32 v12, s6, v32
	s_mov_b32 s28, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[32:33]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s10, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v10, vcc_lo
	v_add_co_u32 v7, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v10, vcc_lo
	global_load_b32 v1, v[3:4], off
	global_load_b32 v11, v[7:8], off
	s_waitcnt vmcnt(1)
	v_sub_nc_u32_e32 v12, v12, v1
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	global_store_b32 v[9:10], v1, off
	v_cmpx_le_u32_e64 s5, v1
	s_cbranch_execz .LBB1_229
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v33, v[3:4], off
	global_load_b32 v9, v[7:8], off
	s_load_b64 s[18:19], s[2:3], 0x50
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_10
; %bb.5:                                ;   in Loop: Header=BB1_3 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[12:13], v2, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19]
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB1_9
; %bb.6:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s14, 0
.LBB1_7:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b64 v[10:11], v2, s[18:19]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[10:11]
	v_and_b32_e32 v10, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v10, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_7
; %bb.8:                                ; %Flow468
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_9:                                ; %Flow470
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_10:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b128 v[10:13], v2, s[18:19]
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[20:21], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s22, s14, 24
	s_mul_i32 s23, s14, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, v2
	s_add_i32 s13, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v10, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v11, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB1_12:                               ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[14:15], s[14:15], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v12, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v13, vcc_lo
	s_mov_b32 s13, s12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, v3
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v12, s12
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v14, s14
	v_mov_b32_e32 v13, s13
	v_mov_b32_e32 v15, s15
	s_clause 0x3
	global_store_b128 v[7:8], v[0:3], off
	global_store_b128 v[7:8], v[12:15], off offset:16
	global_store_b128 v[7:8], v[12:15], off offset:32
	global_store_b128 v[7:8], v[12:15], off offset:48
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_20
; %bb.13:                               ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v2, s[18:19] offset:32 glc
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	v_mov_b32_e32 v15, s21
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v14, s20 :: v_dual_and_b32 v1, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v1, vcc_lo
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[14:17], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB1_16
; %bb.14:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s15, 0
.LBB1_15:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, s21
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_15
.LBB1_16:                               ; %Flow466
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b64 v[3:4], v2, s[18:19] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s14, exec_lo
	v_mbcnt_lo_u32_b32 v1, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_3 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_18:                               ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s14, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_20:                               ; %Flow467
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s22, s22, s1
	v_add_co_u32 v1, vcc_lo, v10, s23
	v_add_co_ci_u32_e32 v4, vcc_lo, s22, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_21:                               ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_23
; %bb.22:                               ;   in Loop: Header=BB1_21 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_23:                               ;   in Loop: Header=BB1_21 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_25
; %bb.24:                               ;   in Loop: Header=BB1_21 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_26
.LBB1_25:                               ;   in Loop: Header=BB1_21 Depth=2
	s_mov_b32 s1, -1
.LBB1_26:                               ; %Flow461
                                        ;   in Loop: Header=BB1_21 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_21
; %bb.27:                               ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[10:11], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_31
; %bb.28:                               ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19] offset:24 glc
	global_load_b64 v[14:15], v2, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, s20
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v16 :: v_dual_cndmask_b32 v12, v12, v1
	v_and_b32_e32 v1, v13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v12, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v14, v3
	v_mov_b32_e32 v14, v7
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_31
; %bb.29:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, 0
.LBB1_30:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[14:15]
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v14, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_30
.LBB1_31:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, .str@rel32@lo+4
	s_addc_u32 s15, s15, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[14:15], 0
	s_cbranch_scc0 .LBB1_118
; %bb.32:                               ;   in Loop: Header=BB1_3 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v13, v11 :: v_dual_and_b32 v36, 2, v10
	v_and_b32_e32 v12, -3, v10
	s_mov_b64 s[20:21], 49
.LBB1_33:                               ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_36 Depth 3
                                        ;       Child Loop BB1_44 Depth 3
                                        ;       Child Loop BB1_52 Depth 3
                                        ;       Child Loop BB1_60 Depth 3
                                        ;       Child Loop BB1_68 Depth 3
                                        ;       Child Loop BB1_76 Depth 3
                                        ;       Child Loop BB1_84 Depth 3
                                        ;       Child Loop BB1_92 Depth 3
                                        ;       Child Loop BB1_100 Depth 3
                                        ;       Child Loop BB1_106 Depth 3
                                        ;       Child Loop BB1_115 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[20:21], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s22, s20, 56
	s_cselect_b32 s23, s21, 0
	s_cmp_gt_u32 s22, 7
	s_cbranch_scc1 .LBB1_38
; %bb.34:                               ;   in Loop: Header=BB1_33 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s22, 0
	s_cbranch_scc1 .LBB1_37
; %bb.35:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_lshl_b64 s[0:1], s[22:23], 3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], s[14:15]
.LBB1_36:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[26:27]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_add_u32 s26, s26, 1
	s_addc_u32 s27, s27, 0
	s_cmp_lg_u32 s0, s24
	v_or_b32_e32 v14, v3, v14
	v_or_b32_e32 v15, v4, v15
	s_cbranch_scc1 .LBB1_36
.LBB1_37:                               ; %Flow437
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s13, 0
	s_branch .LBB1_39
.LBB1_38:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr13
.LBB1_39:                               ; %Flow439
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[14:15]
	s_cbranch_vccnz .LBB1_41
; %bb.40:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[14:15], v2, s[14:15]
	s_add_i32 s13, s22, -8
	s_add_u32 s0, s14, 8
	s_addc_u32 s1, s15, 0
.LBB1_41:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_cmp_gt_u32 s13, 7
	s_cbranch_scc1 .LBB1_46
; %bb.42:                               ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s13, 0
	s_cbranch_scc1 .LBB1_45
; %bb.43:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB1_44:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s0, s26
	s_addc_u32 s31, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v1, v2, s[30:31]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s13, s26
	v_or_b32_e32 v16, v3, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v4, v17
	s_cbranch_scc1 .LBB1_44
.LBB1_45:                               ; %Flow432
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, 0
	s_mov_b32 s29, 0
	s_branch .LBB1_47
.LBB1_46:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr29
.LBB1_47:                               ; %Flow434
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB1_49
; %bb.48:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[16:17], v2, s[0:1]
	s_add_i32 s29, s13, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_49:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_cmp_gt_u32 s29, 7
	s_cbranch_scc1 .LBB1_54
; %bb.50:                               ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s29, 0
	s_cbranch_scc1 .LBB1_53
; %bb.51:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB1_52:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s0, s26
	s_addc_u32 s31, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v1, v2, s[30:31]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s29, s26
	v_or_b32_e32 v18, v3, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v4, v19
	s_cbranch_scc1 .LBB1_52
.LBB1_53:                               ; %Flow427
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, 0
	s_mov_b32 s13, 0
	s_branch .LBB1_55
.LBB1_54:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, -1
                                        ; implicit-def: $sgpr13
.LBB1_55:                               ; %Flow429
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB1_57
; %bb.56:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[18:19], v2, s[0:1]
	s_add_i32 s13, s29, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_57:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_cmp_gt_u32 s13, 7
	s_cbranch_scc1 .LBB1_62
; %bb.58:                               ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s13, 0
	s_cbranch_scc1 .LBB1_61
; %bb.59:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB1_60:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s0, s26
	s_addc_u32 s31, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v1, v2, s[30:31]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s13, s26
	v_or_b32_e32 v20, v3, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v4, v21
	s_cbranch_scc1 .LBB1_60
.LBB1_61:                               ; %Flow422
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, 0
	s_mov_b32 s29, 0
	s_branch .LBB1_63
.LBB1_62:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr29
.LBB1_63:                               ; %Flow424
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB1_65
; %bb.64:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[20:21], v2, s[0:1]
	s_add_i32 s29, s13, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_65:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_cmp_gt_u32 s29, 7
	s_cbranch_scc1 .LBB1_70
; %bb.66:                               ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s29, 0
	s_cbranch_scc1 .LBB1_69
; %bb.67:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB1_68:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s0, s26
	s_addc_u32 s31, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v1, v2, s[30:31]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s29, s26
	v_or_b32_e32 v22, v3, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v4, v23
	s_cbranch_scc1 .LBB1_68
.LBB1_69:                               ; %Flow417
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, 0
	s_mov_b32 s13, 0
	s_branch .LBB1_71
.LBB1_70:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, -1
                                        ; implicit-def: $sgpr13
.LBB1_71:                               ; %Flow419
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB1_73
; %bb.72:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[22:23], v2, s[0:1]
	s_add_i32 s13, s29, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_73:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_cmp_gt_u32 s13, 7
	s_cbranch_scc1 .LBB1_78
; %bb.74:                               ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s13, 0
	s_cbranch_scc1 .LBB1_77
; %bb.75:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB1_76:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s0, s26
	s_addc_u32 s31, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v1, v2, s[30:31]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s13, s26
	v_or_b32_e32 v24, v3, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v4, v25
	s_cbranch_scc1 .LBB1_76
.LBB1_77:                               ; %Flow412
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, 0
	s_mov_b32 s29, 0
	s_branch .LBB1_79
.LBB1_78:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr29
.LBB1_79:                               ; %Flow414
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB1_81
; %bb.80:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[24:25], v2, s[0:1]
	s_add_i32 s29, s13, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_81:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_cmp_gt_u32 s29, 7
	s_cbranch_scc1 .LBB1_86
; %bb.82:                               ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s29, 0
	s_cbranch_scc1 .LBB1_85
; %bb.83:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], s[0:1]
.LBB1_84:                               ; %.preheader.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[26:27]
	s_add_i32 s29, s29, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s24, v[1:2]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_add_u32 s26, s26, 1
	s_addc_u32 s27, s27, 0
	s_cmp_lg_u32 s29, 0
	v_or_b32_e32 v26, v3, v26
	v_or_b32_e32 v27, v4, v27
	s_cbranch_scc1 .LBB1_84
.LBB1_85:                               ; %Flow407
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s13, 0
	s_branch .LBB1_87
.LBB1_86:                               ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s13, -1
.LBB1_87:                               ; %Flow409
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_cbranch_vccnz .LBB1_89
; %bb.88:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[26:27], v2, s[0:1]
.LBB1_89:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_95
; %bb.90:                               ;   in Loop: Header=BB1_33 Depth=2
	global_load_b64 v[30:31], v2, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19]
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v31
	v_and_b32_e32 v3, v3, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v28, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v28, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[28:29], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[28:31], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[30:31]
	s_cbranch_execz .LBB1_94
; %bb.91:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s24, 0
.LBB1_92:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b64 v[28:29], v2, s[18:19]
	v_dual_mov_b32 v31, v4 :: v_dual_mov_b32 v30, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v30
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[28:29]
	v_and_b32_e32 v28, v8, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v28, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[28:29], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[28:31], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[30:31]
	s_or_b32 s24, vcc_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB1_92
; %bb.93:                               ; %Flow402
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
.LBB1_94:                               ; %Flow404
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_95:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b128 v[28:31], v2, s[18:19]
	v_readfirstlane_b32 s24, v3
	v_readfirstlane_b32 s25, v4
	s_mov_b32 s30, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s26, v7
	v_readfirstlane_b32 s27, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[26:27], s[24:25], s[26:27]
	s_mul_i32 s1, s27, 24
	s_mul_hi_u32 s13, s26, 24
	s_mul_i32 s29, s26, 24
	s_and_saveexec_b32 s31, s0
	s_cbranch_execz .LBB1_97
; %bb.96:                               ;   in Loop: Header=BB1_33 Depth=2
	v_dual_mov_b32 v3, s30 :: v_dual_mov_b32 v4, v2
	s_add_i32 s30, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v28, s29
	v_add_co_ci_u32_e32 v8, vcc_lo, s30, v29, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB1_97:                               ;   in Loop: Header=BB1_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	v_cmp_gt_u64_e64 vcc_lo, s[20:21], 56
	v_or_b32_e32 v3, 0, v13
	v_or_b32_e32 v4, v12, v36
	s_lshl_b64 s[26:27], s[26:27], 12
	s_lshl_b32 s30, s22, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s30, s30, 28
	v_cndmask_b32_e32 v13, v3, v13, vcc_lo
	v_cndmask_b32_e32 v7, v4, v12, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v30, s26
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v31, vcc_lo
	s_and_b32 s30, s30, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v12, 0xffffff1f, v7, s30
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[12:15], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[20:23], off offset:32
	global_store_b128 v[3:4], v[24:27], off offset:48
	s_and_saveexec_b32 s26, s0
	s_cbranch_execz .LBB1_105
; %bb.98:                               ;   in Loop: Header=BB1_33 Depth=2
	s_clause 0x1
	global_load_b64 v[16:17], v2, s[18:19] offset:32 glc
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	v_dual_mov_b32 v14, s24 :: v_dual_mov_b32 v15, s25
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s30, v7
	v_readfirstlane_b32 s31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[30:31], s[30:31], s[24:25]
	s_mul_i32 s27, s31, 24
	s_mul_hi_u32 s31, s30, 24
	s_mul_i32 s30, s30, 24
	s_add_i32 s31, s31, s27
	v_add_co_u32 v7, vcc_lo, v28, s30
	v_add_co_ci_u32_e32 v8, vcc_lo, s31, v29, vcc_lo
	s_mov_b32 s27, exec_lo
	global_store_b64 v[7:8], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[14:17], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB1_101
; %bb.99:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s30, 0
.LBB1_100:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
	s_sleep 1
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s30, vcc_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB1_100
.LBB1_101:                              ; %Flow400
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	global_load_b64 v[7:8], v2, s[18:19] offset:16
	s_mov_b32 s30, exec_lo
	s_mov_b32 s27, exec_lo
	v_mbcnt_lo_u32_b32 v1, s30, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_103
; %bb.102:                              ;   in Loop: Header=BB1_33 Depth=2
	s_bcnt1_i32_b32 s30, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s30
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_103:                              ;   in Loop: Header=BB1_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_33 Depth=2
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s27, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s27, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_105:                              ; %Flow401
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_add_i32 s13, s13, s1
	v_add_co_u32 v1, vcc_lo, v28, s29
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_106:                              ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_108
; %bb.107:                              ;   in Loop: Header=BB1_106 Depth=3
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_108:                              ;   in Loop: Header=BB1_106 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_110
; %bb.109:                              ;   in Loop: Header=BB1_106 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_111
.LBB1_110:                              ;   in Loop: Header=BB1_106 Depth=3
	s_mov_b32 s1, -1
.LBB1_111:                              ; %Flow395
                                        ;   in Loop: Header=BB1_106 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_106
; %bb.112:                              ;   in Loop: Header=BB1_33 Depth=2
	global_load_b128 v[12:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_116
; %bb.113:                              ;   in Loop: Header=BB1_33 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19] offset:24 glc
	global_load_b64 v[16:17], v2, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v1, s24
	v_add_co_ci_u32_e32 v15, vcc_lo, s25, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v18 :: v_dual_cndmask_b32 v14, v14, v1
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v14, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v16, v3
	v_mov_b32_e32 v16, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v17, v1, vcc_lo
	v_mov_b32_e32 v17, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_116
; %bb.114:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_mov_b32 s0, 0
.LBB1_115:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[14:17], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[16:17]
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_115
.LBB1_116:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s20, s20, s22
	s_subb_u32 s21, s21, s23
	s_add_u32 s14, s14, s22
	s_addc_u32 s15, s15, s23
	s_cmp_lg_u64 s[20:21], 0
	s_cbranch_scc1 .LBB1_33
; %bb.117:                              ; %Flow440
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB1_119
.LBB1_118:                              ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr12_vgpr13
.LBB1_119:                              ; %Flow455
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_148
; %bb.120:                              ;   in Loop: Header=BB1_3 Depth=1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_126
; %bb.121:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[14:15], v2, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19]
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v15
	v_and_b32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v12, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v12, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB1_125
; %bb.122:                              ; %.preheader3.i.i.i41.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s14, 0
.LBB1_123:                              ; %.preheader3.i.i.i41
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b64 v[12:13], v2, s[18:19]
	v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v14, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[12:13]
	v_and_b32_e32 v12, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v12, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[14:15]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_123
; %bb.124:                              ; %Flow452
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_125:                              ; %Flow454
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_126:                              ; %.loopexit4.i.i.i36
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b128 v[14:17], v2, s[18:19]
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[20:21], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s22, s14, 24
	s_mul_i32 s23, s14, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB1_128
; %bb.127:                              ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, v2
	s_add_i32 s13, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v14, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v15, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB1_128:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[14:15], s[14:15], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, s14
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v17, vcc_lo
	s_mov_b32 s15, s12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v19, s15
	v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v18, s14
	v_dual_mov_b32 v17, s13 :: v_dual_mov_b32 v16, s12
	s_clause 0x3
	global_store_b128 v[3:4], v[10:13], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[16:19], off offset:32
	global_store_b128 v[3:4], v[16:19], off offset:48
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_136
; %bb.129:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v2, s[18:19] offset:32 glc
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	v_dual_mov_b32 v16, s20 :: v_dual_mov_b32 v17, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[20:21]
	s_mul_i32 s15, s15, 24
	s_mul_hi_u32 s24, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s24, s24, s15
	v_add_co_u32 v7, vcc_lo, v14, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s24, v15, vcc_lo
	s_mov_b32 s14, exec_lo
	global_store_b64 v[7:8], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[16:19], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[18:19]
	s_cbranch_execz .LBB1_132
; %bb.130:                              ; %.preheader1.i.i.i39.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s15, 0
.LBB1_131:                              ; %.preheader1.i.i.i39
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s21
	s_sleep 1
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_131
.LBB1_132:                              ; %Flow450
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b64 v[7:8], v2, s[18:19] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s14, exec_lo
	v_mbcnt_lo_u32_b32 v1, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_134
; %bb.133:                              ;   in Loop: Header=BB1_3 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_134:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB1_136
; %bb.135:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[1:2], off
	s_and_b32 m0, s14, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_136:                              ; %Flow451
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s22, s22, s1
	v_add_co_u32 v1, vcc_lo, v14, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s22, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_137:                              ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_139
; %bb.138:                              ;   in Loop: Header=BB1_137 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_139:                              ;   in Loop: Header=BB1_137 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_141
; %bb.140:                              ;   in Loop: Header=BB1_137 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_142
.LBB1_141:                              ;   in Loop: Header=BB1_137 Depth=2
	s_mov_b32 s1, -1
.LBB1_142:                              ; %Flow445
                                        ;   in Loop: Header=BB1_137 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_137
; %bb.143:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b128 v[12:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_147
; %bb.144:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19] offset:24 glc
	global_load_b64 v[10:11], v2, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v17, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v1, s20
	v_add_co_ci_u32_e32 v15, vcc_lo, s21, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v16 :: v_dual_cndmask_b32 v14, v14, v1
	v_mov_b32_e32 v16, v7
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v14, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_147
; %bb.145:                              ; %.preheader.i.i.i38.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, 0
.LBB1_146:                              ; %.preheader.i.i.i38
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[14:17], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[16:17]
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_146
.LBB1_147:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_148:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_154
; %bb.149:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[16:17], v2, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19]
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v17
	v_and_b32_e32 v3, v3, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[16:17]
	s_cbranch_execz .LBB1_153
; %bb.150:                              ; %.preheader3.i.i.i48.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s14, 0
.LBB1_151:                              ; %.preheader3.i.i.i48
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b64 v[10:11], v2, s[18:19]
	v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v16, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v16
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[10:11]
	v_and_b32_e32 v10, v8, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v10, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[16:17]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_151
; %bb.152:                              ; %Flow388
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_153:                              ; %Flow390
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_154:                              ; %.loopexit4.i.i.i42
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b128 v[16:19], v2, s[18:19]
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[20:21], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s22, s14, 24
	s_mul_i32 s23, s14, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB1_156
; %bb.155:                              ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, v2
	s_add_i32 s13, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v16, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v17, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB1_156:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[14:15], s[14:15], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v18, s14
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v19, vcc_lo
	s_mov_b32 s15, s12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v12, 0xffffff1f, v12, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v14, v33 :: v_dual_mov_b32 v15, v2
	v_dual_mov_b32 v21, s15 :: v_dual_mov_b32 v20, s14
	v_dual_mov_b32 v19, s13 :: v_dual_mov_b32 v18, s12
	s_clause 0x3
	global_store_b128 v[3:4], v[12:15], off
	global_store_b128 v[3:4], v[18:21], off offset:16
	global_store_b128 v[3:4], v[18:21], off offset:32
	global_store_b128 v[3:4], v[18:21], off offset:48
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_164
; %bb.157:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x1
	global_load_b64 v[14:15], v2, s[18:19] offset:32 glc
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[20:21]
	s_mul_i32 s15, s15, 24
	s_mul_hi_u32 s24, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s24, s24, s15
	v_add_co_u32 v7, vcc_lo, v16, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s24, v17, vcc_lo
	s_mov_b32 s14, exec_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[14:15]
	s_cbranch_execz .LBB1_160
; %bb.158:                              ; %.preheader1.i.i.i46.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s15, 0
.LBB1_159:                              ; %.preheader1.i.i.i46
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s21
	s_sleep 1
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_159
.LBB1_160:                              ; %Flow386
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b64 v[7:8], v2, s[18:19] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s14, exec_lo
	v_mbcnt_lo_u32_b32 v1, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_162
; %bb.161:                              ;   in Loop: Header=BB1_3 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_162:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB1_164
; %bb.163:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[1:2], off
	s_and_b32 m0, s14, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_164:                              ; %Flow387
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s22, s22, s1
	v_add_co_u32 v1, vcc_lo, v16, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s22, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_165:                              ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_167
; %bb.166:                              ;   in Loop: Header=BB1_165 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_167:                              ;   in Loop: Header=BB1_165 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_169
; %bb.168:                              ;   in Loop: Header=BB1_165 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_170
.LBB1_169:                              ;   in Loop: Header=BB1_165 Depth=2
	s_mov_b32 s1, -1
.LBB1_170:                              ; %Flow381
                                        ;   in Loop: Header=BB1_165 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_165
; %bb.171:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[10:11], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_175
; %bb.172:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19] offset:24 glc
	global_load_b64 v[14:15], v2, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, s20
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v16 :: v_dual_cndmask_b32 v12, v12, v1
	v_and_b32_e32 v1, v13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v12, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v14, v3
	v_mov_b32_e32 v14, v7
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_175
; %bb.173:                              ; %.preheader.i.i.i45.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, 0
.LBB1_174:                              ; %.preheader.i.i.i45
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[14:15]
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v14, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_174
.LBB1_175:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_181
; %bb.176:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[14:15], v2, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[7:8], v2, s[18:19]
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v15
	v_and_b32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v12, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v12, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB1_180
; %bb.177:                              ; %.preheader3.i.i.i55.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s14, 0
.LBB1_178:                              ; %.preheader3.i.i.i55
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b64 v[12:13], v2, s[18:19]
	v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v14, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[12:13]
	v_and_b32_e32 v12, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v12, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[14:15]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_178
; %bb.179:                              ; %Flow374
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_180:                              ; %Flow376
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_181:                              ; %.loopexit4.i.i.i49
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	global_load_b128 v[14:17], v2, s[18:19]
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[20:21], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s22, s14, 24
	s_mul_i32 s23, s14, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB1_183
; %bb.182:                              ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, v2
	s_add_i32 s13, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v14, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v15, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB1_183:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[14:15], s[14:15], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, s14
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v17, vcc_lo
	s_mov_b32 s15, s12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s4
	v_dual_mov_b32 v19, s15 :: v_dual_mov_b32 v18, s14
	v_dual_mov_b32 v17, s13 :: v_dual_mov_b32 v16, s12
	s_clause 0x3
	global_store_b128 v[3:4], v[10:13], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[16:19], off offset:32
	global_store_b128 v[3:4], v[16:19], off offset:48
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_191
; %bb.184:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v2, s[18:19] offset:32 glc
	global_load_b64 v[7:8], v2, s[18:19] offset:40
	v_dual_mov_b32 v16, s20 :: v_dual_mov_b32 v17, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[20:21]
	s_mul_i32 s15, s15, 24
	s_mul_hi_u32 s24, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s24, s24, s15
	v_add_co_u32 v7, vcc_lo, v14, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s24, v15, vcc_lo
	s_mov_b32 s14, exec_lo
	global_store_b64 v[7:8], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[16:19], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[18:19]
	s_cbranch_execz .LBB1_187
; %bb.185:                              ; %.preheader1.i.i.i53.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s15, 0
.LBB1_186:                              ; %.preheader1.i.i.i53
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s21
	s_sleep 1
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_186
.LBB1_187:                              ; %Flow372
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b64 v[7:8], v2, s[18:19] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s14, exec_lo
	v_mbcnt_lo_u32_b32 v1, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_189
; %bb.188:                              ;   in Loop: Header=BB1_3 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_189:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB1_191
; %bb.190:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[1:2], off
	s_and_b32 m0, s14, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_191:                              ; %Flow373
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s22, s22, s1
	v_add_co_u32 v1, vcc_lo, v14, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s22, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_192:                              ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_194
; %bb.193:                              ;   in Loop: Header=BB1_192 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_194:                              ;   in Loop: Header=BB1_192 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_196
; %bb.195:                              ;   in Loop: Header=BB1_192 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_197
.LBB1_196:                              ;   in Loop: Header=BB1_192 Depth=2
	s_mov_b32 s1, -1
.LBB1_197:                              ; %Flow367
                                        ;   in Loop: Header=BB1_192 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_192
; %bb.198:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[7:8], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_202
; %bb.199:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[14:15], v2, s[18:19] offset:24 glc
	global_load_b64 v[12:13], v2, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v1, s20
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v16 :: v_dual_cndmask_b32 v10, v10, v1
	v_and_b32_e32 v1, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v10, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v12, v3
	v_mov_b32_e32 v12, v14
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v13, v1, vcc_lo
	v_mov_b32_e32 v13, v15
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[10:13], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[14:15]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_202
; %bb.200:                              ; %.preheader.i.i.i52.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, 0
.LBB1_201:                              ; %.preheader.i.i.i52
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[10:13], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[12:13]
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_201
.LBB1_202:                              ; %__ockl_printf_append_args.exit56
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_208
; %bb.203:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b64 v[12:13], v2, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[10:11], v2, s[18:19]
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB1_207
; %bb.204:                              ; %.preheader3.i.i.i63.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s14, 0
.LBB1_205:                              ; %.preheader3.i.i.i63
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v2, s[18:19] offset:40
	global_load_b64 v[14:15], v2, s[18:19]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v10
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_205
; %bb.206:                              ; %Flow360
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_207:                              ; %Flow362
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_208:                              ; %.loopexit4.i.i.i57
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[18:19] offset:40
	global_load_b128 v[11:14], v2, s[18:19]
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v15
	v_readfirstlane_b32 s15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[20:21], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s22, s14, 24
	s_mul_i32 s23, s14, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB1_210
; %bb.209:                              ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, v2
	s_add_i32 s13, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v11, s23
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v12, vcc_lo
	global_store_b128 v[15:16], v[3:6], off offset:8
.LBB1_210:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[14:15], s[14:15], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s14
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v14, vcc_lo
	s_mov_b32 s15, s12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v7, 0xffffff1d, v7, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	v_mov_b32_e32 v10, v2
	v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v13, s12
	v_dual_mov_b32 v15, s14 :: v_dual_mov_b32 v14, s13
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_218
; %bb.211:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[18:19] offset:32 glc
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	v_dual_mov_b32 v13, s20 :: v_dual_mov_b32 v14, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[20:21]
	s_mul_i32 s15, s15, 24
	s_mul_hi_u32 s24, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s24, s24, s15
	v_add_co_u32 v3, vcc_lo, v11, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s24, v12, vcc_lo
	s_mov_b32 s14, exec_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[13:16], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB1_214
; %bb.212:                              ; %.preheader1.i.i.i61.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s15, 0
.LBB1_213:                              ; %.preheader1.i.i.i61
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v8, s21
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_213
.LBB1_214:                              ; %Flow358
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b64 v[3:4], v2, s[18:19] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s14, exec_lo
	v_mbcnt_lo_u32_b32 v1, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_216
; %bb.215:                              ;   in Loop: Header=BB1_3 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_216:                              ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB1_218
; %bb.217:                              ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s14, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_218:                              ; %Flow359
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s22, s22, s1
	v_add_co_u32 v1, vcc_lo, v11, s23
	v_add_co_ci_u32_e32 v4, vcc_lo, s22, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_219:                              ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_221
; %bb.220:                              ;   in Loop: Header=BB1_219 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_221:                              ;   in Loop: Header=BB1_219 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_223
; %bb.222:                              ;   in Loop: Header=BB1_219 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_224
.LBB1_223:                              ;   in Loop: Header=BB1_219 Depth=2
	s_mov_b32 s1, -1
.LBB1_224:                              ; %Flow353
                                        ;   in Loop: Header=BB1_219 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_219
; %bb.225:                              ;   in Loop: Header=BB1_3 Depth=1
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_229
; %bb.226:                              ;   in Loop: Header=BB1_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[18:19] offset:40
	global_load_b64 v[11:12], v2, s[18:19] offset:24 glc
	global_load_b64 v[9:10], v2, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s20
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_229
; %bb.227:                              ; %.preheader.i.i.i60.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_mov_b32 s0, 0
.LBB1_228:                              ; %.preheader.i.i.i60
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_228
.LBB1_229:                              ; %Flow471
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s28
	v_add_nc_u32_e32 v32, 1, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v32, v34
	s_or_b32 s7, vcc_lo, s7
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_3
.LBB1_230:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8getIndexPjS_S_ijj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8getIndexPjS_S_ijj, .Lfunc_end1-_Z8getIndexPjS_S_ijj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9540
; NumSgprs: 34
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7scatterPyPjS_ij      ; -- Begin function _Z7scatterPyPjS_ij
	.globl	_Z7scatterPyPjS_ij
	.p2align	8
	.type	_Z7scatterPyPjS_ij,@function
_Z7scatterPyPjS_ij:                     ; @_Z7scatterPyPjS_ij
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_mul_lo_u32 v0, v1, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s5, v0
	s_cbranch_execz .LBB2_4
; %bb.1:
	v_add_nc_u32_e32 v3, s4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, v3, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.2:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_min_u32_e32 v7, s5, v3
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v9, vcc_lo
.LBB2_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v1, v[5:6], off
	global_load_b64 v[8:9], v[3:4], off
	v_add_nc_u32_e32 v0, 1, v0
	v_add_co_u32 v3, vcc_lo, v3, 8
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e64 s0, v0, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_or_b32 s4, s0, s4
	s_waitcnt vmcnt(1)
	v_lshlrev_b64 v[10:11], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s2, v10
	v_add_co_ci_u32_e64 v11, s1, s3, v11, s1
	s_waitcnt vmcnt(0)
	global_store_b64 v[10:11], v[8:9], off
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_3
.LBB2_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7scatterPyPjS_ij
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7scatterPyPjS_ij, .Lfunc_end2-_Z7scatterPyPjS_ij
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18gpu_add_block_sumsPjPKjS_m ; -- Begin function _Z18gpu_add_block_sumsPjPKjS_m
	.globl	_Z18gpu_add_block_sumsPjPKjS_m
	.p2align	8
	.type	_Z18gpu_add_block_sumsPjPKjS_m,@function
_Z18gpu_add_block_sumsPjPKjS_m:         ; @_Z18gpu_add_block_sumsPjPKjS_m
; %bb.0:
	s_clause 0x1
	s_load_b32 s9, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s9, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s15, s10
	v_lshl_add_u32 v0, s9, 1, v0
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[6:7], v[0:1]
	s_cbranch_execz .LBB3_3
; %bb.1:
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_mov_b32 s8, s15
	s_mov_b32 s9, 0
	v_add_nc_u32_e32 v0, s10, v0
	s_lshl_b64 s[8:9], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s4, s4, s8
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_addc_u32 s5, s5, s9
	v_add_co_u32 v2, vcc_lo, s0, v2
	global_load_b32 v4, v[4:5], off
	s_load_b32 s4, s[4:5], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[0:1]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, s4, v4
	global_store_b32 v[2:3], v4, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_3
; %bb.2:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, s4, v2
	global_store_b32 v[0:1], v2, off
.LBB3_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18gpu_add_block_sumsPjPKjS_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z18gpu_add_block_sumsPjPKjS_m, .Lfunc_end3-_Z18gpu_add_block_sumsPjPKjS_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11gpu_prescanPjPKjS_jjj ; -- Begin function _Z11gpu_prescanPjPKjS_jjj
	.globl	_Z11gpu_prescanPjPKjS_jjj
	.p2align	8
	.type	_Z11gpu_prescanPjPKjS_jjj,@function
_Z11gpu_prescanPjPKjS_jjj:              ; @_Z11gpu_prescanPjPKjS_jjj
; %bb.0:
	s_clause 0x4
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s11, s[0:1], 0x20
	s_load_b32 s10, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_mov_b32 s2, s15
	v_lshl_add_u32 v7, v0, 2, 0
	v_lshrrev_b32_e32 v8, 3, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s3, 0xffff
	v_mad_u64_u32 v[1:2], null, s2, s11, v[0:1]
	v_lshl_add_u32 v5, s0, 2, v7
	s_lshr_b32 s1, s3, 3
	v_mov_b32_e32 v4, 0
	s_and_b32 s1, s1, 0x1ffc
	v_add_nc_u32_e32 v6, s0, v0
	v_add_nc_u32_e32 v2, s1, v5
	v_add_nc_u32_e32 v3, s0, v1
	v_cmp_gt_u32_e32 vcc_lo, s10, v1
	ds_store_b32 v7, v4
	ds_store_b32 v5, v4
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB4_3
; %bb.1:
	v_mov_b32_e32 v2, v4
	v_and_b32_e32 v4, 0x7c, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_add_nc_u32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s0, s6, v9
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	v_cmp_gt_u32_e64 s0, s10, v3
	global_load_b32 v2, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_3
; %bb.2:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_lshrrev_b32_e32 v4, 3, v6
	v_and_b32_e32 v4, 0x3ffc, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s0, s6, v9
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v4, v5, v4
	global_load_b32 v2, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
.LBB4_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_lshl_or_b32 v2, v0, 1, 1
	s_cmp_lt_u32 s11, 2
	s_mov_b32 s1, 1
	s_cbranch_scc1 .LBB4_9
; %bb.4:                                ; %.lr.ph
	s_mov_b32 s3, s11
.LBB4_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s6, s3, 1
	s_mov_b32 s7, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e64 s6, v0
	s_cbranch_execz .LBB4_7
; %bb.6:                                ;   in Loop: Header=BB4_5 Depth=1
	v_mad_u64_u32 v[9:10], null, s1, v2, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s1, v9
	v_ashrrev_i32_e32 v10, 5, v9
	v_ashrrev_i32_e32 v11, 5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v10, v9
	v_add_nc_u32_e32 v4, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v9, v9, 2, 0
	v_lshl_add_u32 v4, v4, 2, 0
	ds_load_b32 v9, v9
	ds_load_b32 v10, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v9, v10, v9
	ds_store_b32 v4, v9
.LBB4_7:                                ;   in Loop: Header=BB4_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_lshl_b32 s1, s1, 1
	s_cmp_lt_u32 s3, 4
	s_cbranch_scc1 .LBB4_9
; %bb.8:                                ;   in Loop: Header=BB4_5 Depth=1
	s_mov_b32 s3, s6
	s_branch .LBB4_5
.LBB4_9:                                ; %Flow105
	s_mov_b32 s3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_11
; %bb.10:
	s_lshl_b64 s[2:3], s[2:3], 2
	v_mov_b32_e32 v10, 0
	s_add_u32 s2, s8, s2
	s_addc_u32 s3, s9, s3
	s_add_i32 s0, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s7, s0, 5
	s_add_i32 s7, s7, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s7, 2
	s_add_i32 s0, s0, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s0
	ds_load_b32 v9, v4
	ds_store_b32 v4, v10
	s_waitcnt lgkmcnt(1)
	global_store_b32 v10, v9, s[2:3]
.LBB4_11:
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_lt_u32 s11, 2
	s_cbranch_scc1 .LBB4_16
; %bb.12:                               ; %.lr.ph88
	s_mov_b32 s2, 1
.LBB4_13:                               ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s1, s1, 1
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB4_15
; %bb.14:                               ;   in Loop: Header=BB4_13 Depth=1
	v_mad_u64_u32 v[9:10], null, s1, v2, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s1, v9
	v_ashrrev_i32_e32 v10, 5, v9
	v_ashrrev_i32_e32 v11, 5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v10, v9
	v_add_nc_u32_e32 v4, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v9, v9, 2, 0
	v_lshl_add_u32 v4, v4, 2, 0
	ds_load_b32 v10, v9
	ds_load_b32 v11, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v11, v10
	ds_store_b32 v9, v11
	ds_store_b32 v4, v10
.LBB4_15:                               ;   in Loop: Header=BB4_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_lshl_b32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s2, s11
	s_cbranch_scc0 .LBB4_13
.LBB4_16:                               ; %._crit_edge89
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB4_19
; %bb.17:
	v_and_b32_e32 v0, 0x7c, v8
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v7, v0
	ds_load_b32 v4, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s10, v3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v4, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_19
; %bb.18:
	v_lshrrev_b32_e32 v0, 3, v6
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0x3ffc, v0
	v_add_nc_u32_e32 v0, v5, v0
	ds_load_b32 v5, v0
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v5, off
.LBB4_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11gpu_prescanPjPKjS_jjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z11gpu_prescanPjPKjS_jjj, .Lfunc_end4-_Z11gpu_prescanPjPKjS_jjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 960
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9prefixsumPjS_ij      ; -- Begin function _Z9prefixsumPjS_ij
	.globl	_Z9prefixsumPjS_ij
	.p2align	8
	.type	_Z9prefixsumPjS_ij,@function
_Z9prefixsumPjS_ij:                     ; @_Z9prefixsumPjS_ij
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_mul_lo_u32 v1, v1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v1
	v_cmpx_ge_u32_e64 s3, v0
	s_cbranch_execz .LBB5_4
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v2, 2, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v6, v[5:6], off
	v_add_nc_u32_e32 v5, s2, v0
	v_min_u32_e32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, v2, v5
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v6, off offset:4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v6, v[3:4], off
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.LBB5_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v0, -1, v2
	global_load_b32 v9, v[3:4], off
	v_add_nc_u32_e32 v2, 1, v2
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_ge_u32_e32 vcc_lo, v2, v5
	global_load_b32 v0, v[7:8], off
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	v_add3_u32 v6, v0, v6, v9
	global_store_b32 v[3:4], v6, off
	v_add_co_u32 v3, s0, v3, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB5_3
.LBB5_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9prefixsumPjS_ij
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z9prefixsumPjS_ij, .Lfunc_end5-_Z9prefixsumPjS_ij
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 372
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23serialsum_accrossthreadPjij ; -- Begin function _Z23serialsum_accrossthreadPjij
	.globl	_Z23serialsum_accrossthreadPjij
	.p2align	8
	.type	_Z23serialsum_accrossthreadPjij,@function
_Z23serialsum_accrossthreadPjij:        ; @_Z23serialsum_accrossthreadPjij
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mul_i32 s5, s4, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v0, s5, 1
	v_lshl_add_u32 v3, s2, 1, v0
	v_min_u32_e32 v4, s3, v2
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v3, v4
	s_cbranch_execz .LBB6_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_lo_u32 v2, v1, s4
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s2, v2, s[2:3]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, 0
.LBB6_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v1, s4, v0
	v_add_nc_u32_e32 v5, s4, v3
	s_add_i32 s4, s4, s2
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v1, v[7:8], off
	global_load_b32 v7, v[5:6], off
	v_add_nc_u32_e32 v8, s4, v3
	v_cmp_ge_u32_e32 vcc_lo, v8, v4
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v7, v1
	global_store_b32 v[5:6], v1, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB6_2
.LBB6_3:                                ; %Flow27
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23serialsum_accrossthreadPjij
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z23serialsum_accrossthreadPjij, .Lfunc_end6-_Z23serialsum_accrossthreadPjij
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 288
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11mergethreadPjij     ; -- Begin function _Z11mergethreadPjij
	.globl	_Z11mergethreadPjij
	.p2align	8
	.type	_Z11mergethreadPjij,@function
_Z11mergethreadPjij:                    ; @_Z11mergethreadPjij
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB7_4
; %bb.1:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_mul_lo_u32 v1, v1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s2, v1
	v_min_u32_e32 v3, s3, v0
	v_add_nc_u32_e32 v0, 1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, v0, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_mov_b32 s1, 0
.LBB7_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[1:2], off
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_u32_e32 vcc_lo, v0, v3
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v4
	global_store_b32 v[1:2], v5, off
	v_add_co_u32 v1, s0, v1, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB7_3
.LBB7_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11mergethreadPjij
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z11mergethreadPjij, .Lfunc_end7-_Z11mergethreadPjij
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22serialsum_accrossblockPjiji ; -- Begin function _Z22serialsum_accrossblockPjiji
	.globl	_Z22serialsum_accrossblockPjiji
	.p2align	8
	.type	_Z22serialsum_accrossblockPjiji,@function
_Z22serialsum_accrossblockPjiji:        ; @_Z22serialsum_accrossblockPjiji
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s6, s4, 1
	s_cmp_ge_u32 s6, s5
	s_cbranch_scc1 .LBB8_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, s3
.LBB8_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s6, s2
	s_add_i32 s2, s4, s2
	s_mov_b32 s9, s3
	s_lshl_b64 s[10:11], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s10, s0, s10
	s_addc_u32 s11, s1, s11
	s_lshl_b64 s[8:9], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s0, s8
	s_addc_u32 s9, s1, s9
	s_clause 0x1
	global_load_b32 v1, v0, s[10:11]
	global_load_b32 v2, v0, s[8:9]
	s_add_i32 s7, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s7, s5
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_scc0 .LBB8_2
.LBB8_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22serialsum_accrossblockPjiji
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 12
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z22serialsum_accrossblockPjiji, .Lfunc_end8-_Z22serialsum_accrossblockPjiji
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 168
; NumSgprs: 12
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10mergeblockPjij      ; -- Begin function _Z10mergeblockPjij
	.globl	_Z10mergeblockPjij
	.p2align	8
	.type	_Z10mergeblockPjij,@function
_Z10mergeblockPjij:                     ; @_Z10mergeblockPjij
; %bb.0:
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB9_4
; %bb.1:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[4:5], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s15, s2
	v_add_nc_u32_e32 v0, s2, v0
	s_mul_i32 s6, s2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s4
	v_cmp_eq_u32_e32 vcc_lo, s6, v0
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v0, v2
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_cmp_gt_u32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB9_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b64 s[2:3], s[0:1], 0x0
	s_mov_b32 s7, 0
	v_ashrrev_i32_e32 v3, 31, v0
	s_lshl_b64 s[0:1], s[6:7], 2
	v_add_co_u32 v2, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v2, s4, v0
	v_add_nc_u32_e32 v3, 1, v1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_add_co_u32 v0, vcc_lo, s2, v4
	s_load_b32 s1, s[0:1], 0x0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
.LBB9_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[0:1], off
	v_cmp_ge_i32_e32 vcc_lo, v3, v2
	v_cmp_le_u32_e64 s0, s5, v3
	v_add_nc_u32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s0, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, s1, v4
	global_store_b32 v[0:1], v4, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB9_3
.LBB9_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10mergeblockPjij
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z10mergeblockPjij, .Lfunc_end9-_Z10mergeblockPjij
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	const_sum               ; @const_sum
	.type	const_sum,@object
	.section	.bss,"aw",@nobits
	.globl	const_sum
	.p2align	4, 0x0
const_sum:
	.zero	65536
	.size	const_sum, 65536

	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	" d_sum[i] : %d, total_pre : %d, d_mask[i] : %d \n"
	.size	.str, 49

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7getMaskPyPjijyj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7getMaskPyPjijyj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         120
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8getIndexPjS_S_ijj
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z8getIndexPjS_S_ijj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7scatterPyPjS_ij
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7scatterPyPjS_ij.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18gpu_add_block_sumsPjPKjS_m
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18gpu_add_block_sumsPjPKjS_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
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...

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