/* --------------------------------------------------------------------
        OPTIMIZED CODE MAKING USE OF REGISTERS + SHARED MEMORY
----------------------------------------------------------------------*/


#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
  cudaError_t error = cudaGetLastError ();
  if (error != cudaSuccess) {
    printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
    exit(-1);
  }
}

__global__ void cheby (float h2inv, float a, float b, float c, float d, float * __restrict__ RHS, float * __restrict__ Ap, float * __restrict__ Dinv, float * __restrict__ Ac, float * __restrict__ out, int L, int M, int N, float * __restrict__ out1) {
  //Determing the block's indices
  int blockdim_i= (int)(blockDim.x);
  int i0 = (int)(blockIdx.x)*(blockdim_i-4);
  int i = max (i0, 0) + (int)(threadIdx.x);
  int blockdim_j= (int)(blockDim.y);
  int j0 = (int)(blockIdx.y)*(blockdim_j-4);
  int j = max (j0, 0) + (int)(threadIdx.y);

  //Declarations
  float reg_Ac_m2=0, reg_Ac_m1=0, __shared__ sh_Ac_c0[32][32];
  float reg_Ap_m1=0;
  float reg_Dinv_m2=0, reg_Dinv_m1=0;
  float reg_RHS_m2=0, reg_RHS_m1=0;
  float reg_out1_m2=0, __shared__ sh_out1_m1[32][32];
  float reg_temp1_m1=0, reg_temp1_c0=0, reg_temp1_p1=0;
  float reg_temp2_m2=0, reg_temp2_m1=0, reg_temp2_c0=0;

  //Value Initialization
  if (j <= min (j0+blockdim_j-1, M-1) & i <= min (i0+blockdim_i-1, N-1)) {
    sh_Ac_c0[j-j0][i-i0] = 0;
    sh_out1_m1[j-j0][i-i0] = 0;
  }
  //Rest of the computation
  for (int k=0; k<=L-1; ++k) {
    //Fetch new plane
    sh_Ac_c0[j-j0][i-i0] = Ac[k*M*N + j*N + i];
    reg_Ap_m1 = Ap[max(k-1,0)*M*N + j*N + i];
    reg_Dinv_m1 = Dinv[max(k-1,0)*M*N + j*N + i];
    reg_RHS_m1 = RHS[max(k-1,0)*M*N + j*N + i];

    __syncthreads ();
    if (j >= max (j0+1, 1) & j <= min (j0+blockdim_j-2, M-2) & i >= max (i0+1, 1) & i <= min (i0+blockdim_i-2, N-2)) {
        reg_temp1_p1 -= (h2inv * (((0.03f * (((sh_Ac_c0[j-j0-1][i-i0-1] + sh_Ac_c0[j-j0-1][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0-1]) + sh_Ac_c0[j-j0+1][i-i0+1])) + (0.1f * (((sh_Ac_c0[j-j0-1][i-i0] + sh_Ac_c0[j-j0][i-i0-1]) + sh_Ac_c0[j-j0][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0]))) + (0.46f * sh_Ac_c0[j-j0][i-i0])));
        reg_temp1_c0 += (sh_Ac_c0[j-j0][i-i0] - (h2inv * (((0.1f * (((sh_Ac_c0[j-j0-1][i-i0-1] + sh_Ac_c0[j-j0-1][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0-1]) + sh_Ac_c0[j-j0+1][i-i0+1])) + (0.46f * (((sh_Ac_c0[j-j0-1][i-i0] + sh_Ac_c0[j-j0][i-i0-1]) + sh_Ac_c0[j-j0][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0]))) - (4.26f * sh_Ac_c0[j-j0][i-i0]))));
        reg_temp1_m1 -= (h2inv * (((0.03f * (((sh_Ac_c0[j-j0-1][i-i0-1] + sh_Ac_c0[j-j0-1][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0-1]) + sh_Ac_c0[j-j0+1][i-i0+1])) + (0.1f * (((sh_Ac_c0[j-j0-1][i-i0] + sh_Ac_c0[j-j0][i-i0-1]) + sh_Ac_c0[j-j0][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0]))) + (0.46f * sh_Ac_c0[j-j0][i-i0])));
        sh_out1_m1[j-j0][i-i0] = ((reg_Ac_m1 + (a * (reg_Ac_m1 - reg_Ap_m1))) + ((b * reg_Dinv_m1) * (reg_RHS_m1 - reg_temp1_m1)));
	out1[max(k-1,0)*M*N+j*N+i] = sh_out1_m1[j-j0][i-i0];
    }
    __syncthreads ();
    if (j >= max (j0+2, 1) & j <= min (j0+blockdim_j-3, M-2) & i >= max (i0+2, 1) & i <= min (i0+blockdim_i-3, N-2)) {
        reg_temp2_c0 -= (h2inv * (((0.03f * (((sh_out1_m1[j-j0-1][i-i0-1] + sh_out1_m1[j-j0-1][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0-1]) + sh_out1_m1[j-j0+1][i-i0+1])) + (0.1f * (((sh_out1_m1[j-j0-1][i-i0] + sh_out1_m1[j-j0][i-i0-1]) + sh_out1_m1[j-j0][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0]))) + (0.46f * sh_out1_m1[j-j0][i-i0])));
        reg_temp2_m1 += (sh_out1_m1[j-j0][i-i0] - (h2inv * (((0.1f * (((sh_out1_m1[j-j0-1][i-i0-1] + sh_out1_m1[j-j0-1][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0-1]) + sh_out1_m1[j-j0+1][i-i0+1])) + (0.46f * (((sh_out1_m1[j-j0-1][i-i0] + sh_out1_m1[j-j0][i-i0-1]) + sh_out1_m1[j-j0][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0]))) - (4.26f * sh_out1_m1[j-j0][i-i0]))));
        reg_temp2_m2 -= (h2inv * (((0.03f * (((sh_out1_m1[j-j0-1][i-i0-1] + sh_out1_m1[j-j0-1][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0-1]) + sh_out1_m1[j-j0+1][i-i0+1])) + (0.1f * (((sh_out1_m1[j-j0-1][i-i0] + sh_out1_m1[j-j0][i-i0-1]) + sh_out1_m1[j-j0][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0]))) + (0.46f * sh_out1_m1[j-j0][i-i0])));
        out[max(k-2,0)*M*N + j*N + i] = ((reg_out1_m2 + (c * (reg_out1_m2 - reg_Ac_m2))) + ((d * reg_Dinv_m2) * (reg_RHS_m2 - reg_temp2_m2)));
    }
    __syncthreads ();
    //Value rotation

    reg_Ac_m2 = reg_Ac_m1;
    reg_Ac_m1 = sh_Ac_c0[j-j0][i-i0];
    sh_Ac_c0[j-j0][i-i0] = 0;
    reg_Dinv_m2 = reg_Dinv_m1;
    reg_Dinv_m1 = 0;
    reg_RHS_m2 = reg_RHS_m1;
    reg_RHS_m1 = 0;
    reg_out1_m2 = sh_out1_m1[j-j0][i-i0];
    sh_out1_m1[j-j0][i-i0] = 0;
    reg_temp1_m1 = reg_temp1_c0;
    reg_temp1_c0 = reg_temp1_p1;
    reg_temp1_p1 = 0;
    reg_temp2_m2 = reg_temp2_m1;
    reg_temp2_m1 = reg_temp2_c0;
    reg_temp2_c0 = 0;
    __syncthreads ();
  }
}

extern "C" void host_code (float *h_Ac, float *h_Ap, float *h_Dinv, float *h_RHS, float *h_out, float *c1, float *c2, float h2inv, int L, int M, int N) {
  float *Ac;
  cudaMalloc (&Ac, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for Ac\n");
  cudaMemcpy (Ac, h_Ac, sizeof(float)*L*M*N, cudaMemcpyHostToDevice);
  float *Ap;
  cudaMalloc (&Ap, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for Ap\n");
  cudaMemcpy (Ap, h_Ap, sizeof(float)*L*M*N, cudaMemcpyHostToDevice);
  float *Dinv;
  cudaMalloc (&Dinv, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for Dinv\n");
  cudaMemcpy (Dinv, h_Dinv, sizeof(float)*L*M*N, cudaMemcpyHostToDevice);
  float *RHS;
  cudaMalloc (&RHS, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for RHS\n");
  cudaMemcpy (RHS, h_RHS, sizeof(float)*L*M*N, cudaMemcpyHostToDevice);
  float *out;
  cudaMalloc (&out, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out\n");
  float *out1;
  cudaMalloc (&out1, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out1\n");
  float *out2;
  cudaMalloc (&out2, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out2\n");
  float *out3;
  cudaMalloc (&out3, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out3\n");
  dim3 blockconfig_1 (32, 32, 1);
  dim3 gridconfig_1 (ceil(N, blockconfig_1.x-4), ceil(M, blockconfig_1.y-4), 1);
  cheby <<<gridconfig_1, blockconfig_1>>> (h2inv, c1[0], c2[0], c1[1], c2[1], RHS, Ap, Dinv, Ac, out2, L, M, N, out1);

  dim3 blockconfig_2 (32, 32, 1);
  dim3 gridconfig_2 (ceil(N, blockconfig_2.x-4), ceil(M, blockconfig_2.y-4), 1);
  cheby <<<gridconfig_2, blockconfig_2>>> (h2inv, c1[2], c2[2], c1[3], c2[3], RHS, out1, Dinv, out2, out, L, M, N, out3);
  cudaMemcpy (h_out, out, sizeof(float)*L*M*N, cudaMemcpyDeviceToHost);
}

	.file	"tmpxft_003520f3_00000000-6_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0:
.LFB2173:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2173:
	.size	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L3
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L3:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_
	.type	_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_, @function
_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 20(%rsp)
	movss	%xmm3, 16(%rsp)
	movss	%xmm4, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	304(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 80(%rsp)
	leaq	80(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 64(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	96(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z5chebyfffffPfS_S_S_S_iiiS_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 304
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L7:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_, .-_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_
	.globl	_Z5chebyfffffPfS_S_S_S_iiiS_
	.type	_Z5chebyfffffPfS_S_S_S_iiiS_, @function
_Z5chebyfffffPfS_S_S_S_iiiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_
	.cfi_endproc
.LFE2054:
	.size	_Z5chebyfffffPfS_S_S_S_iiiS_, .-_Z5chebyfffffPfS_S_S_S_iiiS_
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for Ac\n"
.LC2:
	.string	"Failed to allocate device memory for Ap\n"
.LC3:
	.string	"Failed to allocate device memory for Dinv\n"
.LC4:
	.string	"Failed to allocate device memory for RHS\n"
.LC5:
	.string	"Failed to allocate device memory for out\n"
.LC6:
	.string	"Failed to allocate device memory for out1\n"
.LC7:
	.string	"Failed to allocate device memory for out2\n"
.LC8:
	.string	"Failed to allocate device memory for out3\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r9, %rbx
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	%r8, 40(%rsp)
	movl	256(%rsp), %ebp
	leaq	56(%rsp), %rdi
	movq	%rcx, 32(%rsp)
	movq	240(%rsp), %r13
	movq	%rdx, 24(%rsp)
	movslq	264(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	movq	%rdx, %r12
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	movslq	%ebp, %rax
	imulq	%rdx, %rax
	movslq	248(%rsp), %rdx
	imulq	%rdx, %rax
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC3(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC4(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC5(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rsi
	leaq	96(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC6(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rsi
	leaq	104(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC7(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rsi
	leaq	112(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC8(%rip), %rdi
	call	_Z11check_errorPKc
	movl	$28, %ecx
	xorl	%edx, %edx
	movl	%ebp, %eax
	divl	%ecx
	movl	$1, %esi
	cmpl	$1, %edx
	sbbl	$-1, %eax
	xorl	%edx, %edx
	movl	%eax, %r14d
	movl	%r12d, %eax
	divl	%ecx
	movl	%r14d, 136(%rsp)
	movl	$1, %ecx
	cmpl	$1, %edx
	movabsq	$137438953504, %rdx
	sbbl	$-1, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 132(%rsp)
	movq	132(%rsp), %rdi
	movl	%eax, %r15d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	%rdx
	.cfi_def_cfa_offset 248
	movss	4(%r13), %xmm4
	movss	4(%rbx), %xmm3
	movss	0(%r13), %xmm2
	pushq	104(%rsp)
	.cfi_def_cfa_offset 256
	movss	(%rbx), %xmm1
	pushq	%r12
	.cfi_def_cfa_offset 264
	pushq	%rbp
	.cfi_def_cfa_offset 272
	movl	280(%rsp), %r9d
	movq	136(%rsp), %r8
	movq	88(%rsp), %rcx
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	movq	112(%rsp), %rdi
	movss	52(%rsp), %xmm0
	call	_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_
	addq	$32, %rsp
	.cfi_def_cfa_offset 240
.L15:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movl	%r15d, 156(%rsp)
	movabsq	$137438953504, %rdx
	movl	%r14d, 160(%rsp)
	movq	156(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	%rax
	.cfi_def_cfa_offset 248
	movss	12(%r13), %xmm4
	movss	12(%rbx), %xmm3
	movss	8(%r13), %xmm2
	pushq	120(%rsp)
	.cfi_def_cfa_offset 256
	movss	8(%rbx), %xmm1
	pushq	%r12
	.cfi_def_cfa_offset 264
	pushq	%rbp
	.cfi_def_cfa_offset 272
	movl	280(%rsp), %r9d
	movq	120(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	104(%rsp), %rdx
	movq	128(%rsp), %rsi
	movq	112(%rsp), %rdi
	movss	52(%rsp), %xmm0
	call	_Z42__device_stub__Z5chebyfffffPfS_S_S_S_iiiS_fffffPfS_S_S_S_iiiS_
	addq	$32, %rsp
	.cfi_def_cfa_offset 240
.L16:
	movq	8(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC9:
	.string	"_Z5chebyfffffPfS_S_S_S_iiiS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5chebyfffffPfS_S_S_S_iiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* --------------------------------------------------------------------
        OPTIMIZED CODE MAKING USE OF REGISTERS + SHARED MEMORY
----------------------------------------------------------------------*/


#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
  hipError_t error = hipGetLastError ();
  if (error != hipSuccess) {
    printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
    exit(-1);
  }
}

__global__ void cheby (float h2inv, float a, float b, float c, float d, float * __restrict__ RHS, float * __restrict__ Ap, float * __restrict__ Dinv, float * __restrict__ Ac, float * __restrict__ out, int L, int M, int N, float * __restrict__ out1) {
  //Determing the block's indices
  int blockdim_i= (int)(blockDim.x);
  int i0 = (int)(blockIdx.x)*(blockdim_i-4);
  int i = max (i0, 0) + (int)(threadIdx.x);
  int blockdim_j= (int)(blockDim.y);
  int j0 = (int)(blockIdx.y)*(blockdim_j-4);
  int j = max (j0, 0) + (int)(threadIdx.y);

  //Declarations
  float reg_Ac_m2=0, reg_Ac_m1=0, __shared__ sh_Ac_c0[32][32];
  float reg_Ap_m1=0;
  float reg_Dinv_m2=0, reg_Dinv_m1=0;
  float reg_RHS_m2=0, reg_RHS_m1=0;
  float reg_out1_m2=0, __shared__ sh_out1_m1[32][32];
  float reg_temp1_m1=0, reg_temp1_c0=0, reg_temp1_p1=0;
  float reg_temp2_m2=0, reg_temp2_m1=0, reg_temp2_c0=0;

  //Value Initialization
  if (j <= min (j0+blockdim_j-1, M-1) & i <= min (i0+blockdim_i-1, N-1)) {
    sh_Ac_c0[j-j0][i-i0] = 0;
    sh_out1_m1[j-j0][i-i0] = 0;
  }
  //Rest of the computation
  for (int k=0; k<=L-1; ++k) {
    //Fetch new plane
    sh_Ac_c0[j-j0][i-i0] = Ac[k*M*N + j*N + i];
    reg_Ap_m1 = Ap[max(k-1,0)*M*N + j*N + i];
    reg_Dinv_m1 = Dinv[max(k-1,0)*M*N + j*N + i];
    reg_RHS_m1 = RHS[max(k-1,0)*M*N + j*N + i];

    __syncthreads ();
    if (j >= max (j0+1, 1) & j <= min (j0+blockdim_j-2, M-2) & i >= max (i0+1, 1) & i <= min (i0+blockdim_i-2, N-2)) {
        reg_temp1_p1 -= (h2inv * (((0.03f * (((sh_Ac_c0[j-j0-1][i-i0-1] + sh_Ac_c0[j-j0-1][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0-1]) + sh_Ac_c0[j-j0+1][i-i0+1])) + (0.1f * (((sh_Ac_c0[j-j0-1][i-i0] + sh_Ac_c0[j-j0][i-i0-1]) + sh_Ac_c0[j-j0][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0]))) + (0.46f * sh_Ac_c0[j-j0][i-i0])));
        reg_temp1_c0 += (sh_Ac_c0[j-j0][i-i0] - (h2inv * (((0.1f * (((sh_Ac_c0[j-j0-1][i-i0-1] + sh_Ac_c0[j-j0-1][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0-1]) + sh_Ac_c0[j-j0+1][i-i0+1])) + (0.46f * (((sh_Ac_c0[j-j0-1][i-i0] + sh_Ac_c0[j-j0][i-i0-1]) + sh_Ac_c0[j-j0][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0]))) - (4.26f * sh_Ac_c0[j-j0][i-i0]))));
        reg_temp1_m1 -= (h2inv * (((0.03f * (((sh_Ac_c0[j-j0-1][i-i0-1] + sh_Ac_c0[j-j0-1][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0-1]) + sh_Ac_c0[j-j0+1][i-i0+1])) + (0.1f * (((sh_Ac_c0[j-j0-1][i-i0] + sh_Ac_c0[j-j0][i-i0-1]) + sh_Ac_c0[j-j0][i-i0+1]) + sh_Ac_c0[j-j0+1][i-i0]))) + (0.46f * sh_Ac_c0[j-j0][i-i0])));
        sh_out1_m1[j-j0][i-i0] = ((reg_Ac_m1 + (a * (reg_Ac_m1 - reg_Ap_m1))) + ((b * reg_Dinv_m1) * (reg_RHS_m1 - reg_temp1_m1)));
	out1[max(k-1,0)*M*N+j*N+i] = sh_out1_m1[j-j0][i-i0];
    }
    __syncthreads ();
    if (j >= max (j0+2, 1) & j <= min (j0+blockdim_j-3, M-2) & i >= max (i0+2, 1) & i <= min (i0+blockdim_i-3, N-2)) {
        reg_temp2_c0 -= (h2inv * (((0.03f * (((sh_out1_m1[j-j0-1][i-i0-1] + sh_out1_m1[j-j0-1][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0-1]) + sh_out1_m1[j-j0+1][i-i0+1])) + (0.1f * (((sh_out1_m1[j-j0-1][i-i0] + sh_out1_m1[j-j0][i-i0-1]) + sh_out1_m1[j-j0][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0]))) + (0.46f * sh_out1_m1[j-j0][i-i0])));
        reg_temp2_m1 += (sh_out1_m1[j-j0][i-i0] - (h2inv * (((0.1f * (((sh_out1_m1[j-j0-1][i-i0-1] + sh_out1_m1[j-j0-1][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0-1]) + sh_out1_m1[j-j0+1][i-i0+1])) + (0.46f * (((sh_out1_m1[j-j0-1][i-i0] + sh_out1_m1[j-j0][i-i0-1]) + sh_out1_m1[j-j0][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0]))) - (4.26f * sh_out1_m1[j-j0][i-i0]))));
        reg_temp2_m2 -= (h2inv * (((0.03f * (((sh_out1_m1[j-j0-1][i-i0-1] + sh_out1_m1[j-j0-1][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0-1]) + sh_out1_m1[j-j0+1][i-i0+1])) + (0.1f * (((sh_out1_m1[j-j0-1][i-i0] + sh_out1_m1[j-j0][i-i0-1]) + sh_out1_m1[j-j0][i-i0+1]) + sh_out1_m1[j-j0+1][i-i0]))) + (0.46f * sh_out1_m1[j-j0][i-i0])));
        out[max(k-2,0)*M*N + j*N + i] = ((reg_out1_m2 + (c * (reg_out1_m2 - reg_Ac_m2))) + ((d * reg_Dinv_m2) * (reg_RHS_m2 - reg_temp2_m2)));
    }
    __syncthreads ();
    //Value rotation

    reg_Ac_m2 = reg_Ac_m1;
    reg_Ac_m1 = sh_Ac_c0[j-j0][i-i0];
    sh_Ac_c0[j-j0][i-i0] = 0;
    reg_Dinv_m2 = reg_Dinv_m1;
    reg_Dinv_m1 = 0;
    reg_RHS_m2 = reg_RHS_m1;
    reg_RHS_m1 = 0;
    reg_out1_m2 = sh_out1_m1[j-j0][i-i0];
    sh_out1_m1[j-j0][i-i0] = 0;
    reg_temp1_m1 = reg_temp1_c0;
    reg_temp1_c0 = reg_temp1_p1;
    reg_temp1_p1 = 0;
    reg_temp2_m2 = reg_temp2_m1;
    reg_temp2_m1 = reg_temp2_c0;
    reg_temp2_c0 = 0;
    __syncthreads ();
  }
}

extern "C" void host_code (float *h_Ac, float *h_Ap, float *h_Dinv, float *h_RHS, float *h_out, float *c1, float *c2, float h2inv, int L, int M, int N) {
  float *Ac;
  hipMalloc (&Ac, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for Ac\n");
  hipMemcpy (Ac, h_Ac, sizeof(float)*L*M*N, hipMemcpyHostToDevice);
  float *Ap;
  hipMalloc (&Ap, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for Ap\n");
  hipMemcpy (Ap, h_Ap, sizeof(float)*L*M*N, hipMemcpyHostToDevice);
  float *Dinv;
  hipMalloc (&Dinv, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for Dinv\n");
  hipMemcpy (Dinv, h_Dinv, sizeof(float)*L*M*N, hipMemcpyHostToDevice);
  float *RHS;
  hipMalloc (&RHS, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for RHS\n");
  hipMemcpy (RHS, h_RHS, sizeof(float)*L*M*N, hipMemcpyHostToDevice);
  float *out;
  hipMalloc (&out, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out\n");
  float *out1;
  hipMalloc (&out1, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out1\n");
  float *out2;
  hipMalloc (&out2, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out2\n");
  float *out3;
  hipMalloc (&out3, sizeof(float)*L*M*N);
  check_error ("Failed to allocate device memory for out3\n");
  dim3 blockconfig_1 (32, 32, 1);
  dim3 gridconfig_1 (ceil(N, blockconfig_1.x-4), ceil(M, blockconfig_1.y-4), 1);
  cheby <<<gridconfig_1, blockconfig_1>>> (h2inv, c1[0], c2[0], c1[1], c2[1], RHS, Ap, Dinv, Ac, out2, L, M, N, out1);

  dim3 blockconfig_2 (32, 32, 1);
  dim3 gridconfig_2 (ceil(N, blockconfig_2.x-4), ceil(M, blockconfig_2.y-4), 1);
  cheby <<<gridconfig_2, blockconfig_2>>> (h2inv, c1[2], c2[2], c1[3], c2[3], RHS, out1, Dinv, out2, out, L, M, N, out3);
  hipMemcpy (h_out, out, sizeof(float)*L*M*N, hipMemcpyDeviceToHost);
}

	.text
	.file	"test.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_ # -- Begin function _Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	.type	_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_,@function
_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_: # @_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	8(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	4(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	72(%rsp), %r12
	movq	%rdi, (%r12)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r10, 8(%rbx)
	movq	%r11, 16(%rbx)
	movq	%r14, 24(%rbx)
	movq	%r15, 32(%rbx)
	movq	%r12, 40(%rbx)
	movq	%rdi, 48(%rbx)
	movq	%rsi, 56(%rbx)
	movq	%rdx, 64(%rbx)
	movq	%rcx, 72(%rbx)
	movq	%r8, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5chebyfffffPfS_S_S_S_iiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_, .Lfunc_end1-_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%r9, 24(%rsp)                   # 8-byte Spill
	movq	%r8, 88(%rsp)                   # 8-byte Spill
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, %rbx
	movq	%rdi, %r12
	movslq	184(%rsp), %r14
	movslq	192(%rsp), %r13
	movslq	200(%rsp), %rbp
	movq	%r14, 32(%rsp)                  # 8-byte Spill
	imulq	%r13, %r14
	imulq	%rbp, %r14
	shlq	$2, %r14
	leaq	112(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	104(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	72(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.5, %edi
	callq	_Z11check_errorPKc
	leaq	48(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.6, %edi
	callq	_Z11check_errorPKc
	leaq	40(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.7, %edi
	callq	_Z11check_errorPKc
	leaq	96(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.8, %edi
	callq	_Z11check_errorPKc
	movl	%ebp, %eax
	shrl	$2, %eax
	imulq	$613566757, %rax, %rbx          # imm = 0x24924925
	shrq	$32, %rbx
	leal	(%rbx,%rbx,8), %eax
	leal	(%rax,%rax,2), %ecx
	addl	%ebx, %ecx
	xorl	%eax, %eax
	movq	%rbp, 16(%rsp)                  # 8-byte Spill
	movl	%ebp, %r15d
	subl	%ecx, %r15d
	setne	%al
	addl	%ebx, %eax
	movl	%r13d, %ecx
	shrl	$2, %ecx
	imulq	$613566757, %rcx, %rbp          # imm = 0x24924925
	shrq	$32, %rbp
	leal	(%rbp,%rbp,8), %ecx
	leal	(%rcx,%rcx,2), %ecx
	addl	%ebp, %ecx
	xorl	%edi, %edi
	movl	%r13d, %r12d
	subl	%ecx, %r12d
	setne	%dil
	addl	%ebp, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	24(%rsp), %rax                  # 8-byte Reload
	movss	(%rax), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	movss	4(%rax), %xmm3                  # xmm3 = mem[0],zero,zero,zero
	movq	176(%rsp), %rax
	movss	(%rax), %xmm2                   # xmm2 = mem[0],zero,zero,zero
	movss	4(%rax), %xmm4                  # xmm4 = mem[0],zero,zero,zero
	movq	64(%rsp), %rdi
	movq	104(%rsp), %rsi
	movq	72(%rsp), %rdx
	movq	112(%rsp), %rcx
	movq	40(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	40(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB2_2:
	cmpl	$1, %r15d
	sbbl	$-1, %ebx
	cmpl	$1, %r12d
	sbbl	$-1, %ebp
	shlq	$32, %rbp
	orq	%rbx, %rbp
	movq	%rbp, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	24(%rsp), %rax                  # 8-byte Reload
	movss	8(%rax), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	movss	12(%rax), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	movq	176(%rsp), %rax
	movss	8(%rax), %xmm2                  # xmm2 = mem[0],zero,zero,zero
	movss	12(%rax), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	movq	64(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	72(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	56(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	40(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB2_4:
	movq	56(%rsp), %rsi
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5chebyfffffPfS_S_S_S_iiiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z5chebyfffffPfS_S_S_S_iiiS_,@object # @_Z5chebyfffffPfS_S_S_S_iiiS_
	.section	.rodata,"a",@progbits
	.globl	_Z5chebyfffffPfS_S_S_S_iiiS_
	.p2align	3, 0x0
_Z5chebyfffffPfS_S_S_S_iiiS_:
	.quad	_Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	.size	_Z5chebyfffffPfS_S_S_S_iiiS_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for Ac\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for Ap\n"
	.size	.L.str.2, 41

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for Dinv\n"
	.size	.L.str.3, 43

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for RHS\n"
	.size	.L.str.4, 42

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate device memory for out\n"
	.size	.L.str.5, 42

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to allocate device memory for out1\n"
	.size	.L.str.6, 43

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to allocate device memory for out2\n"
	.size	.L.str.7, 43

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate device memory for out3\n"
	.size	.L.str.8, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5chebyfffffPfS_S_S_S_iiiS_"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__chebyfffffPfS_S_S_S_iiiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5chebyfffffPfS_S_S_S_iiiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5chebyfffffPfS_S_S_S_iiiS_ ; -- Begin function _Z5chebyfffffPfS_S_S_S_iiiS_
	.globl	_Z5chebyfffffPfS_S_S_S_iiiS_
	.p2align	8
	.type	_Z5chebyfffffPfS_S_S_S_iiiS_,@function
_Z5chebyfffffPfS_S_S_S_iiiS_:           ; @_Z5chebyfffffPfS_S_S_S_iiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b128 s[16:19], s[0:1], 0x40
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_add_i32 s25, s3, -4
	s_add_i32 s27, s2, -4
	s_mul_i32 s25, s25, s14
	s_mul_i32 s27, s27, s15
	s_max_i32 s4, s25, 0
	s_add_i32 s28, s27, s2
	v_add_nc_u32_e32 v0, s4, v3
	s_max_i32 s4, s27, 0
	s_add_i32 s26, s25, s3
	v_add_nc_u32_e32 v1, s4, v4
	s_min_i32 s2, s28, s17
	v_subrev_nc_u32_e32 v2, s25, v0
	s_min_i32 s3, s26, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	v_cmp_gt_i32_e64 s2, s3, v0
	v_subrev_nc_u32_e32 v5, s27, v1
	v_lshlrev_b32_e32 v2, 2, v2
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v6, v5, 7, v2
	v_mov_b32_e32 v7, 0
	ds_store_2addr_stride64_b32 v6, v7, v7 offset1:16
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_i32 s16, 1
	s_cbranch_scc1 .LBB0_9
; %bb.3:                                ; %.lr.ph
	s_add_i32 s29, s17, -2
	s_add_i32 s2, s28, -2
	s_cmp_lt_i32 s28, s17
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cselect_b32 s3, s2, s29
	v_cmp_ne_u32_e64 s2, 0, v3
	v_cmp_ge_i32_e64 s3, s3, v1
	s_clause 0x4
	s_load_b256 s[4:11], s[0:1], 0x18
	s_load_b64 s[20:21], s[0:1], 0x38
	s_load_b64 s[22:23], s[0:1], 0x50
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b32 s19, s[0:1], 0x10
	s_and_b32 s0, vcc_lo, s2
	s_add_i32 s30, s18, -2
	s_and_b32 s3, s0, s3
	s_add_i32 s0, s26, -2
	s_cmp_lt_i32 s26, s18
	v_dual_mov_b32 v16, 0 :: v_dual_add_nc_u32 v9, -2, v1
	v_dual_mov_b32 v14, 0 :: v_dual_lshlrev_b32 v3, 7, v5
	s_cselect_b32 s0, s0, s30
	s_add_i32 s28, s28, -3
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v4, -2, v0
	v_cmp_ge_i32_e32 vcc_lo, s0, v0
	s_max_i32 s0, s27, -1
	s_min_i32 s1, s28, s29
	v_cmp_le_i32_e64 s0, s0, v9
	v_cmp_ge_i32_e64 s1, s1, v1
	s_max_i32 s2, s25, -1
	v_dual_mov_b32 v24, 0 :: v_dual_add_nc_u32 v5, v3, v2
	v_dual_mov_b32 v17, 0 :: v_dual_add_nc_u32 v10, -4, v2
	v_dual_mov_b32 v15, 0 :: v_dual_add_nc_u32 v8, 0xf80, v3
	v_dual_mov_b32 v26, 0 :: v_dual_add_nc_u32 v3, 0xffffff80, v3
	v_add_nc_u32_e32 v2, 4, v2
	v_cmp_le_i32_e64 s2, s2, v4
	s_add_i32 s26, s26, -3
	s_and_b32 s0, s0, s1
	s_min_i32 s1, s26, s30
	v_dual_mov_b32 v18, 0 :: v_dual_add_nc_u32 v7, v8, v10
	v_add_nc_u32_e32 v8, v8, v2
	v_add_nc_u32_e32 v10, v3, v10
	v_add_nc_u32_e32 v11, v3, v2
	v_mad_u64_u32 v[2:3], null, s18, v1, v[0:1]
	s_and_b32 s2, s2, s0
	v_cmp_ge_i32_e64 s0, s1, v0
	v_dual_mov_b32 v19, 0 :: v_dual_add_nc_u32 v6, 0x1000, v5
	v_dual_mov_b32 v20, 0 :: v_dual_add_nc_u32 v9, 0xffc, v5
	v_add_nc_u32_e32 v12, -4, v5
	s_mov_b32 s24, 0
	s_and_b32 s1, vcc_lo, s3
	s_and_b32 s0, s0, s2
	s_mul_i32 s2, s18, s17
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	s_max_i32 s3, s24, 1
	v_mov_b32_e32 v25, 0
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s3, s17, v[1:2]
	v_mad_u64_u32 v[21:22], null, v3, s18, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[27:28], 2, v[2:3]
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[21:22]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v21, vcc_lo, s10, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v22, vcc_lo, s11, v28, vcc_lo
	v_add_co_u32 v27, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v28, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v29, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v31, v[21:22], off
	global_load_b32 v21, v[27:28], off
	global_load_b32 v23, v[29:30], off
	v_mov_b32_e32 v22, v26
	s_waitcnt vmcnt(2)
	ds_store_b32 v6, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v25, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v26, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s23, v4, vcc_lo
	global_load_b32 v33, v[25:26], off
	ds_load_2addr_b32 v[25:26], v9 offset1:1
	ds_load_2addr_b32 v[27:28], v7 offset1:1
	ds_load_b32 v34, v8
	ds_load_2addr_b32 v[29:30], v6 offset0:1 offset1:33
	ds_load_2addr_b32 v[31:32], v6 offset0:31 offset1:32
	s_waitcnt lgkmcnt(2)
	v_add_f32_e32 v27, v27, v34
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v27, v31
	v_add_f32_e32 v27, v27, v30
	v_add_f32_e32 v25, v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v25, v29
	v_mul_f32_e32 v29, s14, v21
	v_add_f32_e32 v25, v25, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, 0x3dcccccd, v25
	v_fmac_f32_e32 v28, 0x3cf5c28f, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, 0x3eeb851f, v26
	v_fma_f32 v16, -v28, s12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v25, 0x3eeb851f, v25 :: v_dual_sub_f32 v16, v23, v16
	v_fmac_f32_e32 v25, 0x3dcccccd, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, 0xc08851ec, v26
	v_fma_f32 v26, -v25, s12, v26
	v_fma_f32 v25, -v28, s12, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v24, v24, v26 :: v_dual_sub_f32 v27, v22, v33
	v_fma_f32 v27, s13, v27, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v27, v29, v16
	ds_store_b32 v5, v27
	global_store_b32 v[3:4], v27, off
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v16, v24 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	ds_load_2addr_b32 v[3:4], v12 offset1:1
	ds_load_2addr_b32 v[26:27], v10 offset1:1
	ds_load_b32 v24, v11
	ds_load_2addr_b32 v[28:29], v5 offset0:1 offset1:33
	ds_load_2addr_b32 v[30:31], v5 offset0:31 offset1:32
	s_max_i32 s25, s24, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_add_i32 s25, s25, -2
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v3, v27, v3 :: v_dual_add_f32 v24, v26, v24
	v_mad_u64_u32 v[26:27], null, s25, s17, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v28 :: v_dual_add_f32 v24, v24, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, v26, s18, v[0:1]
	v_dual_add_f32 v3, v3, v31 :: v_dual_add_f32 v24, v24, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v26, 0x3eeb851f, v3
	v_mul_f32_e32 v29, 0x3dcccccd, v3
	v_ashrrev_i32_e32 v28, 31, v27
	v_sub_f32_e32 v3, v15, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v26, 0x3dcccccd, v24
	v_fmac_f32_e32 v29, 0x3cf5c28f, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v19, s19, v19 :: v_dual_fmac_f32 v26, 0xc08851ec, v4
	v_fmac_f32_e32 v29, 0x3eeb851f, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v26, s12, v4
	v_fma_f32 v17, -v29, s12, v17
	v_fmac_f32_e32 v15, s15, v3
	v_fma_f32 v3, -v29, s12, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v14, v14, v4
	v_sub_f32_e32 v20, v18, v17
	v_lshlrev_b64 v[17:18], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v19, v20
	v_add_co_u32 v17, vcc_lo, s20, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v18, vcc_lo, s21, v18, vcc_lo
	global_store_b32 v[17:18], v15, off
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v26, v6
	ds_load_b32 v15, v5
	v_dual_mov_b32 v17, v14 :: v_dual_add_nc_u32 v2, s2, v2
	v_dual_mov_b32 v14, v3 :: v_dual_mov_b32 v19, v21
	v_mov_b32_e32 v24, v25
	v_mov_b32_e32 v18, v23
	v_mov_b32_e32 v20, v22
	s_add_i32 s24, s24, 1
	ds_store_b32 v6, v13
	ds_store_b32 v5, v13
	s_cmp_eq_u32 s16, s24
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_9:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5chebyfffffPfS_S_S_S_iiiS_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5chebyfffffPfS_S_S_S_iiiS_, .Lfunc_end0-_Z5chebyfffffPfS_S_S_S_iiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1336
; NumSgprs: 33
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .actual_access:  write_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5chebyfffffPfS_S_S_S_iiiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         _Z5chebyfffffPfS_S_S_S_iiiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
