#include <curand.h>
#include <curand_kernel.h>

#define DIM 1600
#define PI 3.14159265

__global__ void Rotate(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,
                        unsigned char *B_input, size_t i_size, float a,
                        unsigned long col, unsigned long row)
{
  int x = threadIdx.x + (blockIdx.x * blockDim.x);
  int y = threadIdx.y + (blockIdx.y * blockDim.y);
  int offset = x + y * blockDim.x * gridDim.x;
  x = x - (blockDim.x * gridDim.x / 2);
  y = y - (blockDim.y * gridDim.y / 2);

  unsigned char* f_r, *f_g, *f_b;

  int ximg = (x*cos(a) + y*sin(a)) + (col/2), yimg = (y*cos(a) - x*sin(a)) + (row/2);
  if (ximg < col && yimg < row) {
    f_r = (unsigned char*)((char*)R_input + yimg*i_size);
    f_g = (unsigned char*)((char*)G_input + yimg*i_size);
    f_b = (unsigned char*)((char*)B_input + yimg*i_size);
    ptr[offset].x = f_r[ximg];
    ptr[offset].y = f_g[ximg];
    ptr[offset].z = f_b[ximg];
    ptr[offset].w = 255;
  } else{
    ptr[offset].x = 0;
    ptr[offset].y = 0;
    ptr[offset].z = 0;
    ptr[offset].w = 255;
  }

}

__global__ void Scale(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input,
                        unsigned char *R_output, unsigned char *G_output,unsigned char *B_output,
                        size_t i_size, size_t pitch2, float s,
                        unsigned long col, unsigned long row){
  float x = threadIdx.x + (blockIdx.x * blockDim.x);
  float y = threadIdx.y + (blockIdx.y * blockDim.y);
  int offset = x + y * pitch2;
  x = x - (DIM / 2);
  y = y - (DIM / 2);

  unsigned char* f_r, *f_g, *f_b;
  x /= s; y /= s;

  int ximg = x + (col/2), yimg = y + (row/2);
  if (ximg < (col - 1) && yimg < (row - 1)) {
    f_r = (unsigned char*)((char*)R_input + yimg*i_size);
    f_g = (unsigned char*)((char*)G_input + yimg*i_size);
    f_b = (unsigned char*)((char*)B_input + yimg*i_size);
    float cx = x - floor(x);
    float cy = y - floor(y);
    float R1 = f_r[ximg]*(1 - cx) + f_r[ximg + 1]*(cx);
    float R2 = f_r[ximg + i_size]*(1 - cx) + f_r[ximg + 1 + i_size]*(cx);
    R_output[offset] = R1*(1 - cy) + R2*(cy);

    R1 = f_g[ximg]*(1 - cx) + f_g[ximg + 1]*(cx);
    R2 = f_g[ximg + i_size]*(1 - cx) + f_g[ximg + 1 + i_size]*(cx);
    G_output[offset] = R1*(1 - cy) + R2*(cy);

    R1 = f_b[ximg]*(1 - cx) + f_b[ximg + 1]*(cx);
    R2 = f_b[ximg + i_size]*(1 - cx) + f_b[ximg + 1 + i_size]*(cx);
    B_output[offset] = R1*(1 - cy) + R2*(cy);
  }else{
    R_output[offset] = 0;
    G_output[offset] = 0;
    B_output[offset] = 0;
  }
}

	.file	"tmpxft_0034534c_00000000-6_RE_transform.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2224:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2224:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z6RotateP6uchar4PhS1_S1_mfmmP6uchar4PhS1_S1_mfmm
	.type	_Z43__device_stub__Z6RotateP6uchar4PhS1_S1_mfmmP6uchar4PhS1_S1_mfmm, @function
_Z43__device_stub__Z6RotateP6uchar4PhS1_S1_mfmmP6uchar4PhS1_S1_mfmm:
.LFB2246:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z6RotateP6uchar4PhS1_S1_mfmm(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2246:
	.size	_Z43__device_stub__Z6RotateP6uchar4PhS1_S1_mfmmP6uchar4PhS1_S1_mfmm, .-_Z43__device_stub__Z6RotateP6uchar4PhS1_S1_mfmmP6uchar4PhS1_S1_mfmm
	.globl	_Z6RotateP6uchar4PhS1_S1_mfmm
	.type	_Z6RotateP6uchar4PhS1_S1_mfmm, @function
_Z6RotateP6uchar4PhS1_S1_mfmm:
.LFB2247:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z6RotateP6uchar4PhS1_S1_mfmmP6uchar4PhS1_S1_mfmm
	.cfi_endproc
.LFE2247:
	.size	_Z6RotateP6uchar4PhS1_S1_mfmm, .-_Z6RotateP6uchar4PhS1_S1_mfmm
	.globl	_Z39__device_stub__Z5ScalePhS_S_S_S_S_mmfmmPhS_S_S_S_S_mmfmm
	.type	_Z39__device_stub__Z5ScalePhS_S_S_S_S_mmfmmPhS_S_S_S_S_mmfmm, @function
_Z39__device_stub__Z5ScalePhS_S_S_S_S_mmfmmPhS_S_S_S_S_mmfmm:
.LFB2248:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z5ScalePhS_S_S_S_S_mmfmm(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L8:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2248:
	.size	_Z39__device_stub__Z5ScalePhS_S_S_S_S_mmfmmPhS_S_S_S_S_mmfmm, .-_Z39__device_stub__Z5ScalePhS_S_S_S_S_mmfmmPhS_S_S_S_S_mmfmm
	.globl	_Z5ScalePhS_S_S_S_S_mmfmm
	.type	_Z5ScalePhS_S_S_S_S_mmfmm, @function
_Z5ScalePhS_S_S_S_S_mmfmm:
.LFB2249:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z5ScalePhS_S_S_S_S_mmfmmPhS_S_S_S_S_mmfmm
	.cfi_endproc
.LFE2249:
	.size	_Z5ScalePhS_S_S_S_S_mmfmm, .-_Z5ScalePhS_S_S_S_S_mmfmm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5ScalePhS_S_S_S_S_mmfmm"
.LC1:
	.string	"_Z6RotateP6uchar4PhS1_S1_mfmm"
.LC2:
	.string	"precalc_xorwow_matrix"
.LC3:
	.string	"precalc_xorwow_offset_matrix"
.LC4:
	.string	"mrg32k3aM1"
.LC5:
	.string	"mrg32k3aM2"
.LC6:
	.string	"mrg32k3aM1SubSeq"
.LC7:
	.string	"mrg32k3aM2SubSeq"
.LC8:
	.string	"mrg32k3aM1Seq"
.LC9:
	.string	"mrg32k3aM2Seq"
.LC10:
	.string	"__cr_lgamma_table"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2251:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5ScalePhS_S_S_S_S_mmfmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6RotateP6uchar4PhS1_S1_mfmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2251:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>

#define DIM 1600
#define PI 3.14159265

__global__ void Rotate(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,
                        unsigned char *B_input, size_t i_size, float a,
                        unsigned long col, unsigned long row)
{
  int x = threadIdx.x + (blockIdx.x * blockDim.x);
  int y = threadIdx.y + (blockIdx.y * blockDim.y);
  int offset = x + y * blockDim.x * gridDim.x;
  x = x - (blockDim.x * gridDim.x / 2);
  y = y - (blockDim.y * gridDim.y / 2);

  unsigned char* f_r, *f_g, *f_b;

  int ximg = (x*cos(a) + y*sin(a)) + (col/2), yimg = (y*cos(a) - x*sin(a)) + (row/2);
  if (ximg < col && yimg < row) {
    f_r = (unsigned char*)((char*)R_input + yimg*i_size);
    f_g = (unsigned char*)((char*)G_input + yimg*i_size);
    f_b = (unsigned char*)((char*)B_input + yimg*i_size);
    ptr[offset].x = f_r[ximg];
    ptr[offset].y = f_g[ximg];
    ptr[offset].z = f_b[ximg];
    ptr[offset].w = 255;
  } else{
    ptr[offset].x = 0;
    ptr[offset].y = 0;
    ptr[offset].z = 0;
    ptr[offset].w = 255;
  }

}

__global__ void Scale(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input,
                        unsigned char *R_output, unsigned char *G_output,unsigned char *B_output,
                        size_t i_size, size_t pitch2, float s,
                        unsigned long col, unsigned long row){
  float x = threadIdx.x + (blockIdx.x * blockDim.x);
  float y = threadIdx.y + (blockIdx.y * blockDim.y);
  int offset = x + y * pitch2;
  x = x - (DIM / 2);
  y = y - (DIM / 2);

  unsigned char* f_r, *f_g, *f_b;
  x /= s; y /= s;

  int ximg = x + (col/2), yimg = y + (row/2);
  if (ximg < (col - 1) && yimg < (row - 1)) {
    f_r = (unsigned char*)((char*)R_input + yimg*i_size);
    f_g = (unsigned char*)((char*)G_input + yimg*i_size);
    f_b = (unsigned char*)((char*)B_input + yimg*i_size);
    float cx = x - floor(x);
    float cy = y - floor(y);
    float R1 = f_r[ximg]*(1 - cx) + f_r[ximg + 1]*(cx);
    float R2 = f_r[ximg + i_size]*(1 - cx) + f_r[ximg + 1 + i_size]*(cx);
    R_output[offset] = R1*(1 - cy) + R2*(cy);

    R1 = f_g[ximg]*(1 - cx) + f_g[ximg + 1]*(cx);
    R2 = f_g[ximg + i_size]*(1 - cx) + f_g[ximg + 1 + i_size]*(cx);
    G_output[offset] = R1*(1 - cy) + R2*(cy);

    R1 = f_b[ximg]*(1 - cx) + f_b[ximg + 1]*(cx);
    R2 = f_b[ximg + i_size]*(1 - cx) + f_b[ximg + 1 + i_size]*(cx);
    B_output[offset] = R1*(1 - cy) + R2*(cy);
  }else{
    R_output[offset] = 0;
    G_output[offset] = 0;
    B_output[offset] = 0;
  }
}

	.text
	.file	"RE_transform.hip"
	.globl	_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm # -- Begin function _Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.type	_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm,@function
_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm: # @_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	32(%rsp), %r10
	movq	%r9, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, .Lfunc_end0-_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm # -- Begin function _Z20__device_stub__ScalePhS_S_S_S_S_mmfmm
	.type	_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm,@function
_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm: # @_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5ScalePhS_S_S_S_S_mmfmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm, .Lfunc_end1-_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5ScalePhS_S_S_S_S_mmfmm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm,@object # @_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.section	.rodata,"a",@progbits
	.globl	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.p2align	3, 0x0
_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm:
	.quad	_Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.size	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, 8

	.type	_Z5ScalePhS_S_S_S_S_mmfmm,@object # @_Z5ScalePhS_S_S_S_S_mmfmm
	.globl	_Z5ScalePhS_S_S_S_S_mmfmm
	.p2align	3, 0x0
_Z5ScalePhS_S_S_S_S_mmfmm:
	.quad	_Z20__device_stub__ScalePhS_S_S_S_S_mmfmm
	.size	_Z5ScalePhS_S_S_S_S_mmfmm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm"
	.size	.L__unnamed_1, 47

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z5ScalePhS_S_S_S_S_mmfmm"
	.size	.L__unnamed_2, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.addrsig_sym _Z20__device_stub__ScalePhS_S_S_S_S_mmfmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.addrsig_sym _Z5ScalePhS_S_S_S_S_mmfmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm ; -- Begin function _Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.globl	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
	.p2align	8
	.type	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm,@function
_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm: ; @_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
; %bb.0:
	s_load_b32 s16, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e64 s4, 0x48000000, |s16|
	s_and_b32 s17, s16, 0x7fffffff
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_2
; %bb.1:
	s_and_b32 s2, s17, 0x7fffff
	s_lshr_b32 s3, s17, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s5, s2, 0xfe5163ab
	s_mul_i32 s6, s2, 0x3c439041
	s_mul_hi_u32 s7, s2, 0x3c439041
	s_add_u32 s5, s5, s6
	s_addc_u32 s6, 0, s7
	s_mul_i32 s7, s2, 0xdb629599
	s_mul_hi_u32 s8, s2, 0xdb629599
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s2, 0xf534ddc0
	s_mul_hi_u32 s9, s2, 0xf534ddc0
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s2, 0xfc2757d1
	s_mul_hi_u32 s10, s2, 0xfc2757d1
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s2, 0x4e441529
	s_mul_hi_u32 s11, s2, 0x4e441529
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s11, s2, 0xfe5163ab
	s_mul_hi_u32 s12, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s13, s6, s8
	s_cselect_b32 s5, s5, s7
	s_cselect_b32 s6, s11, s6
	s_add_u32 s2, s10, s2
	s_addc_u32 s10, 0, s12
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s11, 0xffffffc0, 0
	s_cselect_b32 s7, s7, s9
	s_cselect_b32 s2, s8, s2
	s_cselect_b32 s8, s9, s10
	s_add_i32 s11, s11, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s11, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s9, s7, s2
	s_cselect_b32 s2, s2, s8
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s8, s5, s13
	s_cselect_b32 s5, s6, s5
	s_add_i32 s3, s3, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s2, s9, s2
	s_cselect_b32 s9, s7, s9
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s5, s5, s8
	s_add_i32 s6, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s6
	s_cmp_eq_u32 s6, 0
	v_mov_b32_e32 v1, s3
	s_cselect_b32 s6, -1, 0
	v_alignbit_b32 v2, s2, s9, v1
	v_alignbit_b32 v3, s9, s7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v2
	v_cndmask_b32_e64 v2, v3, s9, s6
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v3, s2, v2, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v3, s8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v4, v3
	v_min_u32_e32 v4, 32, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v6, 23, v4
	v_alignbit_b32 v1, s7, s5, v1
	v_sub_nc_u32_e32 v5, 31, v4
	v_cndmask_b32_e64 v1, v1, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v2, v2, v1, 30
	v_alignbit_b32 v1, v1, s5, 30
	s_lshr_b32 s5, s2, 29
	s_lshl_b32 s5, s5, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, s8, v2
	v_xor_b32_e32 v1, s8, v1
	s_or_b32 s6, s5, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, s6, v6
	v_alignbit_b32 v3, v3, v2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v1, v2, v1, v5
	v_alignbit_b32 v2, v3, v1, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v5, v2
	v_min_u32_e32 v5, 32, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, 31, v5
	v_alignbit_b32 v1, v2, v1, v7
	v_lshrrev_b32_e32 v2, 9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v1, 9, v1
	v_or_b32_e32 v2, v2, v6
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 23, v4
	v_sub_nc_u32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x3fc90fda, v2
	v_add_nc_u32_e32 v1, 0x33000000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, 0x3fc90fda, v2, -v3
	v_or_b32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v2, 0x33a22168, v4
	s_lshr_b32 s5, s2, 30
	s_mov_b32 s2, 0
	s_add_i32 s3, s3, s5
	v_fmac_f32_e32 v2, 0x3fc90fda, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v1, v3, v2
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr1
.LBB0_3:                                ; %Flow123
	v_mov_b32_e32 v2, s3
	v_mul_f32_e64 v3, 0x3f22f983, |s16|
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v3
	v_fma_f32 v1, 0xbfc90fda, v2, |s16|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v2, 0xb3a22168, v1
	v_fmamk_f32 v1, v2, 0xa7c234c4, v1
	v_cvt_i32_f32_e32 v2, v2
.LBB0_5:                                ; %_ZL3cosf.exit
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_7
; %bb.6:
	s_and_b32 s2, s17, 0x7fffff
	s_lshr_b32 s3, s17, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s5, s2, 0xfe5163ab
	s_mul_i32 s6, s2, 0x3c439041
	s_mul_hi_u32 s7, s2, 0x3c439041
	s_add_u32 s5, s5, s6
	s_addc_u32 s6, 0, s7
	s_mul_i32 s7, s2, 0xdb629599
	s_mul_hi_u32 s8, s2, 0xdb629599
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s2, 0xf534ddc0
	s_mul_hi_u32 s9, s2, 0xf534ddc0
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s2, 0xfc2757d1
	s_mul_hi_u32 s10, s2, 0xfc2757d1
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s2, 0x4e441529
	s_mul_hi_u32 s11, s2, 0x4e441529
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s11, s2, 0xfe5163ab
	s_mul_hi_u32 s12, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s13, s6, s8
	s_cselect_b32 s5, s5, s7
	s_cselect_b32 s6, s11, s6
	s_add_u32 s2, s10, s2
	s_addc_u32 s10, 0, s12
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s11, 0xffffffc0, 0
	s_cselect_b32 s7, s7, s9
	s_cselect_b32 s2, s8, s2
	s_cselect_b32 s8, s9, s10
	s_add_i32 s11, s11, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s11, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s9, s7, s2
	s_cselect_b32 s2, s2, s8
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s8, s5, s13
	s_cselect_b32 s5, s6, s5
	s_add_i32 s3, s3, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s2, s9, s2
	s_cselect_b32 s9, s7, s9
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s5, s5, s8
	s_add_i32 s6, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s6
	s_cmp_eq_u32 s6, 0
	v_mov_b32_e32 v4, s3
	s_cselect_b32 s6, -1, 0
	v_alignbit_b32 v5, s2, s9, v4
	v_alignbit_b32 v6, s9, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v5
	v_cndmask_b32_e64 v5, v6, s9, s6
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s2, v5, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v6, s8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v7, v6
	v_min_u32_e32 v7, 32, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v9, 23, v7
	v_alignbit_b32 v4, s7, s5, v4
	v_sub_nc_u32_e32 v8, 31, v7
	v_cndmask_b32_e64 v4, v4, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v5, v5, v4, 30
	v_alignbit_b32 v4, v4, s5, 30
	s_lshr_b32 s5, s2, 29
	s_lshl_b32 s5, s5, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, s8, v5
	v_xor_b32_e32 v4, s8, v4
	s_or_b32 s6, s5, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, s6, v9
	v_alignbit_b32 v6, v6, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v4, v5, v4, v8
	v_alignbit_b32 v5, v6, v4, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v8, v5
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, 31, v8
	v_alignbit_b32 v4, v5, v4, v10
	v_lshrrev_b32_e32 v5, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v4, 9, v4
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 23, v7
	v_sub_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v6, 0x3fc90fda, v5
	v_add_nc_u32_e32 v4, 0x33000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3fc90fda, v5, -v6
	v_or_b32_e32 v4, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v5, 0x33a22168, v7
	s_lshr_b32 s5, s2, 30
	s_mov_b32 s2, 0
	s_add_i32 s3, s3, s5
	v_fmac_f32_e32 v5, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v5
	s_branch .LBB0_8
.LBB0_7:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr4
.LBB0_8:                                ; %Flow122
	v_mov_b32_e32 v5, s3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_10
; %bb.9:
	v_rndne_f32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0xbfc90fda, v5, |s16|
	v_fmamk_f32 v4, v5, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v4, v5, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v5, v5
.LBB0_10:                               ; %_ZL3sinf.exit
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_12
; %bb.11:
	s_and_b32 s2, s17, 0x7fffff
	s_lshr_b32 s3, s17, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s5, s2, 0xfe5163ab
	s_mul_i32 s6, s2, 0x3c439041
	s_mul_hi_u32 s7, s2, 0x3c439041
	s_add_u32 s5, s5, s6
	s_addc_u32 s6, 0, s7
	s_mul_i32 s7, s2, 0xdb629599
	s_mul_hi_u32 s8, s2, 0xdb629599
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s2, 0xf534ddc0
	s_mul_hi_u32 s9, s2, 0xf534ddc0
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s2, 0xfc2757d1
	s_mul_hi_u32 s10, s2, 0xfc2757d1
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s2, 0x4e441529
	s_mul_hi_u32 s11, s2, 0x4e441529
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s11, s2, 0xfe5163ab
	s_mul_hi_u32 s12, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s13, s6, s8
	s_cselect_b32 s5, s5, s7
	s_cselect_b32 s6, s11, s6
	s_add_u32 s2, s10, s2
	s_addc_u32 s10, 0, s12
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s11, 0xffffffc0, 0
	s_cselect_b32 s7, s7, s9
	s_cselect_b32 s2, s8, s2
	s_cselect_b32 s8, s9, s10
	s_add_i32 s11, s11, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s11, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s9, s7, s2
	s_cselect_b32 s2, s2, s8
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s8, s5, s13
	s_cselect_b32 s5, s6, s5
	s_add_i32 s3, s3, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s2, s9, s2
	s_cselect_b32 s9, s7, s9
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s5, s5, s8
	s_add_i32 s6, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s6
	s_cmp_eq_u32 s6, 0
	v_mov_b32_e32 v6, s3
	s_cselect_b32 s6, -1, 0
	v_alignbit_b32 v7, s2, s9, v6
	v_alignbit_b32 v8, s9, s7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v7
	v_cndmask_b32_e64 v7, v8, s9, s6
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v8, s2, v7, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v8, s8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v8
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 23, v9
	v_alignbit_b32 v6, s7, s5, v6
	v_sub_nc_u32_e32 v10, 31, v9
	v_cndmask_b32_e64 v6, v6, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v7, v7, v6, 30
	v_alignbit_b32 v6, v6, s5, 30
	s_lshr_b32 s5, s2, 29
	s_lshl_b32 s5, s5, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v7, s8, v7
	v_xor_b32_e32 v6, s8, v6
	s_or_b32 s6, s5, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, s6, v11
	v_alignbit_b32 v8, v8, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v6, v7, v6, v10
	v_alignbit_b32 v7, v8, v6, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v10, v7
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, 31, v10
	v_alignbit_b32 v6, v7, v6, v12
	v_lshrrev_b32_e32 v7, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v6, 9, v6
	v_or_b32_e32 v7, v7, v11
	v_add_nc_u32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v8, 23, v9
	v_sub_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, 0x3fc90fda, v7
	v_add_nc_u32_e32 v6, 0x33000000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3fc90fda, v7, -v8
	v_or_b32_e32 v6, s5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v7, v7, 0x33a22168, v9
	s_lshr_b32 s5, s2, 30
	s_mov_b32 s2, 0
	s_add_i32 s3, s3, s5
	v_fmac_f32_e32 v7, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v8, v7
	s_branch .LBB0_13
.LBB0_12:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr6
.LBB0_13:                               ; %Flow121
	v_mov_b32_e32 v7, s3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_15
; %bb.14:
	v_rndne_f32_e32 v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0xbfc90fda, v7, |s16|
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
.LBB0_15:                               ; %_ZL3cosf.exit71
	s_load_b64 s[2:3], s[0:1], 0x40
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_17
; %bb.16:
	s_and_b32 s4, s17, 0x7fffff
	s_lshr_b32 s5, s17, 23
	s_bitset1_b32 s4, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s6, s4, 0xfe5163ab
	s_mul_i32 s7, s4, 0x3c439041
	s_mul_hi_u32 s8, s4, 0x3c439041
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s4, 0xdb629599
	s_mul_hi_u32 s9, s4, 0xdb629599
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s4, 0xf534ddc0
	s_mul_hi_u32 s10, s4, 0xf534ddc0
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s4, 0xfc2757d1
	s_mul_hi_u32 s11, s4, 0xfc2757d1
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s4, 0x4e441529
	s_mul_hi_u32 s12, s4, 0x4e441529
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s12, s4, 0xfe5163ab
	s_mul_hi_u32 s13, s4, 0xa2f9836e
	s_mul_i32 s4, s4, 0xa2f9836e
	s_cselect_b32 s18, s7, s9
	s_cselect_b32 s6, s6, s8
	s_cselect_b32 s7, s12, s7
	s_add_u32 s4, s11, s4
	s_addc_u32 s11, 0, s13
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s12, 0xffffffc0, 0
	s_cselect_b32 s8, s8, s10
	s_cselect_b32 s4, s9, s4
	s_cselect_b32 s9, s10, s11
	s_add_i32 s12, s12, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s12, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s10, s8, s4
	s_cselect_b32 s4, s4, s9
	s_cselect_b32 s8, s18, s8
	s_cselect_b32 s9, s6, s18
	s_cselect_b32 s6, s7, s6
	s_add_i32 s5, s5, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s4, s10, s4
	s_cselect_b32 s10, s8, s10
	s_cselect_b32 s8, s9, s8
	s_cselect_b32 s6, s6, s9
	s_add_i32 s7, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s7
	s_cmp_eq_u32 s7, 0
	v_mov_b32_e32 v8, s5
	s_cselect_b32 s7, -1, 0
	v_alignbit_b32 v9, s4, s10, v8
	v_alignbit_b32 v10, s10, s8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s5, v9
	v_cndmask_b32_e64 v9, v10, s10, s7
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s4, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v10, s4, v9, 30
	s_bfe_u32 s9, s4, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s5, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v10, s5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v10
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v8, s8, s6, v8
	v_sub_nc_u32_e32 v12, 31, v11
	v_cndmask_b32_e64 v8, v8, s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v8, v8, s6, 30
	v_xor_b32_e32 v9, s5, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v8, s5, v8
	s_lshr_b32 s5, s4, 29
	s_lshr_b32 s4, s4, 30
	s_lshl_b32 s5, s5, 31
	v_alignbit_b32 v10, v10, v9, v12
	v_alignbit_b32 v8, v9, v8, v12
	s_or_b32 s6, s5, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, s6, v13
	s_add_i32 s6, s9, s4
	v_alignbit_b32 v9, v10, v8, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v9
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v12
	v_alignbit_b32 v8, v9, v8, v14
	v_lshrrev_b32_e32 v9, 9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v8, 9, v8
	v_or_b32_e32 v9, v9, v13
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 23, v11
	v_sub_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v9
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3fc90fda, v9, -v10
	v_or_b32_e32 v8, s5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v9, 0x33a22168, v11
	s_mov_b32 s5, 0
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v9
	s_branch .LBB0_18
.LBB0_17:
	s_mov_b32 s5, -1
                                        ; implicit-def: $sgpr6
                                        ; implicit-def: $vgpr8
.LBB0_18:                               ; %Flow120
	s_load_b32 s4, s[0:1], 0x4c
	v_mov_b32_e32 v9, s6
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_20
; %bb.19:
	v_rndne_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0xbfc90fda, v3, |s16|
	v_cvt_i32_f32_e32 v9, v3
	v_fmamk_f32 v8, v3, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v8, v3, 0xa7c234c4, v8
.LBB0_20:                               ; %_ZL3sinf.exit79
	v_dual_mul_f32 v10, v1, v1 :: v_dual_and_b32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_mov_b32 s18, 0xb94c1982
	v_mad_u64_u32 v[12:13], null, s14, s4, v[3:4]
	v_bfe_u32 v0, v0, 10, 10
	v_fmaak_f32 v3, s18, v10, 0x3c0881c4
	v_mul_f32_e32 v11, v4, v4
	s_mov_b32 s19, 0x37d75334
	s_mul_i32 s20, s2, s4
	v_mad_u64_u32 v[13:14], null, s15, s5, v[0:1]
	v_fmaak_f32 v0, v10, v3, 0xbe2aaa9d
	v_fmaak_f32 v3, s18, v11, 0x3c0881c4
	s_load_b128 s[12:15], s[0:1], 0x30
	s_lshr_b32 s2, s20, 1
	s_mul_i32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v0, v10, v0 :: v_dual_fmaak_f32 v3, v11, v3, 0xbe2aaa9d
	v_fmaak_f32 v15, s19, v10, 0xbab64f3b
	v_dual_fmac_f32 v1, v1, v0 :: v_dual_mul_f32 v0, v11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v14, v10, v15, 0x3d2aabf7
	v_dual_fmaak_f32 v15, s19, v11, 0xbab64f3b :: v_dual_fmac_f32 v4, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v14, v10, v14, 0xbf000004
	v_dual_fmaak_f32 v15, v11, v15, 0x3d2aabf7 :: v_dual_and_b32 v0, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v10, v14, 1.0
	v_fmaak_f32 v10, v11, v15, 0xbf000004
	v_lshlrev_b32_e32 v14, 30, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_fma_f32 v5, v11, v10, 1.0
	v_and_b32_e32 v11, 1, v2
	v_lshlrev_b32_e32 v2, 30, v2
	v_and_b32_e32 v10, 0x80000000, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v5, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v2, 0x80000000, v2
	v_xor_b32_e32 v4, s17, v10
	v_cndmask_b32_e64 v1, -v1, v3, vcc_lo
	v_subrev_nc_u32_e32 v3, s2, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v0, v4, v0
	s_lshr_b32 s2, s3, 1
	v_cmp_class_f32_e64 vcc_lo, s16, 0x1f8
	v_xor_b32_e32 v1, v2, v1
	v_subrev_nc_u32_e32 v2, s2, v13
	s_waitcnt lgkmcnt(0)
	s_lshr_b64 s[2:3], s[12:13], 1
	v_xor_b32_e32 v0, s16, v0
	s_clz_i32_u32 s4, s3
	v_cvt_f32_i32_e32 v11, v3
	s_min_u32 s4, s4, 32
	v_cvt_f32_i32_e32 v10, v2
	s_lshl_b64 s[2:3], s[2:3], s4
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_min_u32 s2, s2, 1
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, 0
	v_mul_f32_e32 v0, v0, v10
	v_cvt_f32_u32_e32 v2, s2
	s_sub_i32 s2, 32, s4
	s_load_b256 s[4:11], s[0:1], 0x0
                                        ; implicit-def: $vgpr4_vgpr5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, v1, v11
	v_ldexp_f32 v1, v2, s2
	v_mad_u64_u32 v[2:3], null, s20, v13, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v1
	v_cvt_i32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmp_le_u64_e64 s20, s[12:13], v[0:1]
	v_cmp_gt_u64_e64 s2, s[12:13], v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s12, s2
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_dual_mul_f32 v3, v8, v8 :: v_dual_mul_f32 v12, v6, v6
	s_mov_b32 s3, exec_lo
	v_lshlrev_b32_e32 v14, 30, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_fmaak_f32 v4, s18, v3, 0x3c0881c4 :: v_dual_and_b32 v9, 1, v9
	v_fmaak_f32 v5, s19, v3, 0xbab64f3b
	v_and_b32_e32 v13, 1, v7
	v_fmaak_f32 v15, s18, v12, 0x3c0881c4
	v_and_b32_e32 v14, 0x80000000, v14
	v_fmaak_f32 v4, v3, v4, 0xbe2aaa9d
	v_cmp_eq_u32_e64 s2, 0, v9
	v_lshlrev_b32_e32 v7, 30, v7
	v_fmaak_f32 v15, v12, v15, 0xbe2aaa9d
	v_fmaak_f32 v16, s19, v12, 0xbab64f3b
	v_fmaak_f32 v5, v3, v5, 0x3d2aabf7
	v_mul_f32_e32 v4, v3, v4
	s_lshr_b64 s[18:19], s[14:15], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v16, v12, v16, 0x3d2aabf7
	v_dual_fmaak_f32 v5, v3, v5, 0xbf000004 :: v_dual_fmac_f32 v8, v8, v4
	v_xor_b32_e32 v4, s17, v14
	s_clz_i32_u32 s13, s19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, v12, v16, 0xbf000004
	v_fma_f32 v3, v3, v5, 1.0
	v_mul_f32_e32 v5, v12, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v8, s2
	v_fmac_f32_e32 v6, v6, v5
	v_fma_f32 v5, v12, v14, 1.0
	v_cmp_eq_u32_e64 s2, 0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v4, v3
	v_and_b32_e32 v4, 0x80000000, v7
	v_cndmask_b32_e64 v5, -v6, v5, s2
	s_min_u32 s2, s13, 32
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v3, s16, v3
	s_lshl_b64 s[16:17], s[18:19], s2
	s_sub_i32 s2, 32, s2
	v_xor_b32_e32 v4, v4, v5
	s_min_u32 s13, s16, 1
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
	s_or_b32 s13, s17, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	v_cvt_f32_u32_e32 v5, s13
	v_mul_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v3, v4, v10, -v3
	v_ldexp_f32 v4, v5, s2
	s_and_not1_b32 s2, s20, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	v_cvt_i32_f32_e32 v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_le_u64_e32 vcc_lo, s[14:15], v[4:5]
	s_and_b32 s13, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s20, s2, s13
.LBB0_22:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s12
	v_ashrrev_i32_e32 v3, 31, v2
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $vgpr6_vgpr7
	s_and_saveexec_b32 s2, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_24
; %bb.23:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_mov_b32_e32 v8, 0
	s_mov_b32 s12, 0
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_store_b16 v[6:7], v8, off
.LBB0_24:                               ; %Flow119
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v8, s12
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_26
; %bb.25:
	s_load_b64 s[0:1], s[0:1], 0x20
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v7, v5, s0
	v_mul_lo_u32 v8, v4, s1
	v_mad_u64_u32 v[5:6], null, v4, s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v4, v6, v8, v7
	v_add_co_u32 v6, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v4, vcc_lo
	global_load_u8 v8, v[6:7], off
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v9, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, v10, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off
	global_load_u8 v2, v[2:3], off
	v_add_co_u32 v3, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v2, off offset:1
	global_load_u8 v8, v[0:1], off
.LBB0_26:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v0, 0xffffff00, v8
	global_store_b16 v[6:7], v0, off offset:2
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, .Lfunc_end0-_Z6RotateP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4116
; NumSgprs: 23
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z5ScalePhS_S_S_S_S_mmfmm ; -- Begin function _Z5ScalePhS_S_S_S_S_mmfmm
	.globl	_Z5ScalePhS_S_S_S_S_mmfmm
	.p2align	8
	.type	_Z5ScalePhS_S_S_S_S_mmfmm,@function
_Z5ScalePhS_S_S_S_S_mmfmm:              ; @_Z5ScalePhS_S_S_S_S_mmfmm
; %bb.0:
	s_load_b32 s3, s[0:1], 0x64
	v_and_b32_e32 v1, 0x3ff, v0
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x40
	s_load_b512 s[16:31], s[0:1], 0x0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s3, 0xffff
	s_lshr_b32 s3, s3, 16
	v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
	s_load_b128 s[4:7], s[0:1], 0x48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, v2
	v_add_f32_e32 v1, 0xc4480000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_scale_f32 v2, null, s2, s2, v1
	s_waitcnt lgkmcnt(0)
	s_lshr_b64 s[0:1], s[4:5], 1
	v_rcp_f32_e32 v4, v2
	s_clz_i32_u32 s8, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s8, s8, 32
	s_lshl_b64 s[0:1], s[0:1], s8
	s_sub_i32 s8, 32, s8
	s_min_u32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	s_clz_i32_u32 s1, s31
	s_min_u32 s9, s1, 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v6, vcc_lo, v1, s2, v1
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v2, v5, v6
	v_fmac_f32_e32 v5, v7, v4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f32 v2, -v2, v5, v6
	v_cvt_f32_u32_e32 v6, s0
	s_lshl_b64 s[0:1], s[30:31], s9
	s_min_u32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v2, v2, v4, v5
	v_ldexp_f32 v4, v6, s8
	s_or_b32 s0, s1, s0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v6, v2, s2, v1
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_cvt_f32_u32_e32 v2, s0
	s_sub_i32 s0, 32, s9
	v_add_f32_e32 v0, v6, v4
	s_add_u32 s4, s4, -1
	s_addc_u32 s5, s5, -1
	v_ldexp_f32 v2, v2, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, v1
	v_cvt_i32_f32_e32 v0, v0
	s_mov_b32 s3, exec_lo
	v_fma_f32 v2, v2, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_cvt_i32_f32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u64_e64 s0, s[4:5], v[0:1]
                                        ; implicit-def: $vgpr2_vgpr3
	v_cmpx_gt_u64_e64 s[4:5], v[0:1]
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_add_f32_e32 v2, 0xc4480000, v5
	s_lshr_b64 s[4:5], s[6:7], 1
	s_mov_b32 s1, exec_lo
	s_clz_i32_u32 s8, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_min_u32 s8, s8, 32
	v_div_scale_f32 v3, null, s2, s2, v2
	v_div_scale_f32 v8, vcc_lo, v2, s2, v2
	s_lshl_b64 s[4:5], s[4:5], s8
	v_rcp_f32_e32 v5, v3
	s_min_u32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 s4, s5, s4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v3, v5, 1.0
	v_fmac_f32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v8, v5
	v_fma_f32 v9, -v3, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v5
	v_fma_f32 v3, -v3, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v5, v7
	v_cvt_f32_u32_e32 v5, s4
	s_sub_i32 s4, 32, s8
	v_div_fixup_f32 v7, v3, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v5, s4
	s_add_u32 s4, s6, -1
	s_addc_u32 s5, s7, -1
	s_and_not1_b32 s0, s0, exec_lo
	v_add_f32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v2, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[2:3]
	s_and_b32 s2, vcc_lo, exec_lo
	s_or_b32 s0, s0, s2
.LBB1_2:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
	v_ashrrev_i32_e32 v5, 31, v4
                                        ; implicit-def: $sgpr2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_xor_b32 s0, exec_lo, s3
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_add_co_u32 v8, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s24, v4
	v_mov_b32_e32 v12, 0
	v_add_co_ci_u32_e32 v11, vcc_lo, s25, v5, vcc_lo
	s_mov_b32 s2, 0
	s_and_not1_b32 s1, s1, exec_lo
	global_store_b8 v[8:9], v12, off
	global_store_b8 v[10:11], v12, off
.LBB1_4:                                ; %Flow139
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v8, s2
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_mul_lo_u32 v3, v3, s28
	v_mul_lo_u32 v10, v2, s29
	v_mad_u64_u32 v[8:9], null, v2, s28, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v11, v9, v10, v3
	v_add_co_u32 v2, vcc_lo, s16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v11, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, v2, s28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, s29, v3, vcc_lo
	s_clause 0x1
	global_load_u16 v9, v[9:10], off
	global_load_u16 v2, v[2:3], off
	v_floor_f32_e32 v3, v6
	v_sub_f32_e32 v12, v6, v3
	v_floor_f32_e32 v6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v15, v7, v6
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte1_e32 v3, v9
	v_sub_f32_e32 v13, 1.0, v12
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte1_e32 v10, v2
	v_cvt_f32_ubyte0_e32 v9, v9
	v_cvt_f32_ubyte0_e32 v6, v2
	v_mul_f32_e32 v14, v12, v3
	v_add_co_u32 v2, vcc_lo, s22, v4
	v_mul_f32_e32 v7, v12, v10
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v13, v9
	v_dual_sub_f32 v16, 1.0, v15 :: v_dual_fmac_f32 v7, v13, v6
	v_add_co_u32 v6, vcc_lo, s18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v9, v15, v14
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v11, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, v16, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v10, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v14, v9
	v_add_co_u32 v9, vcc_lo, v6, s28
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s29, v7, vcc_lo
	global_store_b8 v[2:3], v14, off
	s_clause 0x1
	global_load_u16 v2, v[9:10], off
	global_load_u16 v3, v[6:7], off
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte1_e32 v6, v2
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte1_e32 v7, v3
	v_cvt_f32_ubyte0_e32 v2, v2
	v_cvt_f32_ubyte0_e32 v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v12, v7
	v_dual_mul_f32 v6, v12, v6 :: v_dual_fmac_f32 v7, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v6, v13, v2
	v_add_co_u32 v2, vcc_lo, s24, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v5, vcc_lo
	v_mul_f32_e32 v6, v15, v6
	v_add_co_u32 v8, vcc_lo, s20, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v6, v16, v7
	v_add_co_u32 v0, vcc_lo, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_cvt_i32_f32_e32 v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v0, s28
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v1, vcc_lo
	global_store_b8 v[2:3], v8, off
	s_clause 0x1
	global_load_u16 v2, v[6:7], off
	global_load_u16 v0, v[0:1], off
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte1_e32 v1, v2
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte1_e32 v3, v0
	v_cvt_f32_ubyte0_e32 v2, v2
	v_cvt_f32_ubyte0_e32 v0, v0
	v_mul_f32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v13, v2
	v_mul_f32_e32 v3, v12, v3
	v_dual_fmac_f32 v3, v13, v0 :: v_dual_mul_f32 v0, v15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v16, v3
	v_cvt_i32_f32_e32 v8, v0
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v0, vcc_lo, s26, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s27, v5, vcc_lo
	global_store_b8 v[0:1], v8, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5ScalePhS_S_S_S_S_mmfmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5ScalePhS_S_S_S_S_mmfmm, .Lfunc_end1-_Z5ScalePhS_S_S_S_S_mmfmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1176
; NumSgprs: 34
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
