#include "cuda.h"
typedef  long long int64;

__global__ void ReceiveFun(double *out, const double*vx, const double*vy, 
  const double*sigmaxx, const double*sigmayy, const double*sigmaxy, int64 nt,
  const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, int64 NX, int64 NY){
  int i = blockIdx.x*blockDim.x + threadIdx.x;
  if (i>=nrcv) return;

  int idx = (rcvi[i]-1)*(NY+2) + rcvj[i]-1;
  switch (rcvtype[i])
  {
    case 0:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = vx[k*(NX+2)*(NY+2)+idx];
      break;

    case 1:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = vy[k*(NX+2)*(NY+2)+idx];
      break;

      case 2:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = sigmaxx[k*(NX+2)*(NY+2)+idx];
      break;

      case 3:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = sigmayy[k*(NX+2)*(NY+2)+idx];
      break;

      case 4:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = sigmaxy[k*(NX+2)*(NY+2)+idx];
      break;
    
    default:
      break;
  }

}

void forwardGPU(double *out, const double*vx, const double*vy, 
      const double*sigmaxx, const double*sigmayy, const double*sigmaxy, int64 nt,
      const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, const int64* nx, const int64* ny){
    long long NX, NY;
    cudaMemcpy(&NX, nx, sizeof(long long), cudaMemcpyDeviceToHost);
    cudaMemcpy(&NY, ny, sizeof(long long), cudaMemcpyDeviceToHost);
    cudaDeviceSynchronize();
    ReceiveFun<<<(nrcv+255)/256, 256>>>(out, vx, vy, sigmaxx, sigmayy, sigmaxy, nt,
      rcvi, rcvj, rcvtype, nrcv, NX, NY);
}


__global__ void Zero(const long long size, double* out) {
  int i = blockIdx.x*blockDim.x + threadIdx.x;
  if(i<size) out[i] = 0.0;
}

__global__ void ReceiveGrad(
  double*d_vx, double*d_vy, 
    double*d_sigmaxx, double*d_sigmayy, double*d_sigmaxy, const double *d_out, 
    int64 nt, const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, int64 NX, int64 NY) {
  int i = blockIdx.x*blockDim.x + threadIdx.x;
  if(i>=nrcv) return;
  int idx = (rcvi[i]-1)*(NY+2) + rcvj[i]-1;
  switch (rcvtype[i])
  {
    case 0:
      for(int k=0;k<nt;k++)
        d_vx[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;

    case 1:
      for(int k=0;k<nt;k++){
        // printf("Top gradients: %f\n", d_out[nt*i+k]);
        d_vy[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      }
        
      break;

      case 2:
      for(int k=0;k<nt;k++)
        d_sigmaxx[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;

      case 3:
      for(int k=0;k<nt;k++)
        d_sigmayy[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;

      case 4:
      for(int k=0;k<nt;k++)
        d_sigmaxy[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;
    
    default:
      break;
  }
}

void backwardGPU(
    double*d_vx, double*d_vy, 
    double*d_sigmaxx, double*d_sigmayy, double*d_sigmaxy, const double *d_out, 
    int64 nt, const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, const int64* nx, const int64* ny){
  long long NX, NY;
  cudaMemcpy(&NX, nx, sizeof(long long), cudaMemcpyDeviceToHost);
  cudaMemcpy(&NY, ny, sizeof(long long), cudaMemcpyDeviceToHost);
  cudaDeviceSynchronize();
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_vx);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_vy);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_sigmaxx);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_sigmayy);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_sigmaxy);
  ReceiveGrad<<<(nrcv+255)/256, 256>>>(d_vx, d_vy, d_sigmaxx, d_sigmayy, d_sigmaxy,
        d_out, nt, rcvi, rcvj, rcvtype, nrcv, NX, NY);
}
	.file	"tmpxft_0028f872_00000000-6_GetReceive.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.type	_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, @function
_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	280(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	288(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	296(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, .-_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.globl	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.type	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, @function
_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.cfi_endproc
.LFE2035:
	.size	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, .-_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.globl	_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_
	.type	_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_, @function
_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%r8, 40(%rsp)
	movq	208(%rsp), %r15
	movq	%rdi, 8(%rsp)
	movq	192(%rsp), %r13
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	movq	200(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	movl	$8, %edx
	movq	168(%rsp), %r14
	movq	%rcx, 32(%rsp)
	movl	$2, %ecx
	movq	176(%rsp), %rbx
	movq	184(%rsp), %rbp
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	cudaMemcpy@PLT
	leaq	56(%rsp), %rdi
	movl	$2, %ecx
	movq	%r15, %rsi
	movl	$8, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movl	$256, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leaq	255(%r13), %rax
	cqto
	idivq	%rcx
	movl	$16777217, %edx
	movl	$1, %ecx
	salq	$8, %rdx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	%rax
	.cfi_def_cfa_offset 168
	movq	%r12, %r9
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	pushq	64(%rsp)
	.cfi_def_cfa_offset 184
	pushq	%r13
	.cfi_def_cfa_offset 192
	pushq	%rbp
	.cfi_def_cfa_offset 200
	pushq	%rbx
	.cfi_def_cfa_offset 208
	pushq	%r14
	.cfi_def_cfa_offset 216
	pushq	216(%rsp)
	.cfi_def_cfa_offset 224
	movq	104(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z58__device_stub__Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxxPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	addq	$64, %rsp
	.cfi_def_cfa_offset 160
.L8:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_, .-_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_
	.globl	_Z24__device_stub__Z4ZeroxPdxPd
	.type	_Z24__device_stub__Z4ZeroxPdxPd, @function
_Z24__device_stub__Z4ZeroxPdxPd:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z4ZeroxPd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z24__device_stub__Z4ZeroxPdxPd, .-_Z24__device_stub__Z4ZeroxPdxPd
	.globl	_Z4ZeroxPd
	.type	_Z4ZeroxPd, @function
_Z4ZeroxPd:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z4ZeroxPdxPd
	.cfi_endproc
.LFE2037:
	.size	_Z4ZeroxPd, .-_Z4ZeroxPd
	.globl	_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx
	.type	_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx, @function
_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	280(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	288(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	296(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L17:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx, .-_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx
	.globl	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.type	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, @function
_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx
	.cfi_endproc
.LFE2039:
	.size	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, .-_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.globl	_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_
	.type	_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_, @function
_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%r8, 40(%rsp)
	movq	208(%rsp), %r15
	movq	%rdi, 8(%rsp)
	leaq	48(%rsp), %rdi
	movq	160(%rsp), %rbx
	movq	%rsi, 16(%rsp)
	movq	200(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	movl	$8, %edx
	movq	168(%rsp), %rbp
	movq	%rcx, 32(%rsp)
	movl	$2, %ecx
	movq	176(%rsp), %r13
	movq	184(%rsp), %r14
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	cudaMemcpy@PLT
	leaq	56(%rsp), %rdi
	movl	$2, %ecx
	movq	%r15, %rsi
	movl	$8, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	56(%rsp), %rdx
	movl	$256, %esi
	movl	$16777217, %ecx
	movl	$1, 84(%rsp)
	addq	$2, %rax
	salq	$8, %rcx
	imulq	%rbx, %rax
	addq	$2, %rdx
	movq	%rcx, 76(%rsp)
	imulq	%rdx, %rax
	addq	$255, %rax
	cqto
	idivq	%rsi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	48(%rsp), %rax
	movq	8(%rsp), %rsi
	leaq	2(%rax), %rdi
	movq	56(%rsp), %rax
	imulq	%rbx, %rdi
	addq	$2, %rax
	imulq	%rax, %rdi
	call	_Z24__device_stub__Z4ZeroxPdxPd
.L23:
	movq	48(%rsp), %rax
	movq	56(%rsp), %rsi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16777217, %ecx
	movl	$1, 84(%rsp)
	addq	$2, %rax
	leaq	2(%rsi), %rdx
	movl	$256, %esi
	salq	$8, %rcx
	imulq	%rbx, %rax
	movq	%rcx, 76(%rsp)
	imulq	%rdx, %rax
	addq	$255, %rax
	cqto
	idivq	%rsi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	48(%rsp), %rax
	movq	16(%rsp), %rsi
	leaq	2(%rax), %rdi
	movq	56(%rsp), %rax
	imulq	%rbx, %rdi
	addq	$2, %rax
	imulq	%rax, %rdi
	call	_Z24__device_stub__Z4ZeroxPdxPd
.L24:
	movq	48(%rsp), %rax
	movq	56(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$256, %esi
	movl	$16777217, %ecx
	movl	$1, 84(%rsp)
	addq	$2, %rax
	addq	$2, %rdx
	salq	$8, %rcx
	imulq	%rbx, %rax
	movq	%rcx, 76(%rsp)
	imulq	%rdx, %rax
	addq	$255, %rax
	cqto
	idivq	%rsi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	48(%rsp), %rax
	movq	24(%rsp), %rsi
	leaq	2(%rax), %rdi
	movq	56(%rsp), %rax
	imulq	%rbx, %rdi
	addq	$2, %rax
	imulq	%rax, %rdi
	call	_Z24__device_stub__Z4ZeroxPdxPd
.L25:
	movq	48(%rsp), %rax
	movq	56(%rsp), %rsi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16777217, %ecx
	movl	$1, 84(%rsp)
	addq	$2, %rax
	leaq	2(%rsi), %rdx
	movl	$256, %esi
	salq	$8, %rcx
	imulq	%rbx, %rax
	movq	%rcx, 76(%rsp)
	imulq	%rdx, %rax
	addq	$255, %rax
	cqto
	idivq	%rsi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	48(%rsp), %rax
	movq	32(%rsp), %rsi
	leaq	2(%rax), %rdi
	movq	56(%rsp), %rax
	imulq	%rbx, %rdi
	addq	$2, %rax
	imulq	%rax, %rdi
	call	_Z24__device_stub__Z4ZeroxPdxPd
.L26:
	movq	48(%rsp), %rax
	movq	56(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$256, %esi
	movl	$16777217, %ecx
	movl	$1, 84(%rsp)
	addq	$2, %rax
	addq	$2, %rdx
	salq	$8, %rcx
	imulq	%rbx, %rax
	movq	%rcx, 76(%rsp)
	imulq	%rdx, %rax
	addq	$255, %rax
	cqto
	idivq	%rsi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	48(%rsp), %rax
	movq	40(%rsp), %rsi
	leaq	2(%rax), %rdi
	movq	56(%rsp), %rax
	imulq	%rbx, %rdi
	addq	$2, %rax
	imulq	%rax, %rdi
	call	_Z24__device_stub__Z4ZeroxPdxPd
.L27:
	movl	$256, %esi
	movl	$16777217, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	192(%rsp), %rax
	salq	$8, %rcx
	movl	$1, 84(%rsp)
	movq	%rcx, 76(%rsp)
	addq	$255, %rax
	cqto
	idivq	%rsi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	%rax
	.cfi_def_cfa_offset 168
	movq	%r12, %r9
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	pushq	64(%rsp)
	.cfi_def_cfa_offset 184
	pushq	216(%rsp)
	.cfi_def_cfa_offset 192
	pushq	%r14
	.cfi_def_cfa_offset 200
	pushq	%r13
	.cfi_def_cfa_offset 208
	pushq	%rbp
	.cfi_def_cfa_offset 216
	pushq	%rbx
	.cfi_def_cfa_offset 224
	movq	104(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z55__device_stub__Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxxPdS_S_S_S_PKdxPKxS3_S3_xxx
	addq	$64, %rsp
	.cfi_def_cfa_offset 160
.L22:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_, .-_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx"
.LC1:
	.string	"_Z4ZeroxPd"
.LC2:
	.string	"_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4ZeroxPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2041:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"
typedef  long long int64;

__global__ void ReceiveFun(double *out, const double*vx, const double*vy, 
  const double*sigmaxx, const double*sigmayy, const double*sigmaxy, int64 nt,
  const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, int64 NX, int64 NY){
  int i = blockIdx.x*blockDim.x + threadIdx.x;
  if (i>=nrcv) return;

  int idx = (rcvi[i]-1)*(NY+2) + rcvj[i]-1;
  switch (rcvtype[i])
  {
    case 0:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = vx[k*(NX+2)*(NY+2)+idx];
      break;

    case 1:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = vy[k*(NX+2)*(NY+2)+idx];
      break;

      case 2:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = sigmaxx[k*(NX+2)*(NY+2)+idx];
      break;

      case 3:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = sigmayy[k*(NX+2)*(NY+2)+idx];
      break;

      case 4:
      for(int k=0;k<nt;k++)
        out[nt*i+k] = sigmaxy[k*(NX+2)*(NY+2)+idx];
      break;
    
    default:
      break;
  }

}

void forwardGPU(double *out, const double*vx, const double*vy, 
      const double*sigmaxx, const double*sigmayy, const double*sigmaxy, int64 nt,
      const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, const int64* nx, const int64* ny){
    long long NX, NY;
    hipMemcpy(&NX, nx, sizeof(long long), hipMemcpyDeviceToHost);
    hipMemcpy(&NY, ny, sizeof(long long), hipMemcpyDeviceToHost);
    hipDeviceSynchronize();
    ReceiveFun<<<(nrcv+255)/256, 256>>>(out, vx, vy, sigmaxx, sigmayy, sigmaxy, nt,
      rcvi, rcvj, rcvtype, nrcv, NX, NY);
}


__global__ void Zero(const long long size, double* out) {
  int i = blockIdx.x*blockDim.x + threadIdx.x;
  if(i<size) out[i] = 0.0;
}

__global__ void ReceiveGrad(
  double*d_vx, double*d_vy, 
    double*d_sigmaxx, double*d_sigmayy, double*d_sigmaxy, const double *d_out, 
    int64 nt, const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, int64 NX, int64 NY) {
  int i = blockIdx.x*blockDim.x + threadIdx.x;
  if(i>=nrcv) return;
  int idx = (rcvi[i]-1)*(NY+2) + rcvj[i]-1;
  switch (rcvtype[i])
  {
    case 0:
      for(int k=0;k<nt;k++)
        d_vx[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;

    case 1:
      for(int k=0;k<nt;k++){
        // printf("Top gradients: %f\n", d_out[nt*i+k]);
        d_vy[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      }
        
      break;

      case 2:
      for(int k=0;k<nt;k++)
        d_sigmaxx[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;

      case 3:
      for(int k=0;k<nt;k++)
        d_sigmayy[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;

      case 4:
      for(int k=0;k<nt;k++)
        d_sigmaxy[k*(NX+2)*(NY+2)+idx] += d_out[nt*i+k];
      break;
    
    default:
      break;
  }
}

void backwardGPU(
    double*d_vx, double*d_vy, 
    double*d_sigmaxx, double*d_sigmayy, double*d_sigmaxy, const double *d_out, 
    int64 nt, const int64 *rcvi, const int64 *rcvj, const int64 *rcvtype, int64 nrcv, const int64* nx, const int64* ny){
  long long NX, NY;
  hipMemcpy(&NX, nx, sizeof(long long), hipMemcpyDeviceToHost);
  hipMemcpy(&NY, ny, sizeof(long long), hipMemcpyDeviceToHost);
  hipDeviceSynchronize();
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_vx);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_vy);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_sigmaxx);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_sigmayy);
  Zero<<<(nt*(NX+2)*(NY+2)+255)/256, 256>>>(nt*(NX+2)*(NY+2), d_sigmaxy);
  ReceiveGrad<<<(nrcv+255)/256, 256>>>(d_vx, d_vy, d_sigmaxx, d_sigmayy, d_sigmaxy,
        d_out, nt, rcvi, rcvj, rcvtype, nrcv, NX, NY);
}
	.text
	.file	"GetReceive.hip"
	.globl	_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx # -- Begin function _Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.type	_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx,@function
_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx: # @_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, .Lfunc_end0-_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.cfi_endproc
                                        # -- End function
	.globl	_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_ # -- Begin function _Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_
	.type	_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_,@function
_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_: # @_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movq	%r8, 8(%rsp)                    # 8-byte Spill
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	128(%rsp), %r14
	movq	144(%rsp), %rbx
	movq	136(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$8, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rdi
	movl	$8, %edx
	movq	%rbx, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	leaq	255(%r14), %rax
	leaq	510(%r14), %rcx
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	shrq	$8, %rcx
	movl	%ecx, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	16(%rsp), %r8                   # 8-byte Reload
	movq	24(%rsp), %r9                   # 8-byte Reload
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB1_2:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_, .Lfunc_end1-_Z10forwardGPUPdPKdS1_S1_S1_S1_xPKxS3_S3_xS3_S3_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__ZeroxPd      # -- Begin function _Z19__device_stub__ZeroxPd
	.type	_Z19__device_stub__ZeroxPd,@function
_Z19__device_stub__ZeroxPd:             # @_Z19__device_stub__ZeroxPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4ZeroxPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z19__device_stub__ZeroxPd, .Lfunc_end2-_Z19__device_stub__ZeroxPd
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx # -- Begin function _Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.type	_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx,@function
_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx: # @_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, .Lfunc_end3-_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.cfi_endproc
                                        # -- End function
	.globl	_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_ # -- Begin function _Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_
	.type	_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_,@function
_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_: # @_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 48(%rsp)                   # 8-byte Spill
	movq	%r8, 40(%rsp)                   # 8-byte Spill
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbp
	movq	112(%rsp), %r12
	movq	160(%rsp), %rbx
	movq	152(%rsp), %rsi
	movabsq	$4294967296, %r13               # imm = 0x100000000
	leaq	8(%rsp), %r14
	movl	$8, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rsp, %r15
	movl	$8, %edx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	(%r14), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%r15), %rcx
	addq	$2, %rcx
	imulq	%rax, %rcx
	leaq	255(%rcx), %rax
	addq	$510, %rcx                      # imm = 0x1FE
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	shrq	$8, %rcx
	movl	%ecx, %edi
	btsq	$32, %rdi
	leaq	256(%r13), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rdi
	addq	$2, %rdi
	imulq	%rax, %rdi
	movq	%rbp, %rsi
	callq	_Z19__device_stub__ZeroxPd
.LBB4_2:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rcx
	addq	$2, %rcx
	imulq	%rax, %rcx
	leaq	255(%rcx), %rax
	addq	$510, %rcx                      # imm = 0x1FE
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	shrq	$8, %rcx
	movl	%ecx, %edi
	orq	%r13, %rdi
	leaq	256(%r13), %rbx
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rdi
	addq	$2, %rdi
	imulq	%rax, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	callq	_Z19__device_stub__ZeroxPd
.LBB4_4:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rcx
	addq	$2, %rcx
	imulq	%rax, %rcx
	leaq	255(%rcx), %rax
	addq	$510, %rcx                      # imm = 0x1FE
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	shrq	$8, %rcx
	movl	%ecx, %edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rdi
	addq	$2, %rdi
	imulq	%rax, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	callq	_Z19__device_stub__ZeroxPd
.LBB4_6:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rcx
	addq	$2, %rcx
	imulq	%rax, %rcx
	leaq	255(%rcx), %rax
	addq	$510, %rcx                      # imm = 0x1FE
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	shrq	$8, %rcx
	movl	%ecx, %edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rdi
	addq	$2, %rdi
	imulq	%rax, %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	callq	_Z19__device_stub__ZeroxPd
.LBB4_8:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rcx
	addq	$2, %rcx
	imulq	%rax, %rcx
	leaq	255(%rcx), %rax
	addq	$510, %rcx                      # imm = 0x1FE
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	movq	144(%rsp), %r14
	shrq	$8, %rcx
	movl	%ecx, %edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.9:
	movq	8(%rsp), %rax
	addq	$2, %rax
	imulq	%r12, %rax
	movq	(%rsp), %rdi
	addq	$2, %rdi
	imulq	%rax, %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	callq	_Z19__device_stub__ZeroxPd
.LBB4_10:
	leaq	255(%r14), %rax
	leaq	510(%r14), %rcx
	testq	%rax, %rax
	cmovnsq	%rax, %rcx
	shrq	$8, %rcx
	movl	%ecx, %edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_12
# %bb.11:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%rbp, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movq	40(%rsp), %rcx                  # 8-byte Reload
	movq	48(%rsp), %r8                   # 8-byte Reload
	movq	56(%rsp), %r9                   # 8-byte Reload
	pushq	8(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB4_12:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_, .Lfunc_end4-_Z11backwardGPUPdS_S_S_S_PKdxPKxS3_S3_xS3_S3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4ZeroxPd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx,@object # @_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.section	.rodata,"a",@progbits
	.globl	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.p2align	3, 0x0
_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx:
	.quad	_Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.size	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, 8

	.type	_Z4ZeroxPd,@object              # @_Z4ZeroxPd
	.globl	_Z4ZeroxPd
	.p2align	3, 0x0
_Z4ZeroxPd:
	.quad	_Z19__device_stub__ZeroxPd
	.size	_Z4ZeroxPd, 8

	.type	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx,@object # @_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.globl	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.p2align	3, 0x0
_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx:
	.quad	_Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.size	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx"
	.size	.L__unnamed_1, 45

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z4ZeroxPd"
	.size	.L__unnamed_2, 11

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx"
	.size	.L__unnamed_3, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.addrsig_sym _Z19__device_stub__ZeroxPd
	.addrsig_sym _Z26__device_stub__ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.addrsig_sym _Z4ZeroxPd
	.addrsig_sym _Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx ; -- Begin function _Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.globl	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
	.p2align	8
	.type	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx,@function
_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx: ; @_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x74
	s_load_b256 s[20:27], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i64_e64 s[24:25], v[1:2]
	s_cbranch_execz .LBB0_29
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x60
	s_load_b512 s[4:19], s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_add_u32 s1, s2, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v4, vcc_lo
	s_addc_u32 s18, s3, 0
	global_load_b32 v0, v[5:6], off
	v_add_co_u32 v5, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s23, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[5:6], off
	global_load_b32 v5, v[7:8], off
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v0, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s1
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v0, v5, -1
	v_cmpx_lt_i64_e32 1, v[3:4]
	s_xor_b32 s19, exec_lo, s0
	s_cbranch_execz .LBB0_19
; %bb.2:                                ; %NodeBlock193
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[3:4]
	s_xor_b32 s20, exec_lo, s0
	s_cbranch_execz .LBB0_14
; %bb.3:                                ; %NodeBlock191
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 3, v[3:4]
	s_xor_b32 s21, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.4:                                ; %LeafBlock189
	s_mov_b32 s22, exec_lo
	v_cmpx_eq_u64_e32 4, v[3:4]
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.preheader94
	v_cmp_lt_i64_e64 s0, s[16:17], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_8
; %bb.6:                                ; %.lr.ph
	v_mul_lo_u32 v4, v2, s16
	v_mul_lo_u32 v5, v1, s17
	v_mad_u64_u32 v[2:3], null, v1, s16, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s0, s26, 2
	s_addc_u32 s2, s27, 0
	s_mul_hi_u32 s3, s1, s0
	s_mul_i32 s2, s1, s2
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, v3, v5, v4
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s18, s0
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	s_mul_i32 s2, s1, s0
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_lshl_b64 s[2:3], s[2:3], 3
	s_mov_b64 s[14:15], 0
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	v_add_co_u32 v0, vcc_lo, v0, s2
	v_cmp_lt_i64_e64 s0, s[14:15], s[16:17]
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, s0, v2, 8
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_cbranch_vccnz .LBB0_7
.LBB0_8:                                ; %Flow198
	s_or_b32 exec_lo, exec_lo, s22
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_9:                                ; %Flow201
	s_and_not1_saveexec_b32 s14, s21
	s_cbranch_execz .LBB0_13
; %bb.10:                               ; %.preheader92
	v_cmp_lt_i64_e64 s0, s[16:17], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_13
; %bb.11:                               ; %.lr.ph98
	v_mul_lo_u32 v4, v2, s16
	v_mul_lo_u32 v5, v1, s17
	v_mad_u64_u32 v[2:3], null, v1, s16, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s0, s26, 2
	s_addc_u32 s2, s27, 0
	s_mul_hi_u32 s3, s1, s0
	s_mul_i32 s2, s1, s2
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, v3, v5, v4
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s18, s0
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	s_mul_i32 s2, s1, s0
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_lshl_b64 s[2:3], s[2:3], 3
	s_mov_b64 s[12:13], 0
.LBB0_12:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	v_add_co_u32 v0, vcc_lo, v0, s2
	v_cmp_ge_i64_e64 s0, s[12:13], s[16:17]
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, s0, v2, 8
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_cbranch_vccz .LBB0_12
.LBB0_13:                               ; %Flow202
	s_or_b32 exec_lo, exec_lo, s14
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_14:                               ; %Flow205
	s_and_not1_saveexec_b32 s12, s20
	s_cbranch_execz .LBB0_18
; %bb.15:                               ; %.preheader90
	v_cmp_lt_i64_e64 s0, s[16:17], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_18
; %bb.16:                               ; %.lr.ph102
	v_mul_lo_u32 v4, v2, s16
	v_mul_lo_u32 v5, v1, s17
	v_mad_u64_u32 v[2:3], null, v1, s16, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s0, s26, 2
	s_addc_u32 s2, s27, 0
	s_mul_hi_u32 s3, s1, s0
	s_mul_i32 s2, s1, s2
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, v3, v5, v4
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s18, s0
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_mul_i32 s2, s1, s0
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_lshl_b64 s[2:3], s[2:3], 3
	s_mov_b64 s[10:11], 0
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	v_add_co_u32 v0, vcc_lo, v0, s2
	v_cmp_ge_i64_e64 s0, s[10:11], s[16:17]
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, s0, v2, 8
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_cbranch_vccz .LBB0_17
.LBB0_18:                               ; %Flow206
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_19:                               ; %Flow214
	s_and_not1_saveexec_b32 s0, s19
	s_cbranch_execz .LBB0_29
; %bb.20:                               ; %NodeBlock
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 0, v[3:4]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.21:                               ; %.preheader88
	v_cmp_lt_i64_e64 s0, s[16:17], 1
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_24
; %bb.22:                               ; %.lr.ph106
	v_mul_lo_u32 v4, v2, s16
	v_mul_lo_u32 v5, v1, s17
	v_mad_u64_u32 v[2:3], null, v1, s16, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s0, s26, 2
	s_addc_u32 s2, s27, 0
	s_mul_hi_u32 s3, s1, s0
	s_mul_i32 s2, s1, s2
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, v3, v5, v4
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s18, s0
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v5, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v1, vcc_lo
	s_mul_i32 s2, s1, s0
	v_add_co_u32 v7, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
	s_lshl_b64 s[2:3], s[2:3], 3
	s_mov_b64 s[8:9], 0
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_23:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[0:1], v[5:6], off
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	v_add_co_u32 v5, vcc_lo, v5, s2
	v_cmp_ge_i64_e64 s0, s[8:9], s[16:17]
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[0:1], off
	v_add_co_u32 v7, s0, v7, 8
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1_vgpr2
	s_cbranch_vccz .LBB0_23
.LBB0_24:                               ; %Flow212
	s_and_not1_saveexec_b32 s0, s10
	s_cbranch_execz .LBB0_29
; %bb.25:                               ; %LeafBlock
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_29
; %bb.26:                               ; %.preheader
	v_cmp_lt_i64_e64 s0, s[16:17], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_29
; %bb.27:                               ; %.lr.ph110
	v_mul_lo_u32 v4, v2, s16
	v_mul_lo_u32 v5, v1, s17
	v_mad_u64_u32 v[2:3], null, v1, s16, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s0, s26, 2
	s_addc_u32 s2, s27, 0
	s_mul_hi_u32 s3, s1, s0
	s_mul_i32 s2, s1, s2
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, v3, v5, v4
	s_add_i32 s2, s3, s2
	s_mul_i32 s18, s18, s0
	s_add_i32 s3, s2, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_mul_i32 s2, s1, s0
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_lshl_b64 s[2:3], s[2:3], 3
	s_mov_b64 s[4:5], 0
.LBB0_28:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_add_co_u32 v0, vcc_lo, v0, s2
	v_cmp_ge_i64_e64 s0, s[4:5], s[16:17]
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, s0, v2, 8
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_cbranch_vccz .LBB0_28
.LBB0_29:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 360
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx, .Lfunc_end0-_Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1468
; NumSgprs: 30
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4ZeroxPd              ; -- Begin function _Z4ZeroxPd
	.globl	_Z4ZeroxPd
	.p2align	8
	.type	_Z4ZeroxPd,@function
_Z4ZeroxPd:                             ; @_Z4ZeroxPd
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v3, v2
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4ZeroxPd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z4ZeroxPd, .Lfunc_end1-_Z4ZeroxPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 120
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx ; -- Begin function _Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.globl	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
	.p2align	8
	.type	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx,@function
_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx: ; @_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x74
	s_load_b256 s[16:23], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i64_e64 s[20:21], v[1:2]
	s_cbranch_execz .LBB2_29
; %bb.1:
	s_clause 0x1
	s_load_b64 s[20:21], s[0:1], 0x60
	s_load_b512 s[0:15], s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v4, vcc_lo
	s_mov_b32 s14, exec_lo
	global_load_b32 v0, v[5:6], off
	v_add_co_u32 v5, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v4, vcc_lo
	global_load_b64 v[3:4], v[5:6], off
	global_load_b32 v5, v[7:8], off
	s_add_u32 s16, s20, 2
	s_addc_u32 s17, s21, 0
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v0, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s16
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v0, v5, -1
	v_cmpx_lt_i64_e32 1, v[3:4]
	s_xor_b32 s18, exec_lo, s14
	s_cbranch_execz .LBB2_19
; %bb.2:                                ; %NodeBlock193
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i64_e32 2, v[3:4]
	s_xor_b32 s19, exec_lo, s14
	s_cbranch_execz .LBB2_14
; %bb.3:                                ; %NodeBlock191
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i64_e32 3, v[3:4]
	s_xor_b32 s20, exec_lo, s14
	s_cbranch_execz .LBB2_9
; %bb.4:                                ; %LeafBlock189
	s_mov_b32 s21, exec_lo
	v_cmpx_eq_u64_e32 4, v[3:4]
	s_cbranch_execz .LBB2_8
; %bb.5:                                ; %.preheader94
	v_cmp_lt_i64_e64 s14, s[12:13], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB2_8
; %bb.6:                                ; %.lr.ph
	v_mul_lo_u32 v4, v2, s12
	v_mul_lo_u32 v5, v1, s13
	v_mad_u64_u32 v[2:3], null, v1, s12, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s14, s22, 2
	s_addc_u32 s15, s23, 0
	s_mul_hi_u32 s24, s16, s14
	s_mul_i32 s15, s16, s15
	s_mul_i32 s25, s17, s14
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v3, v3, v5, v4
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	s_add_i32 s15, s24, s15
	s_mul_i32 s14, s16, s14
	s_add_i32 s15, s15, s25
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
	s_lshl_b64 s[8:9], s[14:15], 3
	s_mov_b64 s[14:15], 0
.LBB2_7:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_cmp_lt_i64_e64 s24, s[14:15], s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB2_7
.LBB2_8:                                ; %Flow198
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr0
.LBB2_9:                                ; %Flow201
	s_and_not1_saveexec_b32 s14, s20
	s_cbranch_execz .LBB2_13
; %bb.10:                               ; %.preheader92
	v_cmp_lt_i64_e64 s8, s[12:13], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB2_13
; %bb.11:                               ; %.lr.ph98
	v_mul_lo_u32 v4, v2, s12
	v_mul_lo_u32 v5, v1, s13
	v_mad_u64_u32 v[2:3], null, v1, s12, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s8, s22, 2
	s_addc_u32 s9, s23, 0
	s_mul_hi_u32 s15, s16, s8
	s_mul_i32 s9, s16, s9
	s_mul_i32 s20, s17, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v3, v3, v5, v4
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	s_add_i32 s9, s15, s9
	s_mul_i32 s8, s16, s8
	s_add_i32 s9, s9, s20
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	s_lshl_b64 s[6:7], s[8:9], 3
	s_mov_b64 s[8:9], 0
.LBB2_12:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_cmp_ge_i64_e64 s15, s[8:9], s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccz .LBB2_12
.LBB2_13:                               ; %Flow202
	s_or_b32 exec_lo, exec_lo, s14
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr0
.LBB2_14:                               ; %Flow205
	s_and_not1_saveexec_b32 s8, s19
	s_cbranch_execz .LBB2_18
; %bb.15:                               ; %.preheader90
	v_cmp_lt_i64_e64 s6, s[12:13], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB2_18
; %bb.16:                               ; %.lr.ph102
	v_mul_lo_u32 v4, v2, s12
	v_mul_lo_u32 v5, v1, s13
	v_mad_u64_u32 v[2:3], null, v1, s12, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s6, s22, 2
	s_addc_u32 s7, s23, 0
	s_mul_hi_u32 s9, s16, s6
	s_mul_i32 s7, s16, s7
	s_mul_i32 s14, s17, s6
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v3, v3, v5, v4
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	s_add_i32 s7, s9, s7
	s_mul_i32 s6, s16, s6
	s_add_i32 s7, s7, s14
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
	s_lshl_b64 s[4:5], s[6:7], 3
	s_mov_b64 s[6:7], 0
.LBB2_17:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_cmp_ge_i64_e64 s9, s[6:7], s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccz .LBB2_17
.LBB2_18:                               ; %Flow206
	s_or_b32 exec_lo, exec_lo, s8
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr0
.LBB2_19:                               ; %Flow214
	s_and_not1_saveexec_b32 s4, s18
	s_cbranch_execz .LBB2_29
; %bb.20:                               ; %NodeBlock
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_i64_e32 0, v[3:4]
	s_xor_b32 s6, exec_lo, s4
	s_cbranch_execz .LBB2_24
; %bb.21:                               ; %.preheader88
	v_cmp_lt_i64_e64 s4, s[12:13], 1
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB2_24
; %bb.22:                               ; %.lr.ph106
	v_mul_lo_u32 v4, v2, s12
	v_mul_lo_u32 v5, v1, s13
	v_mad_u64_u32 v[2:3], null, v1, s12, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s4, s22, 2
	s_addc_u32 s5, s23, 0
	s_mul_hi_u32 s7, s16, s4
	s_mul_i32 s5, s16, s5
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v3, v3, v5, v4
	s_mul_i32 s8, s17, s4
	s_add_i32 s5, s7, s5
	s_mul_i32 s4, s16, s4
	s_add_i32 s5, s5, s8
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
	s_lshl_b64 s[2:3], s[4:5], 3
	s_mov_b64 s[4:5], 0
.LBB2_23:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[0:1], v[5:6], off
	global_load_b64 v[2:3], v[7:8], off
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_add_co_u32 v5, vcc_lo, v5, 8
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_cmp_ge_i64_e64 s7, s[4:5], s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[2:3]
                                        ; implicit-def: $vgpr3_vgpr4
	global_store_b64 v[7:8], v[0:1], off
	v_add_co_u32 v7, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s7
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr0
	s_cbranch_vccz .LBB2_23
.LBB2_24:                               ; %Flow212
	s_and_not1_saveexec_b32 s2, s6
	s_cbranch_execz .LBB2_29
; %bb.25:                               ; %LeafBlock
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_29
; %bb.26:                               ; %.preheader
	v_cmp_lt_i64_e64 s2, s[12:13], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_29
; %bb.27:                               ; %.lr.ph110
	v_mul_lo_u32 v4, v2, s12
	v_mul_lo_u32 v5, v1, s13
	v_mad_u64_u32 v[2:3], null, v1, s12, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s2, s22, 2
	s_addc_u32 s3, s23, 0
	s_mul_hi_u32 s4, s16, s2
	s_mul_i32 s3, s16, s3
	s_mul_i32 s17, s17, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v3, v3, v5, v4
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	s_add_i32 s3, s4, s3
	s_mul_i32 s2, s16, s2
	s_add_i32 s3, s3, s17
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	s_lshl_b64 s[0:1], s[2:3], 3
	s_mov_b64 s[2:3], 0
.LBB2_28:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_cmp_ge_i64_e64 s4, s[2:3], s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	global_store_b64 v[2:3], v[4:5], off
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB2_28
.LBB2_29:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 360
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx, .Lfunc_end2-_Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1488
; NumSgprs: 28
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         108
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         116
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         118
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         120
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         122
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         124
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         126
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         168
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 360
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z10ReceiveFunPdPKdS1_S1_S1_S1_xPKxS3_S3_xxx.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4ZeroxPd
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4ZeroxPd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         108
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         116
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         118
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         120
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         122
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         124
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         126
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         168
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 360
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z11ReceiveGradPdS_S_S_S_PKdxPKxS3_S3_xxx.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
