//nvcc -ptx "E:\семестр 7\НИР\kernel.cu" -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2017\Community\VC\Tools\MSVC\14.16.27023\bin\Hostx64\x64"
//nvcc -ptx "E:\семестр 7\НИР\kernel.cu" -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2017\Community\VC\Tools\MSVC\14.16.27023\bin\Hostx64\x64" -gencode arch=compute_35,code=sm_35 -rdc=true
__device__ float getneighbor(float3 *A, const unsigned int N,const unsigned int M, const unsigned int x, const unsigned int y){
    if (A[x+y*M].z == 0.0) {
        return A[x+y*M].x;
    }
    return 0.0;//A[x+y*M].x;
}
__global__ void kernel(float *U, const unsigned int N,const unsigned int M,const int t,const float v,const float d_x,const float d_t, const float b=20)
{
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {U[(x+y*M)*4+(t+1)%3]=0.0;return;}
	
    float val;
    if (U[(x+y*M)*4+3] > 0.0){
        val = -4*U[(x+y*M)*4+t%3];
        val+= (U[(x-1+y*M)*4+3]>0.0)? U[(x-1+y*M)*4+t%3]:0;//U[(x+1+y*M)*4+t%3];
        val+= (U[(x+1+y*M)*4+3]>0.0)? U[(x+1+y*M)*4+t%3]:0;//U[(x-1+y*M)*4+t%3];
        val+= (U[(x+M+y*M)*4+3]>0.0)? U[(x+M+y*M)*4+t%3]:0;//U[(x-M+y*M)*4+t%3];
        val+= (U[(x-M+y*M)*4+3]>0.0)? U[(x-M+y*M)*4+t%3]:0;//U[(x+M+y*M)*4+t%3];
        val*=(U[(x+y*M)*4+3]*U[(x+y*M)*4+3])*v*v*d_t*d_t/(d_x*d_x); // ???
        //float b=20;
        val += 2*U[(x+y*M)*4+t%3]-U[(x+y*M)*4+(t-1)%3]*(1-d_t*b*0.5);
        val/=(1+d_t*b*0.5);
    } else {val = 0.0;}
    U[(x+y*M)*4+(t+1)%3]=val;
}

__global__ void kernelAndSetIR(float *U, float *IR, const unsigned int N,const unsigned int M,const int t,const float v,const float d_x,const float d_t,const int x_ir,const int y_ir, const float b=20)
{
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {U[(x+y*M)*4+(t+1)%3]=0.0;return;}
	
    float val;
    if (U[(x+y*M)*4+3] > 0.0){
        val = -4*U[(x+y*M)*4+t%3];
        val+= (U[(x-1+y*M)*4+3]>0.0)? U[(x-1+y*M)*4+t%3]:0;//U[(x+1+y*M)*4+t%3];
        val+= (U[(x+1+y*M)*4+3]>0.0)? U[(x+1+y*M)*4+t%3]:0;//U[(x-1+y*M)*4+t%3];
        val+= (U[(x+M+y*M)*4+3]>0.0)? U[(x+M+y*M)*4+t%3]:0;//U[(x-M+y*M)*4+t%3];
        val+= (U[(x-M+y*M)*4+3]>0.0)? U[(x-M+y*M)*4+t%3]:0;//U[(x+M+y*M)*4+t%3];
        val*=(U[(x+y*M)*4+3]*U[(x+y*M)*4+3])*v*v*d_t*d_t/(d_x*d_x); // ???
        //float b=20;
        val += 2*U[(x+y*M)*4+t%3]-U[(x+y*M)*4+(t-1)%3]*(1-d_t*b*0.5);
        val/=(1+d_t*b*0.5);
    } else {val = 0.0;}
    U[(x+y*M)*4+(t+1)%3]=val;
    if (x==x_ir && y==y_ir) IR[t-1]=val; // (t-1) because we run with t+1
}

__global__ void kernelAndSetIRAndSource(float *U, float *IR, const unsigned int N,const unsigned int M,const int t,const float v,const float d_x,const float d_t,const int x_ir,const int y_ir, const int x_s,const int y_s,float* F,const float b=20)
{
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {U[(x+y*M)*4+(t+1)%3]=0.0;return;}
	
    float val;
    if (U[(x+y*M)*4+3] > 0.0){
        val = -4*U[(x+y*M)*4+t%3];
        val+= (U[(x-1+y*M)*4+3]>0.0)? U[(x-1+y*M)*4+t%3]:0;//U[(x+1+y*M)*4+t%3];
        val+= (U[(x+1+y*M)*4+3]>0.0)? U[(x+1+y*M)*4+t%3]:0;//U[(x-1+y*M)*4+t%3];
        val+= (U[(x+M+y*M)*4+3]>0.0)? U[(x+M+y*M)*4+t%3]:0;//U[(x-M+y*M)*4+t%3];
        val+= (U[(x-M+y*M)*4+3]>0.0)? U[(x-M+y*M)*4+t%3]:0;//U[(x+M+y*M)*4+t%3];
        if (x==x_s && y==y_s) val+=F[t-1]; // Source
        val*=(U[(x+y*M)*4+3]*U[(x+y*M)*4+3])*v*v*d_t*d_t/(d_x*d_x); // ???
        //float b=20;
        val += 2*U[(x+y*M)*4+t%3]-U[(x+y*M)*4+(t-1)%3]*(1-d_t*b*0.5);
        val/=(1+d_t*b*0.5);
    } else {val = 0.0;}
    U[(x+y*M)*4+(t+1)%3]=val;
    if (x==x_ir && y==y_ir) IR[t-1]=val; // (t-1) because we run with t+1
}

__global__ void kernel2(float *U, float *U1, const unsigned int N,const unsigned int M,const float v,const float d_x,const float d_t)
{
    float3 *A=(float3*) U;
    float3 *A1=(float3*) U1;
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {    A1[x+y*M] = A[x+y*M]; return;}
	//A[i].x = i;
    float pos = A[x+y*M].x;
    float vel = A[x+y*M].y;
    float wall = A[x+y*M].z;
    if (wall == 0.0){
        float m = A[x+1+y*M].x;//getneighbor(A,N,M,x+1,y);
        m += A[x-1+y*M].x;//getneighbor(A,N,M,x-1,y);
        m += A[x+y*M+M].x;//getneighbor(A,N,M,x,y+1);
        m += A[x+y*M-M].x;//getneighbor(A,N,M,x,y-1);
        m *= .25;
        vel = 1.5*(1.0-wall)*(m-pos)+vel;
        pos=pos+vel;
    } else {pos = 0.0;vel = 0.0;}
    A1[x+y*M].x = pos;//+0.1;
    A1[x+y*M].y = vel;
    A1[x+y*M].z = wall;
}

// __global__ void kernel2(float *U, const unsigned int N,const unsigned int M,int t,const float v,const float d_x,const float d_t)
// {
//     float3 *A1=(float3*) U;
//     float3 *A2=(float3*) (U+1);
//     float3 *A3=(float3*) (U+2);
//     float3 *wall=(float3*) (U+3);
//     float3* A[3] = {A1,A2,A3};
// 	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// 	if (i >= N*M) return;
//     unsigned int x = i % M;
//     unsigned int y = i / M;
//     if (x+1>=M || y+1>=N || x<1 || y<1) {return;}
// 
//     //for (t:=0;t<1000;++t){
//     float val;
//     if (wall[x+y*M].x == 0.0){
//         val = A[t%3][x-1+y*M].x-4*A[t%3][x+y*M].x+A[t%3][x+1+y*M].x+A[t%3][x+y*M+M].x+A[t%3][x+y*M-M].x;
//         val*=v*v*d_t*d_t/(d_x*d_x);
//         val += 2*A[t%3][x+y*M].x-A[(t-1)%3][x+y*M].x;
//     } else {val = 0.0;}
//     A[(t+1)%3][x+y*M].x=val;
// 
// }


	.file	"tmpxft_0020159c_00000000-6_kernel_simple.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11getneighborP6float3jjjj
	.type	_Z11getneighborP6float3jjjj, @function
_Z11getneighborP6float3jjjj:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z11getneighborP6float3jjjj, .-_Z11getneighborP6float3jjjj
	.globl	_Z32__device_stub__Z6kernelPfjjiffffPfjjiffff
	.type	_Z32__device_stub__Z6kernelPfjjiffffPfjjiffff, @function
_Z32__device_stub__Z6kernelPfjjiffffPfjjiffff:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movss	%xmm0, 24(%rsp)
	movss	%xmm1, 20(%rsp)
	movss	%xmm2, 16(%rsp)
	movss	%xmm3, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z6kernelPfjjiffff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z32__device_stub__Z6kernelPfjjiffffPfjjiffff, .-_Z32__device_stub__Z6kernelPfjjiffffPfjjiffff
	.globl	_Z6kernelPfjjiffff
	.type	_Z6kernelPfjjiffff, @function
_Z6kernelPfjjiffff:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z6kernelPfjjiffffPfjjiffff
	.cfi_endproc
.LFE2034:
	.size	_Z6kernelPfjjiffff, .-_Z6kernelPfjjiffff
	.globl	_Z45__device_stub__Z14kernelAndSetIRPfS_jjifffiifPfS_jjifffiif
	.type	_Z45__device_stub__Z14kernelAndSetIRPfS_jjifffiifPfS_jjifffiif, @function
_Z45__device_stub__Z14kernelAndSetIRPfS_jjifffiifPfS_jjifffiif:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movl	%r9d, 4(%rsp)
	movss	%xmm0, 16(%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	movss	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z14kernelAndSetIRPfS_jjifffiif(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L10:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z45__device_stub__Z14kernelAndSetIRPfS_jjifffiifPfS_jjifffiif, .-_Z45__device_stub__Z14kernelAndSetIRPfS_jjifffiifPfS_jjifffiif
	.globl	_Z14kernelAndSetIRPfS_jjifffiif
	.type	_Z14kernelAndSetIRPfS_jjifffiif, @function
_Z14kernelAndSetIRPfS_jjifffiif:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z14kernelAndSetIRPfS_jjifffiifPfS_jjifffiif
	.cfi_endproc
.LFE2036:
	.size	_Z14kernelAndSetIRPfS_jjifffiif, .-_Z14kernelAndSetIRPfS_jjifffiif
	.globl	_Z58__device_stub__Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_fPfS_jjifffiiiiS_f
	.type	_Z58__device_stub__Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_fPfS_jjifffiiiiS_f, @function
_Z58__device_stub__Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_fPfS_jjifffiiiiS_f:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	296(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 44(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 36(%rsp)
	movl	%r9d, 20(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 32(%rsp)
	movss	%xmm1, 28(%rsp)
	movss	%xmm2, 24(%rsp)
	movss	%xmm3, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	80(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 288
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L15:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z58__device_stub__Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_fPfS_jjifffiiiiS_f, .-_Z58__device_stub__Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_fPfS_jjifffiiiiS_f
	.globl	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.type	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, @function
_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_fPfS_jjifffiiiiS_f
	.cfi_endproc
.LFE2038:
	.size	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, .-_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.globl	_Z33__device_stub__Z7kernel2PfS_jjfffPfS_jjfff
	.type	_Z33__device_stub__Z7kernel2PfS_jjfffPfS_jjfff, @function
_Z33__device_stub__Z7kernel2PfS_jjfffPfS_jjfff:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7kernel2PfS_jjfff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L20:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z33__device_stub__Z7kernel2PfS_jjfffPfS_jjfff, .-_Z33__device_stub__Z7kernel2PfS_jjfffPfS_jjfff
	.globl	_Z7kernel2PfS_jjfff
	.type	_Z7kernel2PfS_jjfff, @function
_Z7kernel2PfS_jjfff:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7kernel2PfS_jjfffPfS_jjfff
	.cfi_endproc
.LFE2040:
	.size	_Z7kernel2PfS_jjfff, .-_Z7kernel2PfS_jjfff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7kernel2PfS_jjfff"
.LC1:
	.string	"_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f"
.LC2:
	.string	"_Z14kernelAndSetIRPfS_jjifffiif"
.LC3:
	.string	"_Z6kernelPfjjiffff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7kernel2PfS_jjfff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14kernelAndSetIRPfS_jjifffiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6kernelPfjjiffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2042:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//nvcc -ptx "E:\семестр 7\НИР\kernel.cu" -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2017\Community\VC\Tools\MSVC\14.16.27023\bin\Hostx64\x64"
//nvcc -ptx "E:\семестр 7\НИР\kernel.cu" -ccbin "C:\Program Files (x86)\Microsoft Visual Studio\2017\Community\VC\Tools\MSVC\14.16.27023\bin\Hostx64\x64" -gencode arch=compute_35,code=sm_35 -rdc=true
__device__ float getneighbor(float3 *A, const unsigned int N,const unsigned int M, const unsigned int x, const unsigned int y){
    if (A[x+y*M].z == 0.0) {
        return A[x+y*M].x;
    }
    return 0.0;//A[x+y*M].x;
}
__global__ void kernel(float *U, const unsigned int N,const unsigned int M,const int t,const float v,const float d_x,const float d_t, const float b=20)
{
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {U[(x+y*M)*4+(t+1)%3]=0.0;return;}
	
    float val;
    if (U[(x+y*M)*4+3] > 0.0){
        val = -4*U[(x+y*M)*4+t%3];
        val+= (U[(x-1+y*M)*4+3]>0.0)? U[(x-1+y*M)*4+t%3]:0;//U[(x+1+y*M)*4+t%3];
        val+= (U[(x+1+y*M)*4+3]>0.0)? U[(x+1+y*M)*4+t%3]:0;//U[(x-1+y*M)*4+t%3];
        val+= (U[(x+M+y*M)*4+3]>0.0)? U[(x+M+y*M)*4+t%3]:0;//U[(x-M+y*M)*4+t%3];
        val+= (U[(x-M+y*M)*4+3]>0.0)? U[(x-M+y*M)*4+t%3]:0;//U[(x+M+y*M)*4+t%3];
        val*=(U[(x+y*M)*4+3]*U[(x+y*M)*4+3])*v*v*d_t*d_t/(d_x*d_x); // ???
        //float b=20;
        val += 2*U[(x+y*M)*4+t%3]-U[(x+y*M)*4+(t-1)%3]*(1-d_t*b*0.5);
        val/=(1+d_t*b*0.5);
    } else {val = 0.0;}
    U[(x+y*M)*4+(t+1)%3]=val;
}

__global__ void kernelAndSetIR(float *U, float *IR, const unsigned int N,const unsigned int M,const int t,const float v,const float d_x,const float d_t,const int x_ir,const int y_ir, const float b=20)
{
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {U[(x+y*M)*4+(t+1)%3]=0.0;return;}
	
    float val;
    if (U[(x+y*M)*4+3] > 0.0){
        val = -4*U[(x+y*M)*4+t%3];
        val+= (U[(x-1+y*M)*4+3]>0.0)? U[(x-1+y*M)*4+t%3]:0;//U[(x+1+y*M)*4+t%3];
        val+= (U[(x+1+y*M)*4+3]>0.0)? U[(x+1+y*M)*4+t%3]:0;//U[(x-1+y*M)*4+t%3];
        val+= (U[(x+M+y*M)*4+3]>0.0)? U[(x+M+y*M)*4+t%3]:0;//U[(x-M+y*M)*4+t%3];
        val+= (U[(x-M+y*M)*4+3]>0.0)? U[(x-M+y*M)*4+t%3]:0;//U[(x+M+y*M)*4+t%3];
        val*=(U[(x+y*M)*4+3]*U[(x+y*M)*4+3])*v*v*d_t*d_t/(d_x*d_x); // ???
        //float b=20;
        val += 2*U[(x+y*M)*4+t%3]-U[(x+y*M)*4+(t-1)%3]*(1-d_t*b*0.5);
        val/=(1+d_t*b*0.5);
    } else {val = 0.0;}
    U[(x+y*M)*4+(t+1)%3]=val;
    if (x==x_ir && y==y_ir) IR[t-1]=val; // (t-1) because we run with t+1
}

__global__ void kernelAndSetIRAndSource(float *U, float *IR, const unsigned int N,const unsigned int M,const int t,const float v,const float d_x,const float d_t,const int x_ir,const int y_ir, const int x_s,const int y_s,float* F,const float b=20)
{
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {U[(x+y*M)*4+(t+1)%3]=0.0;return;}
	
    float val;
    if (U[(x+y*M)*4+3] > 0.0){
        val = -4*U[(x+y*M)*4+t%3];
        val+= (U[(x-1+y*M)*4+3]>0.0)? U[(x-1+y*M)*4+t%3]:0;//U[(x+1+y*M)*4+t%3];
        val+= (U[(x+1+y*M)*4+3]>0.0)? U[(x+1+y*M)*4+t%3]:0;//U[(x-1+y*M)*4+t%3];
        val+= (U[(x+M+y*M)*4+3]>0.0)? U[(x+M+y*M)*4+t%3]:0;//U[(x-M+y*M)*4+t%3];
        val+= (U[(x-M+y*M)*4+3]>0.0)? U[(x-M+y*M)*4+t%3]:0;//U[(x+M+y*M)*4+t%3];
        if (x==x_s && y==y_s) val+=F[t-1]; // Source
        val*=(U[(x+y*M)*4+3]*U[(x+y*M)*4+3])*v*v*d_t*d_t/(d_x*d_x); // ???
        //float b=20;
        val += 2*U[(x+y*M)*4+t%3]-U[(x+y*M)*4+(t-1)%3]*(1-d_t*b*0.5);
        val/=(1+d_t*b*0.5);
    } else {val = 0.0;}
    U[(x+y*M)*4+(t+1)%3]=val;
    if (x==x_ir && y==y_ir) IR[t-1]=val; // (t-1) because we run with t+1
}

__global__ void kernel2(float *U, float *U1, const unsigned int N,const unsigned int M,const float v,const float d_x,const float d_t)
{
    float3 *A=(float3*) U;
    float3 *A1=(float3*) U1;
	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
	if (i >= N*M) return;
    unsigned int x = i % M;
    unsigned int y = i / M;
    if (x+1>=M || y+1>=N || x<1 || y<1) {    A1[x+y*M] = A[x+y*M]; return;}
	//A[i].x = i;
    float pos = A[x+y*M].x;
    float vel = A[x+y*M].y;
    float wall = A[x+y*M].z;
    if (wall == 0.0){
        float m = A[x+1+y*M].x;//getneighbor(A,N,M,x+1,y);
        m += A[x-1+y*M].x;//getneighbor(A,N,M,x-1,y);
        m += A[x+y*M+M].x;//getneighbor(A,N,M,x,y+1);
        m += A[x+y*M-M].x;//getneighbor(A,N,M,x,y-1);
        m *= .25;
        vel = 1.5*(1.0-wall)*(m-pos)+vel;
        pos=pos+vel;
    } else {pos = 0.0;vel = 0.0;}
    A1[x+y*M].x = pos;//+0.1;
    A1[x+y*M].y = vel;
    A1[x+y*M].z = wall;
}

// __global__ void kernel2(float *U, const unsigned int N,const unsigned int M,int t,const float v,const float d_x,const float d_t)
// {
//     float3 *A1=(float3*) U;
//     float3 *A2=(float3*) (U+1);
//     float3 *A3=(float3*) (U+2);
//     float3 *wall=(float3*) (U+3);
//     float3* A[3] = {A1,A2,A3};
// 	unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// 	if (i >= N*M) return;
//     unsigned int x = i % M;
//     unsigned int y = i / M;
//     if (x+1>=M || y+1>=N || x<1 || y<1) {return;}
// 
//     //for (t:=0;t<1000;++t){
//     float val;
//     if (wall[x+y*M].x == 0.0){
//         val = A[t%3][x-1+y*M].x-4*A[t%3][x+y*M].x+A[t%3][x+1+y*M].x+A[t%3][x+y*M+M].x+A[t%3][x+y*M-M].x;
//         val*=v*v*d_t*d_t/(d_x*d_x);
//         val += 2*A[t%3][x+y*M].x-A[(t-1)%3][x+y*M].x;
//     } else {val = 0.0;}
//     A[(t+1)%3][x+y*M].x=val;
// 
// }


	.text
	.file	"kernel_simple.hip"
	.globl	_Z21__device_stub__kernelPfjjiffff # -- Begin function _Z21__device_stub__kernelPfjjiffff
	.type	_Z21__device_stub__kernelPfjjiffff,@function
_Z21__device_stub__kernelPfjjiffff:     # @_Z21__device_stub__kernelPfjjiffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	36(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	28(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	20(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	16(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	12(%rsp), %r10
	movss	%xmm3, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	48(%rsp), %r12
	leaq	40(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPfjjiffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPfjjiffff, .Lfunc_end0-_Z21__device_stub__kernelPfjjiffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__kernelAndSetIRPfS_jjifffiif # -- Begin function _Z29__device_stub__kernelAndSetIRPfS_jjifffiif
	.type	_Z29__device_stub__kernelAndSetIRPfS_jjifffiif,@function
_Z29__device_stub__kernelAndSetIRPfS_jjifffiif: # @_Z29__device_stub__kernelAndSetIRPfS_jjifffiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	28(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	20(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	16(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	12(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	8(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	4(%rsp), %r14
	movl	%r9d, (%r14)
	movq	%rsp, %r9
	movss	%xmm3, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14kernelAndSetIRPfS_jjifffiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__kernelAndSetIRPfS_jjifffiif, .Lfunc_end1-_Z29__device_stub__kernelAndSetIRPfS_jjifffiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f # -- Begin function _Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.type	_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f,@function
_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f: # @_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	28(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	20(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	16(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	12(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	8(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	4(%rsp), %r14
	movl	%r9d, (%r14)
	movq	%rsp, %r9
	movss	%xmm3, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 96(%rbx)
	movq	%r9, 104(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, .Lfunc_end2-_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__kernel2PfS_jjfff # -- Begin function _Z22__device_stub__kernel2PfS_jjfff
	.type	_Z22__device_stub__kernel2PfS_jjfff,@function
_Z22__device_stub__kernel2PfS_jjfff:    # @_Z22__device_stub__kernel2PfS_jjfff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	28(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	20(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	16(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7kernel2PfS_jjfff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__kernel2PfS_jjfff, .Lfunc_end3-_Z22__device_stub__kernel2PfS_jjfff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPfjjiffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14kernelAndSetIRPfS_jjifffiif, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7kernel2PfS_jjfff, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPfjjiffff,@object      # @_Z6kernelPfjjiffff
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPfjjiffff
	.p2align	3, 0x0
_Z6kernelPfjjiffff:
	.quad	_Z21__device_stub__kernelPfjjiffff
	.size	_Z6kernelPfjjiffff, 8

	.type	_Z14kernelAndSetIRPfS_jjifffiif,@object # @_Z14kernelAndSetIRPfS_jjifffiif
	.globl	_Z14kernelAndSetIRPfS_jjifffiif
	.p2align	3, 0x0
_Z14kernelAndSetIRPfS_jjifffiif:
	.quad	_Z29__device_stub__kernelAndSetIRPfS_jjifffiif
	.size	_Z14kernelAndSetIRPfS_jjifffiif, 8

	.type	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f,@object # @_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.globl	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.p2align	3, 0x0
_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f:
	.quad	_Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.size	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, 8

	.type	_Z7kernel2PfS_jjfff,@object     # @_Z7kernel2PfS_jjfff
	.globl	_Z7kernel2PfS_jjfff
	.p2align	3, 0x0
_Z7kernel2PfS_jjfff:
	.quad	_Z22__device_stub__kernel2PfS_jjfff
	.size	_Z7kernel2PfS_jjfff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6kernelPfjjiffff"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14kernelAndSetIRPfS_jjifffiif"
	.size	.L__unnamed_2, 32

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f"
	.size	.L__unnamed_3, 45

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7kernel2PfS_jjfff"
	.size	.L__unnamed_4, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPfjjiffff
	.addrsig_sym _Z29__device_stub__kernelAndSetIRPfS_jjifffiif
	.addrsig_sym _Z38__device_stub__kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.addrsig_sym _Z22__device_stub__kernel2PfS_jjfff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPfjjiffff
	.addrsig_sym _Z14kernelAndSetIRPfS_jjifffiif
	.addrsig_sym _Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.addrsig_sym _Z7kernel2PfS_jjfff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPfjjiffff      ; -- Begin function _Z6kernelPfjjiffff
	.globl	_Z6kernelPfjjiffff
	.p2align	8
	.type	_Z6kernelPfjjiffff,@function
_Z6kernelPfjjiffff:                     ; @_Z6kernelPfjjiffff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_18
; %bb.1:
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s2, 0, s5
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s2, v0
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s5
	v_add_nc_u32_e32 v3, 1, v0
	v_sub_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v4, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v0, s5
	v_sub_nc_u32_e32 v8, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, 1, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_le_u32_e64 s11, s5, v9
	v_cmpx_gt_u32_e64 s5, v9
	s_cbranch_execz .LBB0_15
; %bb.2:
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_cmp_le_u32_e64 s1, s5, v1
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s4, v0
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s1, s0
	s_mov_b32 s1, -1
	s_and_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_14
; %bb.3:
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v0, v[4:5], off offset:12
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v0
	s_cbranch_execz .LBB0_13
; %bb.4:
	s_mul_hi_i32 s4, s6, 0x55555556
	v_add_nc_u32_e32 v10, v8, v7
	s_lshr_b32 s13, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s13
	s_mov_b32 s13, exec_lo
	s_mul_i32 s4, s4, 3
	s_sub_i32 s4, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s4, v2
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_lshl_add_u32 v3, v10, 2, -4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[10:11], off offset:12
	global_load_b32 v5, v[5:6], off
	v_mov_b32_e32 v6, 0
	s_waitcnt vmcnt(1)
	v_cmpx_lt_f32_e32 0, v10
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s13
	v_add_lshl_u32 v3, v7, v9, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_co_u32 v9, vcc_lo, s2, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	global_load_b32 v9, v[9:10], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v9
	v_mov_b32_e32 v9, 0
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_add_nc_u32_e32 v3, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_co_u32 v9, vcc_lo, s2, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	global_load_b32 v9, v[9:10], off
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v3, s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v7, 2
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	global_load_b32 v10, v[10:11], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s13
	v_subrev_nc_u32_e32 v3, s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v7, 2
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v7, v[7:8], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v7
	v_mov_b32_e32 v7, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_add_nc_u32_e32 v3, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s4, s6, -1
	v_fmac_f32_e32 v6, -4.0, v5
	s_mul_hi_i32 s5, s4, 0x55555556
	v_add_f32_e32 v12, v5, v5
	s_lshr_b32 s13, s5, 31
	v_mul_f32_e64 v17, s8, s8
	s_add_i32 s5, s5, s13
	v_mul_f32_e32 v0, v0, v0
	s_mul_i32 s5, s5, 3
	v_add_f32_e32 v5, v6, v9
	s_sub_i32 s4, s4, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_dual_mul_f32 v0, s7, v0 :: v_dual_add_nc_u32 v3, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v10
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v0, s7, v0 :: v_dual_add_f32 v5, v5, v7
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	v_mul_f32_e32 v0, s9, v0
	global_load_b32 v8, v[3:4], off
	v_mul_f32_e64 v3, s9, s10
	v_mul_f32_e32 v0, s9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[3:4], v3
	v_div_scale_f32 v18, null, v17, v17, v0
	v_div_scale_f32 v20, vcc_lo, v0, v17, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v18, v19, 1.0
	v_fmac_f32_e32 v19, v11, v19
	v_cvt_f64_f32_e32 v[11:12], v12
	v_fma_f64 v[13:14], v[3:4], -0.5, 1.0
	v_fma_f64 v[3:4], v[3:4], 0.5, 1.0
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[15:16], v8
	v_mul_f32_e32 v8, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v18, v8, v20
	v_fmac_f32_e32 v8, v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v18, v8, v20
	v_div_fmas_f32 v6, v6, v19, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v6, v17, v0
	v_mul_f32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_fma_f64 v[7:8], -v[13:14], v[15:16], v[11:12]
	v_add_f64 v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[5:6]
	v_cvt_f64_f32_e32 v[5:6], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[5:6]
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, v[5:6], v[3:4], v[5:6]
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[7:8], v[3:4], v[5:6]
	v_cvt_f32_f64_e32 v3, v[3:4]
.LBB0_13:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, -1
.LBB0_14:                               ; %Flow146
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s11, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s11, s0, s1
.LBB0_15:                               ; %Flow145
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s0, s11
; %bb.16:
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v1
; %bb.17:                               ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_i32 s1, s0, 0x55555556
	s_lshr_b32 s4, s1, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s4
	s_mul_i32 s1, s1, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s0, s1
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPfjjiffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPfjjiffff, .Lfunc_end0-_Z6kernelPfjjiffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1472
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14kernelAndSetIRPfS_jjifffiif ; -- Begin function _Z14kernelAndSetIRPfS_jjifffiif
	.globl	_Z14kernelAndSetIRPfS_jjifffiif
	.p2align	8
	.type	_Z14kernelAndSetIRPfS_jjifffiif,@function
_Z14kernelAndSetIRPfS_jjifffiif:        ; @_Z14kernelAndSetIRPfS_jjifffiif
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_19
; %bb.1:
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s2, 0, s5
	s_clause 0x1
	s_load_b32 s16, s[0:1], 0x30
	s_load_b128 s[12:15], s[0:1], 0x0
	s_mov_b32 s3, exec_lo
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_mul_lo_u32 v2, v0, s5
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v2
	v_subrev_nc_u32_e32 v4, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_mul_lo_u32 v9, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v1, v9
	v_add_nc_u32_e32 v10, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_u32_e64 s2, s5, v10
	v_cmpx_gt_u32_e64 s5, v10
	s_cbranch_execz .LBB1_17
; %bb.2:
	v_add_nc_u32_e32 v2, 1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_cmp_le_u32_e64 s1, s5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s4, v2
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s4, s1
	s_cbranch_execz .LBB1_16
; %bb.3:
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_load_b32 v5, v[4:5], off offset:12
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v5
	s_cbranch_execz .LBB1_13
; %bb.4:
	s_mul_hi_i32 s1, s6, 0x55555556
	v_add_nc_u32_e32 v11, v6, v9
	s_lshr_b32 s17, s1, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s17
	s_mov_b32 s17, exec_lo
	s_mul_i32 s1, s1, 3
	s_sub_i32 s1, s6, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s1, v2
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_lshl_add_u32 v3, v11, 2, -4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	v_add_co_u32 v7, vcc_lo, s12, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v11, v[11:12], off offset:12
	global_load_b32 v7, v[7:8], off
	v_mov_b32_e32 v8, 0
	s_waitcnt vmcnt(1)
	v_cmpx_lt_f32_e32 0, v11
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v8, v[11:12], off
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s17
	v_add_lshl_u32 v3, v9, v10, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s12, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	global_load_b32 v10, v[10:11], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_add_nc_u32_e32 v3, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s12, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s17
	v_add_nc_u32_e32 v3, s5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v9, 2
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v11, v[11:12], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v11
	v_mov_b32_e32 v11, 0
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB1_10
; %bb.9:
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s17
	v_subrev_nc_u32_e32 v3, s5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v9, 2
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
	global_load_b32 v9, v[12:13], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v9
	v_mov_b32_e32 v9, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_12
; %bb.11:
	v_add_nc_u32_e32 v3, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_co_u32 v12, vcc_lo, s12, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
	global_load_b32 v9, v[12:13], off
.LBB1_12:
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s1, s6, -1
	v_mul_f32_e64 v18, s8, s8
	s_mul_hi_i32 s5, s1, 0x55555556
	v_add_f32_e32 v13, v7, v7
	s_lshr_b32 s17, s5, 31
	v_fmac_f32_e32 v8, -4.0, v7
	s_add_i32 s5, s5, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, 3
	s_sub_i32 s1, s1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v8, v10
	v_add_nc_u32_e32 v3, s1, v2
	v_add_f32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b32 v16, v[3:4], off
	v_mul_f32_e32 v3, v5, v5
	v_mul_f32_e64 v4, s9, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, s7, v3
	v_cvt_f64_f32_e32 v[3:4], v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, s7, v5
	v_mul_f32_e32 v5, s9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, s9, v5
	v_div_scale_f32 v19, null, v18, v18, v5
	v_div_scale_f32 v21, vcc_lo, v5, v18, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v19, v20, 1.0
	v_fma_f64 v[14:15], v[3:4], -0.5, 1.0
	v_fmac_f32_e32 v20, v12, v20
	v_cvt_f64_f32_e32 v[12:13], v13
	v_fma_f64 v[3:4], v[3:4], 0.5, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v21, v20
	v_fma_f32 v23, -v19, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v23, v20
	v_fma_f32 v8, -v19, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v20, v22
	v_div_fixup_f32 v5, v8, v18, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v7
	v_cvt_f64_f32_e32 v[7:8], v5
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[16:17], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[14:15], v[16:17], v[12:13]
	v_add_f64 v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v5, v[7:8]
	v_cvt_f64_f32_e32 v[7:8], v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[9:10], null, v[3:4], v[3:4], v[7:8]
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_div_scale_f64 v[13:14], vcc_lo, v[7:8], v[3:4], v[7:8]
	v_mul_f64 v[15:16], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[9:10], v[15:16], v[13:14]
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[9:10], v[3:4], v[7:8]
	v_cvt_f32_f64_e32 v3, v[3:4]
.LBB1_13:                               ; %Flow158
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s6, 1
	v_cmp_eq_u32_e32 vcc_lo, s10, v6
	s_mul_hi_i32 s1, s0, 0x55555556
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s5, s1, 31
	s_add_i32 s1, s1, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, 3
	s_sub_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s0, v2
	v_cmp_eq_u32_e64 s0, s11, v0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s1, s12, v7
	v_add_co_ci_u32_e64 v7, s1, s13, v8, s1
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s1, vcc_lo, s0
	global_store_b32 v[6:7], v3, off
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_15
; %bb.14:
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[6:7], 2
	s_add_u32 s8, s14, s8
	s_addc_u32 s9, s15, s9
	global_store_b32 v5, v3, s[8:9] offset:-4
.LBB1_15:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, -1
.LBB1_16:                               ; %Flow160
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s2, s1, s0
.LBB1_17:                               ; %Flow159
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_19
; %bb.18:
	s_add_i32 s0, s6, 1
	v_mov_b32_e32 v2, 0
	s_mul_hi_i32 s1, s0, 0x55555556
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s1, 31
	s_add_i32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, 3
	s_sub_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 2, s0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14kernelAndSetIRPfS_jjifffiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14kernelAndSetIRPfS_jjifffiif, .Lfunc_end1-_Z14kernelAndSetIRPfS_jjifffiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1624
; NumSgprs: 20
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f ; -- Begin function _Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.globl	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
	.p2align	8
	.type	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f,@function
_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f: ; @_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b256 s[4:11], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_21
; %bb.1:
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s2, 0, s5
	s_clause 0x1
	s_load_b64 s[16:17], s[0:1], 0x30
	s_load_b128 s[12:15], s[0:1], 0x0
	s_mov_b32 s19, exec_lo
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_mul_lo_u32 v2, v0, s5
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v2
	v_subrev_nc_u32_e32 v4, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_mul_lo_u32 v8, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v1, v8
	v_add_nc_u32_e32 v10, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_u32_e64 s18, s5, v10
	v_cmpx_gt_u32_e64 s5, v10
	s_cbranch_execz .LBB2_19
; %bb.2:
	v_add_nc_u32_e32 v2, 1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_cmp_le_u32_e64 s3, s5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s4, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s3, s2
	s_mov_b32 s2, -1
	s_and_saveexec_b32 s3, s4
	s_cbranch_execz .LBB2_18
; %bb.3:
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v1
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_load_b32 v5, v[4:5], off offset:12
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v5
	s_cbranch_execz .LBB2_15
; %bb.4:
	s_mul_hi_i32 s2, s6, 0x55555556
	v_add_nc_u32_e32 v7, v6, v8
	s_lshr_b32 s20, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s20
	s_mul_i32 s2, s2, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s2, s6, s2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_lshl_add_u32 v3, v7, 2, -4
	v_lshlrev_b64 v[13:14], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s12, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	s_clause 0x1
	global_load_b32 v9, v[13:14], off offset:12
	global_load_b32 v7, v[11:12], off
	s_waitcnt vmcnt(1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v9
	v_mov_b32_e32 v9, 0
	s_and_saveexec_b32 s20, vcc_lo
	s_cbranch_execz .LBB2_6
; %bb.5:
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v9, v[11:12], off
.LBB2_6:
	s_or_b32 exec_lo, exec_lo, s20
	v_add_lshl_u32 v3, v8, v10, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s12, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	global_load_b32 v10, v[10:11], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s20, vcc_lo
	s_cbranch_execz .LBB2_8
; %bb.7:
	v_add_nc_u32_e32 v3, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s12, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s20
	v_add_nc_u32_e32 v3, s5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v8, 2
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v11, v[11:12], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v11
	v_mov_b32_e32 v11, 0
	s_and_saveexec_b32 s20, vcc_lo
	s_cbranch_execz .LBB2_10
; %bb.9:
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s20
	v_subrev_nc_u32_e32 v3, s5, v6
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v8, 2
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
	global_load_b32 v8, v[12:13], off offset:12
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v8
	s_cbranch_execz .LBB2_12
; %bb.11:
	v_add_nc_u32_e32 v3, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB2_12:
	s_or_b32 exec_lo, exec_lo, s5
	v_fmac_f32_e32 v9, -4.0, v7
	v_cmp_eq_u32_e32 vcc_lo, s16, v6
	v_cmp_eq_u32_e64 s2, s17, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v9, v10
	s_and_b32 s5, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v11
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v4
	s_and_saveexec_b32 s2, s5
	s_cbranch_execz .LBB2_14
; %bb.13:
	s_load_b64 s[16:17], s[0:1], 0x38
	s_ashr_i32 s21, s6, 31
	s_mov_b32 s20, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[20:21], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s5, s16, s20
	s_addc_u32 s17, s17, s21
	s_add_u32 s16, s5, -4
	s_addc_u32 s17, s17, -1
	s_load_b32 s5, s[16:17], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, s5, v3
.LBB2_14:
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s2, s6, -1
	s_load_b32 s0, s[0:1], 0x40
	s_mul_hi_i32 s5, s2, 0x55555556
	v_dual_mul_f32 v4, v5, v5 :: v_dual_add_f32 v7, v7, v7
	s_lshr_b32 s16, s5, 31
	v_mul_f32_e64 v13, s8, s8
	s_add_i32 s5, s5, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, 3
	s_sub_i32 s2, s2, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, s2, v2
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v5, s9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
	global_load_b32 v11, v[8:9], off
	v_mul_f32_e32 v8, s7, v4
	v_cvt_f64_f32_e32 v[4:5], v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, s7, v8
	v_mul_f32_e32 v8, s9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, s9, v8
	v_div_scale_f32 v15, null, v13, v13, v14
	v_div_scale_f32 v17, vcc_lo, v14, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v16, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v15, v16, 1.0
	v_fma_f64 v[9:10], v[4:5], -0.5, 1.0
	v_fmac_f32_e32 v16, v8, v16
	v_cvt_f64_f32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v17, v16
	v_fma_f32 v19, -v15, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v16
	v_fma_f32 v15, -v15, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v15, v15, v16, v18
	v_div_fixup_f32 v13, v15, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v13, v3
	v_cvt_f64_f32_e32 v[13:14], v3
	v_fma_f64 v[3:4], v[4:5], 0.5, 1.0
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[11:12], v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[9:10], v[11:12], v[7:8]
	v_add_f64 v[7:8], v[7:8], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v7, v[7:8]
	v_cvt_f64_f32_e32 v[7:8], v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[9:10], null, v[3:4], v[3:4], v[7:8]
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_div_scale_f64 v[13:14], vcc_lo, v[7:8], v[3:4], v[7:8]
	v_mul_f64 v[15:16], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[9:10], v[15:16], v[13:14]
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[9:10], v[3:4], v[7:8]
	v_cvt_f32_f64_e32 v3, v[3:4]
.LBB2_15:                               ; %Flow174
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s0, s6, 1
	v_cmp_eq_u32_e32 vcc_lo, s10, v6
	s_mul_hi_i32 s1, s0, 0x55555556
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s1, 31
	s_add_i32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, 3
	s_sub_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s0, v2
	v_cmp_eq_u32_e64 s0, s11, v0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s1, s12, v7
	v_add_co_ci_u32_e64 v7, s1, s13, v8, s1
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s1, vcc_lo, s0
	global_store_b32 v[6:7], v3, off
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB2_17
; %bb.16:
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[6:7], 2
	s_add_u32 s4, s14, s4
	s_addc_u32 s5, s15, s5
	global_store_b32 v5, v3, s[4:5] offset:-4
.LBB2_17:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, -1
.LBB2_18:                               ; %Flow176
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s18, exec_lo
	s_and_b32 s1, s2, exec_lo
	s_or_b32 s18, s0, s1
.LBB2_19:                               ; %Flow175
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s18
	s_cbranch_execz .LBB2_21
; %bb.20:
	s_add_i32 s0, s6, 1
	v_mov_b32_e32 v2, 0
	s_mul_hi_i32 s1, s0, 0x55555556
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s1, 31
	s_add_i32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, 3
	s_sub_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 2, s0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f, .Lfunc_end2-_Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1724
; NumSgprs: 24
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7kernel2PfS_jjfff     ; -- Begin function _Z7kernel2PfS_jjfff
	.globl	_Z7kernel2PfS_jjfff
	.p2align	8
	.type	_Z7kernel2PfS_jjfff,@function
_Z7kernel2PfS_jjfff:                    ; @_Z7kernel2PfS_jjfff
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
	s_mul_i32 s4, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v3
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB3_9
; %bb.1:
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s4, v0
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s3
	v_add_nc_u32_e32 v2, 1, v0
	v_sub_nc_u32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	v_add_nc_u32_e32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_mul_lo_u32 v6, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v3, v6
	v_add_nc_u32_e32 v8, 1, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_u32_e64 s8, s3, v8
	v_cmpx_gt_u32_e64 s3, v8
	s_cbranch_execz .LBB3_7
; %bb.2:
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_cmp_le_u32_e64 s1, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s2, v0
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s1, s0
	s_mov_b32 s1, -1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_6
; %bb.3:
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[4:5], null, v3, 12, s[4:5]
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
	s_mov_b32 s1, exec_lo
	global_load_b32 v2, v[4:5], off offset:8
	s_waitcnt vmcnt(0)
	v_cmpx_eq_f32_e32 0, v2
	s_cbranch_execz .LBB3_5
; %bb.4:
	v_add_nc_u32_e32 v8, v6, v8
	v_add3_u32 v9, v7, v6, -1
	v_add_nc_u32_e32 v10, s3, v3
	v_subrev_nc_u32_e32 v11, s3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, v8, 12, s[4:5]
	v_mad_u64_u32 v[6:7], null, v9, 12, s[4:5]
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[8:9], null, v10, 12, s[4:5]
	s_clause 0x1
	global_load_b32 v10, v[0:1], off
	global_load_b32 v6, v[6:7], off
	v_mad_u64_u32 v[0:1], null, v11, 12, s[4:5]
	s_clause 0x2
	global_load_b32 v7, v[8:9], off
	global_load_b32 v8, v[0:1], off
	global_load_b64 v[0:1], v[4:5], off
	v_cvt_f64_f32_e32 v[4:5], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], -v[4:5], 1.0
	v_mul_f64 v[4:5], 0x3ff80000, v[4:5]
	s_waitcnt vmcnt(3)
	v_add_f32_e32 v6, v10, v6
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v7
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[8:9], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0x3e800000, v6, -v0
	v_cvt_f64_f32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	v_cvt_f32_f64_e32 v1, v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v1
.LBB3_5:
	s_or_b32 exec_lo, exec_lo, s1
	v_mad_u64_u32 v[4:5], null, v3, 12, s[6:7]
	s_xor_b32 s1, exec_lo, -1
	global_store_b96 v[4:5], v[0:2], off
.LBB3_6:                                ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s8, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s8, s0, s1
.LBB3_7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s8
	s_cbranch_execz .LBB3_9
; %bb.8:
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[0:1], null, v3, 12, s[4:5]
	v_mad_u64_u32 v[4:5], null, v3, 12, s[6:7]
	global_load_b32 v2, v[0:1], off offset:8
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v2, off offset:8
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[0:1], off
.LBB3_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7kernel2PfS_jjfff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z7kernel2PfS_jjfff, .Lfunc_end3-_Z7kernel2PfS_jjfff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 692
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPfjjiffff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPfjjiffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14kernelAndSetIRPfS_jjifffiif
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z14kernelAndSetIRPfS_jjifffiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z23kernelAndSetIRAndSourcePfS_jjifffiiiiS_f.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7kernel2PfS_jjfff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7kernel2PfS_jjfff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
