__device__ float minmod(float a, float b, float c)
{
	float ab = fminf(fabsf(a), fabs(b)) * (copysignf(1.0f, a) + copysignf(1.0f, b)) * 0.5f;
	return fminf(fabsf(ab), fabsf(c)) * (copysignf(1.0f, ab) + copysignf(1.0f, c)) * 0.5f;
}
    
    
__global__ void ReconstructFreeSurface(float *U, float *BottomIntPts, float *UIntPts, float *huvIntPts, int m, int n, float dx, float dy)
{
	// Calculate the row and column of the thread within the thread block
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	
	// Calculate the index of the up, down, left, right terrain elevation values in the BottomIntPts vector
	// 	Note: We only need elevation values from two point on opposite sides of the cell
	//	      because the bottom is piecewise-bilinear, which guarantees that the average
	// 	      of both sets of points on opposing sides of the cell is equal to the value
	//	      at the center of the cell.
	int upTerrainIndex = (row+1)*(n+1)*2 + col*2;
	int downTerrainIndex = row*(n+1)*2 + col*2;
	int leftTerrainIndex = row*(n+1)*2 + col*2 + 1;
	int rightTerrainIndex = row*(n+1)*2 + (col+1)*2 + 1;
	
	// Before performing calculations for a timestep, we need to reset any residual values left over
	// from previous calculations in case a cell goes from wet to dry. In the case of a cell going
	// from wet to dry, the values of huvIntPts and UIntPts for that cell would otherwise remain at the 
	// values from the previous timestep when the cell was wet, causing errors.
	// 	huvIntPts: set h = u = v = 0
	//	UIntPts: set w = ground elevation, u = v = 0
	int cellIntPtIndex = row*n*4*3 + col*4*3;
	
	if (row < m && col < n)
	{
		for (int i=0; i<4; i++)
		{
			for (int j=0; j<3; j++)
			{
				huvIntPts[cellIntPtIndex + i*3 + j] = 0.0f;
				if (j > 0)
				{
					UIntPts[cellIntPtIndex + i*3 + j] = 0.0f;
				}
			}
		}
	
		UIntPts[cellIntPtIndex + 0*3] = BottomIntPts[upTerrainIndex];
		UIntPts[cellIntPtIndex + 1*3] = BottomIntPts[downTerrainIndex];
		UIntPts[cellIntPtIndex + 2*3] = BottomIntPts[rightTerrainIndex];
		UIntPts[cellIntPtIndex + 3*3] = BottomIntPts[leftTerrainIndex];
	}

	// First check if the thread is operating on a cell inside of the block's one cell deep ghost cells
	if (col > 0 && row > 0 && col < n-1 && row < m-1)
	{
	
		// Calculate the index of the cell in the U vector
		int wIndex = row*n*3 + col*3 + 0;
	
		// Now check if the cell has water (evaluates to true if it does)
		// TODO: It may be necessary to have an else statement as well. If a cell goes
		//	 from wet to dry, the value of w may drop below the ground level, so
		//	 if the cell needs to get wet again, the water level will have to increase
		//	 from that value, not from ground level
		if (U[wIndex] > (BottomIntPts[leftTerrainIndex] + BottomIntPts[rightTerrainIndex])/2.0f) 
		{
			float N[3], S[3], E[3], W[3]; // These are the [w, hu, hv] vectors
			float north[3], south[3], east[3], west[3]; // These are the [h, u, v] vectors
			
			float forward, central, backward, slope;
			float Kappa = 0.01f * fmaxf(1.0f, fminf(dx, dy));
			float sqrt2 = sqrtf(2.0f);
			
			// Calculate indices of cells surrounding the current cell in the U vector
			int upIndex = (row+1)*n*3 + col*3;
			int downIndex = (row-1)*n*3 + col*3;
			int leftIndex = row*n*3 + (col-1)*3;
			int rightIndex = row*n*3 + (col+1)*3;
			
			// Reconstruct the free surface so that it is sloped based on the free surface height of adjacent cells
			for (int i=0; i<3; i++)
			{
				// North and South
				forward = (U[upIndex+i] - U[wIndex+i])/dy;
				central = (U[upIndex+i] - U[downIndex+i])/(2.0f*dy);
				backward = (U[wIndex+i] - U[downIndex+i])/dy;
				slope = minmod(1.3f*forward, central, 1.3f*backward);
				
				N[i] = U[wIndex+i] + (dy/2.0f)*slope;
				S[i] = U[wIndex+i] - (dy/2.0f)*slope;
				
				// East and West
				forward = (U[rightIndex+i] - U[wIndex+i])/dx;
				central = (U[rightIndex+i] - U[leftIndex+i])/(2.0f*dx);
				backward = (U[wIndex+i] - U[leftIndex+i])/dx;
				slope = minmod(1.3f*forward, central, 1.3f*backward);
				
				E[i] = U[wIndex+i] + (dx/2.0f)*slope;
				W[i] = U[wIndex+i] - (dx/2.0f)*slope;
			}
			
			// Check the water free surface at the cell interfaces for positivity and correct if necessary
			if (N[0] < BottomIntPts[upTerrainIndex])
			{
				N[0] = BottomIntPts[upTerrainIndex];
				S[0] = 2*U[wIndex] - BottomIntPts[upTerrainIndex];
			}
			else if (S[0] < BottomIntPts[downTerrainIndex])
			{
				S[0] = BottomIntPts[downTerrainIndex];
				N[0] = 2*U[wIndex] - BottomIntPts[downTerrainIndex];
			}
			if (E[0] < BottomIntPts[rightTerrainIndex])
			{
				E[0] = BottomIntPts[rightTerrainIndex];
				W[0] = 2*U[wIndex] - BottomIntPts[rightTerrainIndex];
			}
			else if (W[0] < BottomIntPts[leftTerrainIndex])
			{
				W[0] = BottomIntPts[leftTerrainIndex];
				E[0] = 2*U[wIndex] - BottomIntPts[leftTerrainIndex];
			}
			
			// Calculate the values of h, u, and v using the damping calculations for u and v
			north[0] = N[0] - BottomIntPts[upTerrainIndex];
			south[0] = S[0] - BottomIntPts[downTerrainIndex];
			east[0] = E[0] - BottomIntPts[rightTerrainIndex];
			west[0] = W[0] - BottomIntPts[leftTerrainIndex];
			
			for (int i=1; i<3; i++)
			{
				north[i] = (sqrt2 * north[0] * N[i]) / sqrtf(powf(north[0], 4.0f) + fmaxf(powf(north[0], 4.0f), Kappa));
				south[i] = (sqrt2 * south[0] * S[i]) / sqrtf(powf(south[0], 4.0f) + fmaxf(powf(south[0], 4.0f), Kappa));
				east[i] = (sqrt2 * east[0] * E[i]) / sqrtf(powf(east[0], 4.0f) + fmaxf(powf(east[0], 4.0f), Kappa));
				west[i] = (sqrt2 * west[0] * W[i]) / sqrtf(powf(west[0], 4.0f) + fmaxf(powf(west[0], 4.0f), Kappa));
			}
			
			// Update the values of hu and hv based on new values of u and v
			for (int i=1; i<3; i++)
			{
				N[i] = north[0] * north[i];
				S[i] = south[0] * south[i];
				E[i] = east[0] * east[i];
				W[i] = west[0] * west[i];
			}
			
			// Put the calculated interface values into global memory
			for (int i=0; i<3; i++)
			{
				UIntPts[cellIntPtIndex + 0*3 + i] = N[i];
				UIntPts[cellIntPtIndex + 1*3 + i] = S[i];
				UIntPts[cellIntPtIndex + 2*3 + i] = E[i];
				UIntPts[cellIntPtIndex + 3*3 + i] = W[i];
				
				huvIntPts[cellIntPtIndex + 0*3 + i] = north[i];
				huvIntPts[cellIntPtIndex + 1*3 + i] = south[i];
				huvIntPts[cellIntPtIndex + 2*3 + i] = east[i];
				huvIntPts[cellIntPtIndex + 3*3 + i] = west[i];
			}
			
			// End the kernel here. The values of the conserved variable [h, u, v] need to be stored
			// in global memory for the entire domain before we can begin calculating propagation speeds.
		}
	}
}


__global__ void CalculatePropSpeeds(float *UIntPts, float *huvIntPts, float *propSpeeds, int m, int n)
{
	// Calculate the row and column of the thread within the thread block
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	
	// Constants
	float g = 9.81f;
	
	// Get rid of any residual values in the propSpeeds matrix in case
	// a cell has gone from wet to dry in the previous timestep
	for (int i=0; i<4; i++)
	{
		propSpeeds[row*n*4 + col*4 + i] = 0.0f;
	}
	
	// First check if the thread is operating on a cell inside of the block's one cell deep ghost cells
	if (col > 0 && row > 0 && col < n-1 && row < m-1)
	{
		
		// Make sure cell is wet by making sure at least one value of h is greater than 0
		float hNorth = huvIntPts[row*n*4*3 + col*4*3 + 0*3];		// value of h at the north interface of the current cell
		float hSouth = huvIntPts[(row+1)*n*4*3 + col*4*3 + 1*3];	// value of h at the south interface of the cell above
		float hEast = huvIntPts[row*n*4*3 + col*4*3 + 2*3];		// value of h at the east interface of the current cell
		float hWest = huvIntPts[row*n*4*3 + (col+1)*4*3 + 3*3];		// value of h at the west interface of the cell to the right
		if (hNorth > 0.0f || hSouth > 0.0f || hEast > 0.0f || hWest > 0.0f)
		{
			// Get the rest of the values needed from huvIntPts
			float vNorth = huvIntPts[row*n*4*3 + col*4*3 + 0*3 + 1];	// value of v at the north interface of the current cell
			float vSouth = huvIntPts[(row+1)*n*4*3 + col*4*3 + 1*3 + 1];	// value of v at the south interface of the cell above
			float uEast = huvIntPts[row*n*4*3 + col*4*3 + 2*3 + 1];		// value of u at the east interface of the current cell
			float uWest = huvIntPts[row*n*4*3 + (col+1)*4*3 + 3*3 + 1];	// value of u at the west interface of the cell to the right
		
			// Each cell in propSpeeds contains four values [N, S, E, W]
			// Each thread will calculate the N, E values of it's own cell, the S of the cell above, and the W of
			// the cell to the right.
			int N = row*n*4 + col*4 + 0;	// North value of this cell
			int S = (row+1)*n*4 + col*4 + 1;// South value of cell above
			int E = row*n*4 + col*4 + 2;	// East value of this cell
			int W = row*n*4 + (col+1)*4 + 3;// West value of cell to the right
		
			// Calculate north propagation speed of the current cell
			propSpeeds[N] = fminf(fminf(vNorth - sqrtf(g*hNorth), vSouth - sqrtf(g*hSouth)), 0.0f);
		
			// Calculate south propagation speed of the cell above
			propSpeeds[S] = fmaxf(fmaxf(vNorth + sqrtf(g*hNorth), vSouth + sqrtf(g*hSouth)), 0.0f);
		
			// Calculate east propagation speed of the current cell
			propSpeeds[E] = fminf(fminf(uEast - sqrtf(g*hEast), uWest - sqrtf(g*hWest)), 0.0f);
		
			// Calculate west propagation speed of the cell to the right
			propSpeeds[W] = fmaxf(fmaxf(uEast + sqrtf(g*hEast), uWest + sqrtf(g*hWest)), 0.0f);
		}
	}
}

	.file	"tmpxft_0029c06e_00000000-6_spacialDiscretization.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6minmodfff
	.type	_Z6minmodfff, @function
_Z6minmodfff:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z6minmodfff, .-_Z6minmodfff
	.globl	_Z52__device_stub__Z22ReconstructFreeSurfacePfS_S_S_iiffPfS_S_S_iiff
	.type	_Z52__device_stub__Z22ReconstructFreeSurfacePfS_S_S_iiffPfS_S_S_iiff, @function
_Z52__device_stub__Z22ReconstructFreeSurfacePfS_S_S_iiffPfS_S_S_iiff:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 4(%rsp)
	movss	%xmm1, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z22ReconstructFreeSurfacePfS_S_S_iiff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z52__device_stub__Z22ReconstructFreeSurfacePfS_S_S_iiffPfS_S_S_iiff, .-_Z52__device_stub__Z22ReconstructFreeSurfacePfS_S_S_iiffPfS_S_S_iiff
	.globl	_Z22ReconstructFreeSurfacePfS_S_S_iiff
	.type	_Z22ReconstructFreeSurfacePfS_S_S_iiff, @function
_Z22ReconstructFreeSurfacePfS_S_S_iiff:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z22ReconstructFreeSurfacePfS_S_S_iiffPfS_S_S_iiff
	.cfi_endproc
.LFE2034:
	.size	_Z22ReconstructFreeSurfacePfS_S_S_iiff, .-_Z22ReconstructFreeSurfacePfS_S_S_iiff
	.globl	_Z45__device_stub__Z19CalculatePropSpeedsPfS_S_iiPfS_S_ii
	.type	_Z45__device_stub__Z19CalculatePropSpeedsPfS_S_iiPfS_S_ii, @function
_Z45__device_stub__Z19CalculatePropSpeedsPfS_S_iiPfS_S_ii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19CalculatePropSpeedsPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z45__device_stub__Z19CalculatePropSpeedsPfS_S_iiPfS_S_ii, .-_Z45__device_stub__Z19CalculatePropSpeedsPfS_S_iiPfS_S_ii
	.globl	_Z19CalculatePropSpeedsPfS_S_ii
	.type	_Z19CalculatePropSpeedsPfS_S_ii, @function
_Z19CalculatePropSpeedsPfS_S_ii:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z19CalculatePropSpeedsPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2036:
	.size	_Z19CalculatePropSpeedsPfS_S_ii, .-_Z19CalculatePropSpeedsPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19CalculatePropSpeedsPfS_S_ii"
.LC1:
	.string	"_Z22ReconstructFreeSurfacePfS_S_S_iiff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19CalculatePropSpeedsPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22ReconstructFreeSurfacePfS_S_S_iiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__ float minmod(float a, float b, float c)
{
	float ab = fminf(fabsf(a), fabs(b)) * (copysignf(1.0f, a) + copysignf(1.0f, b)) * 0.5f;
	return fminf(fabsf(ab), fabsf(c)) * (copysignf(1.0f, ab) + copysignf(1.0f, c)) * 0.5f;
}
    
    
__global__ void ReconstructFreeSurface(float *U, float *BottomIntPts, float *UIntPts, float *huvIntPts, int m, int n, float dx, float dy)
{
	// Calculate the row and column of the thread within the thread block
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	
	// Calculate the index of the up, down, left, right terrain elevation values in the BottomIntPts vector
	// 	Note: We only need elevation values from two point on opposite sides of the cell
	//	      because the bottom is piecewise-bilinear, which guarantees that the average
	// 	      of both sets of points on opposing sides of the cell is equal to the value
	//	      at the center of the cell.
	int upTerrainIndex = (row+1)*(n+1)*2 + col*2;
	int downTerrainIndex = row*(n+1)*2 + col*2;
	int leftTerrainIndex = row*(n+1)*2 + col*2 + 1;
	int rightTerrainIndex = row*(n+1)*2 + (col+1)*2 + 1;
	
	// Before performing calculations for a timestep, we need to reset any residual values left over
	// from previous calculations in case a cell goes from wet to dry. In the case of a cell going
	// from wet to dry, the values of huvIntPts and UIntPts for that cell would otherwise remain at the 
	// values from the previous timestep when the cell was wet, causing errors.
	// 	huvIntPts: set h = u = v = 0
	//	UIntPts: set w = ground elevation, u = v = 0
	int cellIntPtIndex = row*n*4*3 + col*4*3;
	
	if (row < m && col < n)
	{
		for (int i=0; i<4; i++)
		{
			for (int j=0; j<3; j++)
			{
				huvIntPts[cellIntPtIndex + i*3 + j] = 0.0f;
				if (j > 0)
				{
					UIntPts[cellIntPtIndex + i*3 + j] = 0.0f;
				}
			}
		}
	
		UIntPts[cellIntPtIndex + 0*3] = BottomIntPts[upTerrainIndex];
		UIntPts[cellIntPtIndex + 1*3] = BottomIntPts[downTerrainIndex];
		UIntPts[cellIntPtIndex + 2*3] = BottomIntPts[rightTerrainIndex];
		UIntPts[cellIntPtIndex + 3*3] = BottomIntPts[leftTerrainIndex];
	}

	// First check if the thread is operating on a cell inside of the block's one cell deep ghost cells
	if (col > 0 && row > 0 && col < n-1 && row < m-1)
	{
	
		// Calculate the index of the cell in the U vector
		int wIndex = row*n*3 + col*3 + 0;
	
		// Now check if the cell has water (evaluates to true if it does)
		// TODO: It may be necessary to have an else statement as well. If a cell goes
		//	 from wet to dry, the value of w may drop below the ground level, so
		//	 if the cell needs to get wet again, the water level will have to increase
		//	 from that value, not from ground level
		if (U[wIndex] > (BottomIntPts[leftTerrainIndex] + BottomIntPts[rightTerrainIndex])/2.0f) 
		{
			float N[3], S[3], E[3], W[3]; // These are the [w, hu, hv] vectors
			float north[3], south[3], east[3], west[3]; // These are the [h, u, v] vectors
			
			float forward, central, backward, slope;
			float Kappa = 0.01f * fmaxf(1.0f, fminf(dx, dy));
			float sqrt2 = sqrtf(2.0f);
			
			// Calculate indices of cells surrounding the current cell in the U vector
			int upIndex = (row+1)*n*3 + col*3;
			int downIndex = (row-1)*n*3 + col*3;
			int leftIndex = row*n*3 + (col-1)*3;
			int rightIndex = row*n*3 + (col+1)*3;
			
			// Reconstruct the free surface so that it is sloped based on the free surface height of adjacent cells
			for (int i=0; i<3; i++)
			{
				// North and South
				forward = (U[upIndex+i] - U[wIndex+i])/dy;
				central = (U[upIndex+i] - U[downIndex+i])/(2.0f*dy);
				backward = (U[wIndex+i] - U[downIndex+i])/dy;
				slope = minmod(1.3f*forward, central, 1.3f*backward);
				
				N[i] = U[wIndex+i] + (dy/2.0f)*slope;
				S[i] = U[wIndex+i] - (dy/2.0f)*slope;
				
				// East and West
				forward = (U[rightIndex+i] - U[wIndex+i])/dx;
				central = (U[rightIndex+i] - U[leftIndex+i])/(2.0f*dx);
				backward = (U[wIndex+i] - U[leftIndex+i])/dx;
				slope = minmod(1.3f*forward, central, 1.3f*backward);
				
				E[i] = U[wIndex+i] + (dx/2.0f)*slope;
				W[i] = U[wIndex+i] - (dx/2.0f)*slope;
			}
			
			// Check the water free surface at the cell interfaces for positivity and correct if necessary
			if (N[0] < BottomIntPts[upTerrainIndex])
			{
				N[0] = BottomIntPts[upTerrainIndex];
				S[0] = 2*U[wIndex] - BottomIntPts[upTerrainIndex];
			}
			else if (S[0] < BottomIntPts[downTerrainIndex])
			{
				S[0] = BottomIntPts[downTerrainIndex];
				N[0] = 2*U[wIndex] - BottomIntPts[downTerrainIndex];
			}
			if (E[0] < BottomIntPts[rightTerrainIndex])
			{
				E[0] = BottomIntPts[rightTerrainIndex];
				W[0] = 2*U[wIndex] - BottomIntPts[rightTerrainIndex];
			}
			else if (W[0] < BottomIntPts[leftTerrainIndex])
			{
				W[0] = BottomIntPts[leftTerrainIndex];
				E[0] = 2*U[wIndex] - BottomIntPts[leftTerrainIndex];
			}
			
			// Calculate the values of h, u, and v using the damping calculations for u and v
			north[0] = N[0] - BottomIntPts[upTerrainIndex];
			south[0] = S[0] - BottomIntPts[downTerrainIndex];
			east[0] = E[0] - BottomIntPts[rightTerrainIndex];
			west[0] = W[0] - BottomIntPts[leftTerrainIndex];
			
			for (int i=1; i<3; i++)
			{
				north[i] = (sqrt2 * north[0] * N[i]) / sqrtf(powf(north[0], 4.0f) + fmaxf(powf(north[0], 4.0f), Kappa));
				south[i] = (sqrt2 * south[0] * S[i]) / sqrtf(powf(south[0], 4.0f) + fmaxf(powf(south[0], 4.0f), Kappa));
				east[i] = (sqrt2 * east[0] * E[i]) / sqrtf(powf(east[0], 4.0f) + fmaxf(powf(east[0], 4.0f), Kappa));
				west[i] = (sqrt2 * west[0] * W[i]) / sqrtf(powf(west[0], 4.0f) + fmaxf(powf(west[0], 4.0f), Kappa));
			}
			
			// Update the values of hu and hv based on new values of u and v
			for (int i=1; i<3; i++)
			{
				N[i] = north[0] * north[i];
				S[i] = south[0] * south[i];
				E[i] = east[0] * east[i];
				W[i] = west[0] * west[i];
			}
			
			// Put the calculated interface values into global memory
			for (int i=0; i<3; i++)
			{
				UIntPts[cellIntPtIndex + 0*3 + i] = N[i];
				UIntPts[cellIntPtIndex + 1*3 + i] = S[i];
				UIntPts[cellIntPtIndex + 2*3 + i] = E[i];
				UIntPts[cellIntPtIndex + 3*3 + i] = W[i];
				
				huvIntPts[cellIntPtIndex + 0*3 + i] = north[i];
				huvIntPts[cellIntPtIndex + 1*3 + i] = south[i];
				huvIntPts[cellIntPtIndex + 2*3 + i] = east[i];
				huvIntPts[cellIntPtIndex + 3*3 + i] = west[i];
			}
			
			// End the kernel here. The values of the conserved variable [h, u, v] need to be stored
			// in global memory for the entire domain before we can begin calculating propagation speeds.
		}
	}
}


__global__ void CalculatePropSpeeds(float *UIntPts, float *huvIntPts, float *propSpeeds, int m, int n)
{
	// Calculate the row and column of the thread within the thread block
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	
	// Constants
	float g = 9.81f;
	
	// Get rid of any residual values in the propSpeeds matrix in case
	// a cell has gone from wet to dry in the previous timestep
	for (int i=0; i<4; i++)
	{
		propSpeeds[row*n*4 + col*4 + i] = 0.0f;
	}
	
	// First check if the thread is operating on a cell inside of the block's one cell deep ghost cells
	if (col > 0 && row > 0 && col < n-1 && row < m-1)
	{
		
		// Make sure cell is wet by making sure at least one value of h is greater than 0
		float hNorth = huvIntPts[row*n*4*3 + col*4*3 + 0*3];		// value of h at the north interface of the current cell
		float hSouth = huvIntPts[(row+1)*n*4*3 + col*4*3 + 1*3];	// value of h at the south interface of the cell above
		float hEast = huvIntPts[row*n*4*3 + col*4*3 + 2*3];		// value of h at the east interface of the current cell
		float hWest = huvIntPts[row*n*4*3 + (col+1)*4*3 + 3*3];		// value of h at the west interface of the cell to the right
		if (hNorth > 0.0f || hSouth > 0.0f || hEast > 0.0f || hWest > 0.0f)
		{
			// Get the rest of the values needed from huvIntPts
			float vNorth = huvIntPts[row*n*4*3 + col*4*3 + 0*3 + 1];	// value of v at the north interface of the current cell
			float vSouth = huvIntPts[(row+1)*n*4*3 + col*4*3 + 1*3 + 1];	// value of v at the south interface of the cell above
			float uEast = huvIntPts[row*n*4*3 + col*4*3 + 2*3 + 1];		// value of u at the east interface of the current cell
			float uWest = huvIntPts[row*n*4*3 + (col+1)*4*3 + 3*3 + 1];	// value of u at the west interface of the cell to the right
		
			// Each cell in propSpeeds contains four values [N, S, E, W]
			// Each thread will calculate the N, E values of it's own cell, the S of the cell above, and the W of
			// the cell to the right.
			int N = row*n*4 + col*4 + 0;	// North value of this cell
			int S = (row+1)*n*4 + col*4 + 1;// South value of cell above
			int E = row*n*4 + col*4 + 2;	// East value of this cell
			int W = row*n*4 + (col+1)*4 + 3;// West value of cell to the right
		
			// Calculate north propagation speed of the current cell
			propSpeeds[N] = fminf(fminf(vNorth - sqrtf(g*hNorth), vSouth - sqrtf(g*hSouth)), 0.0f);
		
			// Calculate south propagation speed of the cell above
			propSpeeds[S] = fmaxf(fmaxf(vNorth + sqrtf(g*hNorth), vSouth + sqrtf(g*hSouth)), 0.0f);
		
			// Calculate east propagation speed of the current cell
			propSpeeds[E] = fminf(fminf(uEast - sqrtf(g*hEast), uWest - sqrtf(g*hWest)), 0.0f);
		
			// Calculate west propagation speed of the cell to the right
			propSpeeds[W] = fmaxf(fmaxf(uEast + sqrtf(g*hEast), uWest + sqrtf(g*hWest)), 0.0f);
		}
	}
}

	.text
	.file	"spacialDiscretization.hip"
	.globl	_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff # -- Begin function _Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff
	.type	_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff,@function
_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff: # @_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	movq	%rsp, %r10
	movss	%xmm1, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22ReconstructFreeSurfacePfS_S_S_iiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff, .Lfunc_end0-_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__CalculatePropSpeedsPfS_S_ii # -- Begin function _Z34__device_stub__CalculatePropSpeedsPfS_S_ii
	.type	_Z34__device_stub__CalculatePropSpeedsPfS_S_ii,@function
_Z34__device_stub__CalculatePropSpeedsPfS_S_ii: # @_Z34__device_stub__CalculatePropSpeedsPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19CalculatePropSpeedsPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__CalculatePropSpeedsPfS_S_ii, .Lfunc_end1-_Z34__device_stub__CalculatePropSpeedsPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22ReconstructFreeSurfacePfS_S_S_iiff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19CalculatePropSpeedsPfS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22ReconstructFreeSurfacePfS_S_S_iiff,@object # @_Z22ReconstructFreeSurfacePfS_S_S_iiff
	.section	.rodata,"a",@progbits
	.globl	_Z22ReconstructFreeSurfacePfS_S_S_iiff
	.p2align	3, 0x0
_Z22ReconstructFreeSurfacePfS_S_S_iiff:
	.quad	_Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff
	.size	_Z22ReconstructFreeSurfacePfS_S_S_iiff, 8

	.type	_Z19CalculatePropSpeedsPfS_S_ii,@object # @_Z19CalculatePropSpeedsPfS_S_ii
	.globl	_Z19CalculatePropSpeedsPfS_S_ii
	.p2align	3, 0x0
_Z19CalculatePropSpeedsPfS_S_ii:
	.quad	_Z34__device_stub__CalculatePropSpeedsPfS_S_ii
	.size	_Z19CalculatePropSpeedsPfS_S_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z22ReconstructFreeSurfacePfS_S_S_iiff"
	.size	.L__unnamed_1, 39

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19CalculatePropSpeedsPfS_S_ii"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__ReconstructFreeSurfacePfS_S_S_iiff
	.addrsig_sym _Z34__device_stub__CalculatePropSpeedsPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22ReconstructFreeSurfacePfS_S_S_iiff
	.addrsig_sym _Z19CalculatePropSpeedsPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22ReconstructFreeSurfacePfS_S_S_iiff ; -- Begin function _Z22ReconstructFreeSurfacePfS_S_S_iiff
	.globl	_Z22ReconstructFreeSurfacePfS_S_S_iiff
	.p2align	8
	.type	_Z22ReconstructFreeSurfacePfS_S_S_iiff,@function
_Z22ReconstructFreeSurfacePfS_S_S_iiff: ; @_Z22ReconstructFreeSurfacePfS_S_S_iiff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v15, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	s_mul_i32 s2, s14, s2
	s_load_b256 s[12:19], s[0:1], 0x0
	v_add_nc_u32_e32 v3, s2, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v2
	v_cmp_gt_i32_e32 vcc_lo, s5, v3
	v_cmp_gt_i32_e64 s0, s4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, v2, s5, v[3:4]
	v_mad_u64_u32 v[6:7], null, v4, s5, v[4:5]
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_lshl_u32 v5, v0, v2, 1
	v_mul_lo_u32 v9, v0, 12
	v_add_lshl_u32 v12, v6, v3, 1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 2, v5
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.preheader306.preheader
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	s_mov_b64 s[0:1], 0
	v_lshlrev_b64 v[13:14], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s16, v13
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v14, vcc_lo
	v_add_co_u32 v1, vcc_lo, s18, v13
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v14, vcc_lo
	v_mov_b32_e32 v13, 0
.LBB0_2:                                ; %.preheader306
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v1, s0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v18, vcc_lo, v10, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v14, v13
	v_add_co_ci_u32_e32 v19, vcc_lo, s1, v11, vcc_lo
	s_add_u32 s0, s0, 12
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 48
	global_store_b64 v[16:17], v[13:14], off
	global_store_b32 v[18:19], v13, off offset:4
	global_store_b32 v[16:17], v13, off offset:8
	global_store_b32 v[18:19], v13, off offset:8
	s_cbranch_scc1 .LBB0_2
; %bb.3:
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[13:14], 2, v[12:13]
	v_lshlrev_b64 v[16:17], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s14, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v14, vcc_lo
	global_load_b32 v1, v[13:14], off
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s14, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v14, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v17, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v1, off
	global_load_b32 v1, v[13:14], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v1, off offset:12
	global_load_b32 v1, v[16:17], off offset:4
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v1, off offset:24
	global_load_b32 v1, v[13:14], off offset:4
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v1, off offset:36
.LBB0_4:                                ; %Flow524
	s_or_b32 exec_lo, exec_lo, s3
	v_min_i32_e32 v1, v2, v3
	s_add_i32 s0, s5, -1
	s_add_i32 s1, s4, -1
	v_cmp_gt_i32_e32 vcc_lo, s0, v3
	v_cmp_gt_i32_e64 s0, s1, v2
	v_cmp_lt_i32_e64 s1, 0, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_26
; %bb.5:
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshl_add_u32 v0, v0, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s14, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v8, vcc_lo
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_clause 0x1
	global_load_b32 v21, v[10:11], off offset:4
	global_load_b32 v22, v[5:6], off offset:4
	v_add_co_u32 v13, vcc_lo, s12, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v8, vcc_lo
	global_load_b32 v23, v[13:14], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v1, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0.5, v1
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v23, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_26
; %bb.6:
	v_mad_u64_u32 v[5:6], null, v4, s5, v[3:4]
	v_add_nc_u32_e32 v2, -1, v2
	v_mul_u32_u24_e32 v4, 3, v15
	s_mul_i32 s2, s2, 3
	v_add_f32_e64 v24, s7, s7
	v_mul_f32_e64 v25, s7, 0.5
	v_mul_lo_u32 v3, s5, v2
	v_lshl_add_u32 v1, v5, 1, v5
	v_add_f32_e64 v26, s6, s6
	v_mul_f32_e64 v27, s6, 0.5
	s_mov_b64 s[8:9], 0
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshl_add_u32 v3, v3, 1, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v28, v3, s2, v4
	v_add_co_u32 v15, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v2, vcc_lo
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2
                                        ; implicit-def: $vgpr2_vgpr3_vgpr4
                                        ; implicit-def: $vgpr2_vgpr3_vgpr4
                                        ; implicit-def: $vgpr4_vgpr5_vgpr6
                                        ; implicit-def: $vgpr4_vgpr5_vgpr6
                                        ; implicit-def: $vgpr6_vgpr7_vgpr8
                                        ; implicit-def: $vgpr6_vgpr7_vgpr8
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v35, v[15:16], off
	v_add_nc_u32_e32 v30, s8, v0
	v_add_nc_u32_e32 v29, s8, v28
	global_load_b32 v36, v[13:14], off
	s_cmp_eq_u32 s8, 2
	v_add_nc_u32_e32 v31, 3, v30
	v_add_nc_u32_e32 v33, -3, v30
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v32, 31, v31
	v_ashrrev_i32_e32 v34, 31, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_lshlrev_b64 v[31:32], 2, v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[33:34], 2, v[33:34]
	v_add_co_u32 v29, vcc_lo, s12, v29
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v30, vcc_lo
	global_load_b32 v37, v[29:30], off
	v_add_co_u32 v29, vcc_lo, s12, v31
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v32, vcc_lo
	v_add_co_u32 v31, vcc_lo, s12, v33
	v_add_co_ci_u32_e32 v32, vcc_lo, s13, v34, vcc_lo
	s_clause 0x1
	global_load_b32 v29, v[29:30], off
	global_load_b32 v30, v[31:32], off
	v_add_co_u32 v13, vcc_lo, v13, 4
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v15, vcc_lo, v15, 4
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v31, v35, v36
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v35, v35, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_scale_f32 v39, s0, v35, v24, v35
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v42, v29, v36
	v_div_scale_f32 v47, s2, v42, s6, v42
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v29, v29, v30
	v_sub_f32_e32 v30, v36, v30
	v_div_scale_f32 v32, null, s7, s7, v31
	v_div_scale_f32 v33, vcc_lo, v31, s7, v31
	v_div_scale_f32 v46, null, s6, s6, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v34, v32
	v_div_scale_f32 v48, null, v26, v26, v29
	v_rcp_f32_e32 v53, v46
	v_div_scale_f32 v50, null, s6, s6, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v54, v48
	v_div_scale_f32 v51, s4, v30, s6, v30
	v_rcp_f32_e32 v55, v50
	v_fma_f32 v38, -v32, v34, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v34, v38, v34
	v_div_scale_f32 v38, null, v24, v24, v35
	v_mul_f32_e32 v43, v33, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v44, v38
	v_fma_f32 v52, -v32, v43, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v43, v52, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v52, -v38, v44, 1.0
	v_fma_f32 v32, -v32, v43, v33
	v_fmac_f32_e32 v44, v52, v44
	v_sub_f32_e32 v37, v36, v37
	v_fma_f32 v33, -v46, v53, 1.0
	v_fma_f32 v52, -v48, v54, 1.0
	v_div_fmas_f32 v32, v32, v34, v43
	v_mul_f32_e32 v34, v39, v44
	v_div_scale_f32 v40, null, s7, s7, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v53, v33, v53 :: v_dual_fmac_f32 v54, v52, v54
	v_div_scale_f32 v41, s1, v37, s7, v37
	v_rcp_f32_e32 v45, v40
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f32_e32 v52, v47, v53
	v_div_scale_f32 v49, s3, v29, v26, v29
	v_div_fixup_f32 v31, v32, s7, v31
	v_fma_f32 v32, -v38, v34, v39
	s_mov_b32 vcc_lo, s0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v56, -v40, v45, 1.0
	v_fmac_f32_e32 v34, v32, v44
	v_fma_f32 v32, -v46, v52, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v45, v56, v45
	v_fma_f32 v56, -v50, v55, 1.0
	v_fma_f32 v38, -v38, v34, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v52, v32, v53
	v_dual_fmac_f32 v55, v56, v55 :: v_dual_mul_f32 v56, v49, v54
	v_mul_f32_e32 v43, v41, v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v32, v38, v44, v34
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v33, -v40, v43, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v32, v32, v24, v35
	v_fmac_f32_e32 v43, v33, v45
	v_fma_f32 v33, -v48, v56, v49
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v40, v43, v41
	v_dual_fmac_f32 v56, v33, v54 :: v_dual_mul_f32 v57, v51, v55
	v_fma_f32 v33, -v46, v52, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v39, v39, v45, v43
	v_fma_f32 v34, -v48, v56, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v58, -v50, v57, v51
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v33, v33, v53, v52
	s_mov_b32 vcc_lo, s3
	v_fmac_f32_e32 v57, v58, v55
	v_div_fmas_f32 v34, v34, v54, v56
	s_mov_b32 vcc_lo, s4
	v_div_fixup_f32 v35, v39, s7, v37
	v_div_fixup_f32 v33, v33, s6, v42
	v_fma_f32 v38, -v50, v57, v51
	v_div_fixup_f32 v29, v34, v26, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v37, v38, v55, v57
	s_cselect_b32 vcc_lo, -1, 0
	v_mul_f32_e32 v33, 0x3fa66666, v33
	s_cmp_eq_u32 s8, 1
	v_div_fixup_f32 v30, v37, s6, v30
	v_bfi_b32 v37, 0x7fffffff, 1.0, v29
	v_mul_f32_e32 v31, 0x3fa66666, v31
	v_min_f32_e64 v29, |v33|, |v29|
	s_cselect_b32 s0, -1, 0
	v_mul_f32_e32 v30, 0x3fa66666, v30
	s_cmp_eq_u32 s8, 0
	v_bfi_b32 v59, 0x7fffffff, 1.0, v31
	v_min_f32_e64 v31, |v31|, |v32|
	v_bfi_b32 v32, 0x7fffffff, 1.0, v32
	s_cselect_b32 s1, -1, 0
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s8, 3
	v_add_f32_e32 v32, v59, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v31, v31, v32
	v_bfi_b32 v32, 0x7fffffff, 1.0, v33
	v_bfi_b32 v33, 0x7fffffff, 1.0, v30
	v_add_f32_e32 v32, v32, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v29, v32
	v_mul_f32_e32 v29, 0.5, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min_f32_e64 v30, |v29|, |v30|
	v_bfi_b32 v29, 0x7fffffff, 1.0, v29
	v_add_f32_e32 v29, v33, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v30, v29
	v_mul_f32_e32 v29, 0.5, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v30, v27, v29, v36
	v_fma_f32 v29, -v27, v29, v36
	v_cndmask_b32_e32 v4, v4, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v2, v2, v29 :: v_dual_mul_f32 v31, 0.5, v31
	v_cndmask_b32_e64 v3, v3, v30, s0
	v_cndmask_b32_e64 v18, v18, v30, s1
	v_cndmask_b32_e64 v1, v1, v29, s0
	v_cndmask_b32_e64 v20, v20, v29, s1
	v_bfi_b32 v37, 0x7fffffff, 1.0, v31
	v_mul_f32_e32 v35, 0x3fa66666, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v34, 0x7fffffff, 1.0, v35
	v_add_f32_e32 v32, v34, v37
	v_min_f32_e64 v31, |v31|, |v35|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v31, v31, v32
	v_mul_f32_e32 v31, 0.5, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v32, v25, v31, v36
	v_fma_f32 v31, -v25, v31, v36
	v_cndmask_b32_e32 v8, v8, v32, vcc_lo
	v_cndmask_b32_e64 v7, v7, v32, s0
	v_cndmask_b32_e64 v17, v17, v32, s1
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v6, v31, vcc_lo
	v_cndmask_b32_e64 v5, v5, v31, s0
	v_cndmask_b32_e64 v19, v19, v31, s1
	s_cbranch_scc0 .LBB0_7
; %bb.8:
	v_ashrrev_i32_e32 v13, 31, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s14, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v13, vcc_lo
	global_load_b32 v0, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_nlt_f32_e32 v17, v0
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_12
; %bb.9:
	global_load_b32 v12, v[10:11], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 v19, v12
; %bb.10:
	v_fma_f32 v17, v23, 2.0, -v12
	v_mov_b32_e32 v19, v12
; %bb.11:                               ; %Flow521
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_12:                               ; %Flow522
	s_and_not1_saveexec_b32 s0, s0
; %bb.13:
	v_mov_b32_e32 v17, v0
	v_fma_f32 v19, v23, 2.0, -v0
; %bb.14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_nlt_f32_e32 v18, v22
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.15:
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_f32_e32 v20, v21
; %bb.16:
	v_fma_f32 v18, v23, 2.0, -v21
	v_mov_b32_e32 v20, v21
; %bb.17:                               ; %Flow519
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr23
.LBB0_18:                               ; %Flow520
	s_and_not1_saveexec_b32 s0, s0
; %bb.19:
	v_mov_b32_e32 v18, v22
	v_fma_f32 v20, v23, 2.0, -v22
; %bb.20:
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v10, v[10:11], off
	v_max_f32_e64 v11, s7, s7
	v_max_f32_e64 v12, s6, s6
	v_sub_f32_e32 v0, v17, v0
	s_mov_b64 s[20:21], 1
	s_mov_b32 s22, 0x3e76c4e1
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_minmax_f32 v11, v12, v11, 1.0
	v_sub_f32_e32 v12, v20, v21
                                        ; implicit-def: $vgpr21
	v_dual_mul_f32 v14, 0x3c23d70a, v11 :: v_dual_sub_f32 v11, v18, v22
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v13, v19, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_max_f32_e32 v10, v14, v14
                                        ; implicit-def: $vgpr14
.LBB0_21:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_frexp_mant_f32_e64 v32, |v0|
	s_delay_alu instid0(VALU_DEP_4)
	v_frexp_mant_f32_e64 v38, |v13|
	v_frexp_mant_f32_e64 v41, |v11|
	v_cmp_eq_f32_e64 s2, 1.0, v12
	v_cndmask_b32_e64 v26, 4.0, 1.0, vcc_lo
	v_cmp_eq_f32_e64 s0, 1.0, v13
	v_cmp_eq_f32_e64 s1, 1.0, v11
	v_frexp_mant_f32_e64 v44, |v12|
	v_cmp_gt_f32_e64 s5, 0x3f2aaaab, v32
	v_cmp_gt_f32_e64 s6, 0x3f2aaaab, v38
	v_cmp_gt_f32_e64 s7, 0x3f2aaaab, v41
	s_cmp_eq_u32 s20, 1
	v_cndmask_b32_e64 v37, 4.0, 1.0, s2
	s_cselect_b32 s2, -1, 0
	v_frexp_exp_i32_f32_e32 v33, v0
	v_cndmask_b32_e64 v28, 4.0, 1.0, s0
	v_frexp_exp_i32_f32_e32 v39, v13
	v_cndmask_b32_e64 v31, 4.0, 1.0, s1
	v_cndmask_b32_e64 v46, v17, v7, s2
	v_cndmask_b32_e64 v48, v18, v3, s2
	v_cndmask_b32_e64 v49, v20, v1, s2
	v_cndmask_b32_e64 v50, 0, 1, s5
	v_trunc_f32_e32 v51, v26
	v_dual_mul_f32 v52, 0.5, v26 :: v_dual_mul_f32 v55, 0.5, v28
	v_cndmask_b32_e64 v53, 0, 1, s6
	v_cndmask_b32_e64 v56, 0, 1, s7
	v_cmp_gt_f32_e64 s8, 0x3f2aaaab, v44
	s_cmp_eq_u32 s20, 2
	v_frexp_exp_i32_f32_e32 v42, v11
	s_cselect_b32 s3, -1, 0
	v_dual_mul_f32 v29, 0x3fb504f3, v0 :: v_dual_mul_f32 v36, 0x3fb504f3, v13
	v_dual_mul_f32 v40, 0x3fb504f3, v11 :: v_dual_mul_f32 v43, 0x3fb504f3, v12
	v_frexp_exp_i32_f32_e32 v45, v12
	v_cndmask_b32_e64 v47, v19, v5, s2
	v_trunc_f32_e32 v54, v28
	v_trunc_f32_e32 v57, v31
	v_dual_mul_f32 v58, 0.5, v31 :: v_dual_mul_f32 v61, 0.5, v37
	v_cndmask_b32_e64 v59, 0, 1, s8
	v_cndmask_b32_e64 v46, v46, v8, s3
	v_cndmask_b32_e64 v48, v48, v4, s3
	v_cndmask_b32_e64 v49, v49, v2, s3
	v_ldexp_f32 v50, v32, v50
	v_subrev_co_ci_u32_e64 v62, s5, 0, v33, s5
	v_cmp_eq_f32_e64 s11, v51, v26
	v_trunc_f32_e32 v51, v52
	v_ldexp_f32 v53, v38, v53
	v_subrev_co_ci_u32_e64 v39, s5, 0, v39, s6
	v_ldexp_f32 v41, v41, v56
	v_subrev_co_ci_u32_e64 v42, s6, 0, v42, s7
	v_trunc_f32_e32 v60, v37
	v_cndmask_b32_e64 v47, v47, v6, s3
	v_cmp_eq_f32_e64 s5, v54, v28
	v_trunc_f32_e32 v54, v55
	v_cmp_eq_f32_e64 s6, v57, v31
	v_trunc_f32_e32 v56, v58
	v_ldexp_f32 v44, v44, v59
	v_subrev_co_ci_u32_e64 v45, s7, 0, v45, s8
	v_trunc_f32_e32 v57, v61
	v_dual_mul_f32 v38, v29, v46 :: v_dual_mul_f32 v29, v36, v47
	v_dual_mul_f32 v32, v40, v48 :: v_dual_mul_f32 v33, v43, v49
	v_dual_add_f32 v43, 1.0, v50 :: v_dual_add_f32 v48, 1.0, v53
	v_cvt_f32_i32_e32 v46, v62
	v_cmp_neq_f32_e64 s12, v51, v52
	v_cvt_f32_i32_e32 v39, v39
	v_add_f32_e32 v51, 1.0, v41
	v_cmp_eq_f32_e32 vcc_lo, 0, v0
	v_cmp_eq_f32_e64 s7, v60, v37
	v_cmp_neq_f32_e64 s8, v54, v55
	v_add_f32_e32 v54, 1.0, v44
	v_cvt_f32_i32_e32 v42, v42
	v_cmp_neq_f32_e64 s9, v56, v58
	v_cvt_f32_i32_e32 v45, v45
	v_cmp_neq_f32_e64 s10, v57, v61
	v_dual_add_f32 v55, -1.0, v43 :: v_dual_add_f32 v58, -1.0, v48
	v_rcp_f32_e32 v56, v43
	v_dual_mul_f32 v57, 0x3f317218, v46 :: v_dual_mul_f32 v60, 0x3f317218, v39
	v_rcp_f32_e32 v59, v48
	v_rcp_f32_e32 v62, v51
	s_and_b32 s12, s11, s12
	v_cndmask_b32_e64 v34, 0x7f800000, 0, vcc_lo
	v_dual_add_f32 v40, -1.0, v50 :: v_dual_add_f32 v47, -1.0, v53
	v_dual_add_f32 v49, -1.0, v41 :: v_dual_add_f32 v52, -1.0, v44
	v_dual_add_f32 v61, -1.0, v51 :: v_dual_add_f32 v64, -1.0, v54
	v_dual_mul_f32 v63, 0x3f317218, v42 :: v_dual_mul_f32 v66, 0x3f317218, v45
	v_rcp_f32_e32 v65, v54
	v_cndmask_b32_e64 v67, 0, v0, s12
	v_dual_sub_f32 v50, v50, v55 :: v_dual_sub_f32 v53, v53, v58
	v_fma_f32 v55, 0x3f317218, v46, -v57
	v_fma_f32 v58, 0x3f317218, v39, -v60
	v_dual_sub_f32 v41, v41, v61 :: v_dual_sub_f32 v44, v44, v64
	v_fma_f32 v61, 0x3f317218, v42, -v63
	v_fma_f32 v64, 0x3f317218, v45, -v66
	v_bfi_b32 v34, 0x7fffffff, v34, v67
	v_mul_f32_e32 v67, v40, v56
	v_dual_fmac_f32 v55, 0xb102e308, v46 :: v_dual_fmac_f32 v58, 0xb102e308, v39
	v_dual_mul_f32 v46, v47, v59 :: v_dual_mul_f32 v39, v49, v62
	v_dual_fmac_f32 v61, 0xb102e308, v42 :: v_dual_fmac_f32 v64, 0xb102e308, v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v42, v52, v65 :: v_dual_mul_f32 v45, v43, v67
	v_add_f32_e32 v70, v60, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v68, v57, v55 :: v_dual_mul_f32 v69, v48, v46
	v_dual_mul_f32 v71, v51, v39 :: v_dual_add_f32 v74, v66, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v72, v63, v61 :: v_dual_mul_f32 v73, v54, v42
	v_fma_f32 v43, v67, v43, -v45
	v_fma_f32 v48, v46, v48, -v69
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v51, v39, v51, -v71
	v_dual_sub_f32 v57, v68, v57 :: v_dual_sub_f32 v60, v70, v60
	v_fma_f32 v54, v42, v54, -v73
	v_dual_fmac_f32 v43, v67, v50 :: v_dual_fmac_f32 v48, v46, v53
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v51, v39, v41
	v_dual_sub_f32 v63, v72, v63 :: v_dual_sub_f32 v66, v74, v66
	v_dual_sub_f32 v50, v55, v57 :: v_dual_sub_f32 v53, v58, v60
	v_fmac_f32_e32 v54, v42, v44
	v_dual_add_f32 v57, v69, v48 :: v_dual_add_f32 v58, v71, v51
	v_add_f32_e32 v55, v45, v43
	v_dual_sub_f32 v41, v61, v63 :: v_dual_sub_f32 v44, v64, v66
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v63, v57, v69 :: v_dual_sub_f32 v66, v58, v71
	v_sub_f32_e32 v64, v47, v57
	v_dual_add_f32 v60, v73, v54 :: v_dual_sub_f32 v45, v55, v45
	v_sub_f32_e32 v69, v49, v58
	v_sub_f32_e32 v61, v40, v55
	v_cmp_class_f32_e64 s23, v0, 0x204
	v_cndmask_b32_e64 v36, 1.0, v0, s12
	v_sub_f32_e32 v43, v45, v43
	v_sub_f32_e32 v45, v47, v64
	v_dual_sub_f32 v47, v63, v48 :: v_dual_sub_f32 v48, v49, v69
	v_sub_f32_e32 v40, v40, v61
	s_or_b32 vcc_lo, vcc_lo, s23
	s_cmp_eq_u32 s20, 0
	v_cmp_eq_f32_e64 s4, 0, v12
	v_sub_f32_e32 v48, v48, v58
	v_sub_f32_e32 v40, v40, v55
	v_sub_f32_e32 v71, v60, v73
	v_cmp_eq_f32_e64 s0, 0, v13
	v_cmp_eq_f32_e64 s1, 0, v11
	v_cndmask_b32_e64 v35, 0x7f800000, 0, s4
	v_dual_add_f32 v40, v43, v40 :: v_dual_sub_f32 v49, v66, v51
	v_sub_f32_e32 v73, v52, v60
	v_cndmask_b32_e64 v27, 0x7f800000, 0, s0
	v_cndmask_b32_e64 v30, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_f32_e32 v40, v61, v40
	v_sub_f32_e32 v45, v45, v57
	v_cmp_class_f32_e64 s24, v13, 0x204
	v_cmp_class_f32_e64 s25, v11, 0x204
	v_cmp_class_f32_e64 s26, v12, 0x204
	v_dual_mul_f32 v40, v56, v40 :: v_dual_add_f32 v43, v47, v45
	v_sub_f32_e32 v51, v52, v73
	v_dual_add_f32 v45, v49, v48 :: v_dual_sub_f32 v52, v71, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v48, v67, v40 :: v_dual_add_f32 v43, v64, v43
	v_dual_sub_f32 v51, v51, v60 :: v_dual_sub_f32 v54, v48, v67
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v43, v59, v43
	v_mul_f32_e32 v55, v48, v48
	v_ldexp_f32 v56, v48, 1
	v_dual_sub_f32 v40, v40, v54 :: v_dual_add_f32 v49, v46, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v54, v48, v48, -v55
	v_dual_add_f32 v63, v40, v40 :: v_dual_sub_f32 v46, v49, v46
	v_mul_f32_e32 v57, v49, v49
	v_ldexp_f32 v64, v40, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v54, v48, v63 :: v_dual_sub_f32 v43, v43, v46
	v_fma_f32 v46, v49, v49, -v57
	v_add_f32_e32 v47, v52, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v63, v55, v54
	v_add_f32_e32 v47, v73, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v55, v63, v55
	v_mul_f32_e32 v75, v48, v63
	v_fmaak_f32 v76, s22, v63, 0x3e91f4c4
	v_mul_f32_e32 v47, v65, v47
	v_add_f32_e32 v65, v43, v43
	v_sub_f32_e32 v54, v54, v55
	v_fma_f32 v55, v63, v48, -v75
	v_fmaak_f32 v76, v63, v76, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v52, v42, v47 :: v_dual_fmac_f32 v55, v63, v40
	v_dual_sub_f32 v42, v52, v42 :: v_dual_add_f32 v45, v69, v45
	v_mul_f32_e32 v61, v52, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v55, v54, v48
	v_mul_f32_e32 v48, v63, v76
	v_dual_sub_f32 v42, v47, v42 :: v_dual_mul_f32 v45, v62, v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v47, v52, v52, -v61
	v_fmac_f32_e32 v46, v49, v65
	v_fma_f32 v63, v63, v76, -v48
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v71, v42, v42
	v_add_f32_e32 v51, v39, v45
	v_ldexp_f32 v58, v49, 1
	v_add_f32_e32 v65, v57, v46
	v_fmac_f32_e32 v63, v54, v76
	v_fmac_f32_e32 v47, v52, v71
	v_ldexp_f32 v62, v52, 1
	v_ldexp_f32 v60, v51, 1
	v_mul_f32_e32 v54, v49, v65
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v40, s22, v65, 0x3e91f4c4 :: v_dual_add_f32 v71, v61, v47
	v_sub_f32_e32 v57, v65, v57
	v_sub_f32_e32 v39, v51, v39
	v_dual_mul_f32 v59, v51, v51 :: v_dual_fmaak_f32 v40, v65, v40, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v61, v71, v61
	v_dual_sub_f32 v46, v46, v57 :: v_dual_sub_f32 v39, v45, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v45, v51, v51, -v59
	v_ldexp_f32 v73, v42, 1
	v_sub_f32_e32 v47, v47, v61
	v_fma_f32 v61, v65, v49, -v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v61, v65, v43
	v_fmac_f32_e32 v61, v46, v49
	v_mul_f32_e32 v49, v65, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v65, v65, v40, -v49
	v_fmac_f32_e32 v65, v46, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v46, v54, v61
	v_ldexp_f32 v66, v43, 1
	v_dual_sub_f32 v54, v46, v54 :: v_dual_add_f32 v67, v39, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v54, v61, v54 :: v_dual_fmac_f32 v45, v51, v67
	v_add_f32_e32 v67, v59, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v59, v67, v59
	v_mul_f32_e32 v57, v51, v67
	v_fmaak_f32 v76, s22, v67, 0x3e91f4c4
	v_sub_f32_e32 v45, v45, v59
	v_mul_f32_e32 v59, v52, v71
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v43, v67, v51, -v57
	v_fmaak_f32 v76, v67, v76, 0x3ecccdef
	v_ldexp_f32 v69, v39, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v43, v67, v39
	v_fma_f32 v39, v71, v52, -v59
	v_dual_fmac_f32 v39, v71, v42 :: v_dual_fmaak_f32 v42, s22, v71, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v39, v47, v52
	v_fmaak_f32 v42, v71, v42, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v52, v71, v42
	v_fma_f32 v71, v71, v42, -v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v71, v47, v42
	v_add_f32_e32 v47, v48, v63
	v_dual_add_f32 v61, v52, v71 :: v_dual_sub_f32 v48, v47, v48
	v_add_f32_e32 v40, v75, v55
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v52, v61, v52
	v_sub_f32_e32 v48, v63, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v42, v40, v75 :: v_dual_add_f32 v75, v49, v65
	v_dual_sub_f32 v52, v71, v52 :: v_dual_fmac_f32 v43, v45, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v48, 0x31739010, v48
	v_mul_f32_e32 v51, v67, v76
	v_sub_f32_e32 v42, v55, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v49, v75, v49 :: v_dual_add_f32 v52, 0x31739010, v52
	v_fma_f32 v67, v67, v76, -v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v49, v65, v49
	v_add_f32_e32 v65, 0x3f2aaaaa, v61
	v_fmac_f32_e32 v67, v45, v76
	v_add_f32_e32 v45, v57, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v76, v59, v39 :: v_dual_add_f32 v49, 0x31739010, v49
	v_add_f32_e32 v55, v51, v67
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v57, v45, v57
	v_sub_f32_e32 v59, v76, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v51, v55, v51
	v_sub_f32_e32 v43, v43, v57
	v_add_f32_e32 v57, 0x3f2aaaaa, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v39, v39, v59
	v_add_f32_e32 v59, 0x3f2aaaaa, v75
	v_add_f32_e32 v63, 0x3f2aaaaa, v55
	v_sub_f32_e32 v51, v67, v51
	v_add_f32_e32 v67, 0xbf2aaaaa, v57
	v_add_f32_e32 v71, 0xbf2aaaaa, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v51, 0x31739010, v51
	v_sub_f32_e32 v47, v47, v67
	v_add_f32_e32 v67, 0xbf2aaaaa, v63
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v71, v75, v71
	v_add_f32_e32 v75, 0xbf2aaaaa, v65
	v_add_f32_e32 v47, v48, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v55, v55, v67
	v_add_f32_e32 v48, v49, v71
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v61, v61, v75
	v_add_f32_e32 v49, v51, v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v55, v59, v48
	v_dual_add_f32 v51, v52, v61 :: v_dual_add_f32 v52, v57, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v61, v63, v49
	v_sub_f32_e32 v59, v59, v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v67, v65, v51
	v_sub_f32_e32 v57, v57, v52
	v_mul_f32_e32 v71, v40, v52
	v_mul_f32_e32 v75, v46, v55
	v_dual_sub_f32 v63, v63, v61 :: v_dual_add_f32 v48, v48, v59
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v47, v47, v57
	v_fma_f32 v57, v40, v52, -v71
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v59, v46, v55, -v75
	v_add_f32_e32 v49, v49, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v57, v40, v47 :: v_dual_mul_f32 v40, v45, v61
	v_sub_f32_e32 v47, v65, v67
	v_mul_f32_e32 v65, v76, v67
	v_fmac_f32_e32 v59, v46, v48
	v_fmac_f32_e32 v57, v42, v52
	v_fma_f32 v63, v45, v61, -v40
	v_add_f32_e32 v47, v51, v47
	v_fma_f32 v51, v76, v67, -v65
	v_fmac_f32_e32 v59, v54, v55
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v63, v45, v49
	v_fmac_f32_e32 v51, v76, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v42, v75, v59
	v_fmac_f32_e32 v63, v43, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v51, v39, v67
	v_dual_add_f32 v39, v71, v57 :: v_dual_sub_f32 v48, v42, v75
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v43, v40, v63
	v_add_f32_e32 v49, v58, v42
	v_add_f32_e32 v45, v65, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v46, v39, v71
	v_dual_add_f32 v47, v56, v39 :: v_dual_sub_f32 v40, v43, v40
	v_add_f32_e32 v52, v60, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v54, v45, v65
	v_dual_add_f32 v55, v62, v45 :: v_dual_sub_f32 v46, v57, v46
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v56, v47, v56
	v_dual_sub_f32 v48, v59, v48 :: v_dual_sub_f32 v57, v49, v58
	v_sub_f32_e32 v40, v63, v40
	v_dual_sub_f32 v58, v52, v60 :: v_dual_sub_f32 v51, v51, v54
	v_sub_f32_e32 v54, v55, v62
	v_dual_sub_f32 v39, v39, v56 :: v_dual_add_f32 v46, v64, v46
	v_sub_f32_e32 v42, v42, v57
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_add_f32 v48, v66, v48 :: v_dual_sub_f32 v43, v43, v58
	v_add_f32_e32 v40, v69, v40
	v_sub_f32_e32 v45, v45, v54
	v_add_f32_e32 v51, v73, v51
	v_dual_add_f32 v39, v46, v39 :: v_dual_add_f32 v42, v48, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v40, v40, v43 :: v_dual_add_f32 v43, v51, v45
	v_dual_add_f32 v45, v47, v39 :: v_dual_add_f32 v46, v49, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v48, v52, v40 :: v_dual_add_f32 v51, v55, v43
	v_dual_sub_f32 v47, v45, v47 :: v_dual_add_f32 v54, v68, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v49, v46, v49
	v_dual_add_f32 v56, v70, v46 :: v_dual_sub_f32 v55, v51, v55
	v_add_f32_e32 v58, v74, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v39, v39, v47
	v_sub_f32_e32 v47, v54, v68
	v_dual_sub_f32 v42, v42, v49 :: v_dual_sub_f32 v49, v56, v70
	v_sub_f32_e32 v43, v43, v55
	v_sub_f32_e32 v55, v58, v74
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v59, v54, v47
	v_sub_f32_e32 v45, v45, v47
	v_dual_add_f32 v47, v50, v39 :: v_dual_sub_f32 v60, v56, v49
	v_sub_f32_e32 v62, v58, v55
	v_sub_f32_e32 v51, v51, v55
	v_add_f32_e32 v55, v44, v43
	v_sub_f32_e32 v52, v48, v52
	v_dual_add_f32 v57, v72, v48 :: v_dual_sub_f32 v46, v46, v49
	v_add_f32_e32 v49, v53, v42
	v_sub_f32_e32 v59, v68, v59
	v_dual_sub_f32 v63, v47, v50 :: v_dual_sub_f32 v60, v70, v60
	v_sub_f32_e32 v62, v74, v62
	v_sub_f32_e32 v66, v55, v44
	v_sub_f32_e32 v40, v40, v52
	v_sub_f32_e32 v52, v57, v72
	v_sub_f32_e32 v64, v49, v53
	v_add_f32_e32 v45, v45, v59
	v_dual_sub_f32 v59, v47, v63 :: v_dual_add_f32 v46, v46, v60
	v_add_f32_e32 v51, v51, v62
	v_dual_sub_f32 v62, v55, v66 :: v_dual_sub_f32 v61, v57, v52
	v_sub_f32_e32 v48, v48, v52
	v_dual_add_f32 v52, v41, v40 :: v_dual_sub_f32 v39, v39, v63
	v_dual_sub_f32 v60, v49, v64 :: v_dual_sub_f32 v43, v43, v66
	v_dual_sub_f32 v50, v50, v59 :: v_dual_add_f32 v45, v47, v45
	v_add_f32_e32 v46, v49, v46
	v_dual_sub_f32 v44, v44, v62 :: v_dual_add_f32 v49, v55, v51
	v_sub_f32_e32 v61, v72, v61
	v_dual_sub_f32 v65, v52, v41 :: v_dual_sub_f32 v42, v42, v64
	v_sub_f32_e32 v47, v53, v60
	v_dual_add_f32 v39, v39, v50 :: v_dual_add_f32 v50, v54, v45
	v_dual_add_f32 v43, v43, v44 :: v_dual_add_f32 v44, v58, v49
	v_add_f32_e32 v48, v48, v61
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_sub_f32 v61, v52, v65 :: v_dual_add_f32 v42, v42, v47
	v_add_f32_e32 v47, v56, v46
	v_sub_f32_e32 v51, v50, v54
	v_sub_f32_e32 v54, v44, v58
	v_sub_f32_e32 v40, v40, v65
	v_dual_sub_f32 v41, v41, v61 :: v_dual_add_f32 v48, v52, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v52, v47, v56 :: v_dual_sub_f32 v45, v45, v51
	v_dual_sub_f32 v49, v49, v54 :: v_dual_add_f32 v40, v40, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v41, v57, v48
	v_dual_sub_f32 v46, v46, v52 :: v_dual_add_f32 v39, v39, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v43, v43, v49
	v_dual_sub_f32 v53, v41, v57 :: v_dual_add_f32 v42, v42, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v45, v50, v39
	v_add_f32_e32 v49, v44, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v48, v48, v53
	v_add_f32_e32 v46, v47, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v50, v45, v50 :: v_dual_mul_f32 v51, v26, v45
	v_sub_f32_e32 v44, v49, v44
	v_mul_f32_e32 v54, v37, v49
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_add_f32 v40, v40, v48 :: v_dual_sub_f32 v47, v46, v47
	v_mul_f32_e32 v52, v28, v46
	v_sub_f32_e32 v39, v39, v50
	v_fma_f32 v45, v26, v45, -v51
	v_sub_f32_e32 v43, v43, v44
	v_fma_f32 v44, v37, v49, -v54
	v_add_f32_e32 v48, v41, v40
	v_sub_f32_e32 v42, v42, v47
	v_fma_f32 v46, v28, v46, -v52
	v_fmac_f32_e32 v45, v26, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v44, v37, v43 :: v_dual_sub_f32 v41, v48, v41
	v_dual_mul_f32 v53, v31, v48 :: v_dual_fmac_f32 v46, v28, v42
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_add_f32 v26, v51, v45 :: v_dual_add_f32 v37, v54, v44
	v_cmp_class_f32_e64 s14, v54, 0x204
	v_cmp_class_f32_e64 s15, v51, 0x204
	v_sub_f32_e32 v40, v40, v41
	v_fma_f32 v41, v31, v48, -v53
	v_add_f32_e32 v28, v52, v46
	v_cmp_class_f32_e64 s12, v52, 0x204
	v_sub_f32_e32 v39, v26, v51
	v_cndmask_b32_e64 v26, v26, v51, s15
	v_sub_f32_e32 v43, v37, v54
	v_cndmask_b32_e64 v37, v37, v54, s14
	v_fmac_f32_e32 v41, v31, v40
	v_sub_f32_e32 v40, v28, v52
	v_cndmask_b32_e64 v28, v28, v52, s12
	v_cmp_eq_f32_e64 s12, 0x42b17218, v26
	v_cmp_eq_f32_e64 s15, 0x42b17218, v37
	v_sub_f32_e32 v39, v45, v39
	v_sub_f32_e32 v43, v44, v43
	v_add_f32_e32 v31, v53, v41
	v_cndmask_b32_e64 v45, 0, 0x37000000, s12
	v_cndmask_b32_e64 v44, 0, 0x37000000, s15
	v_cmp_neq_f32_e64 s15, 0x7f800000, |v26|
	v_cmp_class_f32_e64 s13, v53, 0x204
	v_sub_f32_e32 v42, v31, v53
	v_sub_f32_e32 v26, v26, v45
	v_sub_f32_e32 v40, v46, v40
	v_cndmask_b32_e64 v39, 0, v39, s15
	v_cndmask_b32_e64 v31, v31, v53, s13
	v_cmp_eq_f32_e64 s13, 0x42b17218, v28
	v_cmp_ngt_f32_e64 s15, 0xc2ce8ed0, v26
	v_cmp_neq_f32_e64 s12, 0x7f800000, |v28|
	v_add_f32_e32 v39, v45, v39
	v_mul_f32_e32 v45, 0x3fb8aa3b, v26
	v_cndmask_b32_e64 v46, 0, 0x37000000, s13
	v_cmp_eq_f32_e64 s14, 0x42b17218, v31
	v_sub_f32_e32 v41, v41, v42
	v_cmp_neq_f32_e64 s13, 0x7f800000, |v31|
	v_fma_f32 v47, 0x3fb8aa3b, v26, -v45
	v_rndne_f32_e32 v48, v45
	v_cndmask_b32_e64 v42, 0, 0x37000000, s14
	v_cmp_neq_f32_e64 s14, 0x7f800000, |v37|
	v_cndmask_b32_e64 v40, 0, v40, s12
	v_fmac_f32_e32 v47, 0x32a5705f, v26
	v_sub_f32_e32 v45, v45, v48
	v_cvt_i32_f32_e32 v48, v48
	v_sub_f32_e32 v28, v28, v46
	v_cndmask_b32_e64 v41, 0, v41, s13
	v_sub_f32_e32 v31, v31, v42
	v_add_f32_e32 v45, v45, v47
	v_cndmask_b32_e64 v43, 0, v43, s14
	v_sub_f32_e32 v37, v37, v44
	v_add_f32_e32 v40, v46, v40
	v_mul_f32_e32 v46, 0x3fb8aa3b, v28
	v_exp_f32_e32 v45, v45
	v_dual_add_f32 v41, v42, v41 :: v_dual_mul_f32 v42, 0x3fb8aa3b, v31
	v_dual_add_f32 v43, v44, v43 :: v_dual_mul_f32 v44, 0x3fb8aa3b, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v49, 0x3fb8aa3b, v28, -v46
	v_rndne_f32_e32 v50, v46
	v_fma_f32 v51, 0x3fb8aa3b, v31, -v42
	v_rndne_f32_e32 v52, v42
	v_fma_f32 v53, 0x3fb8aa3b, v37, -v44
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ldexp_f32 v45, v45, v48
	v_rndne_f32_e32 v54, v44
	v_dual_fmac_f32 v49, 0x32a5705f, v28 :: v_dual_sub_f32 v46, v46, v50
	v_fmac_f32_e32 v51, 0x32a5705f, v31
	v_cndmask_b32_e64 v45, 0, v45, s15
	v_cmp_nlt_f32_e64 s15, 0x42b17218, v26
	v_dual_sub_f32 v42, v42, v52 :: v_dual_fmac_f32 v53, 0x32a5705f, v37
	v_sub_f32_e32 v44, v44, v54
	v_add_f32_e32 v46, v46, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v26, 0x7f800000, v45, s15
	v_add_f32_e32 v42, v42, v51
	v_cvt_i32_f32_e32 v50, v50
	v_add_f32_e32 v44, v44, v53
	v_exp_f32_e32 v46, v46
	v_fma_f32 v39, v26, v39, v26
	v_cmp_eq_f32_e64 s15, 0x7f800000, v26
	v_exp_f32_e32 v42, v42
	v_exp_f32_e32 v44, v44
	v_cvt_i32_f32_e32 v52, v52
	v_cvt_i32_f32_e32 v54, v54
	v_cndmask_b32_e64 v26, v39, v26, s15
	v_cmp_ngt_f32_e64 s12, 0xc2ce8ed0, v28
	v_cmp_ngt_f32_e64 s13, 0xc2ce8ed0, v31
	v_ldexp_f32 v46, v46, v50
	v_cmp_ngt_f32_e64 s14, 0xc2ce8ed0, v37
	v_bfi_b32 v26, 0x7fffffff, v26, v36
	v_ldexp_f32 v42, v42, v52
	v_ldexp_f32 v44, v44, v54
	v_cndmask_b32_e64 v46, 0, v46, s12
	v_cmp_nlt_f32_e64 s12, 0x42b17218, v28
	v_cndmask_b32_e64 v36, 0x7fc00000, v26, s11
	v_cmp_gt_f32_e64 s11, 0, v0
	v_cndmask_b32_e64 v28, 0, v42, s13
	v_cmp_nlt_f32_e64 s13, 0x42b17218, v31
	v_cndmask_b32_e64 v31, 0, v44, s14
	v_cmp_nlt_f32_e64 s14, 0x42b17218, v37
	v_cndmask_b32_e64 v26, v26, v36, s11
	v_cndmask_b32_e64 v37, 0x7f800000, v46, s12
	v_cndmask_b32_e64 v28, 0x7f800000, v28, s13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, 0x7f800000, v31, s14
	v_cndmask_b32_e32 v26, v26, v34, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_fma_f32 v40, v37, v40, v37
	v_cmp_eq_f32_e64 s12, 0x7f800000, v37
	v_fma_f32 v41, v28, v41, v28
	v_cmp_eq_f32_e64 s13, 0x7f800000, v28
	v_cndmask_b32_e32 v26, 0x7fc00000, v26, vcc_lo
	v_fma_f32 v42, v31, v43, v31
	v_cndmask_b32_e64 v37, v40, v37, s12
	v_cmp_eq_f32_e64 s14, 0x7f800000, v31
	v_cndmask_b32_e64 v28, v41, v28, s13
	v_max_f32_e32 v34, v26, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v31, v42, v31, s14
	v_max_f32_e32 v34, v34, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v26, v26, v34
	v_mul_f32_e32 v34, 0x4f800000, v26
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v26, v26, v34, vcc_lo
	v_sqrt_f32_e32 v34, v26
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v36, -1, v34
	v_add_nc_u32_e32 v39, 1, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v40, -v36, v34, v26
	v_fma_f32 v41, -v39, v34, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s11, 0, v40
	v_cndmask_b32_e64 v34, v34, v36, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s11, 0, v41
	v_cndmask_b32_e64 v34, v34, v39, s11
	s_cselect_b32 s11, -1, 0
	s_or_b32 s0, s0, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v36, 0x37800000, v34
	v_cndmask_b32_e32 v34, v34, v36, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v26, v34, v26, vcc_lo
	v_div_scale_f32 v34, null, v26, v26, v38
	v_div_scale_f32 v36, vcc_lo, v38, v26, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v39, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v34, v39, 1.0
	v_fmac_f32_e32 v39, v40, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v40, v36, v39
	v_fma_f32 v41, -v34, v40, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v40, v41, v39
	v_fma_f32 v34, -v34, v40, v36
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f32 v34, v34, v39, v40
	s_and_b32 vcc_lo, s5, s8
	s_and_b32 s8, s6, s9
	s_and_b32 s9, s7, s10
	v_cndmask_b32_e64 v36, 1.0, v11, s8
	v_div_fixup_f32 v26, v34, v26, v38
	v_cndmask_b32_e32 v34, 1.0, v13, vcc_lo
	v_cndmask_b32_e64 v38, 1.0, v12, s9
	v_cndmask_b32_e64 v41, 0, v12, s9
	v_bfi_b32 v28, 0x7fffffff, v28, v36
	v_cndmask_b32_e64 v15, v15, v26, s3
	v_cndmask_b32_e64 v14, v14, v26, s2
	v_cndmask_b32_e64 v0, v0, v26, s11
	v_bfi_b32 v26, 0x7fffffff, v37, v34
	v_bfi_b32 v31, 0x7fffffff, v31, v38
	v_cndmask_b32_e32 v39, 0, v13, vcc_lo
	v_cndmask_b32_e64 v40, 0, v11, s8
	v_bfi_b32 v34, 0x7fffffff, v35, v41
	v_cndmask_b32_e64 v35, 0x7fc00000, v26, s5
	v_cndmask_b32_e64 v36, 0x7fc00000, v28, s6
	v_cmp_gt_f32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e64 v37, 0x7fc00000, v31, s7
	v_cmp_gt_f32_e64 s5, 0, v12
	v_cmp_gt_f32_e64 s6, 0, v13
	v_bfi_b32 v27, 0x7fffffff, v27, v39
	v_bfi_b32 v30, 0x7fffffff, v30, v40
	v_cndmask_b32_e32 v28, v28, v36, vcc_lo
	v_cndmask_b32_e64 v31, v31, v37, s5
	v_cndmask_b32_e64 v26, v26, v35, s6
	s_or_b32 vcc_lo, s1, s25
	s_or_b32 s1, s4, s26
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	v_cndmask_b32_e64 v26, v26, v27, s0
	v_cndmask_b32_e32 v27, v28, v30, vcc_lo
	v_cndmask_b32_e64 v28, v31, v34, s1
	v_cmp_o_f32_e64 s1, v13, v13
	v_cmp_o_f32_e32 vcc_lo, v11, v11
	v_cmp_o_f32_e64 s0, v12, v12
	s_cmp_eq_u32 s20, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, 0x7fc00000, v26, s1
	v_cndmask_b32_e32 v27, 0x7fc00000, v27, vcc_lo
	v_cndmask_b32_e64 v28, 0x7fc00000, v28, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_max_f32 v30, v26, v26 :: v_dual_max_f32 v31, v27, v27
	v_max_f32_e32 v34, v28, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_f32_e32 v30, v30, v10
	v_max_f32_e32 v31, v31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f32_e32 v34, v34, v10
	v_dual_add_f32 v26, v26, v30 :: v_dual_add_f32 v27, v27, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v28, v28, v34
	v_mul_f32_e32 v30, 0x4f800000, v26
	v_cmp_gt_f32_e64 s1, 0xf800000, v26
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v31, 0x4f800000, v27
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v27
	v_mul_f32_e32 v34, 0x4f800000, v28
	v_cmp_gt_f32_e64 s0, 0xf800000, v28
	v_cndmask_b32_e64 v26, v26, v30, s1
	v_cndmask_b32_e32 v27, v27, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v28, v34, s0
	v_sqrt_f32_e32 v30, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v31, v27
	v_sqrt_f32_e32 v34, v28
	s_delay_alu instid0(TRANS32_DEP_3)
	v_add_nc_u32_e32 v35, -1, v30
	v_add_nc_u32_e32 v36, 1, v30
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v37, -1, v31
	v_add_nc_u32_e32 v38, 1, v31
	v_add_nc_u32_e32 v39, -1, v34
	v_fma_f32 v41, -v35, v30, v26
	v_add_nc_u32_e32 v40, 1, v34
	v_fma_f32 v43, -v37, v31, v27
	v_fma_f32 v42, -v36, v30, v26
	v_fma_f32 v45, -v39, v34, v28
	v_cmp_ge_f32_e64 s4, 0, v41
	v_fma_f32 v44, -v38, v31, v27
	v_fma_f32 v46, -v40, v34, v28
	v_cmp_lt_f32_e64 s6, 0, v42
	v_cmp_ge_f32_e64 s5, 0, v45
	v_cndmask_b32_e64 v30, v30, v35, s4
	v_cmp_ge_f32_e64 s4, 0, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v34, v34, v39, s5
	v_cmp_lt_f32_e64 s5, 0, v46
	v_cndmask_b32_e64 v31, v31, v37, s4
	v_cmp_lt_f32_e64 s4, 0, v44
	v_cndmask_b32_e64 v30, v30, v36, s6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v34, v34, v40, s5
	v_cndmask_b32_e64 v31, v31, v38, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, 0x37800000, v30
	v_dual_mul_f32 v37, 0x37800000, v34 :: v_dual_mul_f32 v36, 0x37800000, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v35, s1
	v_cmp_class_f32_e64 s1, v26, 0x260
	v_cndmask_b32_e64 v34, v34, v37, s0
	v_cmp_class_f32_e64 s0, v28, 0x260
	v_cndmask_b32_e32 v31, v31, v36, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v27, 0x260
	v_cndmask_b32_e64 v26, v30, v26, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v28, v34, v28, s0
	v_cndmask_b32_e32 v27, v31, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v30, null, v26, v26, v29
	v_div_scale_f32 v36, null, v28, v28, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v34, null, v27, v27, v32
	v_rcp_f32_e32 v38, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v40, v36
	v_div_scale_f32 v31, vcc_lo, v29, v26, v29
	v_rcp_f32_e32 v39, v34
	v_div_scale_f32 v35, s0, v32, v27, v32
	v_div_scale_f32 v37, s1, v33, v28, v33
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fma_f32 v41, -v30, v38, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v43, -v36, v40, 1.0
	v_fma_f32 v42, -v34, v39, 1.0
	v_fmac_f32_e32 v38, v41, v38
	v_dual_fmac_f32 v40, v43, v40 :: v_dual_fmac_f32 v39, v42, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v41, v31, v38
	v_dual_mul_f32 v43, v37, v40 :: v_dual_mul_f32 v42, v35, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v44, -v30, v41, v31
	v_fma_f32 v46, -v36, v43, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v45, -v34, v42, v35
	v_fmac_f32_e32 v41, v44, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v43, v46, v40 :: v_dual_fmac_f32 v42, v45, v39
	v_fma_f32 v30, -v30, v41, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v31, -v34, v42, v35
	v_fma_f32 v34, -v36, v43, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v30, v30, v38, v41
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v31, v31, v39, v42
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v26, v30, v26, v29
	v_div_fmas_f32 v34, v34, v40, v43
	v_div_fixup_f32 v27, v31, v27, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v26, s3
	v_div_fixup_f32 v28, v34, v28, v33
	v_cndmask_b32_e64 v16, v16, v26, s2
	v_cndmask_b32_e64 v13, v13, v26, s11
	v_cndmask_b32_e64 v23, v23, v27, s3
	v_cndmask_b32_e64 v22, v22, v27, s2
	v_cndmask_b32_e64 v11, v11, v27, s11
	v_cndmask_b32_e64 v25, v25, v28, s3
	v_cndmask_b32_e64 v24, v24, v28, s2
	v_cndmask_b32_e64 v12, v12, v28, s11
	s_cbranch_scc0 .LBB0_21
; %bb.22:                               ; %.preheader305
	s_mov_b64 s[2:3], 1
.LBB0_23:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v26, v13, v16 :: v_dual_cndmask_b32 v27, v11, v22
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v27, v27, v23, s0
	v_cndmask_b32_e32 v10, v0, v14, vcc_lo
	v_cndmask_b32_e64 v26, v26, v21, s0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	v_mul_f32_e32 v27, v11, v27
	v_cndmask_b32_e64 v10, v10, v15, s0
	v_mul_f32_e32 v26, v13, v26
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v3, v3, v27 :: v_dual_mul_f32 v10, v0, v10
	v_cndmask_b32_e32 v28, v12, v24, vcc_lo
	v_cndmask_b32_e64 v6, v6, v26, s0
	v_cndmask_b32_e64 v19, v19, v26, s1
	v_cndmask_b32_e64 v4, v4, v27, s0
	v_cndmask_b32_e32 v7, v7, v10, vcc_lo
	v_cndmask_b32_e64 v28, v28, v25, s0
	v_cndmask_b32_e64 v8, v8, v10, s0
	v_cndmask_b32_e64 v17, v17, v10, s1
	v_cndmask_b32_e32 v5, v5, v26, vcc_lo
	v_cndmask_b32_e64 v18, v18, v27, s1
	v_mul_f32_e32 v28, v12, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v28, s0
	v_cndmask_b32_e32 v1, v1, v28, vcc_lo
	v_cndmask_b32_e64 v20, v20, v28, s1
	s_cbranch_scc0 .LBB0_23
; %bb.24:                               ; %.preheader
	v_ashrrev_i32_e32 v10, 31, v9
	s_mov_b64 s[0:1], 0
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s18, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, s16, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v27, vcc_lo
.LBB0_25:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, v26, s2
	v_add_co_ci_u32_e32 v29, vcc_lo, s3, v27, vcc_lo
	v_add_co_u32 v30, vcc_lo, v9, s2
	s_cmp_eq_u32 s0, 1
	v_add_co_ci_u32_e32 v31, vcc_lo, s3, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_dual_cndmask_b32 v32, v17, v7 :: v_dual_cndmask_b32 v33, v19, v5
	v_dual_cndmask_b32 v34, v18, v3 :: v_dual_cndmask_b32 v35, v20, v1
	v_dual_cndmask_b32 v36, v0, v14 :: v_dual_cndmask_b32 v37, v13, v16
	v_dual_cndmask_b32 v38, v11, v22 :: v_dual_cndmask_b32 v39, v12, v24
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	v_dual_cndmask_b32 v32, v32, v8 :: v_dual_cndmask_b32 v33, v33, v6
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_dual_cndmask_b32 v34, v34, v4 :: v_dual_cndmask_b32 v35, v35, v2
	s_cmp_lg_u32 s2, 12
	v_dual_cndmask_b32 v36, v36, v15 :: v_dual_cndmask_b32 v37, v37, v21
	v_dual_cndmask_b32 v38, v38, v23 :: v_dual_cndmask_b32 v39, v39, v25
	s_clause 0x3
	global_store_b32 v[28:29], v32, off
	global_store_b32 v[28:29], v33, off offset:12
	global_store_b32 v[28:29], v34, off offset:24
	global_store_b32 v[28:29], v35, off offset:36
	s_clause 0x3
	global_store_b32 v[30:31], v36, off
	global_store_b32 v[30:31], v37, off offset:12
	global_store_b32 v[30:31], v38, off offset:24
	global_store_b32 v[30:31], v39, off offset:36
	s_cbranch_scc1 .LBB0_25
.LBB0_26:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22ReconstructFreeSurfacePfS_S_S_iiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 77
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22ReconstructFreeSurfacePfS_S_S_iiff, .Lfunc_end0-_Z22ReconstructFreeSurfacePfS_S_S_iiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7740
; NumSgprs: 29
; NumVgprs: 77
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 77
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19CalculatePropSpeedsPfS_S_ii ; -- Begin function _Z19CalculatePropSpeedsPfS_S_ii
	.globl	_Z19CalculatePropSpeedsPfS_S_ii
	.p2align	8
	.type	_Z19CalculatePropSpeedsPfS_S_ii,@function
_Z19CalculatePropSpeedsPfS_S_ii:        ; @_Z19CalculatePropSpeedsPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[4:5], null, s15, s5, v[1:2]
	v_mad_u64_u32 v[5:6], null, s14, s4, v[0:1]
	s_load_b128 s[4:7], s[0:1], 0x8
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s3, v[5:6]
	v_lshlrev_b32_e32 v0, 2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v6, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 16
	global_store_b32 v[8:9], v7, off
	s_cbranch_scc0 .LBB1_1
; %bb.2:
	v_min_i32_e32 v3, v4, v5
	s_add_i32 s0, s3, -1
	s_add_i32 s1, s2, -1
	v_cmp_gt_i32_e32 vcc_lo, s0, v5
	v_cmp_gt_i32_e64 s0, s1, v4
	v_cmp_lt_i32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_5
; %bb.3:
	v_add_nc_u32_e32 v8, s3, v2
	v_mul_lo_u32 v2, v2, 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v8, 12
	v_add_nc_u32_e32 v6, 12, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[9:10], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v10, vcc_lo
	s_clause 0x3
	global_load_b32 v12, v[2:3], off
	global_load_b32 v9, v[4:5], off offset:36
	global_load_b32 v11, v[6:7], off offset:12
	global_load_b32 v10, v[2:3], off offset:24
	s_waitcnt vmcnt(2)
	v_max_f32_e32 v14, v9, v9
	s_waitcnt vmcnt(0)
	v_max3_f32 v13, v12, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f32_e32 v13, v13, v14
	v_cmp_lt_f32_e32 vcc_lo, 0, v13
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_clause 0x3
	global_load_b32 v13, v[2:3], off offset:4
	global_load_b32 v6, v[6:7], off offset:16
	global_load_b32 v4, v[4:5], off offset:40
	global_load_b32 v5, v[2:3], off offset:28
	v_dual_mul_f32 v2, 0x411cf5c3, v12 :: v_dual_mul_f32 v3, 0x411cf5c3, v11
	v_mul_f32_e32 v7, 0x411cf5c3, v10
	v_add_co_u32 v0, s3, s6, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mul_f32 v10, 0x4f800000, v2 :: v_dual_mul_f32 v11, 0x4f800000, v3
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_mul_f32_e32 v9, 0x411cf5c3, v9
	v_cmp_gt_f32_e64 s0, 0xf800000, v3
	v_add_co_ci_u32_e64 v1, s3, s7, v1, s3
	v_cndmask_b32_e32 v10, v2, v10, vcc_lo
	v_lshlrev_b32_e32 v2, 2, v8
	v_mul_f32_e32 v12, 0x4f800000, v7
	v_cndmask_b32_e64 v11, v3, v11, s0
	v_cmp_gt_f32_e64 s1, 0xf800000, v7
	v_sqrt_f32_e32 v3, v10
	v_mul_f32_e32 v14, 0x4f800000, v9
	v_cmp_gt_f32_e64 s2, 0xf800000, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_sqrt_f32_e32 v12, v11
	v_sqrt_f32_e32 v8, v7
	s_delay_alu instid0(TRANS32_DEP_3)
	v_add_nc_u32_e32 v15, -1, v3
	v_cndmask_b32_e64 v9, v9, v14, s2
	v_add_nc_u32_e32 v16, 1, v3
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, -1, v12
	v_sqrt_f32_e32 v14, v9
	v_fma_f32 v23, -v15, v3, v10
	v_add_nc_u32_e32 v18, 1, v12
	v_add_nc_u32_e32 v19, -1, v8
	v_fma_f32 v25, -v17, v12, v11
	v_fma_f32 v24, -v16, v3, v10
	v_cmp_ge_f32_e64 s3, 0, v23
	v_add_nc_u32_e32 v20, 1, v8
	v_fma_f32 v27, -v19, v8, v7
	v_fma_f32 v26, -v18, v12, v11
	v_add_nc_u32_e32 v21, -1, v14
	v_cndmask_b32_e64 v3, v3, v15, s3
	v_cmp_ge_f32_e64 s3, 0, v25
	v_add_nc_u32_e32 v22, 1, v14
	v_fma_f32 v28, -v20, v8, v7
	v_fma_f32 v29, -v21, v14, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, v12, v17, s3
	v_cmp_ge_f32_e64 s3, 0, v27
	v_fma_f32 v30, -v22, v14, v9
	v_cndmask_b32_e64 v8, v8, v19, s3
	v_cmp_ge_f32_e64 s3, 0, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v21, s3
	v_cmp_lt_f32_e64 s3, 0, v24
	v_cndmask_b32_e64 v15, v3, v16, s3
	v_cmp_lt_f32_e64 s3, 0, v26
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v16, 0x37800000, v15
	v_cndmask_b32_e64 v12, v12, v18, s3
	v_cmp_lt_f32_e64 s3, 0, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x37800000, v12
	v_cmp_class_f32_e64 vcc_lo, v10, 0x260
	v_cndmask_b32_e64 v12, v12, v17, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v15, v10, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
	v_cndmask_b32_e32 v11, v12, v11, vcc_lo
	v_cndmask_b32_e64 v8, v8, v20, s3
	v_cmp_lt_f32_e64 s3, 0, v30
	v_cmp_class_f32_e64 vcc_lo, v7, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, 0x37800000, v8
	v_cndmask_b32_e64 v14, v14, v22, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v8, v18, s1
	v_mul_f32_e32 v19, 0x37800000, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v8, v7, vcc_lo
	v_cndmask_b32_e64 v14, v14, v19, s2
	v_cmp_class_f32_e64 vcc_lo, v9, 0x260
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v14, v9, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v9, v13, v10 :: v_dual_sub_f32 v12, v6, v11
	v_add_f32_e32 v10, v10, v13
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v6, v11, v6 :: v_dual_sub_f32 v11, v5, v7
	v_sub_f32_e32 v13, v4, v8
	v_dual_add_f32 v5, v7, v5 :: v_dual_add_f32 v4, v8, v4
	v_min3_f32 v7, v9, v12, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max3_f32 v6, v10, v6, 0
	v_min3_f32 v8, v11, v13, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_max3_f32 v4, v5, v4, 0
	s_clause 0x3
	global_store_b32 v[0:1], v7, off
	global_store_b32 v[2:3], v6, off offset:4
	global_store_b32 v[0:1], v8, off offset:8
	global_store_b32 v[0:1], v4, off offset:28
.LBB1_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19CalculatePropSpeedsPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19CalculatePropSpeedsPfS_S_ii, .Lfunc_end1-_Z19CalculatePropSpeedsPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1188
; NumSgprs: 18
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22ReconstructFreeSurfacePfS_S_S_iiff
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z22ReconstructFreeSurfacePfS_S_S_iiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     77
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19CalculatePropSpeedsPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19CalculatePropSpeedsPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
