#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void j2d64pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
	//Determing the block's indices
	int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 4;
	int i = max(i0,4) + (int)(threadIdx.x);
	int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 4;
	int j = max(j0,4) + 4*(int)(threadIdx.y);

	double (*in)[8200] = (double (*)[8200]) l_in;
	double (*out)[8200] = (double (*)[8200]) l_out;

	if (i>=4 & j>=4 & i<=N-5 & j<=N-5) {
#pragma begin stencil1 unroll j=4,i=1
                                out[j][i] =
                                        (in[j-4][i-4] - in[j-4][i+4] - in[j+4][i-4] + in[j+4][i+4]) * 1.274495 +
                                        (-in[j-4][i-3] + in[j-4][i+3] + in[j-3][i+4] - in[j-3][i-4] + in[j+3][i-4] - in[j+3][i+4] + in[j+4][i-3] - in[j+4][i+3]) * 0.000136017 +
                                        (in[j-4][i-2] - in[j-4][i+2] + in[j-2][i-4] - in[j-2][i+4] - in[j+2][i-4] + in[j+2][i+4] - in[j+4][i-2] + in[j+4][i+2]) * 0.000714000 +
                                        (-in[j-4][i-1] + in[j-4][i+1] - in[j-1][i-4] + in[j-1][i+4] + in[j+1][i-4] - in[j+1][i+4] + in[j+4][i-1] - in[j+4][i+1]) * 0.00285600 +
                                        (in[j-3][i-3] - in[j-3][i+3] - in[j+3][i-3] + in[j+3][i+3]) * 0.00145161 +
                                        (-in[j-3][i-2] + in[j-3][i+2] - in[j-2][i-3] + in[j-2][i+3] + in[j+2][i-3] - in[j+2][i+3] + in[j+3][i-2] - in[j+3][i+2]) * 0.00762000 +
                                        (in[j-3][i-1] - in[j-3][i+1] + in[j-1][i-3] - in[j-1][i+3] - in[j+1][i-3] + in[j+1][i+3] - in[j+3][i-1] + in[j+3][i+1]) * 0.0304800 +
                                        (in[j-2][i-2] -  in[j-2][i+2] - in[j+2][i-2] + in[j+2][i+2]) * 0.0400000 +
                                        (-in[j-2][i-1] + in[j-2][i+1] - in[j-1][i-2] + in[j-1][i+2] + in[j+1][i-2] - in[j+1][i+2] + in[j+2][i-1] - in[j+2][i+1]) * 0.160000 +
                                        (in[j-1][i-1] - in[j-1][i+1] - in[j+1][i-1] + in[j+1][i+1]) * 0.640000;
#pragma end stencil1
	} 
}

extern "C" void host_code (double *h_in, double *h_out, int N) {
	double *in;
	cudaMalloc (&in, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for in\n");
	cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
	double *out;
	cudaMalloc (&out, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for out\n");

	dim3 blockconfig (16, 16);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));

	j2d64pt<<<gridconfig, blockconfig>>> (in, out, N);

	cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
	cudaFree (in); 
	cudaFree (out);
}

	.file	"tmpxft_002dd9a6_00000000-6_j2d64pt-reg.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z29__device_stub__Z7j2d64ptPdS_iPdS_i
	.type	_Z29__device_stub__Z7j2d64ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d64ptPdS_iPdS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7j2d64ptPdS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z29__device_stub__Z7j2d64ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d64ptPdS_iPdS_i
	.globl	_Z7j2d64ptPdS_i
	.type	_Z7j2d64ptPdS_i, @function
_Z7j2d64ptPdS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7j2d64ptPdS_iPdS_i
	.cfi_endproc
.LFE2054:
	.size	_Z7j2d64ptPdS_i, .-_Z7j2d64ptPdS_i
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for in\n"
.LC2:
	.string	"Failed to allocate device memory for out\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movslq	%edx, %rbx
	movq	%rbx, %rbp
	imulq	%rbx, %rbx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	salq	$3, %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movl	%ebp, %eax
	movl	%ebp, %edx
	movl	$1, 24(%rsp)
	shrl	$6, %eax
	shrl	$4, %edx
	testl	$63, %ebp
	je	.L14
	movl	%ebp, %ecx
	incl	%eax
	andl	$15, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %edx
.L14:
	movl	%edx, 28(%rsp)
	movl	24(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 32(%rsp)
	movq	28(%rsp), %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%ebp, %edx
	call	_Z29__device_stub__Z7j2d64ptPdS_iPdS_i
.L15:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC3:
	.string	"_Z7j2d64ptPdS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7j2d64ptPdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void j2d64pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
	//Determing the block's indices
	int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 4;
	int i = max(i0,4) + (int)(threadIdx.x);
	int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 4;
	int j = max(j0,4) + 4*(int)(threadIdx.y);

	double (*in)[8200] = (double (*)[8200]) l_in;
	double (*out)[8200] = (double (*)[8200]) l_out;

	if (i>=4 & j>=4 & i<=N-5 & j<=N-5) {
#pragma begin stencil1 unroll j=4,i=1
                                out[j][i] =
                                        (in[j-4][i-4] - in[j-4][i+4] - in[j+4][i-4] + in[j+4][i+4]) * 1.274495 +
                                        (-in[j-4][i-3] + in[j-4][i+3] + in[j-3][i+4] - in[j-3][i-4] + in[j+3][i-4] - in[j+3][i+4] + in[j+4][i-3] - in[j+4][i+3]) * 0.000136017 +
                                        (in[j-4][i-2] - in[j-4][i+2] + in[j-2][i-4] - in[j-2][i+4] - in[j+2][i-4] + in[j+2][i+4] - in[j+4][i-2] + in[j+4][i+2]) * 0.000714000 +
                                        (-in[j-4][i-1] + in[j-4][i+1] - in[j-1][i-4] + in[j-1][i+4] + in[j+1][i-4] - in[j+1][i+4] + in[j+4][i-1] - in[j+4][i+1]) * 0.00285600 +
                                        (in[j-3][i-3] - in[j-3][i+3] - in[j+3][i-3] + in[j+3][i+3]) * 0.00145161 +
                                        (-in[j-3][i-2] + in[j-3][i+2] - in[j-2][i-3] + in[j-2][i+3] + in[j+2][i-3] - in[j+2][i+3] + in[j+3][i-2] - in[j+3][i+2]) * 0.00762000 +
                                        (in[j-3][i-1] - in[j-3][i+1] + in[j-1][i-3] - in[j-1][i+3] - in[j+1][i-3] + in[j+1][i+3] - in[j+3][i-1] + in[j+3][i+1]) * 0.0304800 +
                                        (in[j-2][i-2] -  in[j-2][i+2] - in[j+2][i-2] + in[j+2][i+2]) * 0.0400000 +
                                        (-in[j-2][i-1] + in[j-2][i+1] - in[j-1][i-2] + in[j-1][i+2] + in[j+1][i-2] - in[j+1][i+2] + in[j+2][i-1] - in[j+2][i+1]) * 0.160000 +
                                        (in[j-1][i-1] - in[j-1][i+1] - in[j+1][i-1] + in[j+1][i+1]) * 0.640000;
#pragma end stencil1
	} 
}

extern "C" void host_code (double *h_in, double *h_out, int N) {
	double *in;
	hipMalloc (&in, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for in\n");
	hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
	double *out;
	hipMalloc (&out, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for out\n");

	dim3 blockconfig (16, 16);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));

	j2d64pt<<<gridconfig, blockconfig>>> (in, out, N);

	hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
	hipFree (in); 
	hipFree (out);
}

	.text
	.file	"j2d64pt-reg.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__j2d64ptPdS_i # -- Begin function _Z22__device_stub__j2d64ptPdS_i
	.type	_Z22__device_stub__j2d64ptPdS_i,@function
_Z22__device_stub__j2d64ptPdS_i:        # @_Z22__device_stub__j2d64ptPdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7j2d64ptPdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__j2d64ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d64ptPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movq	%rdi, %r12
	movslq	%edx, %r15
	movq	%r15, %r14
	imulq	%r15, %r14
	shlq	$3, %r14
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movl	%r15d, %eax
	andl	$15, %eax
	movl	%r15d, %ecx
	shrl	$4, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%r15d, %eax
	andl	$63, %eax
	shrl	$6, %r15d
	cmpl	$1, %eax
	sbbl	$-1, %r15d
	shlq	$32, %r15
	orq	%rcx, %r15
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%ebp, %edx
	callq	_Z22__device_stub__j2d64ptPdS_i
.LBB2_2:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7j2d64ptPdS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z7j2d64ptPdS_i,@object         # @_Z7j2d64ptPdS_i
	.section	.rodata,"a",@progbits
	.globl	_Z7j2d64ptPdS_i
	.p2align	3, 0x0
_Z7j2d64ptPdS_i:
	.quad	_Z22__device_stub__j2d64ptPdS_i
	.size	_Z7j2d64ptPdS_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for in\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for out\n"
	.size	.L.str.2, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7j2d64ptPdS_i"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__j2d64ptPdS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7j2d64ptPdS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7j2d64ptPdS_i         ; -- Begin function _Z7j2d64ptPdS_i
	.globl	_Z7j2d64ptPdS_i
	.p2align	8
	.type	_Z7j2d64ptPdS_i,@function
_Z7j2d64ptPdS_i:                        ; @_Z7j2d64ptPdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_lshrrev_b32_e32 v0, 8, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v2, 0xffc, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s4
	s_mul_i32 s15, s15, s2
	s_max_i32 s4, s14, 0
	s_lshl_b32 s2, s15, 2
	v_add_nc_u32_e32 v0, s4, v1
	s_max_i32 s2, s2, 0
	s_add_i32 s3, s3, -5
	v_add_nc_u32_e32 v2, s2, v2
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v4, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 4, v2
	v_max_i32_e32 v1, v4, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, 8, v0
	v_add_nc_u32_e32 v14, 7, v0
	v_add_nc_u32_e32 v16, 6, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[20:21], 3, v[0:1]
	v_mov_b32_e32 v15, v6
	v_mov_b32_e32 v1, v6
	v_or_b32_e32 v32, 3, v13
	v_dual_mov_b32 v17, v6 :: v_dual_add_nc_u32 v18, 3, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[26:27], 3, v[14:15]
	v_lshlrev_b64 v[24:25], 3, v[5:6]
	v_add_nc_u32_e32 v5, 2, v0
	v_or_b32_e32 v34, 2, v13
	v_lshlrev_b64 v[30:31], 3, v[16:17]
	v_or_b32_e32 v36, 1, v13
	v_dual_mov_b32 v10, v6 :: v_dual_add_nc_u32 v9, 1, v0
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[22:23], null, 0x10040, v2, s[0:1]
	v_lshlrev_b64 v[1:2], 3, v[0:1]
	v_mad_u64_u32 v[14:15], null, 0x10040, v13, s[0:1]
	v_mad_u64_u32 v[16:17], null, 0x10040, v32, s[0:1]
	v_lshlrev_b64 v[28:29], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, v22, v1
	v_add_co_ci_u32_e32 v12, vcc_lo, v23, v2, vcc_lo
	v_add_co_u32 v22, vcc_lo, v22, v20
	v_add_co_ci_u32_e32 v23, vcc_lo, v23, v21, vcc_lo
	v_add_co_u32 v5, vcc_lo, 0x40100, v14
	v_add_co_ci_u32_e32 v96, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v97, vcc_lo, 0xfffcff40, v14
	v_add_co_ci_u32_e32 v98, vcc_lo, -1, v15, vcc_lo
	v_mad_u64_u32 v[32:33], null, 0x10040, v34, s[0:1]
	v_mad_u64_u32 v[34:35], null, 0x10040, v36, s[0:1]
	v_add_co_u32 v36, vcc_lo, v16, v20
	v_add_co_ci_u32_e32 v37, vcc_lo, v17, v21, vcc_lo
	v_add_co_u32 v38, vcc_lo, v16, v24
	v_add_co_ci_u32_e32 v39, vcc_lo, v17, v25, vcc_lo
	v_add_co_u32 v99, vcc_lo, 0xfffdff80, v14
	v_add_co_ci_u32_e32 v100, vcc_lo, -1, v15, vcc_lo
	v_add_co_u32 v40, vcc_lo, v32, v20
	v_add_co_ci_u32_e32 v41, vcc_lo, v33, v21, vcc_lo
	v_add_co_u32 v42, vcc_lo, v32, v24
	v_add_co_ci_u32_e32 v43, vcc_lo, v33, v25, vcc_lo
	v_add_co_u32 v101, vcc_lo, 0xfffeffc0, v14
	v_dual_mov_b32 v8, v6 :: v_dual_add_nc_u32 v7, 5, v0
	v_add_co_ci_u32_e32 v102, vcc_lo, -1, v15, vcc_lo
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v44, vcc_lo, v34, v20
	v_add_co_ci_u32_e32 v45, vcc_lo, v35, v21, vcc_lo
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v46, vcc_lo, v34, v24
	v_add_co_ci_u32_e32 v47, vcc_lo, v35, v25, vcc_lo
	v_add_co_u32 v48, vcc_lo, v16, v9
	v_add_co_ci_u32_e32 v49, vcc_lo, v17, v10, vcc_lo
	v_add_co_u32 v50, vcc_lo, v16, v7
	v_add_co_ci_u32_e32 v51, vcc_lo, v17, v8, vcc_lo
	v_add_co_u32 v52, vcc_lo, v32, v9
	v_add_co_ci_u32_e32 v53, vcc_lo, v33, v10, vcc_lo
	v_add_co_u32 v54, vcc_lo, v32, v26
	v_add_co_ci_u32_e32 v55, vcc_lo, v33, v27, vcc_lo
	v_add_co_u32 v56, vcc_lo, v16, v28
	v_add_co_ci_u32_e32 v57, vcc_lo, v17, v29, vcc_lo
	v_add_co_u32 v58, vcc_lo, v34, v9
	v_add_co_ci_u32_e32 v59, vcc_lo, v35, v10, vcc_lo
	v_add_co_u32 v60, vcc_lo, v34, v26
	v_add_co_ci_u32_e32 v61, vcc_lo, v35, v27, vcc_lo
	v_add_co_u32 v62, vcc_lo, v32, v28
	v_mov_b32_e32 v19, v6
	v_add_co_ci_u32_e32 v63, vcc_lo, v33, v29, vcc_lo
	v_add_co_u32 v64, vcc_lo, v32, v7
	v_add_co_ci_u32_e32 v65, vcc_lo, v33, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[18:19], 3, v[18:19]
	v_add_co_u32 v66, vcc_lo, v34, v28
	v_add_co_ci_u32_e32 v67, vcc_lo, v35, v29, vcc_lo
	v_add_co_u32 v68, vcc_lo, v34, v30
	v_add_co_ci_u32_e32 v69, vcc_lo, v35, v31, vcc_lo
	v_add_co_u32 v70, vcc_lo, v32, v18
	v_add_co_ci_u32_e32 v71, vcc_lo, v33, v19, vcc_lo
	v_add_co_u32 v72, vcc_lo, v34, v18
	v_add_co_ci_u32_e32 v73, vcc_lo, v35, v19, vcc_lo
	v_add_co_u32 v34, vcc_lo, v34, v7
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v8, vcc_lo
	v_add_co_u32 v32, vcc_lo, v5, v20
	v_add_co_ci_u32_e32 v33, vcc_lo, v96, v21, vcc_lo
	s_clause 0x3
	global_load_b128 v[0:3], v[11:12], off offset:56
	global_load_b64 v[22:23], v[22:23], off
	global_load_b128 v[14:17], v[11:12], off offset:8
	global_load_b64 v[32:33], v[32:33], off
	v_add_co_u32 v74, vcc_lo, v97, v20
	v_add_co_ci_u32_e32 v75, vcc_lo, v98, v21, vcc_lo
	v_add_co_u32 v76, vcc_lo, v99, v20
	v_add_co_ci_u32_e32 v77, vcc_lo, v100, v21, vcc_lo
	v_add_co_u32 v20, vcc_lo, v101, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, v102, v21, vcc_lo
	v_add_co_u32 v78, vcc_lo, v97, v24
	v_add_co_ci_u32_e32 v79, vcc_lo, v98, v25, vcc_lo
	v_add_co_u32 v80, vcc_lo, v99, v24
	v_add_co_ci_u32_e32 v81, vcc_lo, v100, v25, vcc_lo
	v_add_co_u32 v24, vcc_lo, v101, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, v102, v25, vcc_lo
	s_mov_b32 s0, 0x222681b0
	s_mov_b32 s1, 0x3f21d3f9
	s_waitcnt vmcnt(2)
	v_add_f64 v[22:23], v[22:23], -v[2:3]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[0:1], -v[14:15]
	s_clause 0x1
	global_load_b64 v[82:83], v[11:12], off offset:24
	global_load_b128 v[0:3], v[11:12], off offset:40
	s_waitcnt vmcnt(2)
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_waitcnt vmcnt(0)
	v_add_f64 v[11:12], v[16:17], -v[2:3]
	v_add_f64 v[16:17], v[0:1], -v[82:83]
	v_add_co_u32 v82, vcc_lo, v5, v9
	v_add_co_ci_u32_e32 v83, vcc_lo, v96, v10, vcc_lo
	v_add_co_u32 v84, vcc_lo, v97, v9
	v_add_co_ci_u32_e32 v85, vcc_lo, v98, v10, vcc_lo
	v_add_co_u32 v86, vcc_lo, v99, v9
	v_add_co_ci_u32_e32 v87, vcc_lo, v100, v10, vcc_lo
	v_add_co_u32 v88, vcc_lo, v101, v9
	v_add_co_ci_u32_e32 v89, vcc_lo, v102, v10, vcc_lo
	v_add_co_u32 v90, vcc_lo, v99, v26
	v_add_co_ci_u32_e32 v91, vcc_lo, v100, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, v101, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, v102, v27, vcc_lo
	v_add_co_u32 v92, vcc_lo, v99, v28
	v_add_co_ci_u32_e32 v93, vcc_lo, v100, v29, vcc_lo
	v_add_co_u32 v28, vcc_lo, v101, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, v102, v29, vcc_lo
	v_add_co_u32 v30, vcc_lo, v101, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, v102, v31, vcc_lo
	v_add_co_u32 v94, vcc_lo, v101, v18
	v_add_co_ci_u32_e32 v95, vcc_lo, v102, v19, vcc_lo
	v_add_co_u32 v18, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v19, vcc_lo, v96, v8, vcc_lo
	v_add_co_u32 v0, vcc_lo, v97, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v98, v8, vcc_lo
	v_add_co_u32 v96, vcc_lo, v99, v7
	v_add_co_ci_u32_e32 v97, vcc_lo, v100, v8, vcc_lo
	v_add_co_u32 v98, vcc_lo, v101, v7
	v_add_co_ci_u32_e32 v99, vcc_lo, v102, v8, vcc_lo
	s_clause 0x3
	global_load_b64 v[100:101], v[0:1], off offset:16
	global_load_b128 v[0:3], v[0:1], off
	global_load_b64 v[102:103], v[84:85], off offset:16
	global_load_b128 v[7:10], v[84:85], off
	v_mov_b32_e32 v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[102:103], -v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], -v[9:10]
	s_clause 0x3
	global_load_b64 v[9:10], v[78:79], off
	global_load_b64 v[74:75], v[74:75], off
	global_load_b64 v[36:37], v[36:37], off
	global_load_b64 v[38:39], v[38:39], off
	v_add_f64 v[7:8], v[7:8], -v[100:101]
	s_waitcnt vmcnt(3)
	v_add_f64 v[9:10], v[14:15], v[9:10]
	s_clause 0x3
	global_load_b64 v[14:15], v[76:77], off
	global_load_b64 v[76:77], v[80:81], off
	global_load_b64 v[40:41], v[40:41], off
	global_load_b64 v[42:43], v[42:43], off
	s_waitcnt vmcnt(3)
	v_add_f64 v[11:12], v[11:12], v[14:15]
	s_clause 0x3
	global_load_b64 v[14:15], v[20:21], off
	global_load_b64 v[20:21], v[24:25], off
	global_load_b64 v[32:33], v[44:45], off
	global_load_b64 v[44:45], v[46:47], off
	s_waitcnt vmcnt(6)
	v_add_f64 v[24:25], v[11:12], -v[76:77]
	s_waitcnt vmcnt(3)
	v_add_f64 v[14:15], v[16:17], -v[14:15]
	s_clause 0x3
	global_load_b64 v[16:17], v[86:87], off
	global_load_b64 v[46:47], v[90:91], off
	global_load_b64 v[52:53], v[52:53], off
	global_load_b64 v[78:79], v[50:51], off offset:16
	s_waitcnt vmcnt(3)
	v_add_f64 v[80:81], v[2:3], -v[16:17]
	v_add_f64 v[2:3], v[9:10], -v[74:75]
	s_clause 0x3
	global_load_b64 v[9:10], v[88:89], off
	global_load_b64 v[74:75], v[26:27], off
	global_load_b64 v[58:59], v[58:59], off
	global_load_b64 v[60:61], v[60:61], off
	v_add_f64 v[26:27], v[14:15], v[20:21]
	s_waitcnt vmcnt(6)
	v_add_f64 v[46:47], v[80:81], v[46:47]
	v_add_f64 v[16:17], v[2:3], v[36:37]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[38:39]
	s_waitcnt vmcnt(3)
	v_add_f64 v[36:37], v[0:1], v[9:10]
	s_clause 0x2
	global_load_b128 v[0:3], v[82:83], off
	global_load_b128 v[9:12], v[18:19], off offset:16
	global_load_b64 v[38:39], v[82:83], off offset:16
	s_waitcnt vmcnt(1)
	v_add_f64 v[76:77], v[22:23], v[11:12]
	v_add_f64 v[0:1], v[16:17], v[0:1]
	global_load_b128 v[14:17], v[18:19], off
	v_add_f64 v[0:1], v[0:1], -v[9:10]
	s_clause 0x5
	global_load_b128 v[9:12], v[92:93], off
	global_load_b128 v[18:21], v[96:97], off
	global_load_b64 v[48:49], v[48:49], off
	global_load_b64 v[82:83], v[28:29], off
	global_load_b64 v[54:55], v[54:55], off
	global_load_b64 v[84:85], v[30:31], off
	v_add_f64 v[30:31], v[24:25], -v[40:41]
	s_clause 0x1
	global_load_b128 v[22:25], v[56:57], off
	global_load_b64 v[40:41], v[66:67], off
	v_add_f64 v[56:57], v[26:27], v[32:33]
	s_clause 0x2
	global_load_b128 v[26:29], v[50:51], off
	global_load_b64 v[50:51], v[62:63], off
	global_load_b64 v[62:63], v[68:69], off
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	s_mov_b32 s0, 0xde7ea5f8
	v_add_f64 v[42:43], v[30:31], v[42:43]
	s_clause 0x5
	global_load_b128 v[30:33], v[64:65], off
	global_load_b64 v[64:65], v[70:71], off
	global_load_b64 v[66:67], v[94:95], off
	global_load_b64 v[68:69], v[98:99], off
	global_load_b64 v[70:71], v[72:73], off
	global_load_b64 v[34:35], v[34:35], off
	v_add_f64 v[44:45], v[56:57], -v[44:45]
	s_mov_b32 s1, 0x3ff46454
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[76:77], s[0:1], v[0:1]
	s_mov_b32 s1, 0x3f476577
	v_add_f64 v[2:3], v[42:43], -v[2:3]
	s_mov_b32 s0, 0x531db446
	s_waitcnt vmcnt(18)
	v_add_f64 v[38:39], v[44:45], v[38:39]
	s_waitcnt vmcnt(17)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[16:17]
	v_add_f64 v[14:15], v[38:39], -v[14:15]
	s_waitcnt vmcnt(15)
	v_add_f64 v[11:12], v[18:19], -v[11:12]
	v_add_f64 v[18:19], v[36:37], -v[74:75]
	v_add_f64 v[36:37], v[46:47], v[52:53]
	s_waitcnt vmcnt(14)
	v_add_f64 v[7:8], v[7:8], -v[48:49]
	v_fma_f64 v[0:1], v[2:3], s[0:1], v[0:1]
	s_mov_b32 s1, 0x3f676577
	v_add_f64 v[9:10], v[9:10], -v[20:21]
	s_waitcnt vmcnt(13)
	v_add_f64 v[11:12], v[11:12], -v[82:83]
	v_add_f64 v[16:17], v[18:19], -v[58:59]
	s_waitcnt vmcnt(12)
	v_add_f64 v[18:19], v[36:37], -v[54:55]
	v_add_f64 v[2:3], v[7:8], v[78:79]
	v_fma_f64 v[0:1], v[14:15], s[0:1], v[0:1]
	s_mov_b32 s0, 0x5e7fbd25
	s_mov_b32 s1, 0x3f57c87e
	s_waitcnt vmcnt(11)
	v_add_f64 v[7:8], v[11:12], v[84:85]
	v_add_f64 v[11:12], v[16:17], v[60:61]
	s_waitcnt vmcnt(10)
	v_add_f64 v[16:17], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[0:1], v[2:3], s[0:1], v[0:1]
	s_mov_b32 s1, 0x3f7f3626
	s_mov_b32 s0, 0x2cba732e
	s_waitcnt vmcnt(7)
	v_add_f64 v[2:3], v[9:10], -v[50:51]
	v_add_f64 v[7:8], v[7:8], v[40:41]
	v_add_f64 v[11:12], v[11:12], -v[24:25]
	v_add_f64 v[14:15], v[16:17], -v[28:29]
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[2:3], v[2:3], v[32:33]
	v_add_f64 v[7:8], v[7:8], -v[62:63]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[11:12], v[26:27]
	v_fma_f64 v[0:1], v[14:15], s[0:1], v[0:1]
	s_mov_b32 s1, 0x3f9f3626
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[64:65]
	v_fma_f64 v[0:1], v[9:10], s[0:1], v[0:1]
	s_waitcnt vmcnt(2)
	v_add_f64 v[9:10], v[66:67], -v[68:69]
	s_mov_b32 s1, 0x3fa47ae1
	s_mov_b32 s0, 0x47ae147b
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[30:31]
	v_fma_f64 v[0:1], v[2:3], s[0:1], v[0:1]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[2:3], v[9:10], -v[70:71]
	s_mov_b32 s1, 0x3fc47ae1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[7:8], s[0:1], v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[34:35]
	s_mov_b32 s1, 0x3fe47ae1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[2:3], s[0:1], v[0:1]
	v_mad_u64_u32 v[2:3], null, 0x10040, v13, s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7j2d64ptPdS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 104
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7j2d64ptPdS_i, .Lfunc_end0-_Z7j2d64ptPdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2264
; NumSgprs: 18
; NumVgprs: 104
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 104
; Occupancy: 12
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7j2d64ptPdS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7j2d64ptPdS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     104
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
