#include "includes.h"

#define ROUND_OFF 50000

#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32

#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)

#define GET_BLOCKS(n, t) (n+t-1) / t

// == Dimension rearrangement Kernel

__global__ void CorrelateDataBackward0Subtract_1d(const int nthreads, int num, int item, int topwidth, int topheight, int topchannels, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int stride1, int stride2, int bottomwidth, int bottomheight, int pbottomwidth, int pbottomheight, int bottomchannels, int bottomcount, int pad_size, float *bottom0diff, const float *bottom0, const float *bottom1, const float *topdiff)
{
CUDA_KERNEL_LOOP(index, nthreads) {
int l = index % bottomwidth + pad_size; //w-pos
int m = (index / bottomwidth) % bottomheight; //h-pos
int n = (index / bottomwidth / bottomheight) % bottomchannels; //channels

//Get X,Y ranges and clamp
// round_off is a trick to enable integer division with ceil, even for negative numbers
// We use a large offset, for the inner part not to become negative.
const int round_off = ROUND_OFF;
const int round_off_s1 = stride1 * round_off;

// We add round_off before_s1 the int division and subtract round_off after it, to ensure the formula matches ceil behavior:
int xmin = (l - 2*kernel_radius - max_displacement + round_off_s1 - 1) / stride1 + 1 - round_off; // ceil (l - 2*kernel_radius - max_displacement) / stride1
int ymin = (m - 2*kernel_radius - 0 + round_off_s1 - 1) / stride1 + 1 - round_off; // ceil (l - 2*kernel_radius - max_displacement) / stride1

// Same here:
int xmax = (l - max_displacement + round_off_s1) / stride1 - round_off; // floor (l - max_displacement) / stride1
int ymax = (m - 0 + round_off_s1) / stride1 - round_off; // floor (m - max_displacement) / stride1


float sum = 0;
if(xmax>=0 && ymax>=0 && (xmin<=topwidth-1) && (ymin<=topheight-1))
{
xmin = max(0,xmin);
xmax = min(topwidth-1,xmax);

ymin = max(0,ymin);
ymax = min(topheight-1,ymax);

{
for(int o = x_shift; o < x_shift + neighborhood_grid_width; o++) {

// Get bottom1 data:
int s2o = stride2 * o;
int idxbot = ((item * pbottomheight + (m)) * pbottomwidth + (l+s2o)) * bottomchannels + n;
float bot0tmp = bottom0[idxbot]; // bottom0[l+s2o,m,n]
float bot1tmp = bottom1[idxbot]; // bottom1[l+s2o,m,n]
float sign = (bot0tmp >= bot1tmp) ? float(1.0) : float(-1.0);

// Index offset for topdiff in following loops:
int op = (o-x_shift); // index [o,p]
int idxopoffset = (item * topchannels + op);

for(int y = ymin; y <= ymax; y++) {
for(int x = xmin; x <= xmax; x++) {
int idxtopdiff = (idxopoffset * topheight + y) * topwidth + x; // topdiff[x,y,o,p]
sum += topdiff[idxtopdiff] * sign;
}
}
}
}
}
const int sumelems = (kernel_radius*2+1)*(kernel_radius*2+1)*bottomchannels;
bottom0diff[index + item*bottomcount] = sum / (float)sumelems;
}

}
	.file	"tmpxft_00275116_00000000-6_CorrelateDataBackward0Subtract_1d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z81__device_stub__Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_iiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.type	_Z81__device_stub__Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_iiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, @function
_Z81__device_stub__Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_iiiiiiiiiiiiiiiiiiiPfPKfS1_S1_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	440(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	448(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	456(%rsp), %rax
	movl	%ecx, 48(%rsp)
	leaq	72(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	464(%rsp), %rax
	movl	%r8d, 44(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	416(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	424(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	432(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 352
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L2:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z81__device_stub__Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_iiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, .-_Z81__device_stub__Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_iiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.globl	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.type	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, @function
_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z81__device_stub__Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_iiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.cfi_endproc
.LFE2033:
	.size	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, .-_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

#define ROUND_OFF 50000

#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32

#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)

#define GET_BLOCKS(n, t) (n+t-1) / t

// == Dimension rearrangement Kernel

__global__ void CorrelateDataBackward0Subtract_1d(const int nthreads, int num, int item, int topwidth, int topheight, int topchannels, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int stride1, int stride2, int bottomwidth, int bottomheight, int pbottomwidth, int pbottomheight, int bottomchannels, int bottomcount, int pad_size, float *bottom0diff, const float *bottom0, const float *bottom1, const float *topdiff)
{
CUDA_KERNEL_LOOP(index, nthreads) {
int l = index % bottomwidth + pad_size; //w-pos
int m = (index / bottomwidth) % bottomheight; //h-pos
int n = (index / bottomwidth / bottomheight) % bottomchannels; //channels

//Get X,Y ranges and clamp
// round_off is a trick to enable integer division with ceil, even for negative numbers
// We use a large offset, for the inner part not to become negative.
const int round_off = ROUND_OFF;
const int round_off_s1 = stride1 * round_off;

// We add round_off before_s1 the int division and subtract round_off after it, to ensure the formula matches ceil behavior:
int xmin = (l - 2*kernel_radius - max_displacement + round_off_s1 - 1) / stride1 + 1 - round_off; // ceil (l - 2*kernel_radius - max_displacement) / stride1
int ymin = (m - 2*kernel_radius - 0 + round_off_s1 - 1) / stride1 + 1 - round_off; // ceil (l - 2*kernel_radius - max_displacement) / stride1

// Same here:
int xmax = (l - max_displacement + round_off_s1) / stride1 - round_off; // floor (l - max_displacement) / stride1
int ymax = (m - 0 + round_off_s1) / stride1 - round_off; // floor (m - max_displacement) / stride1


float sum = 0;
if(xmax>=0 && ymax>=0 && (xmin<=topwidth-1) && (ymin<=topheight-1))
{
xmin = max(0,xmin);
xmax = min(topwidth-1,xmax);

ymin = max(0,ymin);
ymax = min(topheight-1,ymax);

{
for(int o = x_shift; o < x_shift + neighborhood_grid_width; o++) {

// Get bottom1 data:
int s2o = stride2 * o;
int idxbot = ((item * pbottomheight + (m)) * pbottomwidth + (l+s2o)) * bottomchannels + n;
float bot0tmp = bottom0[idxbot]; // bottom0[l+s2o,m,n]
float bot1tmp = bottom1[idxbot]; // bottom1[l+s2o,m,n]
float sign = (bot0tmp >= bot1tmp) ? float(1.0) : float(-1.0);

// Index offset for topdiff in following loops:
int op = (o-x_shift); // index [o,p]
int idxopoffset = (item * topchannels + op);

for(int y = ymin; y <= ymax; y++) {
for(int x = xmin; x <= xmax; x++) {
int idxtopdiff = (idxopoffset * topheight + y) * topwidth + x; // topdiff[x,y,o,p]
sum += topdiff[idxtopdiff] * sign;
}
}
}
}
}
const int sumelems = (kernel_radius*2+1)*(kernel_radius*2+1)*bottomchannels;
bottom0diff[index + item*bottomcount] = sum / (float)sumelems;
}

}
	.text
	.file	"CorrelateDataBackward0Subtract_1d.hip"
	.globl	_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_ # -- Begin function _Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.type	_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_,@function
_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_: # @_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, .Lfunc_end0-_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_,@object # @_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.p2align	3, 0x0
_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_:
	.quad	_Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.size	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_"
	.size	.L__unnamed_1, 68

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z48__device_stub__CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_ ; -- Begin function _Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.globl	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
	.p2align	8
	.type	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_,@function
_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_: ; @_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x7c
	s_load_b32 s28, s[0:1], 0x0
	s_add_u32 s2, s0, 0x70
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s43, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s43, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s28, v1
	s_cbranch_execz .LBB0_18
; %bb.1:                                ; %.lr.ph129
	s_load_b512 s[4:19], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s44, s11, 1
	s_not_b32 s20, s8
	s_mul_i32 s29, s12, 0xc350
	s_sub_i32 s33, s20, s44
	s_not_b32 s20, s44
	s_add_i32 s11, s5, -1
	s_add_i32 s30, s6, -1
	s_add_i32 s31, s10, s9
	s_sub_i32 s8, s29, s8
	s_add_i32 s33, s33, s29
	s_add_i32 s34, s29, s20
	s_cmp_gt_i32 s10, 0
	s_mul_i32 s17, s17, s4
	s_cselect_b32 s10, -1, 0
	s_ashr_i32 s37, s12, 31
	s_ashr_i32 s35, s14, 31
	s_add_i32 s24, s12, s37
	s_ashr_i32 s36, s15, 31
	s_xor_b32 s40, s24, s37
	s_ashr_i32 s20, s18, 31
	v_cvt_f32_u32_e32 v4, s40
	s_add_i32 s21, s14, s35
	s_add_i32 s22, s15, s36
	s_add_i32 s23, s18, s20
	s_xor_b32 s12, s21, s35
	v_rcp_iflag_f32_e32 v4, v4
	s_xor_b32 s38, s22, s36
	s_xor_b32 s39, s23, s20
	v_cvt_f32_u32_e32 v0, s12
	v_cvt_f32_u32_e32 v2, s38
	v_cvt_f32_u32_e32 v3, s39
	s_sub_i32 s42, 0, s40
	s_clause 0x1
	s_load_b32 s41, s[0:1], 0x48
	s_load_b256 s[20:27], s[0:1], 0x50
	s_load_b32 s0, s[2:3], 0x0
	v_rcp_iflag_f32_e32 v0, v0
	v_rcp_iflag_f32_e32 v2, v2
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_rcp_iflag_f32_e32 v3, v3
	s_sub_i32 s1, 0, s12
	s_sub_i32 s2, 0, s38
	s_sub_i32 s3, 0, s39
	v_cvt_u32_f32_e32 v4, v4
	s_mul_i32 s19, s19, s4
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_mul_lo_u32 v8, s42, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_mov_b32 s42, 0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_hi_u32 v11, v4, v8
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_mul_lo_u32 v5, s1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v7, s3, v3
	s_or_b32 s1, s44, 1
	s_mul_i32 s1, s1, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v11, v4, v11
	v_cvt_u32_f32_e32 v2, v2
	v_mul_hi_u32 v5, v0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, v3, v7
	s_mul_i32 s1, s1, s18
	v_mul_lo_u32 v6, s2, v2
	v_cvt_f32_i32_e32 v7, s1
	s_mul_i32 s2, s7, s6
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s0, s43
	v_add_nc_u32_e32 v8, v0, v5
	v_add_nc_u32_e32 v10, v3, v10
	s_mul_i32 s4, s2, s4
	s_mul_i32 s43, s6, s5
	v_mul_hi_u32 v6, v2, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v2, v6
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_8 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
	v_ashrrev_i32_e32 v0, 31, v1
	s_mov_b32 s44, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v0
	v_xor_b32_e32 v2, v2, v0
	v_xor_b32_e32 v0, s35, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v8
	v_mul_lo_u32 v4, v3, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s12, v2
	v_cmp_le_u32_e32 vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s12, v2
	v_cndmask_b32_e32 v2, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v0
	v_sub_nc_u32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 31, v2
	v_add_nc_u32_e32 v3, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v0
	v_xor_b32_e32 v0, s36, v0
	v_mul_hi_u32 v4, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v4, s38
	v_sub_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s38, v3
	v_cmp_le_u32_e32 vcc_lo, s38, v3
	v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s38, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v4, v5, vcc_lo
	v_mul_lo_u32 v4, v2, s14
	v_xor_b32_e32 v3, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v3, v0
	v_sub_nc_u32_e32 v0, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s15
	v_add_nc_u32_e32 v0, s41, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v5, s29, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v5
	v_add_nc_u32_e32 v5, v5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v12
	v_xor_b32_e32 v12, s37, v12
	v_mul_hi_u32 v14, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, v14, s40
	v_add_nc_u32_e32 v17, 1, v14
	v_sub_nc_u32_e32 v5, v5, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s0, s40, v5
	v_cndmask_b32_e64 v14, v14, v17, s0
	v_add_nc_u32_e32 v4, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v4
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v6
	v_xor_b32_e32 v6, s37, v6
	v_mul_hi_u32 v13, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, v13, s40
	v_sub_nc_u32_e32 v4, v4, v15
	v_add_nc_u32_e32 v15, 1, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v16, s40, v4
	v_cmp_le_u32_e32 vcc_lo, s40, v4
	v_cndmask_b32_e32 v13, v13, v15, vcc_lo
	v_subrev_nc_u32_e32 v15, s40, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v4, v16, vcc_lo
	v_add_nc_u32_e32 v16, 1, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v5, v15, s0
	v_cmp_le_u32_e32 vcc_lo, s40, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v4, v13, v16 :: v_dual_add_nc_u32 v15, 1, v14
	v_cmp_le_u32_e32 vcc_lo, s40, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v6
	v_cndmask_b32_e32 v5, v14, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v6
	v_xor_b32_e32 v5, v5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v12
	v_mov_b32_e32 v12, 0
	v_min_i32_e32 v6, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0xc34f, v6
	s_cbranch_execz .LBB0_17
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v12, s34, v2
	v_add_nc_u32_e32 v6, s33, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v14, 31, v12
	v_ashrrev_i32_e32 v13, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v12, v14
	v_add_nc_u32_e32 v6, v6, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v12, v12, v14
	v_xor_b32_e32 v6, v6, v13
	v_xor_b32_e32 v13, s37, v13
	v_xor_b32_e32 v14, s37, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v16, v12, v11
	v_mul_hi_u32 v15, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v18, v16, s40
	v_mul_lo_u32 v17, v15, s40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v12, v12, v18
	v_add_nc_u32_e32 v18, 1, v16
	v_sub_nc_u32_e32 v6, v6, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s0, s40, v12
	v_subrev_nc_u32_e32 v19, s40, v12
	v_cmp_le_u32_e32 vcc_lo, s40, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v16, v18, s0
	v_cndmask_b32_e64 v12, v12, v19, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v18, 1, v16
	v_add_nc_u32_e32 v17, 1, v15
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_subrev_nc_u32_e32 v17, s40, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v6, v17 :: v_dual_add_nc_u32 v17, 1, v15
	v_cmp_le_u32_e32 vcc_lo, s40, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v15, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s40, v12
	v_xor_b32_e32 v6, v6, v13
	v_cndmask_b32_e32 v12, v16, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v13
	v_xor_b32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0xffff3cb1, v6
	v_sub_nc_u32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v6
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v13, 0xffff3cb1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s6, v13
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s45, s0
	s_cbranch_execz .LBB0_16
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_15
; %bb.5:                                ; %.lr.ph125
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v12, 31, v3
	v_max_i32_e32 v13, 0, v13
	v_add_nc_u32_e32 v16, s17, v2
	s_mov_b32 s46, s9
	v_add_nc_u32_e32 v4, 0xffff3cb0, v4
	v_add_nc_u32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v12
	v_mul_hi_u32 v14, v3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v14, v14, s39
	v_sub_nc_u32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v14, s39, v3
	v_cmp_le_u32_e32 vcc_lo, s39, v3
	v_cndmask_b32_e32 v3, v3, v14, vcc_lo
	v_min_i32_e32 v14, s11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s39, v3
	v_add_nc_u32_e32 v15, 0xffff3cb0, v5
	v_max_i32_e32 v5, 0, v6
	v_subrev_nc_u32_e32 v6, s39, v3
	v_cmp_le_i32_e64 s0, v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, v3, v6, vcc_lo
	v_mad_u64_u32 v[2:3], null, v16, s16, v[0:1]
	v_add_nc_u32_e32 v0, s4, v13
	v_min_i32_e32 v15, s30, v15
	v_xor_b32_e32 v6, v4, v12
	v_add_nc_u32_e32 v16, -1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, v13, v15
	v_mad_u64_u32 v[3:4], null, s5, v0, v[5:6]
	v_sub_nc_u32_e32 v0, v6, v12
	v_mov_b32_e32 v12, 0
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_8 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
	s_and_saveexec_b32 s47, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.7:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s46, s13, v[2:3]
	s_mov_b32 s48, 0
	v_mad_u64_u32 v[5:6], null, v4, s18, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s1, s22, v4
	v_add_co_ci_u32_e64 v18, s1, s23, v5, s1
	v_add_co_u32 v4, s1, s24, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s1, s25, v5, s1
	global_load_b32 v6, v[17:18], off
	global_load_b32 v5, v[4:5], off
	v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v17, v13
	s_waitcnt vmcnt(0)
	v_cmp_ge_f32_e64 s1, v6, v5
.LBB0_8:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_10 Depth 4
	s_and_saveexec_b32 s49, s0
	s_cbranch_execz .LBB0_12
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_8 Depth=3
	v_ashrrev_i32_e32 v5, 31, v4
	v_mov_b32_e32 v18, v16
	s_mov_b32 s50, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_co_u32 v5, s2, s26, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, s27, v6, s2
.LBB0_10:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_8 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v19, v[5:6], off
	v_add_nc_u32_e32 v18, 1, v18
	v_add_co_u32 v5, s2, v5, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s2, 0, v6, s2
	v_cmp_ge_i32_e64 s3, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 s50, s3, s50
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v19, -v19, v19, s1
	v_add_f32_e32 v12, v12, v19
	s_and_not1_b32 exec_lo, exec_lo, s50
	s_cbranch_execnz .LBB0_10
; %bb.11:                               ; %Flow
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s50
.LBB0_12:                               ; %Flow203
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s49
	v_add_nc_u32_e32 v5, 1, v17
	v_cmp_ge_i32_e64 s2, v17, v15
	v_dual_mov_b32 v17, v5 :: v_dual_add_nc_u32 v4, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s48, s2, s48
	s_and_not1_b32 exec_lo, exec_lo, s48
	s_cbranch_execnz .LBB0_8
; %bb.13:                               ; %Flow204
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s48
.LBB0_14:                               ; %Flow205
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s47
	v_add_nc_u32_e32 v3, s43, v3
	s_add_i32 s46, s46, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s46, s31
	s_cbranch_scc0 .LBB0_6
	s_branch .LBB0_16
.LBB0_15:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v12, 0
.LBB0_16:                               ; %Flow208
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s45
.LBB0_17:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s44
	v_div_scale_f32 v0, null, v7, v7, v12
	v_div_scale_f32 v3, vcc_lo, v12, v7, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v0, v4, 1.0
	v_fmac_f32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v3, v4
	v_fma_f32 v2, -v0, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v5, v2, v4 :: v_dual_add_nc_u32 v2, s19, v1
	v_add_nc_u32_e32 v1, s7, v1
	v_fma_f32 v0, -v0, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_div_fmas_f32 v0, v0, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_cmp_le_i32_e32 vcc_lo, s28, v1
	v_div_fixup_f32 v0, v0, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s20, v2
	v_add_co_ci_u32_e64 v3, s0, s21, v3, s0
	s_or_b32 s42, vcc_lo, s42
	global_store_b32 v[2:3], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s42
	s_cbranch_execnz .LBB0_2
.LBB0_18:                               ; %Flow210
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 51
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_, .Lfunc_end0-_Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1940
; NumSgprs: 53
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 53
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         116
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         124
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         126
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         128
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         130
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         132
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         134
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         176
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 368
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     53
    .sgpr_spill_count: 0
    .symbol:         _Z33CorrelateDataBackward0Subtract_1diiiiiiiiiiiiiiiiiiiPfPKfS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
