#include "cuda_runtime.h"               // A small gpu volumetric path tracer in 200 lines
#include "device_launch_parameters.h"   // Jerry Guo (c) CGV TU Delft
#include "math_constants.h"             // Based on smallvpt and cu-smallpt
#include "curand_kernel.h"              // Compile: nvcc
#include <stdlib.h>                     // Usage: cusmallvpt [#SPP]
#include <stdio.h>                      // Result: image.ppm

enum Refl_t { DIFF, SPEC, REFR }; 
inline void HandleError(cudaError_t err) {
    if (cudaSuccess != err) { printf("%s\n", cudaGetErrorString(err)); exit(EXIT_FAILURE); }
}
struct Vec { // position, also color (r,g,b) 
    float x, y, z; 
    __host__ __device__ explicit Vec() { x = 0.f; y = 0.f; z = 0.f; }
    __host__ __device__ explicit Vec(float v) { x = v; y = v; z = v; }
    __host__ __device__ explicit Vec(float x_ = 0.f, float y_ = 0.f, float z_ = 0.f) { x = x_; y = y_; z = z_; }
    Vec(const Vec& vec) noexcept = default;
    Vec(Vec&& vec) noexcept = default;
    ~Vec() = default;
    __device__ Vec& operator=(const Vec& b) { this->x = b.x; this->y = b.y; this->z = b.z; return *this; }
    __device__ const Vec operator+(const Vec& b) const { return Vec(x + b.x, y + b.y, z + b.z); }
    __device__ const Vec operator-(const Vec& b) const { return Vec(x - b.x, y - b.y, z - b.z); }
    __host__ __device__ const Vec operator*(float b) const { return Vec(x * b, y * b, z * b); }
    __device__ const Vec mult(const Vec& b) const { return Vec(x * b.x, y * b.y, z * b.z); }
    __device__ float len() const { return sqrt(x * x + y * y + z * z); }
    __device__ Vec& norm() { float inv_len = 1.f / len(); this->x *= inv_len; this->y *= inv_len; this->z *= inv_len; return *this; }
    __device__ float dot(const Vec& b) const { return x * b.x + y * b.y + z * b.z; } // cross: 
    __device__ Vec operator%(Vec& b) { return Vec(y * b.z - z * b.y, z * b.x - x * b.z, x * b.y - y * b.x); }
    __device__ Vec operator%(const Vec& b) { return Vec(y * b.z - z * b.y, z * b.x - x * b.z, x * b.y - y * b.x); }
};
__device__ inline float len(const Vec& v) { return sqrt(v.x*v.x + v.y*v.y + v.z*v.z); }
__device__ inline Vec norm(const Vec& v) { float inv_len = 1.f / len(v); return Vec(v.x * inv_len, v.y * inv_len, v.z * inv_len); }
struct Ray {
    Vec o, d;
    __host__ __device__ explicit Ray() : o(Vec(0.f, 0.f, 0.f)), d(Vec(0.f, 0.f, 0.f)) {}
    __host__ __device__ explicit Ray(Vec o_, Vec d_) noexcept : o(o_), d(d_) {}
    Ray(const Ray& ray) noexcept = default;
    Ray(Ray&& ray) noexcept = default;
    ~Ray() = default;
    __device__ Ray& operator=(const Ray& r) { this->o = r.o; this->d = r.d; return *this; }
};
struct Sphere {
    float rad;       
    Vec p, e, c;     
    Refl_t refl;     
    __host__ __device__ explicit Sphere(float rad_, Vec p_, Vec e_, Vec c_, Refl_t refl_) :
        rad(rad_), p(p_), e(e_), c(c_), refl(refl_) {}
    __device__ float intersect(const Ray& r, float* tin = NULL, float* tout = NULL) const { 
        Vec op = p - r.o; 
        float t, eps = 1e-4, b = op.dot(r.d), det = b * b - op.dot(op) + rad * rad;
        if (det < 0.f) return 0; else det = sqrt(det);
        if (tin && tout) { *tin = (b - det <= 0.f) ? 0.f : b - det; *tout = b + det; }
        return (t = b - det) > eps ? t : ((t = b + det) > eps ? t : 0.f);
    }
};
__host__ __device__ inline float clamp(float x) { return x < 0.f ? 0.f : x>1.f ? 1.f : x; }
__host__ __device__ inline int toInt(float x) { return int(pow(clamp(x), 1.f / 2.2f) * 255.f + .5f); }
__device__ inline bool intersect(const Sphere* spheres, size_t n_sphere, const Ray& r, float& t, int& id, float tmax = 1e20) {
    float d, inf = t = tmax;
    for (int i = int(n_sphere); i--;) if ((d = spheres[i].intersect(r)) && d < t) { t = d; id = i; }
    return t < inf;
}
__device__ inline float sampleSegment(float epsilon, float sigma, float smax) {
    return -log(1.f - epsilon * (1.f - exp(-sigma * smax))) / sigma;
}
__device__ inline Vec sampleSphere(float e1, float e2) {
    float z = 1.f - 2.f * e1, sint = sqrt(1.f - z * z);
    return Vec(cos(2.f * CUDART_PI_F * e2) * sint, sin(2.f * CUDART_PI_F * e2) * sint, z);
}
__device__ inline Vec sampleHG(float g, float e1, float e2) {
    float s = 1.f-2.f*e1,cost=(s+2.f*g*g*g*(-1.0+e1)*e1+g*g*s+2.f*g*(1.f-e1+e1*e1))/((1.f+g*s)*(1.f+g*s)),sint=sqrt(1.f-cost*cost);
    return Vec(cos(2.f * CUDART_PI_F * e2) * sint, sin(2.f * CUDART_PI_F * e2) * sint, cost);
}
__device__ inline void generateOrthoBasis(Vec& u, Vec& v, Vec w) {
    Vec coVec = w;
    if (fabs(w.x) <= fabs(w.y))
        if (fabs(w.x) <= fabs(w.z)) coVec = Vec(0.f, -w.z, w.y); else coVec = Vec(-w.y, w.x, 0.f);
    else if (fabs(w.y) <= fabs(w.z)) coVec = Vec(-w.z, 0.f, w.x); else coVec = Vec(-w.y, w.x, 0.f);
    coVec.norm(); u = w % coVec, v = w % u;
}
__device__ inline float scatter(const Ray& r, Ray* sRay, float tin, float tout, float& s, const float& sigma_s, curandState_t* rand_state) {
    s = sampleSegment(curand_uniform(rand_state), sigma_s, tout - tin);
    Vec x = r.o + r.d * tin + r.d * s;
    Vec dir = sampleHG(-0.5f, curand_uniform(rand_state), curand_uniform(rand_state)); 
    Vec u(0.f, 0.f, 0.f), v(0.f, 0.f, 0.f);
    generateOrthoBasis(u, v, r.d);
    dir = u * dir.x + v * dir.y + r.d * dir.z;
    if (sRay)	*sRay = Ray(x, dir);
    return (1.0f - exp(-sigma_s * (tout - tin)));
}
__device__ Vec radiance(const Sphere* spheres, size_t n_sphere, const Ray& r, int _depth, curandState_t* rand_state) {
    Ray ray = r;
    Vec L(0.f, 0.f, 0.f);
    Vec B(1.f, 1.f, 1.f);
    int depth = _depth;
    float tnear, tfar, scaleBy = 1.f, absorption = 1.f;
    const Sphere homoMedium(300.f, Vec(50.f, 50.f, 80.f), Vec(0.f, 0.f, 0.f), Vec(0.f, 0.f, 0.f), DIFF);
    const float sigma_s = 0.009f, sigma_a = 0.006f, sigma_t = sigma_s + sigma_a;
    while (1) {
        float t;                               // distance to intersection
        int id = 0;                               // id of intersected object
        if (homoMedium.intersect(ray, &tnear, &tfar) > 0) {
            Ray sRay;
            float s, ms = scatter(ray, &sRay, tnear, tfar, s, sigma_s, rand_state), prob_s = ms;
            scaleBy = 1.f / (1.f - prob_s);
            if (curand_uniform(rand_state) <= prob_s) {// Sample surface or volume?
                if (!intersect(spheres, n_sphere, ray, t, id, tnear + s)) {
                    B = B * ms * (1.f - prob_s); ray = sRay; ++depth; continue;
                }
                scaleBy = 1.f;
            } else if (!intersect(spheres, n_sphere, ray, t, id)) return L;
            if (t >= tnear) {
                float dist = (t > tfar ? tfar - tnear : t - tnear);
                absorption = exp(-sigma_t * dist);
            }
        } else if (!intersect(spheres, n_sphere, ray, t, id)) return L;
        const Sphere& obj = spheres[id]; 
        Vec x = r.o + r.d * t, n = Vec(x - obj.p).norm(), nl = n.dot(ray.d) < 0 ? n : n * -1, f = obj.c, Le = obj.e;
        float p = f.x > f.y && f.x > f.z ? f.x : f.y > f.z ? f.y : f.z; 
        if (++depth > 5) if (curand_uniform(rand_state) < p) B = B * (1 / p); else  return L;
        if (n.dot(nl) > 0 || obj.refl != REFR) { B = B * absorption; Le = obj.e * absorption; } else scaleBy = 1.f;
        // Accumulate luminance and throughtput
        L = L + B.mult(Le); B = B.mult(f * scaleBy); ++depth;
        switch (obj.refl) {
            case SPEC: { ray = Ray(x, r.d - n * 2 * n.dot(r.d)); break; }
            case REFR: { 
                ray = Ray(x, r.d - n * 2 * n.dot(r.d)); bool into = n.dot(nl) > 0; 
                float nc = 1, nt = 1.5, nnt = into ? nc / nt : nt / nc, ddn = r.d.dot(nl), cos2t;
                if ((cos2t = 1 - nnt * nnt * (1 - ddn * ddn)) < 0) break;
                Vec tdir = Vec(r.d*nnt-n*((into?1:-1)*(ddn*nnt+sqrt(cos2t)))).norm();
                float a=nt-nc,b=nt+nc,R0=a*a/(b*b),c = 1 - (into ? -ddn : tdir.dot(n));
                float Re=R0+(1-R0)*c*c*c*c*c, Tr=1-Re,P=.25+.5*Re,RP=Re/P,TP = Tr / (1 - P);
                if (curand_uniform(rand_state) < P) B=B*RP; else { ray=Ray(x,tdir); B=B*TP; }
                break;
            }
            default: { 
                float r1=2*CUDART_PI_F*curand_uniform(rand_state),r2=curand_uniform(rand_state),r2s = sqrt(r2);
                Vec w = nl, u = Vec((fabs(w.x) > .1 ? Vec(0, 1) : Vec(1.f, 1.f, 1.f)) % w).norm(), v = w % u;
                Vec d = Vec(u * cos(r1) * r2s + v * sin(r1) * r2s + w * sqrt(1 - r2)).norm();
                ray = Ray(x, d);
            }
        }
    }
}
__global__ void render_kernel(const Sphere* spheres, const size_t n_sphere, Vec* Ls, size_t w, size_t h, int spp) {
    const size_t x = threadIdx.x + blockIdx.x * blockDim.x;
    const size_t y = threadIdx.y + blockIdx.y * blockDim.y;
    const size_t offset = x + y * blockDim.x * gridDim.x;
    const float inv_spp = 1.0f / float(spp);
    if (x >= w || y >= h) return;
    curandState rand_state; curand_init(offset, 0u, 0u, &rand_state);
    Ray cam(Vec(50.f, 52.f, 285.f), norm(Vec(0.f, -0.042612f, -1.f)));
    const float fov = 0.5135f; Vec cx = Vec(w * fov / h, 0.0f, 0.0f);
    Vec cy = norm(Vec(cx % cam.d)) * fov; size_t i = (h - 1u - y) * w + x;
    for (size_t sy = 0u; sy < 2u; ++sy) for (size_t sx = 0u; sx < 2u; ++sx) {
        Vec L(0.f, 0.f, 0.f);
        for (size_t s = 0u; s < spp; ++s) {
            float u1 = 2.f * curand_uniform(&rand_state);
            float u2 = 2.f * curand_uniform(&rand_state);
            float dx = (u1 < 1.f) ? sqrt(u1) - 1.f : 1.f - sqrt(2.f - u1);
            float dy = (u2 < 1.f) ? sqrt(u2) - 1.f : 1.f - sqrt(2.f - u2);
            Vec d = cx * (((sx+0.5+dx)*0.5+x)/w-0.5)+cy*(((sy+0.5+dy)*0.5+y)/h-0.5)+cam.d;
            Ray pRay(cam.o + d * 140.f, d.norm());
            L = L + radiance(spheres, n_sphere, pRay, 0, &rand_state) * inv_spp;
        }
        Ls[i] = Ls[i] + Vec(0.25f * clamp(L.x), 0.25f * clamp(L.y), 0.25f * clamp(L.z));
    }
}
cudaError_t Render(int w, int h, unsigned int spp = 100) {
    const size_t n_sphere = 4;
    Sphere spheres[n_sphere] = {//Scene: radius, position, emission, color, material 
        Sphere(26.5f, Vec(27.f, 18.5f, 78.f),Vec(0.f, 0.f, 0.f),Vec(1.f,1.f,1.f)*.75f,SPEC),//Mirr
        Sphere(12.f, Vec(70.f, 43.f, 78.f), Vec(0.f, 0.f, 0.f), Vec(0.27f,0.8f,0.8f), REFR),//Glas
        Sphere(8.f, Vec(55.f, 87.f, 78.f), Vec(0.f, 0.f, 0.f),  Vec(1,1,1) * .75f, DIFF), //Lite
        Sphere(4.f, Vec(55.f, 80.f, 78.f), Vec(10.f,10.f,10.f),  Vec(0.f, 0.f, 0.f), DIFF) //Lite
    };
    HandleError(cudaSetDevice(0));
    const size_t n_pixels = size_t(w * h);
    Sphere* spheres_device;
    HandleError(cudaMalloc((void**)&spheres_device, sizeof(spheres)));
    HandleError(cudaMemcpy(spheres_device, spheres, sizeof(spheres), cudaMemcpyHostToDevice));
    Vec* film_device;
    HandleError(cudaMalloc((void**)&film_device, sizeof(Vec) * n_pixels));
    HandleError(cudaMemset(film_device, 0, sizeof(Vec) * n_pixels));
    const dim3 nblocks(w / 16, h / 16);
    const dim3 nthreads(16, 16);
    render_kernel <<< nblocks, nthreads >>> (spheres_device, n_sphere, film_device, w, h, spp);
    Vec* film = (Vec*)malloc(n_pixels * sizeof(Vec));
    HandleError(cudaMemcpy(film, film_device, sizeof(Vec) * n_pixels, cudaMemcpyDeviceToHost));
    HandleError(cudaFree(spheres_device));
    HandleError(cudaFree(film_device));
    FILE* f = fopen("image.ppm", "w"); // Write image to PPM file.
    fprintf(f, "P3\n%d %d\n%d\n", w, h, 255);
    for (int i=0;i<w*h;i++) fprintf(f,"%d %d %d ",toInt(film[i].x),toInt(film[i].y),toInt(film[i].z));
    free(film); return cudaSuccess;
}
int main(int argc, char* argv[]) {
    int w = 1024, h = 768, spp = argc == 2 ? atoi(argv[1]) / 4 : 100; 
    Render(w, h, spp); return 0;
}

	.file	"tmpxft_002af328_00000000-6_smallvpt.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2287:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2287:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z11HandleError9cudaError.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%s\n"
	.section	.text._Z11HandleError9cudaError,"axG",@progbits,_Z11HandleError9cudaError,comdat
	.weak	_Z11HandleError9cudaError
	.type	_Z11HandleError9cudaError, @function
_Z11HandleError9cudaError:
.LFB2241:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2241:
	.size	_Z11HandleError9cudaError, .-_Z11HandleError9cudaError
	.section	.text._Z5toIntf,"axG",@progbits,_Z5toIntf,comdat
	.weak	_Z5toIntf
	.type	_Z5toIntf, @function
_Z5toIntf:
.LFB2275:
	.cfi_startproc
	endbr64
	xorps	%xmm1, %xmm1
	pushq	%rcx
	.cfi_def_cfa_offset 16
	comiss	%xmm0, %xmm1
	ja	.L11
	movss	.LC2(%rip), %xmm1
	minss	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	jmp	.L9
.L11:
	xorps	%xmm0, %xmm0
.L9:
	movss	.LC3(%rip), %xmm1
	call	powf@PLT
	mulss	.LC4(%rip), %xmm0
	addss	.LC5(%rip), %xmm0
	popq	%rdx
	.cfi_def_cfa_offset 8
	cvttss2sil	%xmm0, %eax
	ret
	.cfi_endproc
.LFE2275:
	.size	_Z5toIntf, .-_Z5toIntf
	.text
	.globl	_Z8radiancePK6SpheremRK3RayiP17curandStateXORWOW
	.type	_Z8radiancePK6SpheremRK3RayiP17curandStateXORWOW, @function
_Z8radiancePK6SpheremRK3RayiP17curandStateXORWOW:
.LFB2282:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2282:
	.size	_Z8radiancePK6SpheremRK3RayiP17curandStateXORWOW, .-_Z8radiancePK6SpheremRK3RayiP17curandStateXORWOW
	.globl	_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi
	.type	_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi, @function
_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi:
.LFB2309:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13render_kernelPK6SpheremP3Vecmmi(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L16:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2309:
	.size	_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi, .-_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi
	.globl	_Z13render_kernelPK6SpheremP3Vecmmi
	.type	_Z13render_kernelPK6SpheremP3Vecmmi, @function
_Z13render_kernelPK6SpheremP3Vecmmi:
.LFB2310:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi
	.cfi_endproc
.LFE2310:
	.size	_Z13render_kernelPK6SpheremP3Vecmmi, .-_Z13render_kernelPK6SpheremP3Vecmmi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC6:
	.string	"w"
.LC7:
	.string	"image.ppm"
.LC8:
	.string	"P3\n%d %d\n%d\n"
.LC9:
	.string	"%d %d %d "
	.text
	.globl	_Z6Renderiij
	.type	_Z6Renderiij, @function
_Z6Renderiij:
.LFB2283:
	.cfi_startproc
	endbr64
	movabsq	$4701758010974797825, %rcx
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	movl	$253, %edx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	salq	$54, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	movabsq	$4561245704509078897, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	xorl	%edi, %edi
	movl	%ebx, %r14d
	imull	%ebp, %r14d
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	movabsq	$4744542208539230208, %rax
	movq	%rcx, 96(%rsp)
	movabsq	$4768186106594983936, %rcx
	movq	%rcx, 104(%rsp)
	xorl	%ecx, %ecx
	movslq	%r14d, %r12
	movq	%rcx, 120(%rsp)
	imulq	$12, %r12, %r12
	movabsq	$9651932365, %rcx
	movq	%rsi, 128(%rsp)
	movabsq	$4781696905451143168, %rsi
	movq	%rcx, 136(%rsp)
	movabsq	$4799711303988805632, %rcx
	movq	%rsi, 144(%rsp)
	xorl	%esi, %esi
	movq	%rax, 56(%rsp)
	movabsq	$4799711303970324480, %rax
	movq	%rax, 64(%rsp)
	xorl	%eax, %eax
	movq	%rax, 72(%rsp)
	movabsq	$4557642823960100864, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 176(%rsp)
	movl	$129, %eax
	salq	$55, %rax
	movq	%rdx, 80(%rsp)
	movq	%rcx, 152(%rsp)
	movq	%rdx, 168(%rsp)
	movq	%rsi, 160(%rsp)
	movq	$1117519872, 112(%rsp)
	movq	%rax, 184(%rsp)
	movabsq	$4800837203890274304, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4692750812837576704, %rax
	movq	%rax, 200(%rsp)
	subq	$24903680, %rax
	movq	%rdi, 216(%rsp)
	movq	%rdi, 224(%rsp)
	xorl	%edi, %edi
	movq	%rax, 208(%rsp)
	call	cudaSetDevice@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movl	$176, %esi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$176, %edx
	leaq	56(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movq	%r12, %rsi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	call	cudaMemset@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movl	%ebx, %eax
	movl	$16, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movl	$1, %esi
	idivl	%ecx
	movl	%eax, 32(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	%eax, 36(%rsp)
	movq	32(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	movslq	%ebx, %rcx
	movl	%r13d, %r9d
	movslq	%ebp, %r8
	movl	$4, %esi
	call	_Z49__device_stub__Z13render_kernelPK6SpheremP3VecmmiPK6SpheremP3Vecmmi
.L22:
	movq	%r12, %rdi
	xorl	%r15d, %r15d
	call	malloc@PLT
	movq	24(%rsp), %rsi
	movq	%r12, %rdx
	movl	$2, %ecx
	movq	%rax, %rdi
	movq	%rax, %r13
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z11HandleError9cudaError
	leaq	.LC6(%rip), %rsi
	leaq	.LC7(%rip), %rdi
	call	fopen@PLT
	movl	%ebp, %r8d
	movl	%ebx, %ecx
	movl	$255, %r9d
	movq	%rax, %rdi
	movq	%rax, %r12
	leaq	.LC8(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	movq	%r13, %rbx
	leaq	.LC9(%rip), %rbp
	call	__fprintf_chk@PLT
.L23:
	cmpl	%r15d, %r14d
	jle	.L27
	movss	8(%rbx), %xmm0
	incl	%r15d
	addq	$12, %rbx
	call	_Z5toIntf
	movss	-8(%rbx), %xmm0
	movl	%eax, 12(%rsp)
	call	_Z5toIntf
	movss	-12(%rbx), %xmm0
	movl	%eax, 8(%rsp)
	call	_Z5toIntf
	movl	12(%rsp), %r9d
	movq	%rbp, %rdx
	movq	%r12, %rdi
	movl	8(%rsp), %r8d
	movl	%eax, %ecx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L23
.L27:
	movq	%r13, %rdi
	call	free@PLT
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2283:
	.size	_Z6Renderiij, .-_Z6Renderiij
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2284:
	.cfi_startproc
	endbr64
	movl	$100, %eax
	pushq	%rcx
	.cfi_def_cfa_offset 16
	cmpl	$2, %edi
	jne	.L29
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	$4, %ecx
	cltd
	idivl	%ecx
.L29:
	movl	%eax, %edx
	movl	$768, %esi
	movl	$1024, %edi
	call	_Z6Renderiij
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2284:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z13render_kernelPK6SpheremP3Vecmmi"
.LC11:
	.string	"precalc_xorwow_matrix"
.LC12:
	.string	"precalc_xorwow_offset_matrix"
.LC13:
	.string	"mrg32k3aM1"
.LC14:
	.string	"mrg32k3aM2"
.LC15:
	.string	"mrg32k3aM1SubSeq"
.LC16:
	.string	"mrg32k3aM2SubSeq"
.LC17:
	.string	"mrg32k3aM1Seq"
.LC18:
	.string	"mrg32k3aM2Seq"
.LC19:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2312:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13render_kernelPK6SpheremP3Vecmmi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2312:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	1065353216
	.align 4
.LC3:
	.long	1055439406
	.align 4
.LC4:
	.long	1132396544
	.align 4
.LC5:
	.long	1056964608
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"               // A small gpu volumetric path tracer in 200 lines
   // Jerry Guo (c) CGV TU Delft
#include "hip/hip_math_constants.h"             // Based on smallvpt and cu-smallpt
#include "hiprand/hiprand_kernel.h"              // Compile: nvcc
#include <stdlib.h>                     // Usage: cusmallvpt [#SPP]
#include <stdio.h>                      // Result: image.ppm

enum Refl_t { DIFF, SPEC, REFR }; 
inline void HandleError(hipError_t err) {
    if (hipSuccess != err) { printf("%s\n", hipGetErrorString(err)); exit(EXIT_FAILURE); }
}
struct Vec { // position, also color (r,g,b) 
    float x, y, z; 
    __host__ __device__ explicit Vec() { x = 0.f; y = 0.f; z = 0.f; }
    __host__ __device__ explicit Vec(float v) { x = v; y = v; z = v; }
    __host__ __device__ explicit Vec(float x_ = 0.f, float y_ = 0.f, float z_ = 0.f) { x = x_; y = y_; z = z_; }
    Vec(const Vec& vec) noexcept = default;
    Vec(Vec&& vec) noexcept = default;
    ~Vec() = default;
    __device__ Vec& operator=(const Vec& b) { this->x = b.x; this->y = b.y; this->z = b.z; return *this; }
    __device__ const Vec operator+(const Vec& b) const { return Vec(x + b.x, y + b.y, z + b.z); }
    __device__ const Vec operator-(const Vec& b) const { return Vec(x - b.x, y - b.y, z - b.z); }
    __host__ __device__ const Vec operator*(float b) const { return Vec(x * b, y * b, z * b); }
    __device__ const Vec mult(const Vec& b) const { return Vec(x * b.x, y * b.y, z * b.z); }
    __device__ float len() const { return sqrt(x * x + y * y + z * z); }
    __device__ Vec& norm() { float inv_len = 1.f / len(); this->x *= inv_len; this->y *= inv_len; this->z *= inv_len; return *this; }
    __device__ float dot(const Vec& b) const { return x * b.x + y * b.y + z * b.z; } // cross: 
    __device__ Vec operator%(Vec& b) { return Vec(y * b.z - z * b.y, z * b.x - x * b.z, x * b.y - y * b.x); }
    __device__ Vec operator%(const Vec& b) { return Vec(y * b.z - z * b.y, z * b.x - x * b.z, x * b.y - y * b.x); }
};
__device__ inline float len(const Vec& v) { return sqrt(v.x*v.x + v.y*v.y + v.z*v.z); }
__device__ inline Vec norm(const Vec& v) { float inv_len = 1.f / len(v); return Vec(v.x * inv_len, v.y * inv_len, v.z * inv_len); }
struct Ray {
    Vec o, d;
    __host__ __device__ explicit Ray() : o(Vec(0.f, 0.f, 0.f)), d(Vec(0.f, 0.f, 0.f)) {}
    __host__ __device__ explicit Ray(Vec o_, Vec d_) noexcept : o(o_), d(d_) {}
    Ray(const Ray& ray) noexcept = default;
    Ray(Ray&& ray) noexcept = default;
    ~Ray() = default;
    __device__ Ray& operator=(const Ray& r) { this->o = r.o; this->d = r.d; return *this; }
};
struct Sphere {
    float rad;       
    Vec p, e, c;     
    Refl_t refl;     
    __host__ __device__ explicit Sphere(float rad_, Vec p_, Vec e_, Vec c_, Refl_t refl_) :
        rad(rad_), p(p_), e(e_), c(c_), refl(refl_) {}
    __device__ float intersect(const Ray& r, float* tin = NULL, float* tout = NULL) const { 
        Vec op = p - r.o; 
        float t, eps = 1e-4, b = op.dot(r.d), det = b * b - op.dot(op) + rad * rad;
        if (det < 0.f) return 0; else det = sqrt(det);
        if (tin && tout) { *tin = (b - det <= 0.f) ? 0.f : b - det; *tout = b + det; }
        return (t = b - det) > eps ? t : ((t = b + det) > eps ? t : 0.f);
    }
};
__host__ __device__ inline float clamp(float x) { return x < 0.f ? 0.f : x>1.f ? 1.f : x; }
__host__ __device__ inline int toInt(float x) { return int(pow(clamp(x), 1.f / 2.2f) * 255.f + .5f); }
__device__ inline bool intersect(const Sphere* spheres, size_t n_sphere, const Ray& r, float& t, int& id, float tmax = 1e20) {
    float d, inf = t = tmax;
    for (int i = int(n_sphere); i--;) if ((d = spheres[i].intersect(r)) && d < t) { t = d; id = i; }
    return t < inf;
}
__device__ inline float sampleSegment(float epsilon, float sigma, float smax) {
    return -log(1.f - epsilon * (1.f - exp(-sigma * smax))) / sigma;
}
__device__ inline Vec sampleSphere(float e1, float e2) {
    float z = 1.f - 2.f * e1, sint = sqrt(1.f - z * z);
    return Vec(cos(2.f * HIP_PI_F * e2) * sint, sin(2.f * HIP_PI_F * e2) * sint, z);
}
__device__ inline Vec sampleHG(float g, float e1, float e2) {
    float s = 1.f-2.f*e1,cost=(s+2.f*g*g*g*(-1.0+e1)*e1+g*g*s+2.f*g*(1.f-e1+e1*e1))/((1.f+g*s)*(1.f+g*s)),sint=sqrt(1.f-cost*cost);
    return Vec(cos(2.f * HIP_PI_F * e2) * sint, sin(2.f * HIP_PI_F * e2) * sint, cost);
}
__device__ inline void generateOrthoBasis(Vec& u, Vec& v, Vec w) {
    Vec coVec = w;
    if (fabs(w.x) <= fabs(w.y))
        if (fabs(w.x) <= fabs(w.z)) coVec = Vec(0.f, -w.z, w.y); else coVec = Vec(-w.y, w.x, 0.f);
    else if (fabs(w.y) <= fabs(w.z)) coVec = Vec(-w.z, 0.f, w.x); else coVec = Vec(-w.y, w.x, 0.f);
    coVec.norm(); u = w % coVec, v = w % u;
}
__device__ inline float scatter(const Ray& r, Ray* sRay, float tin, float tout, float& s, const float& sigma_s, hiprandState_t* rand_state) {
    s = sampleSegment(hiprand_uniform(rand_state), sigma_s, tout - tin);
    Vec x = r.o + r.d * tin + r.d * s;
    Vec dir = sampleHG(-0.5f, hiprand_uniform(rand_state), hiprand_uniform(rand_state)); 
    Vec u(0.f, 0.f, 0.f), v(0.f, 0.f, 0.f);
    generateOrthoBasis(u, v, r.d);
    dir = u * dir.x + v * dir.y + r.d * dir.z;
    if (sRay)	*sRay = Ray(x, dir);
    return (1.0f - exp(-sigma_s * (tout - tin)));
}
__device__ Vec radiance(const Sphere* spheres, size_t n_sphere, const Ray& r, int _depth, hiprandState_t* rand_state) {
    Ray ray = r;
    Vec L(0.f, 0.f, 0.f);
    Vec B(1.f, 1.f, 1.f);
    int depth = _depth;
    float tnear, tfar, scaleBy = 1.f, absorption = 1.f;
    const Sphere homoMedium(300.f, Vec(50.f, 50.f, 80.f), Vec(0.f, 0.f, 0.f), Vec(0.f, 0.f, 0.f), DIFF);
    const float sigma_s = 0.009f, sigma_a = 0.006f, sigma_t = sigma_s + sigma_a;
    while (1) {
        float t;                               // distance to intersection
        int id = 0;                               // id of intersected object
        if (homoMedium.intersect(ray, &tnear, &tfar) > 0) {
            Ray sRay;
            float s, ms = scatter(ray, &sRay, tnear, tfar, s, sigma_s, rand_state), prob_s = ms;
            scaleBy = 1.f / (1.f - prob_s);
            if (hiprand_uniform(rand_state) <= prob_s) {// Sample surface or volume?
                if (!intersect(spheres, n_sphere, ray, t, id, tnear + s)) {
                    B = B * ms * (1.f - prob_s); ray = sRay; ++depth; continue;
                }
                scaleBy = 1.f;
            } else if (!intersect(spheres, n_sphere, ray, t, id)) return L;
            if (t >= tnear) {
                float dist = (t > tfar ? tfar - tnear : t - tnear);
                absorption = exp(-sigma_t * dist);
            }
        } else if (!intersect(spheres, n_sphere, ray, t, id)) return L;
        const Sphere& obj = spheres[id]; 
        Vec x = r.o + r.d * t, n = Vec(x - obj.p).norm(), nl = n.dot(ray.d) < 0 ? n : n * -1, f = obj.c, Le = obj.e;
        float p = f.x > f.y && f.x > f.z ? f.x : f.y > f.z ? f.y : f.z; 
        if (++depth > 5) if (hiprand_uniform(rand_state) < p) B = B * (1 / p); else  return L;
        if (n.dot(nl) > 0 || obj.refl != REFR) { B = B * absorption; Le = obj.e * absorption; } else scaleBy = 1.f;
        // Accumulate luminance and throughtput
        L = L + B.mult(Le); B = B.mult(f * scaleBy); ++depth;
        switch (obj.refl) {
            case SPEC: { ray = Ray(x, r.d - n * 2 * n.dot(r.d)); break; }
            case REFR: { 
                ray = Ray(x, r.d - n * 2 * n.dot(r.d)); bool into = n.dot(nl) > 0; 
                float nc = 1, nt = 1.5, nnt = into ? nc / nt : nt / nc, ddn = r.d.dot(nl), cos2t;
                if ((cos2t = 1 - nnt * nnt * (1 - ddn * ddn)) < 0) break;
                Vec tdir = Vec(r.d*nnt-n*((into?1:-1)*(ddn*nnt+sqrt(cos2t)))).norm();
                float a=nt-nc,b=nt+nc,R0=a*a/(b*b),c = 1 - (into ? -ddn : tdir.dot(n));
                float Re=R0+(1-R0)*c*c*c*c*c, Tr=1-Re,P=.25+.5*Re,RP=Re/P,TP = Tr / (1 - P);
                if (hiprand_uniform(rand_state) < P) B=B*RP; else { ray=Ray(x,tdir); B=B*TP; }
                break;
            }
            default: { 
                float r1=2*HIP_PI_F*hiprand_uniform(rand_state),r2=hiprand_uniform(rand_state),r2s = sqrt(r2);
                Vec w = nl, u = Vec((fabs(w.x) > .1 ? Vec(0, 1) : Vec(1.f, 1.f, 1.f)) % w).norm(), v = w % u;
                Vec d = Vec(u * cos(r1) * r2s + v * sin(r1) * r2s + w * sqrt(1 - r2)).norm();
                ray = Ray(x, d);
            }
        }
    }
}
__global__ void render_kernel(const Sphere* spheres, const size_t n_sphere, Vec* Ls, size_t w, size_t h, int spp) {
    const size_t x = threadIdx.x + blockIdx.x * blockDim.x;
    const size_t y = threadIdx.y + blockIdx.y * blockDim.y;
    const size_t offset = x + y * blockDim.x * gridDim.x;
    const float inv_spp = 1.0f / float(spp);
    if (x >= w || y >= h) return;
    hiprandState rand_state; hiprand_init(offset, 0u, 0u, &rand_state);
    Ray cam(Vec(50.f, 52.f, 285.f), norm(Vec(0.f, -0.042612f, -1.f)));
    const float fov = 0.5135f; Vec cx = Vec(w * fov / h, 0.0f, 0.0f);
    Vec cy = norm(Vec(cx % cam.d)) * fov; size_t i = (h - 1u - y) * w + x;
    for (size_t sy = 0u; sy < 2u; ++sy) for (size_t sx = 0u; sx < 2u; ++sx) {
        Vec L(0.f, 0.f, 0.f);
        for (size_t s = 0u; s < spp; ++s) {
            float u1 = 2.f * hiprand_uniform(&rand_state);
            float u2 = 2.f * hiprand_uniform(&rand_state);
            float dx = (u1 < 1.f) ? sqrt(u1) - 1.f : 1.f - sqrt(2.f - u1);
            float dy = (u2 < 1.f) ? sqrt(u2) - 1.f : 1.f - sqrt(2.f - u2);
            Vec d = cx * (((sx+0.5+dx)*0.5+x)/w-0.5)+cy*(((sy+0.5+dy)*0.5+y)/h-0.5)+cam.d;
            Ray pRay(cam.o + d * 140.f, d.norm());
            L = L + radiance(spheres, n_sphere, pRay, 0, &rand_state) * inv_spp;
        }
        Ls[i] = Ls[i] + Vec(0.25f * clamp(L.x), 0.25f * clamp(L.y), 0.25f * clamp(L.z));
    }
}
hipError_t Render(int w, int h, unsigned int spp = 100) {
    const size_t n_sphere = 4;
    Sphere spheres[n_sphere] = {//Scene: radius, position, emission, color, material 
        Sphere(26.5f, Vec(27.f, 18.5f, 78.f),Vec(0.f, 0.f, 0.f),Vec(1.f,1.f,1.f)*.75f,SPEC),//Mirr
        Sphere(12.f, Vec(70.f, 43.f, 78.f), Vec(0.f, 0.f, 0.f), Vec(0.27f,0.8f,0.8f), REFR),//Glas
        Sphere(8.f, Vec(55.f, 87.f, 78.f), Vec(0.f, 0.f, 0.f),  Vec(1,1,1) * .75f, DIFF), //Lite
        Sphere(4.f, Vec(55.f, 80.f, 78.f), Vec(10.f,10.f,10.f),  Vec(0.f, 0.f, 0.f), DIFF) //Lite
    };
    HandleError(hipSetDevice(0));
    const size_t n_pixels = size_t(w * h);
    Sphere* spheres_device;
    HandleError(hipMalloc((void**)&spheres_device, sizeof(spheres)));
    HandleError(hipMemcpy(spheres_device, spheres, sizeof(spheres), hipMemcpyHostToDevice));
    Vec* film_device;
    HandleError(hipMalloc((void**)&film_device, sizeof(Vec) * n_pixels));
    HandleError(hipMemset(film_device, 0, sizeof(Vec) * n_pixels));
    const dim3 nblocks(w / 16, h / 16);
    const dim3 nthreads(16, 16);
    render_kernel <<< nblocks, nthreads >>> (spheres_device, n_sphere, film_device, w, h, spp);
    Vec* film = (Vec*)malloc(n_pixels * sizeof(Vec));
    HandleError(hipMemcpy(film, film_device, sizeof(Vec) * n_pixels, hipMemcpyDeviceToHost));
    HandleError(hipFree(spheres_device));
    HandleError(hipFree(film_device));
    FILE* f = fopen("image.ppm", "w"); // Write image to PPM file.
    fprintf(f, "P3\n%d %d\n%d\n", w, h, 255);
    for (int i=0;i<w*h;i++) fprintf(f,"%d %d %d ",toInt(film[i].x),toInt(film[i].y),toInt(film[i].z));
    free(film); return hipSuccess;
}
int main(int argc, char* argv[]) {
    int w = 1024, h = 768, spp = argc == 2 ? atoi(argv[1]) / 4 : 100; 
    Render(w, h, spp); return 0;
}

	.text
	.file	"smallvpt.hip"
	.globl	_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi # -- Begin function _Z28__device_stub__render_kernelPK6SpheremP3Vecmmi
	.type	_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi,@function
_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi: # @_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13render_kernelPK6SpheremP3Vecmmi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi, .Lfunc_end0-_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z6Renderiij
.LCPI1_0:
	.long	0x41d80000                      # float 27
	.long	0x41940000                      # float 18.5
	.zero	4
	.zero	4
.LCPI1_1:
	.long	0x3f400000                      # float 0.75
	.long	0x3f400000                      # float 0.75
	.zero	4
	.zero	4
.LCPI1_2:
	.long	0x428c0000                      # float 70
	.long	0x422c0000                      # float 43
	.zero	4
	.zero	4
.LCPI1_3:
	.long	0x3e8a3d71                      # float 0.270000011
	.long	0x3f4ccccd                      # float 0.800000011
	.zero	4
	.zero	4
.LCPI1_4:
	.long	0x425c0000                      # float 55
	.long	0x42ae0000                      # float 87
	.zero	4
	.zero	4
.LCPI1_5:
	.long	0x425c0000                      # float 55
	.long	0x42a00000                      # float 80
	.zero	4
	.zero	4
.LCPI1_6:
	.long	0x41200000                      # float 10
	.long	0x41200000                      # float 10
	.zero	4
	.zero	4
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI1_7:
	.long	0x3f800000                      # float 1
.LCPI1_8:
	.long	0x3ee8ba2e                      # float 0.454545438
.LCPI1_9:
	.long	0x437f0000                      # float 255
.LCPI1_10:
	.long	0x3f000000                      # float 0.5
.LCPI1_11:
	.long	0x00000000                      # float 0
	.text
	.globl	_Z6Renderiij
	.type	_Z6Renderiij,@function
_Z6Renderiij:                           # @_Z6Renderiij
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%esi, %ebx
	movl	%edi, %r14d
	movl	$1104412672, 16(%rsp)           # imm = 0x41D40000
	movsd	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	%xmm0, 20(%rsp)
	movl	$1117519872, %eax               # imm = 0x429C0000
	movl	%eax, 28(%rsp)
	xorl	%ecx, %ecx
	movq	%rcx, 32(%rsp)
	movl	%ecx, 40(%rsp)
	movsd	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	%xmm0, 44(%rsp)
	movabsq	$5356126208, %rdx               # imm = 0x13F400000
	movq	%rdx, 52(%rsp)
	movl	$1094713344, 60(%rsp)           # imm = 0x41400000
	movsd	.LCPI1_2(%rip), %xmm1           # xmm1 = mem[0],zero
	movsd	%xmm1, 64(%rsp)
	movl	%eax, 72(%rsp)
	movq	%rcx, 76(%rsp)
	movl	%ecx, 84(%rsp)
	movsd	.LCPI1_3(%rip), %xmm1           # xmm1 = mem[0],zero
	movsd	%xmm1, 88(%rsp)
	movabsq	$9651932365, %rdx               # imm = 0x23F4CCCCD
	movq	%rdx, 96(%rsp)
	movl	$1090519040, 104(%rsp)          # imm = 0x41000000
	movsd	.LCPI1_4(%rip), %xmm1           # xmm1 = mem[0],zero
	movsd	%xmm1, 108(%rsp)
	movl	%eax, 116(%rsp)
	movq	%rcx, 120(%rsp)
	movl	%ecx, 128(%rsp)
	movsd	%xmm0, 132(%rsp)
	movq	$1061158912, 140(%rsp)          # imm = 0x3F400000
	movl	$1082130432, 148(%rsp)          # imm = 0x40800000
	movsd	.LCPI1_5(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	%xmm0, 152(%rsp)
	movl	%eax, 160(%rsp)
	movsd	.LCPI1_6(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	%xmm0, 164(%rsp)
	movl	$1092616192, 172(%rsp)          # imm = 0x41200000
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 176(%rsp)
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.1:                                # %_Z11HandleError10hipError_t.exit
	leaq	8(%rsp), %rdi
	movl	$176, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.2:                                # %_Z11HandleError10hipError_t.exit81
	movq	8(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$176, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.3:                                # %_Z11HandleError10hipError_t.exit84
	movl	%ebx, %r13d
	imull	%r14d, %r13d
	movslq	%r13d, %rax
	shlq	$2, %rax
	leaq	(%rax,%rax,2), %r12
	movq	%rsp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.4:                                # %_Z11HandleError10hipError_t.exit87
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.5:                                # %_Z11HandleError10hipError_t.exit90
	leal	15(%r14), %eax
	testl	%r14d, %r14d
	cmovnsl	%r14d, %eax
	sarl	$4, %eax
	leal	15(%rbx), %edi
	testl	%ebx, %ebx
	cmovnsl	%ebx, %edi
	sarl	$4, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.6:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rdx
	movslq	%r14d, %rcx
	movslq	%ebx, %r8
	movl	$4, %esi
	movl	%ebp, %r9d
	callq	_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi
.LBB1_7:
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	(%rsp), %rsi
	movq	%rax, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.8:                                # %_Z11HandleError10hipError_t.exit93
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.9:                                # %_Z11HandleError10hipError_t.exit96
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.10:                               # %_Z11HandleError10hipError_t.exit99
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r12
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	movl	$255, %r8d
	xorl	%eax, %eax
	callq	fprintf
	testl	%r13d, %r13d
	jle	.LBB1_13
# %bb.11:                               # %.lr.ph.preheader
	movl	%r13d, %eax
	shlq	$2, %rax
	leaq	(%rax,%rax,2), %r14
	xorl	%r13d, %r13d
.LBB1_12:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r15,%r13), %xmm0              # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_7(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	minss	%xmm0, %xmm1
	xorps	%xmm2, %xmm2
	cmpltss	%xmm2, %xmm0
	andnps	%xmm1, %xmm0
	movss	.LCPI1_8(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	powf
	movss	.LCPI1_9(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm0
	movss	.LCPI1_10(%rip), %xmm1          # xmm1 = mem[0],zero,zero,zero
	addss	%xmm1, %xmm0
	cvttss2si	%xmm0, %ebx
	movss	4(%r15,%r13), %xmm0             # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_7(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	minss	%xmm0, %xmm1
	cmpltss	.LCPI1_11(%rip), %xmm0
	andnps	%xmm1, %xmm0
	movss	.LCPI1_8(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	powf
	mulss	.LCPI1_9(%rip), %xmm0
	addss	.LCPI1_10(%rip), %xmm0
	cvttss2si	%xmm0, %ebp
	movss	8(%r15,%r13), %xmm0             # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_7(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	minss	%xmm0, %xmm1
	cmpltss	.LCPI1_11(%rip), %xmm0
	andnps	%xmm1, %xmm0
	movss	.LCPI1_8(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	powf
	mulss	.LCPI1_9(%rip), %xmm0
	addss	.LCPI1_10(%rip), %xmm0
	cvttss2si	%xmm0, %r8d
	movl	$.L.str.3, %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	xorl	%eax, %eax
	callq	fprintf
	addq	$12, %r13
	cmpq	%r13, %r14
	jne	.LBB1_12
.LBB1_13:                               # %._crit_edge
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_14:
	.cfi_def_cfa_offset 256
	movl	%eax, %edi
	callq	hipGetErrorString
	movq	%rax, %rdi
	callq	puts@PLT
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z6Renderiij, .Lfunc_end1-_Z6Renderiij
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$100, %edx
	cmpl	$2, %edi
	jne	.LBB2_2
# %bb.1:
	movq	8(%rsi), %rdi
	callq	atoi
                                        # kill: def $eax killed $eax def $rax
	leal	3(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$2, %edx
.LBB2_2:
	movl	$1024, %edi                     # imm = 0x400
	movl	$768, %esi                      # imm = 0x300
	callq	_Z6Renderiij
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13render_kernelPK6SpheremP3Vecmmi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13render_kernelPK6SpheremP3Vecmmi,@object # @_Z13render_kernelPK6SpheremP3Vecmmi
	.section	.rodata,"a",@progbits
	.globl	_Z13render_kernelPK6SpheremP3Vecmmi
	.p2align	3, 0x0
_Z13render_kernelPK6SpheremP3Vecmmi:
	.quad	_Z28__device_stub__render_kernelPK6SpheremP3Vecmmi
	.size	_Z13render_kernelPK6SpheremP3Vecmmi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"image.ppm"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"P3\n%d %d\n%d\n"
	.size	.L.str.2, 13

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d %d %d "
	.size	.L.str.3, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13render_kernelPK6SpheremP3Vecmmi"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__render_kernelPK6SpheremP3Vecmmi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13render_kernelPK6SpheremP3Vecmmi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13render_kernelPK6SpheremP3Vecmmi ; -- Begin function _Z13render_kernelPK6SpheremP3Vecmmi
	.globl	_Z13render_kernelPK6SpheremP3Vecmmi
	.p2align	8
	.type	_Z13render_kernelPK6SpheremP3Vecmmi,@function
_Z13render_kernelPK6SpheremP3Vecmmi:    ; @_Z13render_kernelPK6SpheremP3Vecmmi
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_add_u32 s16, s0, 48
	s_addc_u32 s17, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s7, s2, 16
	v_mad_u64_u32 v[11:12], null, s14, s3, v[1:2]
	v_mov_b32_e32 v12, 0
	v_mad_u64_u32 v[0:1], null, s15, s7, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v1, v12
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s2, s[12:13], v[0:1]
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_109
; %bb.1:
	v_not_b32_e32 v1, v0
	v_not_b32_e32 v2, 0
	s_clz_i32_u32 s2, s11
	v_cvt_f64_u32_e32 v[21:22], s12
	s_min_u32 s2, s2, 32
	v_add_co_u32 v3, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v2, vcc_lo
	s_mov_b32 s21, 0x430c0000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, v3, s10, 0
	v_mul_lo_u32 v5, v4, s10
	v_mul_lo_u32 v6, v3, s11
	s_mov_b32 s22, 0x7fffff
	s_mov_b32 s23, 0x37d75334
	s_mov_b32 s24, 0xb94c1982
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, v1, 12, s[8:9]
	s_lshl_b64 s[8:9], s[10:11], s2
	v_add3_u32 v2, v2, v6, v5
	s_min_u32 s7, s8, 1
	s_clz_i32_u32 s8, s13
	s_or_b32 s7, s9, s7
	s_min_u32 s14, s8, 32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v4
	s_lshl_b64 s[8:9], s[12:13], s14
	s_sub_i32 s2, 32, s2
	v_mad_u64_u32 v[4:5], null, v2, 12, v[1:2]
	v_cvt_f32_u32_e32 v1, s7
	s_min_u32 s7, s8, 1
	s_load_b32 s8, s[0:1], 0x28
	s_or_b32 s7, s9, s7
	s_load_b32 s1, s[16:17], 0x0
	v_ldexp_f32 v1, v1, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, v11, 12, v[3:4]
	v_cvt_f32_u32_e32 v2, s7
	s_sub_i32 s2, 32, s14
	v_mul_f32_e32 v1, 0x3f0374bc, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_ldexp_f32 v2, v2, s2
	global_load_b96 v[8:10], v[13:14], off
	s_mul_hi_i32 s2, s6, 44
	v_div_scale_f32 v3, null, v2, v2, v1
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v24, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_rcp_f32_e32 v4, v3
	s_ashr_i32 s9, s8, 31
	s_cmp_lg_u64 s[8:9], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_scale_f32 v26, null, v24, v24, 1.0
	s_cselect_b32 s18, -1, 0
	s_cmp_lg_u32 s6, 0
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_cselect_b32 s19, -1, 0
	s_add_i32 s20, s6, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v1, v2, v1
	v_mul_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v6, v5
	v_fmac_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v6, v5
	v_div_fmas_f32 v3, v3, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v25, v3, v2, v1
	v_cvt_f64_u32_e32 v[3:4], s13
	s_mov_b32 s12, 0x9999999a
	s_mov_b32 s13, 0x3fb99999
	v_mul_f32_e32 v23, 0xbd2e6169, v25
	v_fmamk_f32 v7, v25, 0x3f7fc494, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v7, v7
	v_fmac_f32_e32 v1, v23, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x4f800000, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	v_cndmask_b32_e32 v5, v1, v2, vcc_lo
	v_cvt_f64_u32_e32 v[1:2], s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v6, v5
	v_ldexp_f64 v[3:4], v[3:4], 32
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v15, -1, v6
	v_add_nc_u32_e32 v16, 1, v6
	v_fma_f32 v17, -v15, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v16, v6, v5
	v_cmp_ge_f32_e64 s0, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v6, v15, s0
	v_cmp_lt_f32_e64 s0, 0, v18
	v_cvt_f64_u32_e32 v[17:18], s10
	s_mov_b64 s[10:11], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v6, v16, s0
	v_ldexp_f64 v[1:2], v[1:2], 32
	v_mul_f32_e32 v15, 0x37800000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_add_f64 v[21:22], v[3:4], v[21:22]
	v_cndmask_b32_e32 v28, v6, v5, vcc_lo
	v_fma_f32 v5, -v26, v27, 1.0
	v_div_scale_f32 v31, vcc_lo, 1.0, v24, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v29, null, v28, v28, 1.0
	v_div_scale_f32 v33, s0, 1.0, v28, 1.0
	v_rcp_f32_e32 v30, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v29, v30, 1.0
	v_fmac_f32_e32 v27, v5, v27
	v_mad_u64_u32 v[5:6], null, v0, s3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v30, v19, v30
	v_mul_f32_e32 v32, v31, v27
	v_add_f64 v[17:18], v[1:2], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[15:16], null, v5, s1, v[11:12]
	v_fma_f32 v19, -v26, v32, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v32, v19, v27 :: v_dual_mov_b32 v5, v16
	v_mul_f32_e32 v16, v33, v30
	v_xor_b32_e32 v15, 0x2c7f967f, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[19:20], null, v6, s1, v[5:6]
	v_fma_f32 v6, -v26, v32, v31
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v5, -v29, v16, v33
	s_mul_i32 s1, s6, 44
	v_mov_b32_e32 v31, 0x438e8000
	s_add_u32 s1, s1, s4
	v_div_fmas_f32 v6, v6, v27, v32
	v_mul_lo_u32 v27, 0x493c4aa1, v15
	v_fmac_f32_e32 v16, v5, v30
	v_xor_b32_e32 v5, 0xa03697cb, v19
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v26, v6, v24, 1.0
	v_mov_b32_e32 v32, 0x40100000
	s_addc_u32 s2, s2, s5
	v_mul_lo_u32 v5, 0x7b99840d, v5
	v_add_nc_u32_e32 v63, 0x75bcd15, v27
	v_fma_f32 v19, -v29, v16, v33
	v_xor_b32_e32 v50, 0x159a55e5, v27
	v_add_nc_u32_e32 v56, 0x583f19, v27
	v_mov_b32_e32 v33, 0x3fc00000
	s_add_u32 s6, s1, 0xffffffd4
	v_div_fmas_f32 v29, v19, v30, v16
	v_cvt_f64_u32_e32 v[15:16], v11
	v_cvt_f64_u32_e32 v[19:20], v0
	v_xor_b32_e32 v54, 0x5491333, v5
	v_add3_u32 v55, v27, v5, 0x64f0c9
	v_div_fixup_f32 v0, v29, v28, 1.0
	v_add_nc_u32_e32 v37, 0x1f123bb5, v5
	v_mov_b32_e32 v30, 0x42500000
	s_mov_b32 s0, -1
	s_addc_u32 s7, s2, -1
	v_mul_f32_e32 v2, v7, v0
	v_mul_f32_e32 v1, 0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v0, v23, v0 :: v_dual_mul_f32 v27, 0x3f0374bc, v1
	v_dual_mul_f32 v28, 0x3f0374bc, v2 :: v_dual_mul_f32 v29, 0x3f0374bc, v0
.LBB0_2:                                ; %.preheader207
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;         Child Loop BB0_14 Depth 4
                                        ;           Child Loop BB0_19 Depth 5
                                        ;           Child Loop BB0_48 Depth 5
                                        ;           Child Loop BB0_57 Depth 5
	v_dual_mov_b32 v4, v56 :: v_dual_mov_b32 v5, v54
	s_xor_b32 s25, s0, -1
	s_mov_b32 s26, -1
	s_mov_b64 s[14:15], 0.5
.LBB0_3:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;         Child Loop BB0_14 Depth 4
                                        ;           Child Loop BB0_19 Depth 5
                                        ;           Child Loop BB0_48 Depth 5
                                        ;           Child Loop BB0_57 Depth 5
	v_mov_b32_e32 v34, 0
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_105
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v34, 0 :: v_dual_mov_b32 v35, 0
	v_mov_b32_e32 v36, 0
	s_mov_b64 s[16:17], 0
.LBB0_5:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_14 Depth 4
                                        ;           Child Loop BB0_19 Depth 5
                                        ;           Child Loop BB0_48 Depth 5
                                        ;           Child Loop BB0_57 Depth 5
	v_lshrrev_b32_e32 v0, 2, v63
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v1, 4, v4
                                        ; implicit-def: $vgpr3
	s_mov_b32 s0, exec_lo
	v_xor_b32_e32 v0, v0, v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 1, v0
	v_xor_b32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v2, v1, v0, v4
	v_add3_u32 v0, v55, v2, 0x587c5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, v0
	v_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v0
	v_cmpx_ngt_f32_e32 1.0, v0
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=3
	v_sub_f32_e32 v0, 2.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v1
	v_add_nc_u32_e32 v6, 1, v1
	v_fma_f32 v7, -v3, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, -v6, v1, v0
	v_cmp_ge_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v3, s0
	v_cmp_lt_f32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v6, s0
	v_mul_f32_e32 v3, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v3, 1.0, v0
                                        ; implicit-def: $vgpr0
.LBB0_7:                                ; %Flow394
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=3
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v1
	v_add_nc_u32_e32 v6, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v3, v1, v0
	v_fma_f32 v11, -v6, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v7
	v_cndmask_b32_e64 v1, v1, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v11
	v_cndmask_b32_e64 v1, v1, v6, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x37800000, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_add_f32_e32 v3, -1.0, v0
.LBB0_9:                                ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_lshrrev_b32_e32 v0, 2, v50
	v_lshlrev_b32_e32 v1, 4, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v50
	v_lshlrev_b32_e32 v6, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v6, v1
	v_xor3_b32 v0, v1, v0, v2
	v_add_nc_u32_e32 v1, 0xb0f8a, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v0, v1
	v_cvt_f32_u32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, 0x2f800000, v6, 0x2f800000
	v_add_f32_e32 v7, v6, v6
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 1.0, v7
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=3
	v_sub_f32_e32 v6, 2.0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, 0x4f800000, v6
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v7
	v_add_nc_u32_e32 v23, 1, v7
	v_fma_f32 v24, -v11, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v23, v7, v6
	v_cmp_ge_f32_e64 s0, 0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cmp_lt_f32_e64 s0, 0, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v23, s0
	v_mul_f32_e32 v11, 0x37800000, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v6, 1.0, v6
.LBB0_11:                               ; %Flow393
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_5 Depth=3
	v_mul_f32_e32 v6, 0x4f800000, v7
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_sqrt_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v7
	v_add_nc_u32_e32 v23, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v11, v7, v6
	v_fma_f32 v38, -v23, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v24
	v_cndmask_b32_e64 v7, v7, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v38
	v_cndmask_b32_e64 v7, v7, v23, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x37800000, v7
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_add_f32_e32 v6, -1.0, v6
.LBB0_13:                               ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_cvt_f64_f32_e32 v[23:24], v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cvt_f64_f32_e32 v[6:7], v6
	s_mov_b32 s27, 0
	s_mov_b32 s28, 0
	v_dual_mov_b32 v58, 1.0 :: v_dual_mov_b32 v63, v37
	v_mov_b32_e32 v64, 0
	v_add_f64 v[23:24], s[14:15], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], s[10:11], v[6:7]
	v_fma_f64 v[23:24], v[23:24], 0.5, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[6:7], 0.5, v[19:20]
	v_div_scale_f64 v[38:39], null, v[17:18], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[40:41], null, v[21:22], v[21:22], v[6:7]
	v_div_scale_f64 v[50:51], vcc_lo, v[23:24], v[17:18], v[23:24]
	v_rcp_f64_e32 v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[44:45], v[40:41]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[46:47], -v[38:39], v[42:43], 1.0
	v_fma_f64 v[48:49], -v[40:41], v[44:45], 1.0
	v_fma_f64 v[42:43], v[42:43], v[46:47], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[44:45], v[44:45], v[48:49], v[44:45]
	v_fma_f64 v[46:47], -v[38:39], v[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], -v[40:41], v[44:45], 1.0
	v_fma_f64 v[42:43], v[42:43], v[46:47], v[42:43]
	v_div_scale_f64 v[46:47], s0, v[6:7], v[21:22], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[44:45], v[48:49], v[44:45]
	v_mul_f64 v[48:49], v[50:51], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[52:53], v[46:47], v[44:45]
	v_fma_f64 v[38:39], -v[38:39], v[48:49], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], -v[40:41], v[52:53], v[46:47]
	v_mov_b32_e32 v47, 1.0
	v_div_fmas_f64 v[38:39], v[38:39], v[42:43], v[48:49]
	s_mov_b32 vcc_lo, s0
                                        ; implicit-def: $vgpr48
                                        ; implicit-def: $vgpr49
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[40:41], v[40:41], v[44:45], v[52:53]
	v_div_fixup_f64 v[23:24], v[38:39], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[40:41], v[21:22], v[6:7]
	v_add_f64 v[23:24], v[23:24], -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -0.5
	v_cvt_f32_f64_e32 v3, v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v6, v[6:7]
	v_mul_f32_e32 v7, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v27, v6
	v_fma_f32 v23, v28, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v25, v3
	v_fmac_f32_e32 v7, v29, v6
	v_add_f32_e32 v3, 0xbd2e6169, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, 0, v11
	v_add_f32_e32 v7, 0xbf7fc494, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v11, v3, v3
	v_fmaak_f32 v43, s21, v6, 0x42480000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v6, v6
	v_mov_b32_e32 v53, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v7, v7
	v_mul_f32_e32 v23, 0x4f800000, v11
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v11, v23, vcc_lo
	v_sqrt_f32_e32 v23, v11
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v24, -1, v23
	v_add_nc_u32_e32 v38, 1, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v24, v23, v11
	v_fma_f32 v40, -v38, v23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v39
	v_cndmask_b32_e64 v23, v23, v24, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v40
	v_cndmask_b32_e64 v23, v23, v38, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, 0x37800000, v23
	v_cndmask_b32_e32 v23, v23, v24, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v23, v11, vcc_lo
	v_div_scale_f32 v23, null, v11, v11, 1.0
	v_div_scale_f32 v39, vcc_lo, 1.0, v11, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v38, -v23, v24, 1.0
	v_fmac_f32_e32 v24, v38, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v40, v39, v24
	v_fma_f32 v38, -v23, v40, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v40, v38, v24
	v_dual_mov_b32 v38, 0 :: v_dual_mov_b32 v59, 1.0
	v_fmamk_f32 v42, v7, 0x430c0000, v31
	v_fmamk_f32 v41, v3, 0x430c0000, v30
	v_fma_f32 v23, -v23, v40, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v52, v42 :: v_dual_mov_b32 v51, v41
	v_div_fmas_f32 v23, v23, v24, v40
	v_mov_b32_e32 v40, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v23, v23, v11, 1.0
	v_mov_b32_e32 v57, 1.0
	v_mov_b32_e32 v39, 0
	v_dual_mov_b32 v11, 1.0 :: v_dual_mul_f32 v46, v7, v23
	v_mul_f32_e32 v44, v6, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v45, v3, v23 :: v_dual_mov_b32 v60, v46
	v_dual_mov_b32 v61, v44 :: v_dual_mov_b32 v62, v45
.LBB0_14:                               ; %.backedge.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_5 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_19 Depth 5
                                        ;           Child Loop BB0_48 Depth 5
                                        ;           Child Loop BB0_57 Depth 5
	v_dual_sub_f32 v6, 0x42480000, v51 :: v_dual_sub_f32 v7, 0x42480000, v53
	s_mov_b32 s1, exec_lo
	v_sub_f32_e32 v23, 0x42a00000, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v6, v62
	v_mul_f32_e32 v6, v6, v6
	v_fmac_f32_e32 v6, v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, v7, v61
	v_fmac_f32_e32 v6, v23, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v23, v60
	v_fma_f32 v6, v3, v3, -v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, 0x47afc800, v6 :: v_dual_mov_b32 v6, 0
	v_cmpx_ngt_f32_e32 0, v7
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mul_f32_e32 v6, 0x4f800000, v7
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_sqrt_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v23, -1, v7
	v_add_nc_u32_e32 v24, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v23, v7, v6
	v_fma_f32 v48, -v24, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v37
	v_cndmask_b32_e64 v7, v7, v23, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v48
	v_cndmask_b32_e64 v7, v7, v24, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, 0x37800000, v7
	v_cndmask_b32_e32 v7, v7, v23, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_add_f32_e32 v48, v3, v6
	v_sub_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v48
	v_cndmask_b32_e32 v6, 0, v48, vcc_lo
	v_cmp_nge_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v49, 0, v3, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v6, v3, vcc_lo
.LBB0_16:                               ; %_ZNK6Sphere9intersectERK3RayPfS3_.exit.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s29, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr66
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $sgpr0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f32_e32 0, v6
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_24
; %bb.17:                               ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_22
; %bb.18:                               ; %.lr.ph.i163.i.preheader
                                        ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v66, 0x60ad78ec
	s_mov_b64 s[2:3], s[6:7]
	s_mov_b32 s29, s20
.LBB0_19:                               ; %.lr.ph.i163.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_5 Depth=3
                                        ;         Parent Loop BB0_14 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	global_load_b128 v[67:70], v12, s[2:3]
	s_mov_b32 s30, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v7, v69, v51 :: v_dual_sub_f32 v24, v70, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v23, v68, v53 :: v_dual_mul_f32 v6, v62, v7
	v_fmac_f32_e32 v6, v61, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v7, v7 :: v_dual_fmac_f32 v6, v60, v24
	v_fmac_f32_e32 v7, v23, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v24, v24
	v_fma_f32 v23, v6, v6, -v7
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v67, v67
	v_cmpx_ngt_f32_e32 0, v23
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_19 Depth=5
	v_mul_f32_e32 v7, 0x4f800000, v23
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v23, v7, vcc_lo
	v_sqrt_f32_e32 v23, v7
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v24, -1, v23
	v_add_nc_u32_e32 v37, 1, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v50, -v24, v23, v7
	v_fma_f32 v54, -v37, v23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v50
	v_cndmask_b32_e64 v23, v23, v24, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v54
	v_cndmask_b32_e64 v23, v23, v37, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, 0x37800000, v23
	v_cndmask_b32_e32 v23, v23, v24, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v23, v7, vcc_lo
	v_add_f32_e32 v23, v6, v7
	v_sub_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v23
	v_cndmask_b32_e32 v7, 0, v23, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v7, v6, vcc_lo
.LBB0_21:                               ; %_ZNK6Sphere9intersectERK3RayPfS3_.exit.i167.i
                                        ;   in Loop: Header=BB0_19 Depth=5
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v7
	v_cmp_lt_f32_e64 s0, v7, v66
	s_and_b32 vcc_lo, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v3, v3, s29, vcc_lo
	s_add_i32 s29, s29, -1
	v_cndmask_b32_e32 v66, v66, v7, vcc_lo
	s_add_u32 s2, s2, 0xffffffd4
	s_addc_u32 s3, s3, -1
	s_cmp_lg_u32 s29, -1
	s_cbranch_scc1 .LBB0_19
	s_branch .LBB0_23
.LBB0_22:                               ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mov_b32 v66, 0x60ad78ec :: v_dual_mov_b32 v3, 0
.LBB0_23:                               ; %_Z9intersectPK6SpheremRK3RayRfRif.exit174.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x60ad78ec, v66
	s_mov_b32 s0, 1
	s_and_b32 s29, vcc_lo, exec_lo
.LBB0_24:                               ; %Flow391
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_saveexec_b32 s30, s1
	v_dual_mov_b32 v70, s0 :: v_dual_mov_b32 v37, v4
	v_dual_mov_b32 v56, v0 :: v_dual_mov_b32 v55, v1
	v_mov_b32_e32 v54, v2
	v_mov_b32_e32 v50, v5
	s_xor_b32 exec_lo, exec_lo, s30
	s_cbranch_execz .LBB0_67
; %bb.25:                               ;   in Loop: Header=BB0_14 Depth=4
	v_lshrrev_b32_e32 v3, 2, v63
	v_lshlrev_b32_e32 v6, 4, v0
	v_lshrrev_b32_e32 v11, 2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v63
	v_xor_b32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v7, 1, v3
	v_xor_b32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v50, v6, v3, v0
	v_lshlrev_b32_e32 v3, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 4, v50
	v_xor_b32_e32 v3, v3, v6
	v_lshrrev_b32_e32 v6, 2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v37, v3, v5, v50
	v_xor_b32_e32 v3, v6, v4
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v4, 4, v37
	v_lshlrev_b32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v5, v4
                                        ; implicit-def: $vgpr5
	v_xor3_b32 v54, v4, v3, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v54, 0x10974f
	v_cvt_f32_u32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_mul_f32_e32 v4, 0x40c90fdb, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x48000000, v4
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_14 Depth=4
	v_and_or_b32 v3, v4, s22, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v3, 0
	v_mov_b32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v3, v[11:12]
	v_mov_b32_e32 v11, v7
	v_lshrrev_b32_e32 v7, 23, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[23:24], null, 0xdb629599, v3, v[11:12]
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 63, v7
	v_mov_b32_e32 v11, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v24, 0, 0xffffffc0, s0
	v_mad_u64_u32 v[55:56], null, 0xf534ddc0, v3, v[11:12]
	v_cndmask_b32_e64 v5, v23, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_mov_b32_e32 v11, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_cndmask_b32_e64 v6, v55, v6, s0
	v_mad_u64_u32 v[65:66], null, 0xfc2757d1, v3, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s1
	v_cndmask_b32_e64 v5, v6, v5, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v24, v7
	v_mov_b32_e32 v11, v66
	v_cndmask_b32_e64 v63, v65, v23, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s2, 31, v7
	v_mad_u64_u32 v[66:67], null, 0x4e441529, v3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v67
	v_mad_u64_u32 v[67:68], null, 0xa2f9836e, v3, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s2
	v_cndmask_b32_e64 v11, v66, v55, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v3, v7
	v_cndmask_b32_e64 v24, v67, v65, s0
	v_cndmask_b32_e64 v56, v68, v66, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v55, 32, v3
	v_cndmask_b32_e64 v7, v24, v11, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, v56, v24, s1
	v_cndmask_b32_e64 v11, v11, v63, s1
	v_cndmask_b32_e64 v56, v63, v6, s1
	v_cmp_eq_u32_e64 s0, 0, v3
	v_cndmask_b32_e64 v24, v24, v7, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v7, v11, s2
	v_cndmask_b32_e64 v11, v11, v56, s2
	v_cndmask_b32_e64 v5, v56, v5, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v63, v24, v7, v55
	v_alignbit_b32 v23, v7, v11, v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v55, v11, v5, v55
	v_cndmask_b32_e64 v3, v63, v24, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v23, v7, s0
	v_cndmask_b32_e64 v11, v55, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v3, 29, 1
	v_alignbit_b32 v23, v3, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v6, v6, v11, 30
	v_alignbit_b32 v5, v11, v5, 30
	v_sub_nc_u32_e32 v24, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v23, v23, v24
	v_xor_b32_e32 v6, v6, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v24
	v_clz_i32_u32_e32 v55, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v55, 32, v55
	v_sub_nc_u32_e32 v11, 31, v55
	v_lshlrev_b32_e32 v63, 23, v55
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v23, v6, v11
	v_alignbit_b32 v5, v6, v5, v11
	v_lshrrev_b32_e32 v11, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	v_alignbit_b32 v6, v23, v5, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v23, 9, v23
	v_clz_i32_u32_e32 v24, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v56, 0.5, v11
	v_min_u32_e32 v24, 32, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v56, v56, v63
	v_sub_nc_u32_e32 v65, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v65
	v_or_b32_e32 v6, v23, v56
	v_add_lshl_u32 v23, v24, v55, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v5, 9, v5
	v_mul_f32_e32 v24, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v23
	v_fma_f32 v23, 0x3fc90fda, v6, -v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 0x33000000, v5
	v_dual_fmac_f32 v23, 0x33a22168, v6 :: v_dual_add_nc_u32 v6, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v5, v11
	v_fmac_f32_e32 v23, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, v24, v23
.LBB0_27:                               ; %Flow390
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_saveexec_b32 s0, s3
; %bb.28:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mul_f32_e32 v3, 0x3f22f983, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v3, v3
	v_fmamk_f32 v5, v3, 0xbfc90fda, v4
	v_cvt_i32_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v3
	v_fmac_f32_e32 v5, 0xa7c234c4, v3
; %bb.29:                               ; %_ZL3cosf.exit.i.i.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr65
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_14 Depth=4
	v_and_or_b32 v3, v4, s22, 0x800000
	v_lshrrev_b32_e32 v7, 23, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[23:24], null, 0xfe5163ab, v3, 0
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_mov_b32_e32 v11, v24
	v_cndmask_b32_e64 v24, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[55:56], null, 0x3c439041, v3, v[11:12]
	v_add_nc_u32_e32 v7, v24, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v56
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[65:66], null, 0xdb629599, v3, v[11:12]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_mov_b32_e32 v11, v66
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v65, v23, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[66:67], null, 0xf534ddc0, v3, v[11:12]
	v_mov_b32_e32 v11, v67
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[67:68], null, 0xfc2757d1, v3, v[11:12]
	v_mov_b32_e32 v11, v68
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v63, v67, v65, vcc_lo
	v_mad_u64_u32 v[68:69], null, 0x4e441529, v3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v69
	v_mad_u64_u32 v[69:70], null, 0xa2f9836e, v3, v[11:12]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v68, v66, vcc_lo
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v24, v69, v67, vcc_lo
	v_cndmask_b32_e32 v56, v70, v68, vcc_lo
	v_cndmask_b32_e32 v7, v66, v55, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v55, v24, v11, s0
	v_cndmask_b32_e64 v24, v56, v24, s0
	v_cndmask_b32_e64 v11, v11, v63, s0
	v_sub_nc_u32_e32 v56, 32, v3
	v_cndmask_b32_e64 v63, v63, v7, s0
	v_cndmask_b32_e64 v7, v7, v23, s0
	v_cndmask_b32_e64 v24, v24, v55, s1
	v_cndmask_b32_e64 v55, v55, v11, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v63, s1
	v_cndmask_b32_e64 v7, v63, v7, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v66, v24, v55, v56
	v_alignbit_b32 v65, v55, v11, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v56, v11, v7, v56
	v_cndmask_b32_e32 v3, v66, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v65, v55, vcc_lo
	v_cndmask_b32_e32 v11, v56, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v24, v3, 29, 1
	v_alignbit_b32 v55, v3, v23, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v23, v23, v11, 30
	v_alignbit_b32 v7, v11, v7, 30
	v_sub_nc_u32_e32 v63, 0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v55, v55, v63
	v_xor_b32_e32 v11, v23, v63
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v63
	v_clz_i32_u32_e32 v56, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v56, 32, v56
	v_sub_nc_u32_e32 v23, 31, v56
	v_lshlrev_b32_e32 v66, 23, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v55, v55, v11, v23
	v_alignbit_b32 v7, v11, v7, v23
	v_lshrrev_b32_e32 v23, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	v_alignbit_b32 v11, v55, v7, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v23, 31, v23
	v_lshrrev_b32_e32 v55, 9, v55
	v_clz_i32_u32_e32 v63, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v65, 0.5, v23
	v_min_u32_e32 v63, 32, v63
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v65, v65, v66
	v_sub_nc_u32_e32 v67, 31, v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v11, v7, v67
	v_or_b32_e32 v11, v55, v65
	v_add_lshl_u32 v55, v63, v56, 23
	v_add_nc_u32_e32 v65, v24, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v7, 9, v7
	v_mul_f32_e32 v56, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v55
	v_fma_f32 v55, 0x3fc90fda, v11, -v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 0x33000000, v7
	v_fmac_f32_e32 v55, 0x33a22168, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v7, v7, v23
	v_fmac_f32_e32 v55, 0x3fc90fda, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v7, v56, v55
.LBB0_31:                               ; %Flow389
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_saveexec_b32 s0, s2
; %bb.32:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mul_f32_e32 v3, 0x3f22f983, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v3, v3
	v_fmamk_f32 v7, v3, 0xbfc90fda, v4
	v_cvt_i32_f32_e32 v65, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, 0xb3a22168, v3
	v_fmac_f32_e32 v7, 0xa7c234c4, v3
; %bb.33:                               ; %_Z8sampleHGfff.exit.i.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_le_f32_e64 s0, |v61|, |v62|
                                        ; implicit-def: $vgpr63
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_39
; %bb.34:                               ;   in Loop: Header=BB0_14 Depth=4
	v_cmp_le_f32_e64 s1, |v61|, |v60|
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $sgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s1
	s_xor_b32 s1, exec_lo, s3
; %bb.35:                               ;   in Loop: Header=BB0_14 Depth=4
	v_xor_b32_e32 v24, 0x80000000, v60
	s_mov_b32 s2, 0
; %bb.36:                               ; %Flow384
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v23, s2
	v_mov_b32_e32 v63, v62
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.37:                               ;   in Loop: Header=BB0_14 Depth=4
	v_xor_b32_e32 v23, 0x80000000, v62
	v_dual_mov_b32 v63, 0 :: v_dual_mov_b32 v24, v61
; %bb.38:                               ; %Flow385
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_39:                               ; %Flow388
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_45
; %bb.40:                               ;   in Loop: Header=BB0_14 Depth=4
	v_cmp_le_f32_e64 s1, |v62|, |v60|
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s1
	s_xor_b32 s1, exec_lo, s3
; %bb.41:                               ;   in Loop: Header=BB0_14 Depth=4
	v_xor_b32_e32 v23, 0x80000000, v60
	s_mov_b32 s2, 0
; %bb.42:                               ; %Flow386
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_saveexec_b32 s1, s1
	v_dual_mov_b32 v24, s2 :: v_dual_mov_b32 v63, v61
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.43:                               ;   in Loop: Header=BB0_14 Depth=4
	v_xor_b32_e32 v23, 0x80000000, v62
	v_dual_mov_b32 v63, 0 :: v_dual_mov_b32 v24, v61
; %bb.44:                               ; %Flow387
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_45:                               ; %_Z18generateOrthoBasisR3VecS0_S_.exit.i.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_f32_e32 v3, v48, v49
	s_mov_b32 s33, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr76
                                        ; implicit-def: $sgpr0
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr73
                                        ; implicit-def: $vgpr74
                                        ; implicit-def: $vgpr75
                                        ; implicit-def: $vgpr72
                                        ; implicit-def: $vgpr71
                                        ; implicit-def: $vgpr78
                                        ; implicit-def: $vgpr79
                                        ; implicit-def: $vgpr77
	s_mov_b32 s3, exec_lo
	v_mul_f32_e32 v3, 0xbc1374bc, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fb8aa3b, v3
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_fma_f32 v55, 0x3fb8aa3b, v3, -v11
	v_rndne_f32_e32 v56, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v55, 0x32a5705f, v3
	v_sub_f32_e32 v11, v11, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v55
	v_cvt_i32_f32_e32 v55, v56
	v_exp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v11, v11, v55
	v_lshrrev_b32_e32 v55, 2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_xor_b32_e32 v2, v55, v2
	v_lshlrev_b32_e32 v55, 4, v54
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7f800000, v11, vcc_lo
	v_sub_f32_e32 v68, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v67, 1.0, v68
	v_div_scale_f32 v3, null, v67, v67, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v56, -v3, v11, 1.0
	v_dual_fmac_f32 v11, v56, v11 :: v_dual_lshlrev_b32 v56, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v56, v56, v55
	v_add_nc_u32_e32 v55, 0x161f14, v1
	v_xor3_b32 v56, v56, v2, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v56, v55
	v_div_scale_f32 v66, vcc_lo, 1.0, v67, 1.0
	v_cvt_f32_u32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v69, v66, v11 :: v_dual_fmaak_f32 v2, 0x2f800000, v2, 0x2f800000
	v_fma_f32 v70, -v3, v69, v66
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v69, v70, v11
	v_fma_f32 v3, -v3, v69, v66
                                        ; implicit-def: $vgpr66
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v11, v69
                                        ; implicit-def: $vgpr69
	v_div_fixup_f32 v11, v3, v67, 1.0
                                        ; implicit-def: $vgpr3
	v_cmpx_le_f32_e32 v2, v68
	s_xor_b32 s31, exec_lo, s3
	s_cbranch_execz .LBB0_54
; %bb.46:                               ;   in Loop: Header=BB0_14 Depth=4
	v_add3_u32 v2, v1, v50, 0x587c5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, v2
	v_fmaak_f32 v2, 0x2f800000, v2, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v68, 1.0
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	v_log_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x3f317217, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v66, 0x3f317217, v2, -v3
	v_fmac_f32_e32 v66, 0x3377d1cf, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v3, v3, v66
	v_cndmask_b32_e64 v66, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v66
	v_div_scale_f32 v3, null, 0xbc1374bc, 0xbc1374bc, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v66, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v69, -v3, v66, 1.0
	v_fmac_f32_e32 v66, v69, v66
	v_div_scale_f32 v69, vcc_lo, v2, 0xbc1374bc, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v70, v69, v66
	v_fma_f32 v71, -v3, v70, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v70, v71, v66
	v_fma_f32 v3, -v3, v70, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v66, v70
	s_and_not1_b32 vcc_lo, exec_lo, s19
	v_div_fixup_f32 v2, v3, 0xbc1374bc, v2
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v69, v49, v2
	v_mov_b32_e32 v66, v69
	s_cbranch_vccnz .LBB0_51
; %bb.47:                               ; %.lr.ph.i.i.preheader
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b64 s[2:3], s[6:7]
	s_mov_b32 s1, s20
.LBB0_48:                               ; %.lr.ph.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_5 Depth=3
                                        ;         Parent Loop BB0_14 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	global_load_b128 v[71:74], v12, s[2:3]
	s_mov_b32 s33, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v73, v73, v51 :: v_dual_sub_f32 v72, v72, v53
	v_sub_f32_e32 v74, v74, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v70, v62, v73
	v_mul_f32_e32 v73, v73, v73
	v_fmac_f32_e32 v73, v72, v72
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v70, v61, v72 :: v_dual_fmac_f32 v73, v74, v74
	v_fmac_f32_e32 v70, v60, v74
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v72, v70, v70, -v73
	v_dual_fmac_f32 v72, v71, v71 :: v_dual_mov_b32 v71, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0, v72
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_48 Depth=5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v72
	v_mul_f32_e32 v71, 0x4f800000, v72
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v71, v72, v71, vcc_lo
	v_sqrt_f32_e32 v72, v71
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v74, 1, v72
	v_add_nc_u32_e32 v73, -1, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v76, -v74, v72, v71
	v_fma_f32 v75, -v73, v72, v71
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v75
	v_cndmask_b32_e64 v72, v72, v73, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v76
	v_cndmask_b32_e64 v72, v72, v74, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v73, 0x37800000, v72
	v_cndmask_b32_e32 v72, v72, v73, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v71, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v71, v72, v71, vcc_lo
	v_add_f32_e32 v72, v70, v71
	v_sub_f32_e32 v70, v70, v71
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v72
	v_cndmask_b32_e32 v71, 0, v72, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v70
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v71, v71, v70, vcc_lo
.LBB0_50:                               ; %_ZNK6Sphere9intersectERK3RayPfS3_.exit.i.i
                                        ;   in Loop: Header=BB0_48 Depth=5
	s_or_b32 exec_lo, exec_lo, s33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v71
	v_cmp_lt_f32_e64 s0, v71, v66
	s_and_b32 vcc_lo, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v3, v3, s1, vcc_lo
	s_add_i32 s1, s1, -1
	v_cndmask_b32_e32 v66, v66, v71, vcc_lo
	s_add_u32 s2, s2, 0xffffffd4
	s_addc_u32 s3, s3, -1
	s_cmp_lg_u32 s1, -1
	s_cbranch_scc1 .LBB0_48
.LBB0_51:                               ; %_Z9intersectPK6SpheremRK3RayRfRif.exit.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, v66, v69
	s_mov_b32 s3, -1
                                        ; implicit-def: $vgpr76
                                        ; implicit-def: $sgpr0
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr73
                                        ; implicit-def: $vgpr74
                                        ; implicit-def: $vgpr75
                                        ; implicit-def: $vgpr72
                                        ; implicit-def: $vgpr69
                                        ; implicit-def: $vgpr71
                                        ; implicit-def: $vgpr78
                                        ; implicit-def: $vgpr79
                                        ; implicit-def: $vgpr77
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_14 Depth=4
	v_add3_u32 v1, v1, v37, 0xb0f8a
	s_xor_b32 s3, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, v1
	v_fmaak_f32 v1, 0x2f800000, v1, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[69:70], v1
	v_fma_f32 v77, v1, -2.0, 1.0
	v_cvt_f64_f32_e32 v[73:74], v77
	v_mul_f32_e32 v75, 0x3e800000, v77
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[75:76], v75
	v_add_f64 v[71:72], v[69:70], -1.0
	v_ldexp_f64 v[71:72], -v[71:72], -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[69:70], v[71:72], v[69:70], v[73:74]
	v_sub_f32_e32 v71, 1.0, v1
	v_fmac_f32_e32 v71, v1, v1
	v_fma_f32 v1, v77, -0.5, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[71:72], v71
	v_mul_f32_e32 v1, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[73:74], v1
	v_mul_f32_e32 v1, v24, v24
	v_fmac_f32_e32 v1, v23, v23
	v_add_f64 v[69:70], v[69:70], v[75:76]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[69:70], v[69:70], -v[71:72]
	v_div_scale_f64 v[71:72], null, v[73:74], v[73:74], v[69:70]
	v_div_scale_f64 v[79:80], vcc_lo, v[69:70], v[73:74], v[69:70]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[75:76], v[71:72]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[77:78], -v[71:72], v[75:76], 1.0
	v_fma_f64 v[75:76], v[75:76], v[77:78], v[75:76]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[77:78], -v[71:72], v[75:76], 1.0
	v_fma_f64 v[75:76], v[75:76], v[77:78], v[75:76]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[77:78], v[79:80], v[75:76]
	v_fma_f64 v[71:72], -v[71:72], v[77:78], v[79:80]
	v_mul_f32_e32 v79, v58, v68
	v_mul_f32_e32 v80, v59, v68
	v_dual_mul_f32 v68, v57, v68 :: v_dual_fmac_f32 v1, v63, v63
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[71:72], v[71:72], v[75:76], v[77:78]
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[69:70], v[71:72], v[73:74], v[69:70]
	v_mul_f32_e32 v71, 0x4f800000, v1
	v_cndmask_b32_e32 v1, v1, v71, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v71, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v72, -1, v71
	v_add_nc_u32_e32 v73, 1, v71
	v_fma_f32 v74, -v72, v71, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v74
	v_mul_f32_e32 v74, v5, v5
	v_fmaak_f32 v82, s24, v74, 0x3c0881c4
	v_cvt_f32_f64_e32 v70, v[69:70]
	v_fmaak_f32 v81, s23, v74, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmaak_f32 v82, v74, v82, 0xbe2aaa9d
	v_fma_f32 v75, -v73, v71, v1
	v_cndmask_b32_e64 v71, v71, v72, s0
	v_fmaak_f32 v81, v74, v81, 0x3d2aabf7
	v_fma_f32 v72, v60, v49, v52
	v_mul_f32_e32 v82, v74, v82
	v_cmp_lt_f32_e64 s0, 0, v75
	v_mul_f32_e32 v75, v7, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v81, v74, v81, 0xbf000004 :: v_dual_fmac_f32 v72, v60, v2
	v_dual_fmac_f32 v5, v5, v82 :: v_dual_fmaak_f32 v84, s23, v75, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v74, v74, v81, 1.0
	v_fmaak_f32 v84, v75, v84, 0x3d2aabf7
	v_cndmask_b32_e64 v69, v71, v73, s0
	v_lshlrev_b32_e32 v73, 30, v6
	v_and_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v84, v75, v84, 0xbf000004
	v_mul_f32_e32 v71, 0x37800000, v69
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, 0, v6
	v_cndmask_b32_e32 v69, v69, v71, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v1, 0x260
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v5, -v5, v74, s1
	v_fma_f32 v71, v61, v49, v53
	s_mov_b32 s1, 0
	v_cndmask_b32_e32 v1, v69, v1, vcc_lo
	v_fma_f32 v86, -v70, v70, 1.0
	v_fma_f32 v69, v62, v49, v51
	v_fmac_f32_e32 v71, v61, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v76, null, v1, v1, 1.0
	v_div_scale_f32 v87, vcc_lo, 1.0, v1, 1.0
	v_cmp_gt_f32_e64 s0, 0xf800000, v86
	v_rcp_f32_e32 v78, v76
	v_fmac_f32_e32 v69, v62, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v85, -v76, v78, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v85, v78
	v_mul_f32_e32 v85, 0x4f800000, v86
	v_mul_f32_e32 v88, v87, v78
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v85, v86, v85, s0
	v_fma_f32 v86, -v76, v88, v87
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v89, v85
	v_fmac_f32_e32 v88, v86, v78
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f32 v76, -v76, v88, v87
	s_waitcnt_depctr 0xfff
	v_dual_fmaak_f32 v83, s24, v75, 0x3c0881c4 :: v_dual_add_nc_u32 v6, -1, v89
	v_and_b32_e32 v77, 1, v65
	v_div_fmas_f32 v74, v76, v78, v88
	v_dual_fmaak_f32 v83, v75, v83, 0xbe2aaa9d :: v_dual_add_nc_u32 v76, 1, v89
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v78, -v6, v89, v85
	v_cmp_eq_u32_e32 vcc_lo, 0, v77
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v1, v74, v1, 1.0
	v_mul_f32_e32 v77, v79, v67
	v_mul_f32_e32 v79, v80, v67
	v_mul_f32_e32 v24, v24, v1
	v_and_b32_e32 v73, 0x80000000, v73
	v_mul_f32_e32 v23, v23, v1
	v_mul_f32_e32 v1, v63, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v63, v60, v24
	v_xor_b32_e32 v5, v73, v5
	v_mul_f32_e32 v83, v75, v83
	v_fma_f32 v75, v75, v84, 1.0
	v_fma_f32 v73, -v76, v89, v85
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v7, v83
	v_cndmask_b32_e32 v7, v75, v7, vcc_lo
	v_cmp_ge_f32_e32 vcc_lo, 0, v78
	v_mul_f32_e32 v78, v68, v67
	v_cndmask_b32_e32 v6, v89, v6, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v73
	v_lshlrev_b32_e32 v65, 30, v65
	v_mul_f32_e32 v73, v61, v1
	v_fma_f32 v1, v62, v1, -v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v6, v6, v76 :: v_dual_and_b32 v65, 0x80000000, v65
	v_cmp_lg_f32_e32 vcc_lo, 0x7f800000, v4
	v_add_nc_u32_e32 v76, 1, v64
	v_xor_b32_e32 v7, v65, v7
	v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
	v_mul_f32_e32 v5, 0x37800000, v6
	v_mul_f32_e32 v65, v62, v23
	v_fma_f32 v23, v60, v23, -v73
	v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v85, 0x260
	v_cndmask_b32_e64 v5, v6, v5, s0
	v_fma_f32 v6, v61, v24, -v65
	v_dual_mul_f32 v24, v62, v1 :: v_dual_mul_f32 v65, v60, v23
	s_mov_b32 s0, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v85, vcc_lo
	v_mul_f32_e32 v63, v61, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v24, v61, v23, -v24
	v_fma_f32 v65, v62, v6, -v65
	v_mul_f32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v63, v60, v1, -v63
	v_mul_f32_e32 v4, v5, v4
	v_mul_f32_e32 v73, v7, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v74, v7, v63
	v_mul_f32_e32 v75, v7, v65
	v_fmac_f32_e32 v73, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v74, v4, v23
	v_fmac_f32_e32 v75, v4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v73, v60, v70
	v_fmac_f32_e32 v74, v62, v70
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v75, v61, v70
.LBB0_53:                               ; %Flow382
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, 1.0
	s_and_b32 s33, s3, exec_lo
.LBB0_54:                               ; %Flow381
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_saveexec_b32 s31, s31
	v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v70, s0
	s_xor_b32 exec_lo, exec_lo, s31
	s_cbranch_execz .LBB0_62
; %bb.55:                               ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_60
; %bb.56:                               ; %.lr.ph.i150.i.preheader
                                        ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v66, 0x60ad78ec
	s_mov_b64 s[2:3], s[6:7]
	s_mov_b32 s34, s20
.LBB0_57:                               ; %.lr.ph.i150.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_5 Depth=3
                                        ;         Parent Loop BB0_14 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	global_load_b128 v[67:70], v12, s[2:3]
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v2, v69, v51 :: v_dual_sub_f32 v5, v70, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v68, v53 :: v_dual_mul_f32 v1, v62, v2
	v_dual_mul_f32 v2, v2, v2 :: v_dual_fmac_f32 v1, v61, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, v4, v4
	v_fmac_f32_e32 v1, v60, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v5
	v_fma_f32 v4, v1, v1, -v2
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v67, v67
	v_cmpx_ngt_f32_e32 0, v4
	s_cbranch_execz .LBB0_59
; %bb.58:                               ;   in Loop: Header=BB0_57 Depth=5
	v_mul_f32_e32 v2, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v4, v2, vcc_lo
	v_sqrt_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v5, -1, v4
	v_add_nc_u32_e32 v6, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v4, v2
	v_fma_f32 v23, -v6, v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v7
	v_cndmask_b32_e64 v4, v4, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v23
	v_cndmask_b32_e64 v4, v4, v6, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0x37800000, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v4, v2, vcc_lo
	v_add_f32_e32 v4, v1, v2
	v_sub_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v4
	v_cndmask_b32_e32 v2, 0, v4, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0x38d1b717, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v1, vcc_lo
.LBB0_59:                               ; %_ZNK6Sphere9intersectERK3RayPfS3_.exit.i154.i
                                        ;   in Loop: Header=BB0_57 Depth=5
	s_or_b32 exec_lo, exec_lo, s35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_cmp_lt_f32_e64 s0, v2, v66
	s_and_b32 vcc_lo, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v3, v3, s34, vcc_lo
	s_add_i32 s34, s34, -1
	v_cndmask_b32_e32 v66, v66, v2, vcc_lo
	s_add_u32 s2, s2, 0xffffffd4
	s_addc_u32 s3, s3, -1
	s_cmp_lg_u32 s34, -1
	s_cbranch_scc1 .LBB0_57
	s_branch .LBB0_61
.LBB0_60:                               ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mov_b32 v66, 0x60ad78ec :: v_dual_mov_b32 v3, 0
.LBB0_61:                               ; %_Z9intersectPK6SpheremRK3RayRfRif.exit161.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x60ad78ec, v66
	v_dual_mov_b32 v70, 1 :: v_dual_mov_b32 v1, v11
	v_dual_mov_b32 v76, v64 :: v_dual_mov_b32 v75, v61
	v_dual_mov_b32 v73, v60 :: v_dual_mov_b32 v74, v62
	v_dual_mov_b32 v72, v52 :: v_dual_mov_b32 v69, v51
	v_mov_b32_e32 v71, v53
	v_dual_mov_b32 v78, v57 :: v_dual_mov_b32 v79, v59
	v_mov_b32_e32 v77, v58
	s_and_not1_b32 s0, s33, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_and_not1_b32 s1, s1, exec_lo
	s_or_b32 s33, s0, s2
.LBB0_62:                               ; %Flow383
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s31
	s_and_saveexec_b32 s0, s33
	s_cbranch_execz .LBB0_66
; %bb.63:                               ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b32 s2, exec_lo
	v_cmpx_ge_f32_e32 v66, v49
	s_cbranch_execz .LBB0_65
; %bb.64:                               ;   in Loop: Header=BB0_14 Depth=4
	v_cmp_gt_f32_e32 vcc_lo, v66, v48
	v_cndmask_b32_e32 v2, v66, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v49
	v_mul_f32_e32 v2, 0xbc75c28f, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x3fb8aa3b, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	v_fma_f32 v5, 0x3fb8aa3b, v2, -v4
	v_rndne_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, 0x32a5705f, v2
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v5
	v_cvt_i32_f32_e32 v5, v6
	v_exp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	v_cndmask_b32_e32 v47, 0x7f800000, v4, vcc_lo
.LBB0_65:                               ; %Flow377
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v70, 0 :: v_dual_mov_b32 v77, v58
	v_dual_mov_b32 v79, v59 :: v_dual_mov_b32 v78, v57
	v_dual_mov_b32 v71, v53 :: v_dual_mov_b32 v72, v52
	v_dual_mov_b32 v69, v51 :: v_dual_mov_b32 v74, v62
	v_dual_mov_b32 v75, v61 :: v_dual_mov_b32 v76, v64
	v_mov_b32_e32 v73, v60
	v_mov_b32_e32 v11, v1
	s_or_b32 s1, s1, exec_lo
.LBB0_66:                               ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v64, v76 :: v_dual_mov_b32 v61, v75
	v_dual_mov_b32 v60, v73 :: v_dual_mov_b32 v53, v71
	v_dual_mov_b32 v62, v74 :: v_dual_mov_b32 v51, v69
	v_dual_mov_b32 v52, v72 :: v_dual_mov_b32 v57, v78
	v_dual_mov_b32 v59, v79 :: v_dual_mov_b32 v58, v77
	v_mov_b32_e32 v63, v0
	s_and_not1_b32 s0, s29, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s29, s0, s1
.LBB0_67:                               ; %Flow392
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s30
	s_and_saveexec_b32 s3, s29
	s_cbranch_execz .LBB0_101
; %bb.68:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mad_i64_i32 v[23:24], null, v3, 44, s[4:5]
	s_mov_b32 s0, -1
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr65
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr69
                                        ; implicit-def: $vgpr68
                                        ; implicit-def: $vgpr71
	s_clause 0x2
	global_load_b32 v72, v[23:24], off offset:36
	global_load_b128 v[0:3], v[23:24], off offset:20
	global_load_b128 v[4:7], v[23:24], off offset:4
	v_cmpx_lt_i32_e32 4, v64
	s_cbranch_execz .LBB0_72
; %bb.69:                               ;   in Loop: Header=BB0_14 Depth=4
	v_lshrrev_b32_e32 v65, 2, v63
	v_add_nc_u32_e32 v55, 0x587c5, v55
	s_waitcnt vmcnt(1)
	v_cmp_gt_f32_e64 s1, v3, v72
	v_cmp_gt_f32_e32 vcc_lo, v2, v3
	v_cmp_gt_f32_e64 s0, v2, v72
	v_xor_b32_e32 v63, v65, v63
	v_lshlrev_b32_e32 v65, 4, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 vcc_lo, vcc_lo, s0
	v_lshlrev_b32_e32 v67, 1, v63
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v65, v67, v65
	v_xor3_b32 v69, v65, v63, v56
	v_cndmask_b32_e64 v65, v72, v3, s1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v63, v69, v55
	v_cvt_f32_u32_e32 v67, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v63, v65, v2, vcc_lo
	v_add_nc_u32_e32 v65, 1, v64
	v_fmaak_f32 v67, 0x2f800000, v67, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 v67, v63
	s_cbranch_execz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_14 Depth=4
	v_div_scale_f32 v51, null, v63, v63, 1.0
	v_div_scale_f32 v65, vcc_lo, 1.0, v63, 1.0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v52, v51
	s_waitcnt_depctr 0xfff
	v_fma_f32 v53, -v51, v52, 1.0
	v_fmac_f32_e32 v52, v53, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v53, v65, v52
	v_fma_f32 v67, -v51, v53, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v53, v67, v52
	v_fma_f32 v51, -v51, v53, v65
                                        ; implicit-def: $vgpr65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v51, v51, v52, v53
                                        ; implicit-def: $vgpr52
                                        ; implicit-def: $vgpr53
	v_div_fixup_f32 v51, v51, v63, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v58, v58, v51
	v_mul_f32_e32 v59, v59, v51
	v_mul_f32_e32 v57, v57, v51
                                        ; implicit-def: $vgpr51
.LBB0_71:                               ; %Flow373
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v63, v50 :: v_dual_mov_b32 v70, v56
	v_dual_mov_b32 v67, v54 :: v_dual_mov_b32 v68, v56
	v_dual_mov_b32 v71, v54 :: v_dual_mov_b32 v50, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v56, v69 :: v_dual_mov_b32 v37, v67
	v_mov_b32_e32 v54, v70
	s_mov_b32 s1, 1
	s_or_not1_b32 s0, s0, exec_lo
.LBB0_72:                               ; %Flow372
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v70, s1
	s_and_saveexec_b32 s29, s0
	s_cbranch_execz .LBB0_100
; %bb.73:                               ;   in Loop: Header=BB0_14 Depth=4
	global_load_b32 v65, v[23:24], off offset:40
	v_fma_f32 v51, v45, v66, v41
	v_fma_f32 v53, v44, v66, v43
	v_fma_f32 v52, v46, v66, v42
	v_mov_b32_e32 v73, 2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v51, v5 :: v_dual_sub_f32 v4, v53, v4
	v_dual_sub_f32 v24, v52, v6 :: v_dual_mul_f32 v23, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v4, v4
	v_fmac_f32_e32 v23, v24, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v23
	v_mul_f32_e32 v6, 0x4f800000, v23
	v_cndmask_b32_e32 v6, v23, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v23, v6
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v67, 1, v23
	v_add_nc_u32_e32 v66, -1, v23
	v_fma_f32 v69, -v67, v23, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v68, -v66, v23, v6
	v_cmp_ge_f32_e64 s0, 0, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v66, s0
	v_cmp_lt_f32_e64 s0, 0, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, v23, v67, s0
	v_mul_f32_e32 v66, 0x37800000, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v23, v66, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	v_cndmask_b32_e32 v6, v23, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v23, null, v6, v6, 1.0
	v_rcp_f32_e32 v66, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v67, -v23, v66, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v66, v67, v66
	v_div_scale_f32 v67, vcc_lo, 1.0, v6, 1.0
	v_mul_f32_e32 v68, v67, v66
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v69, -v23, v68, v67
	v_fmac_f32_e32 v68, v69, v66
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v23, v68, v67
	v_div_fmas_f32 v23, v23, v66, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v66, v23, v6, 1.0
	v_mul_f32_e32 v23, v5, v66
	v_mul_f32_e32 v6, v4, v66
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v5, v24, v66 :: v_dual_mul_f32 v4, v62, v23
	v_fmac_f32_e32 v4, v61, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v60, v5
	v_cmp_gt_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v67, -v23, v23, vcc_lo
	v_cndmask_b32_e64 v66, -v6, v6, vcc_lo
	v_cndmask_b32_e64 v24, -v5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v23, v67
	v_fmac_f32_e32 v4, v6, v66
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v24
	v_cmp_lt_f32_e32 vcc_lo, 0, v4
	v_cmp_nlt_f32_e64 s0, 0, v4
	v_mov_b32_e32 v4, 1.0
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s1, 2, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s1
	s_and_saveexec_b32 s1, s2
; %bb.74:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	v_mul_f32_e32 v1, v47, v1
	v_dual_mul_f32 v0, v47, v0 :: v_dual_mov_b32 v73, v65
	v_mul_f32_e32 v7, v47, v7
	v_mul_f32_e32 v57, v47, v57
	v_mul_f32_e32 v59, v47, v59
	v_mul_f32_e32 v58, v47, v58
	v_mov_b32_e32 v4, v11
; %bb.75:                               ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v38, v7, v58 :: v_dual_mul_f32 v7, v72, v4
	v_dual_mul_f32 v2, v2, v4 :: v_dual_fmac_f32 v39, v1, v57
	v_dual_mul_f32 v3, v3, v4 :: v_dual_fmac_f32 v40, v0, v59
	v_dual_mul_f32 v0, v58, v2 :: v_dual_add_nc_u32 v65, 2, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v2, v57, v7
	v_mul_f32_e32 v1, v59, v3
	s_mov_b32 s30, 0
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr70
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr62
                                        ; implicit-def: $vgpr61
                                        ; implicit-def: $vgpr57
                                        ; implicit-def: $vgpr59
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr69
                                        ; implicit-def: $vgpr68
                                        ; implicit-def: $vgpr71
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr64
                                        ; implicit-def: $vgpr3
	v_cmpx_lt_i32_e32 1, v73
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_85
; %bb.76:                               ; %LeafBlock355
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b32 s1, -1
	s_mov_b32 s31, exec_lo
                                        ; implicit-def: $vgpr70
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr62
                                        ; implicit-def: $vgpr61
                                        ; implicit-def: $vgpr57
                                        ; implicit-def: $vgpr59
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr69
                                        ; implicit-def: $vgpr68
                                        ; implicit-def: $vgpr71
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr64
                                        ; implicit-def: $vgpr3
	v_cmpx_eq_u32_e32 2, v73
	s_cbranch_execz .LBB0_84
; %bb.77:                               ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mul_f32 v72, v45, v67 :: v_dual_add_f32 v3, v6, v6
	v_dual_mul_f32 v74, v45, v23 :: v_dual_mov_b32 v69, v56
	v_dual_add_f32 v60, v23, v23 :: v_dual_add_f32 v73, v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v72, v44, v66 :: v_dual_mov_b32 v57, v2
	v_dual_fmac_f32 v74, v44, v6 :: v_dual_mov_b32 v7, v50
	v_cndmask_b32_e64 v11, 0x3ee38e3a, v32, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v72, v46, v24 :: v_dual_mov_b32 v71, v37
	v_fmac_f32_e32 v74, v46, v5
	v_dual_mov_b32 v70, 0 :: v_dual_mov_b32 v59, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v61, -v72, v72, 1.0
	v_mov_b32_e32 v58, v0
	v_mov_b32_e32 v68, v54
	v_mov_b32_e32 v64, v63
	v_fma_f32 v62, -v60, v74, v45
	v_fma_f32 v11, -v11, v61, 1.0
	v_fma_f32 v61, -v3, v74, v44
	v_mov_b32_e32 v3, v55
	v_fma_f32 v60, -v73, v74, v46
	s_mov_b32 s33, exec_lo
	v_cmpx_ngt_f32_e32 0, v11
	s_cbranch_execz .LBB0_83
; %bb.78:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mul_f32_e32 v3, 0x4f800000, v11
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v11, v3, vcc_lo
	v_sqrt_f32_e32 v7, v3
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v7
	v_add_nc_u32_e32 v57, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v58, -v11, v7, v3
	v_fma_f32 v59, -v57, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v58
	v_cndmask_b32_e64 v7, v7, v11, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s1, 0, v59
	v_cndmask_b32_e64 v7, v7, v57, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x37800000, v7
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	v_cndmask_b32_e64 v11, 0x3f2aaaab, v33, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v7, v3, vcc_lo
	v_fmac_f32_e32 v3, v72, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, -v3, s0
	v_mul_f32_e32 v7, v23, v3
	v_mul_f32_e32 v57, v6, v3
	v_mul_f32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v45, v11, -v7
	v_fma_f32 v57, v44, v11, -v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v3, v46, v11, -v3
	v_mul_f32_e32 v58, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v58, v57, v57
	v_fmac_f32_e32 v58, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v58
	v_mul_f32_e32 v11, 0x4f800000, v58
	v_cndmask_b32_e32 v11, v58, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v58, v11
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v59, -1, v58
	v_add_nc_u32_e32 v64, 1, v58
	v_fma_f32 v68, -v59, v58, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v69, -v64, v58, v11
	v_cmp_ge_f32_e64 s1, 0, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v58, v58, v59, s1
	v_cmp_lt_f32_e64 s1, 0, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v58, v58, v64, s1
                                        ; implicit-def: $sgpr1
	v_mul_f32_e32 v59, 0x37800000, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v58, v58, v59, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
	v_cndmask_b32_e32 v11, v58, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v58, null, v11, v11, 1.0
	v_rcp_f32_e32 v59, v58
	s_waitcnt_depctr 0xfff
	v_fma_f32 v64, -v58, v59, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v59, v64, v59
	v_div_scale_f32 v64, vcc_lo, 1.0, v11, 1.0
	v_mul_f32_e32 v68, v64, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v69, -v58, v68, v64
	v_fmac_f32_e32 v68, v69, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v58, -v58, v68, v64
	v_div_fmas_f32 v58, v58, v59, v68
                                        ; implicit-def: $vgpr59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v58, v11, 1.0
	v_mul_f32_e32 v7, v7, v11
	v_mul_f32_e32 v64, v57, v11
	v_mul_f32_e32 v11, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v57, v23, v7
	v_fmac_f32_e32 v57, v6, v64
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v57, v5, v11
	v_cndmask_b32_e64 v3, -v72, v57, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, 1.0, v3
	v_mul_f32_e32 v57, 0x3f75c28f, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v57, v3, v57
	v_mul_f32_e32 v57, v3, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v57, v3, v57
	v_fmaak_f32 v68, v3, v57, 0x3d23d70a
	v_lshrrev_b32_e32 v3, 2, v63
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[57:58], v68
	v_xor_b32_e32 v3, v3, v63
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[57:58], v[57:58], 0.5, 0x3fd00000
	v_cvt_f32_f64_e32 v71, v[57:58]
	v_lshlrev_b32_e32 v57, 4, v56
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v58, 1, v3
	v_xor_b32_e32 v57, v58, v57
                                        ; implicit-def: $vgpr58
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor3_b32 v69, v57, v3, v56
	v_add_nc_u32_e32 v3, 0x587c5, v55
	v_add_nc_u32_e32 v57, v69, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v57, v57
	v_fmaak_f32 v57, 0x2f800000, v57, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f32_e32 vcc_lo, v57, v71
                                        ; implicit-def: $vgpr57
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_80
; %bb.79:                               ;   in Loop: Header=BB0_14 Depth=4
	v_dual_sub_f32 v57, 1.0, v68 :: v_dual_sub_f32 v58, 1.0, v71
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr71
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v59, null, v58, v58, v57
	v_div_scale_f32 v62, vcc_lo, v57, v58, v57
	v_rcp_f32_e32 v60, v59
	s_waitcnt_depctr 0xfff
	v_fma_f32 v61, -v59, v60, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v60, v61, v60
	v_mul_f32_e32 v61, v62, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v68, -v59, v61, v62
	v_fmac_f32_e32 v61, v68, v60
                                        ; implicit-def: $vgpr68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v59, -v59, v61, v62
                                        ; implicit-def: $vgpr62
	v_div_fmas_f32 v59, v59, v60, v61
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v57, v59, v58, v57
	v_mul_f32_e32 v58, v57, v0
	v_mul_f32_e32 v59, v57, v1
	v_mul_f32_e32 v57, v57, v2
.LBB0_80:                               ; %Flow362
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_saveexec_b32 s0, s0
	v_mov_b32_e32 v70, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_14 Depth=4
	v_div_scale_f32 v7, null, v71, v71, v68
	v_div_scale_f32 v58, vcc_lo, v68, v71, v68
	v_mov_b32_e32 v70, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v7
	v_mov_b32_e32 v64, v61
	s_waitcnt_depctr 0xfff
	v_fma_f32 v57, -v7, v11, 1.0
	v_fmac_f32_e32 v11, v57, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v57, v58, v11
	v_fma_f32 v59, -v7, v57, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v57, v59, v11
	v_fma_f32 v7, -v7, v57, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v11, v57
	v_div_fixup_f32 v57, v7, v71, v68
	v_mov_b32_e32 v11, v60
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v7, v62 :: v_dual_mul_f32 v58, v57, v0
	v_mul_f32_e32 v59, v57, v1
	v_mul_f32_e32 v57, v57, v2
.LBB0_82:                               ; %Flow363
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v60, v11 :: v_dual_mov_b32 v61, v64
	v_dual_mov_b32 v62, v7 :: v_dual_mov_b32 v71, v54
	v_dual_mov_b32 v68, v56 :: v_dual_mov_b32 v7, v37
	v_mov_b32_e32 v64, v50
.LBB0_83:                               ; %Flow364
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, -1
.LBB0_84:                               ; %Flow368
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr73
.LBB0_85:                               ; %Flow367
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_saveexec_b32 s0, s2
; %bb.86:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_14 Depth=4
	v_cmp_ne_u32_e32 vcc_lo, 1, v73
	s_and_not1_b32 s1, s1, exec_lo
	s_mov_b32 s30, exec_lo
                                        ; implicit-def: $vgpr70
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr62
                                        ; implicit-def: $vgpr61
                                        ; implicit-def: $vgpr57
                                        ; implicit-def: $vgpr59
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr69
                                        ; implicit-def: $vgpr68
                                        ; implicit-def: $vgpr71
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr64
                                        ; implicit-def: $vgpr3
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
; %bb.87:                               ; %Flow369
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s31, s1
	s_cbranch_execz .LBB0_97
; %bb.88:                               ;   in Loop: Header=BB0_14 Depth=4
	v_lshrrev_b32_e32 v3, 2, v63
	v_lshlrev_b32_e32 v7, 4, v56
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr57
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v63
	v_lshlrev_b32_e32 v11, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v7, v11, v7
	v_xor3_b32 v68, v7, v3, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v55, v68, 0x587c5
	v_cvt_f32_u32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_mul_f32_e32 v7, 0x40c90fdb, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v11, 23, v7
	v_cmp_ngt_f32_e32 vcc_lo, 0x48000000, v7
	v_and_or_b32 v3, v7, s22, 0x800000
	v_add_nc_u32_e32 v59, 0xffffff88, v11
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s33, exec_lo, s0
	s_cbranch_execz .LBB0_90
; %bb.89:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mad_u64_u32 v[57:58], null, 0xfe5163ab, v3, 0
	v_cmp_lt_u32_e64 s0, 63, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v58
	v_cndmask_b32_e64 v58, 0, 0xffffffc0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[60:61], null, 0x3c439041, v3, v[11:12]
	v_add_nc_u32_e32 v58, v58, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v58
	v_mov_b32_e32 v11, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[61:62], null, 0xdb629599, v3, v[11:12]
	v_mov_b32_e32 v11, v62
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v62, 0, 0xffffffe0, s1
	v_cndmask_b32_e64 v57, v61, v57, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[69:70], null, 0xf534ddc0, v3, v[11:12]
	v_add_nc_u32_e32 v58, v62, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s2, 31, v58
	v_mov_b32_e32 v11, v70
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[70:71], null, 0xfc2757d1, v3, v[11:12]
	v_mov_b32_e32 v11, v71
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[71:72], null, 0x4e441529, v3, v[11:12]
	v_mov_b32_e32 v11, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v62, v71, v69, s0
	v_mad_u64_u32 v[72:73], null, 0xa2f9836e, v3, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v11, v11, v58
	v_cndmask_b32_e64 v64, v72, v70, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v71, v73, v71, s0
	v_cndmask_b32_e64 v70, v70, v61, s0
	v_cndmask_b32_e64 v58, v69, v60, s0
	v_sub_nc_u32_e32 v69, 32, v11
	v_cndmask_b32_e64 v60, v64, v62, s1
	v_cndmask_b32_e64 v64, v71, v64, s1
	v_cndmask_b32_e64 v62, v62, v70, s1
	v_cndmask_b32_e64 v70, v70, v58, s1
	v_cmp_eq_u32_e64 s0, 0, v11
	v_cndmask_b32_e64 v57, v58, v57, s1
	v_cndmask_b32_e64 v64, v64, v60, s2
	v_cndmask_b32_e64 v60, v60, v62, s2
	v_cndmask_b32_e64 v62, v62, v70, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v57, v70, v57, s2
	v_alignbit_b32 v71, v64, v60, v69
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v61, v60, v62, v69
	v_alignbit_b32 v69, v62, v57, v69
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v71, v64, s0
	v_cndmask_b32_e64 v58, v61, v60, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v62, v69, v62, s0
	v_bfe_u32 v60, v11, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v61, v11, v58, 30
	v_alignbit_b32 v58, v58, v62, 30
	v_alignbit_b32 v57, v62, v57, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v64, 0, v60
	v_xor_b32_e32 v61, v61, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v58, v58, v64
	v_xor_b32_e32 v57, v57, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v69, v61
	v_min_u32_e32 v69, 32, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v62, 31, v69
	v_lshlrev_b32_e32 v71, 23, v69
	v_alignbit_b32 v61, v61, v58, v62
	v_alignbit_b32 v57, v58, v57, v62
	v_lshrrev_b32_e32 v62, 29, v11
	v_lshrrev_b32_e32 v11, 30, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v58, v61, v57, 9
	v_lshlrev_b32_e32 v62, 31, v62
	v_lshrrev_b32_e32 v61, 9, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v64, v58
	v_or_b32_e32 v70, 0.5, v62
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v64, 32, v64
	v_sub_nc_u32_e32 v70, v70, v71
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v72, 31, v64
	v_alignbit_b32 v57, v58, v57, v72
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v58, v61, v70
	v_add_lshl_u32 v61, v64, v69, 23
	v_lshrrev_b32_e32 v57, 9, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v64, 0x3fc90fda, v58
	v_sub_nc_u32_e32 v57, v57, v61
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v61, 0x3fc90fda, v58, -v64
	v_add_nc_u32_e32 v57, 0x33000000, v57
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v61, 0x33a22168, v58 :: v_dual_add_nc_u32 v58, v60, v11
	v_or_b32_e32 v57, v57, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v61, 0x3fc90fda, v57
	v_add_f32_e32 v57, v64, v61
.LBB0_90:                               ; %Flow366
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_saveexec_b32 s0, s33
	v_mul_f32_e32 v11, 0x3f22f983, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_rndne_f32_e32 v61, v11
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.91:                               ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v57, v61, 0xbfc90fda, v7
	v_cvt_i32_f32_e32 v58, v61
	v_fmac_f32_e32 v57, 0xb3a22168, v61
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v57, 0xa7c234c4, v61
; %bb.92:                               ; %_ZL3cosf.exit.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_94
; %bb.93:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mad_u64_u32 v[60:61], null, 0xfe5163ab, v3, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v61
	v_mad_u64_u32 v[61:62], null, 0x3c439041, v3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v62
	v_cndmask_b32_e64 v62, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[69:70], null, 0xdb629599, v3, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v59, v62, v59
	v_cmp_lt_u32_e64 s0, 31, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v11, v70 :: v_dual_cndmask_b32 v60, v69, v60
	v_cndmask_b32_e64 v62, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[70:71], null, 0xf534ddc0, v3, v[11:12]
	v_add_nc_u32_e32 v59, v62, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v71
	v_cmp_lt_u32_e64 s1, 31, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[71:72], null, 0xfc2757d1, v3, v[11:12]
	v_mov_b32_e32 v11, v72
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[72:73], null, 0x4e441529, v3, v[11:12]
	v_mov_b32_e32 v11, v73
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[73:74], null, 0xa2f9836e, v3, v[11:12]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v11, v72, v70, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v3, v59
	v_cndmask_b32_e32 v62, v73, v71, vcc_lo
	v_dual_cndmask_b32 v64, v74, v72 :: v_dual_cndmask_b32 v71, v71, v69
	v_cndmask_b32_e32 v59, v70, v61, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v61, v62, v11, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v62, v64, v62, s0
	v_cndmask_b32_e64 v11, v11, v71, s0
	v_sub_nc_u32_e32 v64, 32, v3
	v_cndmask_b32_e64 v70, v71, v59, s0
	v_cndmask_b32_e64 v59, v59, v60, s0
	v_cndmask_b32_e64 v62, v62, v61, s1
	v_cndmask_b32_e64 v61, v61, v11, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v70, s1
	v_cndmask_b32_e64 v59, v70, v59, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v71, v62, v61, v64
	v_alignbit_b32 v69, v61, v11, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v64, v11, v59, v64
	v_dual_cndmask_b32 v3, v71, v62 :: v_dual_cndmask_b32 v60, v69, v61
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v64, v11, vcc_lo
	v_bfe_u32 v61, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v62, v3, v60, 30
	v_alignbit_b32 v60, v60, v11, 30
	v_alignbit_b32 v11, v11, v59, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v69, 0, v61
	v_xor_b32_e32 v62, v62, v69
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v59, v60, v69
	v_xor_b32_e32 v11, v11, v69
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v64, v62
	v_min_u32_e32 v64, 32, v64
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v60, 31, v64
	v_lshlrev_b32_e32 v71, 23, v64
	v_alignbit_b32 v62, v62, v59, v60
	v_alignbit_b32 v11, v59, v11, v60
	v_lshrrev_b32_e32 v60, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v59, v62, v11, 9
	v_lshlrev_b32_e32 v60, 31, v60
	v_lshrrev_b32_e32 v62, 9, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v69, v59
	v_or_b32_e32 v70, 0.5, v60
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v69, 32, v69
	v_sub_nc_u32_e32 v70, v70, v71
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v72, 31, v69
	v_alignbit_b32 v11, v59, v11, v72
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v59, v62, v70
	v_add_lshl_u32 v62, v69, v64, 23
	v_lshrrev_b32_e32 v11, 9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v64, 0x3fc90fda, v59
	v_sub_nc_u32_e32 v11, v11, v62
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v62, 0x3fc90fda, v59, -v64
	v_add_nc_u32_e32 v11, 0x33000000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v62, 0x33a22168, v59
	v_or_b32_e32 v11, v11, v60
	v_add_nc_u32_e32 v60, v61, v3
                                        ; implicit-def: $vgpr61
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v62, 0x3fc90fda, v11
	v_add_f32_e32 v11, v64, v62
.LBB0_94:                               ; %Flow365
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_saveexec_b32 s0, s2
; %bb.95:                               ;   in Loop: Header=BB0_14 Depth=4
	v_fmamk_f32 v11, v61, 0xbfc90fda, v7
	v_cvt_i32_f32_e32 v60, v61
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0xb3a22168, v61
	v_fmac_f32_e32 v11, 0xa7c234c4, v61
; %bb.96:                               ; %_ZL3sinf.exit.i
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_cvt_f64_f32_e64 v[61:62], |v6|
	v_lshrrev_b32_e32 v71, 2, v50
	v_lshlrev_b32_e32 v72, 4, v68
	s_and_not1_b32 s30, s30, exec_lo
	v_dual_mul_f32 v75, v57, v57 :: v_dual_and_b32 v76, 1, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v79, s23, v75, 0xbab64f3b :: v_dual_lshlrev_b32 v58, 30, v58
	v_cmp_lt_f64_e32 vcc_lo, s[12:13], v[61:62]
	v_cndmask_b32_e64 v3, 1.0, 0, vcc_lo
	v_fma_f32 v61, -v3, v67, v24
	v_mul_f32_e32 v59, v3, v24
	v_fma_f32 v64, v3, v67, -v66
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v59, v3, v66, -v59
	v_mul_f32_e32 v62, v59, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v62, v61, v61
	v_fmac_f32_e32 v62, v64, v64
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x4f800000, v62
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v62
	v_cndmask_b32_e32 v62, v62, v3, vcc_lo
	v_add_nc_u32_e32 v3, 0xb0f8a, v55
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v69, v62
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v70, -1, v69
	v_add_nc_u32_e32 v73, 1, v69
	v_fma_f32 v74, -v70, v69, v62
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v77, -v73, v69, v62
	v_cmp_ge_f32_e64 s0, 0, v74
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v69, v69, v70, s0
	v_xor_b32_e32 v70, v71, v50
	v_cmp_lt_f32_e64 s0, 0, v77
	v_mul_f32_e32 v71, v11, v11
	v_fmaak_f32 v77, s24, v75, 0x3c0881c4
	v_cmp_eq_u32_e64 s2, 0, v76
	v_lshlrev_b32_e32 v74, 1, v70
	v_cndmask_b32_e64 v69, v69, v73, s0
	v_dual_fmaak_f32 v80, s23, v71, 0xbab64f3b :: v_dual_and_b32 v73, 1, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v72, v74, v72
	v_mul_f32_e32 v78, 0x37800000, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v78, v69, v78, vcc_lo
	v_xor3_b32 v69, v72, v70, v68
	v_fmaak_f32 v70, v75, v77, 0xbe2aaa9d
	v_dual_fmaak_f32 v77, v75, v79, 0x3d2aabf7 :: v_dual_lshlrev_b32 v60, 30, v60
	v_cmp_class_f32_e64 vcc_lo, v62, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v77, v75, v77, 0xbf000004 :: v_dual_add_nc_u32 v72, v69, v3
	v_and_b32_e32 v60, 0x80000000, v60
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v72, v72
	v_fmaak_f32 v72, 0x2f800000, v72, 0x2f800000
	v_mul_f32_e32 v70, v75, v70
	v_fmaak_f32 v74, s24, v71, 0x3c0881c4
	v_and_b32_e32 v58, 0x80000000, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f32_e64 s0, 0xf800000, v72
	v_fmac_f32_e32 v57, v57, v70
	v_fma_f32 v70, v75, v77, 1.0
	v_dual_sub_f32 v77, 1.0, v72 :: v_dual_fmaak_f32 v74, v71, v74, 0xbe2aaa9d
	v_mul_f32_e32 v75, 0x4f800000, v72
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v57, -v57, v70, s2
	v_cmp_gt_f32_e64 s1, 0xf800000, v77
	v_cmp_eq_u32_e64 s2, 0, v73
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v72, v72, v75, s0
	v_mul_f32_e32 v75, 0x4f800000, v77
	v_xor_b32_e32 v57, v58, v57
	v_mul_f32_e32 v74, v71, v74
	v_cndmask_b32_e64 v75, v77, v75, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v11, v74
	v_dual_fmaak_f32 v79, v71, v80, 0x3d2aabf7 :: v_dual_cndmask_b32 v62, v78, v62
	v_sqrt_f32_e32 v70, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v79, v71, v79, 0xbf000004
	v_div_scale_f32 v78, null, v62, v62, 1.0
	v_div_scale_f32 v81, vcc_lo, 1.0, v62, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v71, v71, v79, 1.0
	v_rcp_f32_e32 v80, v78
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, v71, v11, s2
	v_xor_b32_e32 v11, v60, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v74, -v78, v80, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v80, v74, v80
	v_sqrt_f32_e32 v74, v72
	v_mul_f32_e32 v77, v81, v80
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v71, -v78, v77, v81
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v73, -1, v74
	v_dual_fmac_f32 v77, v71, v80 :: v_dual_add_nc_u32 v76, 1, v74
	v_fma_f32 v58, -v73, v74, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v60, -v76, v74, v72
	v_add_nc_u32_e32 v71, -1, v70
	v_fma_f32 v78, -v78, v77, v81
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v58
	v_cndmask_b32_e64 v58, v74, v73, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v73, v78, v80, v77
	v_fma_f32 v74, -v71, v70, v75
	v_cmp_lt_f32_e32 vcc_lo, 0, v60
	v_add_nc_u32_e32 v79, 1, v70
	v_div_fixup_f32 v60, v73, v62, 1.0
	v_cndmask_b32_e32 v58, v58, v76, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v77, -v79, v70, v75
	v_cmp_ge_f32_e32 vcc_lo, 0, v74
	v_mul_f32_e32 v61, v61, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f32_e64 s2, 0, v77
	v_cndmask_b32_e32 v62, v70, v71, vcc_lo
	v_cmp_lg_f32_e32 vcc_lo, 0x7f800000, v7
	v_dual_mul_f32 v64, v64, v60 :: v_dual_mul_f32 v71, v67, v61
	v_cndmask_b32_e32 v11, 0x7fc00000, v11, vcc_lo
	v_cndmask_b32_e32 v7, 0x7fc00000, v57, vcc_lo
	v_mul_f32_e32 v57, 0x37800000, v58
	v_cndmask_b32_e64 v62, v62, v79, s2
	v_mul_f32_e32 v59, v59, v60
	v_mul_f32_e32 v60, v66, v64
	v_cmp_class_f32_e64 vcc_lo, v72, 0x260
	v_cndmask_b32_e64 v57, v58, v57, s0
	v_mul_f32_e32 v58, 0x37800000, v62
	v_mul_f32_e32 v70, v24, v59
	v_fma_f32 v60, v24, v61, -v60
	v_mul_f32_e32 v61, v61, v7
	v_cndmask_b32_e32 v57, v57, v72, vcc_lo
	v_cndmask_b32_e64 v58, v62, v58, s1
	v_fma_f32 v70, v67, v64, -v70
	v_mul_f32_e32 v60, v60, v11
	v_mul_f32_e32 v62, v59, v7
	v_fma_f32 v59, v66, v59, -v71
	v_cmp_class_f32_e64 vcc_lo, v75, 0x260
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v7, v64, v7 :: v_dual_mul_f32 v60, v57, v60
	v_dual_mov_b32 v71, v56 :: v_dual_mov_b32 v64, v37
	v_cndmask_b32_e32 v58, v58, v75, vcc_lo
	v_mul_f32_e32 v70, v70, v11
	v_dual_mul_f32 v11, v59, v11 :: v_dual_fmac_f32 v60, v57, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v57, v11 :: v_dual_fmac_f32 v60, v67, v58
	v_fmac_f32_e32 v11, v57, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v60, v60
	v_fmac_f32_e32 v11, v24, v58
	v_mul_f32_e32 v72, v57, v70
	v_mov_b32_e32 v70, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v72, v57, v61
	v_fmac_f32_e32 v72, v66, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v72, v72
	v_fmac_f32_e32 v7, v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, 0x4f800000, v7
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
	v_cndmask_b32_e32 v7, v7, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v24, v7
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v57, -1, v24
	v_add_nc_u32_e32 v58, 1, v24
	v_fma_f32 v59, -v57, v24, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v61, -v58, v24, v7
	v_cmp_ge_f32_e64 s0, 0, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v24, v24, v57, s0
	v_cmp_lt_f32_e64 s0, 0, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, v24, v58, s0
	v_mul_f32_e32 v57, 0x37800000, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v24, v24, v57, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x260
	v_cndmask_b32_e32 v7, v24, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v24, null, v7, v7, 1.0
	v_div_scale_f32 v59, vcc_lo, 1.0, v7, 1.0
	v_rcp_f32_e32 v57, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v58, -v24, v57, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v57, v58, v57
	v_mul_f32_e32 v58, v59, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v61, -v24, v58, v59
	v_fmac_f32_e32 v58, v61, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v24, v58, v59
	v_mov_b32_e32 v59, v1
	v_div_fmas_f32 v24, v24, v57, v58
	v_dual_mov_b32 v57, v2 :: v_dual_mov_b32 v58, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v24, v7, 1.0
	v_mov_b32_e32 v7, v54
	v_mul_f32_e32 v61, v72, v24
	v_mul_f32_e32 v62, v60, v24
	v_mul_f32_e32 v60, v11, v24
.LBB0_97:                               ; %Flow370
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s31
	s_and_saveexec_b32 s0, s30
	s_cbranch_execz .LBB0_99
; %bb.98:                               ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mul_f32 v3, v45, v23 :: v_dual_mov_b32 v70, 0
	v_add_f32_e32 v7, v6, v6
	v_dual_add_f32 v11, v23, v23 :: v_dual_mov_b32 v58, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v3, v44, v6 :: v_dual_mov_b32 v68, v54
	v_dual_add_f32 v6, v5, v5 :: v_dual_mov_b32 v57, v2
	v_dual_mov_b32 v64, v63 :: v_dual_fmac_f32 v3, v46, v5
	v_mov_b32_e32 v59, v1
	v_mov_b32_e32 v69, v56
	v_mov_b32_e32 v71, v37
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v61, -v7, v3, v44
	v_fma_f32 v62, -v11, v3, v45
	v_fma_f32 v60, -v6, v3, v46
	v_mov_b32_e32 v7, v50
	v_mov_b32_e32 v3, v55
.LBB0_99:                               ; %Flow371
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v11, v4 :: v_dual_mov_b32 v50, v7
	v_mov_b32_e32 v63, v64
	v_mov_b32_e32 v55, v3
.LBB0_100:                              ; %Flow374
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s29
	v_dual_mov_b32 v37, v71 :: v_dual_mov_b32 v54, v68
	v_mov_b32_e32 v56, v69
	v_mov_b32_e32 v64, v65
.LBB0_101:                              ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_i32_e32 vcc_lo, 2, v70
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, v55 :: v_dual_mov_b32 v4, v37
	v_dual_mov_b32 v5, v50 :: v_dual_mov_b32 v0, v56
	v_mov_b32_e32 v2, v54
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_14
; %bb.102:                              ; %LeafBlock357
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s28
	v_cmp_ne_u32_e32 vcc_lo, 0, v70
	v_dual_mov_b32 v1, v55 :: v_dual_mov_b32 v4, v37
	v_dual_mov_b32 v5, v50 :: v_dual_mov_b32 v0, v56
	v_mov_b32_e32 v2, v54
	s_or_b32 s27, vcc_lo, s27
	s_mov_b32 s28, 0
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_14
; %bb.103:                              ; %_Z8radiancePK6SpheremRK3RayiP12hiprandState.exit
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	v_fmac_f32_e32 v36, v26, v38
	v_fmac_f32_e32 v35, v26, v40
	v_fmac_f32_e32 v34, v26, v39
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[16:17], s[8:9]
	s_cbranch_scc1 .LBB0_106
; %bb.104:                              ;   in Loop: Header=BB0_5 Depth=3
	v_dual_mov_b32 v4, v56 :: v_dual_mov_b32 v5, v54
	s_branch .LBB0_5
.LBB0_105:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v56, v4 :: v_dual_mov_b32 v35, 0
	v_mov_b32_e32 v54, v5
	v_mov_b32_e32 v36, 0
.LBB0_106:                              ; %Flow396
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v36
	s_xor_b32 s0, s26, -1
	s_mov_b32 s14, 0
	s_mov_b32 s15, 0x3ff80000
	s_mov_b32 s26, 0
	v_cndmask_b32_e32 v0, 1.0, v36, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v35
	v_cndmask_b32_e32 v1, 1.0, v35, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, 0x3e800000, v1 :: v_dual_cndmask_b32 v2, 1.0, v34
	v_mul_f32_e32 v0, 0x3e800000, v0
	v_cmp_ngt_f32_e32 vcc_lo, 0, v36
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v35
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, v0, v8 :: v_dual_cndmask_b32 v1, 0, v1
	v_mul_f32_e32 v2, 0x3e800000, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0, v34
	v_dual_add_f32 v9, v1, v9 :: v_dual_cndmask_b32 v2, 0, v2
	s_and_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v10, v2, v10
	global_store_b96 v[13:14], v[8:10], off
	s_cbranch_vccnz .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v4, v56 :: v_dual_mov_b32 v5, v54
	s_branch .LBB0_3
.LBB0_108:                              ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s11, 0x3ff80000
	s_and_b32 vcc_lo, exec_lo, s25
	s_mov_b32 s0, 0
	s_cbranch_vccz .LBB0_2
.LBB0_109:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13render_kernelPK6SpheremP3Vecmmi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 90
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13render_kernelPK6SpheremP3Vecmmi, .Lfunc_end0-_Z13render_kernelPK6SpheremP3Vecmmi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13520
; NumSgprs: 38
; NumVgprs: 90
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 90
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13render_kernelPK6SpheremP3Vecmmi
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z13render_kernelPK6SpheremP3Vecmmi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     90
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
