
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectNhBytes( unsigned char* color, int colorLen0,  unsigned char* bytes, int bytesLen0, int index, int itemSize, int itemsCount, int width, int height, int n, int nh);
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectColorBytes( unsigned char* bytes, int bytesLen0,  unsigned char* color, int colorLen0, int itemSize, int itemsCount, int width, int height, int n, int nh);
// MyCudafy.CudafyFilter
extern "C" __global__ void Merge( unsigned char* a, int aLen0,  unsigned char* b, int bLen0, int i, int parity, int ceilingItemSize, int itemSize, int itemsCount);

// MyCudafy.CudafyFilter
__constant__ unsigned char _color[144];
#define _colorLen0 144
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectNhBytes( unsigned char* color, int colorLen0,  unsigned char* bytes, int bytesLen0, int index, int itemSize, int itemsCount, int width, int height, int n, int nh)
{
	for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < itemsCount; i += blockDim.x * gridDim.x)
	{
		int num = i / (width - 2 * nh) + nh;
		int num2 = i % (width - 2 * nh) + nh;
		color[(num * width + num2)] = bytes[(i * itemSize + index)];
	}
}
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectColorBytes( unsigned char* bytes, int bytesLen0,  unsigned char* color, int colorLen0, int itemSize, int itemsCount, int width, int height, int n, int nh)
{
	for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n * n * itemsCount; i += blockDim.x * gridDim.x)
	{
		int num = i / (n * n);
		int num2 = i % (n * n);
		int num3 = num2 / n;
		int num4 = num2 % n;
		int num5 = num / (width - 2 * nh) + num3;
		int num6 = num % (width - 2 * nh) + num4;
		bytes[(i)] = color[(num5 * width + num6)];
	}
}
// MyCudafy.CudafyFilter
extern "C" __global__ void Merge( unsigned char* a, int aLen0,  unsigned char* b, int bLen0, int i, int parity, int ceilingItemSize, int itemSize, int itemsCount)
{
	for (int j = 0; j < itemsCount * ((1 << (ceilingItemSize - i - 1 & 31)) + parity); j++)
	{
		int num = j / ((1 << (ceilingItemSize - i - 1 & 31)) + parity);
		int num2 = j % ((1 << (ceilingItemSize - i - 1 & 31)) + parity);
		int num3 = num * itemSize + (num2 << (i + 1 & 31)) - (parity << (i & 31));
		int num4 = min(max(num * itemSize, num3), (num + 1) * itemSize);
		int num5 = min(max(num * itemSize, num3 + (1 << (i & 31))), (num + 1) * itemSize);
		int num6 = min(max(num * itemSize, num3 + (2 << (i & 31))), (num + 1) * itemSize);
		int k = num5 - num4;
		int l = num6 - num5;
		int num7 = num6 - num4;
		while (k > 0 && l > 0)
		{
			if (a[(num4 + k - 1)] > a[(num5 + l - 1)])
			{
				b[(num4 + --num7)] = a[(num4 + --k)];
			}
			else
			{
				b[(num4 + --num7)] = a[(num5 + --l)];
			}
		}
		while (k > 0)
		{
			b[(num4 + --num7)] = a[(num4 + --k)];
		}
		while (l > 0)
		{
			b[(num4 + --num7)] = a[(num5 + --l)];
		}
	}
}

	.file	"tmpxft_002bbbe1_00000000-6_CUDAFYSOURCETEMP.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z44__device_stub__Z13SelectNhBytesPhiS_iiiiiiiiPhiS_iiiiiiii
	.type	_Z44__device_stub__Z13SelectNhBytesPhiS_iiiiiiiiPhiS_iiiiiiii, @function
_Z44__device_stub__Z13SelectNhBytesPhiS_iiiiiiiiPhiS_iiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 216
	leaq	SelectNhBytes(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 224
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z44__device_stub__Z13SelectNhBytesPhiS_iiiiiiiiPhiS_iiiiiiii, .-_Z44__device_stub__Z13SelectNhBytesPhiS_iiiiiiiiPhiS_iiiiiiii
	.globl	SelectNhBytes
	.type	SelectNhBytes, @function
SelectNhBytes:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z13SelectNhBytesPhiS_iiiiiiiiPhiS_iiiiiiii
	.cfi_endproc
.LFE2033:
	.size	SelectNhBytes, .-SelectNhBytes
	.globl	_Z46__device_stub__Z16SelectColorBytesPhiS_iiiiiiiPhiS_iiiiiii
	.type	_Z46__device_stub__Z16SelectColorBytesPhiS_iiiiiiiPhiS_iiiiiii, @function
_Z46__device_stub__Z16SelectColorBytesPhiS_iiiiiiiPhiS_iiiiiii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 216
	leaq	SelectColorBytes(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z46__device_stub__Z16SelectColorBytesPhiS_iiiiiiiPhiS_iiiiiii, .-_Z46__device_stub__Z16SelectColorBytesPhiS_iiiiiiiPhiS_iiiiiii
	.globl	SelectColorBytes
	.type	SelectColorBytes, @function
SelectColorBytes:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z16SelectColorBytesPhiS_iiiiiiiPhiS_iiiiiii
	.cfi_endproc
.LFE2035:
	.size	SelectColorBytes, .-SelectColorBytes
	.globl	_Z33__device_stub__Z5MergePhiS_iiiiiiPhiS_iiiiii
	.type	_Z33__device_stub__Z5MergePhiS_iiiiiiPhiS_iiiiii, @function
_Z33__device_stub__Z5MergePhiS_iiiiiiPhiS_iiiiii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 200
	leaq	Merge(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 208
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z33__device_stub__Z5MergePhiS_iiiiiiPhiS_iiiiii, .-_Z33__device_stub__Z5MergePhiS_iiiiiiPhiS_iiiiii
	.globl	Merge
	.type	Merge, @function
Merge:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z5MergePhiS_iiiiiiPhiS_iiiiii
	.cfi_endproc
.LFE2037:
	.size	Merge, .-Merge
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Merge"
.LC1:
	.string	"SelectColorBytes"
.LC2:
	.string	"SelectNhBytes"
.LC3:
	.string	"_color"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	Merge(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	SelectColorBytes(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	SelectNhBytes(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$144, %r9d
	leaq	_ZL6_color(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL6_color
	.comm	_ZL6_color,144,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

// MyCudafy.CudafyFilter
extern "C" __global__ void SelectNhBytes( unsigned char* color, int colorLen0,  unsigned char* bytes, int bytesLen0, int index, int itemSize, int itemsCount, int width, int height, int n, int nh);
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectColorBytes( unsigned char* bytes, int bytesLen0,  unsigned char* color, int colorLen0, int itemSize, int itemsCount, int width, int height, int n, int nh);
// MyCudafy.CudafyFilter
extern "C" __global__ void Merge( unsigned char* a, int aLen0,  unsigned char* b, int bLen0, int i, int parity, int ceilingItemSize, int itemSize, int itemsCount);

// MyCudafy.CudafyFilter
__constant__ unsigned char _color[144];
#define _colorLen0 144
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectNhBytes( unsigned char* color, int colorLen0,  unsigned char* bytes, int bytesLen0, int index, int itemSize, int itemsCount, int width, int height, int n, int nh)
{
	for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < itemsCount; i += blockDim.x * gridDim.x)
	{
		int num = i / (width - 2 * nh) + nh;
		int num2 = i % (width - 2 * nh) + nh;
		color[(num * width + num2)] = bytes[(i * itemSize + index)];
	}
}
// MyCudafy.CudafyFilter
extern "C" __global__ void SelectColorBytes( unsigned char* bytes, int bytesLen0,  unsigned char* color, int colorLen0, int itemSize, int itemsCount, int width, int height, int n, int nh)
{
	for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n * n * itemsCount; i += blockDim.x * gridDim.x)
	{
		int num = i / (n * n);
		int num2 = i % (n * n);
		int num3 = num2 / n;
		int num4 = num2 % n;
		int num5 = num / (width - 2 * nh) + num3;
		int num6 = num % (width - 2 * nh) + num4;
		bytes[(i)] = color[(num5 * width + num6)];
	}
}
// MyCudafy.CudafyFilter
extern "C" __global__ void Merge( unsigned char* a, int aLen0,  unsigned char* b, int bLen0, int i, int parity, int ceilingItemSize, int itemSize, int itemsCount)
{
	for (int j = 0; j < itemsCount * ((1 << (ceilingItemSize - i - 1 & 31)) + parity); j++)
	{
		int num = j / ((1 << (ceilingItemSize - i - 1 & 31)) + parity);
		int num2 = j % ((1 << (ceilingItemSize - i - 1 & 31)) + parity);
		int num3 = num * itemSize + (num2 << (i + 1 & 31)) - (parity << (i & 31));
		int num4 = min(max(num * itemSize, num3), (num + 1) * itemSize);
		int num5 = min(max(num * itemSize, num3 + (1 << (i & 31))), (num + 1) * itemSize);
		int num6 = min(max(num * itemSize, num3 + (2 << (i & 31))), (num + 1) * itemSize);
		int k = num5 - num4;
		int l = num6 - num5;
		int num7 = num6 - num4;
		while (k > 0 && l > 0)
		{
			if (a[(num4 + k - 1)] > a[(num5 + l - 1)])
			{
				b[(num4 + --num7)] = a[(num4 + --k)];
			}
			else
			{
				b[(num4 + --num7)] = a[(num5 + --l)];
			}
		}
		while (k > 0)
		{
			b[(num4 + --num7)] = a[(num4 + --k)];
		}
		while (l > 0)
		{
			b[(num4 + --num7)] = a[(num5 + --l)];
		}
	}
}

	.text
	.file	"CUDAFYSOURCETEMP.hip"
	.globl	__device_stub__SelectNhBytes    # -- Begin function __device_stub__SelectNhBytes
	.type	__device_stub__SelectNhBytes,@function
__device_stub__SelectNhBytes:           # @__device_stub__SelectNhBytes
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$SelectNhBytes, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__SelectNhBytes, .Lfunc_end0-__device_stub__SelectNhBytes
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__SelectColorBytes # -- Begin function __device_stub__SelectColorBytes
	.type	__device_stub__SelectColorBytes,@function
__device_stub__SelectColorBytes:        # @__device_stub__SelectColorBytes
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$SelectColorBytes, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__SelectColorBytes, .Lfunc_end1-__device_stub__SelectColorBytes
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__Merge            # -- Begin function __device_stub__Merge
	.type	__device_stub__Merge,@function
__device_stub__Merge:                   # @__device_stub__Merge
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$Merge, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__Merge, .Lfunc_end2-__device_stub__Merge
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$SelectNhBytes, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$SelectColorBytes, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$Merge, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$_color, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$144, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_color,@object                  # @_color
	.local	_color
	.comm	_color,144,16
	.type	SelectNhBytes,@object           # @SelectNhBytes
	.section	.rodata,"a",@progbits
	.globl	SelectNhBytes
	.p2align	3, 0x0
SelectNhBytes:
	.quad	__device_stub__SelectNhBytes
	.size	SelectNhBytes, 8

	.type	SelectColorBytes,@object        # @SelectColorBytes
	.globl	SelectColorBytes
	.p2align	3, 0x0
SelectColorBytes:
	.quad	__device_stub__SelectColorBytes
	.size	SelectColorBytes, 8

	.type	Merge,@object                   # @Merge
	.globl	Merge
	.p2align	3, 0x0
Merge:
	.quad	__device_stub__Merge
	.size	Merge, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"SelectNhBytes"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"SelectColorBytes"
	.size	.L__unnamed_2, 17

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"Merge"
	.size	.L__unnamed_3, 6

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_color"
	.size	.L__unnamed_4, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__SelectNhBytes
	.addrsig_sym __device_stub__SelectColorBytes
	.addrsig_sym __device_stub__Merge
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _color
	.addrsig_sym SelectNhBytes
	.addrsig_sym SelectColorBytes
	.addrsig_sym Merge
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	SelectNhBytes           ; -- Begin function SelectNhBytes
	.globl	SelectNhBytes
	.p2align	8
	.type	SelectNhBytes,@function
SelectNhBytes:                          ; @SelectNhBytes
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x44
	s_load_b128 s[4:7], s[0:1], 0x1c
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s8, 0xffff
	s_mov_b32 s8, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s10, s[0:1], 0x34
	s_load_b32 s15, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s8, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s11, s7, s8
	s_ashr_i32 s12, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s11, s12
	s_xor_b32 s13, s8, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s13
	s_sub_i32 s2, 0, s13
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_mul_i32 s1, s15, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, v2
	v_mad_u64_u32 v[2:3], null, v1, s5, s[4:5]
	s_mov_b32 s4, 0
	s_mul_i32 s5, s1, s5
	v_add_nc_u32_e32 v0, v0, v4
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s8, v2
	v_add_nc_u32_e32 v2, s5, v2
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_u8 v5, v[3:4], off
	v_ashrrev_i32_e32 v3, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v3
	v_xor_b32_e32 v4, v4, v3
	v_xor_b32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v4, v0
	v_mul_lo_u32 v7, v6, s13
	v_add_nc_u32_e32 v8, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v7
	v_subrev_nc_u32_e32 v7, s13, v4
	v_cmp_le_u32_e32 vcc_lo, s13, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s13, v4
	v_cndmask_b32_e32 v4, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s10, v3
	v_mul_lo_u32 v3, v3, s11
	v_mul_lo_u32 v4, v4, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add3_u32 v3, s10, v1, v3
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_cmp_le_i32_e32 vcc_lo, s6, v1
	v_add_co_u32 v3, s0, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt vmcnt(0)
	global_store_b8 v[3:4], v5, off
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow40
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel SelectNhBytes
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	SelectNhBytes, .Lfunc_end0-SelectNhBytes
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	SelectColorBytes        ; -- Begin function SelectColorBytes
	.globl	SelectColorBytes
	.p2align	8
	.type	SelectColorBytes,@function
SelectColorBytes:                       ; @SelectColorBytes
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x44
	s_load_b64 s[2:3], s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x20
	s_add_u32 s6, s0, 56
	s_addc_u32 s7, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s8, 0xffff
	s_mul_i32 s10, s2, s2
	v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
	s_mul_i32 s4, s10, s4
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_lshl_b32 s3, s3, 1
	s_ashr_i32 s11, s2, 31
	s_sub_i32 s3, s5, s3
	s_add_i32 s8, s2, s11
	s_ashr_i32 s12, s3, 31
	s_xor_b32 s13, s8, s11
	s_add_i32 s9, s3, s12
	v_cvt_f32_u32_e32 v0, s10
	s_xor_b32 s14, s9, s12
	v_cvt_f32_u32_e32 v2, s13
	v_cvt_f32_u32_e32 v3, s14
	s_load_b32 s17, s[6:7], 0x0
	v_rcp_iflag_f32_e32 v0, v0
	s_sub_i32 s15, 0, s10
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_sub_i32 s6, 0, s13
	s_sub_i32 s7, 0, s14
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v0, v0
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s15, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v5, s6, v2
	v_mul_lo_u32 v6, s7, v3
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s17, s16
	s_mov_b32 s16, 0
	v_mul_hi_u32 v4, v0, v4
	v_mul_hi_u32 v5, v2, v5
	v_mul_hi_u32 v6, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v3, v6
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v8, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v8
	v_xor_b32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v0
	v_mul_lo_u32 v6, v5, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v6
	v_subrev_nc_u32_e32 v6, s10, v4
	v_cmp_le_u32_e32 vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 1, v5
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v4
	v_add_nc_u32_e32 v6, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v5, v6, vcc_lo
	v_xor_b32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v4, v8
	v_mad_u64_u32 v[5:6], null, s15, v7, v[1:2]
	v_ashrrev_i32_e32 v6, 31, v7
	v_mul_lo_u32 v9, v7, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v7, v6
	v_ashrrev_i32_e32 v10, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v7, v7, v6
	v_sub_nc_u32_e32 v9, v10, v9
	v_xor_b32_e32 v6, s12, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v11, v7, v3
	v_add_nc_u32_e32 v9, v1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v10
	v_xor_b32_e32 v10, s11, v10
	v_mul_lo_u32 v13, v11, s14
	v_add_nc_u32_e32 v14, 1, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v12, v9, v2
	v_sub_nc_u32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, v12, s13
	v_add_nc_u32_e32 v13, 1, v12
	v_cmp_le_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e32 v11, v11, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v15
	v_subrev_nc_u32_e32 v14, s14, v7
	v_subrev_nc_u32_e32 v15, s13, v9
	v_cmp_le_u32_e64 s0, s13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v7, v14, vcc_lo
	v_cndmask_b32_e64 v12, v12, v13, s0
	v_add_nc_u32_e32 v13, 1, v11
	v_cndmask_b32_e64 v9, v9, v15, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s14, v7
	v_dual_cndmask_b32 v7, v11, v13 :: v_dual_add_nc_u32 v14, 1, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s13, v9
	v_xor_b32_e32 v7, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v12, v14, vcc_lo
	v_sub_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v10
	v_mul_lo_u32 v11, v6, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v9, v10
	v_add_nc_u32_e32 v10, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v10, s5, v[4:5]
	v_mul_lo_u32 v4, v9, s2
	v_sub_nc_u32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v6, v4
	v_sub_nc_u32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v5, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_u8 v6, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s6, v1
	v_add_nc_u32_e32 v1, s1, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v8, vcc_lo
	v_cmp_le_i32_e64 s0, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s16, s0, s16
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v6, off
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow51
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel SelectColorBytes
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	SelectColorBytes, .Lfunc_end1-SelectColorBytes
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 792
; NumSgprs: 20
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	Merge                   ; -- Begin function Merge
	.globl	Merge
	.p2align	8
	.type	Merge,@function
Merge:                                  ; @Merge
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x1c
	s_load_b32 s2, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_not_b32 s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s6
	s_lshl_b32 s6, 1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s6, s5
	s_mul_i32 s8, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB2_12
; %bb.1:                                ; %.lr.ph102
	s_ashr_i32 s9, s6, 31
	s_lshl_b32 s11, s5, s4
	s_add_i32 s2, s6, s9
	s_add_i32 s15, s4, 1
	s_xor_b32 s10, s2, s9
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s5, 0, s10
	s_lshl_b32 s12, 1, s4
	s_lshl_b32 s13, 2, s4
	s_and_b32 s15, s15, 31
	v_rcp_iflag_f32_e32 v0, v0
	s_mov_b32 s14, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_readfirstlane_b32 s16, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s16
	s_mul_hi_u32 s4, s16, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s16, s16, s4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s17, s2, -1
	s_addc_u32 s18, s3, -1
	s_add_u32 s19, s0, -1
	s_addc_u32 s20, s1, -1
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
                                        ;     Child Loop BB2_7 Depth 2
                                        ;     Child Loop BB2_10 Depth 2
	s_mul_hi_u32 s0, s14, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s10
	s_add_i32 s4, s0, 1
	s_sub_i32 s1, s14, s1
	s_sub_i32 s5, s1, s10
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s4, s0
	s_cselect_b32 s1, s5, s1
	s_add_i32 s4, s0, 1
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s4, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, s9
	s_sub_i32 s0, s0, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s6
	s_mul_i32 s0, s0, s7
	s_sub_i32 s1, s14, s1
	s_sub_i32 s4, s0, s11
	s_lshl_b32 s1, s1, s15
	s_add_i32 s1, s4, s1
	s_add_i32 s4, s0, s7
	s_max_i32 s5, s0, s1
	s_add_i32 s21, s1, s12
	s_add_i32 s1, s1, s13
	s_min_i32 s23, s5, s4
	s_max_i32 s5, s0, s21
	s_max_i32 s0, s0, s1
	s_min_i32 s22, s5, s4
	s_min_i32 s0, s0, s4
	s_sub_i32 s25, s22, s23
	s_sub_i32 s21, s0, s22
	s_sub_i32 s24, s0, s23
	s_min_i32 s1, s25, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s1, 1
	s_cbranch_scc1 .LBB2_5
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_ashr_i32 s0, s23, 31
	s_ashr_i32 s1, s24, 31
	s_add_u32 s4, s23, s24
	s_addc_u32 s1, s0, s1
	s_add_u32 s0, s19, s4
	s_addc_u32 s1, s20, s1
.LBB2_4:                                ; %.lr.ph
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s4, s25, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s5, s4, 31
	s_add_u32 s4, s17, s4
	s_addc_u32 s5, s18, s5
	s_add_i32 s26, s21, s22
	global_load_u8 v1, v0, s[4:5]
	s_ashr_i32 s27, s26, 31
	s_add_u32 s4, s17, s26
	s_addc_u32 s5, s18, s27
	s_add_i32 s24, s24, -1
	global_load_u8 v2, v0, s[4:5]
	s_add_i32 s4, s21, -1
	s_add_i32 s5, s25, -1
	s_add_i32 s26, s4, s22
	s_add_i32 s29, s5, s23
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s27, v1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s28, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_gt_u32 s27, s28
	s_cselect_b32 s26, s29, s26
	s_cselect_b32 s25, s5, s25
	s_cselect_b32 s21, s21, s4
	s_ashr_i32 s5, s26, 31
	s_add_u32 s4, s2, s26
	s_addc_u32 s5, s3, s5
	s_cmp_eq_u32 s25, 0
	global_load_u8 v1, v0, s[4:5]
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s21, 0
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s5
	s_waitcnt vmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_add_u32 s0, s0, -1
	s_addc_u32 s1, s1, -1
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB2_4
.LBB2_5:                                ; %.preheader85
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_cmp_lt_i32 s25, 1
	s_cbranch_scc1 .LBB2_8
; %bb.6:                                ; %.lr.ph95.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_ashr_i32 s4, s23, 31
	s_ashr_i32 s0, s24, 31
	s_add_u32 s1, s23, s24
	s_addc_u32 s5, s4, s0
	s_add_u32 s0, s19, s1
	s_addc_u32 s1, s20, s5
	s_ashr_i32 s5, s25, 31
	s_add_u32 s26, s23, s25
	s_addc_u32 s5, s4, s5
	s_add_u32 s4, s17, s26
	s_addc_u32 s5, s18, s5
	s_add_i32 s25, s25, 1
.LBB2_7:                                ; %.lr.ph95
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v1, v0, s[4:5]
	s_add_i32 s24, s24, -1
	s_waitcnt vmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_add_u32 s0, s0, -1
	s_addc_u32 s1, s1, -1
	s_add_u32 s4, s4, -1
	s_addc_u32 s5, s5, -1
	s_add_i32 s25, s25, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s25, 2
	s_cbranch_scc0 .LBB2_7
.LBB2_8:                                ; %.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_cmp_lt_i32 s21, 1
	s_cbranch_scc1 .LBB2_11
; %bb.9:                                ; %.lr.ph99.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_ashr_i32 s4, s22, 31
	s_ashr_i32 s0, s23, 31
	s_ashr_i32 s1, s24, 31
	s_add_u32 s5, s23, s24
	s_addc_u32 s1, s0, s1
	s_add_u32 s0, s19, s5
	s_addc_u32 s1, s20, s1
	s_ashr_i32 s5, s21, 31
	s_add_u32 s22, s22, s21
	s_addc_u32 s5, s4, s5
	s_add_u32 s4, s17, s22
	s_addc_u32 s5, s18, s5
	s_add_i32 s21, s21, 1
.LBB2_10:                               ; %.lr.ph99
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v1, v0, s[4:5]
	s_waitcnt vmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_add_u32 s0, s0, -1
	s_addc_u32 s1, s1, -1
	s_add_u32 s4, s4, -1
	s_addc_u32 s5, s5, -1
	s_add_i32 s21, s21, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s21, 1
	s_cbranch_scc1 .LBB2_10
.LBB2_11:                               ; %._crit_edge
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s14, s8
	s_cbranch_scc0 .LBB2_2
.LBB2_12:                               ; %._crit_edge103
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel Merge
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	Merge, .Lfunc_end2-Merge
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 808
; NumSgprs: 32
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	_color                  ; @_color
	.type	_color,@object
	.section	.bss,"aw",@nobits
	.globl	_color
	.p2align	4, 0x0
_color:
	.zero	144
	.size	_color, 144

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           SelectNhBytes
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         SelectNhBytes.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           SelectColorBytes
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         SelectColorBytes.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           Merge
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         Merge.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
