#include <iostream>
#include <ctime>
#include <curand.h>
using namespace std;

#define n 1048576*2 // Size of array M (should be a power of 2

// Function that catches the error
void testCUDA(cudaError_t error, const char *file, int line)  {
	if (error != cudaSuccess) {
	   printf("There is an error in file %s at line %d\n", file, line);
       exit(EXIT_FAILURE);
	}
}
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))

//Sort initialization #1 : with multiple blocks ---> NOT OPTIMAL
__global__
void sort_array(unsigned int *M){
	int index = blockIdx.x * 2;
	if(M[index] > M[index+1]){
		int swap = M[index];
		M[index] = M[index+1];
		M[index+1] = swap;
	}
}

//Sort initialization #2 : with multiple blocks ---> OPTIMAL (contiguity)
__global__
void sort_array_2(unsigned int *M){
	int stride = min(n/2,1024)*2;
	int index = blockIdx.x * blockDim.x * 2 ;
	for(int i=threadIdx.x*2;i<blockDim.x*2;i+=stride){
		if(M[index+i] > M[index+i+1]){
			int swap = M[index+i];
			M[index+i] = M[index+i+1];
			M[index+i+1] = swap;
		}
	}
}

//Merge path
__global__
void merge_array(unsigned int *m,unsigned int *M,int array_size){
  int index_array = blockIdx.x * array_size;
	int stride = blockDim.x;
	for(int i=threadIdx.x;i<array_size;i+=stride){

	  int size_A = array_size / 2;
	  int size_B = array_size / 2;
	  int offset;

	  int K[2],P[2],Q[2];
	  if( i> size_A ){
	      K[0] = P[1] = i - size_A;
	      K[1] = P[0] = size_A;
	    }
	    else{
	      K[0] = P[1] = 0;
	      K[1] = P[0] = i;
	    }
	    while(true){
	        offset = abs(K[1]-P[1])/2;
	        Q[0] = K[0] + offset;
	        Q[1] = K[1] - offset;
	    if (Q[1] >= 0 && Q[0] <= size_B && (Q[1] == size_A || Q[0] == 0 || M[index_array+Q[1]]>M[index_array+size_A+Q[0]-1])){
	      if(Q[0] == size_B || Q[1] == 0 || M[index_array+Q[1]-1] <= M[index_array+size_A+Q[0]]){
	        if(Q[1] < size_A && (Q[0] == size_B || M[index_array+Q[1]] <= M[index_array+size_A+Q[0]])){
	        m[index_array+i] = M[index_array+Q[1]];
	        }
	        else{
	          m[index_array+i] = M[index_array+size_A+Q[0]];
	        }
	        break;
	      }
	      else {
	        K[0] = Q[0] + 1;
	        K[1] = Q[1] - 1;
	      }
	    }
	    else{
	      P[0] = Q[0] - 1;
	      P[1] = Q[1] + 1;
	    }
		}
	}
	__syncthreads();
}

//Function to Sanity check if the array is sorted or not (CPU)
void sanity_check(unsigned int *M){
  bool sorted = true;
  for (int i = 1; i < n; i++){
      if(M[i]<M[i-1]){
        sorted = false;
				cout << "SORTED = FALSE for i =" << i << endl;
				cout << "M[i-1]=" << M[i-1] << endl;
				cout << "M[i]=" << M[i] << endl;
				break;
      }
    }
  if(sorted==true){
    cout << "*** Is array sorted : True " << endl;
  }
  else{
      cout << "*** Is array sorted : False " << endl;
  }
}

int main () {


// *** Defining variables ***
  unsigned int *M_dev, *M_dev_next;	//Array and its copy to scale merge path procedure
	curandGenerator_t G; 							//Curand RNG
	clock_t timer; 										//Timer for CPU
  cudaEvent_t start,stop;						//Timer for GPU
	float elapsedTime;								//Timer for GPU


// *** Allocating memory ***
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
  testCUDA(cudaMallocManaged(&M_dev, n*sizeof(unsigned int)));
	curandCreateGenerator(&G,CURAND_RNG_PSEUDO_DEFAULT);
	testCUDA(cudaMallocManaged(&M_dev_next, n*sizeof(unsigned int)));


// *** Performing custom random array generation ***
  cout << "---- GENERATING RANDOM ARRAY WITH CURAND ----" << endl;
  cudaEventRecord(start,0);
	curandGenerate(G, M_dev, n); //Generate n pseudo random unsigned int on device
  cudaEventRecord(stop,0);
  cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsedTime,start,stop);
  cout << "*** Length of array created : " << n << endl;
  cout << "*** Execution time : " << elapsedTime << " ms" << endl;


// *** Performing sort initialization ***
  cout << "\n---- SORTING ARRAYS OF LENGTH 2 TO INITIALIZE MERGE PATH ----" << endl;
  cudaEventRecord(start,0);
	//sort_array<<<n/2,1>>>(M_dev);
	sort_array_2<<<n/(2*min(n/2,1024)),min(n/2,1024)>>>(M_dev);
	cudaEventRecord(stop,0);
  cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsedTime,start,stop);
	cout << "*** Execution time : " << elapsedTime << " ms" << endl;


// *** Performing merge path***
	cout << "\n---- MERGING SORTED ARRAYS BY MERGE PATH ----" << endl;
	cudaEventRecord(start,0);
  int nb_arrays = n/2;
  int array_size = 2;
  while (nb_arrays!=1){
		nb_arrays /= 2; //nb of array to merge on next merge_path
    array_size *= 2; //size of arrays on next merge_path
    merge_array<<<nb_arrays,min(array_size,1024)>>>(M_dev_next,M_dev,array_size);
		M_dev = M_dev_next;
		testCUDA(cudaMallocManaged(&M_dev_next, n*sizeof(unsigned int)));
  }
  cudaEventRecord(stop,0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&elapsedTime,start,stop);
  cout << "*** Execution time : " << elapsedTime << " ms" << endl;


//*** Sanity check ***
  unsigned int *M_host = (unsigned int*)malloc(n*sizeof(unsigned int));
  testCUDA(cudaMemcpy(M_host, M_dev, n*sizeof(unsigned int), cudaMemcpyDeviceToHost));

	/*
	//Code to vizualize array sorted
  for(int i=0;i<n;i++){
      cout <<  M_host[i] << "\t";
		}
	*/

	cout << "\n---- SANITY CHECK ----" << endl;
	timer = clock();
	sanity_check(M_host);
	timer = clock() - timer;
	cout << "*** Execution time : " << (float)timer/(CLOCKS_PER_SEC/1000) << " ms" << endl;


//*** free memory on device and host ***
	free(M_host);
  cudaEventDestroy(start);
	cudaEventDestroy(stop);
	cudaFree(M_dev);
	cudaFree(M_dev_next);


  return EXIT_SUCCESS;
}

	.file	"tmpxft_0025d71f_00000000-6_merge_sort_path.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4302:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4302:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"There is an error in file %s at line %d\n"
	.text
	.globl	_Z8testCUDA9cudaErrorPKci
	.type	_Z8testCUDA9cudaErrorPKci, @function
_Z8testCUDA9cudaErrorPKci:
.LFB3635:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L3
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	%edx, %ecx
	movl	$2, %edi
	movq	%rsi, %rdx
	xorl	%eax, %eax
	leaq	.LC0(%rip), %rsi
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L3:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z8testCUDA9cudaErrorPKci, .-_Z8testCUDA9cudaErrorPKci
	.section	.rodata.str1.1
.LC1:
	.string	"SORTED = FALSE for i ="
.LC2:
	.string	"M[i-1]="
.LC3:
	.string	"M[i]="
.LC4:
	.string	"*** Is array sorted : False "
.LC5:
	.string	"*** Is array sorted : True "
	.text
	.globl	_Z12sanity_checkPj
	.type	_Z12sanity_checkPj, @function
_Z12sanity_checkPj:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	$1, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	4(%rdi), %rbx
.L11:
	movl	-4(%rbx), %eax
	cmpl	%eax, (%rbx)
	jnb	.L10
	leaq	_ZSt4cout(%rip), %r12
	leaq	.LC1(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC2(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	-4(%rbx), %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC3(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	(%rbx), %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC4(%rip), %rsi
	movq	%r12, %rdi
	jmp	.L14
.L10:
	incl	%ebp
	addq	$4, %rbx
	cmpl	$2097152, %ebp
	jne	.L11
	leaq	.LC5(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
.L14:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 24
	movq	%rax, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZNSolsEPFRSoS_E.isra.0
	.cfi_endproc
.LFE3636:
	.size	_Z12sanity_checkPj, .-_Z12sanity_checkPj
	.globl	_Z30__device_stub__Z10sort_arrayPjPj
	.type	_Z30__device_stub__Z10sort_arrayPjPj, @function
_Z30__device_stub__Z10sort_arrayPjPj:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10sort_arrayPj(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L15:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z30__device_stub__Z10sort_arrayPjPj, .-_Z30__device_stub__Z10sort_arrayPjPj
	.globl	_Z10sort_arrayPj
	.type	_Z10sort_arrayPj, @function
_Z10sort_arrayPj:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10sort_arrayPjPj
	.cfi_endproc
.LFE3663:
	.size	_Z10sort_arrayPj, .-_Z10sort_arrayPj
	.globl	_Z32__device_stub__Z12sort_array_2PjPj
	.type	_Z32__device_stub__Z12sort_array_2PjPj, @function
_Z32__device_stub__Z12sort_array_2PjPj:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z12sort_array_2Pj(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L20:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z32__device_stub__Z12sort_array_2PjPj, .-_Z32__device_stub__Z12sort_array_2PjPj
	.globl	_Z12sort_array_2Pj
	.type	_Z12sort_array_2Pj, @function
_Z12sort_array_2Pj:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z12sort_array_2PjPj
	.cfi_endproc
.LFE3665:
	.size	_Z12sort_array_2Pj, .-_Z12sort_array_2Pj
	.globl	_Z34__device_stub__Z11merge_arrayPjS_iPjS_i
	.type	_Z34__device_stub__Z11merge_arrayPjS_iPjS_i, @function
_Z34__device_stub__Z11merge_arrayPjS_iPjS_i:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z11merge_arrayPjS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L25:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z34__device_stub__Z11merge_arrayPjS_iPjS_i, .-_Z34__device_stub__Z11merge_arrayPjS_iPjS_i
	.globl	_Z11merge_arrayPjS_i
	.type	_Z11merge_arrayPjS_i, @function
_Z11merge_arrayPjS_i:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z11merge_arrayPjS_iPjS_i
	.cfi_endproc
.LFE3667:
	.size	_Z11merge_arrayPjS_i, .-_Z11merge_arrayPjS_i
	.section	.rodata.str1.1
.LC6:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/jbgaya/CUDA_merge_path/master/merge_sort_path.cu"
.LC7:
	.string	"---- GENERATING RANDOM ARRAY WITH CURAND ----"
.LC8:
	.string	"*** Length of array created : "
.LC9:
	.string	"*** Execution time : "
.LC10:
	.string	" ms"
.LC11:
	.string	"\n---- SORTING ARRAYS OF LENGTH 2 TO INITIALIZE MERGE PATH ----"
.LC12:
	.string	"\n---- MERGING SORTED ARRAYS BY MERGE PATH ----"
.LC13:
	.string	"\n---- SANITY CHECK ----"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rdi
	leaq	16(%rsp), %r14
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	leaq	4(%rsp), %r12
	call	cudaEventCreate@PLT
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$8388608, %esi
	call	cudaMallocManaged@PLT
	movl	$124, %edx
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_Z8testCUDA9cudaErrorPKci
	leaq	24(%rsp), %rdi
	movl	$100, %esi
	call	curandCreateGenerator@PLT
	movl	$1, %edx
	movl	$8388608, %esi
	movq	%r14, %rdi
	call	cudaMallocManaged@PLT
	movl	$126, %edx
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_Z8testCUDA9cudaErrorPKci
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2097152, %edx
	call	curandGenerate@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%r12, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC8(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$2097152, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	4(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC11(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4194305, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 68(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 60(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	8(%rsp), %rdi
	call	_Z32__device_stub__Z12sort_array_2PjPj
.L31:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	movl	$20, %r13d
	movl	$2, %ebx
	movabsq	$4294967297, %r15
	movl	$1048576, %ebp
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%r12, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	4(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC12(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L33:
	movl	%ebp, %eax
	movl	$2, %ecx
	addl	%ebx, %ebx
	movq	%r15, 64(%rsp)
	cltd
	movq	%r15, 52(%rsp)
	movl	56(%rsp), %esi
	idivl	%ecx
	movl	68(%rsp), %ecx
	movl	%eax, %ebp
	movl	$1024, %eax
	cmpl	%eax, %ebx
	movl	%ebp, 48(%rsp)
	movq	48(%rsp), %rdi
	cmovle	%ebx, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 60(%rsp)
	movq	60(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z34__device_stub__Z11merge_arrayPjS_iPjS_i
.L32:
	movq	16(%rsp), %rax
	movl	$1, %edx
	movl	$8388608, %esi
	movq	%r14, %rdi
	movq	%rax, 8(%rsp)
	call	cudaMallocManaged@PLT
	movl	$161, %edx
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_Z8testCUDA9cudaErrorPKci
	decl	%r13d
	jne	.L33
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%r12, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	4(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$8388608, %edi
	call	malloc@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$8388608, %edx
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movl	$171, %edx
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_Z8testCUDA9cudaErrorPKci
	leaq	.LC13(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	call	clock@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	_Z12sanity_checkPj
	call	clock@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%r12, %rax
	movq	%rax, %rbp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtsi2ssq	%rbp, %xmm0
	divss	.LC14(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	main, .-main
	.section	.rodata.str1.1
.LC15:
	.string	"_Z11merge_arrayPjS_i"
.LC16:
	.string	"_Z12sort_array_2Pj"
.LC17:
	.string	"_Z10sort_arrayPj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11merge_arrayPjS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12sort_array_2Pj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10sort_arrayPj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC14:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
#include <hiprand/hiprand.h>
using namespace std;

#define n 1048576*2 // Size of array M (should be a power of 2

// Function that catches the error
void testCUDA(hipError_t error, const char *file, int line)  {
	if (error != hipSuccess) {
	   printf("There is an error in file %s at line %d\n", file, line);
       exit(EXIT_FAILURE);
	}
}
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))

//Sort initialization #1 : with multiple blocks ---> NOT OPTIMAL
__global__
void sort_array(unsigned int *M){
	int index = blockIdx.x * 2;
	if(M[index] > M[index+1]){
		int swap = M[index];
		M[index] = M[index+1];
		M[index+1] = swap;
	}
}

//Sort initialization #2 : with multiple blocks ---> OPTIMAL (contiguity)
__global__
void sort_array_2(unsigned int *M){
	int stride = min(n/2,1024)*2;
	int index = blockIdx.x * blockDim.x * 2 ;
	for(int i=threadIdx.x*2;i<blockDim.x*2;i+=stride){
		if(M[index+i] > M[index+i+1]){
			int swap = M[index+i];
			M[index+i] = M[index+i+1];
			M[index+i+1] = swap;
		}
	}
}

//Merge path
__global__
void merge_array(unsigned int *m,unsigned int *M,int array_size){
  int index_array = blockIdx.x * array_size;
	int stride = blockDim.x;
	for(int i=threadIdx.x;i<array_size;i+=stride){

	  int size_A = array_size / 2;
	  int size_B = array_size / 2;
	  int offset;

	  int K[2],P[2],Q[2];
	  if( i> size_A ){
	      K[0] = P[1] = i - size_A;
	      K[1] = P[0] = size_A;
	    }
	    else{
	      K[0] = P[1] = 0;
	      K[1] = P[0] = i;
	    }
	    while(true){
	        offset = abs(K[1]-P[1])/2;
	        Q[0] = K[0] + offset;
	        Q[1] = K[1] - offset;
	    if (Q[1] >= 0 && Q[0] <= size_B && (Q[1] == size_A || Q[0] == 0 || M[index_array+Q[1]]>M[index_array+size_A+Q[0]-1])){
	      if(Q[0] == size_B || Q[1] == 0 || M[index_array+Q[1]-1] <= M[index_array+size_A+Q[0]]){
	        if(Q[1] < size_A && (Q[0] == size_B || M[index_array+Q[1]] <= M[index_array+size_A+Q[0]])){
	        m[index_array+i] = M[index_array+Q[1]];
	        }
	        else{
	          m[index_array+i] = M[index_array+size_A+Q[0]];
	        }
	        break;
	      }
	      else {
	        K[0] = Q[0] + 1;
	        K[1] = Q[1] - 1;
	      }
	    }
	    else{
	      P[0] = Q[0] - 1;
	      P[1] = Q[1] + 1;
	    }
		}
	}
	__syncthreads();
}

//Function to Sanity check if the array is sorted or not (CPU)
void sanity_check(unsigned int *M){
  bool sorted = true;
  for (int i = 1; i < n; i++){
      if(M[i]<M[i-1]){
        sorted = false;
				cout << "SORTED = FALSE for i =" << i << endl;
				cout << "M[i-1]=" << M[i-1] << endl;
				cout << "M[i]=" << M[i] << endl;
				break;
      }
    }
  if(sorted==true){
    cout << "*** Is array sorted : True " << endl;
  }
  else{
      cout << "*** Is array sorted : False " << endl;
  }
}

int main () {


// *** Defining variables ***
  unsigned int *M_dev, *M_dev_next;	//Array and its copy to scale merge path procedure
	hiprandGenerator_t G; 							//Curand RNG
	clock_t timer; 										//Timer for CPU
  hipEvent_t start,stop;						//Timer for GPU
	float elapsedTime;								//Timer for GPU


// *** Allocating memory ***
	hipEventCreate(&start);
	hipEventCreate(&stop);
  testCUDA(hipMallocManaged(&M_dev, n*sizeof(unsigned int)));
	hiprandCreateGenerator(&G,HIPRAND_RNG_PSEUDO_DEFAULT);
	testCUDA(hipMallocManaged(&M_dev_next, n*sizeof(unsigned int)));


// *** Performing custom random array generation ***
  cout << "---- GENERATING RANDOM ARRAY WITH CURAND ----" << endl;
  hipEventRecord(start,0);
	hiprandGenerate(G, M_dev, n); //Generate n pseudo random unsigned int on device
  hipEventRecord(stop,0);
  hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsedTime,start,stop);
  cout << "*** Length of array created : " << n << endl;
  cout << "*** Execution time : " << elapsedTime << " ms" << endl;


// *** Performing sort initialization ***
  cout << "\n---- SORTING ARRAYS OF LENGTH 2 TO INITIALIZE MERGE PATH ----" << endl;
  hipEventRecord(start,0);
	//sort_array<<<n/2,1>>>(M_dev);
	sort_array_2<<<n/(2*min(n/2,1024)),min(n/2,1024)>>>(M_dev);
	hipEventRecord(stop,0);
  hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsedTime,start,stop);
	cout << "*** Execution time : " << elapsedTime << " ms" << endl;


// *** Performing merge path***
	cout << "\n---- MERGING SORTED ARRAYS BY MERGE PATH ----" << endl;
	hipEventRecord(start,0);
  int nb_arrays = n/2;
  int array_size = 2;
  while (nb_arrays!=1){
		nb_arrays /= 2; //nb of array to merge on next merge_path
    array_size *= 2; //size of arrays on next merge_path
    merge_array<<<nb_arrays,min(array_size,1024)>>>(M_dev_next,M_dev,array_size);
		M_dev = M_dev_next;
		testCUDA(hipMallocManaged(&M_dev_next, n*sizeof(unsigned int)));
  }
  hipEventRecord(stop,0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&elapsedTime,start,stop);
  cout << "*** Execution time : " << elapsedTime << " ms" << endl;


//*** Sanity check ***
  unsigned int *M_host = (unsigned int*)malloc(n*sizeof(unsigned int));
  testCUDA(hipMemcpy(M_host, M_dev, n*sizeof(unsigned int), hipMemcpyDeviceToHost));

	/*
	//Code to vizualize array sorted
  for(int i=0;i<n;i++){
      cout <<  M_host[i] << "\t";
		}
	*/

	cout << "\n---- SANITY CHECK ----" << endl;
	timer = clock();
	sanity_check(M_host);
	timer = clock() - timer;
	cout << "*** Execution time : " << (float)timer/(CLOCKS_PER_SEC/1000) << " ms" << endl;


//*** free memory on device and host ***
	free(M_host);
  hipEventDestroy(start);
	hipEventDestroy(stop);
	hipFree(M_dev);
	hipFree(M_dev_next);


  return EXIT_SUCCESS;
}

	.text
	.file	"merge_sort_path.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z8testCUDA10hipError_tPKci     # -- Begin function _Z8testCUDA10hipError_tPKci
	.type	_Z8testCUDA10hipError_tPKci,@function
_Z8testCUDA10hipError_tPKci:            # @_Z8testCUDA10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB0_2
# %bb.1:
	retq
.LBB0_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z8testCUDA10hipError_tPKci, .Lfunc_end0-_Z8testCUDA10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__sort_arrayPj # -- Begin function _Z25__device_stub__sort_arrayPj
	.type	_Z25__device_stub__sort_arrayPj,@function
_Z25__device_stub__sort_arrayPj:        # @_Z25__device_stub__sort_arrayPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10sort_arrayPj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__sort_arrayPj, .Lfunc_end1-_Z25__device_stub__sort_arrayPj
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__sort_array_2Pj # -- Begin function _Z27__device_stub__sort_array_2Pj
	.type	_Z27__device_stub__sort_array_2Pj,@function
_Z27__device_stub__sort_array_2Pj:      # @_Z27__device_stub__sort_array_2Pj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12sort_array_2Pj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z27__device_stub__sort_array_2Pj, .Lfunc_end2-_Z27__device_stub__sort_array_2Pj
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__merge_arrayPjS_i # -- Begin function _Z26__device_stub__merge_arrayPjS_i
	.type	_Z26__device_stub__merge_arrayPjS_i,@function
_Z26__device_stub__merge_arrayPjS_i:    # @_Z26__device_stub__merge_arrayPjS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11merge_arrayPjS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z26__device_stub__merge_arrayPjS_i, .Lfunc_end3-_Z26__device_stub__merge_arrayPjS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12sanity_checkPj              # -- Begin function _Z12sanity_checkPj
	.type	_Z12sanity_checkPj,@function
_Z12sanity_checkPj:                     # @_Z12sanity_checkPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	$1, %r14d
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %eax
	cmpl	-4(%rbx,%r14,4), %eax
	jb	.LBB4_4
# %bb.2:                                #   in Loop: Header=BB4_1 Depth=1
	incq	%r14
	cmpq	$2097152, %r14                  # imm = 0x200000
	jne	.LBB4_1
# %bb.3:                                # %.critedge
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$27, %edx
	jmp	.LBB4_5
.LBB4_4:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	-4(%rbx,%r14,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%rbx,%r14,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$28, %edx
.LBB4_5:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end4:
	.size	_Z12sanity_checkPj, .Lfunc_end4-_Z12sanity_checkPj
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI5_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	movl	$8388608, %esi                  # imm = 0x800000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB5_1
# %bb.3:                                # %_Z8testCUDA10hipError_tPKci.exit
	leaq	40(%rsp), %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hiprandCreateGenerator
	leaq	32(%rsp), %rdi
	movl	$8388608, %esi                  # imm = 0x800000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.5:                                # %_Z8testCUDA10hipError_tPKci.exit20
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	$_ZSt4cout, %r12d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$45, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	40(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$2097152, %edx                  # imm = 0x200000
	callq	hiprandGenerate
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.8, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$2097152, %esi                  # imm = 0x200000
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.10, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.11, %esi
	movl	$62, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	1024(%r15), %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_7
# %bb.6:
	movq	16(%rsp), %rdi
	callq	_Z27__device_stub__sort_array_2Pj
.LBB5_7:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.10, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$46, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$1048576, %r12d                 # imm = 0x100000
	movl	$2, %ebx
	movl	$1024, %ebp                     # imm = 0x400
	leaq	32(%rsp), %r14
.LBB5_8:                                # %_Z8testCUDA10hipError_tPKci.exit22
                                        # =>This Inner Loop Header: Depth=1
	cmpl	$1, %r12d
	je	.LBB5_13
# %bb.9:                                #   in Loop: Header=BB5_8 Depth=1
	movl	%r12d, %eax
	shrl	$31, %eax
	addl	%r12d, %eax
	movl	%eax, %r12d
	sarl	%r12d
	addl	%ebx, %ebx
	cmpl	%ebp, %ebx
	movl	$1024, %edx                     # imm = 0x400
	cmovll	%ebx, %edx
	movq	%r12, %rdi
	orq	%r15, %rdi
	orq	%r15, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_11
# %bb.10:                               #   in Loop: Header=BB5_8 Depth=1
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	%ebx, %edx
	callq	_Z26__device_stub__merge_arrayPjS_i
.LBB5_11:                               #   in Loop: Header=BB5_8 Depth=1
	movq	32(%rsp), %rax
	movq	%rax, 16(%rsp)
	movl	$8388608, %esi                  # imm = 0x800000
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB5_8
# %bb.12:
	movl	$.L.str, %edi
	movl	$.L.str.6, %esi
	movl	$163, %edx
.LBB5_2:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.LBB5_13:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %r14d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.10, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$8388608, %edi                  # imm = 0x800000
	callq	malloc
	movq	%rax, %rbx
	movq	16(%rsp), %rsi
	movl	$8388608, %edx                  # imm = 0x800000
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_14
# %bb.15:                               # %_Z8testCUDA10hipError_tPKci.exit24
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$23, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	clock
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	_Z12sanity_checkPj
	callq	clock
	movq	%rax, %r15
	subq	%r14, %r15
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15, %xmm0
	divss	.LCPI5_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movl	$.L.str.10, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rbx, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_1:
	.cfi_def_cfa_offset 96
	movl	$.L.str, %edi
	movl	$.L.str.6, %esi
	movl	$126, %edx
	jmp	.LBB5_2
.LBB5_4:
	movl	$.L.str, %edi
	movl	$.L.str.6, %esi
	movl	$128, %edx
	jmp	.LBB5_2
.LBB5_14:
	movl	$.L.str, %edi
	movl	$.L.str.6, %esi
	movl	$173, %edx
	jmp	.LBB5_2
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10sort_arrayPj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12sort_array_2Pj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11merge_arrayPjS_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"There is an error in file %s at line %d\n"
	.size	.L.str, 41

	.type	_Z10sort_arrayPj,@object        # @_Z10sort_arrayPj
	.section	.rodata,"a",@progbits
	.globl	_Z10sort_arrayPj
	.p2align	3, 0x0
_Z10sort_arrayPj:
	.quad	_Z25__device_stub__sort_arrayPj
	.size	_Z10sort_arrayPj, 8

	.type	_Z12sort_array_2Pj,@object      # @_Z12sort_array_2Pj
	.globl	_Z12sort_array_2Pj
	.p2align	3, 0x0
_Z12sort_array_2Pj:
	.quad	_Z27__device_stub__sort_array_2Pj
	.size	_Z12sort_array_2Pj, 8

	.type	_Z11merge_arrayPjS_i,@object    # @_Z11merge_arrayPjS_i
	.globl	_Z11merge_arrayPjS_i
	.p2align	3, 0x0
_Z11merge_arrayPjS_i:
	.quad	_Z26__device_stub__merge_arrayPjS_i
	.size	_Z11merge_arrayPjS_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"SORTED = FALSE for i ="
	.size	.L.str.1, 23

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"M[i-1]="
	.size	.L.str.2, 8

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"M[i]="
	.size	.L.str.3, 6

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"*** Is array sorted : True "
	.size	.L.str.4, 28

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"*** Is array sorted : False "
	.size	.L.str.5, 29

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/jbgaya/CUDA_merge_path/master/merge_sort_path.hip"
	.size	.L.str.6, 112

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"---- GENERATING RANDOM ARRAY WITH CURAND ----"
	.size	.L.str.7, 46

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"*** Length of array created : "
	.size	.L.str.8, 31

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"*** Execution time : "
	.size	.L.str.9, 22

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	" ms"
	.size	.L.str.10, 4

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"\n---- SORTING ARRAYS OF LENGTH 2 TO INITIALIZE MERGE PATH ----"
	.size	.L.str.11, 63

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"\n---- MERGING SORTED ARRAYS BY MERGE PATH ----"
	.size	.L.str.12, 47

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"\n---- SANITY CHECK ----"
	.size	.L.str.13, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10sort_arrayPj"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12sort_array_2Pj"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11merge_arrayPjS_i"
	.size	.L__unnamed_3, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__sort_arrayPj
	.addrsig_sym _Z27__device_stub__sort_array_2Pj
	.addrsig_sym _Z26__device_stub__merge_arrayPjS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10sort_arrayPj
	.addrsig_sym _Z12sort_array_2Pj
	.addrsig_sym _Z11merge_arrayPjS_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10sort_arrayPj        ; -- Begin function _Z10sort_arrayPj
	.globl	_Z10sort_arrayPj
	.p2align	8
	.type	_Z10sort_arrayPj,@function
_Z10sort_arrayPj:                       ; @_Z10sort_arrayPj
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_lshl_b32 s2, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_le_u32 s2, s3
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[0:1], s[0:1]
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10sort_arrayPj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10sort_arrayPj, .Lfunc_end0-_Z10sort_arrayPj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 88
; NumSgprs: 16
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12sort_array_2Pj      ; -- Begin function _Z12sort_array_2Pj
	.globl	_Z12sort_array_2Pj
	.p2align	8
	.type	_Z12sort_array_2Pj,@function
_Z12sort_array_2Pj:                     ; @_Z12sort_array_2Pj
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_lshlrev_b32_e32 v4, 1, v0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s2, s3, 1
	v_cmpx_gt_u32_e64 s2, v4
	s_cbranch_execz .LBB1_5
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mul_i32 s15, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, s15, 1, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s1, 0
	v_add_co_u32 v0, vcc_lo, v0, 4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[2:3], v[0:1], off offset:-4
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_u32_e64 v2, v3
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, v2
	global_store_b64 v[0:1], v[5:6], off offset:-4
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v4, 0x800, v4
	v_add_co_u32 v0, s0, 0x2000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_2
.LBB1_5:                                ; %Flow28
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12sort_array_2Pj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12sort_array_2Pj, .Lfunc_end1-_Z12sort_array_2Pj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11merge_arrayPjS_i    ; -- Begin function _Z11merge_arrayPjS_i
	.globl	_Z11merge_arrayPjS_i
	.p2align	8
	.type	_Z11merge_arrayPjS_i,@function
_Z11merge_arrayPjS_i:                   ; @_Z11merge_arrayPjS_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x10
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB2_23
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b32 s10, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mul_i32 s1, s15, s2
	s_lshr_b32 s8, s2, 1
	s_mov_b32 s13, 0
	s_add_i32 s9, s1, s8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s10, 0xffff
	s_add_u32 s11, s6, -4
	s_addc_u32 s12, s7, -1
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
                                        ;       Child Loop BB2_4 Depth 3
	v_sub_nc_u32_e64 v2, v0, s8 clamp
	v_min_i32_e32 v1, s8, v0
	s_mov_b32 s15, 0
                                        ; implicit-def: $sgpr14
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v2
.LBB2_3:                                ; %.outer
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_4 Depth 3
	s_mov_b32 s16, 0
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v7
	s_mov_b32 s17, -1
	v_sub_nc_u32_e32 v3, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, 0, v3
	v_max_i32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 1, v3
	v_sub_nc_u32_e32 v4, v1, v6
	v_add_nc_u32_e32 v3, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_ge_i32_e64 s0, s8, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s19, vcc_lo, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s18, s19
	s_cbranch_execz .LBB2_8
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=3
	v_cmp_ne_u32_e32 vcc_lo, s8, v4
	v_cmp_ne_u32_e64 s0, 0, v3
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s20, vcc_lo, s0
	s_and_saveexec_b32 s0, s20
	s_cbranch_execz .LBB2_7
; %bb.6:                                ;   in Loop: Header=BB2_4 Depth=3
	v_add_nc_u32_e32 v7, s1, v4
	v_add_nc_u32_e32 v9, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s11, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s12, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, v7, v8
	s_and_b32 s19, vcc_lo, exec_lo
.LBB2_7:                                ; %Flow119
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s19, exec_lo
.LBB2_8:                                ; %Flow118
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s18
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s18, s0
; %bb.9:                                ;   in Loop: Header=BB2_4 Depth=3
	v_add_nc_u32_e32 v7, 1, v4
	s_xor_b32 s17, exec_lo, -1
; %bb.10:                               ; %Flow120
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s17
	s_or_b32 s16, s0, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB2_4
; %bb.11:                               ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_ne_u32_e32 vcc_lo, s8, v3
	v_cmp_ne_u32_e64 s0, v1, v6
	v_cmp_eq_u32_e64 s16, s8, v3
	s_mov_b32 s17, -1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s18, s0, vcc_lo
	s_and_saveexec_b32 s0, s18
	s_cbranch_execz .LBB2_15
; %bb.12:                               ;   in Loop: Header=BB2_3 Depth=2
	v_add_nc_u32_e32 v1, s1, v4
	v_add_nc_u32_e32 v6, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s11, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_clause 0x1
	global_load_b32 v1, v[1:2], off
	global_load_b32 v2, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, v1, v2
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s18, vcc_lo
; %bb.13:                               ;   in Loop: Header=BB2_3 Depth=2
	v_add_nc_u32_e32 v2, 1, v3
	v_add_nc_u32_e32 v1, -1, v4
	s_xor_b32 s17, exec_lo, -1
; %bb.14:                               ; %Flow122
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	v_mov_b32_e32 v7, v5
	s_and_not1_b32 s16, s16, exec_lo
	s_or_not1_b32 s17, s17, exec_lo
.LBB2_15:                               ; %Flow121
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s17
	s_or_b32 s15, s0, s15
	s_and_not1_b32 s0, s14, exec_lo
	s_and_b32 s14, s16, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s14, s0, s14
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB2_3
; %bb.16:                               ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_xor_b32 s15, s14, -1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr1_vgpr2
	v_cmpx_le_i32_e64 s8, v4
	s_xor_b32 s0, exec_lo, s0
; %bb.17:                               ; %._crit_edge88
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v1, s9, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
; %bb.18:                               ; %Flow117
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB2_22
; %bb.19:                               ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v1, s1, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_saveexec_b32 s14, s15
	s_cbranch_execz .LBB2_21
; %bb.20:                               ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v3, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, v5, v6
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
.LBB2_21:                               ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB2_22:                               ; %._crit_edge89
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	v_add_nc_u32_e32 v1, s1, v0
	v_add_nc_u32_e32 v0, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_le_i32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_or_b32 s13, vcc_lo, s13
	v_add_co_u32 v1, s0, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, s5, v2, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB2_2
.LBB2_23:                               ; %Flow124
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11merge_arrayPjS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11merge_arrayPjS_i, .Lfunc_end2-_Z11merge_arrayPjS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 23
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10sort_arrayPj
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z10sort_arrayPj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12sort_array_2Pj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12sort_array_2Pj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11merge_arrayPjS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z11merge_arrayPjS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
