#include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include<time.h>

#define BLOCK_SIZE 25

__global__ void gpu_shared_matrix_mul(float *a, float *b, float *gpu_mul, int n)
{
	__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
	__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];

	int row=blockIdx.y*blockDim.y+threadIdx.y;
	int column=blockIdx.x*blockDim.x+threadIdx.x;
	float sum=0;
	int index;

	for(int i=0;i<gridDim.x;i++)
	{
		index=row*n+i*BLOCK_SIZE+threadIdx.x;
		if(index>=n*n)
		{
			tile_a[threadIdx.y][threadIdx.x]=0;
		}
		else
		{
			tile_a[threadIdx.y][threadIdx.x]=a[index];
		}
		
		index=(i*BLOCK_SIZE+threadIdx.y)*n+column;
		if(index>=n*n)
		{
			tile_b[threadIdx.y][threadIdx.x]=0;
		}
		else
		{
			tile_b[threadIdx.y][threadIdx.x]=b[index];
		}
		__syncthreads();

		for(int k=0;k<BLOCK_SIZE;k++)
		{
			sum+=tile_a[threadIdx.y][k]*tile_b[k][threadIdx.x];
		}
		__syncthreads(); 
	}
	if(row<n && column<n)
	{
		gpu_mul[row*n+column]=sum;
	}
}

void cpu_matrix_mul(float *h_a, float *h_b, float *h_mul, int n)
{
	for(int i=0;i<n;i++)
	{
		for(int j=0;j<n;j++)
		{
			float sum=0;
			for(int l=0;l<n;l++)
			{
				sum+=h_a[i*n+l]*h_b[l*n+j];
			}
			h_mul[i*n+j]=sum;
		}
	}
}

int main()
{
	int n;
	printf("Enter Dimension of square matrix : ");
	scanf("%d", &n);
	float size=sizeof(float)*n*n;
	
	float *h_a, *h_b, *h_c, *h_cc;
	cudaMallocHost((void**)&h_a, size);
	cudaMallocHost((void**)&h_b, size);
	cudaMallocHost((void**)&h_c, size);
	cudaMallocHost((void**)&h_cc, size);

	for(int i=0;i<n;i++)
	{
		for(int j=0;j<n;j++)
		{
			h_a[i*n+j]=1;
			h_b[i*n+j]=2;
		}
	}

	float *d_a, *d_b, *d_c;
	cudaMalloc((void**)&d_a, size);
	cudaMalloc((void**)&d_b, size);
	cudaMalloc((void**)&d_c, size);

	cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
	cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);

	dim3 dimGrid((n+BLOCK_SIZE+1)/BLOCK_SIZE, (n+BLOCK_SIZE+1)/BLOCK_SIZE);
	dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);

	clock_t gpu_start, gpu_end;
	gpu_start=clock();
	gpu_shared_matrix_mul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
	
	cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
	cudaThreadSynchronize();
	gpu_end=clock();
	float gpu_time=float(gpu_end-gpu_start)/float(CLOCKS_PER_SEC);
	printf("GPU Time : %f seconds\n", gpu_time);

	clock_t cpu_start, cpu_end;
	cpu_start=clock();
	cpu_matrix_mul(h_a, h_b, h_cc, n);
	cpu_end=clock();
	float cpu_time=float(cpu_end-cpu_start)/float(CLOCKS_PER_SEC);
	printf("CPU Time : %f seconds\n", cpu_time);

	int flag=1;
	for(int i=0;i<n;i++)
	{
		for(int j=0;j<n;j++)
		{
			if(h_cc[i*n+j]!=h_c[i*n+j])
			{
				flag=0;
				break;
			}
		}
	}
	
	if(flag)
	{
		printf("Success! Speedup : %f\n", cpu_time/gpu_time);
	}
	else
	{
		printf("Incorrect\n");
	}
}


	.file	"tmpxft_00359686_00000000-6_matrix_mult_shared.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14cpu_matrix_mulPfS_S_i
	.type	_Z14cpu_matrix_mulPfS_S_i, @function
_Z14cpu_matrix_mulPfS_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	%rdi, %r10
	xorl	%r9d, %r9d
	movslq	%ecx, %rdi
	movq	%rsi, %r11
	salq	$2, %rdi
	xorl	%esi, %esi
	cmpl	%ecx, %r9d
	jl	.L11
	ret
.L11:
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
.L7:
	xorl	%eax, %eax
	leaq	(%r10,%rsi), %rbp
	leaq	(%rdx,%rsi), %r12
.L6:
	leaq	(%r11,%rax,4), %rbx
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
.L4:
	movss	0(%rbp,%r8,4), %xmm1
	mulss	(%rbx), %xmm1
	incq	%r8
	addq	%rdi, %rbx
	addss	%xmm1, %xmm0
	cmpl	%r8d, %ecx
	jg	.L4
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpl	%eax, %ecx
	jg	.L6
	incl	%r9d
	addq	%rdi, %rsi
	cmpl	%ecx, %r9d
	jl	.L7
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z14cpu_matrix_mulPfS_S_i, .-_Z14cpu_matrix_mulPfS_S_i
	.globl	_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i
	.type	_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i, @function
_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21gpu_shared_matrix_mulPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i, .-_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i
	.globl	_Z21gpu_shared_matrix_mulPfS_S_i
	.type	_Z21gpu_shared_matrix_mulPfS_S_i, @function
_Z21gpu_shared_matrix_mulPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z21gpu_shared_matrix_mulPfS_S_i, .-_Z21gpu_shared_matrix_mulPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Enter Dimension of square matrix : "
.LC2:
	.string	"%d"
.LC7:
	.string	"GPU Time : %f seconds\n"
.LC8:
	.string	"CPU Time : %f seconds\n"
.LC9:
	.string	"Success! Speedup : %f\n"
.LC10:
	.string	"Incorrect\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$120, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	leaq	20(%rsp), %rsi
	leaq	.LC2(%rip), %rdi
	call	__isoc23_scanf@PLT
	movslq	20(%rsp), %rax
	imulq	%rax, %rax
	salq	$2, %rax
	js	.L19
	cvtsi2ssq	%rax, %xmm0
	jmp	.L20
.L19:
	shrq	%rax
	cvtsi2ssq	%rax, %xmm0
	addss	%xmm0, %xmm0
.L20:
	comiss	.LC3(%rip), %xmm0
	jnb	.L21
	cvttss2siq	%xmm0, %rbx
	jmp	.L22
.L21:
	subss	.LC3(%rip), %xmm0
	cvttss2siq	%xmm0, %rbx
	btcq	$63, %rbx
.L22:
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMallocHost@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMallocHost@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMallocHost@PLT
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMallocHost@PLT
	movslq	20(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movq	24(%rsp), %r9
	movq	32(%rsp), %r10
	movss	.LC4(%rip), %xmm0
	movss	.LC5(%rip), %xmm1
	movq	%rdi, %rcx
	salq	$2, %rdi
.L23:
	cmpl	%edx, %ecx
	jle	.L40
	movq	%rsi, %rax
	xorl	%r8d, %r8d
.L24:
	incl	%r8d
	movss	%xmm0, (%r9,%rax)
	movss	%xmm1, (%r10,%rax)
	addq	$4, %rax
	cmpl	%r8d, %ecx
	jne	.L24
	incl	%edx
	addq	%rdi, %rsi
	jmp	.L23
.L40:
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rsi
	movq	56(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	64(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	20(%rsp), %eax
	movl	$25, %ecx
	movl	$1, 88(%rsp)
	movl	$1, 100(%rsp)
	addl	$26, %eax
	cltd
	idivl	%ecx
	movl	%eax, 80(%rsp)
	movl	%eax, 84(%rsp)
	movabsq	$107374182425, %rax
	movq	%rax, 92(%rsp)
	call	clock@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movl	20(%rsp), %ecx
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z46__device_stub__Z21gpu_shared_matrix_mulPfS_S_iPfS_S_i
.L25:
	movq	72(%rsp), %rsi
	movq	40(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	call	clock@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	subq	%rbp, %rax
	cvtsi2ssq	%rax, %xmm2
	movb	$1, %al
	divss	.LC6(%rip), %xmm2
	cvtss2sd	%xmm2, %xmm0
	movss	%xmm2, 12(%rsp)
	call	__printf_chk@PLT
	call	clock@PLT
	movl	20(%rsp), %ecx
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	movq	%rax, %rbx
	call	_Z14cpu_matrix_mulPfS_S_i
	call	clock@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	subq	%rbx, %rax
	cvtsi2ssq	%rax, %xmm1
	movb	$1, %al
	divss	.LC6(%rip), %xmm1
	movss	%xmm1, 8(%rsp)
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movslq	20(%rsp), %rsi
	movq	48(%rsp), %r10
	movq	40(%rsp), %r11
	movss	8(%rsp), %xmm1
	xorl	%edi, %edi
	xorl	%edx, %edx
	movss	12(%rsp), %xmm2
	movq	%rsi, %rcx
	movl	$1, %r9d
	salq	$2, %rsi
.L26:
	cmpl	%edx, %ecx
	jle	.L41
	movq	%rdi, %rax
	xorl	%r8d, %r8d
.L29:
	movss	(%r10,%rax), %xmm0
	ucomiss	(%r11,%rax), %xmm0
	jp	.L34
	jne	.L34
	incl	%r8d
	addq	$4, %rax
	cmpl	%r8d, %ecx
	jne	.L29
	jmp	.L27
.L34:
	xorl	%r9d, %r9d
.L27:
	incl	%edx
	addq	%rsi, %rdi
	jmp	.L26
.L41:
	testl	%r9d, %r9d
	je	.L30
	divss	%xmm2, %xmm1
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	jmp	.L31
.L30:
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L31:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$120, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z21gpu_shared_matrix_mulPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21gpu_shared_matrix_mulPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1593835520
	.align 4
.LC4:
	.long	1065353216
	.align 4
.LC5:
	.long	1073741824
	.align 4
.LC6:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include<time.h>

#define BLOCK_SIZE 25

__global__ void gpu_shared_matrix_mul(float *a, float *b, float *gpu_mul, int n)
{
	__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
	__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];

	int row=blockIdx.y*blockDim.y+threadIdx.y;
	int column=blockIdx.x*blockDim.x+threadIdx.x;
	float sum=0;
	int index;

	for(int i=0;i<gridDim.x;i++)
	{
		index=row*n+i*BLOCK_SIZE+threadIdx.x;
		if(index>=n*n)
		{
			tile_a[threadIdx.y][threadIdx.x]=0;
		}
		else
		{
			tile_a[threadIdx.y][threadIdx.x]=a[index];
		}
		
		index=(i*BLOCK_SIZE+threadIdx.y)*n+column;
		if(index>=n*n)
		{
			tile_b[threadIdx.y][threadIdx.x]=0;
		}
		else
		{
			tile_b[threadIdx.y][threadIdx.x]=b[index];
		}
		__syncthreads();

		for(int k=0;k<BLOCK_SIZE;k++)
		{
			sum+=tile_a[threadIdx.y][k]*tile_b[k][threadIdx.x];
		}
		__syncthreads(); 
	}
	if(row<n && column<n)
	{
		gpu_mul[row*n+column]=sum;
	}
}

void cpu_matrix_mul(float *h_a, float *h_b, float *h_mul, int n)
{
	for(int i=0;i<n;i++)
	{
		for(int j=0;j<n;j++)
		{
			float sum=0;
			for(int l=0;l<n;l++)
			{
				sum+=h_a[i*n+l]*h_b[l*n+j];
			}
			h_mul[i*n+j]=sum;
		}
	}
}

int main()
{
	int n;
	printf("Enter Dimension of square matrix : ");
	scanf("%d", &n);
	float size=sizeof(float)*n*n;
	
	float *h_a, *h_b, *h_c, *h_cc;
	hipHostMalloc((void**)&h_a, size, hipHostMallocDefault);
	hipHostMalloc((void**)&h_b, size, hipHostMallocDefault);
	hipHostMalloc((void**)&h_c, size, hipHostMallocDefault);
	hipHostMalloc((void**)&h_cc, size, hipHostMallocDefault);

	for(int i=0;i<n;i++)
	{
		for(int j=0;j<n;j++)
		{
			h_a[i*n+j]=1;
			h_b[i*n+j]=2;
		}
	}

	float *d_a, *d_b, *d_c;
	hipMalloc((void**)&d_a, size);
	hipMalloc((void**)&d_b, size);
	hipMalloc((void**)&d_c, size);

	hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
	hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);

	dim3 dimGrid((n+BLOCK_SIZE+1)/BLOCK_SIZE, (n+BLOCK_SIZE+1)/BLOCK_SIZE);
	dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);

	clock_t gpu_start, gpu_end;
	gpu_start=clock();
	gpu_shared_matrix_mul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
	
	hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
	hipDeviceSynchronize();
	gpu_end=clock();
	float gpu_time=float(gpu_end-gpu_start)/float(CLOCKS_PER_SEC);
	printf("GPU Time : %f seconds\n", gpu_time);

	clock_t cpu_start, cpu_end;
	cpu_start=clock();
	cpu_matrix_mul(h_a, h_b, h_cc, n);
	cpu_end=clock();
	float cpu_time=float(cpu_end-cpu_start)/float(CLOCKS_PER_SEC);
	printf("CPU Time : %f seconds\n", cpu_time);

	int flag=1;
	for(int i=0;i<n;i++)
	{
		for(int j=0;j<n;j++)
		{
			if(h_cc[i*n+j]!=h_c[i*n+j])
			{
				flag=0;
				break;
			}
		}
	}
	
	if(flag)
	{
		printf("Success! Speedup : %f\n", cpu_time/gpu_time);
	}
	else
	{
		printf("Incorrect\n");
	}
}


	.text
	.file	"matrix_mult_shared.hip"
	.globl	_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i # -- Begin function _Z36__device_stub__gpu_shared_matrix_mulPfS_S_i
	.type	_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i,@function
_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i: # @_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21gpu_shared_matrix_mulPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i, .Lfunc_end0-_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z14cpu_matrix_mulPfS_S_i       # -- Begin function _Z14cpu_matrix_mulPfS_S_i
	.type	_Z14cpu_matrix_mulPfS_S_i,@function
_Z14cpu_matrix_mulPfS_S_i:              # @_Z14cpu_matrix_mulPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB1_8
# %bb.1:                                # %.preheader26.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB1_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
                                        #       Child Loop BB1_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB1_3:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_4 Depth 3
	xorps	%xmm0, %xmm0
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r13,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	incq	%r13
	addq	%r8, %r12
	cmpq	%r13, %rax
	jne	.LBB1_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_3 Depth=2
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB1_3
# %bb.6:                                # %._crit_edge30
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB1_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB1_8:                                # %._crit_edge32
	retq
.Lfunc_end1:
	.size	_Z14cpu_matrix_mulPfS_S_i, .Lfunc_end1-_Z14cpu_matrix_mulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x5f000000                      # float 9.22337203E+18
.LCPI2_1:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	12(%rsp), %rbx
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%rbx), %rax
	imulq	%rax, %rax
	shlq	$2, %rax
	testq	%rax, %rax
	js	.LBB2_1
# %bb.2:
	cvtsi2ss	%rax, %xmm0
	jmp	.LBB2_3
.LBB2_1:
	shrq	%rax
	cvtsi2ss	%rax, %xmm0
	addss	%xmm0, %xmm0
.LBB2_3:
	cvttss2si	%xmm0, %rax
	movq	%rax, %rcx
	sarq	$63, %rcx
	subss	.LCPI2_0(%rip), %xmm0
	cvttss2si	%xmm0, %rbx
	andq	%rcx, %rbx
	orq	%rax, %rbx
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB2_8
# %bb.4:                                # %.preheader50.lr.ph
	movq	24(%rsp), %rcx
	xorl	%edx, %edx
	movq	16(%rsp), %rsi
	xorl	%edi, %edi
.LBB2_5:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movl	%edx, %r9d
	leaq	(%rsi,%r9,4), %r8
	leaq	(%rcx,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%r9,%r10,4)       # imm = 0x3F800000
	movl	$1073741824, (%r8,%r10,4)       # imm = 0x40000000
	incq	%r10
	cmpq	%r10, %rax
	jne	.LBB2_6
# %bb.7:                                # %._crit_edge
                                        #   in Loop: Header=BB2_5 Depth=1
	incq	%rdi
	addl	%eax, %edx
	cmpq	%rax, %rdi
	jne	.LBB2_5
.LBB2_8:                                # %._crit_edge53
	leaq	72(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movq	16(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	12(%rsp), %eax
	addl	$26, %eax
	cltq
	imulq	$1374389535, %rax, %rax         # imm = 0x51EB851F
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$35, %rax
	addl	%ecx, %eax
	movq	%rax, %r15
	shlq	$32, %r15
	orq	%rax, %r15
	callq	clock
	movq	%rax, %r14
	movabsq	$107374182425, %rdx             # imm = 0x1900000019
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	12(%rsp), %ecx
	callq	_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i
.LBB2_10:
	movq	56(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r14, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI2_1(%rip), %xmm0
	movss	%xmm0, 36(%rsp)                 # 4-byte Spill
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	callq	clock
	movq	%rax, %rbx
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB2_17
# %bb.11:                               # %.preheader26.lr.ph.i
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	(,%rax,4), %rdi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
.LBB2_12:                               # %.preheader.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_13 Depth 2
                                        #       Child Loop BB2_14 Depth 3
	movl	%r8d, %r10d
	leaq	(%rcx,%r10,4), %r10
	movq	%r9, %r11
	imulq	%rax, %r11
	leaq	(%rsi,%r11,4), %r11
	movq	%rdx, %r14
	xorl	%r15d, %r15d
.LBB2_13:                               # %.preheader.i
                                        #   Parent Loop BB2_12 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_14 Depth 3
	xorps	%xmm0, %xmm0
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB2_14:                               #   Parent Loop BB2_12 Depth=1
                                        #     Parent Loop BB2_13 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r10,%r13), %xmm1              # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %r13
	addq	%rdi, %r12
	cmpq	%r13, %rdi
	jne	.LBB2_14
# %bb.15:                               # %._crit_edge.i
                                        #   in Loop: Header=BB2_13 Depth=2
	movss	%xmm0, (%r11,%r15,4)
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB2_13
# %bb.16:                               # %._crit_edge30.i
                                        #   in Loop: Header=BB2_12 Depth=1
	incq	%r9
	addl	%eax, %r8d
	cmpq	%rax, %r9
	jne	.LBB2_12
.LBB2_17:                               # %_Z14cpu_matrix_mulPfS_S_i.exit
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI2_1(%rip), %xmm0
	movss	%xmm0, 32(%rsp)                 # 4-byte Spill
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB2_27
# %bb.18:                               # %.preheader.lr.ph
	movq	48(%rsp), %rcx
	movq	56(%rsp), %rdx
	xorl	%esi, %esi
	xorl	%edi, %edi
.LBB2_19:                               # %.lr.ph55.outer
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_20 Depth 2
                                        #       Child Loop BB2_22 Depth 3
	movl	%eax, %r8d
	imull	%esi, %r8d
.LBB2_20:                               # %.lr.ph55
                                        #   Parent Loop BB2_19 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_22 Depth 3
	movl	%r8d, %r10d
	leaq	(%rdx,%r10,4), %r9
	leaq	(%rcx,%r10,4), %r10
	xorl	%r11d, %r11d
.LBB2_22:                               #   Parent Loop BB2_19 Depth=1
                                        #     Parent Loop BB2_20 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r10,%r11,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%r9,%r11,4), %xmm0
	jne	.LBB2_23
	jp	.LBB2_23
# %bb.21:                               #   in Loop: Header=BB2_22 Depth=3
	incq	%r11
	cmpq	%r11, %rax
	jne	.LBB2_22
# %bb.25:                               # %._crit_edge56
                                        #   in Loop: Header=BB2_20 Depth=2
	incq	%rsi
	addl	%eax, %r8d
	cmpq	%rax, %rsi
	jne	.LBB2_20
	jmp	.LBB2_26
.LBB2_23:                               # %._crit_edge56.thread
                                        #   in Loop: Header=BB2_19 Depth=1
	incq	%rsi
	movb	$1, %dil
	cmpq	%rax, %rsi
	jne	.LBB2_19
	jmp	.LBB2_24
.LBB2_26:                               # %._crit_edge61
	testb	$1, %dil
	je	.LBB2_27
.LBB2_24:                               # %._crit_edge61.thread83
	movl	$.Lstr, %edi
	callq	puts@PLT
	jmp	.LBB2_28
.LBB2_27:                               # %._crit_edge61.thread
	movss	32(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	36(%rsp), %xmm0                 # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
.LBB2_28:
	xorl	%eax, %eax
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21gpu_shared_matrix_mulPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21gpu_shared_matrix_mulPfS_S_i,@object # @_Z21gpu_shared_matrix_mulPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z21gpu_shared_matrix_mulPfS_S_i
	.p2align	3, 0x0
_Z21gpu_shared_matrix_mulPfS_S_i:
	.quad	_Z36__device_stub__gpu_shared_matrix_mulPfS_S_i
	.size	_Z21gpu_shared_matrix_mulPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Enter Dimension of square matrix : "
	.size	.L.str, 36

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"GPU Time : %f seconds\n"
	.size	.L.str.2, 23

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"CPU Time : %f seconds\n"
	.size	.L.str.3, 23

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Success! Speedup : %f\n"
	.size	.L.str.4, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21gpu_shared_matrix_mulPfS_S_i"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Incorrect"
	.size	.Lstr, 10

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__gpu_shared_matrix_mulPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21gpu_shared_matrix_mulPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21gpu_shared_matrix_mulPfS_S_i ; -- Begin function _Z21gpu_shared_matrix_mulPfS_S_i
	.globl	_Z21gpu_shared_matrix_mulPfS_S_i
	.p2align	8
	.type	_Z21gpu_shared_matrix_mulPfS_S_i,@function
_Z21gpu_shared_matrix_mulPfS_S_i:       ; @_Z21gpu_shared_matrix_mulPfS_S_i
; %bb.0:
	s_clause 0x4
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v6, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s9, s8, 16
	s_and_b32 s8, s8, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s9, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s8, v[6:7]
	s_cmp_eq_u32 s3, 0
	s_mov_b32 s8, 0
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 2, v6
	v_mul_u32_u24_e32 v8, 0x64, v3
	s_mul_i32 s9, s2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 0x9d0, v2
	v_mad_u32_u24 v9, 0x64, v3, v2
	v_mov_b32_e32 v2, 0
	v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
	v_mad_u32_u24 v10, 0x64, v3, v7
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_mul_i32 s10, s8, 25
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s10, v4
	s_mov_b32 s11, exec_lo
	v_cmpx_gt_i32_e64 s9, v5
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v11, v[5:6], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v12, s10, v3
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v11
	v_mad_u64_u32 v[5:6], null, v12, s2, v[1:2]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s9, v5
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v6, v[5:6], off
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_mov_b32_e32 v5, v7
	s_mov_b32 s10, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v6, s10, v8
	s_add_i32 s10, s10, 4
	ds_load_b32 v11, v5
	ds_load_b32 v6, v6
	v_add_nc_u32_e32 v5, 0x64, v5
	s_cmpk_eq_i32 s10, 0x64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v6, v11
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_10
.LBB0_9:
	v_mov_b32_e32 v2, 0
.LBB0_10:                               ; %Flow66
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v0, v1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v3
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21gpu_shared_matrix_mulPfS_S_i
		.amdhsa_group_segment_fixed_size 5012
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21gpu_shared_matrix_mulPfS_S_i, .Lfunc_end0-_Z21gpu_shared_matrix_mulPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 540
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 5012 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 5012
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21gpu_shared_matrix_mulPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21gpu_shared_matrix_mulPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
