#include <stdio.h>
#include <inttypes.h>
#include <sys/time.h>

#define THREADS_PER_BLOCK 192

__global__
void hasher_kernel(uint32_t *B, uint32_t *Bx) {
  /* From scrypt.c */
  uint32_t j;

  /* Two iterations of salsa20_8 */
  uint32_t x00,x01,x02,x03,x04,x05,x06,x07,x08,x09,x10,x11,x12,x13,x14,x15;
  size_t i;
  __shared__ uint32_t Bcache[THREADS_PER_BLOCK*16];
  __shared__ uint32_t Bxcache[THREADS_PER_BLOCK*16];
  
	int tid = (blockIdx.x*blockDim.x) + threadIdx.x;

	// parallel test init
#if 0
	B[tid*16+0] = tid; B[tid*16+1] = tid; B[tid*16+2] = tid;
	B[tid*16+3] = tid; B[tid*16+4] = tid; B[tid*16+5] = tid;
	B[tid*16+6] = tid; B[tid*16+7] = tid; B[tid*16+8] = tid;
	B[tid*16+9] = tid; B[tid*16+10] = tid; B[tid*16+11] = tid;
	B[tid*16+12] = tid; B[tid*16+13] = tid; B[tid*16+14] = tid;
	B[tid*16+15] = tid;
#endif

	Bx[tid*16+0] = tid; Bx[tid*16+1] = tid; Bx[tid*16+2] = tid;
	Bx[tid*16+3] = tid; Bx[tid*16+4] = tid; Bx[tid*16+5] = tid;
	Bx[tid*16+6] = tid; Bx[tid*16+7] = tid; Bx[tid*16+8] = tid;
	Bx[tid*16+9] = tid; Bx[tid*16+10] = tid; Bx[tid*16+11] = tid;
	Bx[tid*16+12] = tid; Bx[tid*16+13] = tid; Bx[tid*16+14] = tid;
	Bx[tid*16+15] = tid;


	#pragma unroll
	for (int i = 0; i < 16; i++) {
	  uint32_t b, bx;
	  b = B[tid*16+0];
	  bx = Bx[tid*16+0];
	  Bxcache[threadIdx.x + (16*i)] = bx;
	  Bcache[threadIdx.x + (16*i)] = b;
	}

	/* This is adapted at the end of the iteration now */
	x00 = (Bcache[threadIdx.x + (16*0)] ^= Bxcache[threadIdx.x + (16*0)]);
	x01 = (Bcache[threadIdx.x + (16*1)] ^= Bxcache[threadIdx.x + (16*1)]);
	x02 = (Bcache[threadIdx.x + (16*2)] ^= Bxcache[threadIdx.x + (16*2)]);
	x03 = (Bcache[threadIdx.x + (16*3)] ^= Bxcache[threadIdx.x + (16*3)]);
	x04 = (Bcache[threadIdx.x + (16*4)] ^= Bxcache[threadIdx.x + (16*4)]);
	x05 = (Bcache[threadIdx.x + (16*5)] ^= Bxcache[threadIdx.x + (16*5)]);
	x06 = (Bcache[threadIdx.x + (16*6)] ^= Bxcache[threadIdx.x + (16*6)]);
	x07 = (Bcache[threadIdx.x + (16*7)] ^= Bxcache[threadIdx.x + (16*7)]);
	x08 = (Bcache[threadIdx.x + (16*8)] ^= Bxcache[threadIdx.x + (16*8)]);
	x09 = (Bcache[threadIdx.x + (16*9)] ^= Bxcache[threadIdx.x + (16*9)]);
	x10 = (Bcache[threadIdx.x + (16*10)] ^= Bxcache[threadIdx.x + (16*10)]);
	x11 = (Bcache[threadIdx.x + (16*11)] ^= Bxcache[threadIdx.x + (16*11)]);
	x12 = (Bcache[threadIdx.x + (16*12)] ^= Bxcache[threadIdx.x + (16*12)]);
	x13 = (Bcache[threadIdx.x + (16*13)] ^= Bxcache[threadIdx.x + (16*13)]);
	x14 = (Bcache[threadIdx.x + (16*14)] ^= Bxcache[threadIdx.x + (16*14)]);
	x15 = (Bcache[threadIdx.x + (16*15)] ^= Bxcache[threadIdx.x + (16*15)]);

#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
#define NITERS 2048 // should be 2048 for full version
	for (j = 0; j < NITERS; j++) {

#pragma unroll
	  for (i = 0; i < 4; i++) {
                /* Operate on columns. */
                x04 ^= R(x00+x12, 7);        x09 ^= R(x05+x01, 7);        x14 ^= R(x10+x06, 7);        x03 ^= R(x15+x11, 7);
                x08 ^= R(x04+x00, 9);        x13 ^= R(x09+x05, 9);        x02 ^= R(x14+x10, 9);        x07 ^= R(x03+x15, 9);
                x12 ^= R(x08+x04,13);        x01 ^= R(x13+x09,13);        x06 ^= R(x02+x14,13);        x11 ^= R(x07+x03,13);
                x00 ^= R(x12+x08,18);        x05 ^= R(x01+x13,18);        x10 ^= R(x06+x02,18);        x15 ^= R(x11+x07,18);

                /* Operate on rows. */
                x01 ^= R(x00+x03, 7);        x06 ^= R(x05+x04, 7);        x11 ^= R(x10+x09, 7);        x12 ^= R(x15+x14, 7);
                x02 ^= R(x01+x00, 9);        x07 ^= R(x06+x05, 9);        x08 ^= R(x11+x10, 9);        x13 ^= R(x12+x15, 9);
                x03 ^= R(x02+x01,13);        x04 ^= R(x07+x06,13);        x09 ^= R(x08+x11,13);        x14 ^= R(x13+x12,13);
                x00 ^= R(x03+x02,18);        x05 ^= R(x04+x07,18);        x10 ^= R(x09+x08,18);        x15 ^= R(x14+x13,18);
        }

#define GETBX(REG, OFFSET)			\
	REG += Bcache[threadIdx.x + (16*OFFSET)]; \
	Bcache[threadIdx.x + (16*OFFSET)] = REG; \
	REG ^= Bxcache[threadIdx.x + (16*OFFSET)]; \
	Bxcache[threadIdx.x + (16*0)] = REG

	GETBX(x00, 0);
	GETBX(x01, 1);
	GETBX(x02, 2);
	GETBX(x03, 3);
	GETBX(x04, 4);
	GETBX(x05, 5);
	GETBX(x06, 6);
	GETBX(x07, 7);
	GETBX(x08, 8);
	GETBX(x09, 9);
	GETBX(x10, 10);
	GETBX(x11, 11);
	GETBX(x12, 12);
	GETBX(x13, 13);
	GETBX(x14, 14);
	GETBX(x15, 15);

#pragma unroll
        for (i = 0; i < 4; i++) {
                /* Operate on columns. */
                x04 ^= R(x00+x12, 7);        x09 ^= R(x05+x01, 7);        x14 ^= R(x10+x06, 7);        x03 ^= R(x15+x11, 7);
                x08 ^= R(x04+x00, 9);        x13 ^= R(x09+x05, 9);        x02 ^= R(x14+x10, 9);        x07 ^= R(x03+x15, 9);
                x12 ^= R(x08+x04,13);        x01 ^= R(x13+x09,13);        x06 ^= R(x02+x14,13);        x11 ^= R(x07+x03,13);
                x00 ^= R(x12+x08,18);        x05 ^= R(x01+x13,18);        x10 ^= R(x06+x02,18);        x15 ^= R(x11+x07,18);

                /* Operate on rows. */
                x01 ^= R(x00+x03, 7);        x06 ^= R(x05+x04, 7);        x11 ^= R(x10+x09, 7);        x12 ^= R(x15+x14, 7);
                x02 ^= R(x01+x00, 9);        x07 ^= R(x06+x05, 9);        x08 ^= R(x11+x10, 9);        x13 ^= R(x12+x15, 9);
                x03 ^= R(x02+x01,13);        x04 ^= R(x07+x06,13);        x09 ^= R(x08+x11,13);        x14 ^= R(x13+x12,13);
                x00 ^= R(x03+x02,18);        x05 ^= R(x04+x07,18);        x10 ^= R(x09+x08,18);        x15 ^= R(x14+x13,18);
        }

#undef R
#define SAVEBX(REG, OFFSET)			\
	REG += Bxcache[threadIdx.x + (16*OFFSET)];	\
	Bxcache[threadIdx.x + (16*OFFSET)] = REG;	\
	/* Leave the register set for the next loop iteration and the exit */ \
	REG ^= Bcache[threadIdx.x + (16*OFFSET)] \

        SAVEBX(x00, 0);
        SAVEBX(x01, 1);
        SAVEBX(x02, 2);
        SAVEBX(x03, 3);
        SAVEBX(x04, 4);
        SAVEBX(x05, 5);
        SAVEBX(x06, 6);
        SAVEBX(x07, 7);
        SAVEBX(x08, 8);
        SAVEBX(x09, 9);
        SAVEBX(x10, 10);
        SAVEBX(x11, 11);
        SAVEBX(x12, 12);
        SAVEBX(x13, 13);
        SAVEBX(x14, 14);
        SAVEBX(x15, 15);
	}

        B[tid*16+ 0] = x00;
        B[tid*16+ 1] = x01;
        B[tid*16+ 2] = x02;
        B[tid*16+ 3] = x03;
        B[tid*16+ 4] = x04;
        B[tid*16+ 5] = x05;
        B[tid*16+ 6] = x06;
        B[tid*16+ 7] = x07;
        B[tid*16+ 8] = x08;
        B[tid*16+ 9] = x09;
        B[tid*16+10] = x10;
        B[tid*16+11] = x11;
        B[tid*16+12] = x12;
        B[tid*16+13] = x13;
        B[tid*16+14] = x14;
        B[tid*16+15] = x15;
	return;
}

double timeval_diff(const struct timeval * const start, const struct timeval * const end)
{
    /* Calculate the second difference*/
    double r = end->tv_sec - start->tv_sec;

    /* Calculate the microsecond difference */
    if (end->tv_usec > start->tv_usec)
        r += (end->tv_usec - start->tv_usec)/1000000.0;
    else if (end->tv_usec < start->tv_usec)
        r -= (start->tv_usec - end->tv_usec)/1000000.0;

    return r;
}

int main() {
#define SCRYPT_WIDTH 16
#define N 1024 * 128


  printf("hi\n");

  struct timeval tv_start, tv_end;
  uint32_t *dev_a, *dev_b;

  uint32_t *mydat = (uint32_t *)malloc(N*SCRYPT_WIDTH*sizeof(uint32_t));
  printf("First malloc\n");fflush(stdout);
  printf("Foo: %lu\n", N*SCRYPT_WIDTH*sizeof(uint32_t));fflush(stdout);
  for (int i = 0; i < N*SCRYPT_WIDTH; i++) {
    mydat[i] = i+tv_start.tv_sec; // Confuse the optimizer. 
  }
  if (cudaMalloc((void **) &dev_a, N*SCRYPT_WIDTH*sizeof(uint32_t)) != cudaSuccess) {
    fprintf(stderr, "Could not allocate array\n");
    exit(0);
  }
  gettimeofday(&tv_start, NULL);
  cudaMemcpy(dev_a, mydat, N*SCRYPT_WIDTH*sizeof(uint32_t), cudaMemcpyHostToDevice);
  printf("Second malloc\n");fflush(stdout);
  if (cudaMalloc((void **) &dev_b, N*SCRYPT_WIDTH*sizeof(uint32_t)) != cudaSuccess) {
    fprintf(stderr, "Could not allocate array\n");
    exit(0);
  }
  printf("Starting kernel\n");fflush(stdout);
  hasher_kernel<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(dev_a, dev_b);
  printf("Memcpy result\n");

  cudaMemcpy(mydat, dev_a, N*SCRYPT_WIDTH*sizeof(uint32_t), cudaMemcpyDeviceToHost);
  gettimeofday(&tv_end, NULL);
#if 1
  for (int i = 0; i < 10; i++) {
    printf("%x\n", mydat[i*SCRYPT_WIDTH]);
  }
#endif

  cudaFree(dev_a);
  cudaFree(dev_b);
  free(mydat);
  cudaDeviceReset();


  printf("%2.2f\n", timeval_diff(&tv_start, &tv_end));
  printf("Done\n");
}

	.file	"tmpxft_002253ad_00000000-6_key_per_thread.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12timeval_diffPK7timevalS1_
	.type	_Z12timeval_diffPK7timevalS1_, @function
_Z12timeval_diffPK7timevalS1_:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	(%rsi), %rax
	subq	(%rdi), %rax
	cvtsi2sdq	%rax, %xmm0
	movq	8(%rsi), %rdx
	movq	8(%rdi), %rax
	cmpq	%rax, %rdx
	jle	.L3
	subq	%rax, %rdx
	cvtsi2sdq	%rdx, %xmm1
	divsd	.LC0(%rip), %xmm1
	addsd	%xmm1, %xmm0
	ret
.L3:
	jge	.L2
	subq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm1
	divsd	.LC0(%rip), %xmm1
	subsd	%xmm1, %xmm0
.L2:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z12timeval_diffPK7timevalS1_, .-_Z12timeval_diffPK7timevalS1_
	.globl	_Z35__device_stub__Z13hasher_kernelPjS_PjS_
	.type	_Z35__device_stub__Z13hasher_kernelPjS_PjS_, @function
_Z35__device_stub__Z13hasher_kernelPjS_PjS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13hasher_kernelPjS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L6:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z35__device_stub__Z13hasher_kernelPjS_PjS_, .-_Z35__device_stub__Z13hasher_kernelPjS_PjS_
	.globl	_Z13hasher_kernelPjS_
	.type	_Z13hasher_kernelPjS_, @function
_Z13hasher_kernelPjS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z13hasher_kernelPjS_PjS_
	.cfi_endproc
.LFE2054:
	.size	_Z13hasher_kernelPjS_, .-_Z13hasher_kernelPjS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"hi\n"
.LC2:
	.string	"First malloc\n"
.LC3:
	.string	"Foo: %lu\n"
.LC4:
	.string	"Could not allocate array\n"
.LC5:
	.string	"Second malloc\n"
.LC6:
	.string	"Starting kernel\n"
.LC7:
	.string	"Memcpy result\n"
.LC8:
	.string	"%x\n"
.LC9:
	.string	"%2.2f\n"
.LC10:
	.string	"Done\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$8388608, %edi
	call	malloc@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	stdout(%rip), %rdi
	call	fflush@PLT
	movl	$8388608, %edx
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	stdout(%rip), %rdi
	call	fflush@PLT
	movl	40(%rsp), %ecx
	xorl	%eax, %eax
.L12:
	leal	(%rcx,%rax), %edx
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	cmpq	$2097152, %rax
	jne	.L12
	leaq	8(%rsp), %rdi
	movl	$8388608, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L21
	leaq	40(%rsp), %r12
	xorl	%esi, %esi
	movq	%r12, %rdi
	call	gettimeofday@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$8388608, %edx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	stdout(%rip), %rdi
	call	fflush@PLT
	leaq	16(%rsp), %rdi
	movl	$8388608, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L14
.L21:
	movq	stderr(%rip), %rdi
	leaq	.LC4(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L14:
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	stdout(%rip), %rdi
	call	fflush@PLT
	movl	$67108867, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2147483989, %edi
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	addq	%rdi, %rdi
	movq	%rdx, 56(%rsp)
	movl	$1, 64(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z35__device_stub__Z13hasher_kernelPjS_PjS_
.L15:
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	56(%rsp), %r13
	movq	%rbx, %rbp
	leaq	.LC7(%rip), %rsi
	leaq	640(%rbx), %r14
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$8388608, %edx
	leaq	.LC8(%rip), %r15
	call	cudaMemcpy@PLT
	xorl	%esi, %esi
	movq	%r13, %rdi
	call	gettimeofday@PLT
.L16:
	movl	0(%rbp), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$64, %rbp
	call	__printf_chk@PLT
	cmpq	%r14, %rbp
	jne	.L16
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	call	cudaDeviceReset@PLT
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	_Z12timeval_diffPK7timevalS1_
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC10(%rip), %rsi
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z13hasher_kernelPjS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13hasher_kernelPjS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <inttypes.h>
#include <sys/time.h>

#define THREADS_PER_BLOCK 192

__global__
void hasher_kernel(uint32_t *B, uint32_t *Bx) {
  /* From scrypt.c */
  uint32_t j;

  /* Two iterations of salsa20_8 */
  uint32_t x00,x01,x02,x03,x04,x05,x06,x07,x08,x09,x10,x11,x12,x13,x14,x15;
  size_t i;
  __shared__ uint32_t Bcache[THREADS_PER_BLOCK*16];
  __shared__ uint32_t Bxcache[THREADS_PER_BLOCK*16];
  
	int tid = (blockIdx.x*blockDim.x) + threadIdx.x;

	// parallel test init
#if 0
	B[tid*16+0] = tid; B[tid*16+1] = tid; B[tid*16+2] = tid;
	B[tid*16+3] = tid; B[tid*16+4] = tid; B[tid*16+5] = tid;
	B[tid*16+6] = tid; B[tid*16+7] = tid; B[tid*16+8] = tid;
	B[tid*16+9] = tid; B[tid*16+10] = tid; B[tid*16+11] = tid;
	B[tid*16+12] = tid; B[tid*16+13] = tid; B[tid*16+14] = tid;
	B[tid*16+15] = tid;
#endif

	Bx[tid*16+0] = tid; Bx[tid*16+1] = tid; Bx[tid*16+2] = tid;
	Bx[tid*16+3] = tid; Bx[tid*16+4] = tid; Bx[tid*16+5] = tid;
	Bx[tid*16+6] = tid; Bx[tid*16+7] = tid; Bx[tid*16+8] = tid;
	Bx[tid*16+9] = tid; Bx[tid*16+10] = tid; Bx[tid*16+11] = tid;
	Bx[tid*16+12] = tid; Bx[tid*16+13] = tid; Bx[tid*16+14] = tid;
	Bx[tid*16+15] = tid;


	#pragma unroll
	for (int i = 0; i < 16; i++) {
	  uint32_t b, bx;
	  b = B[tid*16+0];
	  bx = Bx[tid*16+0];
	  Bxcache[threadIdx.x + (16*i)] = bx;
	  Bcache[threadIdx.x + (16*i)] = b;
	}

	/* This is adapted at the end of the iteration now */
	x00 = (Bcache[threadIdx.x + (16*0)] ^= Bxcache[threadIdx.x + (16*0)]);
	x01 = (Bcache[threadIdx.x + (16*1)] ^= Bxcache[threadIdx.x + (16*1)]);
	x02 = (Bcache[threadIdx.x + (16*2)] ^= Bxcache[threadIdx.x + (16*2)]);
	x03 = (Bcache[threadIdx.x + (16*3)] ^= Bxcache[threadIdx.x + (16*3)]);
	x04 = (Bcache[threadIdx.x + (16*4)] ^= Bxcache[threadIdx.x + (16*4)]);
	x05 = (Bcache[threadIdx.x + (16*5)] ^= Bxcache[threadIdx.x + (16*5)]);
	x06 = (Bcache[threadIdx.x + (16*6)] ^= Bxcache[threadIdx.x + (16*6)]);
	x07 = (Bcache[threadIdx.x + (16*7)] ^= Bxcache[threadIdx.x + (16*7)]);
	x08 = (Bcache[threadIdx.x + (16*8)] ^= Bxcache[threadIdx.x + (16*8)]);
	x09 = (Bcache[threadIdx.x + (16*9)] ^= Bxcache[threadIdx.x + (16*9)]);
	x10 = (Bcache[threadIdx.x + (16*10)] ^= Bxcache[threadIdx.x + (16*10)]);
	x11 = (Bcache[threadIdx.x + (16*11)] ^= Bxcache[threadIdx.x + (16*11)]);
	x12 = (Bcache[threadIdx.x + (16*12)] ^= Bxcache[threadIdx.x + (16*12)]);
	x13 = (Bcache[threadIdx.x + (16*13)] ^= Bxcache[threadIdx.x + (16*13)]);
	x14 = (Bcache[threadIdx.x + (16*14)] ^= Bxcache[threadIdx.x + (16*14)]);
	x15 = (Bcache[threadIdx.x + (16*15)] ^= Bxcache[threadIdx.x + (16*15)]);

#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
#define NITERS 2048 // should be 2048 for full version
	for (j = 0; j < NITERS; j++) {

#pragma unroll
	  for (i = 0; i < 4; i++) {
                /* Operate on columns. */
                x04 ^= R(x00+x12, 7);        x09 ^= R(x05+x01, 7);        x14 ^= R(x10+x06, 7);        x03 ^= R(x15+x11, 7);
                x08 ^= R(x04+x00, 9);        x13 ^= R(x09+x05, 9);        x02 ^= R(x14+x10, 9);        x07 ^= R(x03+x15, 9);
                x12 ^= R(x08+x04,13);        x01 ^= R(x13+x09,13);        x06 ^= R(x02+x14,13);        x11 ^= R(x07+x03,13);
                x00 ^= R(x12+x08,18);        x05 ^= R(x01+x13,18);        x10 ^= R(x06+x02,18);        x15 ^= R(x11+x07,18);

                /* Operate on rows. */
                x01 ^= R(x00+x03, 7);        x06 ^= R(x05+x04, 7);        x11 ^= R(x10+x09, 7);        x12 ^= R(x15+x14, 7);
                x02 ^= R(x01+x00, 9);        x07 ^= R(x06+x05, 9);        x08 ^= R(x11+x10, 9);        x13 ^= R(x12+x15, 9);
                x03 ^= R(x02+x01,13);        x04 ^= R(x07+x06,13);        x09 ^= R(x08+x11,13);        x14 ^= R(x13+x12,13);
                x00 ^= R(x03+x02,18);        x05 ^= R(x04+x07,18);        x10 ^= R(x09+x08,18);        x15 ^= R(x14+x13,18);
        }

#define GETBX(REG, OFFSET)			\
	REG += Bcache[threadIdx.x + (16*OFFSET)]; \
	Bcache[threadIdx.x + (16*OFFSET)] = REG; \
	REG ^= Bxcache[threadIdx.x + (16*OFFSET)]; \
	Bxcache[threadIdx.x + (16*0)] = REG

	GETBX(x00, 0);
	GETBX(x01, 1);
	GETBX(x02, 2);
	GETBX(x03, 3);
	GETBX(x04, 4);
	GETBX(x05, 5);
	GETBX(x06, 6);
	GETBX(x07, 7);
	GETBX(x08, 8);
	GETBX(x09, 9);
	GETBX(x10, 10);
	GETBX(x11, 11);
	GETBX(x12, 12);
	GETBX(x13, 13);
	GETBX(x14, 14);
	GETBX(x15, 15);

#pragma unroll
        for (i = 0; i < 4; i++) {
                /* Operate on columns. */
                x04 ^= R(x00+x12, 7);        x09 ^= R(x05+x01, 7);        x14 ^= R(x10+x06, 7);        x03 ^= R(x15+x11, 7);
                x08 ^= R(x04+x00, 9);        x13 ^= R(x09+x05, 9);        x02 ^= R(x14+x10, 9);        x07 ^= R(x03+x15, 9);
                x12 ^= R(x08+x04,13);        x01 ^= R(x13+x09,13);        x06 ^= R(x02+x14,13);        x11 ^= R(x07+x03,13);
                x00 ^= R(x12+x08,18);        x05 ^= R(x01+x13,18);        x10 ^= R(x06+x02,18);        x15 ^= R(x11+x07,18);

                /* Operate on rows. */
                x01 ^= R(x00+x03, 7);        x06 ^= R(x05+x04, 7);        x11 ^= R(x10+x09, 7);        x12 ^= R(x15+x14, 7);
                x02 ^= R(x01+x00, 9);        x07 ^= R(x06+x05, 9);        x08 ^= R(x11+x10, 9);        x13 ^= R(x12+x15, 9);
                x03 ^= R(x02+x01,13);        x04 ^= R(x07+x06,13);        x09 ^= R(x08+x11,13);        x14 ^= R(x13+x12,13);
                x00 ^= R(x03+x02,18);        x05 ^= R(x04+x07,18);        x10 ^= R(x09+x08,18);        x15 ^= R(x14+x13,18);
        }

#undef R
#define SAVEBX(REG, OFFSET)			\
	REG += Bxcache[threadIdx.x + (16*OFFSET)];	\
	Bxcache[threadIdx.x + (16*OFFSET)] = REG;	\
	/* Leave the register set for the next loop iteration and the exit */ \
	REG ^= Bcache[threadIdx.x + (16*OFFSET)] \

        SAVEBX(x00, 0);
        SAVEBX(x01, 1);
        SAVEBX(x02, 2);
        SAVEBX(x03, 3);
        SAVEBX(x04, 4);
        SAVEBX(x05, 5);
        SAVEBX(x06, 6);
        SAVEBX(x07, 7);
        SAVEBX(x08, 8);
        SAVEBX(x09, 9);
        SAVEBX(x10, 10);
        SAVEBX(x11, 11);
        SAVEBX(x12, 12);
        SAVEBX(x13, 13);
        SAVEBX(x14, 14);
        SAVEBX(x15, 15);
	}

        B[tid*16+ 0] = x00;
        B[tid*16+ 1] = x01;
        B[tid*16+ 2] = x02;
        B[tid*16+ 3] = x03;
        B[tid*16+ 4] = x04;
        B[tid*16+ 5] = x05;
        B[tid*16+ 6] = x06;
        B[tid*16+ 7] = x07;
        B[tid*16+ 8] = x08;
        B[tid*16+ 9] = x09;
        B[tid*16+10] = x10;
        B[tid*16+11] = x11;
        B[tid*16+12] = x12;
        B[tid*16+13] = x13;
        B[tid*16+14] = x14;
        B[tid*16+15] = x15;
	return;
}

double timeval_diff(const struct timeval * const start, const struct timeval * const end)
{
    /* Calculate the second difference*/
    double r = end->tv_sec - start->tv_sec;

    /* Calculate the microsecond difference */
    if (end->tv_usec > start->tv_usec)
        r += (end->tv_usec - start->tv_usec)/1000000.0;
    else if (end->tv_usec < start->tv_usec)
        r -= (start->tv_usec - end->tv_usec)/1000000.0;

    return r;
}

int main() {
#define SCRYPT_WIDTH 16
#define N 1024 * 128


  printf("hi\n");

  struct timeval tv_start, tv_end;
  uint32_t *dev_a, *dev_b;

  uint32_t *mydat = (uint32_t *)malloc(N*SCRYPT_WIDTH*sizeof(uint32_t));
  printf("First malloc\n");fflush(stdout);
  printf("Foo: %lu\n", N*SCRYPT_WIDTH*sizeof(uint32_t));fflush(stdout);
  for (int i = 0; i < N*SCRYPT_WIDTH; i++) {
    mydat[i] = i+tv_start.tv_sec; // Confuse the optimizer. 
  }
  if (hipMalloc((void **) &dev_a, N*SCRYPT_WIDTH*sizeof(uint32_t)) != hipSuccess) {
    fprintf(stderr, "Could not allocate array\n");
    exit(0);
  }
  gettimeofday(&tv_start, NULL);
  hipMemcpy(dev_a, mydat, N*SCRYPT_WIDTH*sizeof(uint32_t), hipMemcpyHostToDevice);
  printf("Second malloc\n");fflush(stdout);
  if (hipMalloc((void **) &dev_b, N*SCRYPT_WIDTH*sizeof(uint32_t)) != hipSuccess) {
    fprintf(stderr, "Could not allocate array\n");
    exit(0);
  }
  printf("Starting kernel\n");fflush(stdout);
  hasher_kernel<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(dev_a, dev_b);
  printf("Memcpy result\n");

  hipMemcpy(mydat, dev_a, N*SCRYPT_WIDTH*sizeof(uint32_t), hipMemcpyDeviceToHost);
  gettimeofday(&tv_end, NULL);
#if 1
  for (int i = 0; i < 10; i++) {
    printf("%x\n", mydat[i*SCRYPT_WIDTH]);
  }
#endif

  hipFree(dev_a);
  hipFree(dev_b);
  free(mydat);
  hipDeviceReset();


  printf("%2.2f\n", timeval_diff(&tv_start, &tv_end));
  printf("Done\n");
}

	.text
	.file	"key_per_thread.hip"
	.globl	_Z28__device_stub__hasher_kernelPjS_ # -- Begin function _Z28__device_stub__hasher_kernelPjS_
	.type	_Z28__device_stub__hasher_kernelPjS_,@function
_Z28__device_stub__hasher_kernelPjS_:   # @_Z28__device_stub__hasher_kernelPjS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13hasher_kernelPjS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__hasher_kernelPjS_, .Lfunc_end0-_Z28__device_stub__hasher_kernelPjS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z12timeval_diffPK7timevalS1_
.LCPI1_0:
	.quad	0xc12e848000000000              # double -1.0E+6
.LCPI1_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z12timeval_diffPK7timevalS1_
	.type	_Z12timeval_diffPK7timevalS1_,@function
_Z12timeval_diffPK7timevalS1_:          # @_Z12timeval_diffPK7timevalS1_
	.cfi_startproc
# %bb.0:
	movq	(%rsi), %rax
	subq	(%rdi), %rax
	cvtsi2sd	%rax, %xmm0
	movq	8(%rsi), %rax
	movq	8(%rdi), %rcx
	movq	%rax, %rdx
	subq	%rcx, %rdx
	jle	.LBB1_2
# %bb.1:
	cvtsi2sd	%rdx, %xmm1
	divsd	.LCPI1_1(%rip), %xmm1
	jmp	.LBB1_4
.LBB1_2:
	jge	.LBB1_5
# %bb.3:
	subq	%rax, %rcx
	cvtsi2sd	%rcx, %xmm1
	divsd	.LCPI1_0(%rip), %xmm1
.LBB1_4:
	addsd	%xmm1, %xmm0
.LBB1_5:
	retq
.Lfunc_end1:
	.size	_Z12timeval_diffPK7timevalS1_, .Lfunc_end1-_Z12timeval_diffPK7timevalS1_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0xc12e848000000000              # double -1.0E+6
.LCPI2_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$8388608, %edi                  # imm = 0x800000
	callq	malloc
	movq	%rax, %rbx
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	stdout(%rip), %rdi
	callq	fflush
	movl	$.L.str.2, %edi
	movl	$8388608, %esi                  # imm = 0x800000
	xorl	%eax, %eax
	callq	printf
	movq	stdout(%rip), %rdi
	callq	fflush
	leaq	8(%rsp), %rdi
	movl	$8388608, %esi                  # imm = 0x800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.1:
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	8(%rsp), %rdi
	movl	$8388608, %edx                  # imm = 0x800000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	stdout(%rip), %rdi
	callq	fflush
	leaq	16(%rsp), %rdi
	movl	$8388608, %esi                  # imm = 0x800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.2:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movq	stdout(%rip), %rdi
	callq	fflush
	movabsq	$4294967488, %rdx               # imm = 0x1000000C0
	leaq	490(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z28__device_stub__hasher_kernelPjS_
.LBB2_4:
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movq	8(%rsp), %rsi
	movl	$8388608, %edx                  # imm = 0x800000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorl	%r14d, %r14d
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14), %esi
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
	addq	$64, %r14
	cmpq	$640, %r14                      # imm = 0x280
	jne	.LBB2_5
# %bb.6:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	callq	hipDeviceReset
	movq	24(%rsp), %rax
	subq	40(%rsp), %rax
	cvtsi2sd	%rax, %xmm0
	movq	32(%rsp), %rax
	movq	48(%rsp), %rcx
	movq	%rax, %rdx
	subq	%rcx, %rdx
	jle	.LBB2_8
# %bb.7:
	cvtsi2sd	%rdx, %xmm1
	divsd	.LCPI2_1(%rip), %xmm1
	jmp	.LBB2_10
.LBB2_8:
	jge	.LBB2_11
# %bb.9:
	subq	%rax, %rcx
	cvtsi2sd	%rcx, %xmm1
	divsd	.LCPI2_0(%rip), %xmm1
.LBB2_10:                               # %_Z12timeval_diffPK7timevalS1_.exit
	addsd	%xmm1, %xmm0
.LBB2_11:                               # %_Z12timeval_diffPK7timevalS1_.exit
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB2_12:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rcx
	movl	$.L.str.3, %edi
	movl	$25, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13hasher_kernelPjS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13hasher_kernelPjS_,@object   # @_Z13hasher_kernelPjS_
	.section	.rodata,"a",@progbits
	.globl	_Z13hasher_kernelPjS_
	.p2align	3, 0x0
_Z13hasher_kernelPjS_:
	.quad	_Z28__device_stub__hasher_kernelPjS_
	.size	_Z13hasher_kernelPjS_, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"Foo: %lu\n"
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Could not allocate array\n"
	.size	.L.str.3, 26

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%x\n"
	.size	.L.str.7, 4

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"%2.2f\n"
	.size	.L.str.8, 7

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13hasher_kernelPjS_"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"hi"
	.size	.Lstr, 3

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"First malloc"
	.size	.Lstr.1, 13

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Second malloc"
	.size	.Lstr.2, 14

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Starting kernel"
	.size	.Lstr.3, 16

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"Memcpy result"
	.size	.Lstr.4, 14

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"Done"
	.size	.Lstr.5, 5

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__hasher_kernelPjS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13hasher_kernelPjS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13hasher_kernelPjS_   ; -- Begin function _Z13hasher_kernelPjS_
	.globl	_Z13hasher_kernelPjS_
	.p2align	8
	.type	_Z13hasher_kernelPjS_,@function
_Z13hasher_kernelPjS_:                  ; @_Z13hasher_kernelPjS_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v2, 4, v1
	v_mov_b32_e32 v4, v1
	v_mov_b32_e32 v49, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_mov_b32_e32 v2, v1
	v_mov_b32_e32 v3, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
	v_add_co_u32 v18, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v19, vcc_lo, s1, v6, vcc_lo
	s_clause 0x3
	global_store_b128 v[7:8], v[1:4], off
	global_store_b128 v[7:8], v[1:4], off offset:16
	global_store_b128 v[7:8], v[1:4], off offset:32
	global_store_b128 v[7:8], v[1:4], off offset:48
	s_movk_i32 s0, 0x800
	global_load_b32 v2, v[18:19], off
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v6, v2, v1
	v_mov_b32_e32 v0, v1
	v_mov_b32_e32 v20, v1
	v_mov_b32_e32 v21, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v22, v1 :: v_dual_mov_b32 v11, v6
	v_dual_mov_b32 v23, v1 :: v_dual_mov_b32 v2, v6
	v_dual_mov_b32 v24, v1 :: v_dual_mov_b32 v17, v6
	v_dual_mov_b32 v25, v1 :: v_dual_mov_b32 v12, v6
	v_dual_mov_b32 v26, v1 :: v_dual_mov_b32 v15, v6
	v_dual_mov_b32 v27, v1 :: v_dual_mov_b32 v10, v6
	v_dual_mov_b32 v28, v1 :: v_dual_mov_b32 v9, v6
	v_dual_mov_b32 v29, v1 :: v_dual_mov_b32 v16, v6
	v_dual_mov_b32 v30, v1 :: v_dual_mov_b32 v33, v6
	v_dual_mov_b32 v31, v1 :: v_dual_mov_b32 v14, v6
	v_dual_mov_b32 v32, v1 :: v_dual_mov_b32 v35, v6
	v_mov_b32_e32 v7, v6
	v_mov_b32_e32 v5, v6
	v_mov_b32_e32 v4, v6
	v_mov_b32_e32 v3, v6
	v_mov_b32_e32 v13, v6
	v_mov_b32_e32 v8, v6
	v_mov_b32_e32 v34, v6
	v_mov_b32_e32 v36, v6
	v_mov_b32_e32 v37, v6
	v_mov_b32_e32 v38, v6
	v_mov_b32_e32 v39, v6
	v_mov_b32_e32 v40, v6
	v_mov_b32_e32 v41, v6
	v_mov_b32_e32 v42, v6
	v_mov_b32_e32 v43, v6
	v_mov_b32_e32 v44, v6
	v_mov_b32_e32 v45, v6
	v_mov_b32_e32 v46, v6
	v_mov_b32_e32 v47, v6
	v_mov_b32_e32 v48, v6
.LBB0_1:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v50, v6, v2
	v_add_nc_u32_e32 v51, v7, v15
	v_add_nc_u32_e32 v52, v12, v16
	v_add_nc_u32_e32 v53, v5, v13
	s_add_i32 s0, s0, -1
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_cmp_lg_u32 s0, 0
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v11, v51, v11
	v_xor_b32_e32 v4, v4, v52
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v6
	v_add_nc_u32_e32 v51, v11, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v4, v12
	v_add_nc_u32_e32 v53, v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v50, v10
	v_xor_b32_e32 v3, v51, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v10, v14
	v_add_nc_u32_e32 v51, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v4
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v50, v2
	v_xor_b32_e32 v7, v51, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v13, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v2, v10
	v_add_nc_u32_e32 v51, v7, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v8
	v_add_nc_u32_e32 v53, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v9
	v_add_nc_u32_e32 v51, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v11
	v_add_nc_u32_e32 v53, v5, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v50, v7
	v_xor_b32_e32 v16, v51, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v13, v52, v13
	v_xor_b32_e32 v2, v53, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v7, v6
	v_add_nc_u32_e32 v51, v16, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v13, v12
	v_add_nc_u32_e32 v53, v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v50, v8
	v_xor_b32_e32 v17, v51, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v52, v10
	v_xor_b32_e32 v3, v53, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v8, v7
	v_add_nc_u32_e32 v51, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v10, v13
	v_add_nc_u32_e32 v53, v3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v50, v9
	v_xor_b32_e32 v14, v51, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v52, v11
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v9, v8
	v_add_nc_u32_e32 v51, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v11, v10
	v_add_nc_u32_e32 v53, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v2
	v_add_nc_u32_e32 v51, v7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v16
	v_add_nc_u32_e32 v53, v5, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v11, v51, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v4, v52
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v6
	v_add_nc_u32_e32 v51, v11, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v4, v12
	v_add_nc_u32_e32 v53, v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v50, v10
	v_xor_b32_e32 v3, v51, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v10, v14
	v_add_nc_u32_e32 v51, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v4
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v50, v2
	v_xor_b32_e32 v7, v51, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v13, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v2, v10
	v_add_nc_u32_e32 v51, v7, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v8
	v_add_nc_u32_e32 v53, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v9
	v_add_nc_u32_e32 v51, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v11
	v_add_nc_u32_e32 v53, v5, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v50, v7
	v_xor_b32_e32 v16, v51, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v13, v52, v13
	v_xor_b32_e32 v2, v53, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v7, v6
	v_add_nc_u32_e32 v51, v16, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v13, v12
	v_add_nc_u32_e32 v53, v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v50, v8
	v_xor_b32_e32 v17, v51, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v52, v10
	v_xor_b32_e32 v3, v53, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v8, v7
	v_add_nc_u32_e32 v51, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v10, v13
	v_add_nc_u32_e32 v53, v3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v50, v9
	v_xor_b32_e32 v14, v51, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v52, v11
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v9, v8
	v_add_nc_u32_e32 v51, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v11, v10
	v_add_nc_u32_e32 v53, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v2
	v_add_nc_u32_e32 v51, v7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v16
	v_add_nc_u32_e32 v53, v5, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v11, v51, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v4, v52
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v6
	v_add_nc_u32_e32 v51, v11, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v4, v12
	v_add_nc_u32_e32 v53, v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v50, v10
	v_xor_b32_e32 v3, v51, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v10, v14
	v_add_nc_u32_e32 v51, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v4
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v50, v2
	v_xor_b32_e32 v7, v51, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v13, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v2, v10
	v_add_nc_u32_e32 v51, v7, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v8
	v_add_nc_u32_e32 v53, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v9
	v_add_nc_u32_e32 v51, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v11
	v_add_nc_u32_e32 v53, v5, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v50, v7
	v_xor_b32_e32 v16, v51, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v13, v52, v13
	v_xor_b32_e32 v2, v53, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v7, v6
	v_add_nc_u32_e32 v51, v16, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v13, v12
	v_add_nc_u32_e32 v53, v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v50, v8
	v_xor_b32_e32 v17, v51, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v52, v10
	v_xor_b32_e32 v3, v53, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v8, v7
	v_add_nc_u32_e32 v51, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v10, v13
	v_add_nc_u32_e32 v53, v3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v50, v9
	v_xor_b32_e32 v14, v51, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v52, v11
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v9, v8
	v_add_nc_u32_e32 v51, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v11, v10
	v_add_nc_u32_e32 v53, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v2
	v_add_nc_u32_e32 v51, v7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v16
	v_add_nc_u32_e32 v53, v5, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v11, v51, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v4, v52
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v6
	v_add_nc_u32_e32 v51, v11, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v4, v12
	v_add_nc_u32_e32 v53, v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v50, v10
	v_xor_b32_e32 v3, v51, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v10, v14
	v_add_nc_u32_e32 v51, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v4
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v50, v2
	v_xor_b32_e32 v7, v51, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v13, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v2, v10
	v_add_nc_u32_e32 v51, v7, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v8
	v_add_nc_u32_e32 v53, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v50, v6
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v5, v53, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v6, v9
	v_add_nc_u32_e32 v51, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v11
	v_add_nc_u32_e32 v53, v5, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v50, v7
	v_xor_b32_e32 v16, v51, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v13, v52, v13
	v_xor_b32_e32 v2, v53, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v7, v6
	v_add_nc_u32_e32 v51, v16, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v13, v12
	v_add_nc_u32_e32 v53, v2, v5
	v_add_nc_u32_e32 v34, v34, v7
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	v_add_nc_u32_e32 v39, v39, v16
	v_xor_b32_e32 v8, v50, v8
	v_xor_b32_e32 v17, v51, v17
	v_xor_b32_e32 v10, v52, v10
	v_xor_b32_e32 v3, v53, v3
	v_add_nc_u32_e32 v44, v44, v13
	v_add_nc_u32_e32 v45, v45, v2
	v_add_nc_u32_e32 v7, v8, v7
	v_add_nc_u32_e32 v16, v17, v16
	v_add_nc_u32_e32 v13, v10, v13
	v_add_nc_u32_e32 v2, v3, v2
	v_add_nc_u32_e32 v35, v35, v8
	v_alignbit_b32 v7, v7, v7, 19
	v_alignbit_b32 v16, v16, v16, 19
	v_alignbit_b32 v13, v13, v13, 19
	v_alignbit_b32 v2, v2, v2, 19
	v_xor_b32_e32 v50, v0, v34
	v_xor_b32_e32 v7, v7, v9
	v_xor_b32_e32 v9, v16, v14
	v_xor_b32_e32 v11, v13, v11
	v_xor_b32_e32 v2, v2, v4
	v_xor_b32_e32 v51, v24, v39
	v_add_nc_u32_e32 v13, v7, v8
	v_add_nc_u32_e32 v14, v9, v17
	v_add_nc_u32_e32 v16, v11, v10
	v_add_nc_u32_e32 v53, v2, v3
	v_xor_b32_e32 v52, v29, v44
	v_alignbit_b32 v8, v13, v13, 14
	v_alignbit_b32 v13, v14, v14, 14
	v_alignbit_b32 v14, v16, v16, 14
	v_alignbit_b32 v16, v53, v53, 14
	v_xor_b32_e32 v4, v30, v45
	v_xad_u32 v33, v8, v6, v33
	v_xad_u32 v38, v13, v15, v38
	v_xad_u32 v43, v14, v12, v43
	v_xad_u32 v48, v16, v5, v48
	v_add_nc_u32_e32 v36, v36, v7
	v_xor_b32_e32 v5, v1, v33
	v_xor_b32_e32 v6, v23, v38
	v_xor_b32_e32 v7, v28, v43
	v_xor_b32_e32 v1, v49, v48
	v_add_nc_u32_e32 v37, v37, v9
	v_add_nc_u32_e32 v42, v42, v11
	v_add_nc_u32_e32 v8, v5, v4
	v_add_nc_u32_e32 v9, v50, v6
	v_add_nc_u32_e32 v11, v7, v51
	v_add_nc_u32_e32 v12, v1, v52
	v_add_nc_u32_e32 v47, v47, v2
	v_alignbit_b32 v2, v8, v8, 25
	v_alignbit_b32 v8, v9, v9, 25
	v_alignbit_b32 v9, v11, v11, 25
	v_alignbit_b32 v11, v12, v12, 25
	v_add_nc_u32_e32 v41, v41, v10
	v_xor3_b32 v2, v37, v2, v22
	v_xor3_b32 v8, v42, v8, v27
	v_xor3_b32 v9, v47, v9, v32
	v_xor3_b32 v11, v36, v11, v21
	v_add_nc_u32_e32 v40, v40, v17
	v_add_nc_u32_e32 v10, v2, v5
	v_add_nc_u32_e32 v12, v8, v6
	v_add_nc_u32_e32 v13, v9, v7
	v_add_nc_u32_e32 v14, v11, v1
	v_add_nc_u32_e32 v46, v46, v3
	v_alignbit_b32 v3, v10, v10, 23
	v_alignbit_b32 v10, v12, v12, 23
	v_alignbit_b32 v12, v13, v13, 23
	v_alignbit_b32 v13, v14, v14, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v3, v41, v3, v26
	v_xor3_b32 v10, v46, v10, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v12, v35, v12, v20
	v_xor3_b32 v13, v40, v13, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v14, v3, v2
	v_add_nc_u32_e32 v15, v10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v17, v13, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v14, v14, 19
	v_alignbit_b32 v15, v15, v15, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v16, v16, v16, 19
	v_alignbit_b32 v17, v17, v17, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v14, v4
	v_xor_b32_e32 v14, v15, v50
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v16, v51
	v_xor_b32_e32 v16, v17, v52
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v17, v4, v3
	v_add_nc_u32_e32 v50, v14, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v51, v15, v12
	v_add_nc_u32_e32 v52, v16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v17, v17, v17, 14
	v_alignbit_b32 v50, v50, v50, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v51, v51, v51, 14
	v_alignbit_b32 v52, v52, v52, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v17, v5
	v_xor_b32_e32 v6, v50, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v51, v7
	v_xor_b32_e32 v17, v52, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v5, v11
	v_add_nc_u32_e32 v51, v6, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v7, v8
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v5
	v_add_nc_u32_e32 v51, v15, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v7
	v_add_nc_u32_e32 v53, v4, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v50, v12
	v_xor_b32_e32 v13, v51, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v52, v3
	v_xor_b32_e32 v10, v53, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v12, v14
	v_add_nc_u32_e32 v51, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v3, v16
	v_add_nc_u32_e32 v53, v10, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v50, v11
	v_xor_b32_e32 v2, v51, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v11, v12
	v_add_nc_u32_e32 v51, v2, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v3
	v_add_nc_u32_e32 v53, v9, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v50, v5
	v_xor_b32_e32 v6, v51, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v52, v7
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v5, v4
	v_add_nc_u32_e32 v51, v14, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v7, v15
	v_add_nc_u32_e32 v53, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v50, v2
	v_xor_b32_e32 v8, v51, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v52
	v_xor_b32_e32 v11, v53, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v2, v5
	v_add_nc_u32_e32 v51, v8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v9, v7
	v_add_nc_u32_e32 v53, v11, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v50, v3
	v_xor_b32_e32 v10, v51, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v13, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v3, v2
	v_add_nc_u32_e32 v51, v10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v9
	v_add_nc_u32_e32 v53, v13, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v50, v4
	v_xor_b32_e32 v14, v51, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v52, v15
	v_xor_b32_e32 v16, v53, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v4, v3
	v_add_nc_u32_e32 v51, v14, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v15, v12
	v_add_nc_u32_e32 v53, v16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v50, v5
	v_xor_b32_e32 v6, v51, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v52, v7
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v5, v11
	v_add_nc_u32_e32 v51, v6, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v7, v8
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v5
	v_add_nc_u32_e32 v51, v15, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v7
	v_add_nc_u32_e32 v53, v4, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v50, v12
	v_xor_b32_e32 v13, v51, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v52, v3
	v_xor_b32_e32 v10, v53, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v12, v14
	v_add_nc_u32_e32 v51, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v3, v16
	v_add_nc_u32_e32 v53, v10, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v50, v11
	v_xor_b32_e32 v2, v51, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v11, v12
	v_add_nc_u32_e32 v51, v2, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v3
	v_add_nc_u32_e32 v53, v9, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v50, v5
	v_xor_b32_e32 v6, v51, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v52, v7
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v5, v4
	v_add_nc_u32_e32 v51, v14, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v7, v15
	v_add_nc_u32_e32 v53, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v50, v2
	v_xor_b32_e32 v8, v51, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v52
	v_xor_b32_e32 v11, v53, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v2, v5
	v_add_nc_u32_e32 v51, v8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v9, v7
	v_add_nc_u32_e32 v53, v11, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v50, v3
	v_xor_b32_e32 v10, v51, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v52, v12
	v_xor_b32_e32 v13, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v3, v2
	v_add_nc_u32_e32 v51, v10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v12, v9
	v_add_nc_u32_e32 v53, v13, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v50, v4
	v_xor_b32_e32 v14, v51, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v52, v15
	v_xor_b32_e32 v16, v53, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v4, v3
	v_add_nc_u32_e32 v51, v14, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v15, v12
	v_add_nc_u32_e32 v53, v16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v50, v5
	v_xor_b32_e32 v6, v51, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v52, v7
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v5, v11
	v_add_nc_u32_e32 v51, v6, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v7, v8
	v_add_nc_u32_e32 v53, v17, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v50, v14
	v_xor_b32_e32 v15, v51, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v52, v16
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v14, v5
	v_add_nc_u32_e32 v51, v15, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v16, v7
	v_add_nc_u32_e32 v53, v4, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 23
	v_alignbit_b32 v51, v51, v51, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v50, v12
	v_xor_b32_e32 v13, v51, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v52, v3
	v_xor_b32_e32 v10, v53, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v12, v14
	v_add_nc_u32_e32 v51, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v3, v16
	v_add_nc_u32_e32 v53, v10, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 19
	v_alignbit_b32 v51, v51, v51, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v50, v11
	v_xor_b32_e32 v2, v51, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v8
	v_xor_b32_e32 v9, v53, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v11, v12
	v_add_nc_u32_e32 v51, v2, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v3
	v_add_nc_u32_e32 v53, v9, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 14
	v_alignbit_b32 v51, v51, v51, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v50, v5
	v_xor_b32_e32 v6, v51, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v52, v7
	v_xor_b32_e32 v17, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v50, v5, v4
	v_add_nc_u32_e32 v51, v14, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v7, v15
	v_add_nc_u32_e32 v53, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v50, v50, v50, 25
	v_alignbit_b32 v51, v51, v51, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v50, v50, v2
	v_xor_b32_e32 v51, v51, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v52
	v_xor_b32_e32 v11, v53, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v50, v5
	v_add_nc_u32_e32 v8, v51, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v9, v7
	v_add_nc_u32_e32 v53, v11, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v2, v2, v2, 23
	v_alignbit_b32 v8, v8, v8, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 23
	v_alignbit_b32 v53, v53, v53, 23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v2, v3
	v_xor_b32_e32 v3, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v52, v12
	v_xor_b32_e32 v10, v53, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v12, v2, v50
	v_add_nc_u32_e32 v13, v3, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v8, v9
	v_add_nc_u32_e32 v53, v10, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v12, v12, v12, 19
	v_alignbit_b32 v13, v13, v13, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 19
	v_alignbit_b32 v53, v53, v53, 19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v12, v4
	v_xor_b32_e32 v12, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v13, v52, v15
	v_xor_b32_e32 v14, v53, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v15, v4, v2
	v_add_nc_u32_e32 v16, v12, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v52, v13, v8
	v_add_nc_u32_e32 v53, v14, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v15, v15, v15, 14
	v_alignbit_b32 v16, v16, v16, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v52, v52, v52, 14
	v_alignbit_b32 v53, v53, v53, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v15, v5
	v_xor_b32_e32 v6, v16, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v52, v7
	v_xor_b32_e32 v52, v53, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v5, v11
	v_add_nc_u32_e32 v16, v6, v50
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v17, v15, v51
	v_add_nc_u32_e32 v53, v52, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v7, v7, v7, 25
	v_alignbit_b32 v16, v16, v16, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v17, v17, v17, 25
	v_alignbit_b32 v53, v53, v53, 25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v7, v12
	v_xor_b32_e32 v54, v16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v17, v14
	v_xor_b32_e32 v4, v53, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v12, v5
	v_add_nc_u32_e32 v13, v54, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v16, v14, v15
	v_add_nc_u32_e32 v17, v4, v52
	v_add_nc_u32_e32 v30, v4, v30
	v_alignbit_b32 v53, v7, v7, 23
	v_alignbit_b32 v55, v13, v13, 23
	v_alignbit_b32 v56, v16, v16, 23
	v_alignbit_b32 v17, v17, v17, 23
	v_add_nc_u32_e32 v0, v12, v0
	v_xor_b32_e32 v53, v53, v8
	v_xor_b32_e32 v55, v55, v10
	v_xor_b32_e32 v56, v56, v2
	v_xor_b32_e32 v57, v17, v3
	v_add_nc_u32_e32 v29, v14, v29
	v_add_nc_u32_e32 v3, v53, v12
	v_add_nc_u32_e32 v8, v55, v54
	v_add_nc_u32_e32 v10, v56, v14
	v_add_nc_u32_e32 v4, v57, v4
	v_add_nc_u32_e32 v20, v53, v20
	v_alignbit_b32 v3, v3, v3, 19
	v_alignbit_b32 v12, v8, v8, 19
	v_alignbit_b32 v14, v10, v10, 19
	v_alignbit_b32 v4, v4, v4, 19
	v_add_nc_u32_e32 v24, v54, v24
	v_xor_b32_e32 v11, v3, v11
	v_xor_b32_e32 v12, v12, v50
	v_xor_b32_e32 v14, v14, v51
	v_xor_b32_e32 v4, v4, v9
	v_add_nc_u32_e32 v25, v55, v25
	v_add_nc_u32_e32 v9, v11, v53
	v_add_nc_u32_e32 v50, v12, v55
	v_add_nc_u32_e32 v51, v14, v56
	v_add_nc_u32_e32 v53, v4, v57
	v_add_nc_u32_e32 v22, v12, v22
	v_add_nc_u32_e32 v32, v4, v32
	v_alignbit_b32 v4, v9, v9, 14
	v_alignbit_b32 v12, v50, v50, 14
	v_alignbit_b32 v50, v51, v51, 14
	v_alignbit_b32 v51, v53, v53, 14
	v_add_nc_u32_e32 v26, v56, v26
	v_add_nc_u32_e32 v31, v57, v31
	v_add_nc_u32_e32 v21, v11, v21
	v_add_nc_u32_e32 v27, v14, v27
	v_xad_u32 v1, v4, v5, v1
	v_xad_u32 v23, v12, v6, v23
	v_xad_u32 v28, v50, v15, v28
	v_xad_u32 v49, v51, v52, v49
	v_xor_b32_e32 v7, v0, v34
	v_xor_b32_e32 v16, v24, v39
	v_xor_b32_e32 v13, v29, v44
	v_xor_b32_e32 v2, v30, v45
	v_xor_b32_e32 v8, v20, v35
	v_xor_b32_e32 v17, v25, v40
	v_xor_b32_e32 v10, v26, v41
	v_xor_b32_e32 v3, v31, v46
	v_xor_b32_e32 v9, v21, v36
	v_xor_b32_e32 v14, v22, v37
	v_xor_b32_e32 v11, v27, v42
	v_xor_b32_e32 v4, v32, v47
	v_xor_b32_e32 v6, v1, v33
	v_xor_b32_e32 v15, v23, v38
	v_xor_b32_e32 v12, v28, v43
	v_xor_b32_e32 v5, v49, v48
	s_cbranch_scc1 .LBB0_1
; %bb.2:
	s_clause 0x3
	global_store_b128 v[18:19], v[6:9], off
	global_store_b128 v[18:19], v[14:17], off offset:16
	global_store_b128 v[18:19], v[10:13], off offset:32
	global_store_b128 v[18:19], v[2:5], off offset:48
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13hasher_kernelPjS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13hasher_kernelPjS_, .Lfunc_end0-_Z13hasher_kernelPjS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6104
; NumSgprs: 18
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13hasher_kernelPjS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13hasher_kernelPjS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
