#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>

__global__ void sumRandC(int* A, int* B, int m, int n, int k=1)
{
    // m -> number of rows in A
    // n-> number of columns in A
    int id;
    int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
    int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
    int _id = threadId * k;
    for(id = _id; id<(k+_id); ++id)
    {
        int cno,rno;
        cno = id%n;
        rno = id/n;
        // B has capital indexing
        int N = n+1;
        // int M = m+1;
        // matrix dimensions m,n:
        // A[rno][cno]-> id = rno*n+cno;
        if(rno<m)
        {
            // What we are actually doing (in sequential):
            // B[rno][cno]=A[rno][cno]; //A[rno][cno] = A[id];
            // B[rno][n] += A[rno][cno];
            // B[m][cno] += A[rno][cno];
            int idB = rno*N + cno;
            B[idB] = A[id];
            atomicAdd(&B[rno*N + n], A[id]);
            atomicAdd(&B[m*N + cno], A[id]); 
            atomicAdd(&B[m*N + n], A[id]); //Adding all elements to bottom right corner
        }
    }
}

__global__ void findMin(int* B, int m, int n, int k=1)
{
    int id;
    int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
    int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
    int _id = threadId * k;
    for(id = _id; id<(k+_id); ++id)
    {
        int cno,rno;
        cno = id%(n+1);
        rno = id/(n+1);
        if(rno<=m)
        {
            if(cno == n)
            {
                atomicMin(&B[m*(n+1) + n], B[rno*(n+1) + cno]);
            }
            else if(rno == m)
            {
                atomicMin(&B[m*(n+1) + n], B[rno*(n+1) + cno]);
            }
        }
    }
}

__global__ void updameMin(int* A, int* B, int m, int n, int k=1)
{
    int id;
    int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
    int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
    int _id = threadId * k;
    int mn = B[m*(n+1) + n];
    for(id = _id; id<(k+_id); ++id)
    {
        int cno,rno;
        cno = id%(n+1);
        rno = id/(n+1);
        if(rno<m && cno<n)
        {
            B[id] += mn;
        }
    }
}

int main()
{
    int n,i,j,m,k;
    scanf("%d", &m);
    scanf("%d", &n);
    scanf("%d", &k);
    int *a,*b,*sol, *A;
    a = (int *) malloc (m*n*sizeof(int));
    sol = (int *) malloc ((m+1)*(n+1)*sizeof(int));
    // Reading in input
    for(i=0;i<m*n;++i)
        scanf("%d", &a[i]);

    cudaMalloc(&b,(n+1)*(m+1)*sizeof(int));
    cudaMalloc(&A,n*m*sizeof(int));
    cudaMemcpy(A,a,n*m*sizeof(int),cudaMemcpyHostToDevice);

    // Block dimensions can be changed here:
    dim3 blockD(5,5,1);
    // Grid dimensions can be changed here:
    dim3 gridD(5,5,1);
    
    // k for each function is the last argument inthe following function calls and can be changed:
    sumRandC<<<gridD,blockD>>>(A,b,m,n,2);
    findMin<<<gridD,blockD>>>(b,m,n,3);
    updameMin<<<gridD,blockD>>>(A,b,m,n,4);
    
    cudaDeviceSynchronize();
    cudaMemcpy(sol,b,(n+1)*(m+1)*sizeof(int),cudaMemcpyDeviceToHost);
    for(i=0;i<(m+1);i++)
    {
        for(j=0;j<(n+1);j++)
            printf("%d ",sol[(n+1)*i+j]);
        printf("\n");
    }
    return 0;
}

	.file	"tmpxft_00205e19_00000000-6_A2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii
	.type	_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii, @function
_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8sumRandCPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii, .-_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii
	.globl	_Z8sumRandCPiS_iii
	.type	_Z8sumRandCPiS_iii, @function
_Z8sumRandCPiS_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii
	.cfi_endproc
.LFE2053:
	.size	_Z8sumRandCPiS_iii, .-_Z8sumRandCPiS_iii
	.globl	_Z29__device_stub__Z7findMinPiiiiPiiii
	.type	_Z29__device_stub__Z7findMinPiiiiPiiii, @function
_Z29__device_stub__Z7findMinPiiiiPiiii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7findMinPiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z29__device_stub__Z7findMinPiiiiPiiii, .-_Z29__device_stub__Z7findMinPiiiiPiiii
	.globl	_Z7findMinPiiii
	.type	_Z7findMinPiiii, @function
_Z7findMinPiiii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7findMinPiiiiPiiii
	.cfi_endproc
.LFE2055:
	.size	_Z7findMinPiiii, .-_Z7findMinPiiii
	.globl	_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii
	.type	_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9updameMinPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii, .-_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii
	.globl	_Z9updameMinPiS_iii
	.type	_Z9updameMinPiS_iii, @function
_Z9updameMinPiS_iii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii
	.cfi_endproc
.LFE2057:
	.size	_Z9updameMinPiS_iii, .-_Z9updameMinPiS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
.LC1:
	.string	"%d "
.LC2:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	leaq	.LC0(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%r12, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rsi
	call	__isoc23_scanf@PLT
	leaq	4(%rsp), %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	12(%rsp), %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	8(%rsp), %ebx
	movl	4(%rsp), %r13d
	movl	%ebx, %edi
	imull	%r13d, %edi
	incl	%r13d
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	leal	1(%rbx), %edi
	imull	%r13d, %edi
	movq	%rax, %rbp
	xorl	%r13d, %r13d
	movq	%rbp, %r14
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, %rbx
.L19:
	movl	8(%rsp), %edx
	movl	4(%rsp), %eax
	movl	%edx, %ecx
	imull	%eax, %ecx
	cmpl	%r13d, %ecx
	jle	.L30
	movq	%r14, %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	incl	%r13d
	call	__isoc23_scanf@PLT
	addq	$4, %r14
	jmp	.L19
.L30:
	incl	%edx
	leal	1(%rax), %esi
	leaq	16(%rsp), %rdi
	imull	%edx, %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	4(%rsp), %esi
	imull	8(%rsp), %esi
	leaq	24(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	4(%rsp), %edx
	imull	8(%rsp), %edx
	movq	%rbp, %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$21474836485, %rdi
	movl	$1, %esi
	movl	$1, 40(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movl	4(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	$2, %r8d
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z32__device_stub__Z8sumRandCPiS_iiiPiS_iii
.L21:
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movl	4(%rsp), %edx
	movl	8(%rsp), %esi
	movl	$3, %ecx
	movq	16(%rsp), %rdi
	call	_Z29__device_stub__Z7findMinPiiiiPiiii
.L22:
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	4(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	$4, %r8d
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z33__device_stub__Z9updameMinPiS_iiiPiS_iii
.L23:
	call	cudaDeviceSynchronize@PLT
	movl	4(%rsp), %eax
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	leaq	.LC1(%rip), %rbp
	leal	1(%rax), %edx
	movl	8(%rsp), %eax
	incl	%eax
	imull	%eax, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
.L24:
	cmpl	%r12d, 8(%rsp)
	jl	.L31
	xorl	%r13d, %r13d
.L26:
	movl	4(%rsp), %eax
	cmpl	%r13d, %eax
	jl	.L32
	incl	%eax
	movq	%rbp, %rsi
	movl	$2, %edi
	imull	%r12d, %eax
	addl	%r13d, %eax
	incl	%r13d
	cltq
	movl	(%rbx,%rax,4), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L26
.L32:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%r12d
	call	__printf_chk@PLT
	jmp	.L24
.L31:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z9updameMinPiS_iii"
.LC4:
	.string	"_Z7findMinPiiii"
.LC5:
	.string	"_Z8sumRandCPiS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9updameMinPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7findMinPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8sumRandCPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<hip/hip_runtime.h>


__global__ void sumRandC(int* A, int* B, int m, int n, int k=1)
{
    // m -> number of rows in A
    // n-> number of columns in A
    int id;
    int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
    int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
    int _id = threadId * k;
    for(id = _id; id<(k+_id); ++id)
    {
        int cno,rno;
        cno = id%n;
        rno = id/n;
        // B has capital indexing
        int N = n+1;
        // int M = m+1;
        // matrix dimensions m,n:
        // A[rno][cno]-> id = rno*n+cno;
        if(rno<m)
        {
            // What we are actually doing (in sequential):
            // B[rno][cno]=A[rno][cno]; //A[rno][cno] = A[id];
            // B[rno][n] += A[rno][cno];
            // B[m][cno] += A[rno][cno];
            int idB = rno*N + cno;
            B[idB] = A[id];
            atomicAdd(&B[rno*N + n], A[id]);
            atomicAdd(&B[m*N + cno], A[id]); 
            atomicAdd(&B[m*N + n], A[id]); //Adding all elements to bottom right corner
        }
    }
}

__global__ void findMin(int* B, int m, int n, int k=1)
{
    int id;
    int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
    int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
    int _id = threadId * k;
    for(id = _id; id<(k+_id); ++id)
    {
        int cno,rno;
        cno = id%(n+1);
        rno = id/(n+1);
        if(rno<=m)
        {
            if(cno == n)
            {
                atomicMin(&B[m*(n+1) + n], B[rno*(n+1) + cno]);
            }
            else if(rno == m)
            {
                atomicMin(&B[m*(n+1) + n], B[rno*(n+1) + cno]);
            }
        }
    }
}

__global__ void updameMin(int* A, int* B, int m, int n, int k=1)
{
    int id;
    int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
    int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
    int _id = threadId * k;
    int mn = B[m*(n+1) + n];
    for(id = _id; id<(k+_id); ++id)
    {
        int cno,rno;
        cno = id%(n+1);
        rno = id/(n+1);
        if(rno<m && cno<n)
        {
            B[id] += mn;
        }
    }
}

int main()
{
    int n,i,j,m,k;
    scanf("%d", &m);
    scanf("%d", &n);
    scanf("%d", &k);
    int *a,*b,*sol, *A;
    a = (int *) malloc (m*n*sizeof(int));
    sol = (int *) malloc ((m+1)*(n+1)*sizeof(int));
    // Reading in input
    for(i=0;i<m*n;++i)
        scanf("%d", &a[i]);

    hipMalloc(&b,(n+1)*(m+1)*sizeof(int));
    hipMalloc(&A,n*m*sizeof(int));
    hipMemcpy(A,a,n*m*sizeof(int),hipMemcpyHostToDevice);

    // Block dimensions can be changed here:
    dim3 blockD(5,5,1);
    // Grid dimensions can be changed here:
    dim3 gridD(5,5,1);
    
    // k for each function is the last argument inthe following function calls and can be changed:
    sumRandC<<<gridD,blockD>>>(A,b,m,n,2);
    findMin<<<gridD,blockD>>>(b,m,n,3);
    updameMin<<<gridD,blockD>>>(A,b,m,n,4);
    
    hipDeviceSynchronize();
    hipMemcpy(sol,b,(n+1)*(m+1)*sizeof(int),hipMemcpyDeviceToHost);
    for(i=0;i<(m+1);i++)
    {
        for(j=0;j<(n+1);j++)
            printf("%d ",sol[(n+1)*i+j]);
        printf("\n");
    }
    return 0;
}

	.text
	.file	"A2.hip"
	.globl	_Z23__device_stub__sumRandCPiS_iii # -- Begin function _Z23__device_stub__sumRandCPiS_iii
	.type	_Z23__device_stub__sumRandCPiS_iii,@function
_Z23__device_stub__sumRandCPiS_iii:     # @_Z23__device_stub__sumRandCPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8sumRandCPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__sumRandCPiS_iii, .Lfunc_end0-_Z23__device_stub__sumRandCPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__findMinPiiii # -- Begin function _Z22__device_stub__findMinPiiii
	.type	_Z22__device_stub__findMinPiiii,@function
_Z22__device_stub__findMinPiiii:        # @_Z22__device_stub__findMinPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7findMinPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__findMinPiiii, .Lfunc_end1-_Z22__device_stub__findMinPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__updameMinPiS_iii # -- Begin function _Z24__device_stub__updameMinPiS_iii
	.type	_Z24__device_stub__updameMinPiS_iii,@function
_Z24__device_stub__updameMinPiS_iii:    # @_Z24__device_stub__updameMinPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9updameMinPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__updameMinPiS_iii, .Lfunc_end2-_Z24__device_stub__updameMinPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsp, %rbx
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	leaq	4(%rsp), %r14
	movl	$.L.str, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	leaq	28(%rsp), %rsi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%rbx), %ebx
	movl	(%r14), %ebp
	movl	%ebp, %eax
	imull	%ebx, %eax
	movslq	%eax, %r14
	leaq	(,%r14,4), %rdi
	callq	malloc
	movq	%rax, %r15
	incl	%ebx
	incl	%ebp
	imull	%ebx, %ebp
	movslq	%ebp, %r12
	shlq	$2, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbx
	testl	%r14d, %r14d
	jle	.LBB3_4
# %bb.1:                                # %.lr.ph.preheader
	movq	%r15, %r14
	xorl	%r12d, %r12d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r12
	movl	(%rsp), %eax
	movl	4(%rsp), %ecx
	movl	%ecx, %edx
	imull	%eax, %edx
	movslq	%edx, %rdx
	addq	$4, %r14
	cmpq	%rdx, %r12
	jl	.LBB3_2
# %bb.3:                                # %._crit_edge.loopexit
	incl	%ecx
	incl	%eax
	imull	%ecx, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
.LBB3_4:                                # %._crit_edge
	movabsq	$21474836485, %r14              # imm = 0x500000005
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	(%rsp), %edx
	movl	4(%rsp), %ecx
	movl	$2, %r8d
	callq	_Z23__device_stub__sumRandCPiS_iii
.LBB3_6:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	8(%rsp), %rdi
	movl	(%rsp), %esi
	movl	4(%rsp), %edx
	movl	$3, %ecx
	callq	_Z22__device_stub__findMinPiiii
.LBB3_8:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	(%rsp), %edx
	movl	4(%rsp), %ecx
	movl	$4, %r8d
	callq	_Z24__device_stub__updameMinPiS_iii
.LBB3_10:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movslq	4(%rsp), %rax
	incq	%rax
	movslq	(%rsp), %rdx
	incq	%rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, (%rsp)
	js	.LBB3_16
# %bb.11:                               # %.preheader.preheader
	xorl	%r14d, %r14d
.LBB3_12:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_14 Depth 2
	movl	4(%rsp), %eax
	testl	%eax, %eax
	js	.LBB3_15
# %bb.13:                               # %.lr.ph55.preheader
                                        #   in Loop: Header=BB3_12 Depth=1
	xorl	%r15d, %r15d
.LBB3_14:                               # %.lr.ph55
                                        #   Parent Loop BB3_12 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	incl	%eax
	imull	%r14d, %eax
	cltq
	addq	%r15, %rax
	movl	(%rbx,%rax,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	4(%rsp), %eax
	incq	%r15
	leal	-1(%r15), %ecx
	cmpl	%eax, %ecx
	jl	.LBB3_14
.LBB3_15:                               # %._crit_edge56
                                        #   in Loop: Header=BB3_12 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	leal	1(%r14), %eax
	cmpl	(%rsp), %r14d
	movl	%eax, %r14d
	jl	.LBB3_12
.LBB3_16:                               # %._crit_edge59
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8sumRandCPiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7findMinPiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9updameMinPiS_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8sumRandCPiS_iii,@object      # @_Z8sumRandCPiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z8sumRandCPiS_iii
	.p2align	3, 0x0
_Z8sumRandCPiS_iii:
	.quad	_Z23__device_stub__sumRandCPiS_iii
	.size	_Z8sumRandCPiS_iii, 8

	.type	_Z7findMinPiiii,@object         # @_Z7findMinPiiii
	.globl	_Z7findMinPiiii
	.p2align	3, 0x0
_Z7findMinPiiii:
	.quad	_Z22__device_stub__findMinPiiii
	.size	_Z7findMinPiiii, 8

	.type	_Z9updameMinPiS_iii,@object     # @_Z9updameMinPiS_iii
	.globl	_Z9updameMinPiS_iii
	.p2align	3, 0x0
_Z9updameMinPiS_iii:
	.quad	_Z24__device_stub__updameMinPiS_iii
	.size	_Z9updameMinPiS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8sumRandCPiS_iii"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7findMinPiiii"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9updameMinPiS_iii"
	.size	.L__unnamed_3, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__sumRandCPiS_iii
	.addrsig_sym _Z22__device_stub__findMinPiiii
	.addrsig_sym _Z24__device_stub__updameMinPiS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8sumRandCPiS_iii
	.addrsig_sym _Z7findMinPiiii
	.addrsig_sym _Z9updameMinPiS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8sumRandCPiS_iii      ; -- Begin function _Z8sumRandCPiS_iii
	.globl	_Z8sumRandCPiS_iii
	.p2align	8
	.type	_Z8sumRandCPiS_iii,@function
_Z8sumRandCPiS_iii:                     ; @_Z8sumRandCPiS_iii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_8
; %bb.1:                                ; %.lr.ph
	s_clause 0x2
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b64 s[10:11], s[0:1], 0x2c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_add_i32 s7, s5, 1
	v_bfe_u32 v1, v0, 20, 10
	s_mul_i32 s7, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s16, s7, s5
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[16:17], 2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s9, s9, s15
	s_and_b32 s12, s11, 0xffff
	s_add_i32 s9, s9, s14
	s_lshr_b32 s14, s10, 16
	s_mul_i32 s8, s9, s8
	s_and_b32 s15, s10, 0xffff
	s_add_i32 s13, s8, s13
	s_add_u32 s8, s2, s16
	s_addc_u32 s9, s3, s17
	s_ashr_i32 s10, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s11, s5, s10
	s_xor_b32 s11, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s11
	v_rcp_iflag_f32_e32 v4, v2
	v_mad_u64_u32 v[2:3], null, s13, s12, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_sub_i32 s12, 0, s11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v4
	v_mad_u64_u32 v[3:4], null, v2, s14, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v5
	v_mad_u64_u32 v[1:2], null, v3, s15, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s12, v4
	v_mul_lo_u32 v0, v1, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v4, v2
	v_add_nc_u32_e32 v2, s6, v0
	s_mov_b32 s6, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, v4, v1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v0, v1
	v_xor_b32_e32 v5, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v3
	v_mul_lo_u32 v7, v6, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v6
	v_subrev_nc_u32_e32 v8, s11, v5
	v_cmp_le_u32_e32 vcc_lo, s11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
	v_xor_b32_e32 v8, s10, v1
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s11, v5
	v_cndmask_b32_e32 v5, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v8
	v_sub_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v5
	s_cbranch_execz .LBB0_7
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_mul_lo_u32 v8, v5, s5
	s_mov_b32 s13, exec_lo
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v0, v8
	v_add_nc_u32_e32 v5, v8, v5
	global_load_b32 v1, v[6:7], off
	v_add_nc_u32_e32 v8, v12, v5
	v_add_nc_u32_e32 v10, s5, v5
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v8, vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[8:9], v1, off
	global_atomic_add_u32 v[10:11], v1, off
	global_load_b32 v1, v[6:7], off
	v_add_nc_u32_e32 v8, s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_waitcnt vmcnt(0)
	global_atomic_add_u32 v[8:9], v1, off
	global_load_b32 v1, v[6:7], off
.LBB0_4:                                ; %ComputeLoop
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s15, s13
	s_waitcnt vmcnt(0)
	v_readlane_b32 s16, v1, s15
	s_lshl_b32 s15, 1, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s13, s13, s15
	s_add_i32 s14, s14, s16
	s_cmp_lg_u32 s13, 0
	s_cbranch_scc1 .LBB0_4
; %bb.5:                                ; %ComputeEnd
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v1, s14
	global_atomic_add_u32 v4, v1, s[8:9]
.LBB0_7:                                ; %Flow74
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v0, v2
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_2
.LBB0_8:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8sumRandCPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8sumRandCPiS_iii, .Lfunc_end0-_Z8sumRandCPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 732
; NumSgprs: 20
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z7findMinPiiii         ; -- Begin function _Z7findMinPiiii
	.globl	_Z7findMinPiiii
	.p2align	8
	.type	_Z7findMinPiiii,@function
_Z7findMinPiiii:                        ; @_Z7findMinPiiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB1_15
; %bb.1:                                ; %.lr.ph
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b64 s[10:11], s[0:1], 0x24
	s_load_b64 s[0:1], s[0:1], 0x0
	s_add_i32 s7, s5, 1
	v_bfe_u32 v1, v0, 20, 10
	s_mul_i32 s8, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s16, s8, s5
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[16:17], 2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_and_b32 s11, s11, 0xffff
	s_add_i32 s3, s3, s14
	s_lshr_b32 s12, s10, 16
	s_mul_i32 s2, s3, s2
	s_and_b32 s14, s10, 0xffff
	s_add_i32 s13, s2, s13
	s_add_u32 s2, s0, s16
	s_addc_u32 s3, s1, s17
	s_ashr_i32 s9, s7, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s7, s9
	s_xor_b32 s10, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s10
	v_rcp_iflag_f32_e32 v4, v2
	v_mad_u64_u32 v[2:3], null, s13, s11, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_sub_i32 s11, 0, s10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v4
	v_mad_u64_u32 v[3:4], null, v2, s12, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v4, v5
	v_mov_b32_e32 v5, 0
	v_mad_u64_u32 v[1:2], null, v3, s14, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s11, v4
	s_mov_b32 s11, 0
	v_mul_lo_u32 v2, v1, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v4, v0
	v_add_nc_u32_e32 v3, s6, v2
	s_mov_b32 s6, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v0
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_11 Depth 2
	v_ashrrev_i32_e32 v0, 31, v2
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v2, v0
	v_xor_b32_e32 v1, v1, v0
	v_xor_b32_e32 v0, s9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v1, v4
	v_mul_lo_u32 v7, v6, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v7
	v_add_nc_u32_e32 v7, 1, v6
	v_subrev_nc_u32_e32 v8, s10, v1
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v1, v1, v8
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	v_cndmask_b32_e32 v1, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v6, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_i32_e64 s4, v6
	s_cbranch_execz .LBB1_14
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mul_lo_u32 v0, v6, s7
	s_mov_b32 s13, 0
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v2, v0
                                        ; implicit-def: $vgpr0
	v_cmpx_ne_u32_e64 s5, v1
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB1_7
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $vgpr0
	v_cmpx_eq_u32_e64 s4, v6
	s_xor_b32 s15, exec_lo, s15
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s13, exec_lo
	v_add_nc_u32_e32 v0, s8, v1
; %bb.6:                                ; %Flow70
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s13, s13, exec_lo
                                        ; implicit-def: $vgpr6
.LBB1_7:                                ; %Flow69
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_saveexec_b32 s14, s14
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[0:1], null, v6, s7, s[6:7]
	s_or_b32 s13, s13, exec_lo
; %bb.9:                                ; %Flow71
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB1_14
; %bb.10:                               ; %.sink.split
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s14, exec_lo
	s_brev_b32 s13, -2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
.LBB1_11:                               ; %ComputeLoop
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s15, s14
	s_waitcnt vmcnt(0)
	v_readlane_b32 s16, v0, s15
	s_lshl_b32 s15, 1, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s14, s14, s15
	s_min_i32 s13, s13, s16
	s_cmp_lg_u32 s14, 0
	s_cbranch_scc1 .LBB1_11
; %bb.12:                               ; %ComputeEnd
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB1_14
; %bb.13:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v0, s13
	global_atomic_min_i32 v5, v0, s[2:3]
.LBB1_14:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v2, v3
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_2
.LBB1_15:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7findMinPiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7findMinPiiii, .Lfunc_end1-_Z7findMinPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 676
; NumSgprs: 20
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9updameMinPiS_iii     ; -- Begin function _Z9updameMinPiS_iii
	.globl	_Z9updameMinPiS_iii
	.p2align	8
	.type	_Z9updameMinPiS_iii,@function
_Z9updameMinPiS_iii:                    ; @_Z9updameMinPiS_iii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB2_5
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x2
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b64 s[10:11], s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_add_i32 s12, s5, 1
	v_bfe_u32 v1, v0, 20, 10
	s_mul_i32 s0, s12, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s5
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s9, s15
	s_and_b32 s11, s11, 0xffff
	s_add_i32 s7, s7, s14
	s_lshr_b32 s14, s10, 16
	s_mul_i32 s7, s7, s8
	s_and_b32 s10, s10, 0xffff
	s_add_i32 s13, s7, s13
	s_add_u32 s8, s2, s0
	s_addc_u32 s9, s3, s1
	s_ashr_i32 s1, s12, 31
	s_load_b32 s8, s[8:9], 0x0
	s_add_i32 s0, s12, s1
	s_sub_i32 s9, 0, s12
	s_xor_b32 s7, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s7
	s_sub_i32 s0, 0, s7
	v_rcp_iflag_f32_e32 v4, v2
	v_mad_u64_u32 v[2:3], null, s13, s11, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v4
	v_mad_u64_u32 v[3:4], null, v2, s14, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v5
	v_mad_u64_u32 v[1:2], null, v3, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s0, v4
	v_mul_lo_u32 v0, v1, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v4, v2
	v_add_nc_u32_e32 v2, s6, v0
	s_mov_b32 s6, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v1
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v0, v1
	v_xor_b32_e32 v4, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v3
	v_mul_lo_u32 v6, v5, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v6
	v_add_nc_u32_e32 v6, 1, v5
	v_subrev_nc_u32_e32 v7, s7, v4
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v4, v4, v7
	v_xor_b32_e32 v7, s1, v1
	v_add_nc_u32_e32 v6, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	v_cndmask_b32_e32 v4, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v7
	v_sub_nc_u32_e32 v6, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s9, v6, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s4, v6
	v_cmp_gt_i32_e64 s0, s5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, vcc_lo, s0
	s_and_saveexec_b32 s0, s10
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v1, s8, v1
	global_store_b32 v[4:5], v1, off
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v0, v2
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB2_2
.LBB2_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9updameMinPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9updameMinPiS_iii, .Lfunc_end2-_Z9updameMinPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 508
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
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    .name:           _Z8sumRandCPiS_iii
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
