#include <cassert>
#include <cstdlib>
#include <iostream>

#define MASK_DIM 7

#define MASK_OFFSET (MASK_DIM / 2)

__constant__ int mask[7 * 7];

__global__ void conv2d(int *matrix, int *result, int N) {
  int y = blockIdx.y * blockDim.y + threadIdx.y; 
  int x = blockIdx.x * blockDim.x + threadIdx.x; 

  int s_y = y - MASK_OFFSET;
  int s_x = x - MASK_OFFSET;

  int temp = 0;
  for (int i = 0; i < MASK_DIM; i++) {
    for (int j = 0; j < MASK_DIM; j++) {
      if((s_y + i) >= 0 && (s_y + i) < N) {
        if((s_x + j) >= 0 && (s_x + j) < N) {
          temp += matrix[N * (s_y + i) + (s_x + j)] * mask[MASK_DIM * i + j];
        }
      }
    }
  }

  result[N * y + x] = temp;
}

void init_matrix(int *m, int n) {
  for (int i = 0; i < n; i++) {
    for (int j = 0; j < n; j++) {
      m[n * i + j] = rand() % 100;
    }
  }
}

void verify_result(int *matrix, int *result, int *mask, int N) {
  int temp, o_y, o_x;
  
  for(int y = 0; y < N; y++) {
    for(int x = 0; x < N; x++) {
      temp = 0; 
      for (int i = 0; i < MASK_DIM; i++) {
        o_y = y - MASK_OFFSET + i; 
        for (int j = 0; j < MASK_DIM; j++) {  
          o_x = x - MASK_OFFSET + j;
          if(o_y >= 0 && o_y < N) {
            if(o_x >=0 && o_x < N) {
              temp += matrix[N * o_y + o_x] * mask[MASK_DIM * i + j];
            }
          }
        }
      }

      assert(result[N * y + x] == temp);
    }
  }

  printf("result[%d] = %d == %d = temp \n", N * N - 1, result[N * N - 1], temp);
}

int main() {
  int N = 1 << 10;

  size_t bytes_n = sizeof(int) * N * N;
  size_t bytes_m = sizeof(int) * MASK_DIM * MASK_DIM;

  int *matrix = new int[N * N];
  init_matrix(matrix, N);

  int *result = new int[N * N]; 

  int *h_mask = new int[MASK_DIM * MASK_DIM];
  init_matrix(h_mask, MASK_DIM);

  int *d_matrix, *d_result;
  cudaMalloc(&d_matrix, bytes_n); cudaMalloc(&d_result, bytes_n);

  cudaMemcpy(d_matrix, matrix, bytes_n, cudaMemcpyHostToDevice);
  cudaMemcpyToSymbol(mask, h_mask, bytes_m);

  int n_threads = 32;
  int n_blocks = (N + n_threads - 1) / n_threads;

  printf("%d, %d; ", n_threads, n_blocks);

  dim3 block_dim(n_threads, n_threads);
  dim3 grid_dim(n_blocks, n_blocks);

  conv2d<<<grid_dim, block_dim>>>(d_matrix, d_result, N);

  cudaMemcpy(result, d_result, bytes_n, cudaMemcpyDeviceToHost);

  verify_result(matrix, result, h_mask, N);

  std::cout << "COMPLETED SUCCESSFULLY! \n";

  delete[] matrix; delete[] result; delete[] h_mask;
  cudaFree(d_matrix); cudaFree(d_result);

  return 0;
}



	.file	"tmpxft_003abb18_00000000-6_conv2d.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11init_matrixPii
	.type	_Z11init_matrixPii, @function
_Z11init_matrixPii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$100, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movslq	%esi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r13, %rbp
	salq	$2, %r13
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 64
.L3:
	cmpl	%ebp, %r12d
	jge	.L9
	leaq	(%rbx,%r13), %r15
.L4:
	call	rand@PLT
	addq	$4, %rbx
	cltd
	idivl	%r14d
	movl	%edx, -4(%rbx)
	cmpq	%r15, %rbx
	jne	.L4
	incl	%r12d
	jmp	.L3
.L9:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z11init_matrixPii, .-_Z11init_matrixPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"result[%d] = %d == %d = temp \n"
	.text
	.globl	_Z13verify_resultPiS_S_i
	.type	_Z13verify_resultPiS_S_i, @function
_Z13verify_resultPiS_S_i:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	imull	$-3, %ecx, %r10d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leal	-3(%rcx), %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, -32(%rsp)
	movq	%rsi, -24(%rsp)
	movl	$-3, %esi
	movq	%rdx, -16(%rsp)
	movl	%ecx, %edx
.L11:
	leal	3(%rsi), %eax
	cmpl	%eax, %edx
	jle	.L16
	movl	$-3, %ecx
.L17:
	movl	%r10d, %ebx
	movl	%esi, %r9d
	xorl	%edi, %edi
	xorl	%r8d, %r8d
	leal	7(%rcx), %r15d
.L14:
	movl	%ecx, %eax
	movl	%edi, %ebp
.L13:
	cmpl	%r9d, %edx
	jle	.L12
	movl	%eax, %r13d
	orl	%r9d, %r13d
	js	.L12
	cmpl	%eax, %edx
	jle	.L12
	movq	-32(%rsp), %r11
	leal	(%rax,%rbx), %r12d
	movslq	%ebp, %r13
	movslq	%r12d, %r12
	movl	(%r11,%r12,4), %r12d
	movq	-16(%rsp), %r11
	imull	(%r11,%r13,4), %r12d
	addl	%r12d, %r8d
.L12:
	incl	%eax
	incl	%ebp
	cmpl	%r15d, %eax
	jne	.L13
	addl	$7, %edi
	incl	%r9d
	addl	%edx, %ebx
	cmpl	$49, %edi
	jne	.L14
	incl	%ecx
	cmpl	%r14d, %ecx
	jne	.L17
	incl	%esi
	addl	%edx, %r10d
	jmp	.L11
.L16:
	imull	%edx, %edx
	movq	-24(%rsp), %rbx
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movslq	%edx, %rax
	decl	%edx
	movl	-4(%rbx,%rax,4), %ecx
	popq	%rbx
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z13verify_resultPiS_S_i, .-_Z13verify_resultPiS_S_i
	.globl	_Z28__device_stub__Z6conv2dPiS_iPiS_i
	.type	_Z28__device_stub__Z6conv2dPiS_iPiS_i, @function
_Z28__device_stub__Z6conv2dPiS_iPiS_i:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6conv2dPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L24:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z28__device_stub__Z6conv2dPiS_iPiS_i, .-_Z28__device_stub__Z6conv2dPiS_iPiS_i
	.globl	_Z6conv2dPiS_i
	.type	_Z6conv2dPiS_i, @function
_Z6conv2dPiS_i:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6conv2dPiS_iPiS_i
	.cfi_endproc
.LFE3663:
	.size	_Z6conv2dPiS_i, .-_Z6conv2dPiS_i
	.section	.rodata.str1.1
.LC1:
	.string	"%d, %d; "
.LC2:
	.string	"COMPLETED SUCCESSFULLY! \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4194304, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$1024, %esi
	movq	%rax, %rdi
	movq	%rax, %rbp
	call	_Z11init_matrixPii
	movl	$4194304, %edi
	call	_Znam@PLT
	movl	$196, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$7, %esi
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	_Z11init_matrixPii
	movq	%rsp, %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rsi
	movl	$196, %edx
	leaq	_ZL4mask(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$32, %ecx
	movl	$32, %edx
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$1024, %edx
	call	_Z28__device_stub__Z6conv2dPiS_iPiS_i
.L30:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$4194304, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movl	$1024, %ecx
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z13verify_resultPiS_S_i
	movl	$25, %edx
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z6conv2dPiS_i"
.LC4:
	.string	"mask"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6conv2dPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movl	$196, %r9d
	leaq	_ZL4mask(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL4mask
	.comm	_ZL4mask,196,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <cassert>
#include <cstdlib>
#include <iostream>

#define MASK_DIM 7

#define MASK_OFFSET (MASK_DIM / 2)

__constant__ int mask[7 * 7];

__global__ void conv2d(int *matrix, int *result, int N) {
  int y = blockIdx.y * blockDim.y + threadIdx.y; 
  int x = blockIdx.x * blockDim.x + threadIdx.x; 

  int s_y = y - MASK_OFFSET;
  int s_x = x - MASK_OFFSET;

  int temp = 0;
  for (int i = 0; i < MASK_DIM; i++) {
    for (int j = 0; j < MASK_DIM; j++) {
      if((s_y + i) >= 0 && (s_y + i) < N) {
        if((s_x + j) >= 0 && (s_x + j) < N) {
          temp += matrix[N * (s_y + i) + (s_x + j)] * mask[MASK_DIM * i + j];
        }
      }
    }
  }

  result[N * y + x] = temp;
}

void init_matrix(int *m, int n) {
  for (int i = 0; i < n; i++) {
    for (int j = 0; j < n; j++) {
      m[n * i + j] = rand() % 100;
    }
  }
}

void verify_result(int *matrix, int *result, int *mask, int N) {
  int temp, o_y, o_x;
  
  for(int y = 0; y < N; y++) {
    for(int x = 0; x < N; x++) {
      temp = 0; 
      for (int i = 0; i < MASK_DIM; i++) {
        o_y = y - MASK_OFFSET + i; 
        for (int j = 0; j < MASK_DIM; j++) {  
          o_x = x - MASK_OFFSET + j;
          if(o_y >= 0 && o_y < N) {
            if(o_x >=0 && o_x < N) {
              temp += matrix[N * o_y + o_x] * mask[MASK_DIM * i + j];
            }
          }
        }
      }

      assert(result[N * y + x] == temp);
    }
  }

  printf("result[%d] = %d == %d = temp \n", N * N - 1, result[N * N - 1], temp);
}

int main() {
  int N = 1 << 10;

  size_t bytes_n = sizeof(int) * N * N;
  size_t bytes_m = sizeof(int) * MASK_DIM * MASK_DIM;

  int *matrix = new int[N * N];
  init_matrix(matrix, N);

  int *result = new int[N * N]; 

  int *h_mask = new int[MASK_DIM * MASK_DIM];
  init_matrix(h_mask, MASK_DIM);

  int *d_matrix, *d_result;
  hipMalloc(&d_matrix, bytes_n); hipMalloc(&d_result, bytes_n);

  hipMemcpy(d_matrix, matrix, bytes_n, hipMemcpyHostToDevice);
  hipMemcpyToSymbol(HIP_SYMBOL(mask), h_mask, bytes_m);

  int n_threads = 32;
  int n_blocks = (N + n_threads - 1) / n_threads;

  printf("%d, %d; ", n_threads, n_blocks);

  dim3 block_dim(n_threads, n_threads);
  dim3 grid_dim(n_blocks, n_blocks);

  conv2d<<<grid_dim, block_dim>>>(d_matrix, d_result, N);

  hipMemcpy(result, d_result, bytes_n, hipMemcpyDeviceToHost);

  verify_result(matrix, result, h_mask, N);

  std::cout << "COMPLETED SUCCESSFULLY! \n";

  delete[] matrix; delete[] result; delete[] h_mask;
  hipFree(d_matrix); hipFree(d_result);

  return 0;
}



	.text
	.file	"conv2d.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z21__device_stub__conv2dPiS_i  # -- Begin function _Z21__device_stub__conv2dPiS_i
	.type	_Z21__device_stub__conv2dPiS_i,@function
_Z21__device_stub__conv2dPiS_i:         # @_Z21__device_stub__conv2dPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6conv2dPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__conv2dPiS_i, .Lfunc_end0-_Z21__device_stub__conv2dPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11init_matrixPii              # -- Begin function _Z11init_matrixPii
	.type	_Z11init_matrixPii,@function
_Z11init_matrixPii:                     # @_Z11init_matrixPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, (%rsp)                    # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB1_5
# %bb.1:                                # %.preheader.lr.ph
	movl	%esi, %ebx
	movl	%esi, %r15d
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
.LBB1_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	movl	%r12d, %eax
	movq	(%rsp), %rcx                    # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbp
	xorl	%r14d, %r14d
.LBB1_3:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbp,%r14,4)
	incq	%r14
	cmpq	%r14, %r15
	jne	.LBB1_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r13
	addl	%ebx, %r12d
	cmpq	%r15, %r13
	jne	.LBB1_2
.LBB1_5:                                # %._crit_edge13
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z11init_matrixPii, .Lfunc_end1-_Z11init_matrixPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z13verify_resultPiS_S_i        # -- Begin function _Z13verify_resultPiS_S_i
	.type	_Z13verify_resultPiS_S_i,@function
_Z13verify_resultPiS_S_i:               # @_Z13verify_resultPiS_S_i
	.cfi_startproc
# %bb.0:                                # %.preheader43.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $ecx killed $ecx def $rcx
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rcx, -8(%rsp)                  # 8-byte Spill
	movl	%ecx, %r8d
	leaq	(,%r8,4), %r9
	leaq	(%r9,%r9,2), %rax
	subq	%rax, %rdi
	xorl	%ecx, %ecx
.LBB2_1:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
                                        #       Child Loop BB2_3 Depth 3
                                        #         Child Loop BB2_4 Depth 4
	leaq	-3(%rcx), %r11
	movq	%rdi, %rbx
	xorl	%esi, %esi
.LBB2_2:                                # %.preheader
                                        #   Parent Loop BB2_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_3 Depth 3
                                        #         Child Loop BB2_4 Depth 4
	xorl	%r15d, %r15d
	movq	%rbx, %r12
	movq	%rdx, %r13
	xorl	%eax, %eax
.LBB2_3:                                #   Parent Loop BB2_1 Depth=1
                                        #     Parent Loop BB2_2 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB2_4 Depth 4
	leaq	(%r11,%r15), %rbp
	movq	$-3, %r10
.LBB2_4:                                #   Parent Loop BB2_1 Depth=1
                                        #     Parent Loop BB2_2 Depth=2
                                        #       Parent Loop BB2_3 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	testq	%rbp, %rbp
	js	.LBB2_9
# %bb.5:                                #   in Loop: Header=BB2_4 Depth=4
	cmpq	%r8, %rbp
	jge	.LBB2_9
# %bb.6:                                #   in Loop: Header=BB2_4 Depth=4
	movq	%rsi, %r14
	addq	%r10, %r14
	js	.LBB2_9
# %bb.7:                                #   in Loop: Header=BB2_4 Depth=4
	cmpq	%r8, %r14
	jge	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_4 Depth=4
	movl	12(%r13,%r10,4), %r14d
	imull	(%r12,%r10,4), %r14d
	addl	%r14d, %eax
.LBB2_9:                                #   in Loop: Header=BB2_4 Depth=4
	incq	%r10
	cmpq	$4, %r10
	jne	.LBB2_4
# %bb.10:                               #   in Loop: Header=BB2_3 Depth=3
	incq	%r15
	addq	$28, %r13
	addq	%r9, %r12
	cmpq	$7, %r15
	jne	.LBB2_3
# %bb.11:                               #   in Loop: Header=BB2_2 Depth=2
	incq	%rsi
	addq	$4, %rbx
	cmpq	%r8, %rsi
	jne	.LBB2_2
# %bb.12:                               # %._crit_edge
                                        #   in Loop: Header=BB2_1 Depth=1
	incq	%rcx
	addq	%r9, %rdi
	cmpq	%r8, %rcx
	jne	.LBB2_1
# %bb.13:                               # %._crit_edge51
	movq	-8(%rsp), %rcx                  # 8-byte Reload
	imull	%ecx, %ecx
	leal	-1(%rcx), %esi
	movq	-16(%rsp), %rdx                 # 8-byte Reload
	movl	-4(%rdx,%rcx,4), %edx
	movl	$.L.str, %edi
	movl	%eax, %ecx
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end2:
	.size	_Z13verify_resultPiS_S_i, .Lfunc_end2-_Z13verify_resultPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %rbx
	xorl	%r14d, %r14d
	movq	%rax, %r15
.LBB3_1:                                # %.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%r12d, %r12d
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r15,%r12,4)
	incq	%r12
	cmpq	$1024, %r12                     # imm = 0x400
	jne	.LBB3_2
# %bb.3:                                # %._crit_edge.i
                                        #   in Loop: Header=BB3_1 Depth=1
	incq	%r14
	addq	$4096, %r15                     # imm = 0x1000
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB3_1
# %bb.4:                                # %_Z11init_matrixPii.exit
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %r14
	movl	$196, %edi
	callq	_Znam
	movq	%rax, %r15
	xorl	%r12d, %r12d
	movq	%rax, %r13
.LBB3_5:                                # %.lr.ph.i39
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
	xorl	%ebp, %ebp
.LBB3_6:                                #   Parent Loop BB3_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r13,%rbp,4)
	incq	%rbp
	cmpq	$7, %rbp
	jne	.LBB3_6
# %bb.7:                                # %._crit_edge.i46
                                        #   in Loop: Header=BB3_5 Depth=1
	incq	%r12
	addq	$28, %r13
	cmpq	$7, %r12
	jne	.LBB3_5
# %bb.8:                                # %_Z11init_matrixPii.exit49
	leaq	16(%rsp), %r12
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$mask, %edi
	movl	$196, %edx
	movq	%r15, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$.L.str.1, %edi
	movl	$32, %esi
	movl	$32, %edx
	xorl	%eax, %eax
	callq	printf
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	callq	_Z21__device_stub__conv2dPiS_i
.LBB3_10:
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z13verify_resultPiS_S_i
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6conv2dPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$196, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	mask,@object                    # @mask
	.local	mask
	.comm	mask,196,16
	.type	_Z6conv2dPiS_i,@object          # @_Z6conv2dPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z6conv2dPiS_i
	.p2align	3, 0x0
_Z6conv2dPiS_i:
	.quad	_Z21__device_stub__conv2dPiS_i
	.size	_Z6conv2dPiS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"result[%d] = %d == %d = temp \n"
	.size	.L.str, 31

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d, %d; "
	.size	.L.str.1, 9

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"COMPLETED SUCCESSFULLY! \n"
	.size	.L.str.2, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6conv2dPiS_i"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"mask"
	.size	.L__unnamed_2, 5

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__conv2dPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym mask
	.addrsig_sym _Z6conv2dPiS_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6conv2dPiS_i          ; -- Begin function _Z6conv2dPiS_i
	.globl	_Z6conv2dPiS_i
	.p2align	8
	.type	_Z6conv2dPiS_i,@function
_Z6conv2dPiS_i:                         ; @_Z6conv2dPiS_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s8, s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s15, s0, v[2:3]
	s_and_b32 s0, s2, 0xffff
	s_add_u32 s9, s4, -12
	v_mad_u64_u32 v[1:2], null, s14, s0, v[3:4]
	v_mov_b32_e32 v2, 0
	s_addc_u32 s10, s5, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, -3, v0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, mask@rel32@lo+4
	s_addc_u32 s3, s3, mask@rel32@hi+12
	v_add_nc_u32_e32 v4, -3, v1
	v_mul_lo_u32 v6, s8, v3
	v_ashrrev_i32_e32 v5, 31, v1
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v8, 31, v6
	v_add_co_u32 v7, vcc_lo, v1, v6
	v_add_nc_u32_e32 v9, s11, v3
	s_mov_b64 s[4:5], 0
	v_add_co_ci_u32_e32 v8, vcc_lo, v5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, -1, v9
	v_cmp_gt_i32_e64 s0, s8, v9
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_mov_b32_e32 v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s1, s9, v7
	v_add_co_ci_u32_e64 v8, s1, s10, v8, s1
	s_and_b32 s1, vcc_lo, s0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s1
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	v_cmp_lt_i32_e32 vcc_lo, -1, v9
	v_cmp_gt_i32_e64 s0, s8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s13, vcc_lo, s0
	s_and_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=2
	v_add_co_u32 v10, vcc_lo, v7, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v8, vcc_lo
	s_add_u32 s14, s2, s4
	s_addc_u32 s15, s3, s5
	s_load_b32 s13, s[14:15], 0x0
	global_load_b32 v12, v[10:11], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mad_u64_u32 v[10:11], null, s13, v12, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v10
.LBB0_5:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v9, 1, v9
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s4, 28
	s_cbranch_scc0 .LBB0_2
; %bb.7:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s11, s11, 1
	v_add_nc_u32_e32 v6, s8, v6
	s_add_u32 s2, s2, 28
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s11, 7
	s_cbranch_scc0 .LBB0_1
; %bb.8:
	v_mad_u64_u32 v[3:4], null, v0, s8, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6conv2dPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6conv2dPiS_i, .Lfunc_end0-_Z6conv2dPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	mask                    ; @mask
	.type	mask,@object
	.section	.bss,"aw",@nobits
	.globl	mask
	.p2align	4, 0x0
mask:
	.zero	196
	.size	mask, 196

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym mask
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6conv2dPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6conv2dPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
