#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <stdlib.h>
#include <cstdio>

// Fourth order interpolation function.
__host__ __device__ inline double interp(const double m2, const double m1, const double p1, const double p2)
{
  return (-1./16)*(m2+p2) + (9./16)*(m1+p1);
}

// Fourth order gradient function.
__host__ __device__ inline double grad(const double m2, const double m1, const double p1, const double p2)
{
  return (1./24.)*(m2-p2) + (27./24.)*(p1-m1);
}

/* 
4th order advection on cpu
*/
void advec_cpu(double * const __restrict__ ut, 
               const double * const __restrict__ u, const double * const __restrict__ v, const double * const __restrict__ w,
               const int istart, const int iend, 
               const int jstart, const int jend, 
               const int kstart, const int kend, 
               const int icells, const int ijcells)
{
    const int ii1 = 1;
    const int ii2 = 2;
    const int ii3 = 3;
    const int jj1 = 1*icells;
    const int jj2 = 2*icells;
    const int jj3 = 3*icells;
    const int kk1 = 1*ijcells;
    const int kk2 = 2*ijcells;
    const int kk3 = 3*ijcells;

    for (int k=kstart; k<kend; ++k)
        for (int j=jstart; j<jend; ++j)
            #pragma ivdep
            for (int i=istart; i<iend; ++i)
            {
                const int ijk = i + j*icells + k*ijcells;

                ut[ijk] += grad( interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ) * interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ),
                                 interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ) * interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ),
                                 interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ) * interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ),
                                 interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ) * interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ))

                         + grad( interp( v[ijk-ii2-jj1], v[ijk-ii1-jj1], v[ijk-jj1], v[ijk+ii1-jj1] ) * interp( u[ijk-jj3], u[ijk-jj2], u[ijk-jj1], u[ijk    ] ),
                                 interp( v[ijk-ii2    ], v[ijk-ii1    ], v[ijk    ], v[ijk+ii1    ] ) * interp( u[ijk-jj2], u[ijk-jj1], u[ijk    ], u[ijk+jj1] ),
                                 interp( v[ijk-ii2+jj1], v[ijk-ii1+jj1], v[ijk+jj1], v[ijk+ii1+jj1] ) * interp( u[ijk-jj1], u[ijk    ], u[ijk+jj1], u[ijk+jj2] ),
                                 interp( v[ijk-ii2+jj2], v[ijk-ii1+jj2], v[ijk+jj2], v[ijk+ii1+jj2] ) * interp( u[ijk    ], u[ijk+jj1], u[ijk+jj2], u[ijk+jj3] ))

                         + grad( interp( w[ijk-ii2-kk1], w[ijk-ii1-kk1], w[ijk-kk1], w[ijk+ii1-kk1] ) * interp( u[ijk-kk3], u[ijk-kk2], u[ijk-kk1], u[ijk    ] ),
                                 interp( w[ijk-ii2    ], w[ijk-ii1    ], w[ijk    ], w[ijk+ii1    ] ) * interp( u[ijk-kk2], u[ijk-kk1], u[ijk    ], u[ijk+kk1] ),
                                 interp( w[ijk-ii2+kk1], w[ijk-ii1+kk1], w[ijk+kk1], w[ijk+ii1+kk1] ) * interp( u[ijk-kk1], u[ijk    ], u[ijk+kk1], u[ijk+kk2] ),
                                 interp( w[ijk-ii2+kk2], w[ijk-ii1+kk2], w[ijk+kk2], w[ijk+ii1+kk2] ) * interp( u[ijk    ], u[ijk+kk1], u[ijk+kk2], u[ijk+kk3] ));
            }
}


/* 
4th order advection (3D), no shared memory use
*/
__global__ void advec_gpu(double * const __restrict__ ut, 
                          const double * const __restrict__ u, const double * const __restrict__ v, const double * const __restrict__ w,
                          const int istart, const int iend, 
                          const int jstart, const int jend, 
                          const int kstart, const int kend, 
                          const int icells, const int ijcells)
{
    const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
    const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
    const int k = blockIdx.z + kstart;

    if(i < iend && j < jend && k < kend)
    {
        const int ijk = i + j*icells + k*ijcells;

        const int ii1 = 1;
        const int ii2 = 2;
        const int ii3 = 3;
        const int jj1 = 1*icells;
        const int jj2 = 2*icells;
        const int jj3 = 3*icells;
        const int kk1 = 1*ijcells;
        const int kk2 = 2*ijcells;
        const int kk3 = 3*ijcells;

        ut[ijk] += grad( interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ) * interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ),
                         interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ) * interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ),
                         interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ) * interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ),
                         interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ) * interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ))

                 + grad( interp( v[ijk-ii2-jj1], v[ijk-ii1-jj1], v[ijk-jj1], v[ijk+ii1-jj1] ) * interp( u[ijk-jj3], u[ijk-jj2], u[ijk-jj1], u[ijk    ] ),
                         interp( v[ijk-ii2    ], v[ijk-ii1    ], v[ijk    ], v[ijk+ii1    ] ) * interp( u[ijk-jj2], u[ijk-jj1], u[ijk    ], u[ijk+jj1] ),
                         interp( v[ijk-ii2+jj1], v[ijk-ii1+jj1], v[ijk+jj1], v[ijk+ii1+jj1] ) * interp( u[ijk-jj1], u[ijk    ], u[ijk+jj1], u[ijk+jj2] ),
                         interp( v[ijk-ii2+jj2], v[ijk-ii1+jj2], v[ijk+jj2], v[ijk+ii1+jj2] ) * interp( u[ijk    ], u[ijk+jj1], u[ijk+jj2], u[ijk+jj3] ))

                 + grad( interp( w[ijk-ii2-kk1], w[ijk-ii1-kk1], w[ijk-kk1], w[ijk+ii1-kk1] ) * interp( u[ijk-kk3], u[ijk-kk2], u[ijk-kk1], u[ijk    ] ),
                         interp( w[ijk-ii2    ], w[ijk-ii1    ], w[ijk    ], w[ijk+ii1    ] ) * interp( u[ijk-kk2], u[ijk-kk1], u[ijk    ], u[ijk+kk1] ),
                         interp( w[ijk-ii2+kk1], w[ijk-ii1+kk1], w[ijk+kk1], w[ijk+ii1+kk1] ) * interp( u[ijk-kk1], u[ijk    ], u[ijk+kk1], u[ijk+kk2] ),
                         interp( w[ijk-ii2+kk2], w[ijk-ii1+kk2], w[ijk+kk2], w[ijk+ii1+kk2] ) * interp( u[ijk    ], u[ijk+kk1], u[ijk+kk2], u[ijk+kk3] ));
    }
}

/* 
4th order advection, smem
*/
__global__ void advec_gpu_smem(double * const __restrict__ ut, 
                               const double * const __restrict__ u, const double * const __restrict__ v, const double * const __restrict__ w, 
                               const int istart, const int iend, 
                               const int jstart, const int jend, 
                               const int kstart, const int kend, 
                               const int icells, const int ijcells, const int ngc)
{
    extern __shared__ double shared[]; 
    const int smem_block = (blockDim.x + 2*ngc) * (blockDim.y + 2*ngc);
    double *us = &shared[0];
    double *vs = &shared[smem_block];

    const int tx = threadIdx.x;
    const int ty = threadIdx.y;
    const int i  = blockIdx.x*blockDim.x + threadIdx.x + istart;
    const int j  = blockIdx.y*blockDim.y + threadIdx.y + jstart;
    const int blockxpad = blockDim.x+2*ngc;

    if(i < iend && j < jend)
    {
        const int ii1 = 1;
        const int ii2 = 2;
        const int ii3 = 3;
        const int jj1 = 1*icells;
        const int jj2 = 2*icells;
        const int jj3 = 3*icells;
        const int kk1 = 1*ijcells;
        const int kk2 = 2*ijcells;
        const int kk3 = 3*ijcells;
        const int kk4 = 4*ijcells;

        const int jjs1 = 1*blockxpad;
        const int jjs2 = 2*blockxpad;
        const int jjs3 = 3*blockxpad;

        int ijk;
        const int ijks = (tx+ngc) + (ty+ngc)*blockxpad;

        for(int k=kstart; k<kend; ++k)
        {
            ijk  = i + j*icells + k*ijcells; // index in global memory
 
            us[ijks] = u[ijk];
            vs[ijks] = v[ijk];

            if(ty < ngc)
            {
                us[ijks-jjs3] = u[ijk-jj3];
                vs[ijks-jjs3] = v[ijk-jj3];
            }
            if(ty >= blockDim.y-ngc)
            {
                us[ijks+jjs3] = u[ijk+jj3];
                vs[ijks+jjs3] = v[ijk+jj3];
            }

            if(tx < ngc)
            {
                us[ijks-ngc] = u[ijk-ngc];
                vs[ijks-ngc] = v[ijk-ngc];

                if(ty < ngc)
                {
                    us[ijks-jjs3-ngc] = u[ijk-jj3-ngc];
                    vs[ijks-jjs3-ngc] = v[ijk-jj3-ngc];
                }
                if(ty >= blockDim.y-ngc)
                {
                    us[ijks+jjs3-ngc] = u[ijk+jj3-ngc];
                    vs[ijks+jjs3-ngc] = v[ijk+jj3-ngc];
                }
            }
            if(tx >= blockDim.x-ngc)
            {
                us[ijks+ngc] = u[ijk+ngc];
                vs[ijks+ngc] = v[ijk+ngc];

                if(ty < ngc)
                {
                    us[ijks-jjs3+ngc] = u[ijk-jj3+ngc];
                    vs[ijks-jjs3+ngc] = v[ijk-jj3+ngc];
                }
                if(ty >= blockDim.y-ngc)
                {
                    us[ijks+jjs3+ngc] = u[ijk+jj3+ngc];
                    vs[ijks+jjs3+ngc] = v[ijk+jj3+ngc];
                }
            }

            __syncthreads();

            ut[ijk] += grad( interp( us[ijks-ii3], us[ijks-ii2], us[ijks-ii1], us[ijks    ] ) * interp( us[ijks-ii3], us[ijks-ii2], us[ijks-ii1], us[ijks    ] ),
                             interp( us[ijks-ii2], us[ijks-ii1], us[ijks    ], us[ijks+ii1] ) * interp( us[ijks-ii2], us[ijks-ii1], us[ijks    ], us[ijks+ii1] ),
                             interp( us[ijks-ii1], us[ijks    ], us[ijks+ii1], us[ijks+ii2] ) * interp( us[ijks-ii1], us[ijks    ], us[ijks+ii1], us[ijks+ii2] ),
                             interp( us[ijks    ], us[ijks+ii1], us[ijks+ii2], us[ijks+ii3] ) * interp( us[ijks    ], us[ijks+ii1], us[ijks+ii2], us[ijks+ii3] ))

                     + grad( interp( vs[ijks-ii2-jjs1], vs[ijks-ii1-jjs1], vs[ijks-jjs1], vs[ijks+ii1-jjs1] ) * interp( us[ijks-jjs3], us[ijks-jjs2], us[ijks-jjs1], us[ijks     ] ),
                             interp( vs[ijks-ii2    ],  vs[ijks-ii1     ], vs[ijks    ],  vs[ijks+ii1     ] ) * interp( us[ijks-jjs2], us[ijks-jjs1], us[ijks     ], us[ijks+jjs1] ),
                             interp( vs[ijks-ii2+jjs1], vs[ijks-ii1+jjs1], vs[ijks+jjs1], vs[ijks+ii1+jjs1] ) * interp( us[ijks-jjs1], us[ijks     ], us[ijks+jjs1], us[ijks+jjs2] ),
                             interp( vs[ijks-ii2+jjs2], vs[ijks-ii1+jjs2], vs[ijks+jjs2], vs[ijks+ii1+jjs2] ) * interp( us[ijks     ], us[ijks+jjs1], us[ijks+jjs2], us[ijks+jjs3] ))

                     + grad( interp( w[ijk-ii2-kk1], w[ijk-ii1-kk1], w[ijk-kk1], w[ijk+ii1-kk1] ) * interp( u[ijk-kk3], u[ijk-kk2], u[ijk-kk1], us[ijks  ] ),
                             interp( w[ijk-ii2    ], w[ijk-ii1    ], w[ijk    ], w[ijk+ii1    ] ) * interp( u[ijk-kk2], u[ijk-kk1], us[ijks  ], u[ijk+kk1] ),
                             interp( w[ijk-ii2+kk1], w[ijk-ii1+kk1], w[ijk+kk1], w[ijk+ii1+kk1] ) * interp( u[ijk-kk1], us[ijks  ], u[ijk+kk1], u[ijk+kk2] ),
                             interp( w[ijk-ii2+kk2], w[ijk-ii1+kk2], w[ijk+kk2], w[ijk+ii1+kk2] ) * interp( us[ijks  ], u[ijk+kk1], u[ijk+kk2], u[ijk+kk3] ));
        }
    }
}


/* 
Get max difference between two fields
*/
double maxdiff(const double * const __restrict__ a, const double * const __restrict__ b, const int n)
{
    double maxdiff=0;
    double diff=0;
    for(int i=0; i<n; ++i)
    {
        diff = std::abs(a[i]-b[i]);
        if(diff > maxdiff)
            maxdiff = diff;
    }
    return maxdiff;
}

int main()
{
    //
    // Grid
    //
    const int itot = 256;
    const int jtot = 256;
    const int ktot = 256;
    const int gc   = 3;
    const int iter = 10;
    
    //
    // Calculate the required variables.
    //
    const int ncells  = (itot+2*gc)*(jtot+2*gc)*(ktot+2*gc);
    const int istart  = gc;
    const int jstart  = gc;
    const int kstart  = gc;
    const int iend    = itot+gc;
    const int jend    = jtot+gc;
    const int kend    = ktot+gc;
    const int icells  = itot+2*gc;
    const int jcells  = jtot+2*gc;
    const int kcells  = ktot+2*gc;
    const int ijcells = (itot+2*gc)*(jtot+2*gc);
    
    // Padded settings, interior aligned to 128 byte blocks
    const int mo        = 16 - gc;           // Padding at start of array 
    const int pl        = 16-(int)itot%16;   // Elements left in last 128 byte block
    const int icellsp   = itot + pl + (pl < 2*gc)*16;
    const int ijcellsp  = icellsp * jcells;  
    const int ncellsp   = ijcellsp * kcells + mo;
    
    //
    // Prepare fields on HOST
    //
    double *u    = new double[ncells];
    double *v    = new double[ncells];
    double *w    = new double[ncells];
    double *ut   = new double[ncells];
    double *tmp1 = new double[ncells];
    
    for (int n=0; n<ncells; ++n)
    {
    	u [n]   = 0.001 * (std::rand() % 1000) - 0.5;
    	v [n]   = 0.001 * (std::rand() % 1000) - 0.5;
    	w [n]   = 0.001 * (std::rand() % 1000) - 0.5;
    	ut[n]   = 0.;
    	tmp1[n] = 0.;
    }
    
    // 
    // Prepare fields on DEVICE
    //
    double *ud, *vd, *wd, *utd;
    cudaMalloc((void **)&ud,  ncellsp*sizeof(double));
    cudaMalloc((void **)&vd,  ncellsp*sizeof(double));
    cudaMalloc((void **)&wd,  ncellsp*sizeof(double));
    cudaMalloc((void **)&utd, ncellsp*sizeof(double));
    cudaMemcpy2D(&ud[mo],  icellsp*sizeof(double),  u,  icells*sizeof(double), icells*sizeof(double), jcells*kcells, cudaMemcpyHostToDevice);
    cudaMemcpy2D(&vd[mo],  icellsp*sizeof(double),  v,  icells*sizeof(double), icells*sizeof(double), jcells*kcells, cudaMemcpyHostToDevice);
    cudaMemcpy2D(&wd[mo],  icellsp*sizeof(double),  w,  icells*sizeof(double), icells*sizeof(double), jcells*kcells, cudaMemcpyHostToDevice);
    cudaMemcpy2D(&utd[mo], icellsp*sizeof(double),  ut, icells*sizeof(double), icells*sizeof(double), jcells*kcells, cudaMemcpyHostToDevice);
    
    //
    // CUDA thread blocks
    //
    const int blocki = 32;
    const int blockj = 8;
    const int gridi  = itot/blocki + (itot%blocki > 0);
    const int gridj  = jtot/blockj + (jtot%blockj > 0);
    dim3 gridGPU  (gridi, gridj, ktot);
    dim3 gridGPU2d(gridi, gridj, 1);
    dim3 blockGPU(blocki, blockj, 1);

    // 
    // Timer stuff
    //
    cudaEvent_t startEvent, stopEvent;
    cudaEventCreate(&startEvent);
    cudaEventCreate(&stopEvent);
    float  dt1, dt2;

    //
    // Execute kernels
    //
    //////////////////// CPU //////////////////////////
    cudaEventRecord(startEvent, 0);
    for(int n=0; n<iter; ++n) // iter+1 since GPU version is warmed up with one call
    {
       advec_cpu(ut, u, v, w,istart, iend, jstart, jend, kstart, kend, icells, ijcells);
    }
    cudaEventRecord(stopEvent, 0);
    cudaEventSynchronize(stopEvent);
    cudaEventElapsedTime(&dt1, startEvent, stopEvent);
    printf("CPU; elapsed=%f [ms]\n",dt1);
 
    ////////////////////// GPU //////////////////////////
    cudaDeviceSetSharedMemConfig(cudaSharedMemBankSizeEightByte);

    cudaEventRecord(startEvent, 0);
    for(int n=0; n<iter; ++n)
    {
        //advec_gpu<<<gridGPU, blockGPU>>> 
        //         (&utd[mo], &ud[mo], &vd[mo], &wd[mo], istart, iend, jstart, jend, kstart, kend, icellsp, ijcellsp);
        advec_gpu_smem<<<gridGPU2d, blockGPU, 2*(blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>> 
                 (&utd[mo], &ud[mo], &vd[mo], &wd[mo], istart, iend, jstart, jend, kstart, kend, icellsp, ijcellsp, gc);
    }
    cudaEventRecord(stopEvent, 0);
    cudaEventSynchronize(stopEvent);
    cudaEventElapsedTime(&dt2, startEvent, stopEvent);

    //
    // Copy device field to tmp1 
    //
    cudaMemcpy2D(tmp1, icells*sizeof(double), &utd[mo], icellsp*sizeof(double), icells*sizeof(double), jcells*kcells, cudaMemcpyDeviceToHost);

    printf("GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n",dt2,dt1/dt2,maxdiff(ut,tmp1,ncells));

    return 0;
}

	.file	"tmpxft_003385d3_00000000-6_advec4.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3922:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3922:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	.type	_Z9advec_cpuPdPKdS1_S1_iiiiiiii, @function
_Z9advec_cpuPdPKdS1_S1_iiiiiiii:
.LFB3917:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	112(%rsp), %eax
	imull	136(%rsp), %eax
	movq	%rdi, -88(%rsp)
	movl	%r8d, 24(%rsp)
	movl	%r9d, 28(%rsp)
	movl	%eax, 16(%rsp)
	movl	96(%rsp), %eax
	imull	128(%rsp), %eax
	movl	%eax, 20(%rsp)
	movl	128(%rsp), %eax
	addl	%eax, %eax
	cltq
	movq	%rax, -80(%rsp)
	movl	136(%rsp), %eax
	addl	%eax, %eax
	cltq
	movq	%rax, -72(%rsp)
	movslq	128(%rsp), %rax
	movq	%rax, -120(%rsp)
	leaq	(%rax,%rax,2), %rax
	movq	%rax, -64(%rsp)
	imulq	$-16, -120(%rsp), %rax
	movq	%rax, -48(%rsp)
	imulq	$-24, -120(%rsp), %rax
	movsd	.LC0(%rip), %xmm1
	movsd	.LC1(%rip), %xmm2
	movq	%rax, -32(%rsp)
	movslq	136(%rsp), %rax
	movq	%rax, -112(%rsp)
	leaq	(%rax,%rax,2), %rax
	movq	%rax, -16(%rsp)
	imulq	$-16, -112(%rsp), %rax
	movq	%rax, (%rsp)
	imulq	$-24, -112(%rsp), %rax
	movq	%rax, 8(%rsp)
.L3:
	movl	120(%rsp), %eax
	cmpl	%eax, 112(%rsp)
	jge	.L2
	movl	20(%rsp), %eax
	movslq	16(%rsp), %r13
	movl	%eax, -92(%rsp)
	movl	96(%rsp), %eax
	movl	%eax, -96(%rsp)
	movq	-64(%rsp), %rax
	addq	%r13, %rax
	movq	%rax, 32(%rsp)
.L8:
	movl	-96(%rsp), %eax
	cmpl	104(%rsp), %eax
	jge	.L5
	movslq	24(%rsp), %rdi
	movq	-120(%rsp), %r14
	movslq	-92(%rsp), %r12
	movq	-72(%rsp), %r15
	movq	%rdi, %r11
	movq	%rdi, %r8
	movq	-80(%rsp), %rbx
	leaq	(%rdi,%r13), %rax
	subq	%r14, %r11
	movq	-112(%rsp), %r14
	leaq	(%rdi,%r15), %r10
	addq	%r12, %rax
	leaq	(%rdi,%rbx), %rbp
	movq	-120(%rsp), %rbx
	addq	%r13, %r11
	addq	%r13, %r10
	subq	%r14, %r8
	leaq	(%rdi,%r14), %r9
	movq	32(%rsp), %r14
	addq	%r13, %rbp
	addq	%rdi, %rbx
	addq	%r13, %r9
	addq	%r13, %r8
	addq	%r12, %rbp
	addq	%r12, %r14
	addq	%r13, %rbx
	addq	%r12, %r11
	addq	%r12, %r10
	leaq	(%rsi,%r14,8), %r15
	leaq	(%r12,%r13), %r14
	addq	%r12, %rbx
	addq	%r12, %r9
	movq	%r15, -56(%rsp)
	salq	$3, %r14
	addq	%r12, %r8
	salq	$3, %rax
	movq	-48(%rsp), %r15
	salq	$3, %rbp
	salq	$3, %rbx
	salq	$3, %r11
	salq	$3, %r10
	salq	$3, %r9
	addq	%r14, %r15
	salq	$3, %r8
	addq	%rsi, %r15
	movq	%r15, -40(%rsp)
	movq	-32(%rsp), %r15
	addq	%r14, %r15
	addq	%rsi, %r15
	movq	%r15, -24(%rsp)
	movq	-16(%rsp), %r15
	addq	%r13, %r15
	addq	%r12, %r15
	movq	8(%rsp), %r12
	leaq	(%rsi,%r15,8), %r15
	movq	%r15, -8(%rsp)
	movq	(%rsp), %r15
	addq	%r14, %r15
	addq	%rsi, %r15
	addq	%r12, %r14
	addq	%rsi, %r14
.L6:
	cmpl	%edi, 28(%rsp)
	jle	.L11
	movsd	16(%rsi,%rax), %xmm4
	movsd	(%rsi,%rax), %xmm3
	movsd	8(%rsi,%rax), %xmm6
	movsd	24(%rsi,%rax), %xmm10
	movaps	%xmm4, %xmm0
	movsd	-16(%rsi,%rax), %xmm7
	movq	-40(%rsp), %r12
	addsd	%xmm3, %xmm10
	addsd	%xmm6, %xmm0
	movaps	%xmm6, %xmm5
	movsd	8(%rdx,%r11), %xmm15
	addsd	%xmm3, %xmm5
	addsd	%xmm7, %xmm6
	movsd	(%rsi,%r11), %xmm9
	movsd	(%rsi,%rbx), %xmm12
	addsd	-16(%rdx,%r11), %xmm15
	movsd	(%rsi,%r9), %xmm11
	mulsd	%xmm2, %xmm0
	movsd	(%rsi,%r8), %xmm14
	mulsd	%xmm1, %xmm10
	mulsd	%xmm2, %xmm5
	mulsd	%xmm1, %xmm15
	mulsd	%xmm1, %xmm6
	addsd	%xmm0, %xmm10
	movsd	-8(%rsi,%rax), %xmm0
	addsd	%xmm0, %xmm4
	mulsd	%xmm10, %xmm10
	mulsd	%xmm1, %xmm4
	addsd	%xmm5, %xmm4
	movaps	%xmm3, %xmm5
	addsd	%xmm0, %xmm5
	addsd	%xmm7, %xmm0
	movsd	(%r12,%rdi,8), %xmm7
	movq	-24(%rsp), %r12
	movsd	%xmm7, -104(%rsp)
	movsd	(%rdx,%r11), %xmm7
	movsd	(%r12,%rdi,8), %xmm8
	mulsd	%xmm4, %xmm4
	addsd	-8(%rdx,%r11), %xmm7
	mulsd	%xmm2, %xmm5
	movq	-56(%rsp), %r12
	addq	$8, %r11
	addsd	%xmm3, %xmm8
	mulsd	%xmm2, %xmm0
	mulsd	%xmm2, %xmm7
	mulsd	%xmm1, %xmm8
	addsd	%xmm5, %xmm6
	movsd	-24(%rsi,%rax), %xmm5
	addsd	%xmm3, %xmm5
	addsd	%xmm7, %xmm15
	movsd	-104(%rsp), %xmm7
	mulsd	%xmm6, %xmm6
	addsd	%xmm9, %xmm7
	mulsd	%xmm1, %xmm5
	movaps	%xmm15, %xmm13
	movsd	8(%rdx,%rbp), %xmm15
	addsd	-16(%rdx,%rbp), %xmm15
	mulsd	%xmm2, %xmm7
	subsd	%xmm6, %xmm4
	mulsd	%xmm1, %xmm15
	addsd	%xmm0, %xmm5
	movsd	(%rsi,%rbp), %xmm0
	addsd	%xmm7, %xmm8
	movsd	(%rdx,%rbp), %xmm7
	addsd	-8(%rdx,%rbp), %xmm7
	mulsd	%xmm5, %xmm5
	addq	$8, %rbp
	mulsd	%xmm2, %xmm7
	mulsd	%xmm8, %xmm13
	movsd	(%r12,%rdi,8), %xmm8
	subsd	%xmm10, %xmm5
	addsd	%xmm3, %xmm8
	addsd	%xmm7, %xmm15
	movaps	%xmm0, %xmm7
	addsd	%xmm9, %xmm0
	addsd	%xmm12, %xmm7
	mulsd	%xmm1, %xmm8
	addsd	%xmm3, %xmm9
	mulsd	%xmm1, %xmm0
	mulsd	%xmm2, %xmm7
	mulsd	%xmm2, %xmm9
	addsd	%xmm8, %xmm7
	movsd	(%rdx,%rbx), %xmm8
	mulsd	%xmm7, %xmm15
	movaps	%xmm13, %xmm7
	subsd	%xmm15, %xmm7
	movsd	8(%rdx,%rbx), %xmm15
	mulsd	.LC2(%rip), %xmm7
	addsd	-16(%rdx,%rbx), %xmm15
	addsd	-8(%rdx,%rbx), %xmm8
	addq	$8, %rbx
	mulsd	.LC3(%rip), %xmm4
	movsd	(%rcx,%r8), %xmm6
	mulsd	.LC2(%rip), %xmm5
	addsd	-8(%rcx,%r8), %xmm6
	mulsd	%xmm1, %xmm15
	movq	-8(%rsp), %r12
	mulsd	%xmm2, %xmm8
	mulsd	%xmm2, %xmm6
	addsd	%xmm4, %xmm5
	movsd	8(%rcx,%r8), %xmm4
	addsd	-16(%rcx,%r8), %xmm4
	addq	$8, %r8
	addsd	%xmm15, %xmm8
	movaps	%xmm3, %xmm15
	addsd	%xmm12, %xmm15
	addsd	-104(%rsp), %xmm12
	mulsd	%xmm1, %xmm4
	mulsd	%xmm2, %xmm15
	mulsd	%xmm1, %xmm12
	addsd	%xmm4, %xmm6
	movsd	(%r14,%rdi,8), %xmm4
	addsd	%xmm3, %xmm4
	addsd	%xmm15, %xmm0
	movsd	(%rdx,%rax), %xmm15
	addsd	-8(%rdx,%rax), %xmm15
	addsd	%xmm12, %xmm9
	mulsd	%xmm1, %xmm4
	mulsd	%xmm8, %xmm0
	movsd	8(%rdx,%rax), %xmm8
	addsd	-16(%rdx,%rax), %xmm8
	mulsd	%xmm2, %xmm15
	mulsd	%xmm1, %xmm8
	addsd	%xmm15, %xmm8
	mulsd	%xmm8, %xmm9
	subsd	%xmm9, %xmm0
	mulsd	.LC3(%rip), %xmm0
	addsd	%xmm7, %xmm0
	movsd	(%rsi,%r10), %xmm7
	addsd	%xmm11, %xmm7
	addsd	%xmm5, %xmm0
	movsd	(%r15,%rdi,8), %xmm5
	addsd	%xmm14, %xmm5
	mulsd	%xmm2, %xmm7
	mulsd	%xmm2, %xmm5
	addsd	%xmm5, %xmm4
	movsd	8(%rcx,%r10), %xmm5
	addsd	-16(%rcx,%r10), %xmm5
	mulsd	%xmm4, %xmm6
	movsd	(%rcx,%r10), %xmm4
	addsd	-8(%rcx,%r10), %xmm4
	mulsd	%xmm1, %xmm5
	mulsd	%xmm2, %xmm4
	addsd	%xmm4, %xmm5
	movaps	%xmm3, %xmm4
	addsd	(%r12,%rdi,8), %xmm4
	mulsd	%xmm1, %xmm4
	addsd	%xmm7, %xmm4
	movaps	%xmm3, %xmm7
	addsd	%xmm14, %xmm3
	addsd	%xmm11, %xmm7
	mulsd	%xmm4, %xmm5
	movsd	8(%rcx,%r9), %xmm4
	addsd	-16(%rcx,%r9), %xmm4
	mulsd	%xmm2, %xmm7
	mulsd	%xmm2, %xmm3
	mulsd	%xmm1, %xmm4
	subsd	%xmm5, %xmm6
	movsd	(%rcx,%r9), %xmm5
	addsd	-8(%rcx,%r9), %xmm5
	addq	$8, %r9
	mulsd	.LC2(%rip), %xmm6
	mulsd	%xmm2, %xmm5
	addsd	%xmm5, %xmm4
	movsd	(%rsi,%r10), %xmm5
	addq	$8, %r10
	addsd	%xmm14, %xmm5
	mulsd	%xmm1, %xmm5
	addsd	%xmm7, %xmm5
	movsd	8(%rcx,%rax), %xmm7
	addsd	-16(%rcx,%rax), %xmm7
	mulsd	%xmm5, %xmm4
	movsd	(%rcx,%rax), %xmm5
	addsd	-8(%rcx,%rax), %xmm5
	addsd	(%r15,%rdi,8), %xmm11
	mulsd	%xmm1, %xmm7
	movq	-88(%rsp), %r12
	incq	%rdi
	mulsd	%xmm2, %xmm5
	mulsd	%xmm1, %xmm11
	addsd	%xmm7, %xmm5
	addsd	%xmm11, %xmm3
	mulsd	%xmm3, %xmm5
	subsd	%xmm5, %xmm4
	mulsd	.LC3(%rip), %xmm4
	addsd	%xmm4, %xmm6
	addsd	%xmm6, %xmm0
	addsd	(%r12,%rax), %xmm0
	movsd	%xmm0, (%r12,%rax)
	addq	$8, %rax
	jmp	.L6
.L11:
	movl	128(%rsp), %ebx
	incl	-96(%rsp)
	addl	%ebx, -92(%rsp)
	jmp	.L8
.L5:
	movl	136(%rsp), %ebx
	incl	112(%rsp)
	addl	%ebx, 16(%rsp)
	jmp	.L3
.L2:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3917:
	.size	_Z9advec_cpuPdPKdS1_S1_iiiiiiii, .-_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	.globl	_Z7maxdiffPKdS0_i
	.type	_Z7maxdiffPKdS0_i, @function
_Z7maxdiffPKdS0_i:
.LFB3918:
	.cfi_startproc
	endbr64
	movq	.LC5(%rip), %xmm2
	xorl	%eax, %eax
	xorps	%xmm1, %xmm1
.L13:
	cmpl	%eax, %edx
	jle	.L16
	movsd	(%rdi,%rax,8), %xmm0
	subsd	(%rsi,%rax,8), %xmm0
	incq	%rax
	andps	%xmm2, %xmm0
	maxsd	%xmm1, %xmm0
	movaps	%xmm0, %xmm1
	jmp	.L13
.L16:
	movaps	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE3918:
	.size	_Z7maxdiffPKdS0_i, .-_Z7maxdiffPKdS0_i
	.globl	_Z45__device_stub__Z9advec_gpuPdPKdS1_S1_iiiiiiiiPdPKdS1_S1_iiiiiiii
	.type	_Z45__device_stub__Z9advec_gpuPdPKdS1_S1_iiiiiiiiPdPKdS1_S1_iiiiiiii, @function
_Z45__device_stub__Z9advec_gpuPdPKdS1_S1_iiiiiiiiPdPKdS1_S1_iiiiiiii:
.LFB3944:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	64(%rsp), %rcx
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z9advec_gpuPdPKdS1_S1_iiiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L17:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3944:
	.size	_Z45__device_stub__Z9advec_gpuPdPKdS1_S1_iiiiiiiiPdPKdS1_S1_iiiiiiii, .-_Z45__device_stub__Z9advec_gpuPdPKdS1_S1_iiiiiiiiPdPKdS1_S1_iiiiiiii
	.globl	_Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.type	_Z9advec_gpuPdPKdS1_S1_iiiiiiii, @function
_Z9advec_gpuPdPKdS1_S1_iiiiiiii:
.LFB3945:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z9advec_gpuPdPKdS1_S1_iiiiiiiiPdPKdS1_S1_iiiiiiii
	.cfi_endproc
.LFE3945:
	.size	_Z9advec_gpuPdPKdS1_S1_iiiiiiii, .-_Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.globl	_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii
	.type	_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii, @function
_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii:
.LFB3946:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	56(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 256
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L22:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3946:
	.size	_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii, .-_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii
	.globl	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.type	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii, @function
_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii:
.LFB3947:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii
	.cfi_endproc
.LFE3947:
	.size	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii, .-_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC8:
	.string	"CPU; elapsed=%f [ms]\n"
.LC9:
	.string	"GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3919:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$143877824, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$143877824, %edi
	movq	%rax, %r13
	call	_Znam@PLT
	movl	$143877824, %edi
	movq	%rax, %r14
	call	_Znam@PLT
	movl	$143877824, %edi
	movq	%rax, %r15
	call	_Znam@PLT
	movl	$143877824, %edi
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	movq	%rax, %r12
.L28:
	call	rand@PLT
	movl	$1000, %ebp
	cltd
	idivl	%ebp
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC6(%rip), %xmm0
	subsd	.LC7(%rip), %xmm0
	movsd	%xmm0, 0(%r13,%rbx)
	call	rand@PLT
	cltd
	idivl	%ebp
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC6(%rip), %xmm0
	subsd	.LC7(%rip), %xmm0
	movsd	%xmm0, (%r14,%rbx)
	call	rand@PLT
	movq	$0x000000000, (%r12,%rbx)
	cltd
	idivl	%ebp
	movq	8(%rsp), %rax
	movq	$0x000000000, (%rax,%rbx)
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC6(%rip), %xmm0
	subsd	.LC7(%rip), %xmm0
	movsd	%xmm0, (%r15,%rbx)
	addq	$8, %rbx
	cmpq	$143877824, %rbx
	jne	.L28
	leaq	32(%rsp), %rdi
	movl	$149369448, %esi
	movl	$10, %ebp
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$149369448, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$149369448, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$149369448, %esi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rax
	movl	$2096, %ecx
	movq	%r13, %rdx
	pushq	%r9
	.cfi_def_cfa_offset 184
	movl	$2096, %r8d
	movl	$68644, %r9d
	movl	$2176, %esi
	pushq	$1
	.cfi_def_cfa_offset 192
	leaq	104(%rax), %rdi
	call	cudaMemcpy2D@PLT
	movq	56(%rsp), %rax
	movl	$68644, %r9d
	movq	%r14, %rdx
	movl	$2096, %r8d
	movl	$2096, %ecx
	movl	$2176, %esi
	movl	$1, (%rsp)
	leaq	104(%rax), %rdi
	call	cudaMemcpy2D@PLT
	movq	64(%rsp), %rax
	movl	$68644, %r9d
	movq	%r15, %rdx
	movl	$2096, %r8d
	movl	$2096, %ecx
	movl	$2176, %esi
	movl	$1, (%rsp)
	leaq	104(%rax), %rdi
	call	cudaMemcpy2D@PLT
	movq	72(%rsp), %rax
	movq	24(%rsp), %rdx
	movl	$68644, %r9d
	movl	$2096, %r8d
	movl	$2096, %ecx
	movl	$2176, %esi
	movl	$1, (%rsp)
	leaq	104(%rax), %rdi
	call	cudaMemcpy2D@PLT
	movl	$1, 104(%rsp)
	movabsq	$137438953480, %rax
	movq	%rax, 96(%rsp)
	movl	$1073741825, %eax
	salq	$5, %rax
	movl	$1, 116(%rsp)
	movq	%rax, 108(%rsp)
	popq	%r10
	.cfi_def_cfa_offset 184
	popq	%r11
	.cfi_def_cfa_offset 176
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L29:
	pushq	$68644
	.cfi_def_cfa_offset 184
	movq	%r15, %rcx
	movq	%r14, %rdx
	movq	%r13, %rsi
	pushq	$262
	.cfi_def_cfa_offset 192
	movl	$259, %r9d
	movl	$3, %r8d
	pushq	$259
	.cfi_def_cfa_offset 200
	pushq	$3
	.cfi_def_cfa_offset 208
	pushq	$259
	.cfi_def_cfa_offset 216
	pushq	$3
	.cfi_def_cfa_offset 224
	movq	56(%rsp), %rdi
	call	_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	addq	$48, %rsp
	.cfi_def_cfa_offset 176
	decl	%ebp
	jne	.L29
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	movl	$10, %ebp
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	24(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	24(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	call	cudaDeviceSetSharedMemConfig@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L31:
	movl	100(%rsp), %ecx
	movq	92(%rsp), %rdx
	xorl	%r9d, %r9d
	movl	$8512, %r8d
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	48(%rsp), %rax
	movl	$259, %r9d
	leaq	104(%rax), %rcx
	movq	40(%rsp), %rax
	leaq	104(%rax), %rdx
	movq	32(%rsp), %rax
	leaq	104(%rax), %rsi
	movq	56(%rsp), %rax
	pushq	%r8
	.cfi_def_cfa_offset 184
	movl	$3, %r8d
	pushq	$3
	.cfi_def_cfa_offset 192
	pushq	$71264
	.cfi_def_cfa_offset 200
	leaq	104(%rax), %rdi
	pushq	$272
	.cfi_def_cfa_offset 208
	pushq	$259
	.cfi_def_cfa_offset 216
	pushq	$3
	.cfi_def_cfa_offset 224
	pushq	$259
	.cfi_def_cfa_offset 232
	pushq	$3
	.cfi_def_cfa_offset 240
	call	_Z52__device_stub__Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiiiPdPKdS1_S1_iiiiiiiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 176
.L30:
	decl	%ebp
	jne	.L31
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	56(%rsp), %rax
	movl	$2176, %ecx
	movq	%r12, %rdi
	movl	$2096, %esi
	movl	$68644, %r9d
	movl	$2096, %r8d
	leaq	104(%rax), %rdx
	pushq	%rax
	.cfi_def_cfa_offset 184
	pushq	$2
	.cfi_def_cfa_offset 192
	call	cudaMemcpy2D@PLT
	movq	24(%rsp), %rdi
	movl	$17984728, %edx
	movq	%r12, %rsi
	call	_Z7maxdiffPKdS0_i
	movss	44(%rsp), %xmm3
	popq	%rdx
	.cfi_def_cfa_offset 184
	leaq	.LC9(%rip), %rsi
	popq	%rcx
	.cfi_def_cfa_offset 176
	movss	24(%rsp), %xmm1
	movaps	%xmm0, %xmm2
	movl	$2, %edi
	movb	$3, %al
	cvtss2sd	%xmm3, %xmm0
	divss	%xmm3, %xmm1
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3919:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii"
.LC11:
	.string	"_Z9advec_gpuPdPKdS1_S1_iiiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3949:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9advec_gpuPdPKdS1_S1_iiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3949:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	-1078984704
	.align 8
.LC1:
	.long	0
	.long	1071775744
	.align 8
.LC2:
	.long	1431655765
	.long	1067799893
	.align 8
.LC3:
	.long	0
	.long	1072824320
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC5:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC6:
	.long	-755914244
	.long	1062232653
	.align 8
.LC7:
	.long	0
	.long	1071644672
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <stdlib.h>
#include <cstdio>

// Fourth order interpolation function.
__host__ __device__ inline double interp(const double m2, const double m1, const double p1, const double p2)
{
  return (-1./16)*(m2+p2) + (9./16)*(m1+p1);
}

// Fourth order gradient function.
__host__ __device__ inline double grad(const double m2, const double m1, const double p1, const double p2)
{
  return (1./24.)*(m2-p2) + (27./24.)*(p1-m1);
}

/* 
4th order advection on cpu
*/
void advec_cpu(double * const __restrict__ ut, 
               const double * const __restrict__ u, const double * const __restrict__ v, const double * const __restrict__ w,
               const int istart, const int iend, 
               const int jstart, const int jend, 
               const int kstart, const int kend, 
               const int icells, const int ijcells)
{
    const int ii1 = 1;
    const int ii2 = 2;
    const int ii3 = 3;
    const int jj1 = 1*icells;
    const int jj2 = 2*icells;
    const int jj3 = 3*icells;
    const int kk1 = 1*ijcells;
    const int kk2 = 2*ijcells;
    const int kk3 = 3*ijcells;

    for (int k=kstart; k<kend; ++k)
        for (int j=jstart; j<jend; ++j)
            #pragma ivdep
            for (int i=istart; i<iend; ++i)
            {
                const int ijk = i + j*icells + k*ijcells;

                ut[ijk] += grad( interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ) * interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ),
                                 interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ) * interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ),
                                 interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ) * interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ),
                                 interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ) * interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ))

                         + grad( interp( v[ijk-ii2-jj1], v[ijk-ii1-jj1], v[ijk-jj1], v[ijk+ii1-jj1] ) * interp( u[ijk-jj3], u[ijk-jj2], u[ijk-jj1], u[ijk    ] ),
                                 interp( v[ijk-ii2    ], v[ijk-ii1    ], v[ijk    ], v[ijk+ii1    ] ) * interp( u[ijk-jj2], u[ijk-jj1], u[ijk    ], u[ijk+jj1] ),
                                 interp( v[ijk-ii2+jj1], v[ijk-ii1+jj1], v[ijk+jj1], v[ijk+ii1+jj1] ) * interp( u[ijk-jj1], u[ijk    ], u[ijk+jj1], u[ijk+jj2] ),
                                 interp( v[ijk-ii2+jj2], v[ijk-ii1+jj2], v[ijk+jj2], v[ijk+ii1+jj2] ) * interp( u[ijk    ], u[ijk+jj1], u[ijk+jj2], u[ijk+jj3] ))

                         + grad( interp( w[ijk-ii2-kk1], w[ijk-ii1-kk1], w[ijk-kk1], w[ijk+ii1-kk1] ) * interp( u[ijk-kk3], u[ijk-kk2], u[ijk-kk1], u[ijk    ] ),
                                 interp( w[ijk-ii2    ], w[ijk-ii1    ], w[ijk    ], w[ijk+ii1    ] ) * interp( u[ijk-kk2], u[ijk-kk1], u[ijk    ], u[ijk+kk1] ),
                                 interp( w[ijk-ii2+kk1], w[ijk-ii1+kk1], w[ijk+kk1], w[ijk+ii1+kk1] ) * interp( u[ijk-kk1], u[ijk    ], u[ijk+kk1], u[ijk+kk2] ),
                                 interp( w[ijk-ii2+kk2], w[ijk-ii1+kk2], w[ijk+kk2], w[ijk+ii1+kk2] ) * interp( u[ijk    ], u[ijk+kk1], u[ijk+kk2], u[ijk+kk3] ));
            }
}


/* 
4th order advection (3D), no shared memory use
*/
__global__ void advec_gpu(double * const __restrict__ ut, 
                          const double * const __restrict__ u, const double * const __restrict__ v, const double * const __restrict__ w,
                          const int istart, const int iend, 
                          const int jstart, const int jend, 
                          const int kstart, const int kend, 
                          const int icells, const int ijcells)
{
    const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
    const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
    const int k = blockIdx.z + kstart;

    if(i < iend && j < jend && k < kend)
    {
        const int ijk = i + j*icells + k*ijcells;

        const int ii1 = 1;
        const int ii2 = 2;
        const int ii3 = 3;
        const int jj1 = 1*icells;
        const int jj2 = 2*icells;
        const int jj3 = 3*icells;
        const int kk1 = 1*ijcells;
        const int kk2 = 2*ijcells;
        const int kk3 = 3*ijcells;

        ut[ijk] += grad( interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ) * interp( u[ijk-ii3], u[ijk-ii2], u[ijk-ii1], u[ijk    ] ),
                         interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ) * interp( u[ijk-ii2], u[ijk-ii1], u[ijk    ], u[ijk+ii1] ),
                         interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ) * interp( u[ijk-ii1], u[ijk    ], u[ijk+ii1], u[ijk+ii2] ),
                         interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ) * interp( u[ijk    ], u[ijk+ii1], u[ijk+ii2], u[ijk+ii3] ))

                 + grad( interp( v[ijk-ii2-jj1], v[ijk-ii1-jj1], v[ijk-jj1], v[ijk+ii1-jj1] ) * interp( u[ijk-jj3], u[ijk-jj2], u[ijk-jj1], u[ijk    ] ),
                         interp( v[ijk-ii2    ], v[ijk-ii1    ], v[ijk    ], v[ijk+ii1    ] ) * interp( u[ijk-jj2], u[ijk-jj1], u[ijk    ], u[ijk+jj1] ),
                         interp( v[ijk-ii2+jj1], v[ijk-ii1+jj1], v[ijk+jj1], v[ijk+ii1+jj1] ) * interp( u[ijk-jj1], u[ijk    ], u[ijk+jj1], u[ijk+jj2] ),
                         interp( v[ijk-ii2+jj2], v[ijk-ii1+jj2], v[ijk+jj2], v[ijk+ii1+jj2] ) * interp( u[ijk    ], u[ijk+jj1], u[ijk+jj2], u[ijk+jj3] ))

                 + grad( interp( w[ijk-ii2-kk1], w[ijk-ii1-kk1], w[ijk-kk1], w[ijk+ii1-kk1] ) * interp( u[ijk-kk3], u[ijk-kk2], u[ijk-kk1], u[ijk    ] ),
                         interp( w[ijk-ii2    ], w[ijk-ii1    ], w[ijk    ], w[ijk+ii1    ] ) * interp( u[ijk-kk2], u[ijk-kk1], u[ijk    ], u[ijk+kk1] ),
                         interp( w[ijk-ii2+kk1], w[ijk-ii1+kk1], w[ijk+kk1], w[ijk+ii1+kk1] ) * interp( u[ijk-kk1], u[ijk    ], u[ijk+kk1], u[ijk+kk2] ),
                         interp( w[ijk-ii2+kk2], w[ijk-ii1+kk2], w[ijk+kk2], w[ijk+ii1+kk2] ) * interp( u[ijk    ], u[ijk+kk1], u[ijk+kk2], u[ijk+kk3] ));
    }
}

/* 
4th order advection, smem
*/
__global__ void advec_gpu_smem(double * const __restrict__ ut, 
                               const double * const __restrict__ u, const double * const __restrict__ v, const double * const __restrict__ w, 
                               const int istart, const int iend, 
                               const int jstart, const int jend, 
                               const int kstart, const int kend, 
                               const int icells, const int ijcells, const int ngc)
{
    extern __shared__ double shared[]; 
    const int smem_block = (blockDim.x + 2*ngc) * (blockDim.y + 2*ngc);
    double *us = &shared[0];
    double *vs = &shared[smem_block];

    const int tx = threadIdx.x;
    const int ty = threadIdx.y;
    const int i  = blockIdx.x*blockDim.x + threadIdx.x + istart;
    const int j  = blockIdx.y*blockDim.y + threadIdx.y + jstart;
    const int blockxpad = blockDim.x+2*ngc;

    if(i < iend && j < jend)
    {
        const int ii1 = 1;
        const int ii2 = 2;
        const int ii3 = 3;
        const int jj1 = 1*icells;
        const int jj2 = 2*icells;
        const int jj3 = 3*icells;
        const int kk1 = 1*ijcells;
        const int kk2 = 2*ijcells;
        const int kk3 = 3*ijcells;
        const int kk4 = 4*ijcells;

        const int jjs1 = 1*blockxpad;
        const int jjs2 = 2*blockxpad;
        const int jjs3 = 3*blockxpad;

        int ijk;
        const int ijks = (tx+ngc) + (ty+ngc)*blockxpad;

        for(int k=kstart; k<kend; ++k)
        {
            ijk  = i + j*icells + k*ijcells; // index in global memory
 
            us[ijks] = u[ijk];
            vs[ijks] = v[ijk];

            if(ty < ngc)
            {
                us[ijks-jjs3] = u[ijk-jj3];
                vs[ijks-jjs3] = v[ijk-jj3];
            }
            if(ty >= blockDim.y-ngc)
            {
                us[ijks+jjs3] = u[ijk+jj3];
                vs[ijks+jjs3] = v[ijk+jj3];
            }

            if(tx < ngc)
            {
                us[ijks-ngc] = u[ijk-ngc];
                vs[ijks-ngc] = v[ijk-ngc];

                if(ty < ngc)
                {
                    us[ijks-jjs3-ngc] = u[ijk-jj3-ngc];
                    vs[ijks-jjs3-ngc] = v[ijk-jj3-ngc];
                }
                if(ty >= blockDim.y-ngc)
                {
                    us[ijks+jjs3-ngc] = u[ijk+jj3-ngc];
                    vs[ijks+jjs3-ngc] = v[ijk+jj3-ngc];
                }
            }
            if(tx >= blockDim.x-ngc)
            {
                us[ijks+ngc] = u[ijk+ngc];
                vs[ijks+ngc] = v[ijk+ngc];

                if(ty < ngc)
                {
                    us[ijks-jjs3+ngc] = u[ijk-jj3+ngc];
                    vs[ijks-jjs3+ngc] = v[ijk-jj3+ngc];
                }
                if(ty >= blockDim.y-ngc)
                {
                    us[ijks+jjs3+ngc] = u[ijk+jj3+ngc];
                    vs[ijks+jjs3+ngc] = v[ijk+jj3+ngc];
                }
            }

            __syncthreads();

            ut[ijk] += grad( interp( us[ijks-ii3], us[ijks-ii2], us[ijks-ii1], us[ijks    ] ) * interp( us[ijks-ii3], us[ijks-ii2], us[ijks-ii1], us[ijks    ] ),
                             interp( us[ijks-ii2], us[ijks-ii1], us[ijks    ], us[ijks+ii1] ) * interp( us[ijks-ii2], us[ijks-ii1], us[ijks    ], us[ijks+ii1] ),
                             interp( us[ijks-ii1], us[ijks    ], us[ijks+ii1], us[ijks+ii2] ) * interp( us[ijks-ii1], us[ijks    ], us[ijks+ii1], us[ijks+ii2] ),
                             interp( us[ijks    ], us[ijks+ii1], us[ijks+ii2], us[ijks+ii3] ) * interp( us[ijks    ], us[ijks+ii1], us[ijks+ii2], us[ijks+ii3] ))

                     + grad( interp( vs[ijks-ii2-jjs1], vs[ijks-ii1-jjs1], vs[ijks-jjs1], vs[ijks+ii1-jjs1] ) * interp( us[ijks-jjs3], us[ijks-jjs2], us[ijks-jjs1], us[ijks     ] ),
                             interp( vs[ijks-ii2    ],  vs[ijks-ii1     ], vs[ijks    ],  vs[ijks+ii1     ] ) * interp( us[ijks-jjs2], us[ijks-jjs1], us[ijks     ], us[ijks+jjs1] ),
                             interp( vs[ijks-ii2+jjs1], vs[ijks-ii1+jjs1], vs[ijks+jjs1], vs[ijks+ii1+jjs1] ) * interp( us[ijks-jjs1], us[ijks     ], us[ijks+jjs1], us[ijks+jjs2] ),
                             interp( vs[ijks-ii2+jjs2], vs[ijks-ii1+jjs2], vs[ijks+jjs2], vs[ijks+ii1+jjs2] ) * interp( us[ijks     ], us[ijks+jjs1], us[ijks+jjs2], us[ijks+jjs3] ))

                     + grad( interp( w[ijk-ii2-kk1], w[ijk-ii1-kk1], w[ijk-kk1], w[ijk+ii1-kk1] ) * interp( u[ijk-kk3], u[ijk-kk2], u[ijk-kk1], us[ijks  ] ),
                             interp( w[ijk-ii2    ], w[ijk-ii1    ], w[ijk    ], w[ijk+ii1    ] ) * interp( u[ijk-kk2], u[ijk-kk1], us[ijks  ], u[ijk+kk1] ),
                             interp( w[ijk-ii2+kk1], w[ijk-ii1+kk1], w[ijk+kk1], w[ijk+ii1+kk1] ) * interp( u[ijk-kk1], us[ijks  ], u[ijk+kk1], u[ijk+kk2] ),
                             interp( w[ijk-ii2+kk2], w[ijk-ii1+kk2], w[ijk+kk2], w[ijk+ii1+kk2] ) * interp( us[ijks  ], u[ijk+kk1], u[ijk+kk2], u[ijk+kk3] ));
        }
    }
}


/* 
Get max difference between two fields
*/
double maxdiff(const double * const __restrict__ a, const double * const __restrict__ b, const int n)
{
    double maxdiff=0;
    double diff=0;
    for(int i=0; i<n; ++i)
    {
        diff = std::abs(a[i]-b[i]);
        if(diff > maxdiff)
            maxdiff = diff;
    }
    return maxdiff;
}

int main()
{
    //
    // Grid
    //
    const int itot = 256;
    const int jtot = 256;
    const int ktot = 256;
    const int gc   = 3;
    const int iter = 10;
    
    //
    // Calculate the required variables.
    //
    const int ncells  = (itot+2*gc)*(jtot+2*gc)*(ktot+2*gc);
    const int istart  = gc;
    const int jstart  = gc;
    const int kstart  = gc;
    const int iend    = itot+gc;
    const int jend    = jtot+gc;
    const int kend    = ktot+gc;
    const int icells  = itot+2*gc;
    const int jcells  = jtot+2*gc;
    const int kcells  = ktot+2*gc;
    const int ijcells = (itot+2*gc)*(jtot+2*gc);
    
    // Padded settings, interior aligned to 128 byte blocks
    const int mo        = 16 - gc;           // Padding at start of array 
    const int pl        = 16-(int)itot%16;   // Elements left in last 128 byte block
    const int icellsp   = itot + pl + (pl < 2*gc)*16;
    const int ijcellsp  = icellsp * jcells;  
    const int ncellsp   = ijcellsp * kcells + mo;
    
    //
    // Prepare fields on HOST
    //
    double *u    = new double[ncells];
    double *v    = new double[ncells];
    double *w    = new double[ncells];
    double *ut   = new double[ncells];
    double *tmp1 = new double[ncells];
    
    for (int n=0; n<ncells; ++n)
    {
    	u [n]   = 0.001 * (std::rand() % 1000) - 0.5;
    	v [n]   = 0.001 * (std::rand() % 1000) - 0.5;
    	w [n]   = 0.001 * (std::rand() % 1000) - 0.5;
    	ut[n]   = 0.;
    	tmp1[n] = 0.;
    }
    
    // 
    // Prepare fields on DEVICE
    //
    double *ud, *vd, *wd, *utd;
    hipMalloc((void **)&ud,  ncellsp*sizeof(double));
    hipMalloc((void **)&vd,  ncellsp*sizeof(double));
    hipMalloc((void **)&wd,  ncellsp*sizeof(double));
    hipMalloc((void **)&utd, ncellsp*sizeof(double));
    hipMemcpy2D(&ud[mo],  icellsp*sizeof(double),  u,  icells*sizeof(double), icells*sizeof(double), jcells*kcells, hipMemcpyHostToDevice);
    hipMemcpy2D(&vd[mo],  icellsp*sizeof(double),  v,  icells*sizeof(double), icells*sizeof(double), jcells*kcells, hipMemcpyHostToDevice);
    hipMemcpy2D(&wd[mo],  icellsp*sizeof(double),  w,  icells*sizeof(double), icells*sizeof(double), jcells*kcells, hipMemcpyHostToDevice);
    hipMemcpy2D(&utd[mo], icellsp*sizeof(double),  ut, icells*sizeof(double), icells*sizeof(double), jcells*kcells, hipMemcpyHostToDevice);
    
    //
    // CUDA thread blocks
    //
    const int blocki = 32;
    const int blockj = 8;
    const int gridi  = itot/blocki + (itot%blocki > 0);
    const int gridj  = jtot/blockj + (jtot%blockj > 0);
    dim3 gridGPU  (gridi, gridj, ktot);
    dim3 gridGPU2d(gridi, gridj, 1);
    dim3 blockGPU(blocki, blockj, 1);

    // 
    // Timer stuff
    //
    hipEvent_t startEvent, stopEvent;
    hipEventCreate(&startEvent);
    hipEventCreate(&stopEvent);
    float  dt1, dt2;

    //
    // Execute kernels
    //
    //////////////////// CPU //////////////////////////
    hipEventRecord(startEvent, 0);
    for(int n=0; n<iter; ++n) // iter+1 since GPU version is warmed up with one call
    {
       advec_cpu(ut, u, v, w,istart, iend, jstart, jend, kstart, kend, icells, ijcells);
    }
    hipEventRecord(stopEvent, 0);
    hipEventSynchronize(stopEvent);
    hipEventElapsedTime(&dt1, startEvent, stopEvent);
    printf("CPU; elapsed=%f [ms]\n",dt1);
 
    ////////////////////// GPU //////////////////////////
    hipDeviceSetSharedMemConfig(hipSharedMemBankSizeEightByte);

    hipEventRecord(startEvent, 0);
    for(int n=0; n<iter; ++n)
    {
        //advec_gpu<<<gridGPU, blockGPU>>> 
        //         (&utd[mo], &ud[mo], &vd[mo], &wd[mo], istart, iend, jstart, jend, kstart, kend, icellsp, ijcellsp);
        advec_gpu_smem<<<gridGPU2d, blockGPU, 2*(blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>> 
                 (&utd[mo], &ud[mo], &vd[mo], &wd[mo], istart, iend, jstart, jend, kstart, kend, icellsp, ijcellsp, gc);
    }
    hipEventRecord(stopEvent, 0);
    hipEventSynchronize(stopEvent);
    hipEventElapsedTime(&dt2, startEvent, stopEvent);

    //
    // Copy device field to tmp1 
    //
    hipMemcpy2D(tmp1, icells*sizeof(double), &utd[mo], icellsp*sizeof(double), icells*sizeof(double), jcells*kcells, hipMemcpyDeviceToHost);

    printf("GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n",dt2,dt1/dt2,maxdiff(ut,tmp1,ncells));

    return 0;
}

	.text
	.file	"advec4.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9advec_cpuPdPKdS1_S1_iiiiiiii
.LCPI0_0:
	.quad	0x3fb0000000000000              # double 0.0625
.LCPI0_1:
	.quad	0x3fe2000000000000              # double 0.5625
.LCPI0_2:
	.quad	0x3fa5555555555555              # double 0.041666666666666664
.LCPI0_3:
	.quad	0x3ff2000000000000              # double 1.125
	.text
	.globl	_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	.type	_Z9advec_cpuPdPKdS1_S1_iiiiiiii,@function
_Z9advec_cpuPdPKdS1_S1_iiiiiiii:        # @_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$400, %rsp                      # imm = 0x190
	.cfi_def_cfa_offset 456
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, -104(%rsp)                # 4-byte Spill
	movl	%r8d, -108(%rsp)                # 4-byte Spill
	movl	472(%rsp), %ebx
	cmpl	480(%rsp), %ebx
	jge	.LBB0_8
# %bb.1:                                # %.preheader266.lr.ph
	movq	%rcx, %r9
	movq	%rdi, %r14
	movl	496(%rsp), %r10d
	movl	488(%rsp), %r13d
	movl	456(%rsp), %ebp
	movl	-108(%rsp), %r11d               # 4-byte Reload
	movslq	%r11d, %r8
	movslq	-104(%rsp), %rdi                # 4-byte Folded Reload
	subq	%r8, %rdi
	movq	%rdi, 344(%rsp)                 # 8-byte Spill
	leal	-1(%rbx), %eax
	imull	%r10d, %eax
	movq	%rax, -120(%rsp)                # 8-byte Spill
	leal	1(%rbx), %eax
	imull	%r10d, %eax
	movq	%rax, -128(%rsp)                # 8-byte Spill
	leal	2(%rbx), %eax
	imull	%r10d, %eax
	movq	%rax, -40(%rsp)                 # 8-byte Spill
	leal	-3(%rbx), %eax
	imull	%r10d, %eax
	leal	-2(%rbx), %edi
	imull	%r10d, %edi
	movq	%rdi, -48(%rsp)                 # 8-byte Spill
	leal	3(%rbx), %edi
	imull	%r10d, %edi
	movq	%rdi, -56(%rsp)                 # 8-byte Spill
	movl	%r10d, %r8d
	imull	%ebx, %r8d
	addl	%r11d, %r8d
	leal	-1(%rbp), %ebx
	imull	%r13d, %ebx
	movq	%r14, 352(%rsp)                 # 8-byte Spill
	leal	1(%rbp), %r14d
	imull	%r13d, %r14d
	leal	2(%rbp), %r15d
	imull	%r13d, %r15d
	leal	-3(%rbp), %edi
	imull	%r13d, %edi
	leal	-2(%rbp), %ecx
	imull	%r13d, %ecx
	leal	3(%rbp), %r10d
	imull	%r13d, %r10d
	movl	%r13d, %r12d
	imull	%ebp, %r12d
	leal	(%r8,%rbx), %r13d
	movq	%r13, -64(%rsp)                 # 8-byte Spill
	leal	(%rbx,%r8), %r13d
	decl	%r13d
	leal	-2(%rbx,%r8), %ebx
	movq	%rbx, 88(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbx
	leal	(%r8,%r14), %edi
	movq	%rdi, -72(%rsp)                 # 8-byte Spill
	leal	-1(%r14,%r8), %edi
	movq	%rdi, 80(%rsp)                  # 8-byte Spill
	leal	-2(%r14,%r8), %edi
	movq	%rdi, 72(%rsp)                  # 8-byte Spill
	movq	%rcx, %r14
	leal	(%r8,%r15), %edi
	leal	-1(%r15,%r8), %ecx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	leal	(%r15,%r8), %ecx
	addl	$-2, %ecx
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movq	%r10, %r15
	addl	%r8d, %ebx
	movq	%rbx, 96(%rsp)                  # 8-byte Spill
	addl	%r8d, %r14d
	addl	%r8d, %r15d
	leal	(%r8,%r12), %ecx
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	leal	(%r12,%r8), %ecx
	decl	%ecx
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	leal	(%r12,%r8), %ecx
	addl	$-2, %ecx
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
                                        # kill: def $r12d killed $r12d killed $r12 def $r12
	addl	%r11d, %r12d
	movq	-120(%rsp), %r8                 # 8-byte Reload
	leal	(%r12,%r8), %ecx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	leal	(%r8,%r12), %ecx
	decl	%ecx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	leal	-2(%r8,%r12), %ebp
	movq	-48(%rsp), %r8                  # 8-byte Reload
	movq	-128(%rsp), %r10                # 8-byte Reload
	leal	(%r12,%r10), %ecx
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	leal	-1(%r10,%r12), %ecx
	movq	%rcx, (%rsp)                    # 8-byte Spill
	leal	-2(%r10,%r12), %ecx
	movq	%rcx, -8(%rsp)                  # 8-byte Spill
	movq	-56(%rsp), %rcx                 # 8-byte Reload
	movq	-64(%rsp), %r10                 # 8-byte Reload
	movq	-40(%rsp), %rbx                 # 8-byte Reload
	leal	(%r12,%rbx), %r11d
	movq	%r11, -16(%rsp)                 # 8-byte Spill
	leal	-1(%rbx,%r12), %r11d
	movq	%r11, -24(%rsp)                 # 8-byte Spill
	leal	(%rbx,%r12), %r11d
	addl	$-2, %r11d
	movq	%r11, -32(%rsp)                 # 8-byte Spill
	addl	%r12d, %eax
	addl	%r12d, %r8d
	addl	%r12d, %ecx
	movq	-72(%rsp), %r12                 # 8-byte Reload
	movl	496(%rsp), %r11d
	movq	%r11, 280(%rsp)                 # 8-byte Spill
	movl	488(%rsp), %r11d
	movq	%r11, 336(%rsp)                 # 8-byte Spill
	movl	472(%rsp), %ebx
	movsd	.LCPI0_0(%rip), %xmm5           # xmm5 = mem[0],zero
	movsd	.LCPI0_1(%rip), %xmm14          # xmm14 = mem[0],zero
.LBB0_2:                                # %.preheader266
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_3 Depth 2
                                        #       Child Loop BB0_5 Depth 3
	movq	%r13, 104(%rsp)                 # 8-byte Spill
	movq	%rbx, 328(%rsp)                 # 8-byte Spill
	movq	%rcx, -56(%rsp)                 # 8-byte Spill
	movq	%r8, -48(%rsp)                  # 8-byte Spill
	movq	%r8, %r11
	movq	%rax, 320(%rsp)                 # 8-byte Spill
	movq	%rax, %r13
	movq	%r15, 304(%rsp)                 # 8-byte Spill
	movq	%r14, 312(%rsp)                 # 8-byte Spill
	movq	%rbp, %rbx
	movq	96(%rsp), %rbp                  # 8-byte Reload
	movq	%r10, -64(%rsp)                 # 8-byte Spill
	movq	%r10, %r8
	movq	%r12, -72(%rsp)                 # 8-byte Spill
	movq	%rdi, 296(%rsp)                 # 8-byte Spill
	movq	%rdi, %rax
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	8(%rsp), %r10                   # 8-byte Reload
	movq	%r10, 112(%rsp)                 # 8-byte Spill
	movq	-16(%rsp), %r10                 # 8-byte Reload
	movq	%r10, 128(%rsp)                 # 8-byte Spill
	movq	48(%rsp), %r10                  # 8-byte Reload
	movq	%r10, 120(%rsp)                 # 8-byte Spill
	movq	-32(%rsp), %r10                 # 8-byte Reload
	movq	%r10, -80(%rsp)                 # 8-byte Spill
	movq	-8(%rsp), %r10                  # 8-byte Reload
	movq	%r10, 216(%rsp)                 # 8-byte Spill
	movq	%rbx, 288(%rsp)                 # 8-byte Spill
	movq	%rbx, 208(%rsp)                 # 8-byte Spill
	movq	56(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, 200(%rsp)                 # 8-byte Spill
	movq	72(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, 192(%rsp)                 # 8-byte Spill
	movq	88(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, 184(%rsp)                 # 8-byte Spill
	movq	32(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, -88(%rsp)                 # 8-byte Spill
	movq	-24(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, -96(%rsp)                 # 8-byte Spill
	movq	(%rsp), %rbx                    # 8-byte Reload
	movq	%rbx, 176(%rsp)                 # 8-byte Spill
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, 168(%rsp)                 # 8-byte Spill
	movq	64(%rsp), %r10                  # 8-byte Reload
	movq	%r10, 160(%rsp)                 # 8-byte Spill
	movq	80(%rsp), %r10                  # 8-byte Reload
	movq	%r10, 152(%rsp)                 # 8-byte Spill
	movq	104(%rsp), %r10                 # 8-byte Reload
	movq	%r10, 144(%rsp)                 # 8-byte Spill
	movq	40(%rsp), %r10                  # 8-byte Reload
	movq	%r10, 136(%rsp)                 # 8-byte Spill
	movl	456(%rsp), %r10d
	movq	%r10, %rbx
	movl	%r10d, -100(%rsp)               # 4-byte Spill
	cmpl	464(%rsp), %ebx
	jge	.LBB0_7
.LBB0_3:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_5 Depth 3
	movq	%r12, 224(%rsp)                 # 8-byte Spill
	movq	%r8, 232(%rsp)                  # 8-byte Spill
	movq	%rbp, 240(%rsp)                 # 8-byte Spill
	movq	%r13, 248(%rsp)                 # 8-byte Spill
	movq	%r14, 256(%rsp)                 # 8-byte Spill
	movq	%r15, 264(%rsp)                 # 8-byte Spill
	movq	%r11, 272(%rsp)                 # 8-byte Spill
	movl	-108(%rsp), %r10d               # 4-byte Reload
	cmpl	-104(%rsp), %r10d               # 4-byte Folded Reload
	movq	%rax, %r12
	movq	%rdi, %rax
	movq	112(%rsp), %rdi                 # 8-byte Reload
	movq	128(%rsp), %rbx                 # 8-byte Reload
	movq	120(%rsp), %r8                  # 8-byte Reload
	movq	-80(%rsp), %r15                 # 8-byte Reload
	movq	-88(%rsp), %r14                 # 8-byte Reload
	movq	-96(%rsp), %rbp                 # 8-byte Reload
	jge	.LBB0_6
# %bb.4:                                # %.lr.ph
                                        #   in Loop: Header=BB0_3 Depth=2
	xorl	%r13d, %r13d
	movq	%rcx, 360(%rsp)                 # 8-byte Spill
	movq	%r15, -80(%rsp)                 # 8-byte Spill
	movq	%r14, -88(%rsp)                 # 8-byte Spill
	movq	%rbp, -96(%rsp)                 # 8-byte Spill
.LBB0_5:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	leal	(%r8,%r13), %r10d
	leal	(%r14,%r13), %ebp
	movslq	%r10d, %r11
	movslq	%ebp, %r10
	movq	136(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %ebp
	movslq	%ebp, %r14
	movsd	(%rsi,%r10,8), %xmm15           # xmm15 = mem[0],zero
	movsd	(%rsi,%r14,8), %xmm10           # xmm10 = mem[0],zero
	movsd	(%rsi,%r11,8), %xmm2            # xmm2 = mem[0],zero
	movsd	16(%rsi,%r11,8), %xmm0          # xmm0 = mem[0],zero
	movsd	-24(%rsi,%r11,8), %xmm1         # xmm1 = mem[0],zero
	addsd	%xmm2, %xmm1
	movapd	%xmm2, %xmm8
	leal	1(%r8,%r13), %ebp
	movslq	%ebp, %rbp
	movapd	%xmm15, %xmm3
	movsd	(%rsi,%rbp,8), %xmm2            # xmm2 = mem[0],zero
	addsd	%xmm2, %xmm15
	movapd	%xmm10, %xmm4
	addsd	%xmm10, %xmm3
	addsd	%xmm8, %xmm4
	movapd	%xmm4, %xmm7
	addsd	%xmm0, %xmm10
	movapd	%xmm8, %xmm9
	mulsd	%xmm5, %xmm1
	addsd	%xmm2, %xmm9
	movapd	%xmm2, %xmm4
	movapd	%xmm5, %xmm6
	movsd	24(%rsi,%r11,8), %xmm13         # xmm13 = mem[0],zero
	addsd	%xmm8, %xmm13
	movapd	%xmm8, %xmm11
	movsd	%xmm8, 368(%rsp)                # 8-byte Spill
	mulsd	%xmm5, %xmm15
	addsd	%xmm0, %xmm4
	movq	184(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %r15d
	movslq	%r15d, %r15
	mulsd	%xmm5, %xmm13
	movsd	(%rdx,%r15,8), %xmm12           # xmm12 = mem[0],zero
	movq	144(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %r15d
	movslq	%r15d, %r15
	movapd	%xmm14, %xmm8
	mulsd	%xmm14, %xmm3
	movapd	%xmm3, %xmm5
	movsd	(%rdx,%r15,8), %xmm0            # xmm0 = mem[0],zero
	movq	%r8, %rcx
	movq	%rbx, %r8
	movq	%rdi, %rbx
	movq	%rax, %rdi
	movq	%r12, %rax
	movq	232(%rsp), %r12                 # 8-byte Reload
	leal	1(%r12,%r13), %r15d
	movslq	%r15d, %r15
	mulsd	%xmm14, %xmm7
	movsd	%xmm7, -120(%rsp)               # 8-byte Spill
	addsd	(%rdx,%r15,8), %xmm12
	movq	256(%rsp), %r15                 # 8-byte Reload
	leal	(%r15,%r13), %r15d
	mulsd	%xmm6, %xmm10
	movslq	%r15d, %r15
	movsd	(%rsi,%r15,8), %xmm3            # xmm3 = mem[0],zero
	leal	(%r12,%r13), %r15d
	movq	%rax, %r12
	movq	%rdi, %rax
	mulsd	%xmm14, %xmm9
	movslq	%r15d, %r15
	addsd	(%rdx,%r15,8), %xmm0
	mulsd	%xmm14, %xmm4
	movsd	(%rsi,%r15,8), %xmm7            # xmm7 = mem[0],zero
	movq	240(%rsp), %r15                 # 8-byte Reload
	leal	(%r15,%r13), %r15d
	movslq	%r15d, %r15
	mulsd	%xmm6, %xmm12
	movsd	(%rsi,%r15,8), %xmm2            # xmm2 = mem[0],zero
	addsd	%xmm11, %xmm2
	mulsd	%xmm6, %xmm2
	mulsd	%xmm14, %xmm0
	movsd	%xmm0, -128(%rsp)               # 8-byte Spill
	movapd	%xmm3, %xmm11
	addsd	%xmm7, %xmm11
	movsd	(%rdx,%r10,8), %xmm0            # xmm0 = mem[0],zero
	subsd	%xmm1, %xmm5
	movsd	%xmm5, -40(%rsp)                # 8-byte Spill
	movsd	(%rdx,%r14,8), %xmm14           # xmm14 = mem[0],zero
	addsd	(%rdx,%rbp,8), %xmm0
	mulsd	%xmm8, %xmm11
	addsd	(%rdx,%r11,8), %xmm14
	movq	192(%rsp), %rdi                 # 8-byte Reload
	leal	(%rdi,%r13), %r15d
	movsd	-120(%rsp), %xmm1               # 8-byte Reload
                                        # xmm1 = mem[0],zero
	subsd	%xmm15, %xmm1
	movsd	%xmm1, -120(%rsp)               # 8-byte Spill
	movslq	%r15d, %r15
	movsd	(%rdx,%r15,8), %xmm1            # xmm1 = mem[0],zero
	movq	152(%rsp), %rdi                 # 8-byte Reload
	leal	(%rdi,%r13), %r15d
	subsd	%xmm10, %xmm9
	movsd	%xmm9, 384(%rsp)                # 8-byte Spill
	movslq	%r15d, %r15
	movsd	(%rdx,%r15,8), %xmm15           # xmm15 = mem[0],zero
	movq	224(%rsp), %rdi                 # 8-byte Reload
	leal	1(%rdi,%r13), %r15d
	mulsd	%xmm6, %xmm0
	movslq	%r15d, %r15
	addsd	(%rdx,%r15,8), %xmm1
	subsd	%xmm13, %xmm4
	movsd	%xmm4, 392(%rsp)                # 8-byte Spill
	leal	(%rdi,%r13), %r15d
	movq	%rbx, %rdi
	movq	%r8, %rbx
	movq	%rcx, %r8
	movslq	%r15d, %r15
	movsd	(%rsi,%r15,8), %xmm10           # xmm10 = mem[0],zero
	movsd	-128(%rsp), %xmm4               # 8-byte Reload
                                        # xmm4 = mem[0],zero
	subsd	%xmm12, %xmm4
	movsd	%xmm4, -128(%rsp)               # 8-byte Spill
	addsd	%xmm10, %xmm3
	mulsd	%xmm6, %xmm3
	movsd	368(%rsp), %xmm5                # 8-byte Reload
                                        # xmm5 = mem[0],zero
	movapd	%xmm5, %xmm9
	mulsd	%xmm8, %xmm14
	addsd	%xmm7, %xmm9
	addsd	(%rdx,%r15,8), %xmm15
	mulsd	%xmm8, %xmm9
	mulsd	%xmm6, %xmm1
	movq	200(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %r15d
	movslq	%r15d, %r15
	subsd	%xmm2, %xmm11
	movsd	(%rdx,%r15,8), %xmm4            # xmm4 = mem[0],zero
	movq	160(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %r15d
	movslq	%r15d, %r15
	subsd	%xmm0, %xmm14
	movsd	(%rdx,%r15,8), %xmm0            # xmm0 = mem[0],zero
	leal	1(%r12,%r13), %r15d
	movslq	%r15d, %r15
	mulsd	%xmm8, %xmm15
	addsd	(%rdx,%r15,8), %xmm4
	leal	(%r12,%r13), %r15d
	subsd	%xmm3, %xmm9
	movapd	%xmm9, %xmm13
	movslq	%r15d, %r15
	movsd	(%rsi,%r15,8), %xmm3            # xmm3 = mem[0],zero
	addsd	%xmm3, %xmm7
	subsd	%xmm1, %xmm15
	mulsd	%xmm6, %xmm7
	movapd	%xmm5, %xmm9
	movapd	%xmm5, %xmm12
	addsd	%xmm10, %xmm12
	mulsd	%xmm8, %xmm12
	addsd	(%rdx,%r15,8), %xmm0
	movq	264(%rsp), %r15                 # 8-byte Reload
	leal	(%r15,%r13), %r15d
	mulsd	%xmm6, %xmm4
	movslq	%r15d, %r15
	addsd	%xmm3, %xmm10
	movsd	(%rsi,%r15,8), %xmm1            # xmm1 = mem[0],zero
	mulsd	%xmm8, %xmm0
	addsd	%xmm5, %xmm1
	mulsd	%xmm6, %xmm1
	movq	208(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %r15d
	subsd	%xmm7, %xmm12
	movslq	%r15d, %r15
	movsd	(%r9,%r15,8), %xmm2             # xmm2 = mem[0],zero
	movq	168(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %r15d
	subsd	%xmm4, %xmm0
	movslq	%r15d, %r15
	movsd	(%r9,%r15,8), %xmm3             # xmm3 = mem[0],zero
	leal	1(%rax,%r13), %r15d
	mulsd	%xmm8, %xmm10
	movslq	%r15d, %r15
	addsd	(%r9,%r15,8), %xmm2
	subsd	%xmm1, %xmm10
	movq	272(%rsp), %r15                 # 8-byte Reload
	leal	(%r15,%r13), %r15d
	movslq	%r15d, %r15
	movsd	(%rsi,%r15,8), %xmm1            # xmm1 = mem[0],zero
	leal	(%rax,%r13), %r15d
	movslq	%r15d, %r15
	addsd	(%r9,%r15,8), %xmm3
	mulsd	%xmm6, %xmm2
	mulsd	%xmm8, %xmm3
	subsd	%xmm2, %xmm3
	movsd	(%rsi,%r15,8), %xmm5            # xmm5 = mem[0],zero
	mulsd	-128(%rsp), %xmm11              # 8-byte Folded Reload
	movsd	%xmm11, -128(%rsp)              # 8-byte Spill
	movq	248(%rsp), %r15                 # 8-byte Reload
	leal	(%r15,%r13), %r15d
	movslq	%r15d, %r15
	movsd	(%rsi,%r15,8), %xmm11           # xmm11 = mem[0],zero
	mulsd	%xmm14, %xmm13
	movsd	%xmm13, 376(%rsp)               # 8-byte Spill
	addsd	%xmm9, %xmm11
	movapd	%xmm1, %xmm4
	addsd	%xmm5, %xmm4
	mulsd	%xmm6, %xmm11
	movsd	(%r9,%r10,8), %xmm13            # xmm13 = mem[0],zero
	addsd	(%r9,%rbp,8), %xmm13
	mulsd	%xmm8, %xmm4
	subsd	%xmm11, %xmm4
	movsd	(%r9,%r14,8), %xmm11            # xmm11 = mem[0],zero
	addsd	(%r9,%r11,8), %xmm11
	mulsd	%xmm6, %xmm13
	mulsd	%xmm8, %xmm11
	subsd	%xmm13, %xmm11
	mulsd	%xmm15, %xmm12
	leal	(%rdi,%r13), %r10d
	movslq	%r10d, %r10
	movsd	(%rsi,%r10,8), %xmm13           # xmm13 = mem[0],zero
	mulsd	%xmm0, %xmm10
	addsd	%xmm13, %xmm1
	movapd	%xmm9, %xmm0
	movq	216(%rsp), %rcx                 # 8-byte Reload
	leal	(%rcx,%r13), %ebp
	addsd	%xmm5, %xmm0
	movslq	%ebp, %r14
	leal	1(%rdi,%r13), %ebp
	movslq	%ebp, %r15
	mulsd	%xmm6, %xmm1
	movsd	(%r9,%r14,8), %xmm14            # xmm14 = mem[0],zero
	addsd	(%r9,%r15,8), %xmm14
	movq	-80(%rsp), %r15                 # 8-byte Reload
	movq	360(%rsp), %rcx                 # 8-byte Reload
	mulsd	%xmm8, %xmm0
	subsd	%xmm1, %xmm0
	movq	176(%rsp), %r14                 # 8-byte Reload
	leal	(%r14,%r13), %ebp
	movslq	%ebp, %r14
	movq	-96(%rsp), %rbp                 # 8-byte Reload
	mulsd	%xmm6, %xmm14
	movsd	(%r9,%r14,8), %xmm1             # xmm1 = mem[0],zero
	movq	352(%rsp), %r14                 # 8-byte Reload
	addsd	(%r9,%r10,8), %xmm1
	mulsd	%xmm8, %xmm1
	subsd	%xmm14, %xmm1
	movsd	-120(%rsp), %xmm2               # 8-byte Reload
                                        # xmm2 = mem[0],zero
	mulsd	%xmm2, %xmm2
	leal	(%r15,%r13), %r10d
	mulsd	%xmm3, %xmm4
	movslq	%r10d, %r10
	movsd	(%r9,%r10,8), %xmm14            # xmm14 = mem[0],zero
	leal	1(%rbx,%r13), %r10d
	movsd	384(%rsp), %xmm7                # 8-byte Reload
                                        # xmm7 = mem[0],zero
	mulsd	%xmm7, %xmm7
	movslq	%r10d, %r10
	addsd	(%r9,%r10,8), %xmm14
	mulsd	%xmm11, %xmm0
	movapd	%xmm9, %xmm3
	leal	(%rbp,%r13), %r10d
	movslq	%r10d, %r10
	subsd	%xmm2, %xmm7
	movsd	(%r9,%r10,8), %xmm11            # xmm11 = mem[0],zero
	leal	(%rcx,%r13), %r10d
	movslq	%r10d, %r10
	movsd	-40(%rsp), %xmm15               # 8-byte Reload
                                        # xmm15 = mem[0],zero
	mulsd	%xmm15, %xmm15
	addsd	(%rsi,%r10,8), %xmm9
	leal	(%rbx,%r13), %r10d
	movsd	392(%rsp), %xmm2                # 8-byte Reload
                                        # xmm2 = mem[0],zero
	mulsd	%xmm2, %xmm2
	movslq	%r10d, %r10
	addsd	(%r9,%r10,8), %xmm11
	subsd	%xmm2, %xmm15
	movsd	(%rsi,%r10,8), %xmm2            # xmm2 = mem[0],zero
	movq	344(%rsp), %r10                 # 8-byte Reload
	addsd	%xmm2, %xmm5
	mulsd	%xmm6, %xmm5
	subsd	376(%rsp), %xmm12               # 8-byte Folded Reload
	addsd	%xmm13, %xmm3
	mulsd	%xmm8, %xmm3
	subsd	%xmm5, %xmm3
	movapd	%xmm6, %xmm5
	movsd	-128(%rsp), %xmm6               # 8-byte Reload
                                        # xmm6 = mem[0],zero
	subsd	%xmm10, %xmm6
	mulsd	%xmm1, %xmm3
	movsd	.LCPI0_3(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm5, %xmm14
	mulsd	%xmm8, %xmm11
	subsd	%xmm0, %xmm3
	movsd	.LCPI0_2(%rip), %xmm0           # xmm0 = mem[0],zero
	subsd	%xmm14, %xmm11
	addsd	%xmm2, %xmm13
	mulsd	%xmm0, %xmm15
	movapd	%xmm7, %xmm2
	mulsd	%xmm1, %xmm2
	mulsd	%xmm0, %xmm6
	movapd	%xmm6, %xmm7
	mulsd	%xmm1, %xmm12
	mulsd	%xmm5, %xmm9
	addsd	%xmm15, %xmm2
	movapd	%xmm8, %xmm14
	mulsd	%xmm8, %xmm13
	subsd	%xmm9, %xmm13
	mulsd	%xmm11, %xmm13
	addsd	%xmm6, %xmm12
	subsd	%xmm13, %xmm4
	mulsd	%xmm0, %xmm4
	mulsd	%xmm1, %xmm3
	addsd	%xmm2, %xmm12
	addsd	%xmm4, %xmm3
	addsd	%xmm12, %xmm3
	addsd	(%r14,%r11,8), %xmm3
	movsd	%xmm3, (%r14,%r11,8)
	movq	-88(%rsp), %r14                 # 8-byte Reload
	incq	%r13
	cmpq	%r13, %r10
	jne	.LBB0_5
.LBB0_6:                                # %._crit_edge
                                        #   in Loop: Header=BB0_3 Depth=2
	movl	-100(%rsp), %r11d               # 4-byte Reload
	incl	%r11d
	movq	336(%rsp), %r10                 # 8-byte Reload
	addq	%r10, 136(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 144(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 152(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 160(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 168(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 176(%rsp)                 # 8-byte Folded Spill
	addq	%r10, %rbp
	movq	%rbp, -96(%rsp)                 # 8-byte Spill
	addq	%r10, %r14
	movq	%r14, -88(%rsp)                 # 8-byte Spill
	addq	%r10, 184(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 192(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 200(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 208(%rsp)                 # 8-byte Folded Spill
	addq	%r10, 216(%rsp)                 # 8-byte Folded Spill
	addq	%r10, %r15
	movq	%r15, -80(%rsp)                 # 8-byte Spill
	addq	%r10, %r8
	movq	%r8, 120(%rsp)                  # 8-byte Spill
	addq	%r10, %rbx
	movq	%rbx, 128(%rsp)                 # 8-byte Spill
	addq	%r10, %rdi
	movq	%rdi, 112(%rsp)                 # 8-byte Spill
	addq	%r10, %rax
	movq	%rax, %rdi
	addq	%r10, %r12
	movq	%r12, %rax
	movq	224(%rsp), %r12                 # 8-byte Reload
	addq	%r10, %r12
	movq	232(%rsp), %r8                  # 8-byte Reload
	addq	%r10, %r8
	movq	240(%rsp), %rbp                 # 8-byte Reload
	addq	%r10, %rbp
	movq	256(%rsp), %rbx                 # 8-byte Reload
	addq	%r10, %rbx
	movq	264(%rsp), %r15                 # 8-byte Reload
	addq	%r10, %r15
	movq	248(%rsp), %r13                 # 8-byte Reload
	addq	%r10, %r13
	movq	272(%rsp), %r14                 # 8-byte Reload
	addq	%r10, %r14
	addq	%r10, %rcx
	movl	%r11d, -100(%rsp)               # 4-byte Spill
	cmpl	464(%rsp), %r11d
	movq	%r14, %r11
	movq	%rbx, %r14
	jne	.LBB0_3
.LBB0_7:                                # %._crit_edge269
                                        #   in Loop: Header=BB0_2 Depth=1
	movq	328(%rsp), %rbx                 # 8-byte Reload
	incl	%ebx
	movq	280(%rsp), %r11                 # 8-byte Reload
	addq	%r11, 40(%rsp)                  # 8-byte Folded Spill
	movq	104(%rsp), %r13                 # 8-byte Reload
	addq	%r11, %r13
	addq	%r11, 80(%rsp)                  # 8-byte Folded Spill
	addq	%r11, 64(%rsp)                  # 8-byte Folded Spill
	addq	%r11, 16(%rsp)                  # 8-byte Folded Spill
	addq	%r11, (%rsp)                    # 8-byte Folded Spill
	addq	%r11, -24(%rsp)                 # 8-byte Folded Spill
	addq	%r11, 32(%rsp)                  # 8-byte Folded Spill
	addq	%r11, 88(%rsp)                  # 8-byte Folded Spill
	addq	%r11, 72(%rsp)                  # 8-byte Folded Spill
	addq	%r11, 56(%rsp)                  # 8-byte Folded Spill
	movq	288(%rsp), %rbp                 # 8-byte Reload
	addq	%r11, %rbp
	addq	%r11, -8(%rsp)                  # 8-byte Folded Spill
	addq	%r11, -32(%rsp)                 # 8-byte Folded Spill
	addq	%r11, 48(%rsp)                  # 8-byte Folded Spill
	addq	%r11, -16(%rsp)                 # 8-byte Folded Spill
	addq	%r11, 8(%rsp)                   # 8-byte Folded Spill
	addq	%r11, 24(%rsp)                  # 8-byte Folded Spill
	movq	296(%rsp), %rdi                 # 8-byte Reload
	addq	%r11, %rdi
	movq	-72(%rsp), %r12                 # 8-byte Reload
	addq	%r11, %r12
	movq	-64(%rsp), %r10                 # 8-byte Reload
	addq	%r11, %r10
	addq	%r11, 96(%rsp)                  # 8-byte Folded Spill
	movq	312(%rsp), %r14                 # 8-byte Reload
	addq	%r11, %r14
	movq	304(%rsp), %r15                 # 8-byte Reload
	addq	%r11, %r15
	movq	320(%rsp), %rax                 # 8-byte Reload
	addq	%r11, %rax
	movq	-48(%rsp), %r8                  # 8-byte Reload
	addq	%r11, %r8
	movq	-56(%rsp), %rcx                 # 8-byte Reload
	addq	%r11, %rcx
	cmpl	480(%rsp), %ebx
	jne	.LBB0_2
.LBB0_8:                                # %._crit_edge271
	addq	$400, %rsp                      # imm = 0x190
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z9advec_cpuPdPKdS1_S1_iiiiiiii, .Lfunc_end0-_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii # -- Begin function _Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii
	.type	_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii,@function
_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii: # @_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9advec_gpuPdPKdS1_S1_iiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii, .Lfunc_end1-_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii # -- Begin function _Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.type	_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii,@function
_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii: # @_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii, .Lfunc_end2-_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z7maxdiffPKdS0_i
.LCPI3_0:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.text
	.globl	_Z7maxdiffPKdS0_i
	.type	_Z7maxdiffPKdS0_i,@function
_Z7maxdiffPKdS0_i:                      # @_Z7maxdiffPKdS0_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB3_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorpd	%xmm2, %xmm2
	xorl	%ecx, %ecx
	movapd	.LCPI3_0(%rip), %xmm1           # xmm1 = [NaN,NaN]
.LBB3_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movsd	(%rdi,%rcx,8), %xmm0            # xmm0 = mem[0],zero
	subsd	(%rsi,%rcx,8), %xmm0
	andpd	%xmm1, %xmm0
	maxsd	%xmm2, %xmm0
	incq	%rcx
	movapd	%xmm0, %xmm2
	cmpq	%rcx, %rax
	jne	.LBB3_4
# %bb.2:                                # %._crit_edge
	retq
.LBB3_1:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end3:
	.size	_Z7maxdiffPKdS0_i, .Lfunc_end3-_Z7maxdiffPKdS0_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI4_1:
	.quad	0xbfe0000000000000              # double -0.5
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI4_2:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$143877824, %edi                # imm = 0x89366C0
	callq	_Znam
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	$143877824, %edi                # imm = 0x89366C0
	callq	_Znam
	movq	%rax, %r12
	movl	$143877824, %edi                # imm = 0x89366C0
	callq	_Znam
	movq	%rax, %r13
	movl	$143877824, %edi                # imm = 0x89366C0
	callq	_Znam
	movq	%rax, %rbx
	movl	$143877824, %edi                # imm = 0x89366C0
	callq	_Znam
	movq	%rax, %r15
	xorl	%ebp, %ebp
	xorl	%r14d, %r14d
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$1000, %ecx, %ecx               # imm = 0x3E8
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	movsd	.LCPI4_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	movsd	.LCPI4_1(%rip), %xmm1           # xmm1 = mem[0],zero
	addsd	%xmm1, %xmm0
	movq	16(%rsp), %rax                  # 8-byte Reload
	movsd	%xmm0, (%rax,%r14,8)
	callq	rand
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$1000, %ecx, %ecx               # imm = 0x3E8
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	.LCPI4_0(%rip), %xmm0
	addsd	.LCPI4_1(%rip), %xmm0
	movsd	%xmm0, (%r12,%r14,8)
	callq	rand
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$1000, %ecx, %ecx               # imm = 0x3E8
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	.LCPI4_0(%rip), %xmm0
	addsd	.LCPI4_1(%rip), %xmm0
	movsd	%xmm0, (%r13,%r14,8)
	movq	%rbp, (%rbx,%r14,8)
	movq	%rbp, (%r15,%r14,8)
	incq	%r14
	cmpq	$17984728, %r14                 # imm = 0x1126CD8
	jne	.LBB4_1
# %bb.2:
	movq	%r15, 64(%rsp)                  # 8-byte Spill
	leaq	72(%rsp), %rbp
	movl	$149369448, %esi                # imm = 0x8E73268
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$149369448, %esi                # imm = 0x8E73268
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$149369448, %esi                # imm = 0x8E73268
	callq	hipMalloc
	leaq	40(%rsp), %r15
	movl	$149369448, %esi                # imm = 0x8E73268
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%rbp), %rdi
	addq	$104, %rdi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$1, %r14d
	movl	$2176, %esi                     # imm = 0x880
	movl	$2096, %ecx                     # imm = 0x830
	movl	$2096, %r8d                     # imm = 0x830
	movl	$68644, %r9d                    # imm = 0x10C24
	movq	24(%rsp), %rdx                  # 8-byte Reload
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	hipMemcpy2D
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	leaq	56(%rsp), %rax
	movq	(%rax), %rdi
	addq	$104, %rdi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$2176, %esi                     # imm = 0x880
	movl	$2096, %ecx                     # imm = 0x830
	movl	$2096, %r8d                     # imm = 0x830
	movl	$68644, %r9d                    # imm = 0x10C24
	movq	%r12, %rdx
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	hipMemcpy2D
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	addq	$104, %rdi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$2176, %esi                     # imm = 0x880
	movl	$2096, %ecx                     # imm = 0x830
	movl	$2096, %r8d                     # imm = 0x830
	movl	$68644, %r9d                    # imm = 0x10C24
	movq	%r13, %rdx
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	hipMemcpy2D
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	(%r15), %rdi
	addq	$104, %rdi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$2176, %esi                     # imm = 0x880
	movl	$2096, %ecx                     # imm = 0x830
	movl	$2096, %r8d                     # imm = 0x830
	movl	$68644, %r9d                    # imm = 0x10C24
	movq	%rbx, %rdx
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	hipMemcpy2D
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$10, %ebp
	movl	$259, %r14d                     # imm = 0x103
	movq	%rbx, %r15
	movl	$3, %ebx
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movq	%r13, %rcx
	movl	$3, %r8d
	movl	$259, %r9d                      # imm = 0x103
	pushq	$68644                          # imm = 0x10C24
	.cfi_adjust_cfa_offset 8
	pushq	$262                            # imm = 0x106
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z9advec_cpuPdPKdS1_S1_iiiiiiii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
	decl	%ebp
	jne	.LBB4_3
# %bb.4:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movl	$2, %edi
	callq	hipDeviceSetSharedMemConfig
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$10, %ebp
	movabsq	$137438953480, %rbx             # imm = 0x2000000008
	movabsq	$34359738400, %r12              # imm = 0x800000020
	movl	$3, %r14d
	movl	$259, %r13d                     # imm = 0x103
.LBB4_5:                                # =>This Inner Loop Header: Depth=1
	movl	$8512, %r8d                     # imm = 0x2140
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_7
# %bb.6:                                #   in Loop: Header=BB4_5 Depth=1
	movq	40(%rsp), %rdi
	addq	$104, %rdi
	movq	72(%rsp), %rsi
	addq	$104, %rsi
	movq	56(%rsp), %rdx
	addq	$104, %rdx
	movq	48(%rsp), %rcx
	addq	$104, %rcx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$3, %r8d
	movl	$259, %r9d                      # imm = 0x103
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	$71264                          # imm = 0x11660
	.cfi_adjust_cfa_offset 8
	pushq	$272                            # imm = 0x110
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB4_7:                                #   in Loop: Header=BB4_5 Depth=1
	decl	%ebp
	jne	.LBB4_5
# %bb.8:
	movq	8(%rsp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	84(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	40(%rsp), %rdx
	addq	$104, %rdx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$2096, %esi                     # imm = 0x830
	movl	$2176, %ecx                     # imm = 0x880
	movl	$2096, %r8d                     # imm = 0x830
	movl	$68644, %r9d                    # imm = 0x10C24
	movq	72(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	pushq	$2
	.cfi_adjust_cfa_offset 8
	callq	hipMemcpy2D
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	36(%rsp), %xmm1                 # xmm1 = mem[0],zero,zero,zero
	xorpd	%xmm2, %xmm2
	movapd	.LCPI4_2(%rip), %xmm3           # xmm3 = [NaN,NaN]
.LBB4_9:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movapd	%xmm2, %xmm4
	movsd	(%r15,%r14,8), %xmm2            # xmm2 = mem[0],zero
	subsd	(%r12,%r14,8), %xmm2
	andpd	%xmm3, %xmm2
	maxsd	%xmm4, %xmm2
	incq	%r14
	cmpq	$17984728, %r14                 # imm = 0x1126CD8
	jne	.LBB4_9
# %bb.10:                               # %_Z7maxdiffPKdS0_i.exit
	divss	%xmm0, %xmm1
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.1, %edi
	movb	$3, %al
	callq	printf
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9advec_gpuPdPKdS1_S1_iiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9advec_gpuPdPKdS1_S1_iiiiiiii,@object # @_Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.p2align	3, 0x0
_Z9advec_gpuPdPKdS1_S1_iiiiiiii:
	.quad	_Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii
	.size	_Z9advec_gpuPdPKdS1_S1_iiiiiiii, 8

	.type	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii,@object # @_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.globl	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.p2align	3, 0x0
_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii:
	.quad	_Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.size	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CPU; elapsed=%f [ms]\n"
	.size	.L.str, 22

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n"
	.size	.L.str.1, 47

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9advec_gpuPdPKdS1_S1_iiiiiiii"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii"
	.size	.L__unnamed_2, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__advec_gpuPdPKdS1_S1_iiiiiiii
	.addrsig_sym _Z29__device_stub__advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.addrsig_sym _Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9advec_gpuPdPKdS1_S1_iiiiiiii ; -- Begin function _Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.globl	_Z9advec_gpuPdPKdS1_S1_iiiiiiii
	.p2align	8
	.type	_Z9advec_gpuPdPKdS1_S1_iiiiiiii,@function
_Z9advec_gpuPdPKdS1_S1_iiiiiiii:        ; @_Z9advec_gpuPdPKdS1_S1_iiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b256 s[4:11], s[0:1], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s13, s13, s3
	s_mul_i32 s14, s14, s2
	v_add3_u32 v0, s13, s4, v1
	v_add3_u32 v1, s14, s6, v2
	s_add_i32 s8, s15, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_cmp_lt_i32 s8, s9
	s_cselect_b32 s3, -1, 0
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mul_lo_u32 v1, v1, s10
	s_load_b256 s[0:7], s[0:1], 0x0
	s_mul_i32 s8, s8, s11
	s_ashr_i32 s9, s10, 31
	s_lshl_b32 s16, s10, 1
	s_mul_i32 s17, s10, 3
	s_lshl_b32 s18, s11, 1
	s_mul_i32 s19, s11, 3
	v_add3_u32 v2, v0, s8, v1
	s_mov_b32 s8, s10
	s_ashr_i32 s15, s11, 31
	s_lshl_b64 s[12:13], s[8:9], 3
	s_mov_b32 s14, s11
	v_ashrrev_i32_e32 v3, 31, v2
	v_add3_u32 v36, s10, s10, v2
	v_subrev_nc_u32_e32 v48, s10, v2
	v_subrev_nc_u32_e32 v50, s17, v2
	v_subrev_nc_u32_e32 v52, s16, v2
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_add_nc_u32_e32 v38, s10, v36
	v_ashrrev_i32_e32 v37, 31, v36
	v_subrev_nc_u32_e32 v58, s11, v2
	v_subrev_nc_u32_e32 v59, s19, v2
	v_subrev_nc_u32_e32 v61, s18, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v20, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v56, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v57, vcc_lo, s7, v1, vcc_lo
	s_clause 0x1
	global_load_b128 v[4:7], v[20:21], off
	global_load_b128 v[8:11], v[20:21], off offset:-16
	v_sub_co_u32 v22, vcc_lo, v2, s10
	s_clause 0x1
	global_load_b128 v[12:15], v[56:57], off
	global_load_b128 v[16:19], v[56:57], off offset:-16
	v_subrev_co_ci_u32_e32 v23, vcc_lo, s9, v3, vcc_lo
	v_ashrrev_i32_e32 v39, 31, v38
	v_add3_u32 v54, s11, s11, v2
	v_lshlrev_b64 v[63:64], 3, v[36:37]
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_ashrrev_i32_e32 v51, 31, v50
	v_lshlrev_b64 v[67:68], 3, v[38:39]
	v_ashrrev_i32_e32 v53, 31, v52
	v_ashrrev_i32_e32 v55, 31, v54
	v_add_nc_u32_e32 v71, s11, v54
	v_add_co_u32 v24, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v23, vcc_lo
	v_add_co_u32 v32, vcc_lo, v20, s12
	v_add_co_ci_u32_e32 v33, vcc_lo, s13, v21, vcc_lo
	s_clause 0x3
	global_load_b128 v[20:23], v[24:25], off
	global_load_b128 v[24:27], v[24:25], off offset:-16
	global_load_b128 v[28:31], v[32:33], off
	global_load_b128 v[32:35], v[32:33], off offset:-16
	v_sub_co_u32 v2, vcc_lo, v2, s11
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	v_add_co_u32 v65, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v66, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v44, vcc_lo, s4, v63
	v_add_co_ci_u32_e32 v45, vcc_lo, s5, v64, vcc_lo
	v_add_co_u32 v67, vcc_lo, s2, v67
	v_add_co_ci_u32_e32 v68, vcc_lo, s3, v68, vcc_lo
	s_clause 0x1
	global_load_b64 v[69:70], v[65:66], off offset:24
	global_load_b128 v[36:39], v[65:66], off offset:-8
	s_clause 0x1
	global_load_b128 v[40:43], v[44:45], off
	global_load_b128 v[44:47], v[44:45], off offset:-16
	v_lshlrev_b64 v[73:74], 3, v[50:51]
	global_load_b64 v[67:68], v[67:68], off
	v_lshlrev_b64 v[75:76], 3, v[52:53]
	v_lshlrev_b64 v[81:82], 3, v[54:55]
	v_ashrrev_i32_e32 v72, 31, v71
	v_ashrrev_i32_e32 v49, 31, v48
	v_add_co_u32 v73, vcc_lo, s2, v73
	v_add_co_ci_u32_e32 v74, vcc_lo, s3, v74, vcc_lo
	v_add_co_u32 v75, vcc_lo, s2, v75
	v_add_co_ci_u32_e32 v76, vcc_lo, s3, v76, vcc_lo
	v_add_co_u32 v83, vcc_lo, v65, s12
	v_add_co_ci_u32_e32 v84, vcc_lo, s13, v66, vcc_lo
	v_lshlrev_b64 v[71:72], 3, v[71:72]
	v_add_co_u32 v85, vcc_lo, s6, v81
	v_add_co_ci_u32_e32 v86, vcc_lo, s7, v82, vcc_lo
	v_add_co_u32 v63, vcc_lo, s2, v63
	v_add_co_ci_u32_e32 v64, vcc_lo, s3, v64, vcc_lo
	v_lshlrev_b64 v[77:78], 3, v[48:49]
	v_lshlrev_b64 v[79:80], 3, v[2:3]
	s_clause 0x1
	global_load_b128 v[48:51], v[65:66], off offset:8
	global_load_b128 v[52:55], v[65:66], off offset:-24
	v_ashrrev_i32_e32 v60, 31, v59
	v_ashrrev_i32_e32 v62, 31, v61
	s_lshl_b64 s[8:9], s[14:15], 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[59:60], 3, v[59:60]
	v_lshlrev_b64 v[61:62], 3, v[61:62]
	s_waitcnt vmcnt(13)
	v_add_f64 v[89:90], v[10:11], v[4:5]
	v_add_co_u32 v10, vcc_lo, s2, v71
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v72, vcc_lo
	v_add_f64 v[87:88], v[8:9], v[6:7]
	s_clause 0x1
	global_load_b128 v[2:5], v[85:86], off
	global_load_b128 v[6:9], v[85:86], off offset:-16
	s_clause 0x4
	global_load_b64 v[73:74], v[73:74], off
	global_load_b64 v[75:76], v[75:76], off
	global_load_b64 v[71:72], v[83:84], off
	global_load_b64 v[63:64], v[63:64], off
	global_load_b64 v[83:84], v[10:11], off
	v_add_co_u32 v10, vcc_lo, s2, v77
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v78, vcc_lo
	v_add_co_u32 v77, vcc_lo, s6, v79
	v_add_co_ci_u32_e32 v78, vcc_lo, s7, v80, vcc_lo
	v_add_co_u32 v59, vcc_lo, s2, v59
	v_add_co_ci_u32_e32 v60, vcc_lo, s3, v60, vcc_lo
	v_add_co_u32 v61, vcc_lo, s2, v61
	v_add_co_ci_u32_e32 v62, vcc_lo, s3, v62, vcc_lo
	v_add_co_u32 v65, vcc_lo, v65, s8
	v_add_co_ci_u32_e32 v66, vcc_lo, s9, v66, vcc_lo
	s_waitcnt vmcnt(18)
	v_add_f64 v[91:92], v[18:19], v[12:13]
	v_add_co_u32 v18, vcc_lo, s2, v81
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v82, vcc_lo
	global_load_b64 v[79:80], v[10:11], off
	v_add_f64 v[85:86], v[16:17], v[14:15]
	s_clause 0x1
	global_load_b128 v[10:13], v[77:78], off
	global_load_b128 v[14:17], v[77:78], off offset:-16
	s_clause 0x3
	global_load_b64 v[77:78], v[59:60], off
	global_load_b64 v[60:61], v[61:62], off
	global_load_b64 v[65:66], v[65:66], off
	global_load_b64 v[81:82], v[18:19], off
	v_ashrrev_i32_e32 v59, 31, v58
	s_waitcnt vmcnt(23)
	v_add_f64 v[93:94], v[24:25], v[22:23]
	v_add_f64 v[26:27], v[26:27], v[20:21]
	s_waitcnt vmcnt(21)
	v_add_f64 v[30:31], v[32:33], v[30:31]
	v_add_f64 v[28:29], v[34:35], v[28:29]
	v_lshlrev_b64 v[18:19], 3, v[58:59]
	s_waitcnt vmcnt(19)
	v_add_f64 v[32:33], v[38:39], v[69:70]
	s_waitcnt vmcnt(17)
	v_add_f64 v[34:35], v[44:45], v[42:43]
	s_waitcnt vmcnt(16)
	v_add_f64 v[42:43], v[38:39], v[67:68]
	v_add_f64 v[40:41], v[46:47], v[40:41]
	v_add_co_u32 v18, vcc_lo, s2, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	v_add_co_u32 v56, vcc_lo, v56, s8
	v_add_co_ci_u32_e32 v57, vcc_lo, s9, v57, vcc_lo
	global_load_b64 v[58:59], v[18:19], off
	s_clause 0x1
	global_load_b128 v[18:21], v[56:57], off
	global_load_b128 v[22:25], v[56:57], off offset:-16
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s1, 0x3fa55555
	global_load_b64 v[44:45], v[0:1], off
	s_waitcnt vmcnt(19)
	v_add_f64 v[46:47], v[48:49], v[50:51]
	s_waitcnt vmcnt(18)
	v_add_f64 v[52:53], v[52:53], v[38:39]
	v_add_f64 v[50:51], v[36:37], v[50:51]
	v_ldexp_f64 v[30:31], v[30:31], -4
	v_ldexp_f64 v[32:33], v[32:33], -4
	v_ldexp_f64 v[34:35], v[34:35], -4
	v_ldexp_f64 v[42:43], v[42:43], -4
	v_ldexp_f64 v[50:51], v[50:51], -4
	v_fma_f64 v[28:29], 0x3fe20000, v[28:29], -v[30:31]
	v_fma_f64 v[32:33], 0x3fe20000, v[46:47], -v[32:33]
	v_fma_f64 v[34:35], 0x3fe20000, v[40:41], -v[34:35]
	v_ldexp_f64 v[46:47], v[52:53], -4
	v_ldexp_f64 v[52:53], v[87:88], -4
	s_waitcnt vmcnt(16)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_f64 v[2:3], v[8:9], v[2:3]
	v_add_f64 v[6:7], v[54:55], v[48:49]
	s_waitcnt vmcnt(15)
	v_add_f64 v[8:9], v[38:39], v[73:74]
	s_waitcnt vmcnt(13)
	v_add_f64 v[56:57], v[75:76], v[71:72]
	s_waitcnt vmcnt(12)
	v_add_f64 v[67:68], v[71:72], v[63:64]
	s_waitcnt vmcnt(11)
	v_add_f64 v[69:70], v[38:39], v[83:84]
	v_add_f64 v[54:55], v[54:55], v[36:37]
	v_add_f64 v[36:37], v[36:37], v[38:39]
	v_add_f64 v[48:49], v[38:39], v[48:49]
	v_add_f64 v[71:72], v[38:39], v[71:72]
	s_waitcnt vmcnt(8)
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_add_f64 v[73:74], v[75:76], v[79:80]
	v_add_f64 v[62:63], v[79:80], v[63:64]
	v_add_f64 v[75:76], v[38:39], v[79:80]
	s_waitcnt vmcnt(7)
	v_add_f64 v[14:15], v[38:39], v[77:78]
	s_waitcnt vmcnt(5)
	v_add_f64 v[40:41], v[60:61], v[65:66]
	v_ldexp_f64 v[77:78], v[93:94], -4
	v_add_f64 v[10:11], v[16:17], v[10:11]
	v_ldexp_f64 v[4:5], v[4:5], -4
	v_ldexp_f64 v[6:7], v[6:7], -4
	v_ldexp_f64 v[8:9], v[8:9], -4
	v_ldexp_f64 v[56:57], v[56:57], -4
	v_fma_f64 v[42:43], 0x3fe20000, v[67:68], -v[42:43]
	s_waitcnt vmcnt(4)
	v_add_f64 v[67:68], v[65:66], v[81:82]
	v_ldexp_f64 v[69:70], v[69:70], -4
	v_fma_f64 v[46:47], 0x3fe20000, v[54:55], -v[46:47]
	s_waitcnt vmcnt(3)
	v_add_f64 v[16:17], v[60:61], v[58:59]
	v_add_f64 v[60:61], v[38:39], v[58:59]
	s_waitcnt vmcnt(1)
	v_add_f64 v[20:21], v[22:23], v[20:21]
	v_add_f64 v[22:23], v[58:59], v[81:82]
	v_ldexp_f64 v[58:59], v[85:86], -4
	v_add_f64 v[18:19], v[24:25], v[18:19]
	v_add_f64 v[24:25], v[38:39], v[65:66]
	v_fma_f64 v[38:39], 0x3fe20000, v[48:49], -v[50:51]
	v_ldexp_f64 v[12:13], v[12:13], -4
	v_ldexp_f64 v[62:63], v[62:63], -4
	v_ldexp_f64 v[14:15], v[14:15], -4
	v_ldexp_f64 v[40:41], v[40:41], -4
	v_fma_f64 v[26:27], 0x3fe20000, v[26:27], -v[77:78]
	v_fma_f64 v[2:3], 0x3fe20000, v[2:3], -v[4:5]
	v_mul_f64 v[4:5], v[32:33], v[32:33]
	v_fma_f64 v[6:7], 0x3fe20000, v[36:37], -v[6:7]
	v_fma_f64 v[36:37], 0x3fe20000, v[89:90], -v[52:53]
	v_fma_f64 v[8:9], 0x3fe20000, v[73:74], -v[8:9]
	v_fma_f64 v[52:53], 0x3fe20000, v[75:76], -v[56:57]
	v_mul_f64 v[32:33], v[34:35], v[42:43]
	v_fma_f64 v[34:35], 0x3fe20000, v[67:68], -v[69:70]
	v_ldexp_f64 v[20:21], v[20:21], -4
	v_ldexp_f64 v[22:23], v[22:23], -4
	v_fma_f64 v[42:43], 0x3fe20000, v[91:92], -v[58:59]
	v_fma_f64 v[10:11], 0x3fe20000, v[10:11], -v[12:13]
	v_fma_f64 v[30:31], 0x3fe20000, v[71:72], -v[62:63]
	v_fma_f64 v[12:13], 0x3fe20000, v[16:17], -v[14:15]
	v_fma_f64 v[14:15], 0x3fe20000, v[60:61], -v[40:41]
	v_fma_f64 v[4:5], v[46:47], v[46:47], -v[4:5]
	v_mul_f64 v[6:7], v[6:7], v[6:7]
	v_mul_f64 v[16:17], v[36:37], v[52:53]
	v_fma_f64 v[8:9], v[26:27], v[8:9], -v[32:33]
	v_mul_f64 v[2:3], v[2:3], v[34:35]
	v_fma_f64 v[18:19], 0x3fe20000, v[18:19], -v[20:21]
	v_fma_f64 v[20:21], 0x3fe20000, v[24:25], -v[22:23]
	v_mul_f64 v[14:15], v[42:43], v[14:15]
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	v_fma_f64 v[6:7], v[38:39], v[38:39], -v[6:7]
	v_fma_f64 v[16:17], v[28:29], v[30:31], -v[16:17]
	v_mul_f64 v[8:9], v[8:9], s[0:1]
	v_fma_f64 v[2:3], v[10:11], v[12:13], -v[2:3]
	v_fma_f64 v[10:11], v[18:19], v[20:21], -v[14:15]
	v_fma_f64 v[4:5], 0x3ff20000, v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[6:7], 0x3ff20000, v[16:17], v[8:9]
	v_mul_f64 v[2:3], v[2:3], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_fma_f64 v[2:3], 0x3ff20000, v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[44:45], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9advec_gpuPdPKdS1_S1_iiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 95
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9advec_gpuPdPKdS1_S1_iiiiiiii, .Lfunc_end0-_Z9advec_gpuPdPKdS1_S1_iiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2032
; NumSgprs: 22
; NumVgprs: 95
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 95
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii ; -- Begin function _Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.globl	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
	.p2align	8
	.type	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii,@function
_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii: ; @_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x54
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v0, s4, v2
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s21, s2, 16
	s_mul_i32 s26, s14, s3
	s_mul_i32 s15, s15, s21
	v_add_nc_u32_e32 v4, s26, v0
	v_add3_u32 v1, s15, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v4
	v_cmp_gt_i32_e64 s2, s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB1_18
; %bb.1:
	s_load_b32 s22, s[0:1], 0x40
	s_cmp_ge_i32 s8, s9
	s_cbranch_scc1 .LBB1_18
; %bb.2:                                ; %.lr.ph
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, s22, v2
	v_add_nc_u32_e32 v7, s22, v3
	s_lshl_b32 s2, s22, 1
	s_load_b256 s[12:19], s[0:1], 0x0
	s_add_i32 s5, s2, s3
	s_add_i32 s2, s2, s21
	v_mad_u64_u32 v[5:6], null, s5, v7, v[4:5]
	s_mul_i32 s2, s2, s5
	s_mul_i32 s1, s5, 3
	s_lshl_b32 s0, s2, 3
	v_cmp_gt_i32_e32 vcc_lo, s22, v3
	s_add_i32 s6, s0, 0
	s_lshl_b32 s0, s5, 4
	s_delay_alu instid0(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s1, v5
	s_add_i32 s7, s6, s0
	s_sub_i32 s0, s21, s22
	v_lshlrev_b32_e32 v7, 3, v5
	v_cmp_le_u32_e64 s0, s0, v3
	v_add_nc_u32_e32 v3, s1, v5
	v_lshlrev_b32_e32 v6, 3, v6
	s_add_i32 s2, s1, s22
	v_add_nc_u32_e32 v13, 0, v7
	v_add_nc_u32_e32 v14, s6, v7
	v_subrev_nc_u32_e32 v3, s22, v3
	v_add_nc_u32_e32 v15, 0, v6
	v_add_nc_u32_e32 v16, s6, v6
	v_subrev_nc_u32_e32 v6, s22, v5
	s_lshl_b32 s1, s1, 3
	v_lshlrev_b32_e32 v3, 3, v3
	v_subrev_nc_u32_e32 v7, s2, v5
	s_sub_i32 s2, s3, s22
	v_add_nc_u32_e32 v17, s1, v13
	v_lshlrev_b32_e32 v6, 3, v6
	v_add_nc_u32_e32 v23, 0, v3
	v_add_nc_u32_e32 v24, s6, v3
	v_subrev_nc_u32_e32 v3, s5, v5
	v_add_nc_u32_e32 v18, s1, v14
	v_cmp_gt_i32_e64 s1, s22, v2
	v_cmp_le_u32_e64 s2, s2, v2
	v_add_nc_u32_e32 v2, -2, v5
	v_lshlrev_b32_e32 v3, 3, v3
	v_mul_lo_u32 v8, v1, s10
	v_add_nc_u32_e32 v19, 0, v6
	v_add_nc_u32_e32 v20, s6, v6
	v_subrev_nc_u32_e32 v6, s5, v2
	v_add_nc_u32_e32 v34, s6, v3
	v_add_nc_u32_e32 v36, 0, v3
	v_add_nc_u32_e32 v3, -3, v1
	v_add_nc_u32_e32 v1, 3, v1
	v_lshlrev_b32_e32 v2, 3, v2
	s_lshl_b32 s23, s5, 3
	s_lshl_b32 s3, s22, 3
	s_lshl_b32 s24, s5, 1
	v_mul_lo_u32 v1, s10, v1
	s_sub_i32 s25, s7, s23
	v_add_nc_u32_e32 v25, s3, v13
	v_add_nc_u32_e32 v26, s3, v14
	v_add_nc_u32_e32 v27, s3, v15
	v_add_nc_u32_e32 v28, s3, v16
	v_add_nc_u32_e32 v29, s3, v17
	v_add_nc_u32_e32 v30, s3, v18
	s_mul_i32 s3, s11, s8
	v_mul_lo_u32 v3, s10, v3
	v_lshlrev_b32_e32 v7, 3, v7
	v_subrev_nc_u32_e32 v5, s24, v5
	v_lshl_add_u32 v33, v6, 3, s6
	v_add_nc_u32_e32 v39, s25, v2
	v_add_nc_u32_e32 v42, s7, v2
	v_add_nc_u32_e32 v2, s3, v0
	v_add3_u32 v4, s3, s4, v4
	v_add_nc_u32_e32 v6, v0, v8
	s_add_i32 s3, s8, -1
	v_lshl_add_u32 v35, v5, 3, 0
	v_add_nc_u32_e32 v5, v2, v1
	v_add_nc_u32_e32 v46, v4, v1
	v_mad_u64_u32 v[0:1], null, s11, s3, v[6:7]
	s_add_i32 s3, s8, -3
	v_add_nc_u32_e32 v44, v2, v3
	v_add_nc_u32_e32 v49, v2, v8
	v_mad_u64_u32 v[1:2], null, s11, s3, v[6:7]
	s_add_i32 s3, s8, -2
	v_add_nc_u32_e32 v47, v4, v3
	v_mad_u64_u32 v[2:3], null, s11, s3, v[6:7]
	s_add_i32 s3, s8, 2
	v_add_nc_u32_e32 v37, s23, v13
	v_add_nc_u32_e32 v40, s23, v14
	v_mad_u64_u32 v[3:4], null, s11, s3, v[6:7]
	s_add_i32 s3, s8, 3
	v_subrev_nc_u32_e32 v48, s22, v5
	v_mad_u64_u32 v[4:5], null, s11, s3, v[6:7]
	s_mul_i32 s20, s10, 3
	v_add_nc_u32_e32 v21, 0, v7
	v_add_nc_u32_e32 v22, s6, v7
	v_subrev_nc_u32_e32 v31, 24, v13
	v_add_nc_u32_e32 v32, -8, v13
	v_add_nc_u32_e32 v38, -16, v14
	v_add_nc_u32_e32 v41, s23, v37
	v_add_nc_u32_e32 v43, s23, v40
	v_subrev_nc_u32_e32 v45, s22, v44
	v_subrev_nc_u32_e32 v50, s22, v49
	s_ashr_i32 s21, s20, 31
	s_ashr_i32 s23, s22, 31
	s_ashr_i32 s5, s11, 31
	s_mov_b32 s4, s11
	s_mov_b32 s6, 0x55555555
	s_mov_b32 s7, 0x3fa55555
	s_lshl_b64 s[20:21], s[20:21], 3
	s_lshl_b64 s[22:23], s[22:23], 3
	s_lshl_b64 s[24:25], s[4:5], 3
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v9, s26, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[5:6], 3, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s3, s14, v5
	v_add_co_ci_u32_e64 v8, s3, s15, v6, s3
	v_add_co_u32 v11, s3, s16, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s3, s17, v6, s3
	global_load_b64 v[51:52], v[7:8], off
	global_load_b64 v[53:54], v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v13, v[51:52]
	s_waitcnt vmcnt(0)
	ds_store_b64 v14, v[53:54]
	s_and_saveexec_b32 s10, vcc_lo
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v51, s26, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v52, 31, v51
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, s14, v51
	v_add_co_ci_u32_e64 v54, s3, s15, v52, s3
	v_add_co_u32 v51, s3, s16, v51
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v52, s3, s17, v52, s3
	global_load_b64 v[53:54], v[53:54], off
	global_load_b64 v[51:52], v[51:52], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v15, v[53:54]
	s_waitcnt vmcnt(0)
	ds_store_b64 v16, v[51:52]
.LBB1_5:                                ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_3 Depth=1
	v_add_co_u32 v51, s3, v7, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v52, s3, s21, v8, s3
	v_add_co_u32 v53, s3, v11, s20
	v_add_co_ci_u32_e64 v54, s3, s21, v12, s3
	global_load_b64 v[51:52], v[51:52], off
	global_load_b64 v[53:54], v[53:54], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v17, v[51:52]
	s_waitcnt vmcnt(0)
	ds_store_b64 v18, v[53:54]
.LBB1_7:                                ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s1
	s_cbranch_execz .LBB1_12
; %bb.8:                                ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v51, s26, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v52, 31, v51
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, s14, v51
	v_add_co_ci_u32_e64 v54, s3, s15, v52, s3
	v_add_co_u32 v51, s3, s16, v51
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v52, s3, s17, v52, s3
	global_load_b64 v[53:54], v[53:54], off
	global_load_b64 v[51:52], v[51:52], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v19, v[53:54]
	s_waitcnt vmcnt(0)
	ds_store_b64 v20, v[51:52]
	s_and_saveexec_b32 s27, vcc_lo
	s_cbranch_execz .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v51, s26, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v52, 31, v51
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, s14, v51
	v_add_co_ci_u32_e64 v54, s3, s15, v52, s3
	v_add_co_u32 v51, s3, s16, v51
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v52, s3, s17, v52, s3
	global_load_b64 v[53:54], v[53:54], off
	global_load_b64 v[51:52], v[51:52], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v21, v[53:54]
	s_waitcnt vmcnt(0)
	ds_store_b64 v22, v[51:52]
.LBB1_10:                               ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v51, s26, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v52, 31, v51
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, s14, v51
	v_add_co_ci_u32_e64 v54, s3, s15, v52, s3
	v_add_co_u32 v51, s3, s16, v51
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v52, s3, s17, v52, s3
	global_load_b64 v[53:54], v[53:54], off
	global_load_b64 v[51:52], v[51:52], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v23, v[53:54]
	s_waitcnt vmcnt(0)
	ds_store_b64 v24, v[51:52]
.LBB1_12:                               ; %Flow503
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB1_17
; %bb.13:                               ;   in Loop: Header=BB1_3 Depth=1
	v_add_co_u32 v51, s3, v7, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v52, s3, s23, v8, s3
	v_add_co_u32 v11, s3, v11, s22
	v_add_co_ci_u32_e64 v12, s3, s23, v12, s3
	global_load_b64 v[51:52], v[51:52], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v25, v[51:52]
	s_waitcnt vmcnt(0)
	ds_store_b64 v26, v[11:12]
	s_and_saveexec_b32 s27, vcc_lo
	s_cbranch_execz .LBB1_15
; %bb.14:                               ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v11, s26, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v51, s3, s14, v11
	v_add_co_ci_u32_e64 v52, s3, s15, v12, s3
	v_add_co_u32 v11, s3, s16, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s3, s17, v12, s3
	global_load_b64 v[51:52], v[51:52], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v27, v[51:52]
	s_waitcnt vmcnt(0)
	ds_store_b64 v28, v[11:12]
.LBB1_15:                               ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_17
; %bb.16:                               ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v11, s26, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v51, s3, s14, v11
	v_add_co_ci_u32_e64 v52, s3, s15, v12, s3
	v_add_co_u32 v11, s3, s16, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s3, s17, v12, s3
	global_load_b64 v[51:52], v[51:52], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v29, v[51:52]
	s_waitcnt vmcnt(0)
	ds_store_b64 v30, v[11:12]
.LBB1_17:                               ; %Flow501
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_co_u32 v11, s3, s18, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s3, s19, v6, s3
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_clause 0x1
	global_load_b128 v[51:54], v[11:12], off
	global_load_b128 v[55:58], v[11:12], off offset:-16
	ds_load_2addr_b64 v[59:62], v33 offset1:1
	ds_load_2addr_b64 v[63:66], v34 offset1:1
	ds_load_2addr_b64 v[67:70], v38 offset1:1
	ds_load_2addr_b64 v[71:74], v42 offset1:1
	ds_load_2addr_b64 v[75:78], v43 offset1:1
	v_sub_co_u32 v9, s3, v9, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v10, s3, s5, v10, s3
	v_add_co_u32 v111, s3, v7, s24
	v_add_co_ci_u32_e64 v112, s3, s25, v8, s3
	v_add_co_u32 v113, s3, s12, v5
	ds_load_2addr_b64 v[79:82], v32 offset1:1
	ds_load_2addr_b64 v[83:86], v40 offset1:1
	ds_load_b64 v[99:100], v41
	ds_load_2addr_b64 v[87:90], v39 offset1:1
	ds_load_b64 v[101:102], v37
	ds_load_2addr_b64 v[91:94], v14 offset1:1
	ds_load_b64 v[103:104], v15
	ds_load_b64 v[105:106], v35
	ds_load_b64 v[107:108], v36
	v_add_co_ci_u32_e64 v114, s3, s13, v6, s3
	ds_load_b64 v[117:118], v17
	ds_load_2addr_b64 v[5:8], v31 offset1:1
	v_add_nc_u32_e32 v95, s26, v0
	v_add_nc_u32_e32 v97, s26, v3
	v_add_nc_u32_e32 v109, s26, v1
	v_add_nc_u32_e32 v115, s26, v4
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_waitcnt lgkmcnt(11)
	v_add_f64 v[71:72], v[71:72], v[77:78]
	v_ashrrev_i32_e32 v96, 31, v95
	v_ashrrev_i32_e32 v98, 31, v97
	v_ashrrev_i32_e32 v110, 31, v109
	v_ashrrev_i32_e32 v116, 31, v115
	v_add_f64 v[65:66], v[59:60], v[65:66]
	v_add_f64 v[73:74], v[73:74], v[75:76]
	v_add_nc_u32_e32 v77, s26, v2
	s_waitcnt lgkmcnt(5)
	v_add_f64 v[67:68], v[67:68], v[93:94]
	v_add_co_u32 v93, s3, v11, s24
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v94, s3, s25, v12, s3
	v_lshlrev_b64 v[11:12], 3, v[95:96]
	v_lshlrev_b64 v[95:96], 3, v[97:98]
	v_lshlrev_b64 v[97:98], 3, v[109:110]
	v_lshlrev_b64 v[109:110], 3, v[115:116]
	s_waitcnt lgkmcnt(1)
	v_add_f64 v[115:116], v[81:82], v[117:118]
	v_add_co_u32 v117, s3, s18, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v118, s3, s19, v10, s3
	v_add_f64 v[9:10], v[81:82], v[103:104]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[5:6], v[5:6], v[81:82]
	v_ashrrev_i32_e32 v78, 31, v77
	v_add_co_u32 v119, s3, s18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v120, s3, s19, v12, s3
	v_lshlrev_b64 v[77:78], 3, v[77:78]
	v_add_co_u32 v75, s3, s18, v95
	v_add_f64 v[63:64], v[61:62], v[63:64]
	v_add_f64 v[69:70], v[69:70], v[91:92]
	ds_load_2addr_b64 v[59:62], v13 offset0:1 offset1:2
	ds_load_b64 v[91:92], v13 offset:24
	v_add_co_ci_u32_e64 v76, s3, s19, v96, s3
	v_add_co_u32 v97, s3, s14, v97
	v_ldexp_f64 v[71:72], v[71:72], -4
	v_add_co_ci_u32_e64 v98, s3, s15, v98, s3
	v_add_co_u32 v77, s3, s14, v77
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v78, s3, s15, v78, s3
	v_add_co_u32 v103, s3, s14, v11
	v_add_co_ci_u32_e64 v104, s3, s15, v12, s3
	v_add_co_u32 v95, s3, s14, v95
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v96, s3, s15, v96, s3
	v_add_co_u32 v109, s3, s14, v109
	v_add_co_ci_u32_e64 v110, s3, s15, v110, s3
	v_ldexp_f64 v[65:66], v[65:66], -4
	v_add_f64 v[85:86], v[87:88], v[85:86]
	v_add_f64 v[83:84], v[89:90], v[83:84]
	v_add_f64 v[87:88], v[101:102], v[99:100]
	s_waitcnt lgkmcnt(1)
	v_add_f64 v[89:90], v[7:8], v[59:60]
	v_ldexp_f64 v[115:116], v[115:116], -4
	v_add_f64 v[123:124], v[7:8], v[79:80]
	v_ldexp_f64 v[129:130], v[9:10], -4
	v_ldexp_f64 v[131:132], v[5:6], -4
	v_add_f64 v[125:126], v[79:80], v[61:62]
	v_add_f64 v[127:128], v[81:82], v[59:60]
	v_add_f64 v[133:134], v[59:60], v[61:62]
	v_add_f64 v[79:80], v[79:80], v[81:82]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[91:92], v[81:82], v[91:92]
	v_add_f64 v[121:122], v[105:106], v[107:108]
	v_ldexp_f64 v[67:68], v[67:68], -4
	v_add_f64 v[105:106], v[105:106], v[101:102]
	v_add_f64 v[101:102], v[81:82], v[101:102]
	v_add_nc_u32_e32 v45, s11, v45
	v_fma_f64 v[71:72], 0x3fe20000, v[73:74], -v[71:72]
	s_clause 0x1
	global_load_b128 v[5:8], v[75:76], off
	global_load_b128 v[9:12], v[75:76], off offset:-16
	global_load_b64 v[73:74], v[109:110], off
	v_add_nc_u32_e32 v46, s11, v46
	v_add_nc_u32_e32 v47, s11, v47
	v_add_nc_u32_e32 v48, s11, v48
	v_add_nc_u32_e32 v49, s11, v49
	v_add_nc_u32_e32 v44, s11, v44
	v_add_nc_u32_e32 v50, s11, v50
	v_add_nc_u32_e32 v0, s11, v0
	v_add_nc_u32_e32 v1, s11, v1
	v_add_nc_u32_e32 v2, s11, v2
	v_add_nc_u32_e32 v3, s11, v3
	v_add_nc_u32_e32 v4, s11, v4
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s8, s9
	v_fma_f64 v[135:136], 0x3fe20000, v[63:64], -v[65:66]
	v_ldexp_f64 v[85:86], v[85:86], -4
	v_fma_f64 v[75:76], 0x3fe20000, v[87:88], -v[115:116]
	v_ldexp_f64 v[87:88], v[89:90], -4
	global_load_b64 v[89:90], v[111:112], off
	s_clause 0x1
	global_load_b128 v[59:62], v[117:118], off offset:-16
	global_load_b128 v[63:66], v[119:120], off
	s_clause 0x2
	global_load_b64 v[95:96], v[95:96], off
	global_load_b64 v[97:98], v[97:98], off
	global_load_b64 v[77:78], v[77:78], off
	v_fma_f64 v[111:112], 0x3fe20000, v[123:124], -v[131:132]
	v_ldexp_f64 v[91:92], v[91:92], -4
	v_fma_f64 v[109:110], 0x3fe20000, v[121:122], -v[129:130]
	v_fma_f64 v[67:68], 0x3fe20000, v[69:70], -v[67:68]
	v_add_f64 v[69:70], v[107:108], v[99:100]
	v_ldexp_f64 v[99:100], v[105:106], -4
	v_ldexp_f64 v[105:106], v[125:126], -4
	v_fma_f64 v[83:84], 0x3fe20000, v[83:84], -v[85:86]
	v_mul_f64 v[71:72], v[71:72], v[75:76]
	v_fma_f64 v[79:80], 0x3fe20000, v[79:80], -v[87:88]
	v_fma_f64 v[91:92], 0x3fe20000, v[133:134], -v[91:92]
	v_ldexp_f64 v[69:70], v[69:70], -4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[71:72], v[135:136], v[109:110], -v[71:72]
	v_mul_f64 v[75:76], v[91:92], v[91:92]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[69:70], 0x3fe20000, v[101:102], -v[69:70]
	v_fma_f64 v[75:76], v[111:112], v[111:112], -v[75:76]
	s_waitcnt vmcnt(9)
	v_add_f64 v[87:88], v[55:56], v[53:54]
	v_add_f64 v[115:116], v[57:58], v[51:52]
	s_clause 0x1
	global_load_b128 v[51:54], v[93:94], off
	global_load_b128 v[55:58], v[93:94], off offset:-16
	global_load_b64 v[93:94], v[103:104], off
	global_load_b64 v[103:104], v[113:114], off
	v_ldexp_f64 v[87:88], v[87:88], -4
	s_waitcnt vmcnt(11)
	v_add_f64 v[7:8], v[9:10], v[7:8]
	s_waitcnt vmcnt(10)
	v_add_f64 v[9:10], v[81:82], v[73:74]
	v_add_f64 v[73:74], v[81:82], v[107:108]
	v_add_f64 v[5:6], v[11:12], v[5:6]
	s_waitcnt vmcnt(7)
	v_add_f64 v[11:12], v[59:60], v[65:66]
	s_waitcnt vmcnt(6)
	v_add_f64 v[59:60], v[89:90], v[95:96]
	s_waitcnt vmcnt(5)
	v_add_f64 v[65:66], v[81:82], v[97:98]
	s_waitcnt vmcnt(4)
	v_add_f64 v[97:98], v[77:78], v[89:90]
	v_ldexp_f64 v[7:8], v[7:8], -4
	v_ldexp_f64 v[9:10], v[9:10], -4
	v_fma_f64 v[73:74], 0x3fe20000, v[73:74], -v[99:100]
	v_ldexp_f64 v[11:12], v[11:12], -4
	v_ldexp_f64 v[65:66], v[65:66], -4
	v_fma_f64 v[5:6], 0x3fe20000, v[5:6], -v[7:8]
	v_fma_f64 v[7:8], 0x3fe20000, v[59:60], -v[9:10]
	v_ldexp_f64 v[9:10], v[97:98], -4
	v_fma_f64 v[59:60], 0x3fe20000, v[127:128], -v[105:106]
	v_mul_f64 v[67:68], v[67:68], v[73:74]
	v_mul_f64 v[73:74], v[79:80], v[79:80]
	v_add_f64 v[79:80], v[81:82], v[89:90]
	v_mul_f64 v[5:6], v[5:6], v[7:8]
	s_waitcnt vmcnt(2)
	v_add_f64 v[53:54], v[55:56], v[53:54]
	v_add_f64 v[55:56], v[61:62], v[63:64]
	s_waitcnt vmcnt(1)
	v_add_f64 v[61:62], v[77:78], v[93:94]
	v_add_f64 v[63:64], v[93:94], v[95:96]
	v_add_f64 v[77:78], v[81:82], v[93:94]
	v_add_f64 v[51:52], v[57:58], v[51:52]
	v_ldexp_f64 v[53:54], v[53:54], -4
	v_fma_f64 v[11:12], 0x3fe20000, v[55:56], -v[11:12]
	v_fma_f64 v[55:56], 0x3fe20000, v[61:62], -v[65:66]
	v_ldexp_f64 v[57:58], v[63:64], -4
	v_fma_f64 v[63:64], 0x3fe20000, v[115:116], -v[87:88]
	v_fma_f64 v[7:8], 0x3fe20000, v[77:78], -v[9:10]
	v_fma_f64 v[9:10], v[59:60], v[59:60], -v[73:74]
	v_fma_f64 v[59:60], v[83:84], v[69:70], -v[67:68]
	v_mul_f64 v[61:62], v[75:76], s[6:7]
	v_mul_f64 v[65:66], v[71:72], s[6:7]
	v_fma_f64 v[51:52], 0x3fe20000, v[51:52], -v[53:54]
	v_fma_f64 v[5:6], v[11:12], v[55:56], -v[5:6]
	v_fma_f64 v[53:54], 0x3fe20000, v[79:80], -v[57:58]
	v_mul_f64 v[7:8], v[63:64], v[7:8]
	v_fma_f64 v[9:10], 0x3ff20000, v[9:10], v[61:62]
	v_fma_f64 v[11:12], 0x3ff20000, v[59:60], v[65:66]
	v_mul_f64 v[5:6], v[5:6], s[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[7:8], v[51:52], v[53:54], -v[7:8]
	v_add_f64 v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], 0x3ff20000, v[7:8], v[5:6]
	v_add_f64 v[5:6], v[9:10], v[5:6]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[5:6], v[103:104], v[5:6]
	global_store_b64 v[113:114], v[5:6], off
	s_cbranch_scc1 .LBB1_3
.LBB1_18:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 137
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii, .Lfunc_end1-_Z14advec_gpu_smemPdPKdS1_S1_iiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3292
; NumSgprs: 30
; NumVgprs: 137
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 17
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 137
; Occupancy: 10
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
