/*
* Copyright 2015 Netherlands eScience Center, VU University Amsterdam, and Netherlands Forensic Institute
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/**
 * This file contains CUDA kernels for comparing two PRNU noise patterns
 * using Peak To Correlation Energy.
 *
 * @author Ben van Werkhoven <b.vanwerkhoven@esciencecenter.nl>
 * @author Hanno Spreeuw <h.spreeuw@esciencecenter.nl>
 * @version 0.2
 */

// Should be a power of two!!
#ifndef block_size_x
#define block_size_x 256
#endif




//function interfaces to prevent C++ garbling the kernel keys
extern "C" {
    __global__ void computeSums(
            int n,
            const float *x,
            const float *y,
            double *partialXX,
            double *partialX,
            double *partialYY,
            double *partialY,
            double *partialXY
    );

    __global__ void computeNCC(
            int n,
            const double* partialXX,
            const double* partialX,
            const double* partialYY,
            const double* partialY,
            const double* partialXY,
            double* output
    );
}


__device__ __forceinline__ double sumDoublesSharedMem(double input, double *shmem) {
    int ti = threadIdx.x;

    //store local sums in shared memory
    shmem[ti] = input;
    __syncthreads();

    //reduce local sums
    for (unsigned int s=blockDim.x / 2; s>0; s>>=1) {
        if (ti < s) {
            shmem[ti] += shmem[ti + s];
        }
        __syncthreads();
    }

    return shmem[0];
}

/*
 * Simple CUDA Helper function to reduce the output of a
 * reduction kernel with multiple thread blocks to a single value
 *
 * This function performs a sum of an array of doubles
 *
 * This function is to be called with only a single thread block
 */
__global__ void computeNCC(
        int n,
        const double* __restrict__ partialXX,
        const double* __restrict__ partialX,
        const double* __restrict__ partialYY,
        const double* __restrict__ partialY,
        const double* __restrict__ partialXY,
        double* __restrict__ output
) {
    int ti = threadIdx.x;
    __shared__ double shmem[block_size_x];

    //compute thread-local sums
    double sumx = 0.0;
    double sumy = 0.0;
    double sumxx = 0.0;
    double sumyy = 0.0;
    double sumxy = 0.0;

    for (int i=ti; i < n; i+=block_size_x) {
        sumx += partialX[i];
        sumxx += partialXX[i];
        sumy += partialY[i];
        sumyy += partialYY[i];
        sumxy += partialXY[i];
    }

    //reduce local sums
    sumx = sumDoublesSharedMem(sumx, shmem);
    sumxx = sumDoublesSharedMem(sumxx, shmem);
    sumy = sumDoublesSharedMem(sumy, shmem);
    sumyy = sumDoublesSharedMem(sumyy, shmem);
    sumxy = sumDoublesSharedMem(sumxy, shmem);

    //write result
    if (ti == 0) {
        double stddev_x = sqrt(sumxx - sumx * sumx);
        double stddev_y = sqrt(sumyy - sumy * sumy);
        double ncc = sumxy / (stddev_x * stddev_y);

        output[0] = ncc;
    }
}

 
__global__ void computeSums(
        int n,
        const float *__restrict x,
        const float *__restrict y,
        double *__restrict partialXX,
        double *__restrict partialX,
        double *__restrict partialYY,
        double *__restrict partialY,
        double *__restrict partialXY
) {
    int _x = blockIdx.x * block_size_x + threadIdx.x;
    int ti = threadIdx.x;
    int step_size = gridDim.x * block_size_x;

    __shared__ double shmem[block_size_x];

    //compute thread-local sums
    double sumx = 0.0;
    double sumy = 0.0;
    double sumxx = 0.0;
    double sumyy = 0.0;
    double sumxy = 0.0;

    for (int i=_x; i < n; i+=step_size) {
        float v = x[i];
        float w = y[i];
        sumx += v;
        sumxx += v * v;
        sumy += w;
        sumyy += w * w;
        sumxy += v * w;
    }

    //reduce local sums
    sumx = sumDoublesSharedMem(sumx, shmem);
    sumxx = sumDoublesSharedMem(sumxx, shmem);
    sumy = sumDoublesSharedMem(sumy, shmem);
    sumyy = sumDoublesSharedMem(sumyy, shmem);
    sumxy = sumDoublesSharedMem(sumxy, shmem);

    //write result
    if (ti == 0) {
        partialX[blockIdx.x]  = sumx;
        partialXX[blockIdx.x] = sumxx;
        partialY[blockIdx.x]  = sumy;
        partialYY[blockIdx.x] = sumyy;
        partialXY[blockIdx.x] = sumxy;
    }
}   



	.file	"tmpxft_003191e6_00000000-6_normalizedcrosscorrelation.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z10computeNCCiPKdS0_S0_S0_S0_PdiPKdS0_S0_S0_S0_Pd
	.type	_Z46__device_stub__Z10computeNCCiPKdS0_S0_S0_S0_PdiPKdS0_S0_S0_S0_Pd, @function
_Z46__device_stub__Z10computeNCCiPKdS0_S0_S0_S0_PdiPKdS0_S0_S0_S0_Pd:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edi, 12(%rsp)
	leaq	80(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	208(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 56(%rsp)
	leaq	56(%rsp), %rax
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	computeNCC(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z46__device_stub__Z10computeNCCiPKdS0_S0_S0_S0_PdiPKdS0_S0_S0_S0_Pd, .-_Z46__device_stub__Z10computeNCCiPKdS0_S0_S0_S0_PdiPKdS0_S0_S0_S0_Pd
	.globl	computeNCC
	.type	computeNCC, @function
computeNCC:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z10computeNCCiPKdS0_S0_S0_S0_PdiPKdS0_S0_S0_S0_Pd
	.cfi_endproc
.LFE2034:
	.size	computeNCC, .-computeNCC
	.globl	_Z50__device_stub__Z11computeSumsiPKfS0_PdS1_S1_S1_S1_iPKfS0_PdS1_S1_S1_S1_
	.type	_Z50__device_stub__Z11computeSumsiPKfS0_PdS1_S1_S1_S1_iPKfS0_PdS1_S1_S1_S1_, @function
_Z50__device_stub__Z11computeSumsiPKfS0_PdS1_S1_S1_S1_iPKfS0_PdS1_S1_S1_S1_:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%edi, 12(%rsp)
	leaq	88(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	224(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 56(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	232(%rsp), %rax
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%rax, 64(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	computeSums(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z50__device_stub__Z11computeSumsiPKfS0_PdS1_S1_S1_S1_iPKfS0_PdS1_S1_S1_S1_, .-_Z50__device_stub__Z11computeSumsiPKfS0_PdS1_S1_S1_S1_iPKfS0_PdS1_S1_S1_S1_
	.globl	computeSums
	.type	computeSums, @function
computeSums:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z11computeSumsiPKfS0_PdS1_S1_S1_S1_iPKfS0_PdS1_S1_S1_S1_
	.cfi_endproc
.LFE2036:
	.size	computeSums, .-computeSums
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"computeSums"
.LC1:
	.string	"computeNCC"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	computeSums(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	computeNCC(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*
* Copyright 2015 Netherlands eScience Center, VU University Amsterdam, and Netherlands Forensic Institute
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/**
 * This file contains CUDA kernels for comparing two PRNU noise patterns
 * using Peak To Correlation Energy.
 *
 * @author Ben van Werkhoven <b.vanwerkhoven@esciencecenter.nl>
 * @author Hanno Spreeuw <h.spreeuw@esciencecenter.nl>
 * @version 0.2
 */

// Should be a power of two!!
#ifndef block_size_x
#define block_size_x 256
#endif




//function interfaces to prevent C++ garbling the kernel keys
extern "C" {
    __global__ void computeSums(
            int n,
            const float *x,
            const float *y,
            double *partialXX,
            double *partialX,
            double *partialYY,
            double *partialY,
            double *partialXY
    );

    __global__ void computeNCC(
            int n,
            const double* partialXX,
            const double* partialX,
            const double* partialYY,
            const double* partialY,
            const double* partialXY,
            double* output
    );
}


__device__ __forceinline__ double sumDoublesSharedMem(double input, double *shmem) {
    int ti = threadIdx.x;

    //store local sums in shared memory
    shmem[ti] = input;
    __syncthreads();

    //reduce local sums
    for (unsigned int s=blockDim.x / 2; s>0; s>>=1) {
        if (ti < s) {
            shmem[ti] += shmem[ti + s];
        }
        __syncthreads();
    }

    return shmem[0];
}

/*
 * Simple CUDA Helper function to reduce the output of a
 * reduction kernel with multiple thread blocks to a single value
 *
 * This function performs a sum of an array of doubles
 *
 * This function is to be called with only a single thread block
 */
__global__ void computeNCC(
        int n,
        const double* __restrict__ partialXX,
        const double* __restrict__ partialX,
        const double* __restrict__ partialYY,
        const double* __restrict__ partialY,
        const double* __restrict__ partialXY,
        double* __restrict__ output
) {
    int ti = threadIdx.x;
    __shared__ double shmem[block_size_x];

    //compute thread-local sums
    double sumx = 0.0;
    double sumy = 0.0;
    double sumxx = 0.0;
    double sumyy = 0.0;
    double sumxy = 0.0;

    for (int i=ti; i < n; i+=block_size_x) {
        sumx += partialX[i];
        sumxx += partialXX[i];
        sumy += partialY[i];
        sumyy += partialYY[i];
        sumxy += partialXY[i];
    }

    //reduce local sums
    sumx = sumDoublesSharedMem(sumx, shmem);
    sumxx = sumDoublesSharedMem(sumxx, shmem);
    sumy = sumDoublesSharedMem(sumy, shmem);
    sumyy = sumDoublesSharedMem(sumyy, shmem);
    sumxy = sumDoublesSharedMem(sumxy, shmem);

    //write result
    if (ti == 0) {
        double stddev_x = sqrt(sumxx - sumx * sumx);
        double stddev_y = sqrt(sumyy - sumy * sumy);
        double ncc = sumxy / (stddev_x * stddev_y);

        output[0] = ncc;
    }
}

 
__global__ void computeSums(
        int n,
        const float *__restrict x,
        const float *__restrict y,
        double *__restrict partialXX,
        double *__restrict partialX,
        double *__restrict partialYY,
        double *__restrict partialY,
        double *__restrict partialXY
) {
    int _x = blockIdx.x * block_size_x + threadIdx.x;
    int ti = threadIdx.x;
    int step_size = gridDim.x * block_size_x;

    __shared__ double shmem[block_size_x];

    //compute thread-local sums
    double sumx = 0.0;
    double sumy = 0.0;
    double sumxx = 0.0;
    double sumyy = 0.0;
    double sumxy = 0.0;

    for (int i=_x; i < n; i+=step_size) {
        float v = x[i];
        float w = y[i];
        sumx += v;
        sumxx += v * v;
        sumy += w;
        sumyy += w * w;
        sumxy += v * w;
    }

    //reduce local sums
    sumx = sumDoublesSharedMem(sumx, shmem);
    sumxx = sumDoublesSharedMem(sumxx, shmem);
    sumy = sumDoublesSharedMem(sumy, shmem);
    sumyy = sumDoublesSharedMem(sumyy, shmem);
    sumxy = sumDoublesSharedMem(sumxy, shmem);

    //write result
    if (ti == 0) {
        partialX[blockIdx.x]  = sumx;
        partialXX[blockIdx.x] = sumxx;
        partialY[blockIdx.x]  = sumy;
        partialYY[blockIdx.x] = sumyy;
        partialXY[blockIdx.x] = sumxy;
    }
}   



	.text
	.file	"normalizedcrosscorrelation.hip"
	.globl	__device_stub__computeNCC       # -- Begin function __device_stub__computeNCC
	.type	__device_stub__computeNCC,@function
__device_stub__computeNCC:              # @__device_stub__computeNCC
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$computeNCC, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__computeNCC, .Lfunc_end0-__device_stub__computeNCC
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__computeSums      # -- Begin function __device_stub__computeSums
	.type	__device_stub__computeSums,@function
__device_stub__computeSums:             # @__device_stub__computeSums
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$computeSums, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__computeSums, .Lfunc_end1-__device_stub__computeSums
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$computeNCC, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$computeSums, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	computeNCC,@object              # @computeNCC
	.section	.rodata,"a",@progbits
	.globl	computeNCC
	.p2align	3, 0x0
computeNCC:
	.quad	__device_stub__computeNCC
	.size	computeNCC, 8

	.type	computeSums,@object             # @computeSums
	.globl	computeSums
	.p2align	3, 0x0
computeSums:
	.quad	__device_stub__computeSums
	.size	computeSums, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"computeNCC"
	.size	.L__unnamed_1, 11

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"computeSums"
	.size	.L__unnamed_2, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__computeNCC
	.addrsig_sym __device_stub__computeSums
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym computeNCC
	.addrsig_sym computeSums
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	computeNCC              ; -- Begin function computeNCC
	.globl	computeNCC
	.p2align	8
	.type	computeNCC,@function
computeNCC:                             ; @computeNCC
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x30
	v_mov_b32_e32 v7, 0
	v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v21, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v5, v7
	v_mov_b32_e32 v1, v7
	v_dual_mov_b32 v3, v7 :: v_dual_mov_b32 v4, v8
	v_mov_b32_e32 v6, v8
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	v_mov_b32_e32 v2, v8
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x8
	s_load_b64 s[16:17], s[0:1], 0x28
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v22, v0
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v5, v7
	v_mov_b32_e32 v1, v7
	v_mov_b32_e32 v3, v7
	s_mov_b32 s7, 0
	v_mov_b32_e32 v4, v8
	v_mov_b32_e32 v6, v8
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	v_mov_b32_e32 v2, v8
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v11, s2, s10, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, null, s11, 0, s2
	v_add_co_u32 v13, s2, s8, v21
	v_add_co_ci_u32_e64 v14, null, s9, 0, s2
	v_add_co_u32 v15, s2, s14, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, null, s15, 0, s2
	v_add_co_u32 v17, s2, s12, v21
	v_add_co_ci_u32_e64 v18, null, s13, 0, s2
	v_add_co_u32 v19, s2, s16, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v20, null, s17, 0, s2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[23:24], v[11:12], off
	global_load_b64 v[25:26], v[13:14], off
	global_load_b64 v[27:28], v[15:16], off
	global_load_b64 v[29:30], v[17:18], off
	global_load_b64 v[31:32], v[19:20], off
	v_add_co_u32 v11, vcc_lo, 0x800, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, 0x800, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v15, vcc_lo, 0x800, v15
	v_add_nc_u32_e32 v22, 0x100, v22
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v17, vcc_lo, 0x800, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s3, v22
	v_add_co_u32 v19, s2, 0x800, v19
	v_add_co_ci_u32_e64 v20, s2, 0, v20, s2
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(4)
	v_add_f64 v[7:8], v[7:8], v[23:24]
	s_waitcnt vmcnt(3)
	v_add_f64 v[9:10], v[9:10], v[25:26]
	s_waitcnt vmcnt(2)
	v_add_f64 v[5:6], v[5:6], v[27:28]
	s_waitcnt vmcnt(1)
	v_add_f64 v[3:4], v[3:4], v[29:30]
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[31:32]
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %Flow143
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:                                ; %Flow144
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b64 v21, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s0, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s0, 1
	s_cselect_b32 s1, -1, 0
	s_cmp_lt_u32 s0, 2
	s_cbranch_scc1 .LBB0_9
; %bb.5:                                ; %.lr.ph.preheader.i
	s_lshr_b32 s2, s0, 1
.LBB0_6:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s2, v0
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	v_lshl_add_u32 v7, s2, 3, v21
	ds_load_b64 v[7:8], v7
	ds_load_b64 v[11:12], v21
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	ds_store_b64 v21, v[7:8]
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_lshr_b32 s3, s2, 1
	s_cmp_gt_u32 s2, 1
	s_mov_b32 s2, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_6
.LBB0_9:                                ; %_Z19sumDoublesSharedMemdPd.exit
	v_mov_b32_e32 v12, 0
	v_cndmask_b32_e64 v11, 0, 1, s1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	ds_load_b64 v[7:8], v12
	ds_store_b64 v21, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_14
; %bb.10:                               ; %.lr.ph.preheader.i47
	s_lshr_b32 s1, s0, 1
.LBB0_11:                               ; %.lr.ph.i49
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	v_lshl_add_u32 v9, s1, 3, v21
	ds_load_b64 v[9:10], v9
	ds_load_b64 v[13:14], v21
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[9:10], v[9:10], v[13:14]
	ds_store_b64 v21, v[9:10]
.LBB0_13:                               ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_lshr_b32 s2, s1, 1
	s_cmp_gt_u32 s1, 1
	s_mov_b32 s1, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_11
.LBB0_14:                               ; %_Z19sumDoublesSharedMemdPd.exit53
	ds_load_b64 v[9:10], v12
	v_cmp_ne_u32_e32 vcc_lo, 1, v11
	ds_store_b64 v21, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_19
; %bb.15:                               ; %.lr.ph.preheader.i55
	s_lshr_b32 s1, s0, 1
.LBB0_16:                               ; %.lr.ph.i57
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_16 Depth=1
	v_lshl_add_u32 v5, s1, 3, v21
	ds_load_b64 v[5:6], v5
	ds_load_b64 v[12:13], v21
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[5:6], v[5:6], v[12:13]
	ds_store_b64 v21, v[5:6]
.LBB0_18:                               ;   in Loop: Header=BB0_16 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_lshr_b32 s2, s1, 1
	s_cmp_gt_u32 s1, 1
	s_mov_b32 s1, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_16
.LBB0_19:                               ; %_Z19sumDoublesSharedMemdPd.exit61
	v_mov_b32_e32 v12, 0
	v_cmp_ne_u32_e32 vcc_lo, 1, v11
	ds_load_b64 v[5:6], v12
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	ds_store_b64 v21, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_24
; %bb.20:                               ; %.lr.ph.preheader.i63
	s_lshr_b32 s1, s0, 1
.LBB0_21:                               ; %.lr.ph.i65
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
	v_lshl_add_u32 v3, s1, 3, v21
	ds_load_b64 v[3:4], v3
	ds_load_b64 v[13:14], v21
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[13:14]
	ds_store_b64 v21, v[3:4]
.LBB0_23:                               ;   in Loop: Header=BB0_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_lshr_b32 s2, s1, 1
	s_cmp_gt_u32 s1, 1
	s_mov_b32 s1, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_21
.LBB0_24:                               ; %_Z19sumDoublesSharedMemdPd.exit69
	ds_load_b64 v[3:4], v12
	v_cmp_ne_u32_e32 vcc_lo, 1, v11
	ds_store_b64 v21, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_29
; %bb.25:                               ; %.lr.ph.preheader.i71
	s_lshr_b32 s0, s0, 1
.LBB0_26:                               ; %.lr.ph.i73
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_26 Depth=1
	v_lshl_add_u32 v1, s0, 3, v21
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[11:12], v21
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[11:12]
	ds_store_b64 v21, v[1:2]
.LBB0_28:                               ;   in Loop: Header=BB0_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_26
.LBB0_29:                               ; %_Z19sumDoublesSharedMemdPd.exit77
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_fma_f64 v[0:1], -v[7:8], v[7:8], v[9:10]
	v_fma_f64 v[2:3], -v[5:6], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cmp_gt_f64_e64 s0, 0x10000000, v[2:3]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v5, 0, 1, s0
	s_and_b32 s1, vcc_lo, exec_lo
	s_cselect_b32 s1, 0xffffff80, 0
	s_and_b32 s0, s0, exec_lo
	v_lshlrev_b32_e32 v4, 8, v4
	s_cselect_b32 s0, 0xffffff80, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], v4
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	v_lshlrev_b32_e32 v5, 8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], v5
	v_rsq_f64_e32 v[4:5], v[0:1]
	v_rsq_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[8:9], v[0:1], v[4:5]
	v_mul_f64 v[4:5], v[4:5], 0.5
	v_mul_f64 v[10:11], v[2:3], v[6:7]
	v_mul_f64 v[6:7], v[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], -v[4:5], v[8:9], 0.5
	v_fma_f64 v[14:15], -v[6:7], v[10:11], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
	v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
	v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
	v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[12:13], v[4:5], v[8:9]
	v_fma_f64 v[10:11], v[14:15], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
	v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
	v_mov_b32_e32 v12, 0
	v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[4:5], v[4:5], s1
	v_ldexp_f64 v[6:7], v[6:7], s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v4, v0, vcc_lo
	v_cmp_class_f64_e64 s0, v[2:3], 0x260
	v_cndmask_b32_e32 v1, v5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v7, v3, s0
	v_cndmask_b32_e64 v2, v6, v2, s0
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	ds_load_b64 v[2:3], v12
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_div_fixup_f64 v[0:1], v[4:5], v[0:1], v[2:3]
	global_store_b64 v12, v[0:1], s[4:5]
.LBB0_31:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel computeNCC
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	computeNCC, .Lfunc_end0-computeNCC
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1756
; NumSgprs: 20
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	computeSums             ; -- Begin function computeSums
	.globl	computeSums
	.p2align	8
	.type	computeSums,@function
computeSums:                            ; @computeSums
; %bb.0:
	s_clause 0x2
	s_load_b32 s17, s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x38
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_mov_b32 s16, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v1, v5
	v_lshl_add_u32 v11, s16, 8, v0
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v2, v6
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
	s_add_u32 s18, s0, 64
	s_addc_u32 s19, s1, 0
	s_mov_b32 s24, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s17, v11
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s20, s[18:19], 0x0
	s_load_b128 s[12:15], s[0:1], 0x8
	v_ashrrev_i32_e32 v12, 31, v11
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v1, v5
	v_mov_b32_e32 v3, v5
	v_lshlrev_b64 v[12:13], 2, v[11:12]
	s_mov_b32 s1, 0
	v_mov_b32_e32 v4, v6
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v2, v6
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s20, s20, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s21, s20, 31
	s_lshl_b64 s[22:23], s[20:21], 2
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v14, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v12
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v13, vcc_lo
	v_add_co_u32 v12, s0, v12, s22
	global_load_b32 v14, v[14:15], off
	global_load_b32 v16, v[16:17], off
	v_add_co_ci_u32_e64 v13, s0, s23, v13, s0
	v_add_nc_u32_e32 v11, s20, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s17, v11
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v18, v14, v14
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v20, v16, v16
	v_mul_f32_e32 v22, v14, v16
	v_cvt_f64_f32_e32 v[14:15], v14
	v_cvt_f64_f32_e32 v[16:17], v16
	v_cvt_f64_f32_e32 v[18:19], v18
	v_cvt_f64_f32_e32 v[20:21], v20
	v_cvt_f64_f32_e32 v[22:23], v22
	v_add_f64 v[5:6], v[5:6], v[14:15]
	v_add_f64 v[7:8], v[7:8], v[16:17]
	v_add_f64 v[9:10], v[9:10], v[18:19]
	v_add_f64 v[3:4], v[3:4], v[20:21]
	v_add_f64 v[1:2], v[1:2], v[22:23]
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_2
; %bb.3:                                ; %Flow134
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_4:                                ; %Flow135
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s24
	v_lshlrev_b32_e32 v11, 3, v0
	ds_store_b64 v11, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s0, s[18:19], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s0, 1
	s_cselect_b32 s1, -1, 0
	s_cmp_lt_u32 s0, 2
	s_cbranch_scc1 .LBB1_9
; %bb.5:                                ; %.lr.ph.preheader.i
	s_lshr_b32 s12, s0, 1
.LBB1_6:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s13, exec_lo
	v_cmpx_gt_u32_e64 s12, v0
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=1
	v_lshl_add_u32 v5, s12, 3, v11
	ds_load_b64 v[5:6], v5
	ds_load_b64 v[12:13], v11
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[5:6], v[5:6], v[12:13]
	ds_store_b64 v11, v[5:6]
.LBB1_8:                                ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_lshr_b32 s13, s12, 1
	s_cmp_gt_u32 s12, 1
	s_mov_b32 s12, s13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_6
.LBB1_9:                                ; %_Z19sumDoublesSharedMemdPd.exit
	v_mov_b32_e32 v13, 0
	v_cndmask_b32_e64 v12, 0, 1, s1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	ds_load_b64 v[5:6], v13
	ds_store_b64 v11, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_14
; %bb.10:                               ; %.lr.ph.preheader.i50
	s_lshr_b32 s1, s0, 1
.LBB1_11:                               ; %.lr.ph.i52
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB1_13
; %bb.12:                               ;   in Loop: Header=BB1_11 Depth=1
	v_lshl_add_u32 v9, s1, 3, v11
	ds_load_b64 v[9:10], v9
	ds_load_b64 v[14:15], v11
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[9:10], v[9:10], v[14:15]
	ds_store_b64 v11, v[9:10]
.LBB1_13:                               ;   in Loop: Header=BB1_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshr_b32 s12, s1, 1
	s_cmp_gt_u32 s1, 1
	s_mov_b32 s1, s12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_11
.LBB1_14:                               ; %_Z19sumDoublesSharedMemdPd.exit56
	ds_load_b64 v[9:10], v13
	v_cmp_ne_u32_e32 vcc_lo, 1, v12
	ds_store_b64 v11, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_19
; %bb.15:                               ; %.lr.ph.preheader.i58
	s_lshr_b32 s1, s0, 1
.LBB1_16:                               ; %.lr.ph.i60
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_16 Depth=1
	v_lshl_add_u32 v7, s1, 3, v11
	ds_load_b64 v[7:8], v7
	ds_load_b64 v[13:14], v11
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[13:14]
	ds_store_b64 v11, v[7:8]
.LBB1_18:                               ;   in Loop: Header=BB1_16 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshr_b32 s12, s1, 1
	s_cmp_gt_u32 s1, 1
	s_mov_b32 s1, s12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_16
.LBB1_19:                               ; %_Z19sumDoublesSharedMemdPd.exit64
	v_mov_b32_e32 v13, 0
	v_cmp_ne_u32_e32 vcc_lo, 1, v12
	ds_load_b64 v[7:8], v13
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	ds_store_b64 v11, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_24
; %bb.20:                               ; %.lr.ph.preheader.i66
	s_lshr_b32 s1, s0, 1
.LBB1_21:                               ; %.lr.ph.i68
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB1_23
; %bb.22:                               ;   in Loop: Header=BB1_21 Depth=1
	v_lshl_add_u32 v3, s1, 3, v11
	ds_load_b64 v[3:4], v3
	ds_load_b64 v[14:15], v11
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[14:15]
	ds_store_b64 v11, v[3:4]
.LBB1_23:                               ;   in Loop: Header=BB1_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshr_b32 s12, s1, 1
	s_cmp_gt_u32 s1, 1
	s_mov_b32 s1, s12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_21
.LBB1_24:                               ; %_Z19sumDoublesSharedMemdPd.exit72
	ds_load_b64 v[3:4], v13
	v_cmp_ne_u32_e32 vcc_lo, 1, v12
	ds_store_b64 v11, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_29
; %bb.25:                               ; %.lr.ph.preheader.i74
	s_lshr_b32 s0, s0, 1
.LBB1_26:                               ; %.lr.ph.i76
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB1_28
; %bb.27:                               ;   in Loop: Header=BB1_26 Depth=1
	v_lshl_add_u32 v1, s0, 3, v11
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[12:13], v11
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[12:13]
	ds_store_b64 v11, v[1:2]
.LBB1_28:                               ;   in Loop: Header=BB1_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_26
.LBB1_29:                               ; %_Z19sumDoublesSharedMemdPd.exit80
	s_mov_b32 s17, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_31
; %bb.30:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[16:17], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s6, s0
	s_addc_u32 s7, s7, s1
	ds_load_b64 v[0:1], v2
	s_add_u32 s4, s4, s0
	s_addc_u32 s5, s5, s1
	s_add_u32 s10, s10, s0
	s_addc_u32 s11, s11, s1
	s_add_u32 s8, s8, s0
	s_addc_u32 s9, s9, s1
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_clause 0x3
	global_store_b64 v2, v[5:6], s[6:7]
	global_store_b64 v2, v[9:10], s[4:5]
	global_store_b64 v2, v[7:8], s[10:11]
	global_store_b64 v2, v[3:4], s[8:9]
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB1_31:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel computeSums
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	computeSums, .Lfunc_end1-computeSums
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1264
; NumSgprs: 27
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           computeNCC
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         computeNCC.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           computeSums
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         computeSums.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
