#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>

#define SIZE 400
// two dimension
#define Blocks 20        
#define threadPerBlock 20
//For practicing, only consider 16*16 matrix

__global__ void gpuMM_noshared(float* d_a, float* d_b, float* d_res){
    //each thread is responsible for one element of res matrix

    int row = threadIdx.x + blockIdx.x * blockDim.x;
    int col = threadIdx.y + blockIdx.y * blockDim.x;

    for(int k=0;k<SIZE;k++){
        d_res[row * SIZE + col] += d_a[row * SIZE + k] * d_b[k * SIZE + col];
    }
}


__global__ void gpuMM_shared(float* d_a, float* d_b, float* d_res){
    int row = threadIdx.x + blockIdx.x * blockDim.x;
    int col = threadIdx.y + blockIdx.y * blockDim.x;

	__shared__ float tmp_a[20][20];
    __shared__ float tmp_b[20][20];
    
    for(int k=0;k<SIZE/threadPerBlock;k++){
        tmp_a[threadIdx.x][threadIdx.y] = d_a[row*SIZE + k * threadPerBlock + threadIdx.y];
        tmp_b[threadIdx.x][threadIdx.y] = d_b[(k*threadPerBlock + threadIdx.x)*SIZE + col];

        __syncthreads();

        for(int j=0;j<SIZE/Blocks;j++){
            d_res[row*SIZE + col] += tmp_a[threadIdx.x][j] * tmp_b[j][threadIdx.y];
        }
        __syncthreads();
    }
}

void cpuMM(float* a, float* b, float* c){
    for(int i=0;i<SIZE;i++){
        for(int j=0;j<SIZE;j++){
            for(int k=0;k<SIZE;k++){
                c[i*SIZE + j] += a[i* SIZE + k] * b[k * SIZE + j];
            }
        }
    }
}


int main(){
    int sizeByte = SIZE * SIZE * sizeof(float);
    float* h_a = (float* ) malloc(sizeByte);
    float* h_b = (float* ) malloc(sizeByte);
    float* h_c_cpu = (float* ) malloc(sizeByte);
    float* h_c_gpu = (float* ) malloc(sizeByte);

    float time = 0;

    for(int i=0;i<SIZE;i++){
        for(int j=0;j<SIZE;j++){
            h_a[i*SIZE+j] = (i+j)/2+200;
            h_b[i*SIZE+j] = (i+j)/2+200;
            h_c_cpu[i*SIZE+j] = 0;
            h_c_gpu[i*SIZE+j] = 0;
        }
    }

    cudaEvent_t start,stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    cudaEventRecord(start,0);

    cpuMM(h_a,h_b,h_c_cpu);

    cudaEventRecord(stop,0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    printf("Running on CPU, time elapsed...%lf\n",time);
    
    float *d_a;
    float *d_b;
    float *d_c;

    cudaMalloc(&d_a, sizeByte);
    cudaMalloc(&d_b, sizeByte);
    cudaMalloc(&d_c, sizeByte);

    cudaMemcpy(d_a, h_a, sizeByte, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, sizeByte, cudaMemcpyHostToDevice);

    dim3 Grid(20,20,1);
    dim3 Block(20,20,1);

    cudaEventRecord(start,0);

    gpuMM_shared<<<Grid,Block>>>(d_a,d_b,d_c);

    cudaEventRecord(stop,0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    printf("Running on GPU(noshared), time elapsed...%lf\n",time);

    cudaMemcpy(h_c_gpu, d_c, sizeByte, cudaMemcpyDeviceToHost);

    for(int i=0;i<SIZE*SIZE;i++){
        if(h_c_cpu[i] != h_c_gpu[i]){
            printf("Error, CPU(%lf) != GPU(%lf) at index %d\n", h_c_cpu[i], h_c_gpu[i], i);
            return -1;
        }
    }

    return 0;

}

	.file	"tmpxft_002ea81b_00000000-6_gpuMatrixMulti.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5cpuMMPfS_S_
	.type	_Z5cpuMMPfS_S_, @function
_Z5cpuMMPfS_S_:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	leaq	(%rdx,%rax), %r8
	xorl	%ecx, %ecx
	leaq	(%rdi,%rax), %r11
.L7:
	leaq	(%rsi,%rcx,4), %r10
	xorl	%r9d, %r9d
.L4:
	movss	(%r11,%r9,4), %xmm0
	mulss	(%r10), %xmm0
	incq	%r9
	addq	$1600, %r10
	addss	(%r8), %xmm0
	movss	%xmm0, (%r8)
	cmpq	$400, %r9
	jne	.L4
	incq	%rcx
	addq	$4, %r8
	cmpq	$400, %rcx
	jne	.L7
	addq	$1600, %rax
	cmpq	$640000, %rax
	jne	.L3
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z5cpuMMPfS_S_, .-_Z5cpuMMPfS_S_
	.globl	_Z38__device_stub__Z14gpuMM_nosharedPfS_S_PfS_S_
	.type	_Z38__device_stub__Z14gpuMM_nosharedPfS_S_PfS_S_, @function
_Z38__device_stub__Z14gpuMM_nosharedPfS_S_PfS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14gpuMM_nosharedPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L10:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z38__device_stub__Z14gpuMM_nosharedPfS_S_PfS_S_, .-_Z38__device_stub__Z14gpuMM_nosharedPfS_S_PfS_S_
	.globl	_Z14gpuMM_nosharedPfS_S_
	.type	_Z14gpuMM_nosharedPfS_S_, @function
_Z14gpuMM_nosharedPfS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14gpuMM_nosharedPfS_S_PfS_S_
	.cfi_endproc
.LFE2054:
	.size	_Z14gpuMM_nosharedPfS_S_, .-_Z14gpuMM_nosharedPfS_S_
	.globl	_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_
	.type	_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_, @function
_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12gpuMM_sharedPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L15:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_, .-_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_
	.globl	_Z12gpuMM_sharedPfS_S_
	.type	_Z12gpuMM_sharedPfS_S_, @function
_Z12gpuMM_sharedPfS_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_
	.cfi_endproc
.LFE2056:
	.size	_Z12gpuMM_sharedPfS_S_, .-_Z12gpuMM_sharedPfS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Running on CPU, time elapsed...%lf\n"
.LC2:
	.string	"Running on GPU(noshared), time elapsed...%lf\n"
.LC3:
	.string	"Error, CPU(%lf) != GPU(%lf) at index %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$640000, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$640000, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$640000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$640000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$0x00000000, 4(%rsp)
	movq	%rax, %rbp
	xorl	%eax, %eax
.L22:
	imulq	$1600, %rax, %rsi
	movl	%eax, %edi
	xorl	%ecx, %ecx
.L21:
	leal	(%rcx,%rdi), %edx
	incl	%ecx
	sarl	%edx
	addl	$200, %edx
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, 0(%r13,%rsi)
	movss	%xmm0, (%r12,%rsi)
	addq	$4, %rsi
	cmpl	$400, %ecx
	jne	.L21
	incq	%rax
	cmpq	$400, %rax
	jne	.L22
	xorl	%eax, %eax
	movl	$160000, %ecx
	leaq	4(%rsp), %r14
	movq	%rbp, %rdi
	rep stosl
	movl	$160000, %ecx
	movq	%rbx, %rdi
	rep stosl
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movq	%r13, %rdi
	call	_Z5cpuMMPfS_S_
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	leaq	24(%rsp), %rdi
	movl	$640000, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$640000, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$640000, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$640000, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$640000, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$85899345940, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	cudaEventRecord@PLT
	movl	68(%rsp), %ecx
	movl	56(%rsp), %esi
	xorl	%r9d, %r9d
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z36__device_stub__Z12gpuMM_sharedPfS_S_PfS_S_
.L25:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rsi
	movl	$640000, %edx
	movl	$2, %ecx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	xorl	%edx, %edx
.L29:
	movss	(%rbx,%rdx,4), %xmm0
	movss	0(%rbp,%rdx,4), %xmm1
	ucomiss	%xmm1, %xmm0
	jp	.L31
	je	.L26
.L31:
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L20
.L26:
	incq	%rdx
	cmpq	$160000, %rdx
	jne	.L29
	xorl	%eax, %eax
.L20:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z12gpuMM_sharedPfS_S_"
.LC5:
	.string	"_Z14gpuMM_nosharedPfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12gpuMM_sharedPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14gpuMM_nosharedPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>


#define SIZE 400
// two dimension
#define Blocks 20        
#define threadPerBlock 20
//For practicing, only consider 16*16 matrix

__global__ void gpuMM_noshared(float* d_a, float* d_b, float* d_res){
    //each thread is responsible for one element of res matrix

    int row = threadIdx.x + blockIdx.x * blockDim.x;
    int col = threadIdx.y + blockIdx.y * blockDim.x;

    for(int k=0;k<SIZE;k++){
        d_res[row * SIZE + col] += d_a[row * SIZE + k] * d_b[k * SIZE + col];
    }
}


__global__ void gpuMM_shared(float* d_a, float* d_b, float* d_res){
    int row = threadIdx.x + blockIdx.x * blockDim.x;
    int col = threadIdx.y + blockIdx.y * blockDim.x;

	__shared__ float tmp_a[20][20];
    __shared__ float tmp_b[20][20];
    
    for(int k=0;k<SIZE/threadPerBlock;k++){
        tmp_a[threadIdx.x][threadIdx.y] = d_a[row*SIZE + k * threadPerBlock + threadIdx.y];
        tmp_b[threadIdx.x][threadIdx.y] = d_b[(k*threadPerBlock + threadIdx.x)*SIZE + col];

        __syncthreads();

        for(int j=0;j<SIZE/Blocks;j++){
            d_res[row*SIZE + col] += tmp_a[threadIdx.x][j] * tmp_b[j][threadIdx.y];
        }
        __syncthreads();
    }
}

void cpuMM(float* a, float* b, float* c){
    for(int i=0;i<SIZE;i++){
        for(int j=0;j<SIZE;j++){
            for(int k=0;k<SIZE;k++){
                c[i*SIZE + j] += a[i* SIZE + k] * b[k * SIZE + j];
            }
        }
    }
}


int main(){
    int sizeByte = SIZE * SIZE * sizeof(float);
    float* h_a = (float* ) malloc(sizeByte);
    float* h_b = (float* ) malloc(sizeByte);
    float* h_c_cpu = (float* ) malloc(sizeByte);
    float* h_c_gpu = (float* ) malloc(sizeByte);

    float time = 0;

    for(int i=0;i<SIZE;i++){
        for(int j=0;j<SIZE;j++){
            h_a[i*SIZE+j] = (i+j)/2+200;
            h_b[i*SIZE+j] = (i+j)/2+200;
            h_c_cpu[i*SIZE+j] = 0;
            h_c_gpu[i*SIZE+j] = 0;
        }
    }

    hipEvent_t start,stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);
    hipEventRecord(start,0);

    cpuMM(h_a,h_b,h_c_cpu);

    hipEventRecord(stop,0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    printf("Running on CPU, time elapsed...%lf\n",time);
    
    float *d_a;
    float *d_b;
    float *d_c;

    hipMalloc(&d_a, sizeByte);
    hipMalloc(&d_b, sizeByte);
    hipMalloc(&d_c, sizeByte);

    hipMemcpy(d_a, h_a, sizeByte, hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b, sizeByte, hipMemcpyHostToDevice);

    dim3 Grid(20,20,1);
    dim3 Block(20,20,1);

    hipEventRecord(start,0);

    gpuMM_shared<<<Grid,Block>>>(d_a,d_b,d_c);

    hipEventRecord(stop,0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    printf("Running on GPU(noshared), time elapsed...%lf\n",time);

    hipMemcpy(h_c_gpu, d_c, sizeByte, hipMemcpyDeviceToHost);

    for(int i=0;i<SIZE*SIZE;i++){
        if(h_c_cpu[i] != h_c_gpu[i]){
            printf("Error, CPU(%lf) != GPU(%lf) at index %d\n", h_c_cpu[i], h_c_gpu[i], i);
            return -1;
        }
    }

    return 0;

}

	.text
	.file	"gpuMatrixMulti.hip"
	.globl	_Z29__device_stub__gpuMM_nosharedPfS_S_ # -- Begin function _Z29__device_stub__gpuMM_nosharedPfS_S_
	.type	_Z29__device_stub__gpuMM_nosharedPfS_S_,@function
_Z29__device_stub__gpuMM_nosharedPfS_S_: # @_Z29__device_stub__gpuMM_nosharedPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14gpuMM_nosharedPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__gpuMM_nosharedPfS_S_, .Lfunc_end0-_Z29__device_stub__gpuMM_nosharedPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__gpuMM_sharedPfS_S_ # -- Begin function _Z27__device_stub__gpuMM_sharedPfS_S_
	.type	_Z27__device_stub__gpuMM_sharedPfS_S_,@function
_Z27__device_stub__gpuMM_sharedPfS_S_:  # @_Z27__device_stub__gpuMM_sharedPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12gpuMM_sharedPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__gpuMM_sharedPfS_S_, .Lfunc_end1-_Z27__device_stub__gpuMM_sharedPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z5cpuMMPfS_S_                  # -- Begin function _Z5cpuMMPfS_S_
	.type	_Z5cpuMMPfS_S_,@function
_Z5cpuMMPfS_S_:                         # @_Z5cpuMMPfS_S_
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
.LBB2_1:                                # %.preheader16
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
                                        #       Child Loop BB2_3 Depth 3
	imulq	$1600, %rax, %rcx               # imm = 0x640
	addq	%rdx, %rcx
	movq	%rsi, %r8
	xorl	%r9d, %r9d
.LBB2_2:                                # %.preheader
                                        #   Parent Loop BB2_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_3 Depth 3
	movss	(%rcx,%r9,4), %xmm0             # xmm0 = mem[0],zero,zero,zero
	movq	%r8, %r10
	xorl	%r11d, %r11d
.LBB2_3:                                #   Parent Loop BB2_1 Depth=1
                                        #     Parent Loop BB2_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rdi,%r11,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r10), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rcx,%r9,4)
	incq	%r11
	addq	$1600, %r10                     # imm = 0x640
	cmpq	$400, %r11                      # imm = 0x190
	jne	.LBB2_3
# %bb.4:                                #   in Loop: Header=BB2_2 Depth=2
	incq	%r9
	addq	$4, %r8
	cmpq	$400, %r9                       # imm = 0x190
	jne	.LBB2_2
# %bb.5:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%rax
	addq	$1600, %rdi                     # imm = 0x640
	cmpq	$400, %rax                      # imm = 0x190
	jne	.LBB2_1
# %bb.6:
	retq
.Lfunc_end2:
	.size	_Z5cpuMMPfS_S_, .Lfunc_end2-_Z5cpuMMPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$640000, %edi                   # imm = 0x9C400
	callq	malloc
	movq	%rax, %r12
	movl	$640000, %edi                   # imm = 0x9C400
	callq	malloc
	movq	%rax, %r15
	movl	$1, %edi
	movl	$640000, %esi                   # imm = 0x9C400
	callq	calloc@PLT
	movq	%rax, %rbx
	movl	$1, %edi
	movl	$640000, %esi                   # imm = 0x9C400
	callq	calloc@PLT
	movq	%rax, %r14
	movl	$0, 20(%rsp)
	xorl	%eax, %eax
	movl	$1600, %ecx                     # imm = 0x640
	movq	%r12, %rdx
	movq	%r15, %rsi
.LBB3_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%edi, %edi
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rax,%rdi), %r8d
	shrl	%r8d
	addl	$200, %r8d
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r8d, %xmm0
	movss	%xmm0, (%rdx,%rdi,4)
	movss	%xmm0, (%rsi,%rdi,4)
	incq	%rdi
	cmpq	$400, %rdi                      # imm = 0x190
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%rax
	addq	%rcx, %rsi
	addq	%rcx, %rdx
	cmpq	$400, %rax                      # imm = 0x190
	jne	.LBB3_1
# %bb.4:
	leaq	24(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r12, %rax
.LBB3_5:                                # %.preheader16.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
                                        #       Child Loop BB3_7 Depth 3
	imulq	$1600, %r13, %rcx               # imm = 0x640
	addq	%rbx, %rcx
	movq	%r15, %rdx
	xorl	%esi, %esi
.LBB3_6:                                # %.preheader.i
                                        #   Parent Loop BB3_5 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_7 Depth 3
	movss	(%rcx,%rsi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movq	%rdx, %rdi
	xorl	%r8d, %r8d
.LBB3_7:                                #   Parent Loop BB3_5 Depth=1
                                        #     Parent Loop BB3_6 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax,%r8,4), %xmm1             # xmm1 = mem[0],zero,zero,zero
	mulss	(%rdi), %xmm1
	addss	%xmm1, %xmm0
	incq	%r8
	addq	$1600, %rdi                     # imm = 0x640
	cmpq	$400, %r8                       # imm = 0x190
	jne	.LBB3_7
# %bb.8:                                #   in Loop: Header=BB3_6 Depth=2
	movss	%xmm0, (%rcx,%rsi,4)
	incq	%rsi
	addq	$4, %rdx
	cmpq	$400, %rsi                      # imm = 0x190
	jne	.LBB3_6
# %bb.9:                                #   in Loop: Header=BB3_5 Depth=1
	incq	%r13
	addq	$1600, %rax                     # imm = 0x640
	cmpq	$400, %r13                      # imm = 0x190
	jne	.LBB3_5
# %bb.10:                               # %_Z5cpuMMPfS_S_.exit
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	20(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	leaq	48(%rsp), %r13
	movl	$640000, %esi                   # imm = 0x9C400
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rbp
	movl	$640000, %esi                   # imm = 0x9C400
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$640000, %esi                   # imm = 0x9C400
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$640000, %edx                   # imm = 0x9C400
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$640000, %edx                   # imm = 0x9C400
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$85899345940, %rdi              # imm = 0x1400000014
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_12
# %bb.11:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	callq	_Z27__device_stub__gpuMM_sharedPfS_S_
.LBB3_12:
	movq	8(%rsp), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	20(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	32(%rsp), %rsi
	movl	$640000, %edx                   # imm = 0x9C400
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.LBB3_13:                               # =>This Inner Loop Header: Depth=1
	movss	(%rbx,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	(%r14,%r15,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	ucomiss	%xmm1, %xmm0
	jne	.LBB3_14
	jp	.LBB3_14
# %bb.15:                               #   in Loop: Header=BB3_13 Depth=1
	incq	%r15
	cmpq	$160000, %r15                   # imm = 0x27100
	jne	.LBB3_13
# %bb.16:
	xorl	%eax, %eax
	jmp	.LBB3_17
.LBB3_14:
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str.2, %edi
	movl	%r15d, %esi
	movb	$2, %al
	callq	printf
	movl	$-1, %eax
.LBB3_17:                               # %.loopexit
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14gpuMM_nosharedPfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12gpuMM_sharedPfS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14gpuMM_nosharedPfS_S_,@object # @_Z14gpuMM_nosharedPfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z14gpuMM_nosharedPfS_S_
	.p2align	3, 0x0
_Z14gpuMM_nosharedPfS_S_:
	.quad	_Z29__device_stub__gpuMM_nosharedPfS_S_
	.size	_Z14gpuMM_nosharedPfS_S_, 8

	.type	_Z12gpuMM_sharedPfS_S_,@object  # @_Z12gpuMM_sharedPfS_S_
	.globl	_Z12gpuMM_sharedPfS_S_
	.p2align	3, 0x0
_Z12gpuMM_sharedPfS_S_:
	.quad	_Z27__device_stub__gpuMM_sharedPfS_S_
	.size	_Z12gpuMM_sharedPfS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Running on CPU, time elapsed...%lf\n"
	.size	.L.str, 36

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Running on GPU(noshared), time elapsed...%lf\n"
	.size	.L.str.1, 46

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error, CPU(%lf) != GPU(%lf) at index %d\n"
	.size	.L.str.2, 41

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14gpuMM_nosharedPfS_S_"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12gpuMM_sharedPfS_S_"
	.size	.L__unnamed_2, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__gpuMM_nosharedPfS_S_
	.addrsig_sym _Z27__device_stub__gpuMM_sharedPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14gpuMM_nosharedPfS_S_
	.addrsig_sym _Z12gpuMM_sharedPfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14gpuMM_nosharedPfS_S_ ; -- Begin function _Z14gpuMM_nosharedPfS_S_
	.globl	_Z14gpuMM_nosharedPfS_S_
	.p2align	8
	.type	_Z14gpuMM_nosharedPfS_S_,@function
_Z14gpuMM_nosharedPfS_S_:               ; @_Z14gpuMM_nosharedPfS_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
	v_mul_lo_u32 v5, 0x190, v2
	s_load_b64 s[2:3], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v5, v0
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_load_b128 s[0:3], s[0:1], 0x0
	global_load_b32 v4, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, s0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 2, v[0:1]
	v_add_nc_u32_e32 v0, 0x190, v0
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x640
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	global_load_b32 v1, v[7:8], off
	global_load_b32 v7, v[9:10], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v1, v7
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14gpuMM_nosharedPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14gpuMM_nosharedPfS_S_, .Lfunc_end0-_Z14gpuMM_nosharedPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12gpuMM_sharedPfS_S_  ; -- Begin function _Z12gpuMM_sharedPfS_S_
	.globl	_Z12gpuMM_sharedPfS_S_
	.p2align	8
	.type	_Z12gpuMM_sharedPfS_S_,@function
_Z12gpuMM_sharedPfS_S_:                 ; @_Z12gpuMM_sharedPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s14, s2, v[1:2]
	v_bfe_u32 v5, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[5:6]
	v_mul_lo_u32 v6, 0x190, v4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v8, 2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, 0x640, v8
	v_add_nc_u32_e32 v3, v6, v2
	v_add_nc_u32_e32 v10, v6, v5
	v_mov_b32_e32 v6, 0
	v_mul_u32_u24_e32 v7, 0x50, v1
	v_mad_u32_u24 v8, 0x50, v1, v8
	v_ashrrev_i32_e32 v4, 31, v3
	v_mad_u32_u24 v9, 0x50, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s4, 0
.LBB1_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s4, 20
	v_add_nc_u32_e32 v13, s5, v1
	v_add_nc_u32_e32 v5, s5, v10
	s_mov_b32 s5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, 0x190, v13, v[2:3]
	v_mov_b32_e32 v12, v6
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v13, vcc_lo, s0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	global_load_b32 v5, v[13:14], off
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v8, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_b32 v5, v[3:4], off
	v_mov_b32_e32 v11, v0
.LBB1_2:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s5, v7
	s_add_i32 s5, s5, 4
	ds_load_b32 v13, v11
	ds_load_b32 v12, v12
	v_add_nc_u32_e32 v11, 0x50, v11
	s_cmpk_eq_i32 s5, 0x50
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v5, v12, v13
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s4, s4, 1
	global_store_b32 v[3:4], v5, off
	s_cmp_eq_u32 s4, 20
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_1
; %bb.4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12gpuMM_sharedPfS_S_
		.amdhsa_group_segment_fixed_size 3200
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12gpuMM_sharedPfS_S_, .Lfunc_end1-_Z12gpuMM_sharedPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3200 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14gpuMM_nosharedPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14gpuMM_nosharedPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 3200
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12gpuMM_sharedPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12gpuMM_sharedPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
