// X  = H , y = W
#include<iostream>
#include<stdio.h>
#include<cuda.h>
#include<ctime>
#include<cstdlib>
#include<cuda_profiler_api.h>
using namespace std;











// serially intializing tensor of the image
void tensor_init(int * image, int N, int H, int W, int C){
    /*
        Initialise the tensor for the convolution operation.
        Runs on the CPU
        N : Batch Size of the image
        H : Height of the image
        W : Width of the image
        C : channels for the kernels
    */
    srand(time(0));
    int tot =  N*H*W*C;
    for(int i = 0; i< tot;i++){
        image[i] = rand()%256; //random initializing of the image tensor// for simulating it as an image
    }
}





//serially intialising the kernel with given dimensions
void kernel_init(int *krnl, int d, int h,  int w,int c){
    /*
        Initialise the kernel(s) for the convolution operation.
        Runs on the CPU
        d : Number of kernel
        h : Height of the kernel
        w : Width of the kernel
        c : channels for the kernels
    */
    int tot = d*h*w*c;
    for(int i = 0; i< tot;i++){
        if(i%2 ==0){
            krnl[i] = rand()%10; 
        }
        else{   
            krnl[i] = -rand()%10;
            //random initializing of the image tensor
        // cout<<krnl[i]<<endl;
        }
    }
}








// intialising the mask for checking sparsity of the block 
void mask_init(int *mask,int N,int H,int W,int sparsity_perc){
    /*
        Initialise the tensor for the convolution operation.
        Runs on the CPU
        N : Batch Size of the image
        H : Height of the image
        W : Width of the image
    */
    int tot = N*H*W;
    for(int i = 0; i< tot;i++){
        if(rand()%100<=sparsity_perc){
            mask[i] = 0;
        }
        else{
            mask[i] = 1;
        }  //random initializing of the image tensor
    // cout<<mask[i]<<endl;
    }
    
}




// ************************ device kernels **************** to be optimizzed ***************************************
__device__ bool checksparse(int *d_mask,int cx,int cy,int H, int W, int C,int h,int w,int S,int n){// may be i can have some more conditions
    /*
        device function to check for sparsity

        (device int *) d_mask : pointer to the mask of the image
        (int) n: number of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) c_x: x coordinate of the center
        (int) c_y: y coordinate of the center
    
    */
    int x = 0;
    int y = 0;
    for( int l=-(h-1)/2; l <= (h-1)/2; l++ ){
        for( int p=-(w-1)/2; p <= (w-1)/2; p++ ){
            x = cx + l;
            y = cy + p;
            if( d_mask[n*H*W  + W*y  +  x ] == 1 ){
                return false;
            }
        }
    }
    return true;
}






__global__ void gather(int *d_mask, int *d_tensor, int *d_mat,unsigned int *row_address, int * d_row_map, int N , int H , int W , int h, int w, int C , int S ){ 
    /*
        Gather kernel from the paper to check for sparse and non sparse parts of image for convolution

        (device int *) d_mask : pointer to the mask of the image
        (device int *) d_tensor :  pointer to the tensor containing the all the images
        (device int *) d_mat : pointer with memmory alloc to store every non sparse part of thhe images
        (device int *) row_address : pointer to single integer containing the number of non sparse part of the image
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        
    */



    int id2 = blockIdx.x*blockDim.x + threadIdx.x;
    int in = blockIdx.y;
    int x_dim = id2%W;// along the height of the image
    int y_dim = id2/W;// along the length oh the image
    if(x_dim > 0 && x_dim/S + h < H/S){// condition considering s = 1 for now
        if(y_dim > 0 && y_dim/S +w < W/S){
            int cen_x =  x_dim + (h-1)/2;
            int cen_y =  y_dim + (w-1)/2;
            // printf("%d,%d,%d\n",checksparse(d_mask,x_dim,y_dim,H,W,C,h,w,S,in),cen_x,cen_y); 
            if(!checksparse(d_mask,x_dim,y_dim,H,W,C,h,w,S,in)){
                unsigned   int val = atomicInc(row_address,1000000);
                int col_index = 0;
                for( int l=-(h-1)/2; l <= (h-1)/2; l++ ){
                    for( int p=-(w-1)/2; p <= (w-1)/2; p++ ){
                        for( int q=0; q < C; q++){
                            d_mat[val*h*w*C+col_index] = d_mask[in*(H/S)*(W/S)+((int)((cen_x+l)/S))*(W/S)+((int)((cen_y+p)/S))]?d_tensor[in*H*W*C+(cen_x+l)*W*C+(cen_y+p)*C+q]:0;
                            col_index += 1;
                        }
                    }
                }
                d_row_map[val*3+0] = x_dim; /* Store the original x-coordinate corresponding to a row into a map */
                d_row_map[val*3+1] = y_dim; /* Store the original y-coordinate corresponding to a row into a map */
                d_row_map[val*3+2] = in; /* Store the image corresponding to a row in a map */
                // printf("%d\n",val);
            }
        }
    }
}










__global__ void convolution(int *d_mat,int *d_kernel,unsigned int *number_rows ,int d,int *output_mat,int h,int w,int C){
    /*
        The most basic implementation of the cuda kernel;
        (int *)d_mat : pointer to the conovoluted results for all the non scarse part of the original image
        (int *)d_kernel  : kernel for the coonvoltion(d kernels)
        (int *)output_mat :  pointer for finally storing the output of the matrix
        (unsigned int):  int containing the number of non sparse convolution block
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) d : number of kernels
    
    */
    int t_idx = blockDim.x*blockIdx.x + threadIdx.x;// for the number of the element being changed
    int t_idy = blockDim.y*blockIdx.y + threadIdx.y;// for the number of kernels
    output_mat[t_idx*d + t_idy] = 0;
    int offset = h*w*C;
    if(t_idx < *number_rows && t_idy < d){
        // now the convolution part
        for(int i = 0; i < h*w*C; i++ ){
            output_mat[t_idx*d + t_idy] += d_kernel[t_idy*h*w  + i]*d_mat[offset*t_idx + i]; 
            // printf("%d,%d,\n",d_kernel[t_idy*d +i],d_mat[offset*t_idx + i]);
        }
        // printf("%d,%d,%d\n",t_idx,t_idy,output_mat[t_idx*d + t_idy]);
    }
    
}







__global__ void scatter(int *output_mat, int *d_row_map, unsigned int *number_rows, int *output,int H,int W,int d,int h,int w){
    /*
        Putting the peices back together in the final image(restoring the final output part of the kernel
        (int *)output_mat : pointer to the conovoluted results for all the non scarse part of the original image
        (int *)d_row_map  : pointer to the center positions non sparse part of the image
        (int *)output :  pointer to the final image after convolutions
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) d : number of kernels
    
    */
    int image_size = (H - h + 1)*(W-w+1);
    // image size after the convolution happens
    int t_idx = blockIdx.x*blockDim.x + threadIdx.x;// The number of convs in the output matrux
    int t_idy = blockDim.y*blockIdx.y + threadIdx.y;// The number of output kernels
    // printf("%d,%d,%d \n",t_idx,t_idy, 0);
    if(t_idx<*number_rows && t_idy <d){
        int c_x = d_row_map[t_idx*3] - (h-1)/2; // convert the center to convoluted positions
        int c_y = d_row_map[t_idx*3 + 1] - (w-1)/2;
        int N = d_row_map[t_idx*3 + 2];
        output[N*(image_size*d) + t_idy*(image_size) + W*(c_y) + c_x] =  output_mat[t_idx*d + t_idy ];
        //printf("%d,%d,%d\n",output[N*(image_size*d) + t_idy*(image_size) + W*(c_y) + c_x],output_mat[t_idx*d + t_idy ],N*(image_size*d) + t_idy*(image_size) + W*(c_y) + c_x);
    }

}












int main(){
    // taking input of the image(tensor) dimnsions
    int BLOCK_SIZE = 32;
    int N,H,W,C;
    /*
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
    */
    cout<<"Gimme Image Block Dimensions"<<endl;
    N = 4;
    H = 256;
    W = 256;
    C  = 3;
    
    int *tensor = (int *)malloc(N*H*W*C*sizeof(int));
    
    tensor_init(tensor,N,H,W,C);
    
    int h,w,d;
    /*
    
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) d : number of kernels

    */
    int c = C; 
    cout<<"Gimme krnl Block Dimension"<<endl;
    d = 16;
    h = 4;
    w = 4;

    int *kernel = (int *)malloc(sizeof(int)*h*w*c*d);
    kernel_init(kernel,d,h,w,C);
    // space for d kernels

    int per_sp;

    cout<<"Gimme Percent Sparcity of the block"<<endl;

    per_sp =70;

    int S = 1;// assuming the mask dimension to be 1 for now
    int *mask = (int * )malloc(sizeof(int)*N*H*W*C);
    mask_init(mask,N,H,W,per_sp);

    int num_images = 2;
    int n_streams = N/2;


    // memory allocation for tensor kernel and the mask on the device
    int *d_tensor; 
    int *d_kernel; 
    int *d_mask;
    cudaMalloc(&d_tensor,sizeof(int)*N*H*W*C);// 4-D tensor containing images for the convolution operation
    cudaMalloc(&d_kernel,sizeof(int)*d*h*w*c);// for the kernels to stored in the matrix
    cudaMalloc(&d_mask,sizeof(int)*N*H*W); //mask for checking the sparsity of blocks for the kernel 

    // memory copying to the device
    cudaMemcpy( d_kernel, kernel, sizeof(int)*d*h*w*c, cudaMemcpyHostToDevice );
    cudaMemcpy( d_mask, mask, sizeof(int)*N*H*W, cudaMemcpyHostToDevice );
    cudaMemcpy( d_tensor, tensor, sizeof(int)*N*H*W*C, cudaMemcpyHostToDevice );



    // gatther kernel to fill on the device
    int * d_mat;//
    int * d_row_map; 
    unsigned int *row_address;  
    
    cudaMalloc(&d_mat,sizeof(int)*h*w*C*(H-h+1)*(W-w+1)*N); //  considering that all the parts will be in the imsge
    cudaMalloc(&row_address,n_streams*sizeof( unsigned int));
    
    cudaMemset(&row_address, 0, n_streams*sizeof(unsigned int) );
    cudaMalloc(&d_row_map,sizeof(int)*(H-h+1)*(W-w+1)*N*3);
    // create streams:
    // it can roughly handle about 1000 images at once
    cudaStream_t streams[1000]; /* Declaring a set of CUDA streams */
    for( int i=0; i<n_streams; i++ ) cudaStreamCreate(&streams[i]); /* Initializing a set of streams to work on a set of each image */



    // creating memory for the intermediate kernels
    int * output_mat; /// for the putput of the gather kernel
    cudaMalloc(&output_mat,sizeof(int)*(H-h+1)*(W-w+1)*d*N); 


    // final output matrix we all know its dimensionb already
    int * output;
    cudaMalloc(&output,sizeof(int)*N*(H-h+1)*(W-w+1)*d);




    // profiling features          -----------------------
    cudaEvent_t     start,stop; /* CUDA events to time the program */

    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    cudaEventRecord(start);

    

    // blocks and threads for diffrent kernel plaunches -----------


    // for the gather kernle
    dim3 Block(H*W/BLOCK_SIZE,num_images,1);
    dim3 Thread(BLOCK_SIZE,1,1);
    
    //convolution kernel
    dim3 Block_c(((H-h+1)*(W-w+1)*num_images)/BLOCK_SIZE,d,1);
    
    dim3 Thread_c(BLOCK_SIZE,1,1);




    // offset for diffrent arrays -------------
    int offset;   // tensor fooffset
    int mask_offset; // mask offset
    int mat_offset; // d_mat offsaet
    int map_offset; // d_row_map offset
    int o_offset; //output_mat offset
    int om_offset; // output offset
    unsigned int *number_rows = (unsigned int *)malloc(sizeof(int)*n_streams );


    // Allocating memory for the output tensor
    int * h_output = (int *)malloc(sizeof(int)*N*(H-h+1)*(W-w+1)*d);


    //scatter kernel --- 
    
    
    dim3 Block_s(((H-h+1)*(W-w+1)*num_images)/BLOCK_SIZE,d,1);
    dim3 Thread_s(BLOCK_SIZE,1,1);

    //lanching the diffrent streams
    for(int j=0; j<n_streams; j++){

        /* Initialize a set of off-sets for each stream */
        offset = j*H*W*C*num_images; // tensor offset will be needed
        mask_offset = j*(H)*(W)*num_images; /// mask offset will be needed
        mat_offset = h*w*C*(H-h+1)*(W-w+1)*j*num_images;//matrix offset for the value to be in the matrix
        map_offset = 3*(H-h+1)*(W-w+1)*j*num_images;//offset for d_row_map
        o_offset = (H-h+1)*(W-w+1)*d*j*num_images;//offset for convolution output
        om_offset = d*(H-h+1)*(W-w+1)*j*num_images;//final output offset


        // now the kernels.............. 
        // gether kernel
        gather<<<Block, Thread, 0, streams[j]>>>(&d_mask[mask_offset], &d_tensor[offset], &d_mat[mat_offset],&row_address[j], &d_row_map[map_offset],N , H , W , h, w, C , S);
        // cudaMemcpyAsync(&number_rows[j], &row_address[j], sizeof(unsigned int), cudaMemcpyDeviceToHost,streams[j]);
        //convolution kernel
        convolution<<<Block_c, Thread_c,0, streams[j]>>>(&d_mat[mat_offset], d_kernel, &row_address[j], d, &output_mat[om_offset],h,w,C);
        // cout<<"kernel went through"<<endl;

        // convert the kernel back to its original form
        scatter<<<Block_s,Thread_s, 0 , streams[j]>>>(&output_mat[om_offset], &d_row_map[map_offset], &row_address[j], &output[o_offset],H, W, d, h, w);
        
        
    }
    cudaMemcpy(h_output,output,sizeof(int)*(H-h+1)*(W-w+1)*d*N,cudaMemcpyDeviceToHost);

    cudaEventRecord(stop);
    cudaEventSynchronize(stop);
    float   run_time = 0.0;
    cudaEventElapsedTime(&run_time,start,stop);
    cout<<run_time<<endl;
    
    
    // for(int k = 0;k<N;k++){
    //     for(int p = 0; p<d;p++){
    //         cout<<"image"<<" "<<k<<" "<<"kernel"<<" "<<p<<endl;
    //         for(int i = 0; i<(H-h+1);i++){
    //             for(int j = 0; j<(W-w+1);j++){
    //                 cout<<h_output[k*(H-h+1)*(W-w+1)*d + p*(H-h+1)*(W-w+1) + i*(W-w+1)+ j ]<<" ";
    //             }
    //             cout<<endl;
    //         }    
    //         cout<<endl;
    //     }
    //     cout<<endl;
    // }



    // Destroying all the streams in rthe 
    for( int i=0; i<n_streams; i++ ) cudaStreamDestroy(streams[i]);
    return 0;

}
	.file	"tmpxft_0037f948_00000000-6_streams.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0:
.LFB4303:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE4303:
	.size	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	.globl	_Z11tensor_initPiiiii
	.type	_Z11tensor_initPiiiii, @function
_Z11tensor_initPiiiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%ecx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	imull	%ebp, %ebx
	xorl	%ebp, %ebp
	call	time@PLT
	imull	%r14d, %ebx
	movl	%eax, %edi
	call	srand@PLT
	imull	%r13d, %ebx
	movl	$256, %r13d
.L4:
	cmpl	%ebp, %ebx
	jle	.L8
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L4
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z11tensor_initPiiiii, .-_Z11tensor_initPiiiii
	.globl	_Z11kernel_initPiiiii
	.type	_Z11kernel_initPiiiii, @function
_Z11kernel_initPiiiii:
.LFB3636:
	.cfi_startproc
	endbr64
	imull	%edx, %esi
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$10, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xorl	%ebp, %ebp
	imull	%ecx, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	pushq	%r9
	.cfi_def_cfa_offset 48
	movl	%esi, %ebx
	imull	%r8d, %ebx
.L10:
	cmpl	%ebp, %ebx
	jle	.L16
	testl	$1, %ebp
	jne	.L11
	call	rand@PLT
	jmp	.L15
.L11:
	call	rand@PLT
	negl	%eax
.L15:
	cltd
	idivl	%r12d
	movl	%edx, 0(%r13,%rbp,4)
	incq	%rbp
	jmp	.L10
.L16:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z11kernel_initPiiiii, .-_Z11kernel_initPiiiii
	.globl	_Z9mask_initPiiiii
	.type	_Z9mask_initPiiiii, @function
_Z9mask_initPiiiii:
.LFB3637:
	.cfi_startproc
	endbr64
	imull	%edx, %esi
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$100, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%esi, %ebx
	imull	%ecx, %ebx
.L18:
	cmpl	%ebp, %ebx
	jle	.L21
	call	rand@PLT
	cltd
	idivl	%r14d
	xorl	%eax, %eax
	cmpl	%r13d, %edx
	setg	%al
	movl	%eax, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L18
.L21:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z9mask_initPiiiii, .-_Z9mask_initPiiiii
	.globl	_Z11checksparsePiiiiiiiiii
	.type	_Z11checksparsePiiiiiiiiii, @function
_Z11checksparsePiiiiiiiiii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3638:
	.size	_Z11checksparsePiiiiiiiiii, .-_Z11checksparsePiiiiiiiiii
	.globl	_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii
	.type	_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii, @function
_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z6gatherPiS_S_PjS_iiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L24:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii, .-_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii
	.globl	_Z6gatherPiS_S_PjS_iiiiiii
	.type	_Z6gatherPiS_S_PjS_iiiiiii, @function
_Z6gatherPiS_S_PjS_iiiiiii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii
	.cfi_endproc
.LFE3665:
	.size	_Z6gatherPiS_S_PjS_iiiiiii, .-_Z6gatherPiS_S_PjS_iiiiiii
	.globl	_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii
	.type	_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii, @function
_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11convolutionPiS_PjiS_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L29:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii, .-_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii
	.globl	_Z11convolutionPiS_PjiS_iii
	.type	_Z11convolutionPiS_PjiS_iii, @function
_Z11convolutionPiS_PjiS_iii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii
	.cfi_endproc
.LFE3667:
	.size	_Z11convolutionPiS_PjiS_iii, .-_Z11convolutionPiS_PjiS_iii
	.globl	_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii
	.type	_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii, @function
_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii:
.LFB3668:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z7scatterPiS_PjS_iiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L34:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii, .-_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii
	.globl	_Z7scatterPiS_PjS_iiiii
	.type	_Z7scatterPiS_PjS_iiiii, @function
_Z7scatterPiS_PjS_iiiii:
.LFB3669:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii
	.cfi_endproc
.LFE3669:
	.size	_Z7scatterPiS_PjS_iiiii, .-_Z7scatterPiS_PjS_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Gimme Image Block Dimensions"
.LC1:
	.string	"Gimme krnl Block Dimension"
.LC2:
	.string	"Gimme Percent Sparcity of the block"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$4096, %rsp
	.cfi_def_cfa_offset 4144
	orq	$0, (%rsp)
	subq	$4080, %rsp
	.cfi_def_cfa_offset 8224
	leaq	_ZSt4cout(%rip), %r12
	leaq	.LC0(%rip), %rsi
	movq	%r12, %rdi
	movq	%fs:40, %rax
	movq	%rax, 8168(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$3145728, %edi
	call	malloc@PLT
	movl	$3, %r8d
	movl	$256, %ecx
	movl	$256, %edx
	movq	%rax, %rdi
	movl	$4, %esi
	movq	%rax, %rbx
	call	_Z11tensor_initPiiiii
	leaq	.LC1(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$3072, %edi
	call	malloc@PLT
	movl	$3, %r8d
	movl	$4, %ecx
	movl	$4, %edx
	movq	%rax, %rdi
	movl	$16, %esi
	movq	%rax, %r13
	call	_Z11kernel_initPiiiii
	leaq	.LC2(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$3145728, %edi
	call	malloc@PLT
	movl	$70, %r8d
	movl	$256, %ecx
	movl	$256, %edx
	movq	%rax, %rdi
	movl	$4, %esi
	movq	%rax, %rbp
	call	_Z9mask_initPiiiii
	leaq	16(%rsp), %rdi
	movl	$3145728, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	24(%rsp), %rdi
	movl	$3072, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	32(%rsp), %rdi
	movl	$1048576, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	24(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	movl	$3072, %edx
	leaq	168(%rsp), %r13
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$1048576, %edx
	movl	$2147483773, %ebp
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$3145728, %edx
	leaq	56(%rsp), %rbx
	call	cudaMemcpy@PLT
	leaq	40(%rsp), %rdi
	movl	$49158912, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	%rbx, %rdi
	movl	$8, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	$8, %edx
	xorl	%esi, %esi
	movq	%rbx, %rdi
	call	cudaMemset@PLT
	movl	$3072432, %esi
	leaq	48(%rsp), %rdi
	movl	$134217729, %ebx
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	%r13, %rdi
	call	cudaStreamCreate@PLT
	leaq	176(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	64(%rsp), %rdi
	movl	$16386304, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	$16386304, %esi
	leaq	72(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4194305, %eax
	movl	$16386304, %edi
	movl	$1, 104(%rsp)
	salq	$11, %rax
	salq	$5, %rbx
	movl	$1, 116(%rsp)
	salq	$5, %rbp
	movq	%rbx, 108(%rsp)
	movq	%rbp, 120(%rsp)
	movq	%rbx, 132(%rsp)
	movq	%rax, 96(%rsp)
	movl	$1, 128(%rsp)
	movl	$1, 140(%rsp)
	call	malloc@PLT
	movq	%rbp, 144(%rsp)
	xorl	%ebp, %ebp
	movl	$1, 152(%rsp)
	movq	%rax, %r14
	movl	$1, 164(%rsp)
	movq	%rbx, 156(%rsp)
	xorl	%ebx, %ebx
.L43:
	movl	116(%rsp), %ecx
	movq	0(%r13,%rbx,2), %r9
	xorl	%r8d, %r8d
	movq	108(%rsp), %rdx
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	%rbx, %rdi
	movq	56(%rsp), %rcx
	imulq	$6144864, %rbx, %rdx
	addq	40(%rsp), %rdx
	imulq	$393216, %rbx, %rsi
	salq	$17, %rdi
	addq	16(%rsp), %rsi
	addq	32(%rsp), %rdi
	pushq	$1
	.cfi_def_cfa_offset 8232
	imulq	$384054, %rbx, %r8
	addq	%rbx, %rcx
	movl	$4, %r9d
	pushq	$3
	.cfi_def_cfa_offset 8240
	pushq	$4
	.cfi_def_cfa_offset 8248
	pushq	$4
	.cfi_def_cfa_offset 8256
	pushq	$256
	.cfi_def_cfa_offset 8264
	pushq	$256
	.cfi_def_cfa_offset 8272
	addq	96(%rsp), %r8
	call	_Z40__device_stub__Z6gatherPiS_S_PjS_iiiiiiiPiS_S_PjS_iiiiiii
	addq	$48, %rsp
	.cfi_def_cfa_offset 8224
.L40:
	movl	140(%rsp), %ecx
	movq	0(%r13,%rbx,2), %r9
	xorl	%r8d, %r8d
	movq	132(%rsp), %rdx
	movq	120(%rsp), %rdi
	movl	128(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	movq	56(%rsp), %rdx
	imulq	$6144864, %rbx, %rdi
	addq	40(%rsp), %rdi
	pushq	$3
	.cfi_def_cfa_offset 8232
	pushq	$4
	.cfi_def_cfa_offset 8240
	movq	80(%rsp), %r8
	movl	$16, %ecx
	movl	$4, %r9d
	movq	40(%rsp), %rsi
	addq	%rbx, %rdx
	addq	%rbp, %r8
	call	_Z41__device_stub__Z11convolutionPiS_PjiS_iiiPiS_PjiS_iii
	popq	%rdx
	.cfi_def_cfa_offset 8232
	popq	%rcx
	.cfi_def_cfa_offset 8224
.L41:
	movl	164(%rsp), %ecx
	movq	0(%r13,%rbx,2), %r9
	xorl	%r8d, %r8d
	movq	156(%rsp), %rdx
	movq	144(%rsp), %rdi
	movl	152(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	72(%rsp), %rcx
	movq	56(%rsp), %rdx
	imulq	$384054, %rbx, %rsi
	movl	$256, %r9d
	movq	64(%rsp), %rdi
	addq	48(%rsp), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 8232
	movl	$256, %r8d
	pushq	$4
	.cfi_def_cfa_offset 8240
	addq	%rbp, %rcx
	addq	%rbx, %rdx
	pushq	$4
	.cfi_def_cfa_offset 8248
	addq	%rbp, %rdi
	pushq	$16
	.cfi_def_cfa_offset 8256
	call	_Z37__device_stub__Z7scatterPiS_PjS_iiiiiPiS_PjS_iiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 8224
.L42:
	addq	$4, %rbx
	addq	$8193152, %rbp
	cmpq	$8, %rbx
	jne	.L43
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movl	$16386304, %edx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	leaq	12(%rsp), %rdi
	movl	$0x00000000, 12(%rsp)
	call	cudaEventElapsedTime@PLT
	movq	%r12, %rdi
	cvtss2sd	12(%rsp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	168(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	176(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	8168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	addq	$8176, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z7scatterPiS_PjS_iiiii"
.LC5:
	.string	"_Z11convolutionPiS_PjiS_iii"
.LC6:
	.string	"_Z6gatherPiS_S_PjS_iiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3671:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7scatterPiS_PjS_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11convolutionPiS_PjiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6gatherPiS_S_PjS_iiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3671:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// X  = H , y = W
#include<iostream>
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<ctime>
#include<cstdlib>
#include<hip/hip_runtime_api.h>
using namespace std;











// serially intializing tensor of the image
void tensor_init(int * image, int N, int H, int W, int C){
    /*
        Initialise the tensor for the convolution operation.
        Runs on the CPU
        N : Batch Size of the image
        H : Height of the image
        W : Width of the image
        C : channels for the kernels
    */
    srand(time(0));
    int tot =  N*H*W*C;
    for(int i = 0; i< tot;i++){
        image[i] = rand()%256; //random initializing of the image tensor// for simulating it as an image
    }
}





//serially intialising the kernel with given dimensions
void kernel_init(int *krnl, int d, int h,  int w,int c){
    /*
        Initialise the kernel(s) for the convolution operation.
        Runs on the CPU
        d : Number of kernel
        h : Height of the kernel
        w : Width of the kernel
        c : channels for the kernels
    */
    int tot = d*h*w*c;
    for(int i = 0; i< tot;i++){
        if(i%2 ==0){
            krnl[i] = rand()%10; 
        }
        else{   
            krnl[i] = -rand()%10;
            //random initializing of the image tensor
        // cout<<krnl[i]<<endl;
        }
    }
}








// intialising the mask for checking sparsity of the block 
void mask_init(int *mask,int N,int H,int W,int sparsity_perc){
    /*
        Initialise the tensor for the convolution operation.
        Runs on the CPU
        N : Batch Size of the image
        H : Height of the image
        W : Width of the image
    */
    int tot = N*H*W;
    for(int i = 0; i< tot;i++){
        if(rand()%100<=sparsity_perc){
            mask[i] = 0;
        }
        else{
            mask[i] = 1;
        }  //random initializing of the image tensor
    // cout<<mask[i]<<endl;
    }
    
}




// ************************ device kernels **************** to be optimizzed ***************************************
__device__ bool checksparse(int *d_mask,int cx,int cy,int H, int W, int C,int h,int w,int S,int n){// may be i can have some more conditions
    /*
        device function to check for sparsity

        (device int *) d_mask : pointer to the mask of the image
        (int) n: number of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) c_x: x coordinate of the center
        (int) c_y: y coordinate of the center
    
    */
    int x = 0;
    int y = 0;
    for( int l=-(h-1)/2; l <= (h-1)/2; l++ ){
        for( int p=-(w-1)/2; p <= (w-1)/2; p++ ){
            x = cx + l;
            y = cy + p;
            if( d_mask[n*H*W  + W*y  +  x ] == 1 ){
                return false;
            }
        }
    }
    return true;
}






__global__ void gather(int *d_mask, int *d_tensor, int *d_mat,unsigned int *row_address, int * d_row_map, int N , int H , int W , int h, int w, int C , int S ){ 
    /*
        Gather kernel from the paper to check for sparse and non sparse parts of image for convolution

        (device int *) d_mask : pointer to the mask of the image
        (device int *) d_tensor :  pointer to the tensor containing the all the images
        (device int *) d_mat : pointer with memmory alloc to store every non sparse part of thhe images
        (device int *) row_address : pointer to single integer containing the number of non sparse part of the image
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        
    */



    int id2 = blockIdx.x*blockDim.x + threadIdx.x;
    int in = blockIdx.y;
    int x_dim = id2%W;// along the height of the image
    int y_dim = id2/W;// along the length oh the image
    if(x_dim > 0 && x_dim/S + h < H/S){// condition considering s = 1 for now
        if(y_dim > 0 && y_dim/S +w < W/S){
            int cen_x =  x_dim + (h-1)/2;
            int cen_y =  y_dim + (w-1)/2;
            // printf("%d,%d,%d\n",checksparse(d_mask,x_dim,y_dim,H,W,C,h,w,S,in),cen_x,cen_y); 
            if(!checksparse(d_mask,x_dim,y_dim,H,W,C,h,w,S,in)){
                unsigned   int val = atomicInc(row_address,1000000);
                int col_index = 0;
                for( int l=-(h-1)/2; l <= (h-1)/2; l++ ){
                    for( int p=-(w-1)/2; p <= (w-1)/2; p++ ){
                        for( int q=0; q < C; q++){
                            d_mat[val*h*w*C+col_index] = d_mask[in*(H/S)*(W/S)+((int)((cen_x+l)/S))*(W/S)+((int)((cen_y+p)/S))]?d_tensor[in*H*W*C+(cen_x+l)*W*C+(cen_y+p)*C+q]:0;
                            col_index += 1;
                        }
                    }
                }
                d_row_map[val*3+0] = x_dim; /* Store the original x-coordinate corresponding to a row into a map */
                d_row_map[val*3+1] = y_dim; /* Store the original y-coordinate corresponding to a row into a map */
                d_row_map[val*3+2] = in; /* Store the image corresponding to a row in a map */
                // printf("%d\n",val);
            }
        }
    }
}










__global__ void convolution(int *d_mat,int *d_kernel,unsigned int *number_rows ,int d,int *output_mat,int h,int w,int C){
    /*
        The most basic implementation of the cuda kernel;
        (int *)d_mat : pointer to the conovoluted results for all the non scarse part of the original image
        (int *)d_kernel  : kernel for the coonvoltion(d kernels)
        (int *)output_mat :  pointer for finally storing the output of the matrix
        (unsigned int):  int containing the number of non sparse convolution block
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) d : number of kernels
    
    */
    int t_idx = blockDim.x*blockIdx.x + threadIdx.x;// for the number of the element being changed
    int t_idy = blockDim.y*blockIdx.y + threadIdx.y;// for the number of kernels
    output_mat[t_idx*d + t_idy] = 0;
    int offset = h*w*C;
    if(t_idx < *number_rows && t_idy < d){
        // now the convolution part
        for(int i = 0; i < h*w*C; i++ ){
            output_mat[t_idx*d + t_idy] += d_kernel[t_idy*h*w  + i]*d_mat[offset*t_idx + i]; 
            // printf("%d,%d,\n",d_kernel[t_idy*d +i],d_mat[offset*t_idx + i]);
        }
        // printf("%d,%d,%d\n",t_idx,t_idy,output_mat[t_idx*d + t_idy]);
    }
    
}







__global__ void scatter(int *output_mat, int *d_row_map, unsigned int *number_rows, int *output,int H,int W,int d,int h,int w){
    /*
        Putting the peices back together in the final image(restoring the final output part of the kernel
        (int *)output_mat : pointer to the conovoluted results for all the non scarse part of the original image
        (int *)d_row_map  : pointer to the center positions non sparse part of the image
        (int *)output :  pointer to the final image after convolutions
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) d : number of kernels
    
    */
    int image_size = (H - h + 1)*(W-w+1);
    // image size after the convolution happens
    int t_idx = blockIdx.x*blockDim.x + threadIdx.x;// The number of convs in the output matrux
    int t_idy = blockDim.y*blockIdx.y + threadIdx.y;// The number of output kernels
    // printf("%d,%d,%d \n",t_idx,t_idy, 0);
    if(t_idx<*number_rows && t_idy <d){
        int c_x = d_row_map[t_idx*3] - (h-1)/2; // convert the center to convoluted positions
        int c_y = d_row_map[t_idx*3 + 1] - (w-1)/2;
        int N = d_row_map[t_idx*3 + 2];
        output[N*(image_size*d) + t_idy*(image_size) + W*(c_y) + c_x] =  output_mat[t_idx*d + t_idy ];
        //printf("%d,%d,%d\n",output[N*(image_size*d) + t_idy*(image_size) + W*(c_y) + c_x],output_mat[t_idx*d + t_idy ],N*(image_size*d) + t_idy*(image_size) + W*(c_y) + c_x);
    }

}












int main(){
    // taking input of the image(tensor) dimnsions
    int BLOCK_SIZE = 32;
    int N,H,W,C;
    /*
        (int) N: number of the images in the given tensor
        (int) H: Height of the image
        (int) W: Weight of the image
        (int) C: Channels of the image
    */
    cout<<"Gimme Image Block Dimensions"<<endl;
    N = 4;
    H = 256;
    W = 256;
    C  = 3;
    
    int *tensor = (int *)malloc(N*H*W*C*sizeof(int));
    
    tensor_init(tensor,N,H,W,C);
    
    int h,w,d;
    /*
    
        (int) h: height of the kernels
        (int) w: Weight of the kernels
        (int) d : number of kernels

    */
    int c = C; 
    cout<<"Gimme krnl Block Dimension"<<endl;
    d = 16;
    h = 4;
    w = 4;

    int *kernel = (int *)malloc(sizeof(int)*h*w*c*d);
    kernel_init(kernel,d,h,w,C);
    // space for d kernels

    int per_sp;

    cout<<"Gimme Percent Sparcity of the block"<<endl;

    per_sp =70;

    int S = 1;// assuming the mask dimension to be 1 for now
    int *mask = (int * )malloc(sizeof(int)*N*H*W*C);
    mask_init(mask,N,H,W,per_sp);

    int num_images = 2;
    int n_streams = N/2;


    // memory allocation for tensor kernel and the mask on the device
    int *d_tensor; 
    int *d_kernel; 
    int *d_mask;
    hipMalloc(&d_tensor,sizeof(int)*N*H*W*C);// 4-D tensor containing images for the convolution operation
    hipMalloc(&d_kernel,sizeof(int)*d*h*w*c);// for the kernels to stored in the matrix
    hipMalloc(&d_mask,sizeof(int)*N*H*W); //mask for checking the sparsity of blocks for the kernel 

    // memory copying to the device
    hipMemcpy( d_kernel, kernel, sizeof(int)*d*h*w*c, hipMemcpyHostToDevice );
    hipMemcpy( d_mask, mask, sizeof(int)*N*H*W, hipMemcpyHostToDevice );
    hipMemcpy( d_tensor, tensor, sizeof(int)*N*H*W*C, hipMemcpyHostToDevice );



    // gatther kernel to fill on the device
    int * d_mat;//
    int * d_row_map; 
    unsigned int *row_address;  
    
    hipMalloc(&d_mat,sizeof(int)*h*w*C*(H-h+1)*(W-w+1)*N); //  considering that all the parts will be in the imsge
    hipMalloc(&row_address,n_streams*sizeof( unsigned int));
    
    hipMemset(&row_address, 0, n_streams*sizeof(unsigned int) );
    hipMalloc(&d_row_map,sizeof(int)*(H-h+1)*(W-w+1)*N*3);
    // create streams:
    // it can roughly handle about 1000 images at once
    hipStream_t streams[1000]; /* Declaring a set of CUDA streams */
    for( int i=0; i<n_streams; i++ ) hipStreamCreate(&streams[i]); /* Initializing a set of streams to work on a set of each image */



    // creating memory for the intermediate kernels
    int * output_mat; /// for the putput of the gather kernel
    hipMalloc(&output_mat,sizeof(int)*(H-h+1)*(W-w+1)*d*N); 


    // final output matrix we all know its dimensionb already
    int * output;
    hipMalloc(&output,sizeof(int)*N*(H-h+1)*(W-w+1)*d);




    // profiling features          -----------------------
    hipEvent_t     start,stop; /* CUDA events to time the program */

    hipEventCreate(&start);
    hipEventCreate(&stop);

    hipEventRecord(start);

    

    // blocks and threads for diffrent kernel plaunches -----------


    // for the gather kernle
    dim3 Block(H*W/BLOCK_SIZE,num_images,1);
    dim3 Thread(BLOCK_SIZE,1,1);
    
    //convolution kernel
    dim3 Block_c(((H-h+1)*(W-w+1)*num_images)/BLOCK_SIZE,d,1);
    
    dim3 Thread_c(BLOCK_SIZE,1,1);




    // offset for diffrent arrays -------------
    int offset;   // tensor fooffset
    int mask_offset; // mask offset
    int mat_offset; // d_mat offsaet
    int map_offset; // d_row_map offset
    int o_offset; //output_mat offset
    int om_offset; // output offset
    unsigned int *number_rows = (unsigned int *)malloc(sizeof(int)*n_streams );


    // Allocating memory for the output tensor
    int * h_output = (int *)malloc(sizeof(int)*N*(H-h+1)*(W-w+1)*d);


    //scatter kernel --- 
    
    
    dim3 Block_s(((H-h+1)*(W-w+1)*num_images)/BLOCK_SIZE,d,1);
    dim3 Thread_s(BLOCK_SIZE,1,1);

    //lanching the diffrent streams
    for(int j=0; j<n_streams; j++){

        /* Initialize a set of off-sets for each stream */
        offset = j*H*W*C*num_images; // tensor offset will be needed
        mask_offset = j*(H)*(W)*num_images; /// mask offset will be needed
        mat_offset = h*w*C*(H-h+1)*(W-w+1)*j*num_images;//matrix offset for the value to be in the matrix
        map_offset = 3*(H-h+1)*(W-w+1)*j*num_images;//offset for d_row_map
        o_offset = (H-h+1)*(W-w+1)*d*j*num_images;//offset for convolution output
        om_offset = d*(H-h+1)*(W-w+1)*j*num_images;//final output offset


        // now the kernels.............. 
        // gether kernel
        gather<<<Block, Thread, 0, streams[j]>>>(&d_mask[mask_offset], &d_tensor[offset], &d_mat[mat_offset],&row_address[j], &d_row_map[map_offset],N , H , W , h, w, C , S);
        // cudaMemcpyAsync(&number_rows[j], &row_address[j], sizeof(unsigned int), cudaMemcpyDeviceToHost,streams[j]);
        //convolution kernel
        convolution<<<Block_c, Thread_c,0, streams[j]>>>(&d_mat[mat_offset], d_kernel, &row_address[j], d, &output_mat[om_offset],h,w,C);
        // cout<<"kernel went through"<<endl;

        // convert the kernel back to its original form
        scatter<<<Block_s,Thread_s, 0 , streams[j]>>>(&output_mat[om_offset], &d_row_map[map_offset], &row_address[j], &output[o_offset],H, W, d, h, w);
        
        
    }
    hipMemcpy(h_output,output,sizeof(int)*(H-h+1)*(W-w+1)*d*N,hipMemcpyDeviceToHost);

    hipEventRecord(stop);
    hipEventSynchronize(stop);
    float   run_time = 0.0;
    hipEventElapsedTime(&run_time,start,stop);
    cout<<run_time<<endl;
    
    
    // for(int k = 0;k<N;k++){
    //     for(int p = 0; p<d;p++){
    //         cout<<"image"<<" "<<k<<" "<<"kernel"<<" "<<p<<endl;
    //         for(int i = 0; i<(H-h+1);i++){
    //             for(int j = 0; j<(W-w+1);j++){
    //                 cout<<h_output[k*(H-h+1)*(W-w+1)*d + p*(H-h+1)*(W-w+1) + i*(W-w+1)+ j ]<<" ";
    //             }
    //             cout<<endl;
    //         }    
    //         cout<<endl;
    //     }
    //     cout<<endl;
    // }



    // Destroying all the streams in rthe 
    for( int i=0; i<n_streams; i++ ) hipStreamDestroy(streams[i]);
    return 0;

}
	.text
	.file	"streams.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z11tensor_initPiiiii           # -- Begin function _Z11tensor_initPiiiii
	.type	_Z11tensor_initPiiiii,@function
_Z11tensor_initPiiiii:                  # @_Z11tensor_initPiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r14d
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movl	%esi, %r12d
	movq	%rdi, %rbx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	imull	%r15d, %r12d
	imull	%r14d, %ebp
	imull	%r12d, %ebp
	testl	%ebp, %ebp
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	255(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-256, %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z11tensor_initPiiiii, .Lfunc_end0-_Z11tensor_initPiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11kernel_initPiiiii           # -- Begin function _Z11kernel_initPiiiii
	.type	_Z11kernel_initPiiiii,@function
_Z11kernel_initPiiiii:                  # @_Z11kernel_initPiiiii
	.cfi_startproc
# %bb.0:
	imull	%edx, %esi
	imull	%r8d, %ecx
	imull	%esi, %ecx
	testl	%ecx, %ecx
	jle	.LBB1_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%ecx, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, %ecx
	negl	%ecx
	testb	$1, %r15b
	cmovel	%eax, %ecx
	movl	%ecx, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB1_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB1_4:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z11kernel_initPiiiii, .Lfunc_end1-_Z11kernel_initPiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9mask_initPiiiii              # -- Begin function _Z9mask_initPiiiii
	.type	_Z9mask_initPiiiii,@function
_Z9mask_initPiiiii:                     # @_Z9mask_initPiiiii
	.cfi_startproc
# %bb.0:
	imull	%edx, %esi
	imull	%ecx, %esi
	testl	%esi, %esi
	jle	.LBB2_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%r8d, %ebx
	movq	%rdi, %r14
	movl	%esi, %r15d
	xorl	%r12d, %r12d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	xorl	%ecx, %ecx
	cmpl	%ebx, %eax
	setg	%cl
	movl	%ecx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB2_2
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r14
	.cfi_restore %r15
.LBB2_4:                                # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z9mask_initPiiiii, .Lfunc_end2-_Z9mask_initPiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__gatherPiS_S_PjS_iiiiiii # -- Begin function _Z21__device_stub__gatherPiS_S_PjS_iiiiiii
	.type	_Z21__device_stub__gatherPiS_S_PjS_iiiiiii,@function
_Z21__device_stub__gatherPiS_S_PjS_iiiiiii: # @_Z21__device_stub__gatherPiS_S_PjS_iiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6gatherPiS_S_PjS_iiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z21__device_stub__gatherPiS_S_PjS_iiiiiii, .Lfunc_end3-_Z21__device_stub__gatherPiS_S_PjS_iiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convolutionPiS_PjiS_iii # -- Begin function _Z26__device_stub__convolutionPiS_PjiS_iii
	.type	_Z26__device_stub__convolutionPiS_PjiS_iii,@function
_Z26__device_stub__convolutionPiS_PjiS_iii: # @_Z26__device_stub__convolutionPiS_PjiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convolutionPiS_PjiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z26__device_stub__convolutionPiS_PjiS_iii, .Lfunc_end4-_Z26__device_stub__convolutionPiS_PjiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__scatterPiS_PjS_iiiii # -- Begin function _Z22__device_stub__scatterPiS_PjS_iiiii
	.type	_Z22__device_stub__scatterPiS_PjS_iiiii,@function
_Z22__device_stub__scatterPiS_PjS_iiiii: # @_Z22__device_stub__scatterPiS_PjS_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7scatterPiS_PjS_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__scatterPiS_PjS_iiiii, .Lfunc_end5-_Z22__device_stub__scatterPiS_PjS_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$8120, %rsp                     # imm = 0x1FB8
	.cfi_def_cfa_offset 8176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$28, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$3145728, %edi                  # imm = 0x300000
	callq	malloc
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rax, %rdi
	movl	$4, %esi
	movl	$256, %edx                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$3, %r8d
	callq	_Z11tensor_initPiiiii
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$3072, %edi                     # imm = 0xC00
	callq	malloc
	movq	%rax, %r12
	xorl	%ebx, %ebx
.LBB6_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, %ecx
	negl	%ecx
	testb	$1, %bl
	cmovel	%eax, %ecx
	movl	%ecx, (%r12,%rbx,4)
	incq	%rbx
	cmpq	$768, %rbx                      # imm = 0x300
	jne	.LBB6_1
# %bb.2:                                # %_Z11kernel_initPiiiii.exit
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$35, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$3145728, %edi                  # imm = 0x300000
	callq	malloc
	movq	%rax, %r13
	xorl	%ebx, %ebx
.LBB6_3:                                # %.lr.ph.i221
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	xorl	%ecx, %ecx
	cmpl	$71, %eax
	setge	%cl
	movl	%ecx, (%r13,%rbx,4)
	incq	%rbx
	cmpq	$262144, %rbx                   # imm = 0x40000
	jne	.LBB6_3
# %bb.4:                                # %_Z9mask_initPiiiii.exit
	movabsq	$4294967328, %r14               # imm = 0x100000020
	leaq	96(%rsp), %rbx
	movl	$3145728, %esi                  # imm = 0x300000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	88(%rsp), %r15
	movl	$3072, %esi                     # imm = 0xC00
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	80(%rsp), %rbp
	movl	$1048576, %esi                  # imm = 0x100000
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$3072, %edx                     # imm = 0xC00
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movl	$3145728, %edx                  # imm = 0x300000
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rdi
	movl	$49158912, %esi                 # imm = 0x2EE1B00
	callq	hipMalloc
	leaq	24(%rsp), %r12
	movl	$8, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	xorl	%r15d, %r15d
	movl	$8, %edx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	hipMemset
	leaq	48(%rsp), %rdi
	movl	$3072432, %esi                  # imm = 0x2EE1B0
	callq	hipMalloc
	leaq	112(%rsp), %rdi
	callq	hipStreamCreate
	leaq	120(%rsp), %rdi
	callq	hipStreamCreate
	leaq	40(%rsp), %rdi
	movl	$16386304, %esi                 # imm = 0xFA0900
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$16386304, %esi                 # imm = 0xFA0900
	callq	hipMalloc
	leaq	72(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$16386304, %edi                 # imm = 0xFA0900
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movb	$1, %bl
.LBB6_5:                                # =>This Inner Loop Header: Depth=1
	imulq	$6144864, %r15, %r12            # imm = 0x5DC360
	imulq	$384054, %r15, %r13             # imm = 0x5DC36
	movq	112(%rsp,%r15,8), %r9
	movabsq	$8589936640, %rdi               # imm = 0x200000800
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%r14, %rbp
	jne	.LBB6_7
# %bb.6:                                #   in Loop: Header=BB6_5 Depth=1
	movq	%r15, %rdi
	shlq	$19, %rdi
	addq	80(%rsp), %rdi
	leaq	(%r15,%r15,2), %rsi
	shlq	$19, %rsi
	addq	96(%rsp), %rsi
	leaq	(,%r12,4), %rdx
	addq	56(%rsp), %rdx
	leaq	(,%r15,4), %rcx
	addq	24(%rsp), %rcx
	leaq	(,%r13,4), %r8
	addq	48(%rsp), %r8
	movl	$4, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	$3
	.cfi_adjust_cfa_offset 8
	movl	$4, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	$256, %eax                      # imm = 0x100
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z21__device_stub__gatherPiS_S_PjS_iiiiiii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB6_7:                                #   in Loop: Header=BB6_5 Depth=1
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	imulq	$2048288, %r15, %r13            # imm = 0x1F4120
	movq	112(%rsp,%r15,8), %r9
	movabsq	$68719480736, %r14              # imm = 0x1000000FA0
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_9
# %bb.8:                                #   in Loop: Header=BB6_5 Depth=1
	shlq	$2, %r12
	addq	56(%rsp), %r12
	leaq	(,%r15,4), %rdx
	addq	24(%rsp), %rdx
	movq	88(%rsp), %rsi
	leaq	(,%r13,4), %r8
	addq	40(%rsp), %r8
	movq	%r12, %rdi
	movl	$16, %ecx
	movl	$4, %r9d
	pushq	$3
	.cfi_adjust_cfa_offset 8
	pushq	$4
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__convolutionPiS_PjiS_iii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB6_9:                                #   in Loop: Header=BB6_5 Depth=1
	movq	112(%rsp,%r15,8), %r9
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%rbp, %r14
	jne	.LBB6_11
# %bb.10:                               #   in Loop: Header=BB6_5 Depth=1
	shlq	$2, %r13
	movq	40(%rsp), %rdi
	addq	%r13, %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	shlq	$2, %rsi
	addq	48(%rsp), %rsi
	shlq	$2, %r15
	addq	24(%rsp), %r15
	addq	32(%rsp), %r13
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%r15, %rdx
	movq	%r13, %rcx
	movl	$256, %r8d                      # imm = 0x100
	movl	$256, %r9d                      # imm = 0x100
	movl	$4, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	$16
	.cfi_adjust_cfa_offset 8
	callq	_Z22__device_stub__scatterPiS_PjS_iiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_11:                               #   in Loop: Header=BB6_5 Depth=1
	movl	$1, %r15d
	testb	$1, %bl
	movl	$0, %ebx
	jne	.LBB6_5
# %bb.12:                               # %.critedge246
	movq	32(%rsp), %rsi
	movl	$16386304, %edx                 # imm = 0xFA0900
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	108(%rsp), %rbx
	movl	$0, (%rbx)
	movq	72(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	112(%rsp), %rdi
	callq	hipStreamDestroy
	movq	120(%rsp), %rdi
	callq	hipStreamDestroy
	xorl	%eax, %eax
	addq	$8120, %rsp                     # imm = 0x1FB8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6gatherPiS_S_PjS_iiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convolutionPiS_PjiS_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7scatterPiS_PjS_iiiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6gatherPiS_S_PjS_iiiiiii,@object # @_Z6gatherPiS_S_PjS_iiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z6gatherPiS_S_PjS_iiiiiii
	.p2align	3, 0x0
_Z6gatherPiS_S_PjS_iiiiiii:
	.quad	_Z21__device_stub__gatherPiS_S_PjS_iiiiiii
	.size	_Z6gatherPiS_S_PjS_iiiiiii, 8

	.type	_Z11convolutionPiS_PjiS_iii,@object # @_Z11convolutionPiS_PjiS_iii
	.globl	_Z11convolutionPiS_PjiS_iii
	.p2align	3, 0x0
_Z11convolutionPiS_PjiS_iii:
	.quad	_Z26__device_stub__convolutionPiS_PjiS_iii
	.size	_Z11convolutionPiS_PjiS_iii, 8

	.type	_Z7scatterPiS_PjS_iiiii,@object # @_Z7scatterPiS_PjS_iiiii
	.globl	_Z7scatterPiS_PjS_iiiii
	.p2align	3, 0x0
_Z7scatterPiS_PjS_iiiii:
	.quad	_Z22__device_stub__scatterPiS_PjS_iiiii
	.size	_Z7scatterPiS_PjS_iiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Gimme Image Block Dimensions"
	.size	.L.str, 29

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Gimme krnl Block Dimension"
	.size	.L.str.1, 27

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Gimme Percent Sparcity of the block"
	.size	.L.str.2, 36

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6gatherPiS_S_PjS_iiiiiii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11convolutionPiS_PjiS_iii"
	.size	.L__unnamed_2, 28

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7scatterPiS_PjS_iiiii"
	.size	.L__unnamed_3, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__gatherPiS_S_PjS_iiiiiii
	.addrsig_sym _Z26__device_stub__convolutionPiS_PjiS_iii
	.addrsig_sym _Z22__device_stub__scatterPiS_PjS_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6gatherPiS_S_PjS_iiiiiii
	.addrsig_sym _Z11convolutionPiS_PjiS_iii
	.addrsig_sym _Z7scatterPiS_PjS_iiiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6gatherPiS_S_PjS_iiiiiii ; -- Begin function _Z6gatherPiS_S_PjS_iiiiiii
	.globl	_Z6gatherPiS_S_PjS_iiiiiii
	.p2align	8
	.type	_Z6gatherPiS_S_PjS_iiiiiii,@function
_Z6gatherPiS_S_PjS_iiiiiii:             ; @_Z6gatherPiS_S_PjS_iiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x54
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s17, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s3, s17, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s3, s4
	v_cvt_f32_u32_e32 v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
	s_sub_i32 s2, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s5
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v4, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_add_nc_u32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_xor_b32_e32 v5, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v5, v4
	v_mul_lo_u32 v8, v6, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v1, v8
	v_cmpx_lt_i32_e32 0, v7
	s_cbranch_execz .LBB0_26
; %bb.1:
	s_load_b64 s[12:13], s[0:1], 0x3c
	v_ashrrev_i32_e32 v2, 31, v7
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s13, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s13, s3
	s_xor_b32 s13, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s13
	s_sub_i32 s2, 0, s13
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_readfirstlane_b32 s14, v0
	v_add_nc_u32_e32 v0, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s2, s2, s14
	v_xor_b32_e32 v0, v0, v2
	s_mul_hi_u32 s2, s14, s2
	v_xor_b32_e32 v2, s3, v2
	s_add_i32 s14, s14, s2
	s_ashr_i32 s2, s16, 31
	v_mul_hi_u32 v3, v0, s14
	s_add_i32 s6, s16, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s2
	s_xor_b32 s2, s2, s3
	s_mul_hi_u32 s7, s6, s14
	s_mul_i32 s8, s7, s13
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v9, v3, s13
	s_sub_i32 s6, s6, s8
	s_add_i32 s8, s7, 1
	s_sub_i32 s9, s6, s13
	s_cmp_ge_u32 s6, s13
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s6, s9, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v9
	v_add_nc_u32_e32 v9, 1, v3
	s_add_i32 s8, s7, 1
	s_cmp_ge_u32 s6, s13
	s_cselect_b32 s6, s8, s7
	v_subrev_nc_u32_e32 v10, s13, v0
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	s_xor_b32 s6, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_sub_i32 s24, s6, s2
	v_cmp_lt_i32_e64 s2, 0, v6
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_cndmask_b32 v0, v0, v10
	v_add_nc_u32_e32 v9, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	v_cndmask_b32_e32 v0, v3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v2
	v_sub_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s18, v0
	v_cmp_gt_i32_e32 vcc_lo, s24, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_26
; %bb.2:
	v_ashrrev_i32_e32 v0, 31, v6
	s_mul_hi_u32 s2, s5, s14
	s_xor_b32 s4, s4, s3
	s_mul_i32 s6, s2, s13
	s_add_i32 s7, s2, 1
	v_add_nc_u32_e32 v2, v6, v0
	s_sub_i32 s5, s5, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_sub_i32 s6, s5, s13
	s_cmp_ge_u32 s5, s13
	v_xor_b32_e32 v2, v2, v0
	v_xor_b32_e32 v0, s3, v0
	s_cselect_b32 s2, s7, s2
	s_cselect_b32 s5, s6, s5
	s_add_i32 s6, s2, 1
	v_mul_hi_u32 v3, v2, s14
	s_cmp_ge_u32 s5, s13
	s_cselect_b32 s2, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s4
	s_sub_i32 s2, s2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v9, v3, s13
	v_sub_nc_u32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v10, s13, v2
	v_cmp_le_u32_e32 vcc_lo, s13, v2
	v_dual_cndmask_b32 v2, v2, v10 :: v_dual_add_nc_u32 v9, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, 1, v3
	v_cndmask_b32_e32 v2, v3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v0
	v_sub_nc_u32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s19, v0
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_26
; %bb.3:
	s_add_i32 s4, s18, -1
	s_sub_i32 s5, 1, s18
	s_lshr_b32 s6, s4, 31
	s_lshr_b32 s7, s5, 31
	s_add_i32 s4, s4, s6
	s_add_i32 s5, s5, s7
	s_ashr_i32 s20, s4, 1
	s_ashr_i32 s21, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s21, s20
	s_cbranch_scc1 .LBB0_26
; %bb.4:                                ; %.lr.ph37.i
	s_add_i32 s22, s19, -1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_sub_i32 s25, 1, s19
	s_load_b64 s[0:1], s[0:1], 0x20
	s_lshr_b32 s23, s22, 31
	s_lshr_b32 s26, s25, 31
	s_add_i32 s22, s22, s23
	s_add_i32 s25, s25, s26
	s_ashr_i32 s22, s22, 1
	s_ashr_i32 s23, s25, 1
	v_add_nc_u32_e32 v0, s21, v1
	s_cmp_le_i32 s23, s22
	s_mul_i32 s16, s15, s16
	s_cselect_b32 s25, -1, 0
	s_add_i32 s26, s23, s16
	s_add_i32 s27, s23, -1
	v_mad_u64_u32 v[1:2], null, s17, s26, v[0:1]
	s_mov_b32 s26, 0
	s_mov_b32 s30, s21
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $sgpr29
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_mov_b32 s31, -1
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_mov_b32 s33, -1
                                        ; implicit-def: $sgpr34
	s_cbranch_vccnz .LBB0_11
; %bb.6:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v1
	s_mov_b32 s34, 0
	s_mov_b32 s35, s27
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr36
.LBB0_7:                                ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_or_b32 s36, s36, exec_lo
	s_or_b32 s37, s37, exec_lo
	s_mov_b32 s38, exec_lo
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v3, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 1, v3
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	s_add_i32 s35, s35, 1
	v_add_nc_u32_e32 v2, s17, v2
	s_cmp_ge_i32 s35, s22
	s_cselect_b32 s39, -1, 0
	s_and_not1_b32 s37, s37, exec_lo
	s_and_b32 s39, s39, exec_lo
	s_and_not1_b32 s36, s36, exec_lo
	s_or_b32 s37, s37, s39
; %bb.9:                                ; %Flow159
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s38
	s_xor_b32 s38, s36, -1
	s_and_b32 s39, exec_lo, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s34, s39, s34
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s38, s38, exec_lo
	s_or_b32 s33, s33, s38
	s_and_not1_b32 exec_lo, exec_lo, s34
	s_cbranch_execnz .LBB0_7
; %bb.10:                               ; %loop.exit.guard156
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s34
	s_mov_b32 s34, -1
.LBB0_11:                               ; %Flow160
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_b32 s29, s29, exec_lo
	s_and_b32 s34, s34, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s29, s29, s34
	s_and_saveexec_b32 s34, s33
; %bb.12:                               ; %.critedge.i
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s33, s30, 1
	s_cmp_ge_i32 s30, s20
	v_add_nc_u32_e32 v1, 1, v1
	s_cselect_b32 s30, -1, 0
	s_and_not1_b32 s29, s29, exec_lo
	s_or_not1_b32 s31, s30, exec_lo
	s_mov_b32 s30, s33
; %bb.13:                               ; %Flow161
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s34
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s31, exec_lo, s31
	s_or_b32 s26, s31, s26
	s_and_not1_b32 s28, s28, exec_lo
	s_and_b32 s31, s29, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s28, s28, s31
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_5
; %bb.14:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s26
	s_and_saveexec_b32 s25, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, s25
	s_cbranch_execz .LBB0_26
; %bb.15:                               ; %_Z11checksparsePiiiiiiiiii.exit
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0xf4240
	v_add3_u32 v0, s16, s20, v0
	s_cmp_gt_i32 s12, 0
	v_add_nc_u32_e32 v11, s20, v7
	v_add_nc_u32_e32 v12, s22, v6
	s_waitcnt lgkmcnt(0)
	global_atomic_inc_u32 v9, v1, v2, s[10:11] glc
	v_sub_nc_u32_e32 v0, v0, v8
	s_cselect_b32 s10, -1, 0
	s_add_i32 s11, s22, s23
	s_mul_i32 s24, s24, s15
	s_mul_i32 s16, s12, s17
	v_mul_lo_u32 v0, s17, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s11, v5, v0
	s_mul_i32 s11, s19, s18
	s_mul_i32 s11, s11, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v4
	v_mul_lo_u32 v10, s12, v0
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v8, s11, v9
	s_mov_b32 s11, 0
.LBB0_16:                               ; %.preheader.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_17 Depth 2
                                        ;       Child Loop BB0_19 Depth 3
	v_add_nc_u32_e32 v0, s21, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v10
	s_mov_b32 s17, s23
	v_ashrrev_i32_e32 v2, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_xor_b32_e32 v0, v0, v2
	v_xor_b32_e32 v2, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, s14
	v_mul_lo_u32 v4, v3, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s13, v0
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v0, v0, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v2
	v_sub_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s24, v0
	v_mul_lo_u32 v13, v0, s2
.LBB0_17:                               ; %.preheader
                                        ;   Parent Loop BB0_16 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_19 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_22
; %bb.18:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_17 Depth=2
	v_add_nc_u32_e32 v0, s17, v12
	s_mov_b32 s18, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v0
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v2
	v_xor_b32_e32 v2, s3, v2
	v_mul_hi_u32 v3, v0, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s13
	v_sub_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s13, v0
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	v_mov_b32_e32 v4, v14
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v2
	v_add_nc_u32_e32 v2, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_19:                               ;   Parent Loop BB0_16 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v0, v[2:3], off
	v_mov_b32_e32 v5, 0
	s_mov_b32 s19, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_19 Depth=3
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 2, v[4:5]
	v_add_co_u32 v15, vcc_lo, s6, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
	global_load_b32 v5, v[15:16], off
.LBB0_21:                               ;   in Loop: Header=BB0_19 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
	v_add_nc_u32_e32 v0, s11, v8
	v_add_nc_u32_e32 v4, 1, v4
	s_add_i32 s18, s18, -1
	s_add_i32 s11, s11, 1
	s_cmp_eq_u32 s18, 0
	v_lshlrev_b64 v[15:16], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, s8, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[15:16], v5, off
	s_cbranch_scc0 .LBB0_19
.LBB0_22:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_17 Depth=2
	v_add_nc_u32_e32 v14, s12, v14
	s_add_i32 s18, s17, 1
	s_cmp_ge_i32 s17, s22
	s_cbranch_scc1 .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_17 Depth=2
	s_mov_b32 s17, s18
	s_branch .LBB0_17
.LBB0_24:                               ; %._crit_edge105
                                        ;   in Loop: Header=BB0_16 Depth=1
	v_add_nc_u32_e32 v10, s16, v10
	s_add_i32 s17, s21, 1
	s_cmp_ge_i32 s21, s20
	s_mov_b32 s21, s17
	s_cbranch_scc0 .LBB0_16
; %bb.25:                               ; %._crit_edge111
	v_lshl_add_u32 v0, v9, 1, v9
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v5, v1 :: v_dual_add_nc_u32 v4, 1, v0
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_nc_u32_e32 v0, 2, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x2
	global_store_b32 v[2:3], v7, off
	global_store_b32 v[4:5], v6, off
	global_store_b32 v[0:1], v8, off
.LBB0_26:                               ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6gatherPiS_S_PjS_iiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6gatherPiS_S_PjS_iiiiiii, .Lfunc_end0-_Z6gatherPiS_S_PjS_iiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1864
; NumSgprs: 42
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11convolutionPiS_PjiS_iii ; -- Begin function _Z11convolutionPiS_PjiS_iii
	.globl	_Z11convolutionPiS_PjiS_iii
	.p2align	8
	.type	_Z11convolutionPiS_PjiS_iii,@function
_Z11convolutionPiS_PjiS_iii:            ; @_Z11convolutionPiS_PjiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b32 s8, s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s14, s2, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
	s_load_b64 s[2:3], s[0:1], 0x20
	v_mad_u64_u32 v[0:1], null, v3, s8, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_cmp_gt_i32_e64 s2, s8, v4
	global_store_b32 v[0:1], v2, off
	global_load_b32 v5, v2, s[4:5]
	s_load_b128 s[4:7], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s3, s4, s6
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v3, v5
	s_and_b32 s2, vcc_lo, s2
	s_cmp_gt_i32 s3, 0
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s5
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mul_lo_u32 v3, v3, s3
	v_mul_lo_u32 v5, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[5:6], off
	global_load_b32 v10, v[3:4], off
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v10, v9, v[2:3]
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_mov_b32_e32 v2, v7
	global_store_b32 v[0:1], v7, off
	s_cbranch_scc1 .LBB1_2
.LBB1_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convolutionPiS_PjiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11convolutionPiS_PjiS_iii, .Lfunc_end1-_Z11convolutionPiS_PjiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7scatterPiS_PjS_iiiii ; -- Begin function _Z7scatterPiS_PjS_iiiii
	.globl	_Z7scatterPiS_PjS_iiiii
	.p2align	8
	.type	_Z7scatterPiS_PjS_iiiii,@function
_Z7scatterPiS_PjS_iiiii:                ; @_Z7scatterPiS_PjS_iiiii
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x44
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_load_b32 s3, s[8:9], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	s_lshr_b32 s8, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[0:1], null, s15, s8, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s18, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_lshl_add_u32 v3, v2, 1, v2
	v_mad_u64_u32 v[6:7], null, v2, s18, v[0:1]
	s_load_b32 s0, s[0:1], 0x30
	s_sub_i32 s2, s16, s19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s2, s2, 1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_lshlrev_b64 v[1:2], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b96 v[3:5], v[3:4], off
	s_waitcnt lgkmcnt(0)
	s_add_i32 s1, s0, -1
	s_sub_i32 s0, s17, s0
	global_load_b32 v6, v[1:2], off
	s_lshr_b32 s3, s1, 31
	s_add_i32 s4, s19, -1
	s_add_i32 s1, s1, s3
	s_add_i32 s0, s0, 1
	s_ashr_i32 s1, s1, 1
	s_mul_i32 s0, s0, s2
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[1:2], null, v5, s18, v[0:1]
	v_subrev_nc_u32_e32 v0, s1, v4
	s_lshr_b32 s1, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s4, s4, s1
	v_mul_lo_u32 v0, v0, s17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v1, s0, v1
	s_ashr_i32 s0, s4, 1
	v_subrev_nc_u32_e32 v2, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v2, v0, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v6, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7scatterPiS_PjS_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7scatterPiS_PjS_iiiii, .Lfunc_end2-_Z7scatterPiS_PjS_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 22
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6gatherPiS_S_PjS_iiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     42
    .sgpr_spill_count: 0
    .symbol:         _Z6gatherPiS_S_PjS_iiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11convolutionPiS_PjiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11convolutionPiS_PjiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7scatterPiS_PjS_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z7scatterPiS_PjS_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
