/* Voxel sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 */
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <iostream>
#define USECPSEC 1000000ULL

__device__ int binary_search(const long long* input_voxel_idx,
                             int start_id,
                             int stop_id,
                             long long target_voxel_id) {
//    if (threadIdx.x==0)
    if (input_voxel_idx[start_id] > target_voxel_id || input_voxel_idx[stop_id] < target_voxel_id)
        return -1;
    while (start_id <= stop_id) {
        int m = start_id + (stop_id - start_id) / 2;
        if (input_voxel_idx[m] == target_voxel_id)
            return m;
        if (input_voxel_idx[m] < target_voxel_id)
            start_id = m + 1;
        else
            stop_id = m - 1;
    }
    return -1;
}

__global__ void voxel_sampling_binary_gpu_kernel(int batch_size, int input_npoint, int channels,
                                        int center_num, int kernel_size,
                                        float dim_w, float dim_l, float dim_h,
                                        float resolution, float padding,
                                        const float* input_coors,
                                        const float* input_features,
                                        const long long* input_voxel_idx,
                                        const int* input_num_list,
                                        const float* center_coors,
                                        const int* center_num_list,
                                        int* input_accu_list,
                                        int* center_accu_list,
                                        float* output_features,
                                        int* output_idx) {

    if (batch_size*input_npoint <=0 || channels * center_num <= 0) {
//        printf("Voxel sample Op exited unexpectedly.\n");
        return;
    }
	const int half_kernel_size = (kernel_size - 1) / 2;
	const float radius = 1.5 * resolution;
	const float r2 = radius * radius;
	const int kernel_num = kernel_size * kernel_size * kernel_size;
	const int center_offset = kernel_size * kernel_size * half_kernel_size + \
                              kernel_size * half_kernel_size + \
                              half_kernel_size;
	const float EPS = 1e-6;
	int grid_w = dim_w / resolution;
	int grid_l = dim_l / resolution;
	int grid_h = dim_h / resolution;
//	printf("%f, %f, %f\n", dim_w, dim_l, dim_h);

	for (int b=blockIdx.x; b<batch_size; b+=gridDim.x) {
	    for (int i=threadIdx.x; i<center_num_list[b]; i+=blockDim.x) {
	        for (int j=0; j<kernel_num; j++) {
	            output_idx[center_accu_list[b]*kernel_num + i*kernel_num + j] = -1;
	            for (int u=0; u<channels; u++) {
	                output_features[center_accu_list[b]*kernel_num*channels + i*kernel_num*channels + j*channels + u] = padding;
	            }
	        }
	    }
	    __syncthreads();


	    for (int i=threadIdx.x; i<center_num_list[b]; i+=blockDim.x) {
	        float x_c = center_coors[center_accu_list[b]*3 + i*3 + 0];
	        float y_c = center_coors[center_accu_list[b]*3 + i*3 + 1];
	        float z_c = center_coors[center_accu_list[b]*3 + i*3 + 2];
	        int grid_coor_w = x_c / resolution;
	        int grid_coor_l = y_c / resolution;
	        int grid_coor_h = z_c / resolution;
//	        long long grid_idx_c = grid_coor_h * grid_w * grid_l + grid_coor_l * grid_w + grid_coor_w;
            int grid_search_w_min, grid_search_w_max;
            int grid_search_l_min, grid_search_l_max;
            int grid_search_h_min, grid_search_h_max;
	        if (grid_coor_w * resolution + 0.5 * resolution > x_c) {
	            grid_search_w_min = grid_coor_w - 2;
	            grid_search_w_max = grid_coor_w + 1;
	        }else{
	            grid_search_w_min = grid_coor_w - 1;
	            grid_search_w_max = grid_coor_w + 2;
            }
            if (grid_coor_l * resolution + 0.5 * resolution > y_c) {
	            grid_search_l_min = grid_coor_l - 2;
	            grid_search_l_max = grid_coor_l + 1;
	        }else{
	            grid_search_l_min = grid_coor_l - 1;
	            grid_search_l_max = grid_coor_l + 2;
            }
            if (grid_coor_h * resolution + 0.5 * resolution > z_c) {
	            grid_search_h_min = grid_coor_h - 2;
	            grid_search_h_max = grid_coor_h + 1;
	        }else{
	            grid_search_h_min = grid_coor_h - 1;
	            grid_search_h_max = grid_coor_h + 2;
            }

	        for (int w=max(0, grid_search_w_min); w<=min(grid_search_w_max, grid_w-1); w++) {
	            for (int l=max(0, grid_search_l_min); l<=min(grid_search_l_max, grid_l-1); l++) {
	                for (int h=max(0, grid_search_h_min); h<=min(grid_search_h_max, grid_h-1); h++) {
                        long long target_grid_id = h * grid_w * grid_l + l * grid_w + w;
                        int id = binary_search(input_voxel_idx,
                                               input_accu_list[b],
                                               input_accu_list[b] + input_num_list[b] - 1,
                                               target_grid_id);
//                        if (id > 100000)
//                            printf("************VoxelSamplingBinaryOpId: %d\n", id);
                        if (id>=0) {
                            float x_i = input_coors[id*3 + 0];
                            float y_i = input_coors[id*3 + 1];
                            float z_i = input_coors[id*3 + 2];
                            float dx = x_i - x_c + EPS;
                            float dy = y_i - y_c + EPS;
                            float dz = z_i - z_c + EPS;
                            float dx2 = dx * dx;
                            float dy2 = dy * dy;
                            float dz2 = dz * dz;
                            if (dx2 < r2 && dy2 < r2 && dz2 < r2) {
                                int x_coor = __float2int_rz(dx / resolution + 0.5 * fabsf(dx) / dx);
                                int y_coor = __float2int_rz(dy / resolution + 0.5 * fabsf(dy) / dy);
                                int z_coor = __float2int_rz(dz / resolution + 0.5 * fabsf(dz) / dz);
                                int voxel_coor = center_accu_list[b] * kernel_num + i * kernel_num + center_offset + \
                                                 kernel_size * kernel_size * x_coor + \
                                                 kernel_size * y_coor + \
                                                 z_coor;
                                if (output_idx[voxel_coor] < 0) {
                                    output_idx[voxel_coor] = id;
                                    for (int c=0; c<channels; c++) {
                                        output_features[voxel_coor * channels + c] = input_features[id*channels + c];
                                    }
                                }
                            }
                        }
	                }
	            }
	        }
	    }
	}
}


__global__ void voxel_sampling_binary_grad_gpu_kernel(int center_num, int kernel_num, int channels,
                                                     const int* output_idx,
                                                     const float* output_features_grad,
                                                     float* input_features_grad) {
    int batch_size = __float2int_ru((float)center_num / blockDim.x);
    if (center_num==0 || kernel_num*channels == 0) {
        printf("Voxel sample grad Op exited unexpectedly.\n");
        return;
    }
    for (int b=blockIdx.x; b<batch_size; b+=gridDim.x) {
//        for (int i=threadIdx.x; b*blockDim.x + i < ncenters; i+=blockDim.x) {}
        int center_id = b*blockDim.x + threadIdx.x;
        if (center_id < center_num) {
            for (int i=0; i<kernel_num; i++) {
                int voxel_coor = center_id*kernel_num + i;
                int id = output_idx[voxel_coor];
                if (id != -1) {
//                    if (id > 1000000)
//                        printf("************VoxelSamplingBinaryOpId: %d@[voxel_coor=%d, center_id=%d, i=%d, center_num=%d]\n", id, voxel_coor, center_id, i, center_num);
                     for (int c=0; c<channels; c++) {
                        atomicAdd(&input_features_grad[id*channels + c], output_features_grad[voxel_coor*channels + c]);
                     }
                }
            }
        }
    }
}

long long dtime_usec(unsigned long long start){

  timeval tv;
  gettimeofday(&tv, 0);
  return ((tv.tv_sec*USECPSEC)+tv.tv_usec)-start;
}


void voxel_sampling_binary_gpu_launcher(int batch_size, int input_npoint, int channels,
                               int center_num, int kernel_size,
                               float dim_w, float dim_l, float dim_h,
                               float resolution, float padding,
                               const float* input_coors,
                               const float* input_features,
                               const long long* input_voxel_idx,
                               const int* input_num_list,
                               const float* center_coors,
                               const int* center_num_list,
                               int* input_accu_list,
                               int* center_accu_list,
                               float* output_features,
                               int* output_idx) {
    long long dt = dtime_usec(0);
    voxel_sampling_binary_gpu_kernel<<<32,512>>>(batch_size, input_npoint, channels,
                                        center_num, kernel_size,
                                        dim_w, dim_l, dim_h,
                                        resolution, padding,
                                        input_coors,
                                        input_features,
                                        input_voxel_idx,
                                        input_num_list,
                                        center_coors,
                                        center_num_list,
                                        input_accu_list,
                                        center_accu_list,
                                        output_features,
                                        output_idx);
//    dt = dtime_usec(dt);
//	std::cout << "Voxel Sample (forward) CUDA time: " << dt/(float)USECPSEC << "s" << std::endl;


}


void voxel_sampling_binary_grad_gpu_launcher(int center_num, int kernel_num, int channels,
                                             const int* output_idx,
                                            const float* output_features_grad,
                                             float* input_features_grad) {
    voxel_sampling_binary_grad_gpu_kernel<<<32, 512>>>(center_num, kernel_num, channels,
                                                       output_idx,
                                                       output_features_grad,
                                                       input_features_grad);
}
	.file	"tmpxft_002e48a1_00000000-6_voxel_sampling_binary.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13binary_searchPKxiix
	.type	_Z13binary_searchPKxiix, @function
_Z13binary_searchPKxiix:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z13binary_searchPKxiix, .-_Z13binary_searchPKxiix
	.globl	_Z10dtime_usecy
	.type	_Z10dtime_usecy, @function
_Z10dtime_usecy:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%esi, %esi
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	imulq	$1000000, 8(%rsp), %rax
	addq	16(%rsp), %rax
	subq	%rbx, %rax
	movq	24(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z10dtime_usecy, .-_Z10dtime_usecy
	.globl	_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.type	_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, @function
_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movq	384(%rsp), %rax
	movl	%edi, 124(%rsp)
	leaq	152(%rsp), %rdi
	movl	%esi, 120(%rsp)
	leaq	164(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	392(%rsp), %rax
	movl	%edx, 116(%rsp)
	leaq	136(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	400(%rsp), %rax
	movl	%ecx, 112(%rsp)
	leaq	144(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	408(%rsp), %rax
	movl	%r8d, 108(%rsp)
	movq	%rax, 48(%rsp)
	movq	416(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	424(%rsp), %rax
	movss	%xmm0, 104(%rsp)
	movq	%rax, 32(%rsp)
	movq	432(%rsp), %rax
	movss	%xmm1, 100(%rsp)
	movq	%rax, 24(%rsp)
	movq	440(%rsp), %rax
	movss	%xmm2, 96(%rsp)
	movq	%rax, 16(%rsp)
	movq	448(%rsp), %rax
	movss	%xmm3, 92(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm4, 88(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	124(%rsp), %rax
	movl	$1, 160(%rsp)
	movq	%rax, 200(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	116(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	108(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	100(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	92(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 152(%rsp)
	movq	%rax, 164(%rsp)
	movl	$1, 172(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	144(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_(%rip), %rdi
	pushq	144(%rsp)
	.cfi_def_cfa_offset 400
	movq	180(%rsp), %rcx
	movl	188(%rsp), %r8d
	movq	168(%rsp), %rsi
	movl	176(%rsp), %edx
	leaq	216(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L8:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, .-_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.globl	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.type	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, @function
_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.cfi_endproc
.LFE3664:
	.size	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, .-_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.globl	_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.type	_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, @function
_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	192(%rsp), %rax
	movss	%xmm0, 76(%rsp)
	movq	176(%rsp), %rbx
	movss	%xmm1, 72(%rsp)
	movq	184(%rsp), %rbp
	movq	200(%rsp), %r12
	movss	%xmm2, 68(%rsp)
	movq	208(%rsp), %r13
	movq	216(%rsp), %r14
	movss	%xmm3, 64(%rsp)
	movss	%xmm4, 60(%rsp)
	movl	%esi, 12(%rsp)
	movl	%edx, 16(%rsp)
	movl	%ecx, 20(%rsp)
	movl	%r8d, 56(%rsp)
	movq	%r9, 24(%rsp)
	movl	%edi, 8(%rsp)
	xorl	%edi, %edi
	movq	%rax, 32(%rsp)
	movq	224(%rsp), %r15
	movq	232(%rsp), %r10
	movq	240(%rsp), %r11
	movq	%r10, 48(%rsp)
	movq	%r11, 40(%rsp)
	call	_Z10dtime_usecy
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$134217729, %edi
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$5, %rdi
	call	__cudaPushCallConfiguration@PLT
	movq	40(%rsp), %r11
	movq	48(%rsp), %r10
	testl	%eax, %eax
	movss	60(%rsp), %xmm4
	movss	64(%rsp), %xmm3
	movss	68(%rsp), %xmm2
	movss	72(%rsp), %xmm1
	movss	76(%rsp), %xmm0
	jne	.L13
	movq	32(%rsp), %rax
	movq	%r15, 224(%rsp)
	movq	%r14, 216(%rsp)
	movq	24(%rsp), %r9
	movq	%r13, 208(%rsp)
	movl	56(%rsp), %r8d
	movq	%r12, 200(%rsp)
	movl	20(%rsp), %ecx
	movq	%rbp, 184(%rsp)
	movl	16(%rsp), %edx
	movq	%rbx, 176(%rsp)
	movl	12(%rsp), %esi
	movq	%r11, 240(%rsp)
	movl	8(%rsp), %edi
	movq	%r10, 232(%rsp)
	movq	%rax, 192(%rsp)
	addq	$120, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z88__device_stub__Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_iiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
.L13:
	.cfi_restore_state
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, .-_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.globl	_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf
	.type	_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf, @function
_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L16:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf, .-_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf
	.globl	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.type	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, @function
_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf
	.cfi_endproc
.LFE3666:
	.size	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, .-_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.globl	_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf
	.type	_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf, @function
_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movl	$8388609, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$9, %rdx
	movl	%esi, %ebp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movl	$134217729, %edi
	salq	$5, %rdi
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%r12d, %edx
	movl	%ebp, %esi
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z66__device_stub__Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPfiiiPKiPKfPf
.L21:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf, .-_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf"
.LC1:
	.string	"_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3668:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3668:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Voxel sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <iostream>
#define USECPSEC 1000000ULL

__device__ int binary_search(const long long* input_voxel_idx,
                             int start_id,
                             int stop_id,
                             long long target_voxel_id) {
//    if (threadIdx.x==0)
    if (input_voxel_idx[start_id] > target_voxel_id || input_voxel_idx[stop_id] < target_voxel_id)
        return -1;
    while (start_id <= stop_id) {
        int m = start_id + (stop_id - start_id) / 2;
        if (input_voxel_idx[m] == target_voxel_id)
            return m;
        if (input_voxel_idx[m] < target_voxel_id)
            start_id = m + 1;
        else
            stop_id = m - 1;
    }
    return -1;
}

__global__ void voxel_sampling_binary_gpu_kernel(int batch_size, int input_npoint, int channels,
                                        int center_num, int kernel_size,
                                        float dim_w, float dim_l, float dim_h,
                                        float resolution, float padding,
                                        const float* input_coors,
                                        const float* input_features,
                                        const long long* input_voxel_idx,
                                        const int* input_num_list,
                                        const float* center_coors,
                                        const int* center_num_list,
                                        int* input_accu_list,
                                        int* center_accu_list,
                                        float* output_features,
                                        int* output_idx) {

    if (batch_size*input_npoint <=0 || channels * center_num <= 0) {
//        printf("Voxel sample Op exited unexpectedly.\n");
        return;
    }
	const int half_kernel_size = (kernel_size - 1) / 2;
	const float radius = 1.5 * resolution;
	const float r2 = radius * radius;
	const int kernel_num = kernel_size * kernel_size * kernel_size;
	const int center_offset = kernel_size * kernel_size * half_kernel_size + \
                              kernel_size * half_kernel_size + \
                              half_kernel_size;
	const float EPS = 1e-6;
	int grid_w = dim_w / resolution;
	int grid_l = dim_l / resolution;
	int grid_h = dim_h / resolution;
//	printf("%f, %f, %f\n", dim_w, dim_l, dim_h);

	for (int b=blockIdx.x; b<batch_size; b+=gridDim.x) {
	    for (int i=threadIdx.x; i<center_num_list[b]; i+=blockDim.x) {
	        for (int j=0; j<kernel_num; j++) {
	            output_idx[center_accu_list[b]*kernel_num + i*kernel_num + j] = -1;
	            for (int u=0; u<channels; u++) {
	                output_features[center_accu_list[b]*kernel_num*channels + i*kernel_num*channels + j*channels + u] = padding;
	            }
	        }
	    }
	    __syncthreads();


	    for (int i=threadIdx.x; i<center_num_list[b]; i+=blockDim.x) {
	        float x_c = center_coors[center_accu_list[b]*3 + i*3 + 0];
	        float y_c = center_coors[center_accu_list[b]*3 + i*3 + 1];
	        float z_c = center_coors[center_accu_list[b]*3 + i*3 + 2];
	        int grid_coor_w = x_c / resolution;
	        int grid_coor_l = y_c / resolution;
	        int grid_coor_h = z_c / resolution;
//	        long long grid_idx_c = grid_coor_h * grid_w * grid_l + grid_coor_l * grid_w + grid_coor_w;
            int grid_search_w_min, grid_search_w_max;
            int grid_search_l_min, grid_search_l_max;
            int grid_search_h_min, grid_search_h_max;
	        if (grid_coor_w * resolution + 0.5 * resolution > x_c) {
	            grid_search_w_min = grid_coor_w - 2;
	            grid_search_w_max = grid_coor_w + 1;
	        }else{
	            grid_search_w_min = grid_coor_w - 1;
	            grid_search_w_max = grid_coor_w + 2;
            }
            if (grid_coor_l * resolution + 0.5 * resolution > y_c) {
	            grid_search_l_min = grid_coor_l - 2;
	            grid_search_l_max = grid_coor_l + 1;
	        }else{
	            grid_search_l_min = grid_coor_l - 1;
	            grid_search_l_max = grid_coor_l + 2;
            }
            if (grid_coor_h * resolution + 0.5 * resolution > z_c) {
	            grid_search_h_min = grid_coor_h - 2;
	            grid_search_h_max = grid_coor_h + 1;
	        }else{
	            grid_search_h_min = grid_coor_h - 1;
	            grid_search_h_max = grid_coor_h + 2;
            }

	        for (int w=max(0, grid_search_w_min); w<=min(grid_search_w_max, grid_w-1); w++) {
	            for (int l=max(0, grid_search_l_min); l<=min(grid_search_l_max, grid_l-1); l++) {
	                for (int h=max(0, grid_search_h_min); h<=min(grid_search_h_max, grid_h-1); h++) {
                        long long target_grid_id = h * grid_w * grid_l + l * grid_w + w;
                        int id = binary_search(input_voxel_idx,
                                               input_accu_list[b],
                                               input_accu_list[b] + input_num_list[b] - 1,
                                               target_grid_id);
//                        if (id > 100000)
//                            printf("************VoxelSamplingBinaryOpId: %d\n", id);
                        if (id>=0) {
                            float x_i = input_coors[id*3 + 0];
                            float y_i = input_coors[id*3 + 1];
                            float z_i = input_coors[id*3 + 2];
                            float dx = x_i - x_c + EPS;
                            float dy = y_i - y_c + EPS;
                            float dz = z_i - z_c + EPS;
                            float dx2 = dx * dx;
                            float dy2 = dy * dy;
                            float dz2 = dz * dz;
                            if (dx2 < r2 && dy2 < r2 && dz2 < r2) {
                                int x_coor = __float2int_rz(dx / resolution + 0.5 * fabsf(dx) / dx);
                                int y_coor = __float2int_rz(dy / resolution + 0.5 * fabsf(dy) / dy);
                                int z_coor = __float2int_rz(dz / resolution + 0.5 * fabsf(dz) / dz);
                                int voxel_coor = center_accu_list[b] * kernel_num + i * kernel_num + center_offset + \
                                                 kernel_size * kernel_size * x_coor + \
                                                 kernel_size * y_coor + \
                                                 z_coor;
                                if (output_idx[voxel_coor] < 0) {
                                    output_idx[voxel_coor] = id;
                                    for (int c=0; c<channels; c++) {
                                        output_features[voxel_coor * channels + c] = input_features[id*channels + c];
                                    }
                                }
                            }
                        }
	                }
	            }
	        }
	    }
	}
}


__global__ void voxel_sampling_binary_grad_gpu_kernel(int center_num, int kernel_num, int channels,
                                                     const int* output_idx,
                                                     const float* output_features_grad,
                                                     float* input_features_grad) {
    int batch_size = __float2int_ru((float)center_num / blockDim.x);
    if (center_num==0 || kernel_num*channels == 0) {
        printf("Voxel sample grad Op exited unexpectedly.\n");
        return;
    }
    for (int b=blockIdx.x; b<batch_size; b+=gridDim.x) {
//        for (int i=threadIdx.x; b*blockDim.x + i < ncenters; i+=blockDim.x) {}
        int center_id = b*blockDim.x + threadIdx.x;
        if (center_id < center_num) {
            for (int i=0; i<kernel_num; i++) {
                int voxel_coor = center_id*kernel_num + i;
                int id = output_idx[voxel_coor];
                if (id != -1) {
//                    if (id > 1000000)
//                        printf("************VoxelSamplingBinaryOpId: %d@[voxel_coor=%d, center_id=%d, i=%d, center_num=%d]\n", id, voxel_coor, center_id, i, center_num);
                     for (int c=0; c<channels; c++) {
                        atomicAdd(&input_features_grad[id*channels + c], output_features_grad[voxel_coor*channels + c]);
                     }
                }
            }
        }
    }
}

long long dtime_usec(unsigned long long start){

  timeval tv;
  gettimeofday(&tv, 0);
  return ((tv.tv_sec*USECPSEC)+tv.tv_usec)-start;
}


void voxel_sampling_binary_gpu_launcher(int batch_size, int input_npoint, int channels,
                               int center_num, int kernel_size,
                               float dim_w, float dim_l, float dim_h,
                               float resolution, float padding,
                               const float* input_coors,
                               const float* input_features,
                               const long long* input_voxel_idx,
                               const int* input_num_list,
                               const float* center_coors,
                               const int* center_num_list,
                               int* input_accu_list,
                               int* center_accu_list,
                               float* output_features,
                               int* output_idx) {
    long long dt = dtime_usec(0);
    voxel_sampling_binary_gpu_kernel<<<32,512>>>(batch_size, input_npoint, channels,
                                        center_num, kernel_size,
                                        dim_w, dim_l, dim_h,
                                        resolution, padding,
                                        input_coors,
                                        input_features,
                                        input_voxel_idx,
                                        input_num_list,
                                        center_coors,
                                        center_num_list,
                                        input_accu_list,
                                        center_accu_list,
                                        output_features,
                                        output_idx);
//    dt = dtime_usec(dt);
//	std::cout << "Voxel Sample (forward) CUDA time: " << dt/(float)USECPSEC << "s" << std::endl;


}


void voxel_sampling_binary_grad_gpu_launcher(int center_num, int kernel_num, int channels,
                                             const int* output_idx,
                                            const float* output_features_grad,
                                             float* input_features_grad) {
    voxel_sampling_binary_grad_gpu_kernel<<<32, 512>>>(center_num, kernel_num, channels,
                                                       output_idx,
                                                       output_features_grad,
                                                       input_features_grad);
}
	.text
	.file	"voxel_sampling_binary.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_ # -- Begin function _Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.type	_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_,@function
_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_: # @_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	36(%rsp), %rax
	movl	%edi, (%rax)
	leaq	32(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	28(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	20(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	16(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	12(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	8(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	4(%rsp), %r14
	movss	%xmm3, (%r14)
	movq	%rsp, %r15
	movss	%xmm4, (%r15)
	leaq	56(%rsp), %r12
	movq	%r9, (%r12)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	movq	%r15, 72(%rbx)
	movq	%r12, 80(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	48(%rsp), %r12
	leaq	40(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, .Lfunc_end0-_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.cfi_endproc
                                        # -- End function
	.globl	_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf # -- Begin function _Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.type	_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf,@function
_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf: # @_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, .Lfunc_end1-_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z10dtime_usecy                 # -- Begin function _Z10dtime_usecy
	.type	_Z10dtime_usecy,@function
_Z10dtime_usecy:                        # @_Z10dtime_usecy
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imulq	$1000000, (%r14), %rcx          # imm = 0xF4240
	movq	8(%r14), %rax
	subq	%rbx, %rax
	addq	%rcx, %rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z10dtime_usecy, .Lfunc_end2-_Z10dtime_usecy
	.cfi_endproc
                                        # -- End function
	.globl	_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_ # -- Begin function _Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.type	_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_,@function
_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_: # @_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movss	%xmm4, 20(%rsp)                 # 4-byte Spill
	movss	%xmm3, 16(%rsp)                 # 4-byte Spill
	movss	%xmm2, 12(%rsp)                 # 4-byte Spill
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	leaq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	leaq	480(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 96
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	8(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movq	%rbx, %r9
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_ # TAILCALL
.Lfunc_end3:
	.size	_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, .Lfunc_end3-_Z34voxel_sampling_binary_gpu_launcheriiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.cfi_endproc
                                        # -- End function
	.globl	_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf # -- Begin function _Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf
	.type	_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf,@function
_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf: # @_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movl	%esi, %r12d
	movl	%edi, %r13d
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	leaq	480(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf # TAILCALL
.Lfunc_end4:
	.size	_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf, .Lfunc_end4-_Z39voxel_sampling_binary_grad_gpu_launcheriiiPKiPKfPf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_,@object # @_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.section	.rodata,"a",@progbits
	.globl	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.p2align	3, 0x0
_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_:
	.quad	_Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.size	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, 8

	.type	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf,@object # @_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.globl	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.p2align	3, 0x0
_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf:
	.quad	_Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.size	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_"
	.size	.L__unnamed_1, 75

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf"
	.size	.L__unnamed_2, 53

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z47__device_stub__voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.addrsig_sym _Z52__device_stub__voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.addrsig_sym _Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_ ; -- Begin function _Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.globl	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
	.p2align	8
	.type	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_,@function
_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_: ; @_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
; %bb.0:
	s_load_b256 s[24:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s25, s24
	s_mul_i32 s3, s27, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_i32 s2, s2, s3
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_41
; %bb.1:
	s_mov_b32 s34, s15
	s_cmp_ge_i32 s15, s24
	s_cbranch_scc1 .LBB0_41
; %bb.2:                                ; %.lr.ph261
	s_clause 0x3
	s_load_b64 s[40:41], s[0:1], 0x20
	s_load_b512 s[8:23], s[0:1], 0x28
	s_load_b128 s[36:39], s[0:1], 0x68
	s_load_b32 s27, s[0:1], 0x78
	s_add_i32 s4, s28, -1
	s_mul_i32 s7, s28, s28
	s_lshr_b32 s5, s4, 31
	s_mul_i32 s25, s7, s28
	s_add_i32 s4, s4, s5
	v_mov_b32_e32 v20, -1
	s_ashr_i32 s4, s4, 1
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v3, null, s40, s40, s29
	v_div_scale_f32 v6, null, s40, s40, s30
	v_cvt_f64_f32_e32 v[1:2], s40
	v_div_scale_f32 v7, null, s40, s40, s31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v8, v3
	v_rcp_f32_e32 v9, v6
	v_div_scale_f32 v11, vcc_lo, s29, s40, s29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v10, v7
	v_div_scale_f32 v12, s2, s30, s40, s30
	v_div_scale_f32 v15, s3, s31, s40, s31
	v_mul_f32_e64 v18, 0x3fc00000, s40
	v_fma_f32 v4, -v3, v8, 1.0
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v6, v9, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v7, v10, 1.0
	v_dual_fmac_f32 v8, v4, v8 :: v_dual_fmac_f32 v9, v5, v9
	v_dual_fmac_f32 v10, v13, v10 :: v_dual_mul_f32 v13, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v16, v12, v9 :: v_dual_mul_f32 v17, v15, v10
	v_fma_f32 v4, -v3, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, -v6, v16, v12
	v_fma_f32 v14, -v7, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, v4, v8 :: v_dual_fmac_f32 v16, v5, v9
	v_mul_f64 v[4:5], v[1:2], 0.5
	v_fma_f32 v1, -v3, v13, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v6, v16, v12
	v_div_fmas_f32 v1, v1, v8, v13
	s_mov_b32 vcc_lo, s2
	s_add_i32 s2, s28, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v2, v2, v9, v16
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v1, v1, s40, s29
	s_add_i32 s50, s2, 1
	s_cmp_gt_i32 s25, 0
	v_div_fixup_f32 v2, v2, s40, s30
	s_cselect_b32 s29, -1, 0
	s_cmp_gt_i32 s26, 0
	s_mul_i32 s50, s50, s4
	s_cselect_b32 s33, -1, 0
	v_cvt_i32_f32_e32 v16, v2
	v_fmac_f32_e32 v17, v14, v10
	v_mul_f32_e32 v14, v18, v18
	s_add_u32 s30, s0, 0x78
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, -1, v16
	v_fma_f32 v3, -v7, v17, v15
	v_cvt_i32_f32_e32 v15, v1
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v3, v3, v10, v17
	v_add_nc_u32_e32 v17, -1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v3, s40, s31
	s_addc_u32 s31, s1, 0
	v_cvt_i32_f32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v19, -1, v1
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;         Child Loop BB0_19 Depth 4
                                        ;           Child Loop BB0_21 Depth 5
                                        ;             Child Loop BB0_24 Depth 6
                                        ;             Child Loop BB0_34 Depth 6
	s_ashr_i32 s35, s34, 31
	s_mov_b32 s5, exec_lo
	s_lshl_b64 s[0:1], s[34:35], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s42, s18, s0
	s_addc_u32 s43, s19, s1
	global_load_b32 v1, v7, s[42:43]
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v1
	s_cbranch_execz .LBB0_13
; %bb.4:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_load_b32 s4, s[30:31], 0xc
	v_mov_b32_e32 v3, v0
	s_add_u32 s2, s22, s0
	s_addc_u32 s3, s23, s1
	s_mov_b32 s35, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s4, 0xffff
.LBB0_5:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccnz .LBB0_12
; %bb.6:                                ; %.lr.ph232.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_mov_b32 s4, 0
.LBB0_7:                                ; %.lr.ph232
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_9 Depth 4
	global_load_b32 v1, v7, s[2:3]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v6, s25, s[4:5]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s38, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s39, v2, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s33
	global_store_b32 v[1:2], v20, off
	s_cbranch_vccnz .LBB0_10
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_7 Depth=3
	global_load_b32 v1, v7, s[2:3]
	s_mov_b32 s44, s26
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s25, v6, s[4:5]
	v_mul_lo_u32 v1, s26, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s36, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s37, v2, vcc_lo
.LBB0_9:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v6, s41
	s_add_i32 s44, s44, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s44, 0
	global_store_b32 v[1:2], v6, off
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_cbranch_scc0 .LBB0_9
.LBB0_10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, s25
	s_cbranch_scc0 .LBB0_7
; %bb.11:                               ; %._crit_edge233.loopexit
                                        ;   in Loop: Header=BB0_5 Depth=2
	global_load_b32 v1, v7, s[42:43]
.LBB0_12:                               ; %._crit_edge233
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v3, s6, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v3, v1
	s_or_b32 s35, vcc_lo, s35
	s_and_not1_b32 exec_lo, exec_lo, s35
	s_cbranch_execnz .LBB0_5
.LBB0_13:                               ; %Flow352
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v6, v7, s[42:43]
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v6
	s_cbranch_execz .LBB0_40
; %bb.14:                               ; %.lr.ph257
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_load_b32 s2, s[30:31], 0xc
	s_add_u32 s44, s22, s0
	s_addc_u32 s45, s23, s1
	v_mov_b32_e32 v21, v0
	s_add_u32 s46, s20, s0
	s_addc_u32 s47, s21, s1
	s_add_u32 s48, s14, s0
	s_addc_u32 s49, s15, s1
	s_mov_b32 s52, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s51, s2, 0xffff
.LBB0_15:                               ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;         Child Loop BB0_19 Depth 4
                                        ;           Child Loop BB0_21 Depth 5
                                        ;             Child Loop BB0_24 Depth 6
                                        ;             Child Loop BB0_34 Depth 6
	global_load_b32 v1, v7, s[44:45]
	s_mov_b32 s53, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v1, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v2, vcc_lo
	global_load_b96 v[1:3], v[1:2], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v8, null, s40, s40, v1
	v_div_scale_f32 v11, vcc_lo, v1, s40, v1
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_mul_f32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v10, v11
	v_fmac_f32_e32 v10, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v10, v11
	v_div_fmas_f32 v8, v8, v9, v10
	v_cvt_f64_f32_e32 v[10:11], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v8, v8, s40, v1
	v_cvt_i32_f32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v8, v12
	v_mul_f32_e32 v8, s40, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[8:9], v8
	v_add_f64 v[8:9], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, v[8:9], v[10:11]
	v_cndmask_b32_e64 v8, 2, 1, vcc_lo
	v_cndmask_b32_e64 v9, -1, -2, vcc_lo
	v_add_nc_u32_e32 v10, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v12
	v_min_i32_e32 v22, v10, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v8, 0, v9
	v_cmpx_le_i32_e64 v8, v22
	s_cbranch_execz .LBB0_39
; %bb.16:                               ; %.lr.ph253
                                        ;   in Loop: Header=BB0_15 Depth=2
	v_div_scale_f32 v6, null, s40, s40, v3
	v_div_scale_f32 v9, null, s40, s40, v2
	v_div_scale_f32 v23, vcc_lo, v3, s40, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v10, v6
	v_rcp_f32_e32 v11, v9
	s_mov_b32 s54, 0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v6, v10, 1.0
	v_fma_f32 v13, -v9, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v12, v10 :: v_dual_fmac_f32 v11, v13, v11
	v_div_scale_f32 v12, s0, v2, s40, v2
	v_dual_mul_f32 v13, v23, v10 :: v_dual_mul_f32 v24, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v6, v13, v23
	v_fma_f32 v26, -v9, v24, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, v25, v10 :: v_dual_fmac_f32 v24, v26, v11
	v_cvt_f64_f32_e32 v[25:26], v2
	v_fma_f32 v6, -v6, v13, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v9, v24, v12
	v_div_fmas_f32 v6, v6, v10, v13
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v9, v9, v11, v24
	v_cvt_f64_f32_e32 v[23:24], v3
	v_div_fixup_f32 v6, v6, s40, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v9, v9, s40, v2
	v_cvt_i32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v13, v9
	v_cvt_f32_i32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v9, v13
	v_mul_f32_e32 v11, s40, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[11:12], v11
	v_add_f64 v[11:12], v[4:5], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s0, v[11:12], v[23:24]
	v_cndmask_b32_e64 v12, 2, 1, s0
	v_mul_f32_e32 v9, s40, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[9:10], v9
	v_add_f64 v[9:10], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, v[9:10], v[25:26]
	v_cndmask_b32_e64 v9, -1, -2, s0
	v_add_nc_u32_e32 v9, v9, v6
	v_add_nc_u32_e32 v6, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v23, 0, v9
	v_min_i32_e32 v26, v6, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s1, v23, v26
	v_cndmask_b32_e64 v10, -1, -2, vcc_lo
	v_cndmask_b32_e64 v11, 2, 1, vcc_lo
	v_add_nc_u32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v11, v13
	v_max_i32_e32 v24, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_i32_e32 v25, v11, v18
	v_cmp_le_i32_e64 s0, v24, v25
.LBB0_17:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_19 Depth 4
                                        ;           Child Loop BB0_21 Depth 5
                                        ;             Child Loop BB0_24 Depth 6
                                        ;             Child Loop BB0_34 Depth 6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s55, s0
	s_cbranch_execz .LBB0_37
; %bb.18:                               ; %.lr.ph248.preheader
                                        ;   in Loop: Header=BB0_17 Depth=3
	v_mov_b32_e32 v9, v24
	s_mov_b32 s56, 0
.LBB0_19:                               ; %.lr.ph248
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_17 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_21 Depth 5
                                        ;             Child Loop BB0_24 Depth 6
                                        ;             Child Loop BB0_34 Depth 6
	s_and_saveexec_b32 s57, s1
	s_cbranch_execz .LBB0_36
; %bb.20:                               ; %.lr.ph243.preheader
                                        ;   in Loop: Header=BB0_19 Depth=4
	v_mov_b32_e32 v27, v23
	s_mov_b32 s58, 0
.LBB0_21:                               ; %.lr.ph243
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_17 Depth=3
                                        ;         Parent Loop BB0_19 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB0_24 Depth 6
                                        ;             Child Loop BB0_34 Depth 6
	global_load_b32 v10, v7, s[46:47]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	v_readfirstlane_b32 s5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[10:11]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b64 v[28:29], v[11:12], off
	v_mad_u64_u32 v[11:12], null, v27, v16, v[9:10]
	v_mov_b32_e32 v10, -1
	v_mad_u64_u32 v[12:13], null, v11, v15, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	s_waitcnt vmcnt(0)
	v_cmpx_le_i64_e64 v[28:29], v[12:13]
	s_cbranch_execz .LBB0_29
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=5
	global_load_b32 v6, v7, s[48:49]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s5, s2
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[60:61], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s60, s12, s60
	s_addc_u32 s61, s13, s61
	global_load_b64 v[10:11], v7, s[60:61]
	s_waitcnt vmcnt(0)
	v_cmp_ge_i64_e32 vcc_lo, v[10:11], v[12:13]
	v_mov_b32_e32 v10, -1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_28
; %bb.23:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_21 Depth=5
	v_mov_b32_e32 v6, s2
	v_mov_b32_e32 v28, s5
	s_mov_b32 s5, 0
                                        ; implicit-def: $sgpr6
.LBB0_24:                               ; %.preheader.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_17 Depth=3
                                        ;         Parent Loop BB0_19 Depth=4
                                        ;           Parent Loop BB0_21 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v10, -1
	s_or_b32 s6, s6, exec_lo
	s_mov_b32 s59, exec_lo
	v_cmpx_ge_i32_e64 v6, v28
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_24 Depth=6
	v_sub_nc_u32_e32 v10, v6, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v11, 31, v10
	v_add_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 1, v10
	v_add_nc_u32_e32 v10, v10, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_nc_u32_e32 v31, -1, v10
	v_lshlrev_b64 v[29:30], 3, v[10:11]
	v_add_nc_u32_e32 v11, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v29, vcc_lo, s12, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v30, vcc_lo
	global_load_b64 v[29:30], v[29:30], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i64_e64 s2, v[29:30], v[12:13]
	v_cmp_eq_u64_e32 vcc_lo, v[29:30], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v11, s2
	v_cmp_gt_i64_e64 s2, v[29:30], v[12:13]
	v_cndmask_b32_e64 v6, v6, v31, s2
	s_and_not1_b32 s2, s6, exec_lo
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s2, s6
.LBB0_26:                               ; %Flow338
                                        ;   in Loop: Header=BB0_24 Depth=6
	s_or_b32 exec_lo, exec_lo, s59
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s6
	s_or_b32 s5, s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_24
; %bb.27:                               ; %Flow339
                                        ;   in Loop: Header=BB0_21 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_28:                               ; %Flow340
                                        ;   in Loop: Header=BB0_21 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_29:                               ; %_Z13binary_searchPKxiix.exit
                                        ;   in Loop: Header=BB0_21 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b32 s59, exec_lo
	v_cmpx_lt_i32_e32 -1, v10
	s_cbranch_execz .LBB0_35
; %bb.30:                               ;   in Loop: Header=BB0_21 Depth=5
	v_lshl_add_u32 v6, v10, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[6:7]
	v_add_co_u32 v11, vcc_lo, s8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	global_load_b96 v[11:13], v[11:12], off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v6, v11, v1 :: v_dual_sub_f32 v13, v13, v3
	v_add_f32_e32 v11, 0x358637bd, v6
	v_sub_f32_e32 v12, v12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, 0x358637bd, v13 :: v_dual_mul_f32 v13, v11, v11
	v_dual_add_f32 v12, 0x358637bd, v12 :: v_dual_mul_f32 v29, v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, v13, v14
	v_mul_f32_e32 v28, v12, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s3, v29, v14
	v_cmp_lt_f32_e64 s2, v28, v14
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_35
; %bb.31:                               ;   in Loop: Header=BB0_21 Depth=5
	v_cvt_f64_f32_e64 v[28:29], |v11|
	v_cvt_f64_f32_e64 v[30:31], |v12|
	v_cvt_f64_f32_e64 v[32:33], |v6|
	v_cvt_f64_f32_e32 v[34:35], v11
	v_cvt_f64_f32_e32 v[36:37], v12
	v_cvt_f64_f32_e32 v[38:39], v6
	global_load_b32 v13, v7, s[44:45]
	v_div_scale_f32 v64, null, s40, s40, v11
	v_div_scale_f32 v65, null, s40, s40, v12
	v_div_scale_f32 v67, null, s40, s40, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v66, v64
	v_rcp_f32_e32 v68, v65
	s_waitcnt_depctr 0xfff
	v_fma_f32 v69, -v64, v66, 1.0
	v_mul_f64 v[28:29], v[28:29], 0.5
	v_mul_f64 v[30:31], v[30:31], 0.5
	v_mul_f64 v[32:33], v[32:33], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[40:41], null, v[34:35], v[34:35], v[28:29]
	v_div_scale_f64 v[42:43], null, v[36:37], v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[44:45], null, v[38:39], v[38:39], v[32:33]
	v_div_scale_f64 v[58:59], s2, v[28:29], v[34:35], v[28:29]
	v_rcp_f64_e32 v[46:47], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[48:49], v[42:43]
	v_rcp_f64_e32 v[50:51], v[44:45]
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[52:53], -v[40:41], v[46:47], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[42:43], v[48:49], 1.0
	v_fma_f64 v[56:57], -v[44:45], v[50:51], 1.0
	v_fma_f64 v[46:47], v[46:47], v[52:53], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[54:55], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[50:51], v[50:51], v[56:57], v[50:51]
	v_fma_f64 v[52:53], -v[40:41], v[46:47], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[54:55], -v[42:43], v[48:49], 1.0
	v_fma_f64 v[56:57], -v[44:45], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[46:47], v[46:47], v[52:53], v[46:47]
	v_div_scale_f64 v[52:53], s3, v[30:31], v[36:37], v[30:31]
	v_fma_f64 v[48:49], v[48:49], v[54:55], v[48:49]
	v_div_scale_f64 v[54:55], s4, v[32:33], v[38:39], v[32:33]
	v_fma_f64 v[50:51], v[50:51], v[56:57], v[50:51]
	v_mul_f64 v[56:57], v[58:59], v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[60:61], v[52:53], v[48:49]
	v_mul_f64 v[62:63], v[54:55], v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], -v[40:41], v[56:57], v[58:59]
	v_rcp_f32_e32 v58, v67
	v_div_scale_f32 v59, vcc_lo, v11, s40, v11
	v_fma_f64 v[42:43], -v[42:43], v[60:61], v[52:53]
	v_fma_f32 v52, -v65, v68, 1.0
	v_div_scale_f32 v53, s5, v12, s40, v12
	v_fma_f64 v[44:45], -v[44:45], v[62:63], v[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_fmac_f32_e32 v68, v52, v68
	v_fmac_f32_e32 v66, v69, v66
	v_fma_f32 v69, -v67, v58, 1.0
	v_div_scale_f32 v52, s6, v6, s40, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v58, v69, v58
	v_mul_f32_e32 v69, v53, v68
	v_mul_f32_e32 v55, v52, v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v71, -v65, v69, v53
	v_fmac_f32_e32 v69, v71, v68
	v_mul_f32_e32 v70, v59, v66
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v53, -v65, v69, v53
	v_fma_f32 v54, -v64, v70, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v70, v54, v66
	v_fma_f32 v54, -v67, v55, v52
	v_fma_f32 v59, -v64, v70, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v55, v54, v58
	v_div_fmas_f32 v54, v59, v66, v70
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[40:41], v[40:41], v[46:47], v[56:57]
	s_mov_b32 vcc_lo, s5
	v_fma_f32 v47, -v67, v55, v52
	v_div_fmas_f32 v46, v53, v68, v69
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v11, v54, s40, v11
	v_div_fmas_f64 v[42:43], v[42:43], v[48:49], v[60:61]
	s_mov_b32 vcc_lo, s6
	v_div_fixup_f32 v46, v46, s40, v12
	v_div_fmas_f32 v48, v47, v58, v55
	s_mov_b32 vcc_lo, s4
	v_cvt_f64_f32_e32 v[11:12], v11
	v_div_fmas_f64 v[44:45], v[44:45], v[50:51], v[62:63]
	v_cvt_f64_f32_e32 v[46:47], v46
	v_div_fixup_f32 v6, v48, s40, v6
	v_div_fixup_f64 v[28:29], v[40:41], v[34:35], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cvt_f64_f32_e32 v[34:35], v6
	v_div_fixup_f64 v[30:31], v[42:43], v[36:37], v[30:31]
	v_div_fixup_f64 v[32:33], v[44:45], v[38:39], v[32:33]
	v_add_f64 v[11:12], v[28:29], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[30:31], v[46:47]
	v_add_f64 v[30:31], v[32:33], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v6, v[11:12]
	v_cvt_f32_f64_e32 v11, v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v12, v[30:31]
	v_trunc_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v28, v11
	v_cvt_i32_f32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v6, v28
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v28, v13, v21
	v_mul_lo_u32 v13, s7, v11
	v_trunc_f32_e32 v12, v12
	v_mul_lo_u32 v30, v6, s28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v31, v28, s25
	v_cvt_i32_f32_e32 v29, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v12, v13, s50, v30
	v_add3_u32 v12, v12, v29, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s38, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s39, v13, vcc_lo
	global_load_b32 v30, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 0, v30
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_35
; %bb.32:                               ;   in Loop: Header=BB0_21 Depth=5
	s_and_not1_b32 vcc_lo, exec_lo, s33
	global_store_b32 v[12:13], v10, off
	s_cbranch_vccnz .LBB0_35
; %bb.33:                               ; %.lr.ph239
                                        ;   in Loop: Header=BB0_21 Depth=5
	v_mad_u64_u32 v[12:13], null, s28, v28, v[11:12]
	s_mov_b32 s2, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[30:31], null, s28, v12, v[6:7]
	v_mul_lo_u32 v6, s28, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, s50, v29, v6
	v_mul_lo_u32 v11, s26, v6
	v_mul_lo_u32 v6, v10, s26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[10:11], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[6:7]
	v_add_co_u32 v10, vcc_lo, s36, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s37, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s10, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
.LBB0_34:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_17 Depth=3
                                        ;         Parent Loop BB0_19 Depth=4
                                        ;           Parent Loop BB0_21 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	global_load_b32 v6, v[12:13], off
	v_add_co_u32 v12, vcc_lo, v12, 4
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 0
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v6, off
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_cbranch_scc1 .LBB0_34
.LBB0_35:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_21 Depth=5
	s_or_b32 exec_lo, exec_lo, s59
	v_add_nc_u32_e32 v6, 1, v27
	v_cmp_ge_i32_e32 vcc_lo, v27, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v27, v6
	s_or_b32 s58, vcc_lo, s58
	s_and_not1_b32 exec_lo, exec_lo, s58
	s_cbranch_execnz .LBB0_21
.LBB0_36:                               ; %Flow342
                                        ;   in Loop: Header=BB0_19 Depth=4
	s_or_b32 exec_lo, exec_lo, s57
	v_add_nc_u32_e32 v6, 1, v9
	v_cmp_ge_i32_e32 vcc_lo, v9, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v9, v6
	s_or_b32 s56, vcc_lo, s56
	s_and_not1_b32 exec_lo, exec_lo, s56
	s_cbranch_execnz .LBB0_19
.LBB0_37:                               ; %Flow344
                                        ;   in Loop: Header=BB0_17 Depth=3
	s_or_b32 exec_lo, exec_lo, s55
	v_add_nc_u32_e32 v6, 1, v8
	v_cmp_ge_i32_e32 vcc_lo, v8, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v8, v6
	s_or_b32 s54, vcc_lo, s54
	s_and_not1_b32 exec_lo, exec_lo, s54
	s_cbranch_execnz .LBB0_17
; %bb.38:                               ; %._crit_edge254.loopexit
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s54
	global_load_b32 v6, v7, s[42:43]
.LBB0_39:                               ; %Flow345
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s53
	v_add_nc_u32_e32 v21, s51, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v21, v6
	s_or_b32 s52, vcc_lo, s52
	s_and_not1_b32 exec_lo, exec_lo, s52
	s_cbranch_execnz .LBB0_15
.LBB0_40:                               ; %Flow347
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s35
	s_add_i32 s34, s27, s34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s34, s24
	s_cbranch_scc0 .LBB0_3
.LBB0_41:                               ; %.loopexit228
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 72
		.amdhsa_next_free_sgpr 62
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_, .Lfunc_end0-_Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3372
; NumSgprs: 64
; NumVgprs: 72
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 64
; NumVGPRsForWavesPerEU: 72
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf ; -- Begin function _Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.globl	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
	.p2align	8
	.type	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf,@function
_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf: ; @_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s4, 0
	s_cselect_b32 s7, -1, 0
	s_cmp_eq_u32 s5, 0
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s9, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, s9, s8
	s_or_b32 s7, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_mov_b32 s7, -1
	s_cbranch_vccz .LBB1_13
; %bb.1:
	s_load_b32 s7, s[2:3], 0xc
	v_cvt_f32_i32_e32 v1, s4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s7, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s7
	v_div_scale_f32 v3, null, v2, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v7, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v4
	v_fma_f32 v3, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v6
	v_div_fixup_f32 v1, v3, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ceil_f32_e32 v1, v1
	v_cvt_i32_f32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, s15, v5
	s_cbranch_vccnz .LBB1_12
; %bb.2:                                ; %.lr.ph65
	s_load_b32 s12, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	s_cmp_lt_i32 s5, 1
	s_cselect_b32 s13, -1, 0
	s_cmp_lt_i32 s6, 1
	s_cselect_b32 s14, -1, 0
	s_xor_b32 s13, s13, -1
	s_xor_b32 s14, s14, -1
.LBB1_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
                                        ;       Child Loop BB1_7 Depth 3
                                        ;         Child Loop BB1_8 Depth 4
	v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_and_b32 s17, vcc_lo, s13
	s_and_saveexec_b32 s16, s17
	s_cbranch_execz .LBB1_11
; %bb.4:                                ; %.lr.ph63
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_mul_lo_u32 v6, v1, s5
	s_mov_b32 s17, 0
.LBB1_5:                                ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_7 Depth 3
                                        ;         Child Loop BB1_8 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s17, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	s_and_b32 s19, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s18, s19
	s_cbranch_execz .LBB1_10
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_5 Depth=2
	v_mul_lo_u32 v7, v2, s6
	v_mul_lo_u32 v8, v1, s6
	s_mov_b32 s19, 0
.LBB1_7:                                ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_8 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s19, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, s19, v7
	s_mov_b32 s20, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v9, vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v4, v[1:2], off
.LBB1_8:                                ; %atomicrmw.start
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ;       Parent Loop BB1_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v4, v9
	global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v3, v4
	v_mov_b32_e32 v4, v3
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB1_8
; %bb.9:                                ; %atomicrmw.end
                                        ;   in Loop: Header=BB1_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s19, s19, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s19, s6
	s_cbranch_scc1 .LBB1_7
.LBB1_10:                               ; %Flow256
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s5
	s_cbranch_scc1 .LBB1_5
.LBB1_11:                               ; %Flow258
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s15, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, s15, v5
	s_cbranch_vccnz .LBB1_3
.LBB1_12:                               ; %Flow260
	s_mov_b32 s7, 0
.LBB1_13:                               ; %Flow341
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB1_155
; %bb.14:
	s_load_b64 s[2:3], s[2:3], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v2
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v7
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_20
; %bb.15:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[10:11], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[4:5], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v10
	v_and_b32_e32 v1, v1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[8:9], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[10:11]
	s_cbranch_execz .LBB1_19
; %bb.16:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB1_17:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v6, v5, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[8:9]
	v_mad_u64_u32 v[4:5], null, v6, 24, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v4
	global_load_b64 v[8:9], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_17
; %bb.18:                               ; %Flow338
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_19:                               ; %Flow340
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_20:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v8, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[9:10], v8, s[2:3] offset:40
	global_load_b128 v[3:6], v8, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB1_22
; %bb.21:
	v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v8
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v4, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[0:1], v[9:12], off offset:8
.LBB1_22:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[7:8]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	v_dual_mov_b32 v7, 33 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v8
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v14, s15
	v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s14
	s_clause 0x3
	global_store_b128 v[0:1], v[7:10], off
	global_store_b128 v[0:1], v[11:14], off offset:16
	global_store_b128 v[0:1], v[11:14], off offset:32
	global_store_b128 v[0:1], v[11:14], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_30
; %bb.23:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
	global_load_b64 v[5:6], v11, s[2:3] offset:40
	v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, s5, v6
	v_and_b32_e32 v5, s4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v7, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v7, v6
	v_add_co_u32 v9, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v6, vcc_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v11, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[7:8], v[14:15]
	s_cbranch_execz .LBB1_26
; %bb.24:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB1_25:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5
	s_sleep 1
	global_store_b64 v[9:10], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[5:8], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_25
.LBB1_26:                               ; %Flow336
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v8, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v7, s10, 0
	global_load_b64 v[5:6], v8, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v7
	s_cbranch_execz .LBB1_28
; %bb.27:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v7, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[7:8], off offset:8
.LBB1_28:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB1_30
; %bb.29:
	global_load_b32 v5, v[5:6], off offset:24
	v_mov_b32_e32 v6, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[5:6], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_30:                               ; %Flow337
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v3, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_31:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_31 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB1_33:                               ;   in Loop: Header=BB1_31 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_35
; %bb.34:                               ;   in Loop: Header=BB1_31 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_36
.LBB1_35:                               ;   in Loop: Header=BB1_31 Depth=1
	s_mov_b32 s1, -1
.LBB1_36:                               ; %Flow331
                                        ;   in Loop: Header=BB1_31 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_31
; %bb.37:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_41
; %bb.38:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[2:3] offset:40
	global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
	global_load_b64 v[7:8], v9, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_41
; %bb.39:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_40:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_40
.LBB1_41:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_mov_b32 s0, -1
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB1_127
; %bb.42:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v8, v1 :: v_dual_and_b32 v7, -3, v0
	v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v5, 2
	v_mov_b32_e32 v6, 1
	s_mov_b64 s[6:7], 43
.LBB1_43:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_46 Depth 2
                                        ;     Child Loop BB1_53 Depth 2
                                        ;     Child Loop BB1_61 Depth 2
                                        ;     Child Loop BB1_69 Depth 2
                                        ;     Child Loop BB1_77 Depth 2
                                        ;     Child Loop BB1_85 Depth 2
                                        ;     Child Loop BB1_93 Depth 2
                                        ;     Child Loop BB1_101 Depth 2
                                        ;     Child Loop BB1_109 Depth 2
                                        ;     Child Loop BB1_115 Depth 2
                                        ;     Child Loop BB1_124 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB1_48
; %bb.44:                               ;   in Loop: Header=BB1_43 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB1_47
; %bb.45:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB1_46:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v3, v28, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v9, v3, v9
	v_or_b32_e32 v10, v4, v10
	s_cbranch_scc1 .LBB1_46
.LBB1_47:                               ; %Flow306
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB1_48:                               ; %Flow308
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB1_50
; %bb.49:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[9:10], v28, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB1_50:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB1_55
; %bb.51:                               ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB1_54
; %bb.52:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB1_53:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v11, v3, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB1_53
.LBB1_54:                               ; %Flow301
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB1_56
.LBB1_55:                               ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr14
.LBB1_56:                               ; %Flow303
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_58
; %bb.57:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[11:12], v28, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_58:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB1_63
; %bb.59:                               ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_62
; %bb.60:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB1_61:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB1_61
.LBB1_62:                               ; %Flow296
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB1_64
.LBB1_63:                               ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB1_64:                               ; %Flow298
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_66
; %bb.65:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[13:14], v28, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_66:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB1_71
; %bb.67:                               ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB1_70
; %bb.68:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB1_69:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB1_69
.LBB1_70:                               ; %Flow291
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB1_72
.LBB1_71:                               ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr14
.LBB1_72:                               ; %Flow293
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_74
; %bb.73:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[15:16], v28, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_74:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB1_79
; %bb.75:                               ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_78
; %bb.76:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB1_77:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB1_77
.LBB1_78:                               ; %Flow286
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB1_80
.LBB1_79:                               ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB1_80:                               ; %Flow288
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_82
; %bb.81:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[17:18], v28, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_82:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB1_87
; %bb.83:                               ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB1_86
; %bb.84:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB1_85:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB1_85
.LBB1_86:                               ; %Flow281
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB1_88
.LBB1_87:                               ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr14
.LBB1_88:                               ; %Flow283
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_90
; %bb.89:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[19:20], v28, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_90:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB1_95
; %bb.91:                               ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_94
; %bb.92:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB1_93:                               ; %.preheader.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v3, v28, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v21, v3, v21
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB1_93
.LBB1_94:                               ; %Flow276
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB1_96
.LBB1_95:                               ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s10, -1
.LBB1_96:                               ; %Flow278
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_98
; %bb.97:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[21:22], v28, s[0:1]
.LBB1_98:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	v_mov_b32_e32 v27, v2
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v27
	v_cmp_eq_u32_e64 s0, s0, v27
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_104
; %bb.99:                               ;   in Loop: Header=BB1_43 Depth=1
	global_load_b64 v[25:26], v28, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v28, s[2:3] offset:40
	global_load_b64 v[23:24], v28, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v26
	v_and_b32_e32 v3, v3, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v29, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v29, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v23, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v24, v4, vcc_lo
	global_load_b64 v[23:24], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v28, v[23:26], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[25:26]
	s_cbranch_execz .LBB1_103
; %bb.100:                              ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s11, 0
.LBB1_101:                              ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[23:24], v28, s[2:3] offset:40
	global_load_b64 v[29:30], v28, s[2:3]
	v_dual_mov_b32 v26, v4 :: v_dual_mov_b32 v25, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v23, v23, v25
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v23, 24, v[29:30]
	v_and_b32_e32 v29, v24, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[23:24], null, v29, 24, v[4:5]
	v_mov_b32_e32 v4, v23
	global_load_b64 v[23:24], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v28, v[23:26], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[25:26]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_101
; %bb.102:                              ; %Flow271
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_103:                              ; %Flow273
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_104:                              ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v28, s[2:3] offset:40
	global_load_b128 v[23:26], v28, s[2:3]
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v29
	v_readfirstlane_b32 s13, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB1_106
; %bb.105:                              ;   in Loop: Header=BB1_43 Depth=1
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, v28
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v29, vcc_lo, v23, s15
	v_add_co_ci_u32_e32 v30, vcc_lo, s16, v24, vcc_lo
	global_store_b128 v[29:30], v[3:6], off offset:8
.LBB1_106:                              ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v3, 2, v7
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_cndmask_b32_e32 v7, v3, v7, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[27:28]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v25, vcc_lo, v25, s12
	v_add_co_ci_u32_e32 v26, vcc_lo, s13, v26, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v25, v3
	v_and_or_b32 v7, 0xffffff1f, v7, s16
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[11:14], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[19:22], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_114
; %bb.107:                              ;   in Loop: Header=BB1_43 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v28, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v28, s[2:3] offset:40
	v_dual_mov_b32 v13, s10 :: v_dual_mov_b32 v14, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v7
	v_readfirstlane_b32 s17, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v11, vcc_lo, v23, s16
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v24, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v28, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB1_110
; %bb.108:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s16, 0
.LBB1_109:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
	s_sleep 1
	global_store_b64 v[11:12], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v28, v[7:10], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_109
.LBB1_110:                              ; %Flow269
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[7:8], v28, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v9, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v9
	s_cbranch_execz .LBB1_112
; %bb.111:                              ;   in Loop: Header=BB1_43 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v27, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[27:28], off offset:8
.LBB1_112:                              ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB1_114
; %bb.113:                              ;   in Loop: Header=BB1_43 Depth=1
	global_load_b32 v27, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v27
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[27:28], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_114:                              ; %Flow270
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v7, vcc_lo, v23, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_115:                              ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v9, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_117
; %bb.116:                              ;   in Loop: Header=BB1_115 Depth=2
	global_load_b32 v9, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v9, 1, v9
.LBB1_117:                              ;   in Loop: Header=BB1_115 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v9
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_119
; %bb.118:                              ;   in Loop: Header=BB1_115 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_120
.LBB1_119:                              ;   in Loop: Header=BB1_115 Depth=2
	s_mov_b32 s1, -1
.LBB1_120:                              ; %Flow264
                                        ;   in Loop: Header=BB1_115 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_115
; %bb.121:                              ;   in Loop: Header=BB1_43 Depth=1
	global_load_b128 v[7:10], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_125
; %bb.122:                              ;   in Loop: Header=BB1_43 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v28, s[2:3] offset:40
	global_load_b64 v[13:14], v28, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v28, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
	v_and_b32_e32 v4, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v9, v3
	v_mul_hi_u32 v15, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v4, v15, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v28, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_125
; %bb.123:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_mov_b32 s0, 0
.LBB1_124:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v28, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_124
.LBB1_125:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_eq_u64 s[6:7], 0
	s_cbranch_scc0 .LBB1_43
; %bb.126:                              ; %Flow309
	s_mov_b32 s0, 0
.LBB1_127:                              ; %Flow325
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_155
; %bb.128:
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_134
; %bb.129:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB1_133
; %bb.130:                              ; %.preheader3.i.i.i45.preheader
	s_mov_b32 s5, 0
.LBB1_131:                              ; %.preheader3.i.i.i45
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_131
; %bb.132:                              ; %Flow322
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_133:                              ; %Flow324
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_134:                              ; %.loopexit4.i.i.i40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB1_136
; %bb.135:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB1_136:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v9, s15
	v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_144
; %bb.137:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v6, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB1_140
; %bb.138:                              ; %.preheader1.i.i.i43.preheader
	s_mov_b32 s10, 0
.LBB1_139:                              ; %.preheader1.i.i.i43
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_139
.LBB1_140:                              ; %Flow320
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_142
; %bb.141:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_142:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_144
; %bb.143:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_144:                              ; %Flow321
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_145:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_147
; %bb.146:                              ;   in Loop: Header=BB1_145 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_147:                              ;   in Loop: Header=BB1_145 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_149
; %bb.148:                              ;   in Loop: Header=BB1_145 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_150
.LBB1_149:                              ;   in Loop: Header=BB1_145 Depth=1
	s_mov_b32 s1, -1
.LBB1_150:                              ; %Flow315
                                        ;   in Loop: Header=BB1_145 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_145
; %bb.151:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_155
; %bb.152:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_155
; %bb.153:                              ; %.preheader.i.i.i42.preheader
	s_mov_b32 s0, 0
.LBB1_154:                              ; %.preheader.i.i.i42
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_154
.LBB1_155:                              ; %__ockl_printf_append_string_n.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf, .Lfunc_end1-_Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5916
; NumSgprs: 23
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"Voxel sample grad Op exited unexpectedly.\n"
	.size	.str, 43

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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    .language_version:
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    .symbol:         _Z32voxel_sampling_binary_gpu_kerneliiiiifffffPKfS0_PKxPKiS0_S4_PiS5_PfS5_.kd
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    .language:       OpenCL C
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    .name:           _Z37voxel_sampling_binary_grad_gpu_kerneliiiPKiPKfPf
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
