#include <stdio.h>

#define QUEENS 10

__device__
void kiir(char *A)
{
    char s[QUEENS*21 + 1];
    int k = 0;

    for(int i = 0; i < QUEENS; i++)
    {
        for(int j = 0; j < QUEENS; j++)
        {
            if(A[i] == j)
                s[k++] =  'Q';
            else
                s[k++] = '.';

            s[k++] = ' ';
        }
        s[k++] = '\n';
    }

    s[k] = '\0';

    printf("%s\n", s);
}

__global__
void queen(int *db, const int n)
{
    {
	bool B[QUEENS];
	
	for(int i = 0; i < QUEENS; i++)
	    B[i] = 0;
	
	B[threadIdx.x] = 1;
	B[threadIdx.y] = 1;
	B[threadIdx.z] = 1;
	B[blockIdx.x/10] = 1;
	B[blockIdx.x%10] = 1;
	B[blockIdx.y/10] = 1;
	B[blockIdx.y%10] = 1;
	B[blockIdx.z/10] = 1;
	B[blockIdx.z%10] = 1;
	B[n] = 1;
	
	for(int i = 0; i < QUEENS; i++)
	    if(B[i] == 0)
		return;
    }
    
    char A[QUEENS];
    
    A[0] = threadIdx.x;
    A[1] = threadIdx.y;
    A[2] = threadIdx.z;
    A[3] = blockIdx.x/10;
    A[4] = blockIdx.x%10;
    A[5] = blockIdx.y/10;
    A[6] = blockIdx.y%10;
    A[7] = blockIdx.z/10;
    A[8] = blockIdx.z%10;
    A[9] = n;

    for(int i = 0; i < QUEENS - 1; i++)
        for(int j = i + 1; j < QUEENS; j++)
            if(abs(i - j) == abs(A[i] - A[j]))
                return;
	    
    atomicAdd(db, 1);
    printf("%d.\n", *db);
    kiir(A);
}

int
main()
{
    int h = 0, *d;
    cudaMalloc((void**) &d, sizeof(int));
    cudaMemcpy(d, &h, sizeof(int), cudaMemcpyHostToDevice);

    dim3 blocksPerGrid(100, 100, 100);
    dim3 threadsPerBlock(10, 10, 10);
    
    for(int i = 0; i < QUEENS; i++)
	queen<<<blocksPerGrid, threadsPerBlock>>>(d, i);

    cudaMemcpy(&h, d, sizeof(int), cudaMemcpyDeviceToHost);
    cudaFree(d);
    cudaDeviceReset();

    cudaError_t error = cudaGetLastError();
    if(error != cudaSuccess)
    {
        fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(error));
        return -1;
    }

    fprintf(stderr, "Solutions: %d\n", h);

    fprintf(stderr, "\nDone\n");
    return 0;
}

	.file	"tmpxft_0038a98e_00000000-6_queen.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4kiirPc
	.type	_Z4kiirPc, @function
_Z4kiirPc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z4kiirPc, .-_Z4kiirPc
	.globl	_Z25__device_stub__Z5queenPiiPii
	.type	_Z25__device_stub__Z5queenPiiPii, @function
_Z25__device_stub__Z5queenPiiPii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5queenPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z25__device_stub__Z5queenPiiPii, .-_Z25__device_stub__Z5queenPiiPii
	.globl	_Z5queenPii
	.type	_Z5queenPii, @function
_Z5queenPii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z5queenPiiPii
	.cfi_endproc
.LFE2054:
	.size	_Z5queenPii, .-_Z5queenPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: %s\n"
.LC1:
	.string	"Solutions: %d\n"
.LC2:
	.string	"\nDone\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$4, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	xorl	%eax, %eax
	leaq	4(%rsp), %rbp
	movl	%eax, 4(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$100, 24(%rsp)
	movabsq	$429496729700, %rax
	movq	%rax, 16(%rsp)
	movabsq	$42949672970, %rax
	movq	%rax, 28(%rsp)
	movl	$10, 36(%rsp)
.L12:
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z25__device_stub__Z5queenPiiPii
.L11:
	incl	%ebx
	cmpl	$10, %ebx
	jne	.L12
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L13
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %eax
	jmp	.L10
.L13:
	movl	4(%rsp), %ecx
	movq	stderr(%rip), %rdi
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	xorl	%eax, %eax
.L10:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z5queenPii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5queenPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

#define QUEENS 10

__device__
void kiir(char *A)
{
    char s[QUEENS*21 + 1];
    int k = 0;

    for(int i = 0; i < QUEENS; i++)
    {
        for(int j = 0; j < QUEENS; j++)
        {
            if(A[i] == j)
                s[k++] =  'Q';
            else
                s[k++] = '.';

            s[k++] = ' ';
        }
        s[k++] = '\n';
    }

    s[k] = '\0';

    printf("%s\n", s);
}

__global__
void queen(int *db, const int n)
{
    {
	bool B[QUEENS];
	
	for(int i = 0; i < QUEENS; i++)
	    B[i] = 0;
	
	B[threadIdx.x] = 1;
	B[threadIdx.y] = 1;
	B[threadIdx.z] = 1;
	B[blockIdx.x/10] = 1;
	B[blockIdx.x%10] = 1;
	B[blockIdx.y/10] = 1;
	B[blockIdx.y%10] = 1;
	B[blockIdx.z/10] = 1;
	B[blockIdx.z%10] = 1;
	B[n] = 1;
	
	for(int i = 0; i < QUEENS; i++)
	    if(B[i] == 0)
		return;
    }
    
    char A[QUEENS];
    
    A[0] = threadIdx.x;
    A[1] = threadIdx.y;
    A[2] = threadIdx.z;
    A[3] = blockIdx.x/10;
    A[4] = blockIdx.x%10;
    A[5] = blockIdx.y/10;
    A[6] = blockIdx.y%10;
    A[7] = blockIdx.z/10;
    A[8] = blockIdx.z%10;
    A[9] = n;

    for(int i = 0; i < QUEENS - 1; i++)
        for(int j = i + 1; j < QUEENS; j++)
            if(abs(i - j) == abs(A[i] - A[j]))
                return;
	    
    atomicAdd(db, 1);
    printf("%d.\n", *db);
    kiir(A);
}

int
main()
{
    int h = 0, *d;
    hipMalloc((void**) &d, sizeof(int));
    hipMemcpy(d, &h, sizeof(int), hipMemcpyHostToDevice);

    dim3 blocksPerGrid(100, 100, 100);
    dim3 threadsPerBlock(10, 10, 10);
    
    for(int i = 0; i < QUEENS; i++)
	queen<<<blocksPerGrid, threadsPerBlock>>>(d, i);

    hipMemcpy(&h, d, sizeof(int), hipMemcpyDeviceToHost);
    hipFree(d);
    hipDeviceReset();

    hipError_t error = hipGetLastError();
    if(error != hipSuccess)
    {
        fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(error));
        return -1;
    }

    fprintf(stderr, "Solutions: %d\n", h);

    fprintf(stderr, "\nDone\n");
    return 0;
}

	.text
	.file	"queen.hip"
	.globl	_Z20__device_stub__queenPii     # -- Begin function _Z20__device_stub__queenPii
	.type	_Z20__device_stub__queenPii,@function
_Z20__device_stub__queenPii:            # @_Z20__device_stub__queenPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5queenPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__queenPii, .Lfunc_end0-_Z20__device_stub__queenPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	12(%rsp), %rbx
	movl	$0, (%rbx)
	leaq	16(%rsp), %r14
	movl	$4, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
	movabsq	$429496729700, %r14             # imm = 0x6400000064
	movabsq	$42949672970, %r15              # imm = 0xA0000000A
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$100, %esi
	movq	%r15, %rdx
	movl	$10, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	16(%rsp), %rdi
	movl	%ebx, %esi
	callq	_Z20__device_stub__queenPii
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	incl	%ebx
	cmpl	$10, %ebx
	jne	.LBB1_1
# %bb.4:
	movq	16(%rsp), %rsi
	leaq	12(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	callq	hipGetLastError
	movq	stderr(%rip), %rbx
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.6:
	movl	12(%rsp), %edx
	xorl	%ebp, %ebp
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
	movl	$6, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB1_7
.LBB1_5:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %ebp
.LBB1_7:
	movl	%ebp, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5queenPii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5queenPii,@object             # @_Z5queenPii
	.section	.rodata,"a",@progbits
	.globl	_Z5queenPii
	.p2align	3, 0x0
_Z5queenPii:
	.quad	_Z20__device_stub__queenPii
	.size	_Z5queenPii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: %s\n"
	.size	.L.str, 16

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Solutions: %d\n"
	.size	.L.str.1, 15

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\nDone\n"
	.size	.L.str.2, 7

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5queenPii"
	.size	.L__unnamed_1, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__queenPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5queenPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	v_or_b32_e32 v2, 2, v0
	v_cmp_eq_u32_e64 s0, 0, v6
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v2, v0, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u64_e32 0, v[7:8]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v11, 2 :: v_dual_and_b32 v6, 2, v10
	v_mov_b32_e32 v30, 0
	v_and_b32_e32 v0, -3, v10
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_mov_b32_e32 v12, 1
	s_mov_b32 s12, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v32, 0, v5 :: v_dual_cndmask_b32 v31, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v31
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v31
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[9:10], 3, v[31:32]
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, v8
	v_mov_b32_e32 v13, v7
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v10, v[13:14]
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v15, 0xffff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v15, v2
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow232
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow234
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow236
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v7
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	s_clause 0x5
	flat_load_u8 v2, v[7:8]
	flat_load_u8 v3, v[7:8] offset:1
	flat_load_u8 v9, v[7:8] offset:2
	flat_load_u8 v10, v[7:8] offset:3
	flat_load_u8 v13, v[7:8] offset:5
	flat_load_u8 v14, v[7:8] offset:4
	v_mov_b32_e32 v16, v30
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v3, 8, v3
	s_clause 0x1
	flat_load_u8 v15, v[7:8] offset:7
	flat_load_d16_hi_u8 v16, v[7:8] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_or_b32_e32 v2, v3, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v3, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v3, 0, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v2, v2, 0, 0
	v_or3_b32 v2, v2, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v15
	v_add_nc_u32_e32 v15, -8, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_or3_b32 v3, v3, v16, v9
	v_add_co_u32 v9, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v15
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v15
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v16, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v15
	flat_load_u8 v16, v[16:17]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v17, s11 :: v_dual_and_b32 v16, 0xffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], s0, v[16:17]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v16, v13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow227
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_15:                               ; %Flow229
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr15
.LBB0_16:                               ; %Flow231
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v13, v[9:10]
	flat_load_u8 v14, v[9:10] offset:1
	flat_load_u8 v16, v[9:10] offset:2
	flat_load_u8 v17, v[9:10] offset:3
	flat_load_u8 v18, v[9:10] offset:5
	flat_load_u8 v19, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v20, v30 :: v_dual_and_b32 v13, 0xffff, v13
	s_clause 0x1
	flat_load_u8 v21, v[9:10] offset:7
	flat_load_d16_hi_u8 v20, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v14, 8, v14
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v16, 16, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v17, 24, v17
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v13, v14, v13
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v14, 8, v18
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v13, v13, v16, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v14, 0, v19, v14
	v_add_nc_u32_e32 v17, -8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v13, v13, 0, 0
	v_or3_b32 v13, v13, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v16, 24, v21
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v14, v14, v20, v16
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	flat_load_u8 v18, v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow222
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_23:                               ; %Flow224
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB0_24:                               ; %Flow226
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v15, v[9:10]
	flat_load_u8 v16, v[9:10] offset:1
	flat_load_u8 v18, v[9:10] offset:2
	flat_load_u8 v19, v[9:10] offset:3
	flat_load_u8 v20, v[9:10] offset:5
	flat_load_u8 v21, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v22, v30 :: v_dual_and_b32 v15, 0xffff, v15
	s_clause 0x1
	flat_load_u8 v23, v[9:10] offset:7
	flat_load_d16_hi_u8 v22, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v16, 8, v16
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v18
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v15, v16, v15
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v16, 8, v20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v15, v15, v18, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v16, 0, v21, v16
	v_add_nc_u32_e32 v19, -8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v15, v15, 0, 0
	v_or3_b32 v15, v15, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v23
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v16, v16, v22, v18
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v19
	flat_load_u8 v20, v[20:21]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v21, s11 :: v_dual_and_b32 v20, 0xffff, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v18, v21, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v20, v17
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow217
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_31:                               ; %Flow219
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr19
.LBB0_32:                               ; %Flow221
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v17, v[9:10]
	flat_load_u8 v18, v[9:10] offset:1
	flat_load_u8 v20, v[9:10] offset:2
	flat_load_u8 v21, v[9:10] offset:3
	flat_load_u8 v22, v[9:10] offset:5
	flat_load_u8 v23, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v24, v30 :: v_dual_and_b32 v17, 0xffff, v17
	s_clause 0x1
	flat_load_u8 v25, v[9:10] offset:7
	flat_load_d16_hi_u8 v24, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v18, 8, v18
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v20, 16, v20
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 24, v21
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v22
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v20, v21
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v23, v18
	v_add_nc_u32_e32 v21, -8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v20, 24, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v24, v20
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	flat_load_u8 v22, v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow212
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_39:                               ; %Flow214
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB0_40:                               ; %Flow216
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v23, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v19, v[9:10]
	flat_load_u8 v20, v[9:10] offset:1
	flat_load_u8 v22, v[9:10] offset:2
	flat_load_u8 v23, v[9:10] offset:3
	flat_load_u8 v24, v[9:10] offset:5
	flat_load_u8 v25, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v26, v30 :: v_dual_and_b32 v19, 0xffff, v19
	s_clause 0x1
	flat_load_u8 v27, v[9:10] offset:7
	flat_load_d16_hi_u8 v26, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v20, 8, v20
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v22
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v23, 24, v23
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v19, v20, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v24
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v19, v19, v22, v23
	s_waitcnt vmcnt(2)
	v_or3_b32 v20, 0, v25, v20
	v_add_nc_u32_e32 v23, -8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v19, v19, 0, 0
	v_or3_b32 v19, v19, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v27
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v20, v20, v26, v22
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v23
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v23
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v24, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v23
	flat_load_u8 v24, v[24:25]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v25, s11 :: v_dual_and_b32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], s0, v[24:25]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v24, v21
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow207
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_47:                               ; %Flow209
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr23
.LBB0_48:                               ; %Flow211
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v21, v[9:10]
	flat_load_u8 v22, v[9:10] offset:1
	flat_load_u8 v24, v[9:10] offset:2
	flat_load_u8 v25, v[9:10] offset:3
	flat_load_u8 v26, v[9:10] offset:5
	flat_load_u8 v27, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v28, v30 :: v_dual_and_b32 v21, 0xffff, v21
	s_clause 0x1
	flat_load_u8 v29, v[9:10] offset:7
	flat_load_d16_hi_u8 v28, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v22, 8, v22
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v24, 16, v24
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 24, v25
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v21, v22, v21
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v26
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v21, v21, v24, v25
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v27, v22
	v_add_nc_u32_e32 v25, -8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, 0, 0
	v_or3_b32 v21, v21, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v24, 24, v29
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v22, v22, v28, v24
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v26, v[9:10]
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v26, 0xffff, v26
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow202
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow204
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_56:                               ; %Flow206
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v23, v[9:10]
	flat_load_u8 v24, v[9:10] offset:1
	flat_load_u8 v25, v[9:10] offset:2
	flat_load_u8 v26, v[9:10] offset:3
	flat_load_u8 v27, v[9:10] offset:5
	flat_load_u8 v28, v[9:10] offset:4
	v_mov_b32_e32 v29, v30
	s_clause 0x1
	flat_load_u8 v34, v[9:10] offset:7
	flat_load_d16_hi_u8 v29, v[9:10] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v9, 0xffff, v23
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v10, 8, v24
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v25
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 8, v27
	v_or_b32_e32 v9, v10, v9
	v_lshlrev_b32_e32 v10, 24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v23, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v10, 0, v28, v24
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v34
	v_or3_b32 v9, v9, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v24, v10, v29, v23
	v_or3_b32 v23, v9, 0, 0
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v33
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v10, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, 24
	v_mul_hi_u32 v34, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v34, v10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v10, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[34:35], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[34:35]
	v_and_b32_e32 v34, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v34, 24, v[10:11]
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow199
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow201
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s14, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s17, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v26, vcc_lo
	v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[34:35], v[9:12], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v9, 0, v1
	v_or_b32_e32 v10, v0, v6
	v_lshl_add_u32 v34, v31, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v10, v0
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_and_b32_e32 v34, 0x1e0, v34
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_and_or_b32 v0, 0xffffff1f, v0, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[0:3], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[4:5]
	s_mul_i32 s7, s17, 24
	s_mul_hi_u32 s15, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s16
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[17:18]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s15, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[13:14], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v30, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow197
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[0:1], v30, s[2:3] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[29:30], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v29, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow198
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s13, s13, s1
	v_add_co_u32 v0, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow192
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[0:3], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v17, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v18 :: v_dual_cndmask_b32 v13, v13, v17
	v_and_b32_e32 v3, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v13, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v17, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v15, v2
	v_mov_b32_e32 v15, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[2:3], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[2:3], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v31
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v32, vcc_lo
	v_add_co_u32 v7, s0, v7, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, v8, v32, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr10
.LBB0_87:                               ; %Flow253
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB0_116
; %bb.88:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[7:8], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[5:6]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB0_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, 24, v[11:12]
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_93:                               ; %Flow251
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v12, v3
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[8:9], v[11:14], off offset:8
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB0_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow247
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow248
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, -1
.LBB0_110:                              ; %Flow242
                                        ;   in Loop: Header=BB0_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_105
; %bb.111:
	global_load_b128 v[0:3], v[6:7], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_115
; %bb.112:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_116:                              ; %Flow254
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5708
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z5queenPii             ; -- Begin function _Z5queenPii
	.globl	_Z5queenPii
	.p2align	8
	.type	_Z5queenPii,@function
_Z5queenPii:                            ; @_Z5queenPii
; %bb.0:
	s_mov_b64 s[18:19], s[0:1]
	s_mov_b64 s[2:3], 0
	s_movk_i32 s32, 0xf0
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_cmp_lg_u32 s2, 5
	v_lshlrev_b16 v10, 8, v10
	s_cselect_b32 vcc_lo, -1, 0
	v_and_b32_e32 v9, 0xff, v9
	v_lshlrev_b16 v6, 8, v6
	v_and_b32_e32 v8, 0xff, v8
	v_lshlrev_b16 v7, 8, v7
	v_lshlrev_b16 v5, 8, v5
	v_or_b32_e32 v9, v9, v10
	v_and_b32_e32 v4, 0xff, v4
	s_cmp_lg_u32 s2, 3
	v_or_b32_e32 v8, v8, v7
	v_and_b32_e32 v3, 0xff, v3
	v_lshlrev_b32_e32 v10, 16, v9
	v_or_b32_e32 v6, v4, v6
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s2, 4
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xffff, v6
	s_cmp_lg_u32 s2, 0
	v_or_b32_e32 v4, v4, v10
	v_lshrrev_b32_e32 v10, 24, v10
	v_and_b32_e32 v7, 0xffff, v5
	v_or_b32_e32 v5, v3, v5
	v_lshlrev_b32_e32 v3, 16, v8
	v_lshrrev_b32_e32 v11, 8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_or_b32_e32 v7, v7, v3
	v_lshrrev_b64 v[3:4], 24, v[3:4]
	v_cndmask_b32_e64 v4, 0, v6, s1
	v_cndmask_b32_e32 v6, 0, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s2, 6
	v_lshrrev_b32_e32 v12, 8, v7
	v_cndmask_b32_e64 v7, 0, v3, s0
	v_cndmask_b32_e32 v3, 0, v5, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s2, 2
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s2, 7
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s2, 1
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s2, 9
	v_cndmask_b32_e32 v5, 0, v12, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s2, 8
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 10
	s_cbranch_scc0 .LBB1_1
; %bb.2:
	v_and_b32_e32 v36, 0x3ff, v0
	v_bfe_u32 v37, v0, 10, 10
	v_bfe_u32 v43, v0, 20, 10
	s_load_b32 s28, s[18:19], 0x8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s5, 9, v36
	v_cmp_ne_u32_e64 s6, 9, v37
	v_cmp_ne_u32_e64 s9, 8, v36
	v_cmp_ne_u32_e64 s10, 8, v37
	v_cmp_ne_u32_e64 s4, 5, v36
	v_cmp_ne_u32_e64 s7, 6, v36
	s_and_b32 s12, s6, s5
	v_cmp_ne_u32_e64 s6, 6, v37
	v_cmp_ne_u32_e64 s11, 5, v37
	v_cmp_ne_u32_e64 s3, 4, v36
	s_and_b32 s10, s10, s9
	v_cmp_ne_u32_e64 s9, 4, v37
	v_cmp_ne_u32_e64 s8, 7, v36
	v_cmp_ne_u32_e64 s5, 7, v37
	v_cmp_ne_u32_e64 s2, 3, v36
	s_and_b32 s6, s6, s7
	s_and_b32 s7, s11, s4
	v_cmp_ne_u32_e64 s4, 3, v37
	v_cmp_ne_u32_e64 s1, 2, v36
	s_and_b32 s9, s9, s3
	v_cmp_ne_u32_e64 s3, 2, v37
	v_cmp_ne_u32_e64 s0, 1, v36
	s_and_b32 s8, s5, s8
	v_cmp_ne_u32_e64 s5, 1, v37
	v_cmp_ne_u32_e32 vcc_lo, 0, v36
	s_and_b32 s4, s4, s2
	v_cmp_ne_u32_e64 s2, 0, v37
	s_and_b32 s3, s3, s1
	v_cmp_ne_u32_e64 s1, 0, v43
	s_and_b32 s5, s5, s0
	v_cmp_ne_u32_e64 s0, 1, v43
	s_and_b32 s2, s2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v43
	s_and_b32 s2, s1, s2
	v_cmp_ne_u32_e64 s1, 3, v43
	s_and_b32 s5, s0, s5
	v_cmp_ne_u32_e64 s0, 4, v43
	s_and_b32 s3, vcc_lo, s3
	v_cmp_ne_u32_e32 vcc_lo, 5, v43
	s_and_b32 s4, s1, s4
	v_cmp_ne_u32_e64 s1, 6, v43
	s_and_b32 s9, s0, s9
	v_cmp_ne_u32_e64 s0, 7, v43
	s_and_b32 s7, vcc_lo, s7
	v_cmp_ne_u32_e32 vcc_lo, 8, v43
	s_and_b32 s6, s1, s6
	v_cmp_ne_u32_e64 s1, 9, v43
	s_and_b32 s0, s0, s8
	s_mul_hi_u32 s8, s13, 0xcccccccd
	s_and_b32 s10, vcc_lo, s10
	s_lshr_b32 s22, s8, 3
	s_and_b32 s1, s1, s12
	s_cmp_lg_u32 s22, 9
	s_cselect_b32 s8, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s8, s1
	s_cmp_lg_u32 s22, 8
	s_cselect_b32 s8, -1, 0
	s_and_b32 s8, s8, s10
	s_cmp_lg_u32 s22, 7
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s10, s0
	s_cmp_lg_u32 s22, 6
	s_cselect_b32 s10, -1, 0
	s_and_b32 s6, s10, s6
	s_cmp_lg_u32 s22, 5
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s10, s7
	s_cmp_lg_u32 s22, 4
	s_cselect_b32 s10, -1, 0
	s_and_b32 s9, s10, s9
	s_cmp_lg_u32 s22, 3
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s10, s4
	s_cmp_lg_u32 s22, 2
	s_cselect_b32 s10, -1, 0
	s_and_b32 s3, s10, s3
	s_cmp_lg_u32 s22, 1
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s10, s5
	s_cmp_lg_u32 s22, 0
	s_mul_i32 s10, s22, 10
	s_cselect_b32 s11, -1, 0
	s_sub_i32 s23, s13, s10
	s_and_b32 s2, s11, s2
	s_cmp_lg_u32 s23, 0
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s10, s2
	s_cmp_lg_u32 s23, 1
	s_cselect_b32 s10, -1, 0
	s_and_b32 s5, s10, s5
	s_cmp_lg_u32 s23, 2
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s10, s3
	s_cmp_lg_u32 s23, 3
	s_cselect_b32 s10, -1, 0
	s_and_b32 s4, s10, s4
	s_cmp_lg_u32 s23, 4
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s10, s9
	s_cmp_lg_u32 s23, 5
	s_cselect_b32 s10, -1, 0
	s_and_b32 s7, s10, s7
	s_cmp_lg_u32 s23, 6
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, s10, s6
	s_cmp_lg_u32 s23, 7
	s_cselect_b32 s10, -1, 0
	s_and_b32 s0, s10, s0
	s_cmp_lg_u32 s23, 8
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s8, s10, s8
	s_cmp_lg_u32 s23, 9
	s_mul_hi_u32 s10, s14, 0xcccccccd
	s_cselect_b32 s11, -1, 0
	s_lshr_b32 s24, s10, 3
	s_and_b32 s1, s11, s1
	s_cmp_lg_u32 s24, 9
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s10, s1
	s_cmp_lg_u32 s24, 8
	s_cselect_b32 s10, -1, 0
	s_and_b32 s8, s10, s8
	s_cmp_lg_u32 s24, 7
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s10, s0
	s_cmp_lg_u32 s24, 6
	s_cselect_b32 s10, -1, 0
	s_and_b32 s6, s10, s6
	s_cmp_lg_u32 s24, 5
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s10, s7
	s_cmp_lg_u32 s24, 4
	s_cselect_b32 s10, -1, 0
	s_and_b32 s9, s10, s9
	s_cmp_lg_u32 s24, 3
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s10, s4
	s_cmp_lg_u32 s24, 2
	s_cselect_b32 s10, -1, 0
	s_and_b32 s3, s10, s3
	s_cmp_lg_u32 s24, 1
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s10, s5
	s_cmp_lg_u32 s24, 0
	s_mul_i32 s10, s24, 10
	s_cselect_b32 s11, -1, 0
	s_sub_i32 s25, s14, s10
	s_and_b32 s2, s11, s2
	s_cmp_lg_u32 s25, 0
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s10, s2
	s_cmp_lg_u32 s25, 1
	s_cselect_b32 s10, -1, 0
	s_and_b32 s5, s10, s5
	s_cmp_lg_u32 s25, 2
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s10, s3
	s_cmp_lg_u32 s25, 3
	s_cselect_b32 s10, -1, 0
	s_and_b32 s4, s10, s4
	s_cmp_lg_u32 s25, 4
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s10, s9
	s_cmp_lg_u32 s25, 5
	s_cselect_b32 s10, -1, 0
	s_and_b32 s7, s10, s7
	s_cmp_lg_u32 s25, 6
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, s10, s6
	s_cmp_lg_u32 s25, 7
	s_cselect_b32 s10, -1, 0
	s_and_b32 s0, s10, s0
	s_cmp_lg_u32 s25, 8
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s8, s10, s8
	s_cmp_lg_u32 s25, 9
	s_mul_hi_u32 s10, s15, 0xcccccccd
	s_cselect_b32 s11, -1, 0
	s_lshr_b32 s26, s10, 3
	s_and_b32 s1, s11, s1
	s_cmp_lg_u32 s26, 9
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s10, s1
	s_cmp_lg_u32 s26, 8
	s_cselect_b32 s10, -1, 0
	s_and_b32 s8, s10, s8
	s_cmp_lg_u32 s26, 7
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s10, s0
	s_cmp_lg_u32 s26, 6
	s_cselect_b32 s10, -1, 0
	s_and_b32 s6, s10, s6
	s_cmp_lg_u32 s26, 5
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s10, s7
	s_cmp_lg_u32 s26, 4
	s_cselect_b32 s10, -1, 0
	s_and_b32 s9, s10, s9
	s_cmp_lg_u32 s26, 3
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s10, s4
	s_cmp_lg_u32 s26, 2
	s_cselect_b32 s10, -1, 0
	s_and_b32 s3, s10, s3
	s_cmp_lg_u32 s26, 1
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s10, s5
	s_cmp_lg_u32 s26, 0
	s_mul_i32 s10, s26, 10
	s_cselect_b32 s11, -1, 0
	s_sub_i32 s27, s15, s10
	s_and_b32 s2, s11, s2
	s_cmp_lg_u32 s27, 0
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, s10, s2
	s_cmp_lg_u32 s27, 1
	s_cselect_b32 s2, -1, 0
	s_and_b32 s5, s2, s5
	s_cmp_lg_u32 s27, 2
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, s2, s3
	s_cmp_lg_u32 s27, 3
	s_cselect_b32 s2, -1, 0
	s_and_b32 s4, s2, s4
	s_cmp_lg_u32 s27, 4
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s2, s9
	s_cmp_lg_u32 s27, 5
	s_cselect_b32 s2, -1, 0
	s_and_b32 s3, s2, s7
	s_cmp_lg_u32 s27, 6
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s6
	s_cmp_lg_u32 s27, 7
	s_cselect_b32 s6, -1, 0
	s_and_b32 s6, s6, s0
	s_cmp_lg_u32 s27, 8
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s8
	s_cmp_lg_u32 s27, 9
	s_cselect_b32 s7, -1, 0
	s_and_b32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s28, 9
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 vcc_lo, s7, s1
	s_cmp_lg_u32 s28, 8
	v_cndmask_b32_e32 v0, 1, v2, vcc_lo
	s_cselect_b32 s1, -1, 0
	s_and_b32 s0, s1, s0
	s_cmp_lg_u32 s28, 7
	v_cndmask_b32_e64 v1, 1, v1, s0
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s6
	s_cmp_lg_u32 s28, 6
	v_cndmask_b32_e64 v2, 1, v10, s1
	s_cselect_b32 s6, -1, 0
	s_and_b32 s2, s6, s2
	s_cmp_lg_u32 s28, 5
	v_cndmask_b32_e64 v9, 1, v9, s2
	s_cselect_b32 s6, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s6, s3
	s_cmp_lg_u32 s28, 4
	v_cndmask_b32_e64 v6, 1, v6, s3
	s_cselect_b32 s6, -1, 0
                                        ; implicit-def: $sgpr3
	s_and_b32 vcc_lo, s6, s9
	s_cmp_lg_u32 s28, 3
	v_cndmask_b32_e32 v4, 1, v4, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s4
	s_cmp_lg_u32 s28, 2
	v_cndmask_b32_e64 v7, 1, v7, s0
	s_cselect_b32 s1, -1, 0
	s_and_b32 s1, s1, s11
	s_cmp_lg_u32 s28, 1
	v_cndmask_b32_e64 v8, 1, v8, s1
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, s2, s5
	s_cmp_lg_u32 s28, 0
	v_cndmask_b32_e32 v5, 1, v5, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_mov_b32 s2, 0
	s_and_b32 vcc_lo, s0, s10
	s_mov_b64 s[0:1], 0
	v_cndmask_b32_e32 v3, 1, v3, vcc_lo
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_cmp_gt_u32 s0, 9
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v10, v3, v5, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v10, v10, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 6
	v_cndmask_b32_e32 v10, v10, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 8
	v_cndmask_b32_e32 v10, v10, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v10, v10, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, 0xff, v10
	v_cmp_eq_u16_e32 vcc_lo, 0, v10
	s_or_b32 s5, s4, vcc_lo
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_and_b32 s5, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s5, s2
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, s4, exec_lo
	s_or_b32 s3, s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_3
; %bb.4:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB1_221
; %bb.5:
	s_mov_b64 s[0:1], 1
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
                                        ; implicit-def: $sgpr6
                                        ; implicit-def: $sgpr7
.LBB1_6:                                ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, 1
	s_mov_b32 s9, 0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s5, 2
	v_cndmask_b32_e32 v0, v36, v37, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s5, 3
	s_mov_b32 s10, -1
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e32 v0, v0, v43, vcc_lo
	s_cmp_eq_u32 s5, 4
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, s22, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s5, 5
	v_cndmask_b32_e64 v0, v0, s23, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s5, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, s24, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s5, 7
	v_cndmask_b32_e64 v0, v0, s25, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s5, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, s26, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s5, 9
	v_cndmask_b32_e64 v0, v0, s27, s2
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v0, v0, s28, s2
	s_mov_b64 s[2:3], s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_bfe_i32 v0, v0, 0, 8
.LBB1_7:                                ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_abs_i32 s13, s10
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_cndmask_b32_e32 v1, v36, v37, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_cselect_b32 s14, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v43, vcc_lo
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e64 v1, v1, s22, s14
	s_cselect_b32 s14, -1, 0
	s_cmp_eq_u32 s2, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, s23, s14
	s_cselect_b32 s14, -1, 0
	s_cmp_eq_u32 s2, 6
	v_cndmask_b32_e64 v1, v1, s24, s14
	s_cselect_b32 s14, -1, 0
	s_cmp_eq_u32 s2, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, s25, s14
	s_cselect_b32 s14, -1, 0
	s_cmp_eq_u32 s2, 8
	v_cndmask_b32_e64 v1, v1, s26, s14
	s_cselect_b32 s14, -1, 0
	s_cmp_eq_u32 s2, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, s27, s14
	s_cselect_b32 s14, -1, 0
	s_or_b32 s11, s11, exec_lo
	s_or_b32 s12, s12, exec_lo
	v_cndmask_b32_e64 v1, v1, s28, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfe_i32 v1, v1, 0, 8
	v_sub_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, 0, v1
	v_max_i32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, s13, v1
	s_and_saveexec_b32 s13, vcc_lo
; %bb.8:                                ;   in Loop: Header=BB1_7 Depth=2
	s_add_u32 s14, s2, 1
	s_addc_u32 s15, s3, 0
	s_add_i32 s10, s10, -1
	s_cmp_gt_u32 s2, 8
	s_cselect_b32 s2, -1, 0
	s_and_not1_b32 s3, s12, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_and_not1_b32 s11, s11, exec_lo
	s_or_b32 s12, s3, s2
	s_mov_b64 s[2:3], s[14:15]
; %bb.9:                                ; %Flow433
                                        ;   in Loop: Header=BB1_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_xor_b32 s13, s11, -1
	s_and_b32 s14, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s9, s14, s9
	s_and_not1_b32 s8, s8, exec_lo
	s_and_b32 s13, s13, exec_lo
	s_or_b32 s8, s8, s13
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_7
; %bb.10:                               ; %loop.exit.guard321
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_mov_b32 s2, -1
	s_or_b32 s7, s7, exec_lo
	s_and_saveexec_b32 s3, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
; %bb.11:                               ; %.critedge.loopexit
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s5, s5, 1
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s5, 9
	s_cselect_b32 s2, -1, 0
	s_and_not1_b32 s7, s7, exec_lo
	s_or_not1_b32 s2, s2, exec_lo
; %bb.12:                               ; %Flow435
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s4, s2, s4
	s_and_not1_b32 s2, s6, exec_lo
	s_and_b32 s3, s7, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s2, s3
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_6
; %bb.13:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s4
	s_xor_b32 s0, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_221
; %bb.14:                               ; %.critedge30
	s_load_b64 s[0:1], s[18:19], 0x0
	s_mov_b32 s3, exec_lo
	s_mov_b32 s2, exec_lo
	v_mbcnt_lo_u32_b32 v0, s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_16
; %bb.15:
	s_bcnt1_i32_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_16:
	s_or_b32 exec_lo, exec_lo, s2
	v_mbcnt_lo_u32_b32 v38, -1, 0
	v_mov_b32_e32 v3, 0
	s_load_b64 s[20:21], s[18:19], 0x60
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v0, v38
	s_waitcnt lgkmcnt(0)
	global_load_b32 v41, v3, s[0:1]
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_22
; %bb.17:
	global_load_b64 v[6:7], v3, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v3, s[20:21] offset:40
	global_load_b64 v[4:5], v3, s[20:21]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v7
	v_and_b32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v8, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v8, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v5, v2, vcc_lo
	global_load_b64 v[4:5], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v3, v[4:7], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[6:7]
	s_cbranch_execz .LBB1_21
; %bb.18:                               ; %.preheader3.i.i.i.preheader
	v_mov_b32_e32 v4, 0
	s_mov_b32 s3, 0
.LBB1_19:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[20:21] offset:40
	global_load_b64 v[9:10], v4, s[20:21]
	v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v7, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[2:3]
	v_mov_b32_e32 v2, v5
	global_load_b64 v[5:6], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[5:8], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[7:8]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_19
; %bb.20:                               ; %Flow428
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_21:                               ; %Flow430
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_22:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[20:21] offset:40
	global_load_b128 v[4:7], v3, s[20:21]
	v_readfirstlane_b32 s2, v1
	v_readfirstlane_b32 s3, v2
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_24
; %bb.23:
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, 0
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v2, vcc_lo, s8, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[1:2], v[8:11], off offset:8
.LBB1_24:
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s8, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s9, s8
	v_lshlrev_b64 v[2:3], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s10, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v0, v2
	v_mov_b32_e32 v0, 33
	s_mov_b32 s11, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v1
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v8, s8
	v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
	v_mov_b32_e32 v11, s11
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_32
; %bb.25:
	s_clause 0x1
	global_load_b64 v[12:13], v1, s[20:21] offset:32 glc
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	v_mov_b32_e32 v10, s2
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v11, s3 :: v_dual_and_b32 v0, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v3, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v3, v0
	v_add_co_u32 v8, vcc_lo, v4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v0, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v1, v[10:13], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[12:13]
	s_cbranch_execz .LBB1_28
; %bb.26:                               ; %.preheader1.i.i.i.preheader
	v_mov_b32_e32 v10, 0
.LBB1_27:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_27
.LBB1_28:                               ; %Flow426
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	global_load_b64 v[0:1], v3, s[20:21] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_30
; %bb.29:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_30:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_32
; %bb.31:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_32:                               ; %Flow427
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_33:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_35
; %bb.34:                               ;   in Loop: Header=BB1_33 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_35:                               ;   in Loop: Header=BB1_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_37
; %bb.36:                               ;   in Loop: Header=BB1_33 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_38
.LBB1_37:                               ;   in Loop: Header=BB1_33 Depth=1
	s_mov_b32 s1, -1
.LBB1_38:                               ; %Flow421
                                        ;   in Loop: Header=BB1_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_33
; %bb.39:
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_43
; %bb.40:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[20:21] offset:40
	global_load_b64 v[9:10], v8, s[20:21] offset:24 glc
	global_load_b64 v[6:7], v8, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_43
; %bb.41:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_42:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_42
.LBB1_43:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v6, 0
	s_cselect_b32 s4, 5, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s4
	s_add_u32 s8, s18, 16
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v5, v38
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v5
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_49
; %bb.44:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[9:10], v1, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	global_load_b64 v[6:7], v1, s[20:21]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v3, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[7:8], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[9:10]
	s_cbranch_execz .LBB1_48
; %bb.45:                               ; %.preheader3.i.i.i36.preheader
	s_mov_b32 s3, 0
.LBB1_46:                               ; %.preheader3.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	global_load_b64 v[11:12], v1, s[20:21]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v8, v3, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
	v_mov_b32_e32 v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
	v_mov_b32_e32 v7, v3
	global_load_b64 v[7:8], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_46
; %bb.47:                               ; %Flow414
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_48:                               ; %Flow416
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_49:                               ; %.loopexit4.i.i.i31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s2, v7
	v_readfirstlane_b32 s3, v8
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[9:10], v6, s[20:21] offset:40
	global_load_b128 v[1:4], v6, s[20:21]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_51
; %bb.50:
	v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, v6
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v12, vcc_lo, s8, v2, vcc_lo
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB1_51:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v7
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_and_or_b32 v39, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v8, vcc_lo, v4, v8, vcc_lo
	v_dual_mov_b32 v42, v6 :: v_dual_mov_b32 v3, s8
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
	v_mov_b32_e32 v6, s11
	s_clause 0x3
	global_store_b128 v[7:8], v[39:42], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_59
; %bb.52:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v9, s2
	v_mov_b32_e32 v10, s3
	s_clause 0x1
	global_load_b64 v[11:12], v0, s[20:21] offset:32 glc
	global_load_b64 v[3:4], v0, s[20:21] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v7, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v0, v[9:12], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[11:12]
	s_cbranch_execz .LBB1_55
; %bb.53:                               ; %.preheader1.i.i.i34.preheader
	s_mov_b32 s8, 0
.LBB1_54:                               ; %.preheader1.i.i.i34
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v0, v[3:6], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_54
.LBB1_55:                               ; %Flow412
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v6, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	global_load_b64 v[3:4], v6, s[20:21] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_57
; %bb.56:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB1_57:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_59
; %bb.58:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_59:                               ; %Flow413
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_60:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_62
; %bb.61:                               ;   in Loop: Header=BB1_60 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_62:                               ;   in Loop: Header=BB1_60 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_64
; %bb.63:                               ;   in Loop: Header=BB1_60 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_65
.LBB1_64:                               ;   in Loop: Header=BB1_60 Depth=1
	s_mov_b32 s1, -1
.LBB1_65:                               ; %Flow407
                                        ;   in Loop: Header=BB1_60 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_60
; %bb.66:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_70
; %bb.67:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[20:21] offset:40
	global_load_b64 v[7:8], v6, s[20:21] offset:24 glc
	global_load_b64 v[4:5], v6, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_70
; %bb.68:                               ; %.preheader.i.i.i33.preheader
	s_mov_b32 s0, 0
.LBB1_69:                               ; %.preheader.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_69
.LBB1_70:                               ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 32
	v_mov_b32_e32 v2, 10
	s_mov_b32 s0, 0
	s_mov_b32 s1, 0
.LBB1_71:                               ; %.preheader22.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_72 Depth 2
	s_cmp_eq_u32 s0, 1
	s_mov_b32 s3, 0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v3, v36, v37, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v43, vcc_lo
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e64 v3, v3, s22, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, s23, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s0, 6
	v_cndmask_b32_e64 v3, v3, s24, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s0, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, s25, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s0, 8
	v_cndmask_b32_e64 v3, v3, s26, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s0, 9
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, s27, s2
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v3, v3, s28, s2
	v_readfirstlane_b32 s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_i32 v3, v3, 0, 8
	s_add_i32 s2, s2, s1
.LBB1_72:                               ;   Parent Loop BB1_71 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_add_i32 s4, s2, s3
	v_add_nc_u32_e32 v3, -1, v3
	s_add_i32 s3, s3, 2
	s_add_i32 s5, s4, 1
	v_cndmask_b32_e64 v4, 46, 0x51, vcc_lo
	s_cmp_eq_u32 s3, 20
	s_clause 0x1
	scratch_store_b8 off, v4, s4
	scratch_store_b8 off, v1, s5
	s_cbranch_scc0 .LBB1_72
; %bb.73:                               ;   in Loop: Header=BB1_71 Depth=1
	s_add_i32 s1, s1, s3
	s_add_i32 s0, s0, 1
	s_add_i32 s2, s2, s3
	s_add_i32 s1, s1, 1
	s_cmp_eq_u32 s0, 10
	scratch_store_b8 off, v2, s2
	s_cbranch_scc0 .LBB1_71
; %bb.74:
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, v38
	s_add_i32 s2, s2, 1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	scratch_store_b8 off, v5, s2
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_80
; %bb.75:
	global_load_b64 v[2:3], v5, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v5, s[20:21] offset:40
	global_load_b64 v[6:7], v5, s[20:21]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v8, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v8, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v5, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[2:3]
	s_cbranch_execz .LBB1_79
; %bb.76:                               ; %.preheader3.i.i.i.i.preheader
	s_mov_b32 s3, 0
.LBB1_77:                               ; %.preheader3.i.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v5, s[20:21] offset:40
	global_load_b64 v[8:9], v5, s[20:21]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, v0, v2
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v0, 24, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v7 :: v_dual_and_b32 v1, v1, v3
	v_mad_u64_u32 v[7:8], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v5, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_77
; %bb.78:                               ; %Flow400
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_79:                               ; %Flow402
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_80:                               ; %.loopexit4.i.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[20:21] offset:40
	global_load_b128 v[0:3], v5, s[20:21]
	v_readfirstlane_b32 s2, v6
	v_readfirstlane_b32 s3, v7
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_82
; %bb.81:
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_82:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v2, v4
	v_mov_b32_e32 v2, 33
	s_mov_b32 s11, s8
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, v6, v5, vcc_lo
	v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v13, s11
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v12, s10
	v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
	s_clause 0x3
	global_store_b128 v[8:9], v[2:5], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_90
; %bb.83:
	s_clause 0x1
	global_load_b64 v[14:15], v3, s[20:21] offset:32 glc
	global_load_b64 v[4:5], v3, s[20:21] offset:40
	v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v13, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v4
	v_readfirstlane_b32 s9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v10, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[10:11], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[12:15], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[14:15]
	s_cbranch_execz .LBB1_86
; %bb.84:                               ; %.preheader1.i.i.i.i.preheader
	s_mov_b32 s8, 0
.LBB1_85:                               ; %.preheader1.i.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
	s_sleep 1
	global_store_b64 v[10:11], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v3, v[4:7], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_85
.LBB1_86:                               ; %Flow398
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v5, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	global_load_b64 v[2:3], v5, s[20:21] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_88
; %bb.87:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_88:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_90
; %bb.89:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_90:                               ; %Flow399
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_91:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_93
; %bb.92:                               ;   in Loop: Header=BB1_91 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_93:                               ;   in Loop: Header=BB1_91 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_95
; %bb.94:                               ;   in Loop: Header=BB1_91 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_96
.LBB1_95:                               ;   in Loop: Header=BB1_91 Depth=1
	s_mov_b32 s1, -1
.LBB1_96:                               ; %Flow393
                                        ;   in Loop: Header=BB1_91 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_91
; %bb.97:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_101
; %bb.98:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[20:21] offset:40
	global_load_b64 v[9:10], v8, s[20:21] offset:24 glc
	global_load_b64 v[6:7], v8, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_101
; %bb.99:                               ; %.preheader.i.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_100:                              ; %.preheader.i.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_100
.LBB1_101:                              ; %__ockl_printf_begin.exit.i
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_mov_b32_e32 v6, 0
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v5, 0
	s_cselect_b32 s2, -1, 0
	v_mov_b32_e32 v3, s1
	v_cndmask_b32_e64 v2, 0, 1, s2
	s_add_u32 s8, s18, 16
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	v_lshlrev_b32_e32 v4, 2, v2
	v_mov_b32_e32 v2, s0
	s_swappc_b64 s[30:31], s[2:3]
	v_cmp_eq_u32_e64 s1, 16, -1
	v_mov_b32_e32 v25, 0
	v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v26, 0
	v_cmp_ne_u32_e64 s0, 16, -1
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_105
; %bb.102:                              ; %.preheader.i.preheader
	v_add_nc_u32_e64 v1, 16, -1
	s_mov_b32 s1, 0
.LBB1_103:                              ; %.preheader.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, 1, v1
	scratch_load_u8 v2, v1, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v2
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_103
; %bb.104:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	s_mov_b64 s[2:3], src_private_base
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cndmask_b32_e64 v2, 0, s3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v1, vcc_lo, 16, v1
	v_subrev_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v2, vcc_lo
.LBB1_105:
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_192
; %bb.106:
	v_dual_mov_b32 v31, 16 :: v_dual_and_b32 v36, -3, v0
	v_mov_b32_e32 v4, 1
	v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v3, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v37
	s_mov_b32 s7, 0
	s_mov_b32 s6, 0
.LBB1_107:                              ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_110 Depth 2
                                        ;     Child Loop BB1_118 Depth 2
                                        ;     Child Loop BB1_126 Depth 2
                                        ;     Child Loop BB1_134 Depth 2
                                        ;     Child Loop BB1_142 Depth 2
                                        ;     Child Loop BB1_150 Depth 2
                                        ;     Child Loop BB1_158 Depth 2
                                        ;     Child Loop BB1_166 Depth 2
                                        ;     Child Loop BB1_174 Depth 2
                                        ;     Child Loop BB1_180 Depth 2
                                        ;     Child Loop BB1_189 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[25:26]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v30, 0, v26 :: v_dual_cndmask_b32 v29, 56, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v29
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_113
; %bb.108:                              ;   in Loop: Header=BB1_107 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v29
	s_cbranch_execz .LBB1_112
; %bb.109:                              ; %.preheader31.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_lshlrev_b64 v[1:2], 3, v[29:30]
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v2, v31
	v_mov_b32_e32 v8, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_110:                              ; %.preheader31.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_u8 v9, v2, off
	v_mov_b32_e32 v10, s7
	v_add_nc_u32_e32 v2, 1, v2
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v1
	v_or_b32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v7, v9, v7
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_110
; %bb.111:                              ; %Flow364
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_112:                              ; %Flow366
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_113:                              ; %Flow368
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_saveexec_b32 s0, s2
	v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, v31
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_115
; %bb.114:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v1, v31, off
	scratch_load_u8 v2, v31, off offset:1
	scratch_load_u8 v7, v31, off offset:2
	scratch_load_u8 v8, v31, off offset:3
	scratch_load_u8 v9, v31, off offset:5
	scratch_load_u8 v10, v31, off offset:4
	v_mov_b32_e32 v11, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v1, 0xffff, v1
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v2, 8, v2
	s_clause 0x1
	scratch_load_u8 v12, v31, off offset:7
	scratch_load_d16_hi_u8 v11, v31, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v7, 16, v7
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v8, 24, v8
	v_or_b32_e32 v1, v2, v1
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v2, 8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v1, v1, v7, v8
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v10, v2
	v_add_nc_u32_e32 v2, -8, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v1, v1, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v8, 24, v12
	s_waitcnt vmcnt(0)
	v_or3_b32 v8, v7, v11, v8
	v_or3_b32 v7, v1, 0, 0
	v_add_nc_u32_e32 v1, 8, v31
.LBB1_115:                              ; %.loopexit32.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr9_vgpr10
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v2
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_121
; %bb.116:                              ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v2
	s_cbranch_execz .LBB1_120
; %bb.117:                              ; %.preheader29.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_118:                              ; %.preheader29.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s7 :: v_dual_add_nc_u32 v11, s5, v1
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v2
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v9, v11, v9
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_118
; %bb.119:                              ; %Flow359
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_120:                              ; %Flow361
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr2
.LBB1_121:                              ; %Flow363
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v13, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_123
; %bb.122:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v9, v1, off
	scratch_load_u8 v10, v1, off offset:1
	scratch_load_u8 v11, v1, off offset:2
	scratch_load_u8 v12, v1, off offset:3
	scratch_load_u8 v13, v1, off offset:5
	scratch_load_u8 v14, v1, off offset:4
	v_mov_b32_e32 v15, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v9, 0xffff, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 8, v10
	s_clause 0x1
	scratch_load_u8 v16, v1, off offset:7
	scratch_load_d16_hi_u8 v15, v1, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v1, 8, v1
	v_or_b32_e32 v9, v10, v9
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v10, 8, v13
	v_add_nc_u32_e32 v13, -8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v9, v9, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v10, 0, v14, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v9, v9, 0, 0
	v_or3_b32 v9, v9, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v10, v10, v15, v11
.LBB1_123:                              ; %.loopexit30.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v13
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_129
; %bb.124:                              ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v13
	s_cbranch_execz .LBB1_128
; %bb.125:                              ; %.preheader27.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_126:                              ; %.preheader27.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v15, s7 :: v_dual_add_nc_u32 v2, s5, v1
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v13
	scratch_load_u8 v2, v2, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], s0, v[14:15]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v11, v14, v11
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_126
; %bb.127:                              ; %Flow354
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_128:                              ; %Flow356
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr13
.LBB1_129:                              ; %Flow358
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v2, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_131
; %bb.130:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v2, v1, off
	scratch_load_u8 v11, v1, off offset:1
	scratch_load_u8 v12, v1, off offset:2
	scratch_load_u8 v14, v1, off offset:3
	scratch_load_u8 v15, v1, off offset:5
	scratch_load_u8 v16, v1, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v28 :: v_dual_and_b32 v2, 0xffff, v2
	s_clause 0x1
	scratch_load_u8 v18, v1, off offset:7
	scratch_load_d16_hi_u8 v17, v1, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v12, 16, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v1, 8, v1
	v_or_b32_e32 v2, v11, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v12, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v2, 0, 0
	v_add_nc_u32_e32 v2, -8, v13
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v12, 24, v18
	s_waitcnt vmcnt(0)
	v_or3_b32 v12, v11, v17, v12
	v_or3_b32 v11, v14, 0, 0
.LBB1_131:                              ; %.loopexit28.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v2
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_137
; %bb.132:                              ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v2
	s_cbranch_execz .LBB1_136
; %bb.133:                              ; %.preheader25.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_134:                              ; %.preheader25.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s7 :: v_dual_add_nc_u32 v15, s5, v1
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v2
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v14, v16, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v15, v13
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_134
; %bb.135:                              ; %Flow349
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_136:                              ; %Flow351
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr2
.LBB1_137:                              ; %Flow353
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_139
; %bb.138:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v13, v1, off
	scratch_load_u8 v14, v1, off offset:1
	scratch_load_u8 v15, v1, off offset:2
	scratch_load_u8 v16, v1, off offset:3
	scratch_load_u8 v17, v1, off offset:5
	scratch_load_u8 v18, v1, off offset:4
	v_mov_b32_e32 v19, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v13, 0xffff, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 8, v14
	s_clause 0x1
	scratch_load_u8 v20, v1, off offset:7
	scratch_load_d16_hi_u8 v19, v1, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v1, 8, v1
	v_or_b32_e32 v13, v14, v13
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v14, 8, v17
	v_add_nc_u32_e32 v17, -8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v13, v13, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v14, 0, v18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v13, v13, 0, 0
	v_or3_b32 v13, v13, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v20
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v14, v14, v19, v15
.LBB1_139:                              ; %.loopexit26.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_145
; %bb.140:                              ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB1_144
; %bb.141:                              ; %.preheader23.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_142:                              ; %.preheader23.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v19, s7 :: v_dual_add_nc_u32 v2, s5, v1
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v17
	scratch_load_u8 v2, v2, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v18, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_142
; %bb.143:                              ; %Flow344
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_144:                              ; %Flow346
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB1_145:                              ; %Flow348
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v2, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_147
; %bb.146:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v2, v1, off
	scratch_load_u8 v15, v1, off offset:1
	scratch_load_u8 v16, v1, off offset:2
	scratch_load_u8 v18, v1, off offset:3
	scratch_load_u8 v19, v1, off offset:5
	scratch_load_u8 v20, v1, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v21, v28 :: v_dual_and_b32 v2, 0xffff, v2
	s_clause 0x1
	scratch_load_u8 v22, v1, off offset:7
	scratch_load_d16_hi_u8 v21, v1, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v15, 8, v15
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v16, 16, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v18, 24, v18
	v_add_nc_u32_e32 v1, 8, v1
	v_or_b32_e32 v2, v15, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v16, v18
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v20, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_or3_b32 v18, v2, 0, 0
	v_add_nc_u32_e32 v2, -8, v17
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v16, 24, v22
	s_waitcnt vmcnt(0)
	v_or3_b32 v16, v15, v21, v16
	v_or3_b32 v15, v18, 0, 0
.LBB1_147:                              ; %.loopexit24.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v2
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_153
; %bb.148:                              ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v2
	s_cbranch_execz .LBB1_152
; %bb.149:                              ; %.preheader21.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_150:                              ; %.preheader21.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s7 :: v_dual_add_nc_u32 v19, s5, v1
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v2
	scratch_load_u8 v19, v19, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v19, v17
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_150
; %bb.151:                              ; %Flow339
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_152:                              ; %Flow341
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr2
.LBB1_153:                              ; %Flow343
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_155
; %bb.154:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v17, v1, off
	scratch_load_u8 v18, v1, off offset:1
	scratch_load_u8 v19, v1, off offset:2
	scratch_load_u8 v20, v1, off offset:3
	scratch_load_u8 v21, v1, off offset:5
	scratch_load_u8 v22, v1, off offset:4
	v_mov_b32_e32 v23, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v17, 0xffff, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v18, 8, v18
	s_clause 0x1
	scratch_load_u8 v24, v1, off offset:7
	scratch_load_d16_hi_u8 v23, v1, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v19, 16, v19
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v20, 24, v20
	v_add_nc_u32_e32 v1, 8, v1
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v21
	v_add_nc_u32_e32 v21, -8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v19, v20
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v22, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v19, 24, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v23, v19
.LBB1_155:                              ; %.loopexit22.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_161
; %bb.156:                              ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB1_160
; %bb.157:                              ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_158:                              ; %.preheader.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_u8 v2, v1, off
	v_mov_b32_e32 v23, s7
	v_add_nc_u32_e32 v21, -1, v21
	v_add_nc_u32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v22, 0xffff, v2
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, v23, v20
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_158
; %bb.159:                              ; %Flow334
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_160:                              ; %Flow336
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr1
.LBB1_161:                              ; %Flow338
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_163
; %bb.162:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x5
	scratch_load_u8 v2, v1, off
	scratch_load_u8 v19, v1, off offset:1
	scratch_load_u8 v20, v1, off offset:2
	scratch_load_u8 v21, v1, off offset:3
	scratch_load_u8 v22, v1, off offset:5
	scratch_load_u8 v23, v1, off offset:4
	v_mov_b32_e32 v24, v28
	s_clause 0x1
	scratch_load_u8 v27, v1, off offset:7
	scratch_load_d16_hi_u8 v24, v1, off offset:6
	s_waitcnt vmcnt(7)
	v_and_b32_e32 v1, 0xffff, v2
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v2, 8, v19
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v19, 16, v20
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v22
	v_or_b32_e32 v1, v2, v1
	v_lshlrev_b32_e32 v2, 24, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v1, v1, v19, v2
	s_waitcnt vmcnt(2)
	v_or3_b32 v2, 0, v23, v20
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v19, 24, v27
	v_or3_b32 v1, v1, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v20, v2, v24, v19
	v_or3_b32 v19, v1, 0, 0
.LBB1_163:                              ; %.loopexit.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v27, v38
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v27
	v_cmp_eq_u32_e64 s0, s0, v27
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_169
; %bb.164:                              ;   in Loop: Header=BB1_107 Depth=1
	global_load_b64 v[23:24], v28, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v28, s[20:21] offset:40
	global_load_b64 v[21:22], v28, s[20:21]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v24
	v_and_b32_e32 v1, v1, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v32, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v32, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v21, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v22, v2, vcc_lo
	global_load_b64 v[21:22], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v28, v[21:24], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[23:24]
	s_cbranch_execz .LBB1_168
; %bb.165:                              ; %.preheader3.i.i19.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_mov_b32 s3, 0
.LBB1_166:                              ; %.preheader3.i.i19.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[21:22], v28, s[20:21] offset:40
	global_load_b64 v[32:33], v28, s[20:21]
	v_dual_mov_b32 v24, v2 :: v_dual_mov_b32 v23, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v21, v21, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v21, 24, v[32:33]
	v_and_b32_e32 v32, v22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, v32, 24, v[2:3]
	v_mov_b32_e32 v2, v21
	global_load_b64 v[21:22], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v28, v[21:24], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[23:24]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_166
; %bb.167:                              ; %Flow331
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_168:                              ; %Flow333
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_169:                              ; %.loopexit4.i.i14.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[32:33], v28, s[20:21] offset:40
	global_load_b128 v[21:24], v28, s[20:21]
	v_readfirstlane_b32 s2, v1
	v_readfirstlane_b32 s3, v2
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v32
	v_readfirstlane_b32 s5, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s8, s4, 24
	s_mul_i32 s9, s4, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB1_171
; %bb.170:                              ;   in Loop: Header=BB1_107 Depth=1
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v32, vcc_lo, v21, s9
	v_add_co_ci_u32_e32 v33, vcc_lo, s12, v22, vcc_lo
	v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, v28
	global_store_b128 v[32:33], v[1:4], off offset:8
.LBB1_171:                              ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_cmp_lt_u64_e32 vcc_lo, 56, v[25:26]
	v_or_b32_e32 v1, 2, v5
	v_lshl_add_u32 v2, v29, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v1, v5 :: v_dual_and_b32 v32, 0x1e0, v2
	v_lshlrev_b64 v[1:2], 6, v[27:28]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v23, vcc_lo, v23, s4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v24, vcc_lo
	v_and_or_b32 v5, 0xffffff1f, v5, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v23, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, v24, v2, vcc_lo
	s_clause 0x3
	global_store_b128 v[1:2], v[5:8], off
	global_store_b128 v[1:2], v[9:12], off offset:16
	global_store_b128 v[1:2], v[13:16], off offset:32
	global_store_b128 v[1:2], v[17:20], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_179
; %bb.172:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x1
	global_load_b64 v[13:14], v28, s[20:21] offset:32 glc
	global_load_b64 v[5:6], v28, s[20:21] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	v_readfirstlane_b32 s11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s5
	v_add_co_u32 v9, vcc_lo, v21, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v22, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v28, v[11:14], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[7:8], v[13:14]
	s_cbranch_execz .LBB1_175
; %bb.173:                              ; %.preheader1.i.i17.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_mov_b32 s10, 0
.LBB1_174:                              ; %.preheader1.i.i17.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3
	s_sleep 1
	global_store_b64 v[9:10], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v28, v[5:8], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_174
.LBB1_175:                              ; %Flow329
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[5:6], v28, s[20:21] offset:16
	s_mov_b32 s10, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v7, s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v7
	s_cbranch_execz .LBB1_177
; %bb.176:                              ;   in Loop: Header=BB1_107 Depth=1
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v27, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[27:28], off offset:8
.LBB1_177:                              ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB1_179
; %bb.178:                              ;   in Loop: Header=BB1_107 Depth=1
	global_load_b32 v27, v[5:6], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v27
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[27:28], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_179:                              ; %Flow330
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s8, s8, s1
	v_add_co_u32 v5, vcc_lo, v21, s9
	v_add_co_ci_u32_e32 v6, vcc_lo, s8, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB1_180:                              ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v7, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_182
; %bb.181:                              ;   in Loop: Header=BB1_180 Depth=2
	global_load_b32 v7, v[5:6], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v7, 1, v7
.LBB1_182:                              ;   in Loop: Header=BB1_180 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v7
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_184
; %bb.183:                              ;   in Loop: Header=BB1_180 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_185
.LBB1_184:                              ;   in Loop: Header=BB1_180 Depth=2
	s_mov_b32 s1, -1
.LBB1_185:                              ; %Flow324
                                        ;   in Loop: Header=BB1_180 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_180
; %bb.186:                              ;   in Loop: Header=BB1_107 Depth=1
	global_load_b128 v[5:8], v[1:2], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_190
; %bb.187:                              ;   in Loop: Header=BB1_107 Depth=1
	s_clause 0x2
	global_load_b64 v[1:2], v28, s[20:21] offset:40
	global_load_b64 v[11:12], v28, s[20:21] offset:24 glc
	global_load_b64 v[9:10], v28, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v13, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v7, v7, v13
	v_and_b32_e32 v2, v8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, v7, v1
	v_mul_hi_u32 v13, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, vcc_lo, v9, v1
	v_mov_b32_e32 v9, v11
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v2, v13, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[1:2], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v28, v[7:10], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_190
; %bb.188:                              ; %.preheader.i.i16.i.i.preheader
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_mov_b32 s0, 0
.LBB1_189:                              ; %.preheader.i.i16.i.i
                                        ;   Parent Loop BB1_107 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[1:2], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v28, v[7:10], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_189
.LBB1_190:                              ; %__ockl_hostcall_preview.exit20.i.i
                                        ;   in Loop: Header=BB1_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v25, vcc_lo, v25, v29
	v_sub_co_ci_u32_e32 v26, vcc_lo, v26, v30, vcc_lo
	v_add_nc_u32_e32 v31, v31, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[25:26]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_107
; %bb.191:                              ; %Flow369
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_193
.LBB1_192:
	s_mov_b32 s0, -1
.LBB1_193:                              ; %Flow386
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_221
; %bb.194:
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v38
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v38
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_200
; %bb.195:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[7:8], v1, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	global_load_b64 v[4:5], v1, s[20:21]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v7
	v_and_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v6, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[7:8]
	s_cbranch_execz .LBB1_199
; %bb.196:                              ; %.preheader3.i.i.i19.i.preheader
	s_mov_b32 s3, 0
.LBB1_197:                              ; %.preheader3.i.i.i19.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	global_load_b64 v[9:10], v1, s[20:21]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v2, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v2, 24, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v5 :: v_dual_and_b32 v3, v3, v8
	v_mad_u64_u32 v[5:6], null, v3, 24, v[2:3]
	global_load_b64 v[5:6], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_197
; %bb.198:                              ; %Flow382
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_199:                              ; %Flow384
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_200:                              ; %.loopexit4.i.i.i14.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v39, 0
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[7:8], v39, s[20:21] offset:40
	global_load_b128 v[1:4], v39, s[20:21]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_202
; %bb.201:
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v10, vcc_lo, s10, v2, vcc_lo
	v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, v39
	v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
	global_store_b128 v[9:10], v[5:8], off offset:8
.LBB1_202:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[5:6], 6, v[38:39]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v5
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_and_or_b32 v36, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v8, vcc_lo, v4, v6, vcc_lo
	v_dual_mov_b32 v38, v39 :: v_dual_mov_b32 v3, s8
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
	v_mov_b32_e32 v6, s11
	s_clause 0x3
	global_store_b128 v[7:8], v[36:39], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_210
; %bb.203:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v9, s2
	v_mov_b32_e32 v10, s3
	s_clause 0x1
	global_load_b64 v[11:12], v0, s[20:21] offset:32 glc
	global_load_b64 v[3:4], v0, s[20:21] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v7, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v0, v[9:12], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[11:12]
	s_cbranch_execz .LBB1_206
; %bb.204:                              ; %.preheader1.i.i.i17.i.preheader
	s_mov_b32 s8, 0
.LBB1_205:                              ; %.preheader1.i.i.i17.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v0, v[3:6], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_205
.LBB1_206:                              ; %Flow380
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v6, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	global_load_b64 v[3:4], v6, s[20:21] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_208
; %bb.207:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB1_208:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_210
; %bb.209:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_210:                              ; %Flow381
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_211:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_213
; %bb.212:                              ;   in Loop: Header=BB1_211 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_213:                              ;   in Loop: Header=BB1_211 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_215
; %bb.214:                              ;   in Loop: Header=BB1_211 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_216
.LBB1_215:                              ;   in Loop: Header=BB1_211 Depth=1
	s_mov_b32 s1, -1
.LBB1_216:                              ; %Flow375
                                        ;   in Loop: Header=BB1_211 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_211
; %bb.217:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_221
; %bb.218:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[20:21] offset:40
	global_load_b64 v[7:8], v6, s[20:21] offset:24 glc
	global_load_b64 v[4:5], v6, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_221
; %bb.219:                              ; %.preheader.i.i.i16.i.preheader
	s_mov_b32 s0, 0
.LBB1_220:                              ; %.preheader.i.i.i16.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_220
.LBB1_221:                              ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5queenPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 240
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 44
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5queenPii, .Lfunc_end1-_Z5queenPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 12756
; NumSgprs: 35
; NumVgprs: 44
; ScratchSize: 240
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 44
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%s\n"
	.size	.str, 4

	.type	.str.1,@object                  ; @.str.1
.str.1:
	.asciz	"%d.\n"
	.size	.str.1, 5

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5queenPii
    .private_segment_fixed_size: 240
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z5queenPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     44
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
