#include<stdio.h>
#include <signal.h>
#define fg 0.1
#define fe 100
#define damp 0.01
#define critical_factor  0.008
#define SCREEN_WIDTH 600
#define SCREEN_HEIGHT 600
const int MAX_SIZE = 500;
// [self.x,self.y,self.vx,self.vy,self.m,self.charge]
//    0     1       2       3       4       5
__global__ void myop( float * d_output, float *d_input,int size)
{
  __shared__ float buffer[MAX_SIZE*6];
  int id = threadIdx.x;
  float my[6];
  for(int i = 0; i< 6; i++)
  {
    float temp  =d_input[6*id+i];
  buffer[6*id+i]=temp;
  my[i]=temp;

  }
  __syncthreads();

  for(int i = 0; i< size; i++)
  {
    if(i==id)
    continue;
    float other[6];
    for(int j = 0; j<6;j++)
    {
      other[j]=buffer[6*i+j];
    }
    float dx = my[0]-other[0];
    float dy = my[1]-other[1];
    float r = sqrtf(dx*dx+dy*dy);
    float fx =-(fg*my[4]*other[4]-fe*my[5]*other[5])*dx;
    fx=fx/(r*r*r);
    float fy =-(fg*my[4]*other[4]-fe*my[5]*other[5])*dy;
    fy=fy/(r*r*r);
    if(r>10)
    {
      my[2]+=(fx/my[4]);
      my[3]+=(fy/my[4]);
    }
    else if(r>3)
    {
      my[2]+=fx*critical_factor*r*r;
      my[3]+=fy*critical_factor*r*r;
      my[2]-=damp*(my[2]-other[2])*abs(my[2])*abs(my[5]-other[5])*abs(my[1]-other[1]);
      my[3]-=damp*(my[3]-other[3])*abs(my[3])*abs(my[5]-other[5])*abs(my[2]-other[2]);
    }

  }
  buffer[6*id+2]=my[2];
  buffer[6*id+3]=my[3];
  buffer[6*id]+=my[2];
  buffer[6*id+1]+=my[3];
  if(buffer[6*id]>SCREEN_WIDTH)
  {
    buffer[6*id+2]=-buffer[6*id+2];
    buffer[6*id]=SCREEN_WIDTH-2;
  }
  else if(buffer[6*id]<0)
  {
    buffer[6*id+2]=-buffer[6*id+2];
    buffer[6*id]=2;
  }
  if(buffer[6*id+1]>SCREEN_HEIGHT)
  {
    buffer[6*id+3]=-buffer[6*id+3];
    buffer[6*id+1]=SCREEN_HEIGHT-2;
  }
  else if(buffer[6*id+1]<0)
    {
      buffer[6*id+3]=-buffer[6*id+3];
      buffer[6*id+1]=2;
    }
  __syncthreads();
  for(int i = 0; i< 6; i++)
  {
    d_output[6*id+i]=buffer[6*id+i];
  }
}
extern "C"{
float * calcAndUpdate(float * input, int size)
{
  float * d_input, * d_output;
  float *result = (float *)malloc((size*6+2)*sizeof(float));
  if(size>500)
  {
    return 0;

  }
  cudaMalloc(&d_input,(size*6)*sizeof(float));
  cudaMalloc(&d_output,(size*6)*sizeof(float));
  cudaMemcpy(d_input,input,(size*6)*sizeof(float),cudaMemcpyHostToDevice);
  myop<<<1,size>>>(d_output,d_input,size);
  cudaMemcpy(result,d_output,(size*6)*sizeof(float),cudaMemcpyDeviceToHost);
  // for(int i = 0; i< 6*size; i++)
  // {
  //   printf("%f \t",result[i]);
  //   if(i%6==0)
  //   {
  //     printf("\n");
  //   }
  // }
  return result;

}
}
int main()
{

}

	.file	"tmpxft_00399b53_00000000-6_gravity.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2044:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2044:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2041:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	ret
	.cfi_endproc
.LFE2041:
	.size	main, .-main
	.text
	.globl	_Z26__device_stub__Z4myopPfS_iPfS_i
	.type	_Z26__device_stub__Z4myopPfS_iPfS_i, @function
_Z26__device_stub__Z4myopPfS_iPfS_i:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4myopPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L3:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_Z26__device_stub__Z4myopPfS_iPfS_i, .-_Z26__device_stub__Z4myopPfS_iPfS_i
	.globl	_Z4myopPfS_i
	.type	_Z4myopPfS_i, @function
_Z4myopPfS_i:
.LFB2067:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z4myopPfS_iPfS_i
	.cfi_endproc
.LFE2067:
	.size	_Z4myopPfS_i, .-_Z4myopPfS_i
	.globl	calcAndUpdate
	.type	calcAndUpdate, @function
calcAndUpdate:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	imull	$6, %esi, %ebx
	leal	2(%rbx), %edi
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	cmpl	$500, %ebp
	jg	.L9
	movslq	%ebx, %rbx
	movq	%rsp, %rdi
	movq	%rax, %r13
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%ebp, 28(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, 32(%rsp)
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	%ebp, %edx
	call	_Z26__device_stub__Z4myopPfS_iPfS_i
.L11:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
.L9:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	movq	%r13, %rax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	calcAndUpdate, .-calcAndUpdate
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4myopPfS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2069:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4myopPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2069:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include <signal.h>
#define fg 0.1
#define fe 100
#define damp 0.01
#define critical_factor  0.008
#define SCREEN_WIDTH 600
#define SCREEN_HEIGHT 600
const int MAX_SIZE = 500;
// [self.x,self.y,self.vx,self.vy,self.m,self.charge]
//    0     1       2       3       4       5
__global__ void myop( float * d_output, float *d_input,int size)
{
  __shared__ float buffer[MAX_SIZE*6];
  int id = threadIdx.x;
  float my[6];
  for(int i = 0; i< 6; i++)
  {
    float temp  =d_input[6*id+i];
  buffer[6*id+i]=temp;
  my[i]=temp;

  }
  __syncthreads();

  for(int i = 0; i< size; i++)
  {
    if(i==id)
    continue;
    float other[6];
    for(int j = 0; j<6;j++)
    {
      other[j]=buffer[6*i+j];
    }
    float dx = my[0]-other[0];
    float dy = my[1]-other[1];
    float r = sqrtf(dx*dx+dy*dy);
    float fx =-(fg*my[4]*other[4]-fe*my[5]*other[5])*dx;
    fx=fx/(r*r*r);
    float fy =-(fg*my[4]*other[4]-fe*my[5]*other[5])*dy;
    fy=fy/(r*r*r);
    if(r>10)
    {
      my[2]+=(fx/my[4]);
      my[3]+=(fy/my[4]);
    }
    else if(r>3)
    {
      my[2]+=fx*critical_factor*r*r;
      my[3]+=fy*critical_factor*r*r;
      my[2]-=damp*(my[2]-other[2])*abs(my[2])*abs(my[5]-other[5])*abs(my[1]-other[1]);
      my[3]-=damp*(my[3]-other[3])*abs(my[3])*abs(my[5]-other[5])*abs(my[2]-other[2]);
    }

  }
  buffer[6*id+2]=my[2];
  buffer[6*id+3]=my[3];
  buffer[6*id]+=my[2];
  buffer[6*id+1]+=my[3];
  if(buffer[6*id]>SCREEN_WIDTH)
  {
    buffer[6*id+2]=-buffer[6*id+2];
    buffer[6*id]=SCREEN_WIDTH-2;
  }
  else if(buffer[6*id]<0)
  {
    buffer[6*id+2]=-buffer[6*id+2];
    buffer[6*id]=2;
  }
  if(buffer[6*id+1]>SCREEN_HEIGHT)
  {
    buffer[6*id+3]=-buffer[6*id+3];
    buffer[6*id+1]=SCREEN_HEIGHT-2;
  }
  else if(buffer[6*id+1]<0)
    {
      buffer[6*id+3]=-buffer[6*id+3];
      buffer[6*id+1]=2;
    }
  __syncthreads();
  for(int i = 0; i< 6; i++)
  {
    d_output[6*id+i]=buffer[6*id+i];
  }
}
extern "C"{
float * calcAndUpdate(float * input, int size)
{
  float * d_input, * d_output;
  float *result = (float *)malloc((size*6+2)*sizeof(float));
  if(size>500)
  {
    return 0;

  }
  hipMalloc(&d_input,(size*6)*sizeof(float));
  hipMalloc(&d_output,(size*6)*sizeof(float));
  hipMemcpy(d_input,input,(size*6)*sizeof(float),hipMemcpyHostToDevice);
  myop<<<1,size>>>(d_output,d_input,size);
  hipMemcpy(result,d_output,(size*6)*sizeof(float),hipMemcpyDeviceToHost);
  // for(int i = 0; i< 6*size; i++)
  // {
  //   printf("%f \t",result[i]);
  //   if(i%6==0)
  //   {
  //     printf("\n");
  //   }
  // }
  return result;

}
}
int main()
{

}

	.text
	.file	"gravity.hip"
	.globl	_Z19__device_stub__myopPfS_i    # -- Begin function _Z19__device_stub__myopPfS_i
	.type	_Z19__device_stub__myopPfS_i,@function
_Z19__device_stub__myopPfS_i:           # @_Z19__device_stub__myopPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4myopPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__myopPfS_i, .Lfunc_end0-_Z19__device_stub__myopPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	calcAndUpdate                   # -- Begin function calcAndUpdate
	.type	calcAndUpdate,@function
calcAndUpdate:                          # @calcAndUpdate
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %r15d
	movq	%rdi, %r12
	leal	(%r15,%r15), %eax
	leal	(%rax,%rax,2), %eax
	movslq	%eax, %r14
	leaq	8(,%r14,4), %rdi
	callq	malloc
	cmpl	$500, %r15d                     # imm = 0x1F4
	jle	.LBB1_2
# %bb.1:
	xorl	%ebx, %ebx
	jmp	.LBB1_5
.LBB1_2:
	movq	%rax, %rbx
	shlq	$2, %r14
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r15d, %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	callq	_Z19__device_stub__myopPfS_i
.LBB1_4:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
.LBB1_5:
	movq	%rbx, %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	calcAndUpdate, .Lfunc_end1-calcAndUpdate
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4myopPfS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4myopPfS_i,@object            # @_Z4myopPfS_i
	.section	.rodata,"a",@progbits
	.globl	_Z4myopPfS_i
	.p2align	3, 0x0
_Z4myopPfS_i:
	.quad	_Z19__device_stub__myopPfS_i
	.size	_Z4myopPfS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4myopPfS_i"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__myopPfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4myopPfS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4myopPfS_i            ; -- Begin function _Z4myopPfS_i
	.globl	_Z4myopPfS_i
	.p2align	8
	.type	_Z4myopPfS_i,@function
_Z4myopPfS_i:                           ; @_Z4myopPfS_i
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mul_u32_u24_e32 v13, 6, v0
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v12, 2, v13
	v_mov_b32_e32 v8, v12
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s2, s10, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, null, s11, 0, s2
	s_mov_b64 s[10:11], 0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, 4
	s_cmp_eq_u32 s10, 5
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s10, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s10, 3
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s10, 2
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s10, 1
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s10, 0
	s_cselect_b32 s6, -1, 0
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s10, 6
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v9
	v_dual_cndmask_b32 v5, v5, v9 :: v_dual_add_nc_u32 v8, 4, v8
	v_cndmask_b32_e64 v4, v4, v9, s2
	v_cndmask_b32_e64 v3, v3, v9, s3
	v_cndmask_b32_e64 v2, v2, v9, s4
	v_cndmask_b32_e64 v1, v1, v9, s5
	v_cndmask_b32_e64 v14, v14, v9, s6
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_load_b32 s5, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_15
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s6, 0x9999999a
	s_mov_b32 s10, 0xd2f1a9fc
	s_mov_b32 s12, 0x47ae147b
	s_mov_b32 s7, 0x3fb99999
	s_mov_b32 s11, 0x3f80624d
	s_mov_b32 s13, 0x3f847ae1
	s_mov_b32 s16, 0
	s_mov_b32 s17, 0
                                        ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
.LBB0_4:                                ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	s_mov_b32 s18, exec_lo
	v_cmpx_ne_u32_e64 s17, v0
	s_cbranch_execz .LBB0_14
; %bb.5:                                ; %.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b32 s19, s16
.LBB0_6:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v15, s19
	s_cmp_eq_u32 s14, 5
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s14, 4
	ds_load_b32 v15, v15
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s14, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s14, 2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s14, 1
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cselect_b32 s4, -1, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_add_i32 s19, s19, 4
	s_cmp_eq_u32 s14, 6
	s_waitcnt lgkmcnt(0)
	v_cndmask_b32_e32 v11, v11, v15, vcc_lo
	v_cndmask_b32_e64 v10, v10, v15, s0
	v_cndmask_b32_e64 v9, v9, v15, s1
	v_cndmask_b32_e64 v8, v8, v15, s2
	v_cndmask_b32_e64 v7, v7, v15, s3
	v_cndmask_b32_e64 v6, v6, v15, s4
	s_cbranch_scc0 .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	v_cvt_f64_f32_e32 v[15:16], v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v14, v6
	v_cvt_f64_f32_e32 v[23:24], v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[15:16], s[6:7]
	v_sub_f32_e32 v15, v1, v7
	v_mul_f32_e32 v17, 0xc2c80000, v5
	v_mul_f32_e32 v19, v17, v11
	v_cvt_f64_f32_e32 v[17:18], v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[19:20], v19
	v_fma_f64 v[16:17], v[21:22], v[17:18], v[19:20]
	v_cvt_f64_f32_e32 v[18:19], v15
	v_mul_f32_e32 v22, v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v25, v25
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v22
	v_mul_f64 v[20:21], v[23:24], -v[16:17]
	v_mul_f64 v[16:17], v[18:19], -v[16:17]
	v_mul_f32_e32 v18, 0x4f800000, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v18, v22, v18, vcc_lo
	v_sqrt_f32_e32 v19, v18
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v23, 1, v19
	v_add_nc_u32_e32 v22, -1, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v23, v19, v18
	v_fma_f32 v24, -v22, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e64 s0, 0, v24
	v_cvt_f32_f64_e32 v20, v[20:21]
	v_cvt_f32_f64_e32 v16, v[16:17]
	v_cndmask_b32_e64 v17, v19, v22, s0
	v_cmp_lt_f32_e64 s0, 0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v17, v23, s0
	v_mul_f32_e32 v19, 0x37800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v17, v19, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v18, 0x260
	v_cndmask_b32_e32 v18, v17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v18
	v_mul_f32_e32 v19, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v17, null, v19, v19, v20
	v_div_scale_f32 v21, null, v19, v19, v16
	v_div_scale_f32 v26, vcc_lo, v20, v19, v20
	v_rcp_f32_e32 v22, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v17, v22, 1.0
	v_fma_f32 v25, -v21, v23, 1.0
	v_fmac_f32_e32 v22, v24, v22
	v_div_scale_f32 v24, s0, v16, v19, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v23, v25, v23
	v_mul_f32_e32 v25, v26, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, v24, v23
	v_fma_f32 v28, -v17, v25, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, -v21, v27, v24
	v_fmac_f32_e32 v25, v28, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, v29, v23
	v_fma_f32 v17, -v17, v25, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v21, v27, v24
	v_div_fmas_f32 v17, v17, v22, v25
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v21, v21, v23, v27
	v_div_fixup_f32 v17, v17, v19, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v16, v21, v19, v16
	v_cmpx_nlt_f32_e32 0x41200000, v18
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_f32_e32 0x40400000, v18
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	v_cvt_f64_f32_e32 v[19:20], v17
	v_cvt_f64_f32_e32 v[17:18], v18
	v_cvt_f64_f32_e32 v[21:22], v2
	v_cvt_f64_f32_e32 v[2:3], v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[19:20], s[10:11]
	v_mul_f64 v[19:20], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[19:20], v[17:18], v[21:22]
	v_cvt_f64_f32_e32 v[21:22], v16
	v_cvt_f32_f64_e32 v23, v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[21:22], s[10:11]
	v_mul_f64 v[19:20], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[19:20], v[17:18], v[2:3]
	v_sub_f32_e32 v20, v5, v11
	v_cvt_f32_f64_e32 v24, v[2:3]
	v_sub_f32_e32 v16, v23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[21:22], v16
	v_cvt_f64_f32_e64 v[16:17], |v23|
	v_mul_f64 v[18:19], v[21:22], s[12:13]
	v_cvt_f64_f32_e64 v[20:21], |v20|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f64 v[2:3], v[18:19], v[16:17]
	v_sub_f32_e32 v19, v24, v9
	v_cvt_f64_f32_e64 v[15:16], |v15|
	v_cvt_f64_f32_e32 v[17:18], v23
	v_cvt_f64_f32_e32 v[22:23], v19
	v_mul_f64 v[2:3], v[2:3], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[2:3], -v[2:3], v[15:16], v[17:18]
	v_cvt_f64_f32_e64 v[15:16], |v24|
	v_mul_f64 v[17:18], v[22:23], s[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v2, v[2:3]
	v_mul_f64 v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v2, v8
	v_mul_f64 v[15:16], v[15:16], v[20:21]
	v_cvt_f64_f32_e32 v[19:20], v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e64 v[17:18], |v3|
	v_fma_f64 v[15:16], -v[15:16], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v3, v[15:16]
.LBB0_10:                               ; %Flow137
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
.LBB0_11:                               ; %Flow139
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=1
	v_div_scale_f32 v15, null, v4, v4, v17
	v_div_scale_f32 v18, null, v4, v4, v16
	v_div_scale_f32 v23, vcc_lo, v17, v4, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v19, v15
	v_rcp_f32_e32 v20, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v15, v19, 1.0
	v_fma_f32 v22, -v18, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v19, v21, v19 :: v_dual_fmac_f32 v20, v22, v20
	v_div_scale_f32 v21, s0, v16, v4, v16
	v_mul_f32_e32 v22, v23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, v21, v20
	v_fma_f32 v25, -v15, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v18, v24, v21
	v_fmac_f32_e32 v22, v25, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, v26, v20
	v_fma_f32 v15, -v15, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v18, v24, v21
	v_div_fmas_f32 v15, v15, v19, v22
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v18, v18, v20, v24
	v_div_fixup_f32 v15, v15, v4, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v16, v18, v4, v16
	v_dual_add_f32 v2, v2, v15 :: v_dual_add_f32 v3, v3, v16
.LBB0_13:                               ; %Flow140
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_14:                               ; %Flow142
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s17, s17, 1
	s_add_i32 s16, s16, 24
	s_cmp_eq_u32 s17, s5
	s_cbranch_scc0 .LBB0_4
.LBB0_15:                               ; %Flow144
	v_dual_mov_b32 v5, 0x44158000 :: v_dual_lshlrev_b32 v4, 2, v13
	s_mov_b32 s1, exec_lo
	ds_load_b64 v[0:1], v4
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0x44160000, v0
	ds_store_2addr_b64 v4, v[0:1], v[2:3] offset1:1
	v_cmpx_nlt_f32_e32 0x44160000, v0
; %bb.16:
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v5, 2.0
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s2
; %bb.17:                               ; %Flow136
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_19
; %bb.18:                               ; %.sink.split
	v_xor_b32_e32 v0, 0x80000000, v2
	ds_store_2addr_b32 v4, v5, v0 offset1:2
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_lt_f32_e64 s0, 0x44160000, v1
	v_mov_b32_e32 v0, 0x44158000
	s_mov_b32 s1, exec_lo
	v_cmpx_nlt_f32_e32 0x44160000, v1
; %bb.20:
	v_cmp_gt_f32_e32 vcc_lo, 0, v1
	v_mov_b32_e32 v0, 2.0
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s2
; %bb.21:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ; %.sink.split100
	v_xor_b32_e32 v1, 0x80000000, v3
	ds_store_2addr_b32 v4, v0, v1 offset0:1 offset1:3
.LBB0_23:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v0, s0, s8, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s9, 0, s0
	s_movk_i32 s0, 0xffe8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_24:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s0, v4
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	ds_load_b32 v2, v2 offset:24
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc0 .LBB0_24
; %bb.25:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4myopPfS_i
		.amdhsa_group_segment_fixed_size 12000
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4myopPfS_i, .Lfunc_end0-_Z4myopPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1724
; NumSgprs: 22
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 12000 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 12000
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4myopPfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z4myopPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
