#include "includes.h"
/*
*  This program is a CUDA C program simulating the N-body system
*    of two galaxies as PHY 241 FINAL PROJECTS
*
*/

/*
*  TODO:
*    1. andromeda
*    2. For accel of center of A, only consider accel from center of B. The same for B.
*    3. When the distance between A and B, the soft parameter changed to 0.2Rmin
*    4. report
*    5. presentation
*
*/



/*
**  Modify the constant parameters if neccessary
**    Constant Section
*/
#define PI 3.14159265
#define BUFFERSIZE 256
#ifndef BLOCKSIZE
#define BLOCKSIZE 256
#endif
//#define SOFTPARAMETER 0.2 * RMIN
// #define AU 149597870700.0
// #define R (77871.0 * 1000.0 / AU)
// #define G (4.0 * pow(PI, 2))
#define G 0.287915013
#define MASS_1 1000              // Center mass of 1st galaxy
#define MASS_2 1000                // Center mass of 2nd galaxy
#define NUM_OF_RING_1 12         // Number of rings in 1st galaxy
#define NUM_OF_RING_2 12          // Number of rings in 2nd galaxy
// #define RING_BASE_1 (R * 0.2)       // Radius of first ring in 1st galaxy
// #define RING_BASE_2 (R * 0.2)       // Radius of first ring in 2nd galaxy
#define NUM_P_BASE 12             // Number of particles in the first ring
#define INC_NUM_P 3               // increment of number of particles each step
// #define INC_R_RING (0.5 * R)      // increment of radius of rings each step
#define PMASS 1             // mass of each particle
#define V_PARAMTER 1            // Parameter adding to initial velocity to make it elliptic
#define RMIN 1
#define ECCEN 0.5
#define RMAX ((1.0 + ECCEN) * RMIN / (1.0 - ECCEN))
#define RING_BASE_1 (RMIN * 0.2)       // Radius of first ring in 1st galaxy
#define RING_BASE_2 (RMIN * 0.2)       // Radius of first ring in 2nd galaxy
#define INC_R_RING (RMIN * 0.05)      // increment of radius of rings each step
#define SOFTPARAMETER 0.000001
/*
*  Major Function Declarations Section
*
*/


/*
*  Functions Implmenetation Section
*
*/

__global__ void accel(int n, double *x, double *y, double *z, double *vx, double *vy, double *vz, double* mass, double dt){
const unsigned int serial = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int tdx = threadIdx.x;
__shared__ double lx[BLOCKSIZE];
__shared__ double ly[BLOCKSIZE];
__shared__ double lz[BLOCKSIZE];

if(serial < n){
double ax = 0.0, ay = 0.0, az = 0.0, norm, thisX = x[serial], thisY = y[serial], thisZ = z[serial];
for(int i = 0; i < gridDim.x; i++){
// Copy data from main memory
lx[tdx] = x[i * BLOCKSIZE + tdx];
lz[tdx] = y[i * BLOCKSIZE + tdx];
ly[tdx] = z[i * BLOCKSIZE + tdx];
__syncthreads();

// Accumulates the acceleration
int itrSize = min(BLOCKSIZE, n - i * BLOCKSIZE);
for(int j = 0; j < itrSize; j++){
norm = pow(SOFTPARAMETER + pow(thisX - lx[j], 2) + pow(thisY - ly[j], 2) + pow(thisZ - lz[j], 2), 1.5);
if(i * BLOCKSIZE + j != serial){
ax += - G * mass[i * BLOCKSIZE + j] * (thisX - lx[j]) / norm;
ay += - G * mass[i * BLOCKSIZE + j] * (thisY - ly[j]) / norm;
az += - G * mass[i * BLOCKSIZE + j] * (thisZ - lz[j]) / norm;
}
}
}

// Updates velocities in each directions
vx[serial] += 0.5 * dt * ax;
vy[serial] += 0.5 * dt * ay;
vz[serial] += 0.5 * dt * az;
}
}
	.file	"tmpxft_002acd38_00000000-6_accel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z5acceliPdS_S_S_S_S_S_diPdS_S_S_S_S_S_d
	.type	_Z38__device_stub__Z5acceliPdS_S_S_S_S_S_diPdS_S_S_S_S_S_d, @function
_Z38__device_stub__Z5acceliPdS_S_S_S_S_S_diPdS_S_S_S_S_S_d:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 16(%rsp)
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z5acceliPdS_S_S_S_S_S_d(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z38__device_stub__Z5acceliPdS_S_S_S_S_S_diPdS_S_S_S_S_S_d, .-_Z38__device_stub__Z5acceliPdS_S_S_S_S_S_diPdS_S_S_S_S_S_d
	.globl	_Z5acceliPdS_S_S_S_S_S_d
	.type	_Z5acceliPdS_S_S_S_S_S_d, @function
_Z5acceliPdS_S_S_S_S_S_d:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z5acceliPdS_S_S_S_S_S_diPdS_S_S_S_S_S_d
	.cfi_endproc
.LFE2033:
	.size	_Z5acceliPdS_S_S_S_S_S_d, .-_Z5acceliPdS_S_S_S_S_S_d
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5acceliPdS_S_S_S_S_S_d"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5acceliPdS_S_S_S_S_S_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/*
*  This program is a CUDA C program simulating the N-body system
*    of two galaxies as PHY 241 FINAL PROJECTS
*
*/

/*
*  TODO:
*    1. andromeda
*    2. For accel of center of A, only consider accel from center of B. The same for B.
*    3. When the distance between A and B, the soft parameter changed to 0.2Rmin
*    4. report
*    5. presentation
*
*/



/*
**  Modify the constant parameters if neccessary
**    Constant Section
*/
#define PI 3.14159265
#define BUFFERSIZE 256
#ifndef BLOCKSIZE
#define BLOCKSIZE 256
#endif
//#define SOFTPARAMETER 0.2 * RMIN
// #define AU 149597870700.0
// #define R (77871.0 * 1000.0 / AU)
// #define G (4.0 * pow(PI, 2))
#define G 0.287915013
#define MASS_1 1000              // Center mass of 1st galaxy
#define MASS_2 1000                // Center mass of 2nd galaxy
#define NUM_OF_RING_1 12         // Number of rings in 1st galaxy
#define NUM_OF_RING_2 12          // Number of rings in 2nd galaxy
// #define RING_BASE_1 (R * 0.2)       // Radius of first ring in 1st galaxy
// #define RING_BASE_2 (R * 0.2)       // Radius of first ring in 2nd galaxy
#define NUM_P_BASE 12             // Number of particles in the first ring
#define INC_NUM_P 3               // increment of number of particles each step
// #define INC_R_RING (0.5 * R)      // increment of radius of rings each step
#define PMASS 1             // mass of each particle
#define V_PARAMTER 1            // Parameter adding to initial velocity to make it elliptic
#define RMIN 1
#define ECCEN 0.5
#define RMAX ((1.0 + ECCEN) * RMIN / (1.0 - ECCEN))
#define RING_BASE_1 (RMIN * 0.2)       // Radius of first ring in 1st galaxy
#define RING_BASE_2 (RMIN * 0.2)       // Radius of first ring in 2nd galaxy
#define INC_R_RING (RMIN * 0.05)      // increment of radius of rings each step
#define SOFTPARAMETER 0.000001
/*
*  Major Function Declarations Section
*
*/


/*
*  Functions Implmenetation Section
*
*/

__global__ void accel(int n, double *x, double *y, double *z, double *vx, double *vy, double *vz, double* mass, double dt){
const unsigned int serial = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int tdx = threadIdx.x;
__shared__ double lx[BLOCKSIZE];
__shared__ double ly[BLOCKSIZE];
__shared__ double lz[BLOCKSIZE];

if(serial < n){
double ax = 0.0, ay = 0.0, az = 0.0, norm, thisX = x[serial], thisY = y[serial], thisZ = z[serial];
for(int i = 0; i < gridDim.x; i++){
// Copy data from main memory
lx[tdx] = x[i * BLOCKSIZE + tdx];
lz[tdx] = y[i * BLOCKSIZE + tdx];
ly[tdx] = z[i * BLOCKSIZE + tdx];
__syncthreads();

// Accumulates the acceleration
int itrSize = min(BLOCKSIZE, n - i * BLOCKSIZE);
for(int j = 0; j < itrSize; j++){
norm = pow(SOFTPARAMETER + pow(thisX - lx[j], 2) + pow(thisY - ly[j], 2) + pow(thisZ - lz[j], 2), 1.5);
if(i * BLOCKSIZE + j != serial){
ax += - G * mass[i * BLOCKSIZE + j] * (thisX - lx[j]) / norm;
ay += - G * mass[i * BLOCKSIZE + j] * (thisY - ly[j]) / norm;
az += - G * mass[i * BLOCKSIZE + j] * (thisZ - lz[j]) / norm;
}
}
}

// Updates velocities in each directions
vx[serial] += 0.5 * dt * ax;
vy[serial] += 0.5 * dt * ay;
vz[serial] += 0.5 * dt * az;
}
}
	.text
	.file	"accel.hip"
	.globl	_Z20__device_stub__acceliPdS_S_S_S_S_S_d # -- Begin function _Z20__device_stub__acceliPdS_S_S_S_S_S_d
	.type	_Z20__device_stub__acceliPdS_S_S_S_S_S_d,@function
_Z20__device_stub__acceliPdS_S_S_S_S_S_d: # @_Z20__device_stub__acceliPdS_S_S_S_S_S_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	72(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	64(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5acceliPdS_S_S_S_S_S_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__acceliPdS_S_S_S_S_S_d, .Lfunc_end0-_Z20__device_stub__acceliPdS_S_S_S_S_S_d
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5acceliPdS_S_S_S_S_S_d, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5acceliPdS_S_S_S_S_S_d,@object # @_Z5acceliPdS_S_S_S_S_S_d
	.section	.rodata,"a",@progbits
	.globl	_Z5acceliPdS_S_S_S_S_S_d
	.p2align	3, 0x0
_Z5acceliPdS_S_S_S_S_S_d:
	.quad	_Z20__device_stub__acceliPdS_S_S_S_S_S_d
	.size	_Z5acceliPdS_S_S_S_S_S_d, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5acceliPdS_S_S_S_S_S_d"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__acceliPdS_S_S_S_S_S_d
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5acceliPdS_S_S_S_S_S_d
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5acceliPdS_S_S_S_S_S_d ; -- Begin function _Z5acceliPdS_S_S_S_S_S_d
	.globl	_Z5acceliPdS_S_S_S_S_S_d
	.p2align	8
	.type	_Z5acceliPdS_S_S_S_S_S_d,@function
_Z5acceliPdS_S_S_S_S_S_d:               ; @_Z5acceliPdS_S_S_S_S_S_d
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x54
	s_load_b32 s5, s[0:1], 0x0
	s_add_u32 s2, s0, 0x48
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s5, v3
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_load_b32 s33, s[2:3], 0x0
	s_load_b512 s[8:23], s[0:1], 0x8
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	s_mov_b32 s84, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v5
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s33, 0
	s_cbranch_scc1 .LBB0_9
; %bb.2:                                ; %.lr.ph97
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v2, vcc_lo
	v_add_co_u32 v11, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v13, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v2, vcc_lo
	global_load_b64 v[9:10], v[6:7], off
	global_load_b64 v[11:12], v[11:12], off
	global_load_b64 v[13:14], v[13:14], off
	v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v4, 3, v0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v27, 0x3ff00000
	s_mov_b32 s6, 0x55555555
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v25, 0x1000, v4
	v_add_nc_u32_e32 v26, 0x800, v4
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_mov_b32 s24, 0xfefa39ef
	s_mov_b32 s26, 0x3b39803f
	s_mov_b32 s28, 0x968915a9
	s_mov_b32 s30, 0x4222de17
	s_mov_b32 s34, 0x3abe935a
	s_mov_b32 s36, 0x47e6c9c2
	s_mov_b32 s38, 0xcfa74449
	s_mov_b32 s40, 0x71bf3c30
	s_mov_b32 s42, 0x1c7792ce
	s_mov_b32 s44, 0x924920da
	s_mov_b32 s46, 0x9999999c
	s_mov_b32 s48, 0xd5df274d
	s_mov_b32 s52, 0x652b82fe
	s_mov_b32 s54, 0xfca7ab0c
	s_mov_b32 s56, 0x6a5dcb37
	s_mov_b32 s58, 0x623fde64
	s_mov_b32 s60, 0x7c89e6b0
	s_mov_b32 s62, 0x14761f6e
	s_mov_b32 s64, 0x1852b7b0
	s_mov_b32 s66, 0x11122322
	s_mov_b32 s68, 0x555502a1
	s_mov_b32 s70, 0x55555511
	s_mov_b32 s72, 11
	s_mov_b32 s74, 0xa0b5ed8d
	s_mov_b32 s76, 0x173731ce
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s25, 0x3fe62e42
	s_mov_b32 s27, 0x3c7abc9e
	s_mov_b32 s29, 0x3fba6564
	s_mov_b32 s31, 0x3fbdee67
	s_mov_b32 s35, 0x3fbe25e4
	s_mov_b32 s37, 0x3fc110ef
	s_mov_b32 s39, 0x3fc3b13b
	s_mov_b32 s41, 0x3fc745d1
	s_mov_b32 s43, 0x3fcc71c7
	s_mov_b32 s45, 0x3fd24924
	s_mov_b32 s47, 0x3fd99999
	s_mov_b32 s49, 0x3c8543b0
	s_mov_b32 s51, 0xbfe55555
	s_mov_b32 s53, 0x3ff71547
	s_mov_b32 s55, 0x3e928af3
	s_mov_b32 s57, 0x3e5ade15
	s_mov_b32 s59, 0x3ec71dee
	s_mov_b32 s61, 0x3efa0199
	s_mov_b32 s63, 0x3f2a01a0
	s_mov_b32 s65, 0x3f56c16c
	s_mov_b32 s67, 0x3f811111
	s_mov_b32 s69, 0x3fa55555
	s_mov_b32 s71, 0x3fc55555
	s_mov_b32 s73, 0x3fe00000
	s_mov_b32 s75, 0x3eb0c6f7
	s_mov_b32 s77, 0xbfd26d33
	s_mov_b32 s79, 0xbfe62e42
	s_mov_b32 s81, 0xbc7abc9e
	s_mov_b32 s85, s5
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_lshl_b32 s0, s84, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v20, v5 :: v_dual_add_nc_u32 v19, s0, v0
	s_cmp_ge_i32 s0, s5
	v_lshlrev_b64 v[19:20], 3, v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, s8, v19
	v_add_co_ci_u32_e32 v22, vcc_lo, s9, v20, vcc_lo
	v_add_co_u32 v23, vcc_lo, s10, v19
	v_add_co_ci_u32_e32 v24, vcc_lo, s11, v20, vcc_lo
	v_add_co_u32 v19, vcc_lo, s12, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s13, v20, vcc_lo
	global_load_b64 v[21:22], v[21:22], off
	global_load_b64 v[23:24], v[23:24], off
	global_load_b64 v[19:20], v[19:20], off
	s_waitcnt vmcnt(2)
	ds_store_b64 v4, v[21:22]
	s_waitcnt vmcnt(1)
	ds_store_b64 v25, v[23:24]
	s_waitcnt vmcnt(0)
	ds_store_b64 v26, v[19:20]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_8
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_med3_i32 v28, s85, 1, 0x100
	v_mov_b32_e32 v29, v3
	s_mov_b32 s86, 0
	s_mov_b64 s[82:83], s[20:21]
.LBB0_5:                                ; %.lr.ph
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s87, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v29
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v6, s86
	s_mov_b32 s50, s6
	s_mov_b32 s78, s24
	s_mov_b32 s80, s26
	s_load_b64 s[88:89], s[82:83], 0x0
	ds_load_2addr_stride64_b64 v[19:22], v6 offset1:4
	ds_load_b64 v[23:24], v6 offset:4096
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[19:20], v[9:10], -v[19:20]
	v_add_f64 v[21:22], v[11:12], -v[21:22]
	v_add_f64 v[23:24], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f64_e64 v[30:31], |v[19:20]|
	v_frexp_mant_f64_e64 v[32:33], |v[21:22]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f64_e64 v[34:35], |v[23:24]|
	v_cmp_gt_f64_e64 s1, s[6:7], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e64 s0, s[6:7], v[32:33]
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, 0, 1, s1
	v_ldexp_f64 v[30:31], v[30:31], v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, 0, 1, s0
	v_ldexp_f64 v[32:33], v[32:33], v6
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_ldexp_f64 v[34:35], v[34:35], v6
	v_frexp_exp_i32_f64_e32 v6, v[19:20]
	v_add_f64 v[36:37], v[30:31], 1.0
	v_add_f64 v[52:53], v[30:31], -1.0
	v_add_f64 v[38:39], v[32:33], 1.0
	v_add_f64 v[54:55], v[32:33], -1.0
	v_add_f64 v[42:43], v[34:35], 1.0
	v_add_f64 v[56:57], v[34:35], -1.0
	v_subrev_co_ci_u32_e64 v6, s1, 0, v6, s1
	v_rcp_f64_e32 v[40:41], v[36:37]
	v_add_f64 v[58:59], v[36:37], -1.0
	v_rcp_f64_e32 v[44:45], v[38:39]
	v_add_f64 v[64:65], v[38:39], -1.0
	v_rcp_f64_e32 v[48:49], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_add_f64 v[30:31], v[30:31], -v[58:59]
	v_fma_f64 v[46:47], -v[36:37], v[40:41], 1.0
	v_add_f64 v[58:59], v[42:43], -1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_2)
	v_add_f64 v[32:33], v[32:33], -v[64:65]
	v_fma_f64 v[50:51], -v[38:39], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fma_f64 v[40:41], v[46:47], v[40:41], v[40:41]
	v_fma_f64 v[46:47], -v[42:43], v[48:49], 1.0
	v_add_f64 v[34:35], v[34:35], -v[58:59]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[44:45], v[50:51], v[44:45], v[44:45]
	v_fma_f64 v[50:51], -v[36:37], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[46:47], v[48:49], v[48:49]
	v_fma_f64 v[48:49], -v[38:39], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], v[50:51], v[40:41], v[40:41]
	v_fma_f64 v[50:51], -v[42:43], v[46:47], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[48:49], v[44:45], v[44:45]
	v_mul_f64 v[48:49], v[52:53], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[50:51], v[46:47], v[46:47]
	v_mul_f64 v[50:51], v[54:55], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[60:61], v[36:37], v[48:49]
	v_mul_f64 v[62:63], v[56:57], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[66:67], v[38:39], v[50:51]
	v_fma_f64 v[36:37], v[48:49], v[36:37], -v[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[68:69], v[42:43], v[62:63]
	v_fma_f64 v[38:39], v[50:51], v[38:39], -v[66:67]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[48:49], v[30:31], v[36:37]
	v_fma_f64 v[36:37], v[62:63], v[42:43], -v[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[50:51], v[32:33], v[38:39]
	v_add_f64 v[38:39], v[60:61], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[62:63], v[34:35], v[36:37]
	v_add_f64 v[36:37], v[66:67], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[52:53], -v[38:39]
	v_add_f64 v[58:59], v[68:69], v[34:35]
	v_add_f64 v[60:61], v[38:39], -v[60:61]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[64:65], v[54:55], -v[36:37]
	v_add_f64 v[66:67], v[36:37], -v[66:67]
	v_add_f64 v[52:53], v[52:53], -v[42:43]
	v_add_f64 v[70:71], v[56:57], -v[58:59]
	v_add_f64 v[30:31], v[60:61], -v[30:31]
	v_add_f64 v[54:55], v[54:55], -v[64:65]
	v_add_f64 v[32:33], v[66:67], -v[32:33]
	v_add_f64 v[38:39], v[52:53], -v[38:39]
	v_add_f64 v[52:53], v[58:59], -v[68:69]
	v_add_f64 v[56:57], v[56:57], -v[70:71]
	v_add_f64 v[36:37], v[54:55], -v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], v[38:39]
	v_add_f64 v[34:35], v[52:53], -v[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[38:39], v[56:57], -v[58:59]
	v_add_f64 v[32:33], v[32:33], v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[42:43], v[30:31]
	v_add_f64 v[34:35], v[34:35], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[64:65], v[32:33]
	v_mul_f64 v[30:31], v[40:41], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[70:71], v[34:35]
	v_mul_f64 v[32:33], v[44:45], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[48:49], v[30:31]
	v_mul_f64 v[34:35], v[46:47], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[38:39], v[50:51], v[32:33]
	v_add_f64 v[40:41], v[36:37], -v[48:49]
	v_mul_f64 v[46:47], v[36:37], v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[42:43], v[62:63], v[34:35]
	v_add_f64 v[44:45], v[38:39], -v[50:51]
	v_mul_f64 v[48:49], v[38:39], v[38:39]
	v_add_f64 v[30:31], v[30:31], -v[40:41]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[40:41], v[42:43], -v[62:63]
	v_mul_f64 v[52:53], v[42:43], v[42:43]
	v_add_f64 v[32:33], v[32:33], -v[44:45]
	v_fma_f64 v[44:45], v[36:37], v[36:37], -v[46:47]
	v_add_f64 v[50:51], v[30:31], v[30:31]
	v_add_f64 v[34:35], v[34:35], -v[40:41]
	v_fma_f64 v[40:41], v[38:39], v[38:39], -v[48:49]
	v_add_f64 v[54:55], v[32:33], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[44:45], v[36:37], v[50:51], v[44:45]
	v_fma_f64 v[50:51], v[42:43], v[42:43], -v[52:53]
	v_add_f64 v[56:57], v[34:35], v[34:35]
	v_fma_f64 v[40:41], v[38:39], v[54:55], v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[54:55], v[46:47], v[44:45]
	v_fma_f64 v[50:51], v[42:43], v[56:57], v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[56:57], v[48:49], v[40:41]
	v_fma_f64 v[58:59], v[54:55], s[30:31], s[28:29]
	v_add_f64 v[46:47], v[54:55], -v[46:47]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[60:61], v[52:53], v[50:51]
	v_mul_f64 v[72:73], v[36:37], v[54:55]
	v_fma_f64 v[62:63], v[56:57], s[30:31], s[28:29]
	v_add_f64 v[48:49], v[56:57], -v[48:49]
	v_mul_f64 v[78:79], v[38:39], v[56:57]
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[34:35]
	v_add_f64 v[44:45], v[44:45], -v[46:47]
	v_fma_f64 v[64:65], v[60:61], s[30:31], s[28:29]
	v_add_f64 v[52:53], v[60:61], -v[52:53]
	v_fma_f64 v[80:81], v[54:55], v[36:37], -v[72:73]
	v_mul_f64 v[84:85], v[42:43], v[60:61]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[34:35]
	v_add_f64 v[40:41], v[40:41], -v[48:49]
	v_fma_f64 v[86:87], v[56:57], v[38:39], -v[78:79]
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[36:37]
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[34:35]
	v_add_f64 v[50:51], v[50:51], -v[52:53]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[38:39]
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[38:39]
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[38:39]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[42:43]
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[42:43]
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[42:43]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[58:59], v[54:55], v[58:59], s[46:47]
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[46:47]
	v_mul_f64 v[66:67], v[54:55], v[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[64:65], v[60:61], v[64:65], s[46:47]
	v_mul_f64 v[68:69], v[56:57], v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[46:47], v[54:55], v[58:59], -v[66:67]
	v_fma_f64 v[54:55], v[54:55], v[30:31], v[80:81]
	v_mul_f64 v[70:71], v[60:61], v[64:65]
	v_ldexp_f64 v[30:31], v[30:31], 1
	v_fma_f64 v[48:49], v[56:57], v[62:63], -v[68:69]
	v_fma_f64 v[56:57], v[56:57], v[32:33], v[86:87]
	v_ldexp_f64 v[32:33], v[32:33], 1
	v_fma_f64 v[46:47], v[44:45], v[58:59], v[46:47]
	v_fma_f64 v[44:45], v[44:45], v[36:37], v[54:55]
	v_fma_f64 v[52:53], v[60:61], v[64:65], -v[70:71]
	v_ldexp_f64 v[36:37], v[36:37], 1
	v_fma_f64 v[48:49], v[40:41], v[62:63], v[48:49]
	v_fma_f64 v[40:41], v[40:41], v[38:39], v[56:57]
	v_ldexp_f64 v[38:39], v[38:39], 1
	v_add_f64 v[58:59], v[66:67], v[46:47]
	v_fma_f64 v[52:53], v[50:51], v[64:65], v[52:53]
	v_add_f64 v[62:63], v[68:69], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[64:65], v[58:59], -v[66:67]
	v_add_f64 v[66:67], v[58:59], s[6:7]
	v_add_f64 v[74:75], v[70:71], v[52:53]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[68:69], v[62:63], -v[68:69]
	v_add_f64 v[76:77], v[62:63], s[6:7]
	v_add_f64 v[46:47], v[46:47], -v[64:65]
	v_add_f64 v[64:65], v[66:67], s[50:51]
	v_add_f64 v[70:71], v[74:75], -v[70:71]
	v_add_f64 v[82:83], v[74:75], s[6:7]
	v_add_f64 v[48:49], v[48:49], -v[68:69]
	v_add_f64 v[68:69], v[76:77], s[50:51]
	v_add_f64 v[46:47], v[46:47], s[48:49]
	v_add_f64 v[58:59], v[58:59], -v[64:65]
	v_add_f64 v[52:53], v[52:53], -v[70:71]
	v_add_f64 v[64:65], v[82:83], s[50:51]
	v_fma_f64 v[70:71], v[60:61], v[42:43], -v[84:85]
	v_add_f64 v[48:49], v[48:49], s[48:49]
	v_add_f64 v[62:63], v[62:63], -v[68:69]
	v_add_f64 v[46:47], v[46:47], v[58:59]
	v_add_f64 v[52:53], v[52:53], s[48:49]
	v_add_f64 v[54:55], v[74:75], -v[64:65]
	v_fma_f64 v[58:59], v[60:61], v[34:35], v[70:71]
	v_add_f64 v[60:61], v[72:73], v[44:45]
	v_ldexp_f64 v[34:35], v[34:35], 1
	v_add_f64 v[48:49], v[48:49], v[62:63]
	v_add_f64 v[56:57], v[66:67], v[46:47]
	v_add_f64 v[52:53], v[52:53], v[54:55]
	v_fma_f64 v[50:51], v[50:51], v[42:43], v[58:59]
	v_add_f64 v[58:59], v[78:79], v[40:41]
	v_add_f64 v[72:73], v[60:61], -v[72:73]
	v_add_f64 v[54:55], v[76:77], v[48:49]
	v_ldexp_f64 v[42:43], v[42:43], 1
	v_add_f64 v[62:63], v[66:67], -v[56:57]
	v_mul_f64 v[64:65], v[60:61], v[56:57]
	v_add_f64 v[66:67], v[82:83], v[52:53]
	v_add_f64 v[68:69], v[84:85], v[50:51]
	v_add_f64 v[78:79], v[58:59], -v[78:79]
	v_add_f64 v[44:45], v[44:45], -v[72:73]
	v_add_f64 v[70:71], v[76:77], -v[54:55]
	v_mul_f64 v[74:75], v[58:59], v[54:55]
	v_add_f64 v[46:47], v[46:47], v[62:63]
	v_fma_f64 v[62:63], v[60:61], v[56:57], -v[64:65]
	v_add_f64 v[76:77], v[82:83], -v[66:67]
	v_mul_f64 v[80:81], v[68:69], v[66:67]
	v_add_f64 v[40:41], v[40:41], -v[78:79]
	v_add_f64 v[48:49], v[48:49], v[70:71]
	v_fma_f64 v[70:71], v[58:59], v[54:55], -v[74:75]
	v_fma_f64 v[46:47], v[60:61], v[46:47], v[62:63]
	v_add_f64 v[60:61], v[68:69], -v[84:85]
	v_add_f64 v[52:53], v[52:53], v[76:77]
	v_fma_f64 v[62:63], v[68:69], v[66:67], -v[80:81]
	v_fma_f64 v[48:49], v[58:59], v[48:49], v[70:71]
	v_frexp_exp_i32_f64_e32 v58, v[21:22]
	v_fma_f64 v[44:45], v[44:45], v[56:57], v[46:47]
	v_add_f64 v[46:47], v[50:51], -v[60:61]
	v_fma_f64 v[50:51], v[68:69], v[52:53], v[62:63]
	v_cvt_f64_i32_e32 v[52:53], v6
	v_frexp_exp_i32_f64_e32 v6, v[23:24]
	v_fma_f64 v[40:41], v[40:41], v[54:55], v[48:49]
	v_subrev_co_ci_u32_e64 v58, s0, 0, v58, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[58:59], v58
	v_add_f64 v[48:49], v[64:65], v[44:45]
	v_fma_f64 v[46:47], v[46:47], v[66:67], v[50:51]
	v_mul_f64 v[66:67], v[52:53], s[24:25]
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_add_f64 v[50:51], v[74:75], v[40:41]
	v_mul_f64 v[68:69], v[58:59], s[24:25]
	v_add_f64 v[54:55], v[48:49], -v[64:65]
	v_add_f64 v[56:57], v[36:37], v[48:49]
	v_add_f64 v[60:61], v[80:81], v[46:47]
	v_add_f64 v[62:63], v[50:51], -v[74:75]
	v_add_f64 v[64:65], v[38:39], v[50:51]
	v_add_f64 v[44:45], v[44:45], -v[54:55]
	v_add_f64 v[36:37], v[56:57], -v[36:37]
	v_cvt_f64_i32_e32 v[54:55], v6
	v_add_f64 v[70:71], v[60:61], -v[80:81]
	v_add_f64 v[72:73], v[42:43], v[60:61]
	v_add_f64 v[40:41], v[40:41], -v[62:63]
	v_add_f64 v[38:39], v[64:65], -v[38:39]
	v_fma_f64 v[62:63], v[52:53], s[24:25], -v[66:67]
	v_add_f64 v[30:31], v[30:31], v[44:45]
	v_add_f64 v[36:37], v[48:49], -v[36:37]
	v_mul_f64 v[44:45], v[54:55], s[24:25]
	v_add_f64 v[46:47], v[46:47], -v[70:71]
	v_add_f64 v[42:43], v[72:73], -v[42:43]
	v_fma_f64 v[48:49], v[58:59], s[24:25], -v[68:69]
	v_add_f64 v[32:33], v[32:33], v[40:41]
	v_add_f64 v[38:39], v[50:51], -v[38:39]
	v_fma_f64 v[40:41], v[52:53], s[26:27], v[62:63]
	v_add_f64 v[30:31], v[30:31], v[36:37]
	v_fma_f64 v[36:37], v[54:55], s[24:25], -v[44:45]
	v_add_f64 v[34:35], v[34:35], v[46:47]
	v_add_f64 v[42:43], v[60:61], -v[42:43]
	v_fma_f64 v[46:47], v[58:59], s[26:27], v[48:49]
	v_add_f64 v[32:33], v[32:33], v[38:39]
	v_add_f64 v[38:39], v[66:67], v[40:41]
	v_add_f64 v[48:49], v[56:57], v[30:31]
	v_fma_f64 v[36:37], v[54:55], s[26:27], v[36:37]
	v_add_f64 v[34:35], v[34:35], v[42:43]
	v_add_f64 v[42:43], v[68:69], v[46:47]
	v_add_f64 v[50:51], v[64:65], v[32:33]
	v_add_f64 v[66:67], v[38:39], -v[66:67]
	v_add_f64 v[52:53], v[38:39], v[48:49]
	v_add_f64 v[54:55], v[44:45], v[36:37]
	v_add_f64 v[56:57], v[48:49], -v[56:57]
	v_add_f64 v[58:59], v[72:73], v[34:35]
	v_add_f64 v[68:69], v[42:43], -v[68:69]
	v_add_f64 v[60:61], v[42:43], v[50:51]
	v_add_f64 v[64:65], v[50:51], -v[64:65]
	v_add_f64 v[40:41], v[40:41], -v[66:67]
	v_add_f64 v[62:63], v[52:53], -v[38:39]
	v_add_f64 v[44:45], v[54:55], -v[44:45]
	v_add_f64 v[30:31], v[30:31], -v[56:57]
	v_add_f64 v[70:71], v[54:55], v[58:59]
	v_add_f64 v[56:57], v[58:59], -v[72:73]
	v_add_f64 v[46:47], v[46:47], -v[68:69]
	v_add_f64 v[74:75], v[60:61], -v[42:43]
	v_add_f64 v[32:33], v[32:33], -v[64:65]
	v_add_f64 v[76:77], v[52:53], -v[62:63]
	v_add_f64 v[48:49], v[48:49], -v[62:63]
	v_add_f64 v[64:65], v[40:41], v[30:31]
	v_add_f64 v[78:79], v[70:71], -v[54:55]
	v_add_f64 v[36:37], v[36:37], -v[44:45]
	v_add_f64 v[34:35], v[34:35], -v[56:57]
	v_add_f64 v[80:81], v[60:61], -v[74:75]
	v_add_f64 v[50:51], v[50:51], -v[74:75]
	v_add_f64 v[38:39], v[38:39], -v[76:77]
	v_add_f64 v[62:63], v[70:71], -v[78:79]
	v_add_f64 v[44:45], v[58:59], -v[78:79]
	v_add_f64 v[56:57], v[36:37], v[34:35]
	v_add_f64 v[42:43], v[42:43], -v[80:81]
	v_add_f64 v[38:39], v[48:49], v[38:39]
	v_add_f64 v[48:49], v[54:55], -v[62:63]
	v_add_f64 v[54:55], v[46:47], v[32:33]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[42:43], v[50:51], v[42:43]
	v_add_f64 v[50:51], v[64:65], -v[40:41]
	v_add_f64 v[38:39], v[64:65], v[38:39]
	v_add_f64 v[44:45], v[44:45], v[48:49]
	v_add_f64 v[48:49], v[54:55], -v[46:47]
	v_add_f64 v[42:43], v[54:55], v[42:43]
	v_add_f64 v[58:59], v[64:65], -v[50:51]
	v_add_f64 v[64:65], v[56:57], -v[36:37]
	v_add_f64 v[30:31], v[30:31], -v[50:51]
	v_add_f64 v[62:63], v[52:53], v[38:39]
	v_add_f64 v[44:45], v[56:57], v[44:45]
	v_add_f64 v[54:55], v[54:55], -v[48:49]
	v_add_f64 v[32:33], v[32:33], -v[48:49]
	v_add_f64 v[66:67], v[60:61], v[42:43]
	v_add_f64 v[40:41], v[40:41], -v[58:59]
	v_add_f64 v[48:49], v[56:57], -v[64:65]
	v_add_f64 v[34:35], v[34:35], -v[64:65]
	v_add_f64 v[50:51], v[62:63], -v[52:53]
	v_add_f64 v[52:53], v[70:71], v[44:45]
	v_add_f64 v[46:47], v[46:47], -v[54:55]
	v_add_f64 v[54:55], v[66:67], -v[60:61]
	v_add_f64 v[30:31], v[30:31], v[40:41]
	v_add_f64 v[36:37], v[36:37], -v[48:49]
	v_add_f64 v[38:39], v[38:39], -v[50:51]
	v_add_f64 v[40:41], v[52:53], -v[70:71]
	v_add_f64 v[32:33], v[32:33], v[46:47]
	v_add_f64 v[42:43], v[42:43], -v[54:55]
	v_add_f64 v[34:35], v[34:35], v[36:37]
	v_add_f64 v[30:31], v[30:31], v[38:39]
	v_add_f64 v[36:37], v[44:45], -v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[32:33], v[42:43]
	v_add_f64 v[38:39], v[62:63], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[34:35], v[36:37]
	v_add_f64 v[36:37], v[66:67], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[40:41], v[38:39], -v[62:63]
	v_add_f64 v[42:43], v[38:39], v[38:39]
	v_add_f64 v[44:45], v[52:53], v[34:35]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[46:47], v[36:37], -v[66:67]
	v_add_f64 v[48:49], v[36:37], v[36:37]
	v_add_f64 v[30:31], v[30:31], -v[40:41]
	v_fma_f64 v[38:39], v[38:39], 2.0, -v[42:43]
	v_cmp_class_f64_e64 vcc_lo, v[42:43], 0x204
	v_add_f64 v[40:41], v[44:45], -v[52:53]
	v_add_f64 v[50:51], v[44:45], v[44:45]
	v_add_f64 v[32:33], v[32:33], -v[46:47]
	v_fma_f64 v[36:37], v[36:37], 2.0, -v[48:49]
	v_cmp_class_f64_e64 s0, v[48:49], 0x204
	v_fma_f64 v[30:31], v[30:31], 2.0, v[38:39]
	v_add_f64 v[34:35], v[34:35], -v[40:41]
	v_fma_f64 v[38:39], v[44:45], 2.0, -v[50:51]
	v_fma_f64 v[32:33], v[32:33], 2.0, v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[42:43], v[30:31]
	v_fma_f64 v[34:35], v[34:35], 2.0, v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[38:39], v[48:49], v[32:33]
	v_cndmask_b32_e32 v41, v37, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[46:47], v[50:51], v[34:35]
	v_cndmask_b32_e32 v40, v36, v42, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[50:51], 0x204
	v_add_f64 v[36:37], v[36:37], -v[42:43]
	v_cndmask_b32_e64 v53, v39, v49, s0
	v_cndmask_b32_e64 v52, v38, v48, s0
	v_add_f64 v[38:39], v[38:39], -v[48:49]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[54:55], v[52:53], s[52:53]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[52:53]|
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[52:53]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[52:53]
	v_cndmask_b32_e32 v57, v47, v51, vcc_lo
	v_mul_f64 v[44:45], v[40:41], s[52:53]
	v_add_f64 v[30:31], v[30:31], -v[36:37]
	v_cndmask_b32_e32 v56, v46, v50, vcc_lo
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[40:41]|
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[40:41]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[40:41]
	v_add_f64 v[36:37], v[46:47], -v[50:51]
	v_rndne_f64_e32 v[54:55], v[54:55]
	v_add_f64 v[32:33], v[32:33], -v[38:39]
	v_rndne_f64_e32 v[44:45], v[44:45]
	v_cndmask_b32_e32 v31, 0, v31, vcc_lo
	v_mul_f64 v[58:59], v[56:57], s[52:53]
	v_add_f64 v[34:35], v[34:35], -v[36:37]
	v_fma_f64 v[62:63], v[54:55], s[78:79], v[52:53]
	v_cndmask_b32_e64 v33, 0, v33, s2
	v_cndmask_b32_e64 v32, 0, v32, s2
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[56:57]
	v_fma_f64 v[60:61], v[44:45], s[78:79], v[40:41]
	v_cvt_i32_f64_e32 v6, v[44:45]
	v_rndne_f64_e32 v[58:59], v[58:59]
	v_fma_f64 v[62:63], v[54:55], s[80:81], v[62:63]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[60:61], v[44:45], s[80:81], v[60:61]
	v_fma_f64 v[64:65], v[58:59], s[78:79], v[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[62:63], s[56:57], s[54:55]
	v_fma_f64 v[66:67], v[60:61], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[64:65], v[58:59], s[80:81], v[64:65]
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[58:59]
	v_fma_f64 v[70:71], v[64:65], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[60:61]
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[58:59]
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[62:63]
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[64:65]
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[64:65]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[62:63]
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[66:67]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[66:67]
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[64:65]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[68:69]
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[66:67]
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[70:71]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[70:71]
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[62:63], v[68:69], s[72:73]
	v_fma_f64 v[66:67], v[60:61], v[66:67], s[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[70:71]
	v_fma_f64 v[68:69], v[62:63], v[68:69], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[60:61], v[66:67], 1.0
	v_fma_f64 v[70:71], v[64:65], v[70:71], s[72:73]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[44:45], v[60:61], v[66:67], 1.0
	v_cvt_i32_f64_e32 v66, v[54:55]
	v_fma_f64 v[54:55], v[62:63], v[68:69], 1.0
	v_fma_f64 v[60:61], v[64:65], v[70:71], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[42:43], v[44:45], v6
	v_cvt_i32_f64_e32 v6, v[58:59]
	v_ldexp_f64 v[48:49], v[54:55], v66
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[44:45], v[64:65], v[60:61], 1.0
	v_cndmask_b32_e64 v43, 0x7ff00000, v43, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[38:39], v[44:45], v6
	v_cndmask_b32_e64 v41, 0, v43, s1
	v_cndmask_b32_e32 v30, 0, v30, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[56:57]|
	v_cndmask_b32_e32 v40, 0, v42, vcc_lo
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[56:57]
	v_cndmask_b32_e64 v6, 0x7ff00000, v49, s3
	s_and_b32 s3, s4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[40:41], v[30:31], v[40:41]
	v_cmp_class_f64_e64 vcc_lo, v[40:41], 0x204
	v_cndmask_b32_e64 v37, 0, v6, s4
	v_cndmask_b32_e64 v36, 0, v48, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[32:33], v[36:37], v[32:33], v[36:37]
	v_cndmask_b32_e64 v35, 0, v35, s0
	v_cndmask_b32_e64 v34, 0, v34, s0
	s_and_b32 s0, s2, s1
	v_cndmask_b32_e64 v39, 0x7ff00000, v39, s1
	v_cndmask_b32_e64 v38, 0, v38, s0
	v_cmp_class_f64_e64 s0, v[36:37], 0x204
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[21:22]|
	v_dual_cndmask_b32 v31, v31, v41 :: v_dual_cndmask_b32 v30, v30, v40
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[19:20]|
	v_cndmask_b32_e64 v39, 0, v39, s2
	v_cmp_neq_f64_e64 s2, 0, v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], |v[30:31]|, s[74:75]
	v_fma_f64 v[34:35], v[38:39], v[34:35], v[38:39]
	v_cmp_class_f64_e64 s3, v[38:39], 0x204
	v_cndmask_b32_e64 v6, v33, v37, s0
	v_cndmask_b32_e64 v32, v32, v36, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[23:24]|
	s_delay_alu instid0(VALU_DEP_3)
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_cndmask_b32_e32 v37, 0, v30, vcc_lo
	v_cndmask_b32_e32 v30, 0x7ff00000, v31, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[19:20]
	v_cndmask_b32_e64 v31, v35, v39, s3
	v_cndmask_b32_e64 v6, 0x7ff00000, v6, s1
	s_and_b32 s1, s2, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v31, 0x7fffffff, v31
	v_cndmask_b32_e64 v35, 0x7ff00000, v31, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v31, 0, v6, s2
	v_cndmask_b32_e64 v6, v34, v38, s3
	v_cndmask_b32_e32 v33, 0x3eb0c6f7, v30, vcc_lo
	v_cndmask_b32_e64 v30, 0, v32, s1
	v_cmp_neq_f64_e64 s1, 0, v[23:24]
	v_cndmask_b32_e32 v32, 0xa0b5ed8d, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[32:33], v[30:31]
	s_and_b32 vcc_lo, s1, s0
	v_cndmask_b32_e64 v33, 0, v35, s1
	v_cndmask_b32_e32 v32, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[30:31], v[30:31], v[32:33]
	v_frexp_mant_f64_e32 v[32:33], v[30:31]
	v_cmp_eq_f64_e64 s3, 0, v[30:31]
	v_cmp_eq_f64_e64 s2, 0x7ff00000, v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[32:33]
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_ldexp_f64 v[32:33], v[32:33], v6
	v_frexp_exp_i32_f64_e32 v6, v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[32:33], 1.0
	v_add_f64 v[40:41], v[32:33], -1.0
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, 1.0, v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[36:37], v[34:35]
	v_add_f64 v[42:43], v[34:35], -1.0
	v_add_f64 v[32:33], v[32:33], -v[42:43]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[38:39], -v[34:35], v[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[38:39], v[36:37], v[36:37]
	v_fma_f64 v[38:39], -v[34:35], v[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[38:39], v[36:37], v[36:37]
	v_mul_f64 v[38:39], v[40:41], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[44:45], v[34:35], v[38:39]
	v_fma_f64 v[34:35], v[38:39], v[34:35], -v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[38:39], v[32:33], v[34:35]
	v_add_f64 v[34:35], v[44:45], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[42:43], v[40:41], -v[34:35]
	v_add_f64 v[44:45], v[34:35], -v[44:45]
	v_add_f64 v[40:41], v[40:41], -v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[44:45], -v[32:33]
	v_add_f64 v[34:35], v[40:41], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[32:33], v[34:35]
	v_add_f64 v[32:33], v[42:43], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[32:33], v[36:37], v[32:33]
	v_add_f64 v[34:35], v[38:39], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[34:35], -v[38:39]
	v_mul_f64 v[38:39], v[34:35], v[34:35]
	v_add_f64 v[32:33], v[32:33], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[34:35], v[34:35], -v[38:39]
	v_add_f64 v[40:41], v[32:33], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[34:35], v[40:41], v[36:37]
	v_add_f64 v[40:41], v[38:39], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[40:41], s[30:31], s[28:29]
	v_add_f64 v[38:39], v[40:41], -v[38:39]
	v_mul_f64 v[48:49], v[34:35], v[40:41]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[36:37], -v[38:39]
	v_fma_f64 v[50:51], v[40:41], v[34:35], -v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[36:37]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[40:41]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[44:45]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[44:45], v[40:41], v[42:43]
	v_fma_f64 v[38:39], v[40:41], v[42:43], -v[44:45]
	v_fma_f64 v[40:41], v[40:41], v[32:33], v[50:51]
	v_ldexp_f64 v[32:33], v[32:33], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[36:37], v[42:43], v[38:39]
	v_fma_f64 v[36:37], v[36:37], v[34:35], v[40:41]
	v_ldexp_f64 v[34:35], v[34:35], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[42:43], v[44:45], v[38:39]
	v_add_f64 v[44:45], v[42:43], -v[44:45]
	v_add_f64 v[46:47], v[42:43], s[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[38:39], -v[44:45]
	v_add_f64 v[44:45], v[46:47], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[38:39], s[48:49]
	v_add_f64 v[42:43], v[42:43], -v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[38:39], v[42:43]
	v_add_f64 v[42:43], v[48:49], v[36:37]
	v_add_f64 v[40:41], v[46:47], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[48:49], v[42:43], -v[48:49]
	v_add_f64 v[44:45], v[46:47], -v[40:41]
	v_mul_f64 v[46:47], v[42:43], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[36:37], -v[48:49]
	v_add_f64 v[38:39], v[38:39], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[42:43], v[40:41], -v[46:47]
	v_fma_f64 v[38:39], v[42:43], v[38:39], v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[36:37], v[40:41], v[38:39]
	v_cvt_f64_i32_e32 v[40:41], v6
	v_cndmask_b32_e32 v6, 0x3ff80000, v27, vcc_lo
	v_add_f64 v[38:39], v[46:47], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[38:39], -v[46:47]
	v_add_f64 v[44:45], v[34:35], v[38:39]
	v_mul_f64 v[46:47], v[40:41], s[24:25]
	v_add_f64 v[36:37], v[36:37], -v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[44:45], -v[34:35]
	v_fma_f64 v[42:43], v[40:41], s[24:25], -v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[32:33], v[36:37]
	v_add_f64 v[34:35], v[38:39], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[40:41], s[26:27], v[42:43]
	v_add_f64 v[32:33], v[32:33], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[46:47], v[36:37]
	v_add_f64 v[38:39], v[44:45], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[46:47], v[34:35], -v[46:47]
	v_add_f64 v[40:41], v[34:35], v[38:39]
	v_add_f64 v[44:45], v[38:39], -v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[36:37], -v[46:47]
	v_add_f64 v[42:43], v[40:41], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[32:33], -v[44:45]
	v_add_f64 v[48:49], v[40:41], -v[42:43]
	v_add_f64 v[38:39], v[38:39], -v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[36:37], v[32:33]
	v_add_f64 v[34:35], v[34:35], -v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[38:39], v[34:35]
	v_add_f64 v[38:39], v[42:43], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[42:43], v[34:35]
	v_add_f64 v[42:43], v[42:43], -v[38:39]
	v_add_f64 v[32:33], v[32:33], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[44:45], v[40:41], v[34:35]
	v_add_f64 v[36:37], v[36:37], -v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[44:45], -v[40:41]
	v_add_f64 v[32:33], v[32:33], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[34:35], -v[38:39]
	v_add_f64 v[32:33], v[32:33], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[44:45], v[32:33]
	v_add_f64 v[36:37], v[34:35], -v[44:45]
	v_mul_f64 v[38:39], v[5:6], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[32:33], -v[36:37]
	v_fma_f64 v[34:35], v[5:6], v[34:35], -v[38:39]
	v_cmp_class_f64_e64 vcc_lo, v[38:39], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[5:6], v[32:33], v[34:35]
	v_add_f64 v[34:35], v[38:39], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v37, v35, v39 :: v_dual_cndmask_b32 v36, v34, v38
	v_add_f64 v[34:35], v[34:35], -v[38:39]
	v_mul_f64 v[40:41], v[36:37], s[52:53]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[36:37]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[36:37]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[36:37]
	v_add_f64 v[32:33], v[32:33], -v[34:35]
	v_trunc_f64_e32 v[34:35], v[5:6]
	v_rndne_f64_e32 v[40:41], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v32, 0, v32 :: v_dual_cndmask_b32 v33, 0, v33
	s_and_b32 vcc_lo, s1, s0
	v_fma_f64 v[42:43], v[40:41], s[78:79], v[36:37]
	v_cvt_i32_f64_e32 v46, v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[40:41], s[80:81], v[42:43]
	v_fma_f64 v[44:45], v[42:43], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[58:59]
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[62:63]
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[66:67]
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[70:71]
	v_fma_f64 v[44:45], v[42:43], v[44:45], s[72:73]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[42:43], v[44:45], 1.0
	v_fma_f64 v[40:41], v[42:43], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[38:39], v[40:41], v46
	v_mul_f64 v[40:41], v[5:6], 0.5
	v_cndmask_b32_e64 v39, 0x7ff00000, v39, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f64_e32 v[36:37], v[40:41]
	v_cndmask_b32_e32 v38, 0, v38, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, v[34:35], v[5:6]
	v_mul_f64 v[34:35], s[88:89], s[76:77]
	v_cndmask_b32_e64 v39, 0, v39, s1
	v_cndmask_b32_e64 v6, 0x7ff00000, 0, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[38:39], v[32:33], v[38:39]
	v_cmp_class_f64_e64 s1, v[38:39], 0x204
	v_cmp_neq_f64_e64 s0, v[36:37], v[40:41]
	v_mul_f64 v[19:20], v[19:20], v[34:35]
	v_mul_f64 v[21:22], v[21:22], v[34:35]
	v_mul_f64 v[23:24], v[23:24], v[34:35]
	v_cndmask_b32_e64 v33, v33, v39, s1
	v_cndmask_b32_e64 v32, v32, v38, s1
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cndmask_b32_e32 v36, 0, v31, vcc_lo
	v_cndmask_b32_e32 v37, 0x3ff00000, v31, vcc_lo
	s_or_b32 vcc_lo, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v32, 0, vcc_lo
	v_bfi_b32 v6, 0x7fffffff, v6, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v33, 0x7fffffff, v33, v37
	v_cndmask_b32_e32 v6, v33, v6, vcc_lo
	v_cmp_o_f64_e32 vcc_lo, v[30:31], v[30:31]
	v_cndmask_b32_e32 v30, 0, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v31, 0x7ff80000, v6, vcc_lo
	v_div_scale_f64 v[32:33], null, v[30:31], v[30:31], v[19:20]
	v_div_scale_f64 v[34:35], null, v[30:31], v[30:31], v[21:22]
	v_div_scale_f64 v[36:37], null, v[30:31], v[30:31], v[23:24]
	v_div_scale_f64 v[50:51], vcc_lo, v[19:20], v[30:31], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[38:39], v[32:33]
	v_rcp_f64_e32 v[40:41], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[42:43], v[36:37]
	v_fma_f64 v[44:45], -v[32:33], v[38:39], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[46:47], -v[34:35], v[40:41], 1.0
	v_fma_f64 v[48:49], -v[36:37], v[42:43], 1.0
	v_fma_f64 v[38:39], v[38:39], v[44:45], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], v[40:41], v[46:47], v[40:41]
	v_fma_f64 v[42:43], v[42:43], v[48:49], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[46:47], -v[34:35], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], -v[36:37], v[42:43], 1.0
	v_fma_f64 v[38:39], v[38:39], v[44:45], v[38:39]
	v_div_scale_f64 v[44:45], s0, v[21:22], v[30:31], v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], v[40:41], v[46:47], v[40:41]
	v_div_scale_f64 v[46:47], s1, v[23:24], v[30:31], v[23:24]
	v_fma_f64 v[42:43], v[42:43], v[48:49], v[42:43]
	v_mul_f64 v[48:49], v[50:51], v[38:39]
	v_mul_f64 v[52:53], v[44:45], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[54:55], v[46:47], v[42:43]
	v_fma_f64 v[32:33], -v[32:33], v[48:49], v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], -v[34:35], v[52:53], v[44:45]
	v_fma_f64 v[36:37], -v[36:37], v[54:55], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[32:33], v[32:33], v[38:39], v[48:49]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[34:35], v[34:35], v[40:41], v[52:53]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[36:37], v[36:37], v[42:43], v[54:55]
	v_div_fixup_f64 v[19:20], v[32:33], v[30:31], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[21:22], v[34:35], v[30:31], v[21:22]
	v_div_fixup_f64 v[23:24], v[36:37], v[30:31], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[19:20]
	v_add_f64 v[17:18], v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], v[23:24]
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s87
	v_add_nc_u32_e32 v28, -1, v28
	v_add_nc_u32_e32 v29, -1, v29
	s_add_u32 s82, s82, 8
	s_addc_u32 s83, s83, 0
	s_add_i32 s86, s86, 8
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	s_cbranch_vccz .LBB0_5
.LBB0_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s84, s84, 1
	s_addk_i32 s85, 0xff00
	v_add_nc_u32_e32 v3, 0xffffff00, v3
	s_add_u32 s20, s20, 0x800
	s_addc_u32 s21, s21, 0
	s_cmp_eq_u32 s84, s33
	s_cbranch_scc0 .LBB0_3
.LBB0_9:                                ; %Flow144
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s14, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v2, vcc_lo
	v_mul_f64 v[9:10], s[22:23], 0.5
	global_load_b64 v[5:6], v[3:4], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], v[7:8], v[5:6]
	v_add_co_u32 v7, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v2, vcc_lo
	global_store_b64 v[3:4], v[5:6], off
	global_load_b64 v[3:4], v[7:8], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], v[9:10], v[17:18], v[3:4]
	global_store_b64 v[7:8], v[3:4], off
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[9:10], v[15:16], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5acceliPdS_S_S_S_S_S_d
		.amdhsa_group_segment_fixed_size 6144
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 88
		.amdhsa_next_free_sgpr 90
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5acceliPdS_S_S_S_S_S_d, .Lfunc_end0-_Z5acceliPdS_S_S_S_S_S_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7188
; NumSgprs: 92
; NumVgprs: 88
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 6144 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 92
; NumVGPRsForWavesPerEU: 88
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 6144
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5acceliPdS_S_S_S_S_S_d
    .private_segment_fixed_size: 0
    .sgpr_count:     92
    .sgpr_spill_count: 0
    .symbol:         _Z5acceliPdS_S_S_S_S_S_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     88
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
