/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/



#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <vector_types.h>
#include <device_launch_parameters.h>

#define N 20

/*
operaciones con matrices
*/

//GLOABL: funcion llamada desde el host y ejecutada en el device (kernel)

__global__ void suma(float *A, float *B, float *C)
{
	//indice de las columnas
	int columna = threadIdx.x;
	//indice de las filas
	int fila = threadIdx.y;
	//indice lineal
	int Id = columna + fila * blockDim.x;
	//sumamos cada elemento
	C[Id] = A[Id] + B[Id];
}


//Cada elemento de la matriz C se obtiene como la suma de los
//elementos de la matriz A ubicados en posiciones adyacentes

__global__ void add(float *A, float *C) 
{
	int columna = threadIdx.x;
	//indice de las filas
	int fila = threadIdx.y;
	//indice lineal
	int Id = columna + fila * blockDim.x;

	int id1 = (columna - 1) + fila * blockDim.x;
	int id2 = (columna + 1) + fila * blockDim.x;
	int id3 = columna + (fila - 1) * blockDim.x;
	int id4 = columna + (fila + 1) * blockDim.x;

	if ((fila > 0 && fila < N - 1) && (columna > 0 && columna < N - 1)) {

		C[Id] = A[id1] + A[id2] + A[id3] + A[id4];
	}
	else
	{
		C[Id] = A[Id];
	}
}


// funcion chequeo de errores

__host__ void check_CUDA_Error(const char *mensaje) 
{
	cudaError_t error;
	cudaDeviceSynchronize();
	error = cudaGetLastError();
	if (error != cudaSuccess) {
		printf("ERROR %d: %s (%s)\n", error, cudaGetErrorString(error), mensaje);
	}
}



int main(int argc, char** argv) 
{
	//declaracions
	float *hst_A, *hst_B, *hst_C;
	float *dev_A, *dev_B, *dev_C;
	int size = N * N * sizeof(float);

	//reserva de memoria en el host
	hst_A = (float*)malloc(size);
	hst_B = (float*)malloc(size);
	hst_C = (float*)malloc(size);

	//reserva de memoria en el device
	cudaMalloc((void**)&dev_A, size);
	check_CUDA_Error("Error malloc dev_A!");
	cudaMalloc((void**)&dev_B, size);
	check_CUDA_Error("Error malloc dev_B!");
	cudaMalloc((void**)&dev_C, size);
	check_CUDA_Error("Error malloc dev_C!");

	//inicializacion de los vectores

	for (int i = 0; i < N*N; i++) {

		hst_A[i] = (float)(rand() % 5);
		hst_B[i] = (float)(rand() % 5);
	}

	//enviar datos del hosto al device
	
	cudaMemcpy(dev_A, hst_A, size, cudaMemcpyHostToDevice);
	check_CUDA_Error("Error Memcpy hst_A To dev_A");
	cudaMemcpy(dev_B, hst_B, size, cudaMemcpyHostToDevice);
	check_CUDA_Error("Error Memcpy hst_B To dev_B");
	//cudaMemcpy(dev_C, hst_C, N*N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_C, hst_C, size, cudaMemcpyHostToDevice);
	check_CUDA_Error("Error Memcpy hst_C To dev_C");
	//dimenciones del kernel
	dim3 Nbloques(1);
	dim3 hilosB(N, N);

	//////MEDICION DE TIEMPO EN GPU///////////////
	// declaracion de eventos para medir el tiempo de ejecucion en la GPU
	cudaEvent_t start;
	cudaEvent_t stop;
	// creacion de eventos
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	// marca de inicio
	cudaEventRecord(start, 0);
	//llamada al kernel dibimensional de NxN hilos
	//suma <<<Nbloques, hilosB >>> (dev_A, dev_B, dev_C);
	add<<<Nbloques, hilosB >>>(dev_A, dev_C);
	check_CUDA_Error("Error kernel");
	
	// marca de final
	cudaEventRecord(stop, 0);
	// sincronizacion GPU-CPU
	cudaEventSynchronize(stop);
	// calculo del tiempo en milisegundos
	float elapsedTime;
	cudaEventElapsedTime(&elapsedTime, start, stop);
	////////MEDICION DE TIEMPO EN GPU/////////////////

	//recodiga de los datos
	cudaMemcpy(hst_C, dev_C, size, cudaMemcpyDeviceToHost);
	check_CUDA_Error("Error Memcpy dev_C To hst_C");
	//impresion del resultado
	
	printf("A:\n");
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++)
		{
			printf("%.2f\t", hst_A[j + i * N]);
		}
		printf("\n");
	}

	
	printf("B:\n");
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++)
		{
			printf("%.2f\t", hst_B[j + i * N]);
		}
		printf("\n");
	}
	
	printf("C:\n");
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++)
		{
			printf("%.2f\t", hst_C[j + i * N]);
		}
		printf("\n");
	}
	printf("\n\n");
	printf("> Tiempo de ejecucion: %f ms\n", elapsedTime);

	cudaFree(hst_A);
	cudaFree(hst_B);
	cudaFree(hst_C);
	free(hst_A);
	free(hst_B);
	free(hst_C);

	printf("\n pulsa INTRO parsa finalizar...");
	fflush(stdin);
	char tecla = getchar();

	return 0;
}


	.file	"tmpxft_003a16e8_00000000-6_ejemplo6_1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"ERROR %d: %s (%s)\n"
	.text
	.globl	_Z16check_CUDA_ErrorPKc
	.type	_Z16check_CUDA_ErrorPKc, @function
_Z16check_CUDA_ErrorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%r10
	.cfi_def_cfa_offset 32
	call	cudaDeviceSynchronize@PLT
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	movl	%eax, %ebx
	call	cudaGetErrorString@PLT
	popq	%r9
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movq	%rbp, %r8
	movl	%ebx, %edx
	movq	%rax, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L2:
	.cfi_restore_state
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z16check_CUDA_ErrorPKc, .-_Z16check_CUDA_ErrorPKc
	.globl	_Z27__device_stub__Z4sumaPfS_S_PfS_S_
	.type	_Z27__device_stub__Z4sumaPfS_S_PfS_S_, @function
_Z27__device_stub__Z4sumaPfS_S_PfS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4sumaPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z27__device_stub__Z4sumaPfS_S_PfS_S_, .-_Z27__device_stub__Z4sumaPfS_S_PfS_S_
	.globl	_Z4sumaPfS_S_
	.type	_Z4sumaPfS_S_, @function
_Z4sumaPfS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z4sumaPfS_S_PfS_S_
	.cfi_endproc
.LFE2054:
	.size	_Z4sumaPfS_S_, .-_Z4sumaPfS_S_
	.globl	_Z24__device_stub__Z3addPfS_PfS_
	.type	_Z24__device_stub__Z3addPfS_PfS_, @function
_Z24__device_stub__Z3addPfS_PfS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z3addPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L11:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z24__device_stub__Z3addPfS_PfS_, .-_Z24__device_stub__Z3addPfS_PfS_
	.globl	_Z3addPfS_
	.type	_Z3addPfS_, @function
_Z3addPfS_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z3addPfS_PfS_
	.cfi_endproc
.LFE2056:
	.size	_Z3addPfS_, .-_Z3addPfS_
	.section	.rodata.str1.1
.LC1:
	.string	"Error malloc dev_A!"
.LC2:
	.string	"Error malloc dev_B!"
.LC3:
	.string	"Error malloc dev_C!"
.LC4:
	.string	"Error Memcpy hst_A To dev_A"
.LC5:
	.string	"Error Memcpy hst_B To dev_B"
.LC6:
	.string	"Error Memcpy hst_C To dev_C"
.LC7:
	.string	"Error kernel"
.LC8:
	.string	"Error Memcpy dev_C To hst_C"
.LC9:
	.string	"A:\n"
.LC10:
	.string	"%.2f\t"
.LC11:
	.string	"\n"
.LC12:
	.string	"B:\n"
.LC13:
	.string	"C:\n"
.LC14:
	.string	"\n\n"
.LC15:
	.string	"> Tiempo de ejecucion: %f ms\n"
.LC16:
	.string	"\n pulsa INTRO parsa finalizar..."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1600, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$5, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1600, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$1600, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$1600, %esi
	leaq	8(%rsp), %rdi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	.LC1(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
	movl	$1600, %esi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC2(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
	leaq	24(%rsp), %rdi
	movl	$1600, %esi
	call	cudaMalloc@PLT
	leaq	.LC3(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
.L17:
	call	rand@PLT
	cltd
	idivl	%r14d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r12,%r13)
	call	rand@PLT
	cltd
	idivl	%r14d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, 0(%rbp,%r13)
	addq	$4, %r13
	cmpq	$1600, %r13
	jne	.L17
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$1600, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1600, %edx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1600, %edx
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
	leaq	32(%rsp), %rdi
	movabsq	$4294967297, %rax
	movl	$1, 56(%rsp)
	movq	%rax, 48(%rsp)
	movabsq	$85899345940, %rax
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	68(%rsp), %ecx
	movl	56(%rsp), %esi
	xorl	%r9d, %r9d
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z24__device_stub__Z3addPfS_PfS_
.L18:
	leaq	.LC7(%rip), %rdi
	xorl	%r13d, %r13d
	call	_Z16check_CUDA_ErrorPKc
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1600, %edx
	call	cudaMemcpy@PLT
	leaq	.LC8(%rip), %rdi
	call	_Z16check_CUDA_ErrorPKc
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	imulq	$80, %r13, %r14
	xorl	%r15d, %r15d
	addq	%r12, %r14
.L20:
	cvtss2sd	(%r14,%r15,4), %xmm0
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r15
	cmpq	$20, %r15
	jne	.L20
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$20, %r13
	jne	.L19
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
.L22:
	imulq	$80, %r13, %r15
	xorl	%r14d, %r14d
	addq	%rbp, %r15
.L23:
	cvtss2sd	(%r15,%r14,4), %xmm0
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r14
	cmpq	$20, %r14
	jne	.L23
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$20, %r13
	jne	.L22
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
.L25:
	imulq	$80, %r13, %r15
	xorl	%r14d, %r14d
	addq	%rbx, %r15
.L26:
	cvtss2sd	(%r15,%r14,4), %xmm0
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r14
	cmpq	$20, %r14
	jne	.L26
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$20, %r13
	jne	.L25
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%r12, %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	stdin(%rip), %rdi
	call	fflush@PLT
	call	getchar@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z3addPfS_"
.LC18:
	.string	"_Z4sumaPfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z3addPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4sumaPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/



#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/hip_vector_types.h>


#define N 20

/*
operaciones con matrices
*/

//GLOABL: funcion llamada desde el host y ejecutada en el device (kernel)

__global__ void suma(float *A, float *B, float *C)
{
	//indice de las columnas
	int columna = threadIdx.x;
	//indice de las filas
	int fila = threadIdx.y;
	//indice lineal
	int Id = columna + fila * blockDim.x;
	//sumamos cada elemento
	C[Id] = A[Id] + B[Id];
}


//Cada elemento de la matriz C se obtiene como la suma de los
//elementos de la matriz A ubicados en posiciones adyacentes

__global__ void add(float *A, float *C) 
{
	int columna = threadIdx.x;
	//indice de las filas
	int fila = threadIdx.y;
	//indice lineal
	int Id = columna + fila * blockDim.x;

	int id1 = (columna - 1) + fila * blockDim.x;
	int id2 = (columna + 1) + fila * blockDim.x;
	int id3 = columna + (fila - 1) * blockDim.x;
	int id4 = columna + (fila + 1) * blockDim.x;

	if ((fila > 0 && fila < N - 1) && (columna > 0 && columna < N - 1)) {

		C[Id] = A[id1] + A[id2] + A[id3] + A[id4];
	}
	else
	{
		C[Id] = A[Id];
	}
}


// funcion chequeo de errores

__host__ void check_CUDA_Error(const char *mensaje) 
{
	hipError_t error;
	hipDeviceSynchronize();
	error = hipGetLastError();
	if (error != hipSuccess) {
		printf("ERROR %d: %s (%s)\n", error, hipGetErrorString(error), mensaje);
	}
}



int main(int argc, char** argv) 
{
	//declaracions
	float *hst_A, *hst_B, *hst_C;
	float *dev_A, *dev_B, *dev_C;
	int size = N * N * sizeof(float);

	//reserva de memoria en el host
	hst_A = (float*)malloc(size);
	hst_B = (float*)malloc(size);
	hst_C = (float*)malloc(size);

	//reserva de memoria en el device
	hipMalloc((void**)&dev_A, size);
	check_CUDA_Error("Error malloc dev_A!");
	hipMalloc((void**)&dev_B, size);
	check_CUDA_Error("Error malloc dev_B!");
	hipMalloc((void**)&dev_C, size);
	check_CUDA_Error("Error malloc dev_C!");

	//inicializacion de los vectores

	for (int i = 0; i < N*N; i++) {

		hst_A[i] = (float)(rand() % 5);
		hst_B[i] = (float)(rand() % 5);
	}

	//enviar datos del hosto al device
	
	hipMemcpy(dev_A, hst_A, size, hipMemcpyHostToDevice);
	check_CUDA_Error("Error Memcpy hst_A To dev_A");
	hipMemcpy(dev_B, hst_B, size, hipMemcpyHostToDevice);
	check_CUDA_Error("Error Memcpy hst_B To dev_B");
	//cudaMemcpy(dev_C, hst_C, N*N * sizeof(float), cudaMemcpyHostToDevice);
	hipMemcpy(dev_C, hst_C, size, hipMemcpyHostToDevice);
	check_CUDA_Error("Error Memcpy hst_C To dev_C");
	//dimenciones del kernel
	dim3 Nbloques(1);
	dim3 hilosB(N, N);

	//////MEDICION DE TIEMPO EN GPU///////////////
	// declaracion de eventos para medir el tiempo de ejecucion en la GPU
	hipEvent_t start;
	hipEvent_t stop;
	// creacion de eventos
	hipEventCreate(&start);
	hipEventCreate(&stop);
	// marca de inicio
	hipEventRecord(start, 0);
	//llamada al kernel dibimensional de NxN hilos
	//suma <<<Nbloques, hilosB >>> (dev_A, dev_B, dev_C);
	add<<<Nbloques, hilosB >>>(dev_A, dev_C);
	check_CUDA_Error("Error kernel");
	
	// marca de final
	hipEventRecord(stop, 0);
	// sincronizacion GPU-CPU
	hipEventSynchronize(stop);
	// calculo del tiempo en milisegundos
	float elapsedTime;
	hipEventElapsedTime(&elapsedTime, start, stop);
	////////MEDICION DE TIEMPO EN GPU/////////////////

	//recodiga de los datos
	hipMemcpy(hst_C, dev_C, size, hipMemcpyDeviceToHost);
	check_CUDA_Error("Error Memcpy dev_C To hst_C");
	//impresion del resultado
	
	printf("A:\n");
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++)
		{
			printf("%.2f\t", hst_A[j + i * N]);
		}
		printf("\n");
	}

	
	printf("B:\n");
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++)
		{
			printf("%.2f\t", hst_B[j + i * N]);
		}
		printf("\n");
	}
	
	printf("C:\n");
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++)
		{
			printf("%.2f\t", hst_C[j + i * N]);
		}
		printf("\n");
	}
	printf("\n\n");
	printf("> Tiempo de ejecucion: %f ms\n", elapsedTime);

	hipFree(hst_A);
	hipFree(hst_B);
	hipFree(hst_C);
	free(hst_A);
	free(hst_B);
	free(hst_C);

	printf("\n pulsa INTRO parsa finalizar...");
	fflush(stdin);
	char tecla = getchar();

	return 0;
}


	.text
	.file	"ejemplo6_1.hip"
	.globl	_Z19__device_stub__sumaPfS_S_   # -- Begin function _Z19__device_stub__sumaPfS_S_
	.type	_Z19__device_stub__sumaPfS_S_,@function
_Z19__device_stub__sumaPfS_S_:          # @_Z19__device_stub__sumaPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4sumaPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__sumaPfS_S_, .Lfunc_end0-_Z19__device_stub__sumaPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__addPfS_      # -- Begin function _Z18__device_stub__addPfS_
	.type	_Z18__device_stub__addPfS_,@function
_Z18__device_stub__addPfS_:             # @_Z18__device_stub__addPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__addPfS_, .Lfunc_end1-_Z18__device_stub__addPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z16check_CUDA_ErrorPKc         # -- Begin function _Z16check_CUDA_ErrorPKc
	.type	_Z16check_CUDA_ErrorPKc,@function
_Z16check_CUDA_ErrorPKc:                # @_Z16check_CUDA_ErrorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	callq	hipDeviceSynchronize
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_1
# %bb.2:
	movl	%eax, %ebp
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movl	%ebp, %esi
	movq	%rax, %rdx
	movq	%rbx, %rcx
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB2_1:
	.cfi_def_cfa_offset 32
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z16check_CUDA_ErrorPKc, .Lfunc_end2-_Z16check_CUDA_ErrorPKc
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1600, %edi                     # imm = 0x640
	callq	malloc
	movq	%rax, %rbx
	movl	$1600, %edi                     # imm = 0x640
	callq	malloc
	movq	%rax, %r14
	movl	$1600, %edi                     # imm = 0x640
	callq	malloc
	movq	%rax, %r15
	leaq	32(%rsp), %rdi
	movl	$1600, %esi                     # imm = 0x640
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z16check_CUDA_ErrorPKc
	leaq	48(%rsp), %rdi
	movl	$1600, %esi                     # imm = 0x640
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z16check_CUDA_ErrorPKc
	leaq	16(%rsp), %rdi
	movl	$1600, %esi                     # imm = 0x640
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z16check_CUDA_ErrorPKc
	xorl	%r12d, %r12d
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbx,%r12,4)
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%r12
	cmpq	$400, %r12                      # imm = 0x190
	jne	.LBB3_1
# %bb.2:
	movq	32(%rsp), %rdi
	movl	$1600, %edx                     # imm = 0x640
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.4, %edi
	callq	_Z16check_CUDA_ErrorPKc
	movq	48(%rsp), %rdi
	movl	$1600, %edx                     # imm = 0x640
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %edi
	callq	_Z16check_CUDA_ErrorPKc
	movq	16(%rsp), %rdi
	movl	$1600, %edx                     # imm = 0x640
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.6, %edi
	callq	_Z16check_CUDA_ErrorPKc
	leaq	40(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$85899345940, %rdx              # imm = 0x1400000014
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z18__device_stub__addPfS_
.LBB3_4:
	movl	$.L.str.7, %edi
	callq	_Z16check_CUDA_ErrorPKc
	movq	8(%rsp), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movl	$1600, %edx                     # imm = 0x640
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %edi
	callq	_Z16check_CUDA_ErrorPKc
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	%rbx, %r13
.LBB3_5:                                # %.preheader67
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
	xorl	%ebp, %ebp
.LBB3_6:                                #   Parent Loop BB3_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%rbp,4), %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	incq	%rbp
	cmpq	$20, %rbp
	jne	.LBB3_6
# %bb.7:                                #   in Loop: Header=BB3_5 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r12
	addq	$80, %r13
	cmpq	$20, %r12
	jne	.LBB3_5
# %bb.8:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%r12d, %r12d
	movq	%r14, %r13
.LBB3_9:                                # %.preheader66
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_10 Depth 2
	xorl	%ebp, %ebp
.LBB3_10:                               #   Parent Loop BB3_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%rbp,4), %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	incq	%rbp
	cmpq	$20, %rbp
	jne	.LBB3_10
# %bb.11:                               #   in Loop: Header=BB3_9 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r12
	addq	$80, %r13
	cmpq	$20, %r12
	jne	.LBB3_9
# %bb.12:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%r12d, %r12d
	movq	%r15, %r13
.LBB3_13:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_14 Depth 2
	xorl	%ebp, %ebp
.LBB3_14:                               #   Parent Loop BB3_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%rbp,4), %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	incq	%rbp
	cmpq	$20, %rbp
	jne	.LBB3_14
# %bb.15:                               #   in Loop: Header=BB3_13 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r12
	addq	$80, %r13
	cmpq	$20, %r12
	jne	.LBB3_13
# %bb.16:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	28(%rsp), %xmm0
	movl	$.L.str.15, %edi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	hipFree
	movq	%r15, %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movl	$.L.str.16, %edi
	xorl	%eax, %eax
	callq	printf
	movq	stdin(%rip), %rdi
	callq	fflush
	callq	getchar
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4sumaPfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addPfS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4sumaPfS_S_,@object           # @_Z4sumaPfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z4sumaPfS_S_
	.p2align	3, 0x0
_Z4sumaPfS_S_:
	.quad	_Z19__device_stub__sumaPfS_S_
	.size	_Z4sumaPfS_S_, 8

	.type	_Z3addPfS_,@object              # @_Z3addPfS_
	.globl	_Z3addPfS_
	.p2align	3, 0x0
_Z3addPfS_:
	.quad	_Z18__device_stub__addPfS_
	.size	_Z3addPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"ERROR %d: %s (%s)\n"
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Error malloc dev_A!"
	.size	.L.str.1, 20

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error malloc dev_B!"
	.size	.L.str.2, 20

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Error malloc dev_C!"
	.size	.L.str.3, 20

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Error Memcpy hst_A To dev_A"
	.size	.L.str.4, 28

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Error Memcpy hst_B To dev_B"
	.size	.L.str.5, 28

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Error Memcpy hst_C To dev_C"
	.size	.L.str.6, 28

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Error kernel"
	.size	.L.str.7, 13

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Error Memcpy dev_C To hst_C"
	.size	.L.str.8, 28

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"%.2f\t"
	.size	.L.str.10, 6

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"> Tiempo de ejecucion: %f ms\n"
	.size	.L.str.15, 30

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"\n pulsa INTRO parsa finalizar..."
	.size	.L.str.16, 33

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4sumaPfS_S_"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z3addPfS_"
	.size	.L__unnamed_2, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"A:"
	.size	.Lstr, 3

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"B:"
	.size	.Lstr.1, 3

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"C:"
	.size	.Lstr.2, 3

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\n"
	.size	.Lstr.3, 2

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__sumaPfS_S_
	.addrsig_sym _Z18__device_stub__addPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4sumaPfS_S_
	.addrsig_sym _Z3addPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4sumaPfS_S_           ; -- Begin function _Z4sumaPfS_S_
	.globl	_Z4sumaPfS_S_
	.p2align	8
	.type	_Z4sumaPfS_S_,@function
_Z4sumaPfS_S_:                          ; @_Z4sumaPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v1, s2, v1
	v_add_lshl_u32 v0, v1, v0, 2
	s_clause 0x1
	global_load_b32 v1, v0, s[4:5]
	global_load_b32 v2, v0, s[6:7]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v1, v2
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4sumaPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4sumaPfS_S_, .Lfunc_end0-_Z4sumaPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 120
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3addPfS_              ; -- Begin function _Z3addPfS_
	.globl	_Z3addPfS_
	.p2align	8
	.type	_Z3addPfS_,@function
_Z3addPfS_:                             ; @_Z3addPfS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x1c
	v_bfe_u32 v6, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_load_b128 s[0:3], s[0:1], 0x0
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, -1, v6
	v_add_nc_u32_e32 v5, -1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_max_u32_e32 v1, v0, v5
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u32_u24 v0, v6, s5, v2
	v_lshlrev_b32_e32 v3, 2, v0
	v_cmpx_lt_u32_e32 17, v1
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB1_2
; %bb.1:
	global_load_b32 v4, v3, s[0:1]
	v_mov_b32_e32 v1, 0
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr3
.LBB1_2:                                ; %Flow
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_mul_u32_u24_e32 v1, s5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v9, s5, v1
	s_lshl_b32 s5, s5, 1
	v_dual_mov_b32 v8, v6 :: v_dual_add_nc_u32 v5, v1, v5
	global_load_b32 v1, v3, s[0:1] offset:4
	s_waitcnt vmcnt(1)
	v_subrev_nc_u32_e32 v4, s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v4, v2
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_lshl_u32 v2, v9, v2, 2
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	s_clause 0x2
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[7:8], off
	global_load_b32 v2, v2, s[0:1]
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v1, v3, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v1, v4
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, v6 :: v_dual_add_f32 v4, v3, v2
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 6
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z3addPfS_, .Lfunc_end1-_Z3addPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 8
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4sumaPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z4sumaPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3addPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z3addPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
