#include <stdio.h>
#define ll long long int

const ll m = 0x5DEECE66Dll;
const ll mask = (1ll << 48) - 1;

#define advance1(s) s = (s * m + 11ll) & mask
#define advance2(s)  \
    advance1(s); \
    advance1(s);
#define getIntBounded(x, s, n)              \
    if ((n & (-n)) == n)                    \
    {                                       \
        advance1(s);                        \
        x = (int)((n * (s >> 17)) >> 31);   \
    }                                       \
    else                                    \
    {                                       \
        do                                  \
        {                                   \
            advance1(s);                    \
            bits = s >> 17;                 \
            val = bits % n;                 \
        } while (bits - val + (n - 1) < 0); \
        x = val;                            \
    }
#define nextFloat(x, s) \
    x = ((advance1(s)) >> 32) / 1.6777216E7F;
#define swap(x, y) \
    x += y;        \
    y = x;         \
    x -= y;

__device__
void check_seed(ll seed)
{
    ll color, stem_height;
    ll bits, val;
    float temp;
    ll tempi;
    getIntBounded(color, seed, 5);
    if (color != 0)
    {
        return;
    }
    getIntBounded(stem_height, seed, 5);
    if (stem_height != 0)
    {
        return;
    }
    nextFloat(temp, seed);
    if (temp < 0.25f)
    {
        return;
    }
    nextFloat(temp, seed);
    if (temp < 0.05f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
        getIntBounded(tempi, seed, 5); // unknown, dynamic skip

    // 2 sides:
    getIntBounded(tempi, seed, 3);
    if (tempi != 0)
    {
        return;
    }

    int a[] = {0, 1, 2, 3};
    /*
    4, 3, 2 as x:
     swap(a[x-1], a[nextInt(x)])
    */
    getIntBounded(tempi, seed, 4);
    swap(a[3], a[tempi]);
    getIntBounded(tempi, seed, 3);
    swap(a[2], a[tempi]);
    getIntBounded(tempi, seed, 2);
    swap(a[1], a[tempi]);
    // 2 = south, 3 = west
    if (a[0] + a[1] != 5)
    {
        return;
    }
    int i;
    for (i = 0; i < 2; i++)
    {
        // height
        getIntBounded(tempi, seed, 5);
        if (tempi != 1)
            return;

        if (a[i] == 2)
        {
            nextFloat(temp, seed);
            if (temp < 0.25f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.05f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            advance2(seed); // skip sea pickles and corals which would get overriten

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }

            getIntBounded(tempi, seed, 5);
            if (tempi != 3)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            // coral on top:
            nextFloat(temp, seed);
            if (temp >= 0.25f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 4) {
                return;
            }
            

            // wall corals:
            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 4)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }


            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip
        }
        else if (a[i] == 3)
        {
            nextFloat(temp, seed);
            if (temp < 0.25f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.05f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }

            getIntBounded(tempi, seed, 5);
            if (tempi != 1)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2) getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            advance2(seed); // skip sea pickles and corals which would get overriten

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            // coral on top:
            nextFloat(temp, seed);
            if (temp >= 0.25f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 1) {
                return;
            }
            

            // wall corals:
            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 0)
            {
                return;
            }


            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }



            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip
        }
    }

    printf("%lld\n", seed);
}

__global__
void find() {
    ll i = 0;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (i = index; i < (1ll << 36); i += stride) {
        check_seed(i);
    }
}

int main(void) {
    printf("Begin\n");
    int blockSize = 256;
    // ll N = 1ll << ;
    // int numBlocks = (N + blockSize - 1) / blockSize;
    int numBlocks = 32768;
    find<<<numBlocks, blockSize>>>();
    cudaDeviceSynchronize();
    printf("End\n");
}

	.file	"tmpxft_0039566c_00000000-6_check.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10check_seedx
	.type	_Z10check_seedx, @function
_Z10check_seedx:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10check_seedx, .-_Z10check_seedx
	.globl	_Z22__device_stub__Z4findvv
	.type	_Z22__device_stub__Z4findvv, @function
_Z22__device_stub__Z4findvv:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z4findv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L4:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z22__device_stub__Z4findvv, .-_Z22__device_stub__Z4findvv
	.globl	_Z4findv
	.type	_Z4findv, @function
_Z4findv:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z22__device_stub__Z4findvv
	.cfi_endproc
.LFE2054:
	.size	_Z4findv, .-_Z4findv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Begin\n"
.LC1:
	.string	"End\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$131073, %edi
	salq	$8, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$15, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	call	_Z22__device_stub__Z4findvv
.L11:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z4findv"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4findv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#define ll long long int

const ll m = 0x5DEECE66Dll;
const ll mask = (1ll << 48) - 1;

#define advance1(s) s = (s * m + 11ll) & mask
#define advance2(s)  \
    advance1(s); \
    advance1(s);
#define getIntBounded(x, s, n)              \
    if ((n & (-n)) == n)                    \
    {                                       \
        advance1(s);                        \
        x = (int)((n * (s >> 17)) >> 31);   \
    }                                       \
    else                                    \
    {                                       \
        do                                  \
        {                                   \
            advance1(s);                    \
            bits = s >> 17;                 \
            val = bits % n;                 \
        } while (bits - val + (n - 1) < 0); \
        x = val;                            \
    }
#define nextFloat(x, s) \
    x = ((advance1(s)) >> 32) / 1.6777216E7F;
#define swap(x, y) \
    x += y;        \
    y = x;         \
    x -= y;

__device__
void check_seed(ll seed)
{
    ll color, stem_height;
    ll bits, val;
    float temp;
    ll tempi;
    getIntBounded(color, seed, 5);
    if (color != 0)
    {
        return;
    }
    getIntBounded(stem_height, seed, 5);
    if (stem_height != 0)
    {
        return;
    }
    nextFloat(temp, seed);
    if (temp < 0.25f)
    {
        return;
    }
    nextFloat(temp, seed);
    if (temp < 0.05f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
    {
        return;
    }

    nextFloat(temp, seed);
    if (temp < 0.2f)
        getIntBounded(tempi, seed, 5); // unknown, dynamic skip

    // 2 sides:
    getIntBounded(tempi, seed, 3);
    if (tempi != 0)
    {
        return;
    }

    int a[] = {0, 1, 2, 3};
    /*
    4, 3, 2 as x:
     swap(a[x-1], a[nextInt(x)])
    */
    getIntBounded(tempi, seed, 4);
    swap(a[3], a[tempi]);
    getIntBounded(tempi, seed, 3);
    swap(a[2], a[tempi]);
    getIntBounded(tempi, seed, 2);
    swap(a[1], a[tempi]);
    // 2 = south, 3 = west
    if (a[0] + a[1] != 5)
    {
        return;
    }
    int i;
    for (i = 0; i < 2; i++)
    {
        // height
        getIntBounded(tempi, seed, 5);
        if (tempi != 1)
            return;

        if (a[i] == 2)
        {
            nextFloat(temp, seed);
            if (temp < 0.25f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.05f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            advance2(seed); // skip sea pickles and corals which would get overriten

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }

            getIntBounded(tempi, seed, 5);
            if (tempi != 3)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            // coral on top:
            nextFloat(temp, seed);
            if (temp >= 0.25f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 4) {
                return;
            }
            

            // wall corals:
            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 4)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }


            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip
        }
        else if (a[i] == 3)
        {
            nextFloat(temp, seed);
            if (temp < 0.25f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.05f)
                return;
            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }

            getIntBounded(tempi, seed, 5);
            if (tempi != 1)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2) getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            advance2(seed); // skip sea pickles and corals which would get overriten

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip

            // coral on top:
            nextFloat(temp, seed);
            if (temp >= 0.25f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 1) {
                return;
            }
            

            // wall corals:
            nextFloat(temp, seed);
            if (temp >= 0.2f)
            {
                return;
            }
            getIntBounded(tempi, seed, 5);
            if (tempi != 0)
            {
                return;
            }


            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }

            nextFloat(temp, seed);
            if (temp < 0.2f)
            {
                return;
            }



            nextFloat(temp, seed);
            if (temp < 0.2f)
                getIntBounded(tempi, seed, 5); // unknown, dynamic skip
        }
    }

    printf("%lld\n", seed);
}

__global__
void find() {
    ll i = 0;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (i = index; i < (1ll << 36); i += stride) {
        check_seed(i);
    }
}

int main(void) {
    printf("Begin\n");
    int blockSize = 256;
    // ll N = 1ll << ;
    // int numBlocks = (N + blockSize - 1) / blockSize;
    int numBlocks = 32768;
    find<<<numBlocks, blockSize>>>();
    hipDeviceSynchronize();
    printf("End\n");
}

	.text
	.file	"check.hip"
	.globl	_Z19__device_stub__findv        # -- Begin function _Z19__device_stub__findv
	.type	_Z19__device_stub__findv,@function
_Z19__device_stub__findv:               # @_Z19__device_stub__findv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z4findv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__findv, .Lfunc_end0-_Z19__device_stub__findv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$.Lstr, %edi
	callq	puts@PLT
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	leaq	32512(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	callq	_Z19__device_stub__findv
.LBB1_2:
	callq	hipDeviceSynchronize
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4findv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4findv,@object                # @_Z4findv
	.section	.rodata,"a",@progbits
	.globl	_Z4findv
	.p2align	3, 0x0
_Z4findv:
	.quad	_Z19__device_stub__findv
	.size	_Z4findv, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4findv"
	.size	.L__unnamed_1, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Begin"
	.size	.Lstr, 6

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"End"
	.size	.Lstr.1, 4

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__findv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4findv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v8, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[0:1], 0
	s_cbranch_scc0 .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_and_b32_e32 v0, -3, v8
	v_dual_mov_b32 v32, s1 :: v_dual_mov_b32 v11, 2
	v_dual_mov_b32 v31, s0 :: v_dual_mov_b32 v12, 1
	v_mov_b32_e32 v5, v1
	v_dual_mov_b32 v30, 0 :: v_dual_and_b32 v35, 2, v8
	v_mbcnt_lo_u32_b32 v36, -1, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s11, 0
	s_mov_b32 s10, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[2:3]
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v34, 0, v3 :: v_dual_cndmask_b32 v33, 56, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v33
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v33
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[9:10], 3, v[33:34]
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v13, v31
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v14, v32
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v[13:14], off
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v6, v15, v6
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow172
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow174
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow176
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v9, v31
	v_mov_b32_e32 v10, v32
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[6:7], v[31:32], off
	v_add_co_u32 v9, vcc_lo, v31, 8
	v_add_nc_u32_e32 v0, -8, v33
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v32, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v15, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v15, v[15:16], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v16, s11 :: v_dual_and_b32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v14, v16, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v15, v13
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow167
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_15:                               ; %Flow169
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB0_16:                               ; %Flow171
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[13:14], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v17, -8, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	global_load_u8 v0, v[18:19], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow162
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_23:                               ; %Flow164
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB0_24:                               ; %Flow166
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v0, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[15:16], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v0, -8, v17
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v19, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v19, v[19:20], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v20, s11 :: v_dual_and_b32 v19, 0xffff, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v19, v17
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow157
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_31:                               ; %Flow159
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB0_32:                               ; %Flow161
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[17:18], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v21, -8, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	global_load_u8 v0, v[22:23], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow152
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_39:                               ; %Flow154
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB0_40:                               ; %Flow156
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v0, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[19:20], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v0, -8, v21
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v23, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v23, v[23:24], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v24, s11 :: v_dual_and_b32 v23, 0xffff, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], s0, v[23:24]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v22, v24, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v23, v21
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow147
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_47:                               ; %Flow149
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB0_48:                               ; %Flow151
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[21:22], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v25, -8, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v[9:10], off
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v26, 0xffff, v0
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow142
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow144
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_56:                               ; %Flow146
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[23:24], v[9:10], off
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v36
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v10, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v10, v0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v0, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[37:38], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v0, 24, v[37:38]
	v_and_b32_e32 v37, v26, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v10
	v_mad_u64_u32 v[25:26], null, v37, 24, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow139
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow141
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[37:38], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v37
	v_readfirstlane_b32 s7, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s13, s6, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s16, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v37, vcc_lo, v25, s13
	v_add_co_ci_u32_e32 v38, vcc_lo, s16, v26, vcc_lo
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[37:38], v[9:12], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_cmp_lt_u64_e32 vcc_lo, 56, v[2:3]
	v_or_b32_e32 v0, 0, v5
	v_or_b32_e32 v9, v4, v35
	v_lshl_add_u32 v10, v33, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v0, v5 :: v_dual_cndmask_b32 v0, v9, v4
	v_and_b32_e32 v4, 0x1e0, v10
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	v_and_or_b32 v4, 0xffffff1f, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[4:7], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[4:5], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v4
	v_readfirstlane_b32 s15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[4:5]
	s_mul_i32 s7, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[17:18]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s14, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
	s_sleep 1
	global_store_b64 v[13:14], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v30, v[4:7], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow137
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[4:5], v30, s[2:3] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[29:30], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v29, v[4:5], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow138
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s12, s12, s1
	v_add_co_u32 v0, vcc_lo, v25, s13
	v_add_co_ci_u32_e32 v5, vcc_lo, s12, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v0, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow132
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[4:7], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[6:7], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v0
	v_and_b32_e32 v0, v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v13, v6
	v_mul_hi_u32 v7, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v15, v6
	v_mov_b32_e32 v15, v9
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v16, v0, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v2, vcc_lo, v2, v33
	v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v34, vcc_lo
	v_add_co_u32 v31, s0, v31, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v32, s0, v32, v34, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow177
	s_or_b32 exec_lo, exec_lo, s10
	s_mov_b32 s0, 0
	s_branch .LBB0_88
.LBB0_87:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_88:                               ; %Flow192
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_117
; %bb.89:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_95
; %bb.90:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[9:10], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[5:6]
	s_cbranch_execz .LBB0_94
; %bb.91:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_92:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v3, v5
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v3, 24, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v10 :: v_dual_and_b32 v4, v4, v6
	v_mad_u64_u32 v[10:11], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[5:6]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_92
; %bb.93:                               ; %Flow189
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %Flow191
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_95:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_97
; %bb.96:
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v14, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v3
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_97:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[9:10], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v9
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_105
; %bb.98:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_101
; %bb.99:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_100:                              ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_100
.LBB0_101:                              ; %Flow187
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_103
; %bb.102:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_103:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_105
; %bb.104:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_105:                              ; %Flow188
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_106:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_106 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_108:                              ;   in Loop: Header=BB0_106 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_110
; %bb.109:                              ;   in Loop: Header=BB0_106 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_111
.LBB0_110:                              ;   in Loop: Header=BB0_106 Depth=1
	s_mov_b32 s1, -1
.LBB0_111:                              ; %Flow182
                                        ;   in Loop: Header=BB0_106 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_106
; %bb.112:
	global_load_b128 v[4:7], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_116
; %bb.113:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[2:3], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v12 :: v_dual_cndmask_b32 v0, v0, v11
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v2
	v_mov_b32_e32 v2, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v3, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_116
; %bb.114:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_115:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[2:3]
	v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_115
.LBB0_116:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_117:                              ; %.loopexit33
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 4464
; NumSgprs: 34
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z4findv                ; -- Begin function _Z4findv
	.globl	_Z4findv
	.p2align	8
	.type	_Z4findv,@function
_Z4findv:                               ; @_Z4findv
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0xc
	s_load_b32 s3, s[0:1], 0x0
	s_mov_b64 s[18:19], s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_cls_i32 s4, 0
	v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v48, 2
	v_mbcnt_lo_u32_b32 v52, -1, 0
	v_mov_b32_e32 v49, 1
	v_mov_b32_e32 v39, 33
	s_mov_b32 s24, -1
	s_mov_b32 s26, 0x9999999a
	s_mov_b32 s28, 0x544e593d
	s_mov_b32 s20, 0
	s_mov_b32 s25, 15
	s_mov_b32 s27, 0x3fc99999
	s_movk_i32 s29, 0xaa8
	s_mov_b32 s38, 0xcccccccd
	s_mov_b32 s40, 0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lg_u64 s[0:1], 0
	v_mad_u64_u32 v[50:51], null, s15, s2, v[0:1]
	s_cselect_b32 s33, 6, 0
	s_add_i32 s4, s4, -1
	s_mul_i32 s17, s3, s2
	s_min_u32 s37, s4, 32
	s_ashr_i32 s36, s17, 31
	s_sub_i32 s39, 32, s37
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v51, 31, v50
.LBB1_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_13 Depth 2
                                        ;     Child Loop BB1_102 Depth 2
                                        ;     Child Loop BB1_110 Depth 2
                                        ;     Child Loop BB1_116 Depth 2
                                        ;     Child Loop BB1_125 Depth 2
                                        ;     Child Loop BB1_129 Depth 2
                                        ;     Child Loop BB1_137 Depth 2
                                        ;     Child Loop BB1_143 Depth 2
                                        ;     Child Loop BB1_152 Depth 2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v50, 11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, 0xdeece66d, v51
	v_lshl_add_u32 v1, v50, 2, v50
	s_mov_b32 s41, exec_lo
	v_add3_u32 v3, v0, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v0, v3, v2, 17
	v_and_b32_e32 v0, 0x7fffffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, 0xcccccccd, v0
	v_cmpx_gt_u32_e32 0x33333334, v0
	s_cbranch_execz .LBB1_154
; %bb.2:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_alignbit_b32 v2, v1, v0, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0x7fffffff, v2
	v_mul_lo_u32 v2, 0xcccccccd, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 0x33333334, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3e800000, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.4:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3d4ccccd, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.5:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3e4ccccd, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.6:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3e4ccccd, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.7:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3e4ccccd, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.8:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v1, v2
	v_and_b32_e32 v1, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v1
	v_lshlrev_b64 v[3:4], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v3, 1, v3
	v_or_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_ldexp_f32 v3, v3, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x33800000, v3
	v_cmpx_gt_f32_e32 0x3e4ccccd, v3
; %bb.9:                                ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[3:4], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v2
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v4, v0
	v_and_b32_e32 v4, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
; %bb.10:                               ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_alignbit_b32 v0, v3, v2, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0x7fffffff, v0
	v_mul_lo_u32 v0, 0xaaaaaaab, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 0x55555556, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_154
; %bb.11:                               ;   in Loop: Header=BB1_1 Depth=1
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v1, v3, v1, v2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, 0xdeece66d, v1
	v_add3_u32 v3, v4, v3, v0
	v_bfe_u32 v0, v1, 14, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v1, v3, v2, 17
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
	v_cmp_eq_u32_e64 s0, 2, v0
	v_cmp_ne_u32_e64 s1, 3, v0
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, 2, s0
	v_cndmask_b32_e64 v4, 3, v4, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 3, v4
	v_dual_cndmask_b32 v6, 1, v4 :: v_dual_and_b32 v1, 0x7fffffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v5, 0x55555556, v1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v7, 0, v4, vcc_lo
	v_cndmask_b32_e64 v4, 2, v4, s0
	v_lshl_add_u32 v5, v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v1, v5
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_lshl_add_u32 v2, v2, 2, v2
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	v_cmp_eq_u32_e64 s0, 2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_dual_cndmask_b32 v8, v7, v6 :: v_dual_and_b32 v3, 0x8000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v4, s0
	v_cmp_eq_u32_e64 s0, 3, v5
	v_cndmask_b32_e64 v8, v8, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v8, v4
	v_cndmask_b32_e32 v4, v6, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_bfe_u32 v6, v1, 15, 1
	v_cndmask_b32_e32 v5, v7, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v2, 0, v2, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 3, v6
	v_cmp_eq_u32_e64 s1, 0, v6
	v_cndmask_b32_e32 v3, v5, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v6
	v_cndmask_b32_e64 v3, v3, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v2, s0
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v5, v3, s1
	v_cmp_eq_u32_e64 s1, 5, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB1_154
; %bb.12:                               ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s2, 0
	v_cndmask_b32_e64 v7, v2, v3, s0
	v_dual_cndmask_b32 v8, 0, v3 :: v_dual_mov_b32 v9, s2
	v_and_b32_e32 v1, 0xffff, v1
	s_mov_b64 s[0:1], 0
	s_mov_b32 s9, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr5
.LBB1_13:                               ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mad_u64_u32 v[44:45], null, 0xdeece66d, v0, 11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_or_b32 s5, s5, exec_lo
	s_or_b32 s4, s4, exec_lo
	v_add3_u32 v4, v1, v45, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v45, 0xffff, v4
	v_alignbit_b32 v2, v45, v44, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s38, 0x33333333
	v_cmp_gt_u32_e32 vcc_lo, 0x33333333, v0
                                        ; implicit-def: $vgpr0_vgpr1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB1_97
; %bb.14:                               ;   in Loop: Header=BB1_13 Depth=2
	s_xor_b32 s7, s9, -1
	s_cmp_eq_u32 s0, 1
	s_mov_b32 s8, 0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v0, v6, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 2, v0
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_54
; %bb.15:                               ; %LeafBlock52
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_mov_b32 s8, -1
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 3, v0
	s_cbranch_execz .LBB1_53
; %bb.16:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v44, 11
	v_mul_lo_u32 v0, 0xdeece66d, v4
	v_lshl_add_u32 v1, v44, 2, v44
	s_mov_b32 s9, 0
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v0, v3, v1
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e800000, v0
	s_cbranch_execz .LBB1_52
; %bb.17:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s10, 0
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3d4ccccd, v2
	s_cbranch_execz .LBB1_51
; %bb.18:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s11, 0
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_50
; %bb.19:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s12, 0
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nle_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_49
; %bb.20:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[4:5], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s13, 0
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v1, v5, v0
	v_alignbit_b32 v0, v5, v4, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0x7fffffff, v0
	v_mad_u64_u32 v[0:1], null, v2, s38, 0x33333333
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x33333333, v0
	s_cbranch_execz .LBB1_48
; %bb.21:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v4, 11
	v_mul_lo_u32 v0, 0xdeece66d, v5
	v_lshl_add_u32 v1, v4, 2, v4
	s_mov_b32 s14, 0
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v0, v3, v1
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_47
; %bb.22:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v1, v2
	v_and_b32_e32 v1, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v1
	v_lshlrev_b64 v[3:4], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v3, 1, v3
	v_or_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_ldexp_f32 v3, v3, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x33800000, v3
	v_cvt_f64_f32_e32 v[3:4], v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f64_e32 s[26:27], v[3:4]
; %bb.23:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[3:4], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v2
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v4, v0
	v_and_b32_e32 v4, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
; %bb.24:                               ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, 0xd498, v0
	v_mul_lo_u32 v1, 0xbd0ac4b5, v1
	v_mad_u64_u32 v[2:3], null, 0xbd0ac4b5, v0, s[28:29]
	s_mov_b32 s15, 0
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v4
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_46
; %bb.25:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s16, 0
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_45
; %bb.26:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s21, 0
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_44
; %bb.27:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v1, v2
	v_and_b32_e32 v1, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v1
	v_lshlrev_b64 v[3:4], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v3, 1, v3
	v_or_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_ldexp_f32 v3, v3, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x33800000, v3
	v_cmpx_gt_f32_e32 0x3e4ccccd, v3
; %bb.28:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[3:4], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v2
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v4, v0
	v_and_b32_e32 v4, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
; %bb.29:                               ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s22, 0
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s37, v[40:41]
	v_min_u32_e32 v1, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v1, v4, v1
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, s39
	v_mul_f32_e32 v1, 0x33800000, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nle_f32_e32 0x3e800000, v1
	s_cbranch_execz .LBB1_43
; %bb.30:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[3:4], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v0, 0xdeece66d, v0
	v_lshl_add_u32 v1, v2, 2, v2
	s_mov_b32 s23, 0
	s_mov_b32 s22, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v0, v4, v1
	v_alignbit_b32 v0, v4, v3, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0x7fffffff, v0
	v_mad_u64_u32 v[0:1], null, v2, s38, 0x33333333
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x33333333, v0
	s_cbranch_execz .LBB1_42
; %bb.31:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v3, 11
	v_mul_lo_u32 v2, 0xdeece66d, v4
	v_lshl_add_u32 v3, v3, 2, v3
	s_mov_b32 s30, 0
	s_mov_b32 s23, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v2, v1, v3
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nle_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_41
; %bb.32:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[4:5], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s31, 0
	s_mov_b32 s30, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v1, v5, v0
	v_alignbit_b32 v0, v5, v4, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0x7fffffff, v0
	v_mul_lo_u32 v0, 0xcccccccd, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x33333334, v0
	s_cbranch_execz .LBB1_40
; %bb.33:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v4, 11
	v_mul_lo_u32 v0, 0xdeece66d, v5
	v_lshl_add_u32 v1, v4, 2, v4
	s_mov_b32 s34, 0
	s_mov_b32 s31, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v0, v3, v1
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_39
; %bb.34:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s35, 0
	s_mov_b32 s34, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v2
	s_xor_b32 s34, exec_lo, s34
	s_cbranch_execz .LBB1_38
; %bb.35:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[44:45], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s35, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v45, v0
	v_and_b32_e32 v45, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v45
	v_lshlrev_b64 v[1:2], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v1, 1, v1
	v_or_b32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v1
	v_ldexp_f32 v1, v1, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x33800000, v1
	v_cmpx_gt_f32_e32 0x3e4ccccd, v1
; %bb.36:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[1:2], null, 0xdeece66d, v44, 11
	v_mul_lo_u32 v0, 0xdeece66d, v0
	v_lshl_add_u32 v3, v44, 2, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v2, v3
	v_and_b32_e32 v2, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v45, v2 :: v_dual_mov_b32 v44, v1
; %bb.37:                               ; %Flow82
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s35
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s35, exec_lo
.LBB1_38:                               ; %Flow120
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s34, s35, exec_lo
.LBB1_39:                               ; %Flow119
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s31, s34, exec_lo
.LBB1_40:                               ; %Flow118
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s30, s31, exec_lo
.LBB1_41:                               ; %Flow117
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s23, s30, exec_lo
.LBB1_42:                               ; %Flow116
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s22, s23, exec_lo
.LBB1_43:                               ; %Flow115
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s22, exec_lo
.LBB1_44:                               ; %Flow114
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s16, s21, exec_lo
.LBB1_45:                               ; %Flow113
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s15, s16, exec_lo
.LBB1_46:                               ; %Flow112
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s14, s15, exec_lo
.LBB1_47:                               ; %Flow111
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s13, s14, exec_lo
.LBB1_48:                               ; %Flow110
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s12, s13, exec_lo
.LBB1_49:                               ; %Flow109
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s12, exec_lo
.LBB1_50:                               ; %Flow108
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s10, s11, exec_lo
.LBB1_51:                               ; %Flow107
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s9, s10, exec_lo
.LBB1_52:                               ; %Flow106
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s8, s9, exec_lo
.LBB1_53:                               ; %Flow105
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s8, s8, exec_lo
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr4
.LBB1_54:                               ; %Flow104
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_94
; %bb.55:                               ; %LeafBlock
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_mov_b32 s9, -1
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 2, v0
	s_cbranch_execz .LBB1_93
; %bb.56:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v44, 11
	v_mul_lo_u32 v0, 0xdeece66d, v4
	v_lshl_add_u32 v1, v44, 2, v44
	s_mov_b32 s10, 0
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v0, v3, v1
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e800000, v0
	s_cbranch_execz .LBB1_92
; %bb.57:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s11, 0
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3d4ccccd, v2
	s_cbranch_execz .LBB1_91
; %bb.58:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s12, 0
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_90
; %bb.59:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s13, 0
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_89
; %bb.60:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s14, 0
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_88
; %bb.61:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v1, v2
	v_and_b32_e32 v1, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v1
	v_lshlrev_b64 v[3:4], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v3, 1, v3
	v_or_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_ldexp_f32 v3, v3, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x33800000, v3
	v_cmpx_gt_f32_e32 0x3e4ccccd, v3
; %bb.62:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[3:4], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v2
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v4, v0
	v_and_b32_e32 v4, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
; %bb.63:                               ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, 0xd498, v0
	v_mul_lo_u32 v1, 0xbd0ac4b5, v1
	v_mad_u64_u32 v[2:3], null, 0xbd0ac4b5, v0, s[28:29]
	s_mov_b32 s15, 0
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v4
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_87
; %bb.64:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s16, 0
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nle_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_86
; %bb.65:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[4:5], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s21, 0
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v1, v5, v0
	v_alignbit_b32 v0, v5, v4, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0x7fffffff, v0
	v_mad_u64_u32 v[0:1], null, v2, s38, 0xffffffff99999999
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x33333333, v0
	s_cbranch_execz .LBB1_85
; %bb.66:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v4, 11
	v_mul_lo_u32 v0, 0xdeece66d, v5
	v_lshl_add_u32 v1, v4, 2, v4
	s_mov_b32 s22, 0
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v0, v3, v1
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_84
; %bb.67:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v1, v2
	v_and_b32_e32 v1, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v1
	v_lshlrev_b64 v[3:4], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v3, 1, v3
	v_or_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_ldexp_f32 v3, v3, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x33800000, v3
	v_cmpx_gt_f32_e32 0x3e4ccccd, v3
; %bb.68:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[3:4], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v2
	v_lshl_add_u32 v0, v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v4, v0
	v_and_b32_e32 v4, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
; %bb.69:                               ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s23, 0
	s_mov_b32 s22, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nle_f32_e32 0x3e800000, v0
	s_cbranch_execz .LBB1_83
; %bb.70:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s30, 0
	s_mov_b32 s23, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_alignbit_b32 v2, v1, v0, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0x7fffffff, v2
	v_mad_u64_u32 v[2:3], null, v4, s38, 0xffffffffcccccccc
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x33333333, v2
	s_cbranch_execz .LBB1_82
; %bb.71:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s31, 0
	s_mov_b32 s30, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_and_b32_e32 v40, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s37, v[40:41]
	v_min_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v1, v0
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, s39
	v_mul_f32_e32 v0, 0x33800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v0
	s_cbranch_execz .LBB1_81
; %bb.72:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s34, 0
	s_mov_b32 s31, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nle_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_80
; %bb.73:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s35, 0
	s_mov_b32 s34, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v1, v3, v0
	v_alignbit_b32 v0, v3, v2, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0x7fffffff, v0
	v_mad_u64_u32 v[0:1], null, v4, s38, 0xffffffffcccccccc
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x33333333, v0
	s_cbranch_execz .LBB1_79
; %bb.74:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v2, 11
	v_mul_lo_u32 v3, 0xdeece66d, v3
	v_lshl_add_u32 v2, v2, 2, v2
	s_mov_b32 s42, 0
	s_mov_b32 s35, exec_lo
                                        ; implicit-def: $vgpr44_vgpr45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v2
	v_and_b32_e32 v40, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], s37, v[40:41]
	v_min_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, s39
	v_mul_f32_e32 v2, 0x33800000, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3e4ccccd, v2
	s_cbranch_execz .LBB1_78
; %bb.75:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[44:45], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	s_mov_b32 s42, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v45, v0
	v_and_b32_e32 v45, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v45
	v_lshlrev_b64 v[1:2], s37, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v1, 1, v1
	v_or_b32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v1
	v_ldexp_f32 v1, v1, s39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x33800000, v1
	v_cmpx_gt_f32_e32 0x3e4ccccd, v1
; %bb.76:                               ;   in Loop: Header=BB1_13 Depth=2
	v_mad_u64_u32 v[1:2], null, 0xdeece66d, v44, 11
	v_mul_lo_u32 v0, 0xdeece66d, v0
	v_lshl_add_u32 v3, v44, 2, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v2, v3
	v_and_b32_e32 v2, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v45, v2 :: v_dual_mov_b32 v44, v1
; %bb.77:                               ; %Flow83
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s42
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s42, exec_lo
.LBB1_78:                               ; %Flow137
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s35
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s35, s42, exec_lo
.LBB1_79:                               ; %Flow136
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s34, s35, exec_lo
.LBB1_80:                               ; %Flow135
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s31, s34, exec_lo
.LBB1_81:                               ; %Flow134
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s30, s31, exec_lo
.LBB1_82:                               ; %Flow133
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s23, s30, exec_lo
.LBB1_83:                               ; %Flow132
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s22, s23, exec_lo
.LBB1_84:                               ; %Flow131
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s22, exec_lo
.LBB1_85:                               ; %Flow130
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s16, s21, exec_lo
.LBB1_86:                               ; %Flow129
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s15, s16, exec_lo
.LBB1_87:                               ; %Flow128
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s14, s15, exec_lo
.LBB1_88:                               ; %Flow127
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s13, s14, exec_lo
.LBB1_89:                               ; %Flow126
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s12, s13, exec_lo
.LBB1_90:                               ; %Flow125
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s12, exec_lo
.LBB1_91:                               ; %Flow124
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s10, s11, exec_lo
.LBB1_92:                               ; %Flow123
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s9, s10, exec_lo
.LBB1_93:                               ; %Flow122
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s8, exec_lo
	s_and_b32 s8, s9, exec_lo
	s_or_b32 s8, s1, s8
.LBB1_94:                               ; %Flow121
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s10, -1
	s_mov_b32 s11, -1
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr9
	s_and_saveexec_b32 s12, s8
; %bb.95:                               ;   in Loop: Header=BB1_13 Depth=2
	s_mov_b32 s9, 0
	s_mov_b64 s[0:1], 1
	s_xor_b32 s11, exec_lo, -1
	s_or_not1_b32 s10, s7, exec_lo
; %bb.96:                               ; %Flow138
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	v_dual_mov_b32 v0, v44 :: v_dual_mov_b32 v1, v45
	s_and_not1_b32 s1, s5, exec_lo
	s_and_b32 s5, s11, exec_lo
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s7, s10, exec_lo
	s_or_b32 s5, s1, s5
	s_or_b32 s4, s4, s7
.LBB1_97:                               ; %Flow103
                                        ;   in Loop: Header=BB1_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s4
	s_or_b32 s2, s1, s2
	s_and_not1_b32 s1, s3, exec_lo
	s_and_b32 s3, s5, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s1, s3
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_13
; %bb.98:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_xor_b32 s0, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_154
; %bb.99:                               ;   in Loop: Header=BB1_1 Depth=1
	s_load_b64 s[34:35], s[18:19], 0x50
	v_mov_b32_e32 v40, v52
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v40
	v_cmp_eq_u32_e64 s0, s0, v40
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_105
; %bb.100:                              ;   in Loop: Header=BB1_1 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v41, s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v41, s[34:35] offset:40
	global_load_b64 v[4:5], v41, s[34:35]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v41, v[0:3], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_104
; %bb.101:                              ; %.preheader3.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s3, 0
.LBB1_102:                              ; %.preheader3.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v41, s[34:35] offset:40
	global_load_b64 v[6:7], v41, s[34:35]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v41, v[0:3], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_102
; %bb.103:                              ; %Flow78
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_104:                              ; %Flow80
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_105:                              ; %.loopexit4.i.i.i.i
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v41, s[34:35] offset:40
	global_load_b128 v[0:3], v41, s[34:35]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_107
; %bb.106:                              ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v46, s8 :: v_dual_mov_b32 v47, v41
	global_store_b128 v[4:5], v[46:49], off offset:8
.LBB1_107:                              ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[40:41]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v40, v41
	v_mov_b32_e32 v42, v41
	v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v5, s23
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, s22
	s_clause 0x3
	global_store_b128 v[6:7], v[39:42], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_115
; %bb.108:                              ;   in Loop: Header=BB1_1 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v41, s[34:35] offset:32 glc
	global_load_b64 v[2:3], v41, s[34:35] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v41, v[10:13], s[34:35] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_111
; %bb.109:                              ; %.preheader1.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s8, 0
.LBB1_110:                              ; %.preheader1.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v41, v[2:5], s[34:35] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_110
.LBB1_111:                              ; %Flow76
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v41, s[34:35] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_113
; %bb.112:                              ;   in Loop: Header=BB1_1 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v40, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[40:41], off offset:8
.LBB1_113:                              ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_115
; %bb.114:                              ;   in Loop: Header=BB1_1 Depth=1
	global_load_b32 v40, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v40
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[40:41], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_115:                              ; %Flow77
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_116:                              ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_118
; %bb.117:                              ;   in Loop: Header=BB1_116 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_118:                              ;   in Loop: Header=BB1_116 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_120
; %bb.119:                              ;   in Loop: Header=BB1_116 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_121
.LBB1_120:                              ;   in Loop: Header=BB1_116 Depth=2
	s_mov_b32 s1, -1
.LBB1_121:                              ; %Flow71
                                        ;   in Loop: Header=BB1_116 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_116
; %bb.122:                              ;   in Loop: Header=BB1_1 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_126
; %bb.123:                              ;   in Loop: Header=BB1_1 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v41, s[34:35] offset:40
	global_load_b64 v[8:9], v41, s[34:35] offset:24 glc
	global_load_b64 v[6:7], v41, s[34:35]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v41, v[2:5], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_126
; %bb.124:                              ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s0, 0
.LBB1_125:                              ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v41, v[2:5], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_125
.LBB1_126:                              ; %__ockl_printf_begin.exit.i
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, s33 :: v_dual_mov_b32 v3, v41
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_dual_mov_b32 v43, v1 :: v_dual_mov_b32 v40, v52
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v40
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v40
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_132
; %bb.127:                              ;   in Loop: Header=BB1_1 Depth=1
	global_load_b64 v[3:4], v41, s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v41, s[34:35] offset:40
	global_load_b64 v[5:6], v41, s[34:35]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v41, v[1:4], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[3:4]
	s_cbranch_execz .LBB1_131
; %bb.128:                              ; %.preheader3.i.i.i228.i.preheader
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s3, 0
.LBB1_129:                              ; %.preheader3.i.i.i228.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v41, s[34:35] offset:40
	global_load_b64 v[7:8], v41, s[34:35]
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v2, v2, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[7:8]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[1:2]
	global_load_b64 v[1:2], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v41, v[1:4], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_129
; %bb.130:                              ; %Flow64
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_131:                              ; %Flow66
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_132:                              ; %.loopexit4.i.i.i223.i
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v41, s[34:35] offset:40
	global_load_b128 v[1:4], v41, s[34:35]
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_134
; %bb.133:                              ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v6, vcc_lo, s10, v2, vcc_lo
	v_dual_mov_b32 v46, s8 :: v_dual_mov_b32 v47, v41
	global_store_b128 v[5:6], v[46:49], off offset:8
.LBB1_134:                              ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s21, s20
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[40:41]
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v42, 0xffffff1d, v0, 34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v4, vcc_lo
	v_dual_mov_b32 v3, s20 :: v_dual_mov_b32 v4, s21
	v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
	s_clause 0x3
	global_store_b128 v[7:8], v[42:45], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_142
; %bb.135:                              ;   in Loop: Header=BB1_1 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v41, s[34:35] offset:32 glc
	global_load_b64 v[3:4], v41, s[34:35] offset:40
	v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v10, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v7, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v41, v[9:12], s[34:35] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[11:12]
	s_cbranch_execz .LBB1_138
; %bb.136:                              ; %.preheader1.i.i.i226.i.preheader
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s8, 0
.LBB1_137:                              ; %.preheader1.i.i.i226.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v41, v[3:6], s[34:35] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_137
.LBB1_138:                              ; %Flow62
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[3:4], v41, s[34:35] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_140
; %bb.139:                              ;   in Loop: Header=BB1_1 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v40, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[40:41], off offset:8
.LBB1_140:                              ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_142
; %bb.141:                              ;   in Loop: Header=BB1_1 Depth=1
	global_load_b32 v40, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v40
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[40:41], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_142:                              ; %Flow63
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_143:                              ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_145
; %bb.144:                              ;   in Loop: Header=BB1_143 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_145:                              ;   in Loop: Header=BB1_143 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_147
; %bb.146:                              ;   in Loop: Header=BB1_143 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_148
.LBB1_147:                              ;   in Loop: Header=BB1_143 Depth=2
	s_mov_b32 s1, -1
.LBB1_148:                              ; %Flow57
                                        ;   in Loop: Header=BB1_143 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_143
; %bb.149:                              ;   in Loop: Header=BB1_1 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_153
; %bb.150:                              ;   in Loop: Header=BB1_1 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v41, s[34:35] offset:40
	global_load_b64 v[6:7], v41, s[34:35] offset:24 glc
	global_load_b64 v[4:5], v41, s[34:35]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v41, v[0:3], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_153
; %bb.151:                              ; %.preheader.i.i.i225.i.preheader
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s0, 0
.LBB1_152:                              ; %.preheader.i.i.i225.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v41, v[0:3], s[34:35] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_152
.LBB1_153:                              ; %Flow55
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_154:                              ; %_Z10check_seedx.exit
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s41
	v_add_co_u32 v50, vcc_lo, v50, s17
	v_add_co_ci_u32_e32 v51, vcc_lo, s36, v51, vcc_lo
	v_cmp_lt_i64_e32 vcc_lo, s[24:25], v[50:51]
	s_or_b32 s40, vcc_lo, s40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s40
	s_cbranch_execnz .LBB1_1
; %bb.155:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4findv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 53
		.amdhsa_next_free_sgpr 43
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z4findv, .Lfunc_end1-_Z4findv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9984
; NumSgprs: 45
; NumVgprs: 53
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 45
; NumVGPRsForWavesPerEU: 53
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%lld\n"
	.size	.str, 6

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         80
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4findv
    .private_segment_fixed_size: 0
    .sgpr_count:     45
    .sgpr_spill_count: 0
    .symbol:         _Z4findv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     53
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
