#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define warp_size 32
#define Hwarp_size 16
#define A 0
#define B 15

void checkCUDAError(const char* msg);

__host__ __device__ inline double f(double x)
{
	return exp(x)*sin(x);
}


__host__ __device__ inline unsigned int getFirstSetBitPos(int n)
{
   return log2((float)(n&-n))+1;
}


__global__ void romberg(double a, double b, int row_size, double *result)	//row_size<=25, preferably 14
{
	extern __shared__ double local_array[];
	double diff = (b-a)/gridDim.x, step;
	int max_eval = (1<<(row_size-1)),k;
	b = a + (blockIdx.x+1)*diff;
	a += blockIdx.x*diff;
	
	step = (b-a)/max_eval;
	
	double local_col[25];
	for(int i = 0; i < row_size; i++)
		local_col[i] = 0.0;
	if(!threadIdx.x)
	{
		k = blockDim.x;
		local_col[0] = f(a) + f(b);
	}
	else
		k = threadIdx.x;
	
	for(; k < max_eval; k += blockDim.x)
	{
		local_col[row_size - getFirstSetBitPos(k)] += 2.0*f(a + step*k);
	}
	for(int i = 0; i < row_size; i++)
	{
		local_array[row_size*threadIdx.x + i] = local_col[i];
	}
	__syncthreads();
	if(threadIdx.x < row_size)
	{
		double sum = 0.0;
		for(int i = threadIdx.x; i < blockDim.x*row_size; i+=row_size)
			sum += local_array[i];
		
		local_array[threadIdx.x] = sum;
	}
	
	if(!threadIdx.x)
	{
		double *romberg_table = local_col;
		romberg_table[0] = local_array[0];
		for(int k = 1; k < row_size; k++)
			romberg_table[k] = romberg_table[k-1] + local_array[k];
		for(int k = 0; k < row_size; k++)	
			romberg_table[k]*= (b-a)/(1<<(k+1));
		
		for(int col = 0 ; col < row_size-1 ; col++)
		{
			for(int row = row_size-1; row > col; row--)
			{
				romberg_table[row] = romberg_table[row] + (romberg_table[row] - romberg_table[row-1])/((1<<(2*col+1))-1);
			}
		}
		result[blockIdx.x] = romberg_table[row_size-1];
	}

}


int main( int argc, char** argv)
{
	double *d_result, *h_result,sum=0.0;
	int numBlocks = 128, numThreadsPerBlock = 64, row_size = 13, max_eval = (1<<(row_size-1));
	cudaDeviceSetCacheConfig(cudaFuncCachePreferShared);
    cudaMalloc( (void **) &d_result, numBlocks*sizeof(double) );
	h_result = new double[numBlocks];
	
	timeval t;
	double t1,t2,t3,t4;
	
	gettimeofday(&t, NULL);
	t1 = t.tv_sec*1000.0 + (t.tv_usec/1000.0);
	
	
	romberg<<< numBlocks, numThreadsPerBlock, row_size*numThreadsPerBlock*sizeof(double) >>>(A,B,row_size,d_result);
	cudaThreadSynchronize();
	
	gettimeofday(&t, NULL);
	t2 = t.tv_sec*1000.0 + (t.tv_usec/1000.0);
	checkCUDAError("kernel invocation");
	cudaMemcpy( h_result, d_result, numBlocks*sizeof(double), cudaMemcpyDeviceToHost );
	checkCUDAError("memcpy");
	
	//for(int k = 0; k<(max_eval+1)*numBlocks; k++ )
	//	printf("%lf\t",h_result[k]);
	for(int k=0;k<numBlocks;k++)
		sum+=h_result[k];
	printf("TIME : %lf ms with ans = %lf\n\n\n",t2-t1,sum);
}

void checkCUDAError(const char *msg)
{
    cudaError_t err = cudaGetLastError();
    if( cudaSuccess != err)
    {
        fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
        exit(EXIT_FAILURE);
    }
}

	.file	"tmpxft_002ee14c_00000000-6_romberg_v2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Cuda error: %s: %s.\n"
	.text
	.globl	_Z14checkCUDAErrorPKc
	.type	_Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	leaq	.LC0(%rip), %rdx
	movq	%rax, %r8
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
	.globl	_Z29__device_stub__Z7rombergddiPdddiPd
	.type	_Z29__device_stub__Z7rombergddiPdddiPd, @function
_Z29__device_stub__Z7rombergddiPdddiPd:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 12(%rsp)
	leaq	48(%rsp), %rcx
	leaq	40(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	56(%rsp), %rdi
	leaq	68(%rsp), %rsi
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7rombergddiPd(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L6:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z29__device_stub__Z7rombergddiPdddiPd, .-_Z29__device_stub__Z7rombergddiPdddiPd
	.globl	_Z7rombergddiPd
	.type	_Z7rombergddiPd, @function
_Z7rombergddiPd:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7rombergddiPdddiPd
	.cfi_endproc
.LFE2056:
	.size	_Z7rombergddiPd, .-_Z7rombergddiPd
	.section	.rodata.str1.1
.LC4:
	.string	"kernel invocation"
.LC5:
	.string	"memcpy"
.LC6:
	.string	"TIME : %lf ms with ans = %lf\n\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$88, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rbp
	call	cudaDeviceSetCacheConfig@PLT
	movl	$1024, %esi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1024, %edi
	call	_Znam@PLT
	xorl	%esi, %esi
	movq	%rbp, %rdi
	movq	%rax, %rbx
	call	gettimeofday@PLT
	cvtsi2sdq	56(%rsp), %xmm1
	movl	$67108865, %edx
	movl	$33554433, %edi
	salq	$6, %rdx
	xorl	%r9d, %r9d
	salq	$7, %rdi
	movl	$1, %ecx
	mulsd	.LC2(%rip), %xmm1
	movl	$6656, %r8d
	movl	$1, %esi
	cvtsi2sdq	64(%rsp), %xmm0
	divsd	.LC2(%rip), %xmm0
	addsd	%xmm0, %xmm1
	movsd	%xmm1, (%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	24(%rsp), %rsi
	movsd	.LC3(%rip), %xmm1
	movl	$13, %edi
	xorps	%xmm0, %xmm0
	call	_Z29__device_stub__Z7rombergddiPdddiPd
.L12:
	call	cudaThreadSynchronize@PLT
	xorl	%esi, %esi
	movq	%rbp, %rdi
	call	gettimeofday@PLT
	cvtsi2sdq	56(%rsp), %xmm0
	mulsd	.LC2(%rip), %xmm0
	leaq	.LC4(%rip), %rdi
	cvtsi2sdq	64(%rsp), %xmm1
	divsd	.LC2(%rip), %xmm1
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 8(%rsp)
	call	_Z14checkCUDAErrorPKc
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rdi
	call	_Z14checkCUDAErrorPKc
	movsd	8(%rsp), %xmm0
	xorl	%eax, %eax
	xorps	%xmm1, %xmm1
.L13:
	addsd	(%rbx,%rax,8), %xmm1
	incq	%rax
	cmpq	$128, %rax
	jne	.L13
	subsd	(%rsp), %xmm0
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$88, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z7rombergddiPd"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7rombergddiPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1083129856
	.align 8
.LC3:
	.long	0
	.long	1076756480
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define warp_size 32
#define Hwarp_size 16
#define A 0
#define B 15

void checkCUDAError(const char* msg);

__host__ __device__ inline double f(double x)
{
	return exp(x)*sin(x);
}


__host__ __device__ inline unsigned int getFirstSetBitPos(int n)
{
   return log2((float)(n&-n))+1;
}


__global__ void romberg(double a, double b, int row_size, double *result)	//row_size<=25, preferably 14
{
	extern __shared__ double local_array[];
	double diff = (b-a)/gridDim.x, step;
	int max_eval = (1<<(row_size-1)),k;
	b = a + (blockIdx.x+1)*diff;
	a += blockIdx.x*diff;
	
	step = (b-a)/max_eval;
	
	double local_col[25];
	for(int i = 0; i < row_size; i++)
		local_col[i] = 0.0;
	if(!threadIdx.x)
	{
		k = blockDim.x;
		local_col[0] = f(a) + f(b);
	}
	else
		k = threadIdx.x;
	
	for(; k < max_eval; k += blockDim.x)
	{
		local_col[row_size - getFirstSetBitPos(k)] += 2.0*f(a + step*k);
	}
	for(int i = 0; i < row_size; i++)
	{
		local_array[row_size*threadIdx.x + i] = local_col[i];
	}
	__syncthreads();
	if(threadIdx.x < row_size)
	{
		double sum = 0.0;
		for(int i = threadIdx.x; i < blockDim.x*row_size; i+=row_size)
			sum += local_array[i];
		
		local_array[threadIdx.x] = sum;
	}
	
	if(!threadIdx.x)
	{
		double *romberg_table = local_col;
		romberg_table[0] = local_array[0];
		for(int k = 1; k < row_size; k++)
			romberg_table[k] = romberg_table[k-1] + local_array[k];
		for(int k = 0; k < row_size; k++)	
			romberg_table[k]*= (b-a)/(1<<(k+1));
		
		for(int col = 0 ; col < row_size-1 ; col++)
		{
			for(int row = row_size-1; row > col; row--)
			{
				romberg_table[row] = romberg_table[row] + (romberg_table[row] - romberg_table[row-1])/((1<<(2*col+1))-1);
			}
		}
		result[blockIdx.x] = romberg_table[row_size-1];
	}

}


int main( int argc, char** argv)
{
	double *d_result, *h_result,sum=0.0;
	int numBlocks = 128, numThreadsPerBlock = 64, row_size = 13, max_eval = (1<<(row_size-1));
	hipDeviceSetCacheConfig(hipFuncCachePreferShared);
    hipMalloc( (void **) &d_result, numBlocks*sizeof(double) );
	h_result = new double[numBlocks];
	
	timeval t;
	double t1,t2,t3,t4;
	
	gettimeofday(&t, NULL);
	t1 = t.tv_sec*1000.0 + (t.tv_usec/1000.0);
	
	
	romberg<<< numBlocks, numThreadsPerBlock, row_size*numThreadsPerBlock*sizeof(double) >>>(A,B,row_size,d_result);
	hipDeviceSynchronize();
	
	gettimeofday(&t, NULL);
	t2 = t.tv_sec*1000.0 + (t.tv_usec/1000.0);
	checkCUDAError("kernel invocation");
	hipMemcpy( h_result, d_result, numBlocks*sizeof(double), hipMemcpyDeviceToHost );
	checkCUDAError("memcpy");
	
	//for(int k = 0; k<(max_eval+1)*numBlocks; k++ )
	//	printf("%lf\t",h_result[k]);
	for(int k=0;k<numBlocks;k++)
		sum+=h_result[k];
	printf("TIME : %lf ms with ans = %lf\n\n\n",t2-t1,sum);
}

void checkCUDAError(const char *msg)
{
    hipError_t err = hipGetLastError();
    if( hipSuccess != err)
    {
        fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
        exit(EXIT_FAILURE);
    }
}

	.text
	.file	"romberg_v2.hip"
	.globl	_Z22__device_stub__rombergddiPd # -- Begin function _Z22__device_stub__rombergddiPd
	.type	_Z22__device_stub__rombergddiPd,@function
_Z22__device_stub__rombergddiPd:        # @_Z22__device_stub__rombergddiPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	32(%rsp), %rcx
	movsd	%xmm1, (%rcx)
	leaq	4(%rsp), %rdx
	movl	%edi, (%rdx)
	leaq	24(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rdi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7rombergddiPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__rombergddiPd, .Lfunc_end0-_Z22__device_stub__rombergddiPd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x402e000000000000              # double 15
.LCPI1_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1, %edi
	callq	hipDeviceSetCacheConfig
	movq	%rsp, %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	movl	$1024, %edi                     # imm = 0x400
	callq	_Znam
	movq	%rax, %rbx
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r14), %r12
	movq	8(%r14), %r15
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	leaq	64(%rdx), %rdi
	movl	$6656, %r8d                     # imm = 0x1A00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	(%rsp), %rsi
	movsd	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero
	xorps	%xmm0, %xmm0
	movl	$13, %edi
	callq	_Z22__device_stub__rombergddiPd
.LBB1_2:
	callq	hipDeviceSynchronize
	xorl	%r13d, %r13d
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r14), %rbp
	movq	8(%r14), %r14
	movl	$.L.str, %edi
	callq	_Z14checkCUDAErrorPKc
	movq	(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.1, %edi
	callq	_Z14checkCUDAErrorPKc
	xorpd	%xmm1, %xmm1
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	addsd	(%rbx,%r13,8), %xmm1
	incq	%r13
	cmpq	$128, %r13
	jne	.LBB1_3
# %bb.4:
	cvtsi2sd	%rbp, %xmm2
	movsd	.LCPI1_1(%rip), %xmm3           # xmm3 = mem[0],zero
	mulsd	%xmm3, %xmm2
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r14, %xmm0
	divsd	%xmm3, %xmm0
	addsd	%xmm2, %xmm0
	xorps	%xmm2, %xmm2
	cvtsi2sd	%r12, %xmm2
	cvtsi2sd	%r15, %xmm4
	mulsd	%xmm3, %xmm2
	divsd	%xmm3, %xmm4
	addsd	%xmm2, %xmm4
	subsd	%xmm4, %xmm0
	movl	$.L.str.2, %edi
	movb	$2, %al
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z14checkCUDAErrorPKc           # -- Begin function _Z14checkCUDAErrorPKc
	.type	_Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc:                  # @_Z14checkCUDAErrorPKc
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 32
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.3, %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7rombergddiPd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7rombergddiPd,@object         # @_Z7rombergddiPd
	.section	.rodata,"a",@progbits
	.globl	_Z7rombergddiPd
	.p2align	3, 0x0
_Z7rombergddiPd:
	.quad	_Z22__device_stub__rombergddiPd
	.size	_Z7rombergddiPd, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"kernel invocation"
	.size	.L.str, 18

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"memcpy"
	.size	.L.str.1, 7

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"TIME : %lf ms with ans = %lf\n\n\n"
	.size	.L.str.2, 32

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Cuda error: %s: %s.\n"
	.size	.L.str.3, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7rombergddiPd"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__rombergddiPd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7rombergddiPd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7rombergddiPd         ; -- Begin function _Z7rombergddiPd
	.globl	_Z7rombergddiPd
	.p2align	8
	.type	_Z7rombergddiPd,@function
_Z7rombergddiPd:                        ; @_Z7rombergddiPd
; %bb.0:
	s_clause 0x1
	s_load_b32 s11, s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x20
	s_add_u32 s12, s0, 32
	s_addc_u32 s13, s1, 0
	s_mov_b32 s10, s15
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s11, 0
	s_cselect_b32 s33, -1, 0
	s_cmp_lt_i32 s11, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v3, 16
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, s11
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v2, v1
	s_add_i32 s3, s3, -1
	s_cmp_eq_u32 s3, 0
	scratch_store_b64 v3, v[1:2], off
	v_add_nc_u32_e32 v3, 8, v3
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_load_b128 s[4:7], s[0:1], 0x0
	v_cvt_f64_u32_e32 v[1:2], s2
	s_add_i32 s2, s10, 1
	v_mov_b32_e32 v15, v0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], s[6:7], -s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], v[3:4]
	v_div_scale_f64 v[11:12], vcc_lo, v[3:4], v[1:2], v[3:4]
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
	v_cvt_f64_u32_e32 v[7:8], s2
	v_cmp_eq_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[1:2], v[5:6], v[1:2], v[3:4]
	v_cvt_f64_u32_e32 v[5:6], s10
	v_fma_f64 v[3:4], v[1:2], v[7:8], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[1:2], v[1:2], v[5:6], s[4:5]
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB0_15
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |v[1:2]|
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_6
; %bb.5:
	v_ldexp_f64 v[5:6], |v[1:2]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[1:2]|
	v_trig_preop_f64 v[7:8], |v[1:2]|, 0
	v_and_b32_e32 v9, 0x7fffffff, v2
	v_trig_preop_f64 v[19:20], |v[1:2]|, 2
	s_mov_b32 s4, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s14, 0x33145c07
	s_mov_b32 s15, 0x3c91a626
	v_cndmask_b32_e32 v6, v9, v6, vcc_lo
	v_cndmask_b32_e32 v5, v1, v5, vcc_lo
	v_trig_preop_f64 v[9:10], |v[1:2]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[11:12], v[7:8], v[5:6]
	v_mul_f64 v[13:14], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[7:8], v[5:6], -v[11:12]
	v_fma_f64 v[9:10], v[9:10], v[5:6], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[13:14], v[7:8]
	v_add_f64 v[17:18], v[15:16], -v[13:14]
	v_add_f64 v[23:24], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], -v[17:18]
	v_add_f64 v[7:8], v[7:8], -v[17:18]
	v_ldexp_f64 v[17:18], v[23:24], -2
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[17:18]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	v_add_f64 v[7:8], v[7:8], v[13:14]
	v_fract_f64_e32 v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, 0, v14 :: v_dual_cndmask_b32 v13, 0, v13
	v_mul_f64 v[25:26], v[19:20], v[5:6]
	v_ldexp_f64 v[13:14], v[13:14], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[25:26], v[9:10]
	v_fma_f64 v[5:6], v[19:20], v[5:6], -v[25:26]
	v_add_f64 v[15:16], v[21:22], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[11:12], v[15:16]
	v_add_f64 v[27:28], v[15:16], -v[21:22]
	v_add_f64 v[23:24], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[15:16], -v[27:28]
	v_add_f64 v[7:8], v[7:8], -v[27:28]
	v_add_f64 v[11:12], v[17:18], -v[11:12]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[23:24]
	v_add_f64 v[23:24], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x40100000, 0
	v_add_f64 v[31:32], v[21:22], -v[23:24]
	v_add_f64 v[13:14], v[13:14], s[4:5]
	v_add_f64 v[9:10], v[9:10], -v[23:24]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[25:26], -v[31:32]
	v_add_f64 v[29:30], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[21:22]
	v_add_f64 v[9:10], v[9:10], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v29, v[29:30]
	v_add_f64 v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[27:28], v29
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[27:28]
	v_add_f64 v[5:6], v[11:12], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[17:18], v[13:14]
	v_add_f64 v[7:8], v[9:10], -v[13:14]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[17:18], -v[7:8]
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v13, s3, 0, v29, vcc_lo
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[9:10], -s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[7:8], v[5:6]
	v_mul_f64 v[11:12], v[9:10], s[6:7]
	v_add_f64 v[7:8], v[9:10], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[9:10], s[6:7], -v[11:12]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[9:10], s[14:15], v[14:15]
	v_fma_f64 v[7:8], v[5:6], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[11:12], v[7:8]
	v_add_f64 v[9:10], v[5:6], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	s_branch .LBB0_7
.LBB0_6:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $vgpr7_vgpr8
.LBB0_7:                                ; %Flow174
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_9
; %bb.8:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[5:6], |v[1:2]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[9:10], v[5:6]
	v_fma_f64 v[5:6], v[9:10], s[4:5], |v[1:2]|
	v_mul_f64 v[7:8], v[9:10], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[9:10], s[6:7], v[5:6]
	v_add_f64 v[11:12], v[5:6], v[7:8]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_fma_f64 v[7:8], v[9:10], s[6:7], v[7:8]
	v_add_f64 v[5:6], v[11:12], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_fma_f64 v[7:8], v[9:10], s[4:5], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[13:14], v[7:8]
	v_add_f64 v[11:12], v[5:6], -v[13:14]
	v_cvt_i32_f64_e32 v13, v[9:10]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[11:12]
.LBB0_9:                                ; %_Z1fd.exit
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |v[3:4]|
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_11
; %bb.10:
	v_ldexp_f64 v[9:10], |v[3:4]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[3:4]|
	v_trig_preop_f64 v[11:12], |v[3:4]|, 0
	v_and_b32_e32 v14, 0x7fffffff, v4
	v_trig_preop_f64 v[24:25], |v[3:4]|, 2
	s_mov_b32 s4, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s14, 0x33145c07
	s_mov_b32 s15, 0x3c91a626
	v_dual_cndmask_b32 v9, v3, v9 :: v_dual_cndmask_b32 v10, v14, v10
	v_trig_preop_f64 v[14:15], |v[3:4]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[11:12], v[9:10]
	v_mul_f64 v[18:19], v[14:15], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], v[9:10], -v[16:17]
	v_fma_f64 v[14:15], v[14:15], v[9:10], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], v[11:12]
	v_add_f64 v[22:23], v[20:21], -v[18:19]
	v_add_f64 v[28:29], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[20:21], -v[22:23]
	v_add_f64 v[11:12], v[11:12], -v[22:23]
	v_ldexp_f64 v[22:23], v[28:29], -2
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_add_f64 v[11:12], v[11:12], v[18:19]
	v_fract_f64_e32 v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v19, 0, v19, vcc_lo
	v_mul_f64 v[30:31], v[24:25], v[9:10]
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[18:19], v[18:19], 2
	v_add_f64 v[26:27], v[30:31], v[14:15]
	v_fma_f64 v[9:10], v[24:25], v[9:10], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], v[11:12]
	v_add_f64 v[22:23], v[16:17], v[20:21]
	v_add_f64 v[32:33], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[22:23], v[18:19]
	v_add_f64 v[38:39], v[20:21], -v[32:33]
	v_add_f64 v[11:12], v[11:12], -v[32:33]
	v_add_f64 v[16:17], v[22:23], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x40100000, 0
	v_add_f64 v[36:37], v[26:27], -v[28:29]
	v_add_f64 v[18:19], v[18:19], s[4:5]
	v_add_f64 v[14:15], v[14:15], -v[28:29]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[30:31], -v[36:37]
	v_add_f64 v[34:35], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[26:27]
	v_add_f64 v[14:15], v[14:15], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v34, v[34:35]
	v_add_f64 v[11:12], v[14:15], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[32:33], v34
	v_add_f64 v[14:15], v[20:21], -v[16:17]
	v_add_f64 v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[32:33]
	v_add_f64 v[9:10], v[14:15], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], v[18:19]
	v_add_f64 v[11:12], v[24:25], -v[18:19]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[22:23], -v[11:12]
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v14, s3, 0, v34, vcc_lo
	v_add_f64 v[9:10], v[9:10], v[11:12]
	v_add_f64 v[11:12], v[24:25], -s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[11:12], v[9:10]
	v_mul_f64 v[17:18], v[15:16], s[6:7]
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], s[6:7], -v[17:18]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], s[14:15], v[19:20]
	v_fma_f64 v[11:12], v[9:10], s[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[17:18], v[11:12]
	v_add_f64 v[15:16], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	s_branch .LBB0_12
.LBB0_11:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr9_vgpr10
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_12:                               ; %Flow173
	s_load_b32 s14, s[12:13], 0xc
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_14
; %bb.13:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[9:10], |v[3:4]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[14:15], v[9:10]
	v_fma_f64 v[9:10], v[14:15], s[4:5], |v[3:4]|
	v_mul_f64 v[11:12], v[14:15], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[14:15], s[6:7], v[9:10]
	v_add_f64 v[16:17], v[9:10], v[11:12]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], -v[16:17]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[11:12]
	v_fma_f64 v[11:12], v[14:15], s[6:7], v[11:12]
	v_add_f64 v[9:10], v[16:17], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_fma_f64 v[11:12], v[14:15], s[4:5], v[9:10]
	v_cvt_i32_f64_e32 v14, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[18:19], v[11:12]
	v_add_f64 v[16:17], v[9:10], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[16:17]
.LBB0_14:                               ; %_Z1fd.exit90
	s_mov_b32 s4, 0x652b82fe
	s_mov_b32 s5, 0x3ff71547
	s_mov_b32 s6, 0xfca7ab0c
	v_mul_f64 v[15:16], v[3:4], s[4:5]
	v_mul_f64 v[17:18], v[1:2], s[4:5]
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s5, 0xbfe62e42
	s_mov_b32 s7, 0x3e928af3
	v_mul_f64 v[27:28], v[9:10], v[9:10]
	v_mul_f64 v[29:30], v[5:6], v[5:6]
	s_mov_b32 s16, 0xf9a43bb8
	s_mov_b32 s17, 0x3de5e0b2
	s_mov_b32 s18, 0x11122322
	s_mov_b32 s19, 0x3f811111
	s_mov_b32 s20, 0x9037ab78
	s_mov_b32 s21, 0x3e21eeb6
	s_mov_b32 s22, 0x19f4ec90
	s_mov_b32 s23, 0x3efa01a0
	v_mul_f64 v[47:48], v[11:12], 0.5
	v_mul_f64 v[53:54], v[7:8], 0.5
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[3:4]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[3:4]
	v_cmp_ngt_f64_e64 s8, 0xc090cc00, v[1:2]
	v_rndne_f64_e32 v[15:16], v[15:16]
	v_rndne_f64_e32 v[17:18], v[17:18]
	v_mul_f64 v[37:38], v[27:28], 0.5
	v_mul_f64 v[41:42], v[29:30], 0.5
	v_mul_f64 v[49:50], v[9:10], -v[27:28]
	v_mul_f64 v[55:56], v[5:6], -v[29:30]
	v_fma_f64 v[19:20], v[15:16], s[4:5], v[3:4]
	v_fma_f64 v[21:22], v[17:18], s[4:5], v[1:2]
	s_mov_b32 s4, 0x3b39803f
	s_mov_b32 s5, 0xbc7abc9e
	v_add_f64 v[43:44], -v[37:38], 1.0
	v_add_f64 v[45:46], -v[41:42], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[15:16], s[4:5], v[19:20]
	v_fma_f64 v[21:22], v[17:18], s[4:5], v[21:22]
	s_mov_b32 s4, 0x6a5dcb37
	s_mov_b32 s5, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[51:52], -v[43:44], 1.0
	v_add_f64 v[57:58], -v[45:46], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[19:20], s[4:5], s[6:7]
	v_fma_f64 v[25:26], v[21:22], s[4:5], s[6:7]
	s_mov_b32 s4, 0x623fde64
	s_mov_b32 s5, 0x3ec71dee
	s_mov_b32 s6, 0x1852b7b0
	s_mov_b32 s7, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[51:52], -v[37:38]
	v_add_f64 v[41:42], v[57:58], -v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[4:5]
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[4:5]
	s_mov_b32 s4, 0x7c89e6b0
	s_mov_b32 s5, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[37:38], v[9:10], -v[11:12], v[37:38]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[4:5]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[4:5]
	s_mov_b32 s4, 0x14761f6e
	s_mov_b32 s5, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[4:5]
	s_mov_b32 s4, 0xb42fdfa7
	s_mov_b32 s5, 0xbe5ae600
	v_fma_f64 v[31:32], v[27:28], s[16:17], s[4:5]
	v_fma_f64 v[33:34], v[29:30], s[16:17], s[4:5]
	s_mov_b32 s4, 0x46cc5e42
	s_mov_b32 s5, 0xbda907db
	s_mov_b32 s16, 0x555502a1
	v_fma_f64 v[35:36], v[27:28], s[4:5], s[20:21]
	v_fma_f64 v[39:40], v[29:30], s[4:5], s[20:21]
	s_mov_b32 s17, 0x3fa55555
	s_mov_b32 s4, 0xa17f65f6
	s_mov_b32 s5, 0xbe927e4f
	s_mov_b32 s20, 0x55555511
	s_mov_b32 s21, 0x3fc55555
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[6:7]
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[6:7]
	s_mov_b32 s6, 0x796cde01
	s_mov_b32 s7, 0x3ec71de3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[6:7]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[6:7]
	s_mov_b32 s6, 0x19e83e5c
	s_mov_b32 s7, 0xbf2a01a0
	v_fma_f64 v[35:36], v[27:28], v[35:36], s[4:5]
	v_fma_f64 v[39:40], v[29:30], v[39:40], s[4:5]
	s_mov_b32 s4, 11
	s_mov_b32 s5, 0x3fe00000
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[18:19]
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[18:19]
	s_mov_b32 s18, 0x11110bb3
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[6:7]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[6:7]
	s_mov_b32 s6, 0x16c16967
	s_mov_b32 s7, 0xbf56c16c
	v_fma_f64 v[35:36], v[27:28], v[35:36], s[22:23]
	v_fma_f64 v[39:40], v[29:30], v[39:40], s[22:23]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[16:17]
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[16:17]
	s_mov_b32 s16, 0x55555555
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[18:19]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[18:19]
	v_fma_f64 v[35:36], v[27:28], v[35:36], s[6:7]
	v_fma_f64 v[39:40], v[29:30], v[39:40], s[6:7]
	v_cmp_nlt_f64_e64 s7, 0x40900000, v[1:2]
	v_cmp_class_f64_e64 s6, v[1:2], 0x1f8
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[20:21]
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[20:21]
	v_fma_f64 v[31:32], v[49:50], v[31:32], v[47:48]
	v_fma_f64 v[33:34], v[55:56], v[33:34], v[53:54]
	v_mul_f64 v[47:48], v[27:28], v[27:28]
	v_fma_f64 v[35:36], v[27:28], v[35:36], s[16:17]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[4:5]
	v_fma_f64 v[25:26], v[21:22], v[25:26], s[4:5]
	v_cmp_class_f64_e64 s5, v[3:4], 0x1f8
	v_fma_f64 v[11:12], v[27:28], v[31:32], -v[11:12]
	v_mul_f64 v[27:28], v[29:30], v[29:30]
	v_fma_f64 v[31:32], v[29:30], v[39:40], s[16:17]
	v_fma_f64 v[39:40], v[5:6], -v[7:8], v[41:42]
	v_fma_f64 v[7:8], v[29:30], v[33:34], -v[7:8]
	v_cvt_i32_f64_e32 v29, v[15:16]
	s_mov_b32 s17, 0xbfc55555
	v_fma_f64 v[23:24], v[19:20], v[23:24], 1.0
	v_fma_f64 v[25:26], v[21:22], v[25:26], 1.0
	v_fma_f64 v[11:12], v[49:50], s[16:17], v[11:12]
	v_fma_f64 v[7:8], v[55:56], s[16:17], v[7:8]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[15:16], v[19:20], v[23:24], 1.0
	v_fma_f64 v[19:20], v[47:48], v[35:36], v[37:38]
	v_fma_f64 v[23:24], v[27:28], v[31:32], v[39:40]
	v_cvt_i32_f64_e32 v27, v[17:18]
	v_fma_f64 v[17:18], v[21:22], v[25:26], 1.0
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_ldexp_f64 v[15:16], v[15:16], v29
	v_add_f64 v[19:20], v[43:44], v[19:20]
	v_add_f64 v[11:12], v[45:46], v[23:24]
	v_and_b32_e32 v21, 1, v14
	v_ldexp_f64 v[7:8], v[17:18], v27
	v_dual_cndmask_b32 v16, 0x7ff00000, v16 :: v_dual_and_b32 v17, 1, v13
	s_and_b32 vcc_lo, s3, vcc_lo
	v_dual_cndmask_b32 v15, 0, v15 :: v_dual_lshlrev_b32 v14, 30, v14
	v_cmp_eq_u32_e64 s4, 0, v21
	s_and_b32 vcc_lo, s8, s7
	v_cndmask_b32_e64 v16, 0, v16, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, 0xffff, s14
	v_cndmask_b32_e64 v9, v19, v9, s4
	v_cndmask_b32_e64 v10, v20, v10, s4
	v_cmp_eq_u32_e64 s4, 0, v17
	v_and_b32_e32 v14, 0x80000000, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, 0, v9, s5
	v_cndmask_b32_e64 v11, v11, v5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v10, v14
	v_cndmask_b32_e64 v14, 0x7ff00000, v8, s7
	v_cndmask_b32_e64 v6, v12, v6, s4
	v_cndmask_b32_e64 v10, 0x7ff80000, v5, s5
	v_lshlrev_b32_e32 v5, 30, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[8:9], v[15:16], v[9:10]
	v_xor_b32_e32 v5, v5, v2
	v_cndmask_b32_e64 v10, 0, v11, s6
	v_mov_b32_e32 v15, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 0x80000000, v5
	v_xor_b32_e32 v12, v6, v5
	v_cndmask_b32_e32 v5, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, v14, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, 0x7ff80000, v12, s6
	v_fma_f64 v[5:6], v[5:6], v[10:11], v[8:9]
	scratch_store_b64 off, v[5:6], off offset:16
.LBB0_15:                               ; %Flow175
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_f64 v[3:4], v[3:4], -v[1:2]
	s_add_i32 s74, s11, -1
	s_mov_b32 s76, exec_lo
	s_lshl_b32 s75, 1, s74
	v_cmpx_gt_i32_e64 s75, v15
	s_cbranch_execz .LBB0_22
; %bb.16:                               ; %.lr.ph103
	v_cvt_f64_i32_e32 v[5:6], s75
	s_load_b32 s3, s[12:13], 0xc
	v_sub_nc_u32_e32 v16, 0, v15
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s18, 0x6dc9c883
	s_mov_b32 s20, 0x33145c00
	s_mov_b32 s22, 0x252049c0
	s_mov_b32 s24, 0x652b82fe
	s_mov_b32 s26, 0xfefa39ef
	s_mov_b32 s28, 0x3b39803f
	s_mov_b32 s30, 0xfca7ab0c
	s_mov_b32 s34, 0x6a5dcb37
	s_mov_b32 s36, 0x623fde64
	s_mov_b32 s38, 0x7c89e6b0
	s_mov_b32 s40, 0x14761f6e
	s_mov_b32 s42, 0x1852b7b0
	s_mov_b32 s44, 0x11122322
	s_mov_b32 s46, 0x555502a1
	s_mov_b32 s48, 0x55555511
	s_mov_b32 s50, 11
	s_mov_b32 s52, 0x9037ab78
	s_mov_b32 s54, 0x46cc5e42
	s_mov_b32 s56, 0xa17f65f6
	s_mov_b32 s58, 0x19f4ec90
	s_mov_b32 s60, 0x16c16967
	s_mov_b32 s62, 0xb42fdfa7
	s_mov_b32 s64, 0xf9a43bb8
	s_mov_b32 s66, 0x796cde01
	s_mov_b32 s68, 0x19e83e5c
	s_mov_b32 s77, 0
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s9, 0xbff921fb
	s_mov_b32 s15, 0x3c91a626
	s_mov_b32 s16, 0x33145c07
	s_mov_b32 s19, 0x3fe45f30
	s_mov_b32 s21, 0xbc91a626
	s_mov_b32 s23, 0xb97b839a
	s_mov_b32 s25, 0x3ff71547
	v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
	v_div_scale_f64 v[13:14], vcc_lo, v[3:4], v[5:6], v[3:4]
	s_mov_b32 s27, 0xbfe62e42
	s_mov_b32 s29, 0xbc7abc9e
	s_mov_b32 s31, 0x3e928af3
	s_mov_b32 s35, 0x3e5ade15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s78, s3, 0xffff
	s_mov_b32 s37, 0x3ec71dee
	s_mov_b32 s39, 0x3efa0199
	s_mov_b32 s41, 0x3f2a01a0
	s_mov_b32 s43, 0x3f56c16c
	s_mov_b32 s45, 0x3f811111
	s_mov_b32 s47, 0x3fa55555
	s_mov_b32 s49, 0x3fc55555
	s_mov_b32 s51, 0x3fe00000
	s_mov_b32 s53, 0x3e21eeb6
	s_mov_b32 s55, 0xbda907db
	s_mov_b32 s57, 0xbe927e4f
	s_mov_b32 s59, 0x3efa01a0
	s_mov_b32 s61, 0xbf56c16c
	s_mov_b32 s63, 0xbe5ae600
	s_mov_b32 s65, 0x3de5e0b2
	s_mov_b32 s67, 0x3ec71de3
	s_mov_b32 s69, 0xbf2a01a0
	s_mov_b32 s70, 0x55555555
	s_mov_b32 s72, 0x11110bb3
	s_mov_b32 s79, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
	v_div_fixup_f64 v[5:6], v[7:8], v[5:6], v[3:4]
	v_mov_b32_e32 v7, 0
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	v_cvt_f64_i32_e32 v[8:9], v15
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr13_vgpr14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[5:6], v[8:9], v[1:2]
	v_cmpx_ngt_f64_e64 0x41d00000, |v[9:10]|
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	v_ldexp_f64 v[11:12], |v[9:10]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[9:10]|
	v_trig_preop_f64 v[13:14], |v[9:10]|, 0
	v_and_b32_e32 v8, 0x7fffffff, v10
	v_trig_preop_f64 v[17:18], |v[9:10]|, 1
	v_trig_preop_f64 v[27:28], |v[9:10]|, 2
	s_mov_b32 s6, s8
	s_mov_b32 s17, s15
	v_dual_cndmask_b32 v11, v9, v11 :: v_dual_cndmask_b32 v12, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[19:20], v[13:14], v[11:12]
	v_mul_f64 v[21:22], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[11:12], -v[19:20]
	v_fma_f64 v[17:18], v[17:18], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[21:22], v[13:14]
	v_add_f64 v[25:26], v[23:24], -v[21:22]
	v_add_f64 v[31:32], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[23:24], -v[25:26]
	v_add_f64 v[13:14], v[13:14], -v[25:26]
	v_ldexp_f64 v[25:26], v[31:32], -2
	v_add_f64 v[19:20], v[31:32], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[21:22], -v[29:30]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[23:24], -v[19:20]
	v_add_f64 v[13:14], v[13:14], v[21:22]
	v_fract_f64_e32 v[21:22], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0, v21, vcc_lo
	v_mul_f64 v[33:34], v[27:28], v[11:12]
	v_cndmask_b32_e32 v22, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[21:22], v[21:22], 2
	v_add_f64 v[29:30], v[33:34], v[17:18]
	v_fma_f64 v[11:12], v[27:28], v[11:12], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[29:30], v[13:14]
	v_add_f64 v[25:26], v[19:20], v[23:24]
	v_add_f64 v[35:36], v[23:24], -v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[25:26], v[21:22]
	v_add_f64 v[41:42], v[23:24], -v[35:36]
	v_add_f64 v[13:14], v[13:14], -v[35:36]
	v_add_f64 v[19:20], v[25:26], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[31:32]
	v_add_f64 v[31:32], v[29:30], -v[33:34]
	v_cndmask_b32_e64 v8, 0, 0x40100000, vcc_lo
	v_add_f64 v[39:40], v[29:30], -v[31:32]
	v_add_f64 v[17:18], v[17:18], -v[31:32]
	v_add_f64 v[29:30], v[29:30], -v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], v[7:8]
	v_add_f64 v[31:32], v[33:34], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], v[29:30]
	v_add_f64 v[37:38], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], v[31:32]
	v_cvt_i32_f64_e32 v8, v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[17:18], v[13:14]
	v_add_f64 v[17:18], v[23:24], -v[19:20]
	v_cvt_f64_i32_e32 v[35:36], v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[21:22], v[21:22], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[17:18], v[11:12]
	v_add_f64 v[27:28], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[27:28], -v[21:22]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[27:28]
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	v_add_co_ci_u32_e64 v17, s3, 0, v8, vcc_lo
	v_cndmask_b32_e64 v8, 0, 0x3ff00000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[27:28], -v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[13:14], v[11:12]
	v_mul_f64 v[20:21], v[18:19], s[6:7]
	v_add_f64 v[13:14], v[18:19], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[18:19], s[6:7], -v[20:21]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[18:19], s[16:17], v[22:23]
	v_fma_f64 v[13:14], v[11:12], s[6:7], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[20:21], v[13:14]
	v_add_f64 v[18:19], v[11:12], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[18:19]
.LBB0_19:                               ; %Flow170
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_and_not1_saveexec_b32 s3, s4
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	v_mul_f64 v[11:12], |v[9:10]|, s[18:19]
	s_mov_b32 s14, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[17:18], v[11:12]
	v_fma_f64 v[11:12], v[17:18], s[8:9], |v[9:10]|
	v_mul_f64 v[13:14], v[17:18], s[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], s[20:21], v[11:12]
	v_add_f64 v[19:20], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	v_add_f64 v[19:20], v[19:20], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_fma_f64 v[13:14], v[17:18], s[14:15], v[13:14]
	v_add_f64 v[11:12], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_fma_f64 v[13:14], v[17:18], s[22:23], v[11:12]
	v_cvt_i32_f64_e32 v17, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[21:22], v[13:14]
	v_add_f64 v[19:20], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[19:20]
.LBB0_21:                               ; %_Z1fd.exit95
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mul_f64 v[18:19], v[9:10], s[24:25]
	v_mul_f64 v[24:25], v[11:12], v[11:12]
	v_and_b32_e32 v8, v15, v16
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[9:10]
	v_cmp_class_f64_e64 s5, v[9:10], 0x1f8
	s_mov_b32 s73, s45
	v_mul_f64 v[36:37], v[13:14], 0.5
	v_cvt_f32_i32_e32 v8, v8
	s_mov_b32 s71, s47
	v_subrev_nc_u32_e32 v16, s78, v16
	v_add_nc_u32_e32 v15, s78, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v8
	v_cndmask_b32_e64 v28, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v32, 0, 0x42000000, vcc_lo
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[9:10]
	v_mul_f32_e32 v8, v8, v28
	v_rndne_f64_e32 v[18:19], v[18:19]
	v_fma_f64 v[26:27], v[24:25], s[64:65], s[62:63]
	v_fma_f64 v[28:29], v[24:25], s[54:55], s[52:53]
	v_mul_f64 v[30:31], v[24:25], 0.5
	v_mul_f64 v[38:39], v[11:12], -v[24:25]
	v_fma_f64 v[20:21], v[18:19], s[26:27], v[9:10]
	v_lshlrev_b32_e32 v9, 30, v17
	v_log_f32_e32 v8, v8
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[66:67]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[56:57]
	v_add_f64 v[34:35], -v[30:31], 1.0
	v_xor_b32_e32 v9, v9, v10
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v8, v8, v32 :: v_dual_and_b32 v9, 0x80000000, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, 1.0, v8
	v_cvt_u32_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, s11, v8
	v_lshl_add_u32 v42, v8, 3, 16
	v_cvt_i32_f64_e32 v8, v[18:19]
	scratch_load_b64 v[32:33], v42, off
	v_fma_f64 v[20:21], v[18:19], s[28:29], v[20:21]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[68:69]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[58:59]
	v_add_f64 v[40:41], -v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[20:21], s[34:35], s[30:31]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[72:73]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[60:61]
	v_add_f64 v[30:31], v[40:41], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[36:37]
	v_fma_f64 v[26:27], v[38:39], v[26:27], v[36:37]
	v_mul_f64 v[36:37], v[24:25], v[24:25]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[70:71]
	v_fma_f64 v[30:31], v[11:12], -v[13:14], v[30:31]
	s_mov_b32 s71, s79
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[38:39]
	v_fma_f64 v[13:14], v[24:25], v[26:27], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[40:41]
	v_fma_f64 v[13:14], v[38:39], s[70:71], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[42:43]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[44:45]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[48:49]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
	v_fma_f64 v[18:19], v[20:21], v[22:23], 1.0
	v_fma_f64 v[20:21], v[36:37], v[28:29], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[18:19], v[18:19], v8
	v_add_f64 v[20:21], v[34:35], v[20:21]
	v_and_b32_e32 v8, 1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s4, 0, v8
	v_cndmask_b32_e32 v13, 0x7ff00000, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v21, v12, s4
	v_cndmask_b32_e64 v8, v20, v11, s4
	s_and_b32 vcc_lo, s3, vcc_lo
	v_cndmask_b32_e64 v11, 0, v13, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v10, v9
	v_cndmask_b32_e64 v8, 0, v8, s5
	v_cndmask_b32_e32 v10, 0, v18, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s75, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0x7ff80000, v9, s5
	s_or_b32 s77, vcc_lo, s77
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], 2.0, v[32:33]
	scratch_store_b64 v42, v[8:9], off
	s_and_not1_b32 exec_lo, exec_lo, s77
	s_cbranch_execnz .LBB0_17
.LBB0_22:                               ; %Flow172
	s_or_b32 exec_lo, exec_lo, s76
	v_cndmask_b32_e64 v5, 0, 1, s33
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB0_25
; %bb.23:                               ; %.lr.ph105
	v_mul_lo_u32 v1, v0, s11
	v_mov_b32_e32 v2, 16
	s_mov_b32 s3, s11
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v1, v1, 3, 0
.LBB0_24:                               ; =>This Inner Loop Header: Depth=1
	scratch_load_b64 v[6:7], v2, off
	v_add_nc_u32_e32 v2, 8, v2
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 0
	s_waitcnt vmcnt(0)
	ds_store_b64 v1, v[6:7]
	v_add_nc_u32_e32 v1, 8, v1
	s_cbranch_scc0 .LBB0_24
.LBB0_25:                               ; %._crit_edge106
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e64 s11, v0
	s_cbranch_execz .LBB0_31
; %bb.26:                               ; %.preheader98
	s_load_b32 s4, s[12:13], 0xc
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v6, v0, 3, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s4, s11
	v_cmpx_gt_u32_e64 s4, v0
	s_cbranch_execz .LBB0_30
; %bb.27:                               ; %.lr.ph109.preheader
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v7, v6
	s_mov_b32 s6, 0
	s_lshl_b32 s7, s11, 3
.LBB0_28:                               ; %.lr.ph109
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[8:9], v7
	v_add_nc_u32_e32 v0, s11, v0
	v_add_nc_u32_e32 v7, s7, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	s_or_b32 s6, vcc_lo, s6
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_28
; %bb.29:                               ; %Flow165
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_30:                               ; %Flow166
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	ds_store_b64 v6, v[1:2]
.LBB0_31:                               ; %Flow167
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_44
; %bb.32:
	v_mov_b32_e32 v0, 0
	s_cmp_gt_i32 s11, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lt_i32 s11, 2
	ds_load_b64 v[0:1], v0
	s_waitcnt lgkmcnt(0)
	scratch_store_b64 off, v[0:1], off offset:16
	s_cbranch_scc1 .LBB0_35
; %bb.33:                               ; %.lr.ph113.preheader
	v_or_b32_e64 v0, 16, 8
	s_add_i32 s3, 0, 8
	s_mov_b32 s4, s74
.LBB0_34:                               ; %.lr.ph113
                                        ; =>This Inner Loop Header: Depth=1
	scratch_load_b64 v[1:2], v0, off offset:-8
	v_mov_b32_e32 v6, s3
	s_add_i32 s4, s4, -1
	s_add_i32 s3, s3, 8
	s_cmp_eq_u32 s4, 0
	ds_load_b64 v[6:7], v6
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	scratch_store_b64 v0, v[1:2], off
	v_add_nc_u32_e32 v0, 8, v0
	s_cbranch_scc0 .LBB0_34
.LBB0_35:                               ; %.preheader97
	v_cmp_ne_u32_e32 vcc_lo, 1, v5
	s_cbranch_vccnz .LBB0_38
; %bb.36:                               ; %.lr.ph115.preheader
	v_mov_b32_e32 v0, 16
	s_mov_b32 s3, 0
.LBB0_37:                               ; %.lr.ph115
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s4, 2, s3
	scratch_load_b64 v[9:10], v0, off
	v_cvt_f64_i32_e32 v[1:2], s4
	s_add_i32 s3, s3, 1
	s_cmp_eq_u32 s11, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], v[3:4]
	v_div_scale_f64 v[13:14], vcc_lo, v[3:4], v[1:2], v[3:4]
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
	v_fma_f64 v[11:12], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
	v_mul_f64 v[11:12], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], -v[5:6], v[11:12], v[13:14]
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[1:2], v[5:6], v[1:2], v[3:4]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[1:2], v[1:2], v[9:10]
	scratch_store_b64 v0, v[1:2], off
	v_add_nc_u32_e32 v0, 8, v0
	s_cbranch_scc0 .LBB0_37
.LBB0_38:                               ; %.preheader96
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_43
; %bb.39:                               ; %.preheader.preheader
	s_lshl_b32 s2, s11, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e64 v0, s2, 16
	s_mov_b32 s2, 0
	v_add_nc_u32_e32 v2, -8, v0
.LBB0_40:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_41 Depth 2
	s_lshl_b32 s3, s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v3, v2
	s_or_b32 s3, s3, 1
	s_lshl_b32 s3, -1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b32 s3, s3
	v_cvt_f64_i32_e32 v[0:1], s3
	s_mov_b32 s3, s74
.LBB0_41:                               ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b128 v[4:7], v3, off offset:-8
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_le_i32 s3, s2
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[6:7], -v[4:5]
	v_div_scale_f64 v[8:9], null, v[0:1], v[0:1], v[4:5]
	v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
	v_div_fixup_f64 v[4:5], v[8:9], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_nc_u32_e32 v6, -8, v3
	scratch_store_b64 v3, v[4:5], off
	v_mov_b32_e32 v3, v6
	s_cbranch_scc0 .LBB0_41
; %bb.42:                               ;   in Loop: Header=BB0_40 Depth=1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s74
	s_cbranch_scc0 .LBB0_40
.LBB0_43:                               ; %._crit_edge118
	s_lshl_b32 s2, s11, 3
	s_load_b64 s[0:1], s[0:1], 0x18
	s_add_i32 s2, s2, 16
	s_mov_b32 s11, 0
	scratch_load_b64 v[0:1], off, s2 offset:-8
	s_lshl_b64 s[2:3], s[10:11], 3
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_waitcnt vmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB0_44:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7rombergddiPd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 224
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 59
		.amdhsa_next_free_sgpr 80
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7rombergddiPd, .Lfunc_end0-_Z7rombergddiPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6680
; NumSgprs: 82
; NumVgprs: 59
; ScratchSize: 224
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 82
; NumVGPRsForWavesPerEU: 59
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7rombergddiPd
    .private_segment_fixed_size: 224
    .sgpr_count:     82
    .sgpr_spill_count: 0
    .symbol:         _Z7rombergddiPd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     59
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
