#include "includes.h"
__device__ void sort(unsigned char* filterVector)
{
for (int i = 0; i < FILTER_WIDTH*FILTER_HEIGHT; i++) {
for (int j = i + 1; j < FILTER_WIDTH*FILTER_HEIGHT; j++) {
if (filterVector[i] > filterVector[j]) {
//Swap the variables
unsigned char tmp = filterVector[i];
filterVector[i] = filterVector[j];
filterVector[j] = tmp;
}
}
}
}
__global__ void medianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;

// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
unsigned char filterVector[FILTER_WIDTH*FILTER_HEIGHT];
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
filterVector[ky*FILTER_WIDTH+kx] = srcImage[((y+ky)*width + (x+kx))*channel+c];
}
}
// Sorting values of filter
sort(filterVector);
dstImage[(y*width+x)*channel+c] =  filterVector[(FILTER_WIDTH*FILTER_HEIGHT)/2];
}
}
}
	.file	"tmpxft_0036f354_00000000-6_medianFilter.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4sortPh
	.type	_Z4sortPh, @function
_Z4sortPh:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z4sortPh, .-_Z4sortPh
	.globl	_Z37__device_stub__Z12medianFilterPhS_jjiPhS_jji
	.type	_Z37__device_stub__Z12medianFilterPhS_jjiPhS_jji, @function
_Z37__device_stub__Z12medianFilterPhS_jjiPhS_jji:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12medianFilterPhS_jji(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z37__device_stub__Z12medianFilterPhS_jjiPhS_jji, .-_Z37__device_stub__Z12medianFilterPhS_jjiPhS_jji
	.globl	_Z12medianFilterPhS_jji
	.type	_Z12medianFilterPhS_jji, @function
_Z12medianFilterPhS_jji:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12medianFilterPhS_jjiPhS_jji
	.cfi_endproc
.LFE2034:
	.size	_Z12medianFilterPhS_jji, .-_Z12medianFilterPhS_jji
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12medianFilterPhS_jji"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12medianFilterPhS_jji(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ void sort(unsigned char* filterVector)
{
for (int i = 0; i < FILTER_WIDTH*FILTER_HEIGHT; i++) {
for (int j = i + 1; j < FILTER_WIDTH*FILTER_HEIGHT; j++) {
if (filterVector[i] > filterVector[j]) {
//Swap the variables
unsigned char tmp = filterVector[i];
filterVector[i] = filterVector[j];
filterVector[j] = tmp;
}
}
}
}
__global__ void medianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;

// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
unsigned char filterVector[FILTER_WIDTH*FILTER_HEIGHT];
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
filterVector[ky*FILTER_WIDTH+kx] = srcImage[((y+ky)*width + (x+kx))*channel+c];
}
}
// Sorting values of filter
sort(filterVector);
dstImage[(y*width+x)*channel+c] =  filterVector[(FILTER_WIDTH*FILTER_HEIGHT)/2];
}
}
}
	.text
	.file	"medianFilter.hip"
	.globl	_Z27__device_stub__medianFilterPhS_jji # -- Begin function _Z27__device_stub__medianFilterPhS_jji
	.type	_Z27__device_stub__medianFilterPhS_jji,@function
_Z27__device_stub__medianFilterPhS_jji: # @_Z27__device_stub__medianFilterPhS_jji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12medianFilterPhS_jji, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__medianFilterPhS_jji, .Lfunc_end0-_Z27__device_stub__medianFilterPhS_jji
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12medianFilterPhS_jji, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12medianFilterPhS_jji,@object # @_Z12medianFilterPhS_jji
	.section	.rodata,"a",@progbits
	.globl	_Z12medianFilterPhS_jji
	.p2align	3, 0x0
_Z12medianFilterPhS_jji:
	.quad	_Z27__device_stub__medianFilterPhS_jji
	.size	_Z12medianFilterPhS_jji, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12medianFilterPhS_jji"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__medianFilterPhS_jji
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12medianFilterPhS_jji
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12medianFilterPhS_jji ; -- Begin function _Z12medianFilterPhS_jji
	.globl	_Z12medianFilterPhS_jji
	.p2align	8
	.type	_Z12medianFilterPhS_jji,@function
_Z12medianFilterPhS_jji:                ; @_Z12medianFilterPhS_jji
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s14, s14, s3
	s_mov_b32 s3, exec_lo
	v_add_nc_u32_e32 v2, s14, v1
	v_cmpx_lt_i32_e32 0, v2
	s_cbranch_execz .LBB0_13
; %bb.1:
	s_load_b128 s[16:19], s[0:1], 0x10
	v_bfe_u32 v0, v0, 10, 10
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s16, -1
	s_add_i32 s3, s17, -1
	v_cmp_gt_u32_e32 vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e64 s2, s3, v3
	v_cmp_lt_i32_e64 s3, 0, v3
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_cmp_gt_i32 s18, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_13
; %bb.2:                                ; %.preheader47.lr.ph
	v_add_nc_u32_e32 v0, -1, v3
	s_load_b128 s[20:23], s[0:1], 0x0
	s_mul_i32 s19, s18, s16
	s_mov_b32 s26, 0
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s16, v0, v[1:2]
	v_mad_u64_u32 v[0:1], null, v3, s16, v[2:3]
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr2
	v_add3_u32 v1, v4, s14, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v0, s18
                                        ; implicit-def: $vgpr0
	v_mul_lo_u32 v5, s18, v1
.LBB0_3:                                ; %.preheader47
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;     Child Loop BB0_8 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v11, v5
	s_mov_b32 s12, -1
	s_mov_b64 s[8:9], 0
.LBB0_4:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v12, v11
	s_mov_b64 s[10:11], -4
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt lgkmcnt(0)
	global_load_u8 v13, v12, s[20:21]
	s_add_i32 s7, s8, s10
	v_add_nc_u32_e32 v12, s18, v12
	s_cmp_eq_u32 s7, 3
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s7, 2
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s7, 1
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s7, 0
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s7, 4
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s7, 5
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s7, 6
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s7, 7
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s7, 8
	s_cselect_b32 s7, -1, 0
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s10, -1
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v2, v2, v13, vcc_lo
	v_cndmask_b32_e64 v6, v6, v13, s0
	v_cndmask_b32_e64 v3, v3, v13, s1
	v_cndmask_b32_e64 v0, v0, v13, s2
	v_cndmask_b32_e64 v1, v1, v13, s3
	v_cndmask_b32_e64 v7, v7, v13, s4
	v_cndmask_b32_e64 v9, v9, v13, s5
	v_cndmask_b32_e64 v8, v8, v13, s6
	v_cndmask_b32_e64 v10, v10, v13, s7
	s_cbranch_scc0 .LBB0_5
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s12, s12, 1
	v_add_nc_u32_e32 v11, s19, v11
	s_add_u32 s8, s8, 3
	s_addc_u32 s9, s9, 0
	s_cmp_lg_u32 s12, 2
	s_cbranch_scc1 .LBB0_4
; %bb.7:                                ; %.preheader46.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s27, 0
	s_mov_b64 s[16:17], 1
.LBB0_8:                                ; %.preheader46
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	s_cmp_gt_u32 s27, 7
	s_cbranch_scc1 .LBB0_11
; %bb.9:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_mov_b64 s[24:25], s[16:17]
.LBB0_10:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_8 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_cmp_eq_u32 s27, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b16 v12, 8, v3
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s27, 2
	v_dual_cndmask_b32 v20, v0, v3 :: v_dual_and_b32 v11, 0xff, v0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s27, 3
	v_and_b32_e32 v13, 0xff, v6
	v_lshlrev_b16 v14, 8, v2
	v_lshlrev_b16 v16, 8, v7
	v_and_b32_e32 v17, 0xff, v9
	v_lshlrev_b16 v18, 8, v8
	v_and_b32_e32 v19, 0xff, v10
	v_and_b32_e32 v15, 0xff, v1
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s27, 4
	v_or_b32_e32 v11, v11, v12
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s27, 5
	v_or_b32_e32 v12, v13, v14
	v_or_b32_e32 v13, v15, v16
	v_or_b32_e32 v14, v17, v18
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s27, 6
	v_and_b32_e32 v11, 0xffff, v11
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s27, 7
	v_lshlrev_b32_e32 v12, 16, v12
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s27, 8
	v_and_b32_e32 v13, 0xffff, v13
	v_lshlrev_b32_e32 v14, 16, v14
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s24, 1
	v_or_b32_e32 v11, v11, v12
	s_cselect_b32 s7, -1, 0
	v_or_b32_e32 v12, v13, v14
	v_cndmask_b32_e64 v14, v0, v3, s7
	s_cmp_eq_u32 s24, 2
	v_cndmask_b32_e64 v15, v20, v6, s0
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s24, 3
	v_cndmask_b32_e64 v14, v14, v6, s8
	s_cselect_b32 s9, -1, 0
	s_cmp_eq_u32 s24, 4
	v_cndmask_b32_e64 v15, v15, v2, s1
	s_cselect_b32 s10, -1, 0
	v_cndmask_b32_e64 v14, v14, v2, s9
	s_cmp_eq_u32 s24, 5
	s_cselect_b32 s11, -1, 0
	v_cndmask_b32_e64 v13, v15, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v1, s10
	s_cmp_eq_u32 s24, 6
	s_cselect_b32 s12, -1, 0
	v_cndmask_b32_e64 v13, v13, v7, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v7, s11
	s_cmp_eq_u32 s24, 7
	s_cselect_b32 s13, -1, 0
	v_cndmask_b32_e64 v13, v13, v9, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v9, s12
	s_cmp_eq_u32 s24, 8
	s_cselect_b32 s14, -1, 0
	v_cndmask_b32_e64 v13, v13, v8, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v8, s13
	s_cmp_eq_u32 s27, 0
	s_cselect_b32 s15, -1, 0
	v_cndmask_b32_e64 v13, v13, v10, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v10, s14
	s_cmp_eq_u32 s24, 0
	v_and_b32_e32 v15, 0xff, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v9, v14, s4
	v_cndmask_b32_e64 v8, v8, v14, s5
	v_cndmask_b32_e64 v1, v1, v14, s2
	v_cndmask_b32_e64 v7, v7, v14, s3
	v_cndmask_b32_e64 v6, v6, v14, s0
	v_cndmask_b32_e32 v3, v3, v14, vcc_lo
	v_cndmask_b32_e64 v0, v0, v14, s15
	v_cndmask_b32_e64 v2, v2, v14, s1
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e64 v6, v6, v13, s8
	v_cndmask_b32_e64 v3, v3, v13, s7
	v_cndmask_b32_e32 v0, v0, v13, vcc_lo
	v_cndmask_b32_e64 v2, v2, v13, s9
	v_cndmask_b32_e64 v7, v7, v13, s11
	v_cndmask_b32_e64 v1, v1, v13, s10
	v_cndmask_b32_e64 v8, v8, v13, s13
	v_cndmask_b32_e64 v9, v9, v13, s12
	v_lshlrev_b16 v3, 8, v3
	v_and_b32_e32 v0, 0xff, v0
	v_lshlrev_b16 v2, 8, v2
	v_and_b32_e32 v6, 0xff, v6
	v_lshlrev_b16 v7, 8, v7
	v_and_b32_e32 v1, 0xff, v1
	v_lshlrev_b16 v8, 8, v8
	v_and_b32_e32 v9, 0xff, v9
	v_or_b32_e32 v0, v0, v3
	v_or_b32_e32 v2, v6, v2
	v_or_b32_e32 v1, v1, v7
	v_and_b32_e32 v16, 0xff, v14
	v_or_b32_e32 v3, v9, v8
	v_and_b32_e32 v0, 0xffff, v0
	v_lshlrev_b32_e32 v2, 16, v2
	v_and_b32_e32 v1, 0xffff, v1
	v_cndmask_b32_e64 v10, v10, v14, s6
	v_lshlrev_b32_e32 v3, 16, v3
	v_cmp_gt_u16_e32 vcc_lo, v15, v16
	v_or_b32_e32 v0, v0, v2
	s_add_u32 s0, s24, 1
	v_cndmask_b32_e64 v10, v10, v13, s14
	v_or_b32_e32 v1, v1, v3
	s_addc_u32 s1, s25, 0
	v_cndmask_b32_e32 v0, v11, v0, vcc_lo
	s_cmp_gt_u32 s24, 7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v12, v1 :: v_dual_and_b32 v10, 0xff, v10
	s_mov_b64 s[24:25], s[0:1]
	v_lshrrev_b32_e32 v6, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v19, v10, vcc_lo
	v_lshrrev_b64 v[2:3], 24, v[0:1]
	v_lshrrev_b32_e32 v8, 24, v1
	v_lshrrev_b32_e32 v9, 16, v1
	v_lshrrev_b32_e32 v7, 8, v1
	v_lshrrev_b32_e32 v3, 8, v0
	s_cbranch_scc0 .LBB0_10
.LBB0_11:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_add_i32 s27, s27, 1
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_eq_u32 s27, 9
	s_cbranch_scc0 .LBB0_8
; %bb.12:                               ; %_Z4sortPh.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v11, s26, v4
	v_add_nc_u32_e32 v5, 1, v5
	s_add_i32 s26, s26, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s26, s18
	global_store_b8 v11, v1, s[22:23]
	s_cbranch_scc0 .LBB0_3
.LBB0_13:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12medianFilterPhS_jji
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12medianFilterPhS_jji, .Lfunc_end0-_Z12medianFilterPhS_jji
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1300
; NumSgprs: 30
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12medianFilterPhS_jji
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z12medianFilterPhS_jji.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
