#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>

using namespace std;
#define D_CHECK(err){\
    if(err !=cudaSuccess)\
        printf("error %s,at %d\n",cudaGetErrorString(err),__LINE__);    \
}

//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752

__global__ void g_rand_init(int size,curandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,curandState *states);
__global__ void g_S_init(int *S,int size,curandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag);


template <typename T>
class ising{
public:
    // host values
    int row;
    int col;
    int size;
    T J;
    // 交換相互作用エネルギー
    int block_x,block_y;
    int thread_x,thread_y;
    dim3 grid,block;
    int nthreads;
    int sumE;
    float invT;
    FILE *fp;
    
    T *S;
    // スピンの情報

    T *E;
    // 各スピンのエネルギー

    T *hE;
    // エネルギー計算用
    
    // device values
    cudaError_t err;
    curandState *states;
    //乱数列生成用

    T *dS;
    // デバイス側のスピン

    T *dE;
    // デバイス側の各スピンのエネルギー


    //functions 
    ising(int row_,int col_,T J_,float temperature);
    ~ising();

    void devInit(int bx,int by,int tx,int ty);
    // デバイス側の初期化

    void toFile();
    // ファイルの書き出し

    void checkEnergy();
    // 系のエネルギーのチェック

    void run();
   //シミュレーションのスタート

    void devEnd();
    // デバイスの変数の解放
};

template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
    row = row_;
    col = col_;
    size = row_ * col_;
    J = J_;
    invT = 1.0/temperature_;
    sumE = 0;
    S = (T *) malloc(sizeof(T) * size);
    E = (T *) malloc(sizeof(T) * size);
    hE = (T *) malloc(sizeof(T) * size);
    
    if((fp = fopen("result.dat","w")) == NULL){
        printf("Error at opening file.\n");
        exit(0);
    }
    
    fprintf(fp,"#%9d%9d\n",row,col);
    for(int i=0;i<size;i++)
        S[i] = 0;
}

template <typename T>
ising<T>::~ising(){
    free(S);
    free(E);
    free(hE);
    fclose(fp);
}

template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
    nthreads = bx * by * tx * ty;
    dim3 grid_(bx,by),block_(tx,ty);
    grid = grid_;
    block = block_;

    printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
    cudaMalloc((curandState **)&states,sizeof(curandState)*nthreads);
    cudaMalloc((T **)&dS,sizeof(T)*size);
    cudaMalloc((T **)&dE,sizeof(T)*size);

    g_rand_init<<<grid,block>>>(size,states);
    g_S_init<<<grid,block>>>(dS,size,states);
    D_CHECK(cudaMemcpy(S,dS,sizeof(int)*size,cudaMemcpyDeviceToHost));
}

template <typename T>
void ising<T>::devEnd(){
    cudaFree(states);
    cudaFree(dS);
    cudaFree(dE);
    cudaDeviceReset();
}

__global__ void g_rand_init(int size,curandState *states){
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    int idx = x + y*gridDim.x*blockDim.x;
    if(idx < size){
        curand_init(idx,0,0,&states[idx]);
    }
}

__global__ void g_S_init(int *S,int size,curandState *states){
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    int idx = x + y*gridDim.x*blockDim.x;
    if(idx < size){
        if(curand_uniform(&states[idx]) <= 0.5)
            S[idx] = -1;
        else
            S[idx] = 1;
    }
}


template <typename T>
void ising<T>::run(){
    int flag;
    flag = 0;
    g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
    flag = 1;
    g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}

template <typename T>
void ising<T>::toFile(){
    for(int i=0;i<size;i++)
        fprintf(fp,"%3d",S[i]);
    return;
}

__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag)
{
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    int idx = x + y*gridDim.x*blockDim.x;
    int nx;
    int ny;
    float prob;

    if( x < row && y < col){
        if((x+y)% 2 == flag){
            S[x*col+y] = -S[x*col+y];
            E[x*col+y] = 0;
            nx = x-1;
            ny = y;
            if(nx < 0)
                nx = col-1;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];

            nx = x;
            ny = y-1;
            if(ny < 0)
                ny = row-1;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];

            nx = x+1;
            ny = y;
            if(nx >= row)
                nx = 0;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];

            nx = x;
            ny = y+1;
            if(ny >= col)
                ny = 0;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
            if( E[x*col+y]>=0){
                prob = curand_uniform(&states[idx]);
                if(prob > exp(-2.0*E[x*col+y]*invT)){
                    S[x*col+y] = -S[x*col+y];
                }
            }
        }
    }
    __syncthreads();
}

int main(void){
    int row = ROW;
    int col = COL;
    int J = 1;

    ising<int> ising2d(row,col,J,0.5);
    ising2d.devInit(64,64,32,32);

    ising2d.toFile();

    for(int i=0;i<100;i++){
        ising2d.run();
        //ising2d.checkEnergy();
        //ising2d.toFile();
    }
    ising2d.devEnd();
    return 0;
}


	.file	"tmpxft_00262cec_00000000-6_2d_ising.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3858:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3858:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
	.type	_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW, @function
_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW:
.LFB3880:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11g_rand_initiP17curandStateXORWOW(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3880:
	.size	_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW, .-_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
	.globl	_Z11g_rand_initiP17curandStateXORWOW
	.type	_Z11g_rand_initiP17curandStateXORWOW, @function
_Z11g_rand_initiP17curandStateXORWOW:
.LFB3881:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
	.cfi_endproc
.LFE3881:
	.size	_Z11g_rand_initiP17curandStateXORWOW, .-_Z11g_rand_initiP17curandStateXORWOW
	.globl	_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
	.type	_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW, @function
_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW:
.LFB3882:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8g_S_initPiiP17curandStateXORWOW(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3882:
	.size	_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW, .-_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
	.globl	_Z8g_S_initPiiP17curandStateXORWOW
	.type	_Z8g_S_initPiiP17curandStateXORWOW, @function
_Z8g_S_initPiiP17curandStateXORWOW:
.LFB3883:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
	.cfi_endproc
.LFE3883:
	.size	_Z8g_S_initPiiP17curandStateXORWOW, .-_Z8g_S_initPiiP17curandStateXORWOW
	.globl	_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
	.type	_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi, @function
_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi:
.LFB3884:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10g_simulateifPiS_iiP17curandStateXORWOWi(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L13:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3884:
	.size	_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi, .-_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
	.globl	_Z10g_simulateifPiS_iiP17curandStateXORWOWi
	.type	_Z10g_simulateifPiS_iiP17curandStateXORWOWi, @function
_Z10g_simulateifPiS_iiP17curandStateXORWOWi:
.LFB3885:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
	.cfi_endproc
.LFE3885:
	.size	_Z10g_simulateifPiS_iiP17curandStateXORWOWi, .-_Z10g_simulateifPiS_iiP17curandStateXORWOWi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10g_simulateifPiS_iiP17curandStateXORWOWi"
.LC1:
	.string	"_Z8g_S_initPiiP17curandStateXORWOW"
.LC2:
	.string	"_Z11g_rand_initiP17curandStateXORWOW"
.LC3:
	.string	"precalc_xorwow_matrix"
.LC4:
	.string	"precalc_xorwow_offset_matrix"
.LC5:
	.string	"mrg32k3aM1"
.LC6:
	.string	"mrg32k3aM2"
.LC7:
	.string	"mrg32k3aM1SubSeq"
.LC8:
	.string	"mrg32k3aM2SubSeq"
.LC9:
	.string	"mrg32k3aM1Seq"
.LC10:
	.string	"mrg32k3aM2Seq"
.LC11:
	.string	"__cr_lgamma_table"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3887:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10g_simulateifPiS_iiP17curandStateXORWOWi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8g_S_initPiiP17curandStateXORWOW(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11g_rand_initiP17curandStateXORWOW(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3887:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED5Ev,comdat
	.align 2
	.weak	_ZN5isingIiED2Ev
	.type	_ZN5isingIiED2Ev, @function
_ZN5isingIiED2Ev:
.LFB4191:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4191
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	movq	80(%rdi), %rdi
	call	free@PLT
	movq	88(%rbx), %rdi
	call	free@PLT
	movq	96(%rbx), %rdi
	call	free@PLT
	movq	72(%rbx), %rdi
	call	fclose@PLT
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4191:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table._ZN5isingIiED2Ev,"aG",@progbits,_ZN5isingIiED5Ev,comdat
.LLSDA4191:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4191-.LLSDACSB4191
.LLSDACSB4191:
.LLSDACSE4191:
	.section	.text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED5Ev,comdat
	.size	_ZN5isingIiED2Ev, .-_ZN5isingIiED2Ev
	.weak	_ZN5isingIiED1Ev
	.set	_ZN5isingIiED1Ev,_ZN5isingIiED2Ev
	.section	.rodata.str1.1
.LC12:
	.string	"w"
.LC13:
	.string	"result.dat"
.LC14:
	.string	"Error at opening file.\n"
.LC15:
	.string	"#%9d%9d\n"
.LC16:
	.string	"grid=[%d,%d],block[%d,%d]\n"
.LC17:
	.string	"error %s,at %d\n"
.LC18:
	.string	"%3d"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB3855:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA3855
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%r10d, %r10d
	movl	$462422016, %edi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%rbx
	subq	$152, %rsp
	.cfi_offset 3, -24
	movq	%fs:40, %rax
	movq	%rax, -24(%rbp)
	movabsq	$46179488377344, %rax
	movq	%r10, -104(%rbp)
	movq	$1073741824, -96(%rbp)
	movq	%rax, -160(%rbp)
	movl	$16825, %eax
	salq	$18, %rax
	movq	%rax, -152(%rbp)
	subq	$115605503, %rax
	movq	%rax, -128(%rbp)
	movq	%rax, -120(%rbp)
	movq	%rax, -112(%rbp)
	call	malloc@PLT
	movl	$462422016, %edi
	movq	%rax, -80(%rbp)
	call	malloc@PLT
	movl	$462422016, %edi
	movq	%rax, -72(%rbp)
	call	malloc@PLT
	leaq	.LC12(%rip), %rsi
	leaq	.LC13(%rip), %rdi
	movq	%rax, -64(%rbp)
.LEHB0:
	call	fopen@PLT
	movq	%rax, -88(%rbp)
	testq	%rax, %rax
	jne	.L23
	movl	$2, %edi
	leaq	.LC14(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L23:
	movl	-156(%rbp), %r8d
	movl	-160(%rbp), %ecx
	movq	%rax, %rdi
	leaq	.LC15(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.LEHE0:
	movq	-80(%rbp), %rdx
	xorl	%eax, %eax
.L24:
	cmpl	%eax, -152(%rbp)
	jle	.L42
	xorl	%r9d, %r9d
	movl	%r9d, (%rdx,%rax,4)
	incq	%rax
	jmp	.L24
.L42:
	movl	$32, %r9d
	movl	$32, %r8d
	movabsq	$274877907008, %rax
	movl	$64, %ecx
	movq	%rax, -128(%rbp)
	movl	$64, %edx
	movl	$2, %edi
	movabsq	$137438953473, %rax
	movq	%rax, -120(%rbp)
	movl	$134217729, %eax
	leaq	.LC16(%rip), %rsi
	salq	$5, %rax
	movl	$4194304, -104(%rbp)
	movq	%rax, -112(%rbp)
	xorl	%eax, %eax
.LEHB1:
	call	__printf_chk@PLT
	movslq	-104(%rbp), %rsi
	leaq	-48(%rbp), %rdi
	imulq	$48, %rsi, %rsi
	call	cudaMalloc@PLT
	movslq	-152(%rbp), %rsi
	leaq	-40(%rbp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	-152(%rbp), %rsi
	leaq	-32(%rbp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	-108(%rbp), %ecx
	movq	-116(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-128(%rbp), %rdi
	movl	-120(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	-48(%rbp), %rsi
	movl	-152(%rbp), %edi
	call	_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
.L26:
	movl	-108(%rbp), %ecx
	movq	-116(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-128(%rbp), %rdi
	movl	-120(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	movl	-152(%rbp), %esi
	movq	-40(%rbp), %rdi
	testl	%eax, %eax
	jne	.L27
	movq	-48(%rbp), %rdx
	call	_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
.L27:
	movslq	-152(%rbp), %rdx
	movq	-40(%rbp), %rsi
	movl	$2, %ecx
	movq	-80(%rbp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	-152(%rbp), %rdx
	testl	%eax, %eax
	jne	.L28
.L30:
	xorl	%ebx, %ebx
	jmp	.L29
.L28:
	movq	-40(%rbp), %rsi
	movq	-80(%rbp), %rdi
	salq	$2, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movq	%rax, %rdx
	movl	$127, %ecx
	leaq	.LC17(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L30
.L31:
	movq	-80(%rbp), %rax
	movq	-88(%rbp), %rdi
	movl	$2, %esi
	leaq	.LC18(%rip), %rdx
	movl	(%rax,%rbx,4), %ecx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	incq	%rbx
.L29:
	cmpl	%ebx, -152(%rbp)
	jg	.L31
	movl	$100, %ebx
.L34:
	movl	-108(%rbp), %ecx
	movq	-116(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-128(%rbp), %rdi
	movl	-120(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	-48(%rbp), %r9
	movl	-160(%rbp), %ecx
	pushq	%r8
	movq	-32(%rbp), %rdx
	movl	-156(%rbp), %r8d
	pushq	$0
	movq	-40(%rbp), %rsi
	movss	-96(%rbp), %xmm0
	movl	-148(%rbp), %edi
	.cfi_escape 0x2e,0x10
	call	_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
	popq	%rsi
	popq	%rdi
.L32:
	movl	-108(%rbp), %ecx
	movq	-116(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-128(%rbp), %rdi
	movl	-120(%rbp), %esi
	.cfi_escape 0x2e,0
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	-48(%rbp), %r9
	movl	-156(%rbp), %r8d
	pushq	%rcx
	movq	-32(%rbp), %rdx
	movl	-160(%rbp), %ecx
	pushq	$1
	movq	-40(%rbp), %rsi
	movss	-96(%rbp), %xmm0
	movl	-148(%rbp), %edi
	.cfi_escape 0x2e,0x10
	call	_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
	popq	%rax
	popq	%rdx
.L33:
	decl	%ebx
	jne	.L34
	movq	-48(%rbp), %rdi
	.cfi_escape 0x2e,0
	call	cudaFree@PLT
	movq	-40(%rbp), %rdi
	call	cudaFree@PLT
	movq	-32(%rbp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
.LEHE1:
	leaq	-160(%rbp), %rdi
	call	_ZN5isingIiED1Ev
	movq	-24(%rbp), %rax
	subq	%fs:40, %rax
	je	.L37
	jmp	.L40
.L38:
	endbr64
	movq	%rax, %rbx
.L35:
	leaq	-160(%rbp), %rdi
	call	_ZN5isingIiED1Ev
	movq	-24(%rbp), %rax
	subq	%fs:40, %rax
	jne	.L40
	movq	%rbx, %rdi
.LEHB2:
	call	_Unwind_Resume@PLT
.LEHE2:
.L40:
	call	__stack_chk_fail@PLT
.L37:
	movq	-8(%rbp), %rbx
	xorl	%eax, %eax
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3855:
	.section	.gcc_except_table,"a",@progbits
.LLSDA3855:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE3855-.LLSDACSB3855
.LLSDACSB3855:
	.uleb128 .LEHB0-.LFB3855
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB3855
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L38-.LFB3855
	.uleb128 0
	.uleb128 .LEHB2-.LFB3855
	.uleb128 .LEHE2-.LEHB2
	.uleb128 0
	.uleb128 0
.LLSDACSE3855:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>

using namespace std;
#define D_CHECK(err){\
    if(err !=hipSuccess)\
        printf("error %s,at %d\n",hipGetErrorString(err),__LINE__);    \
}

//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752

__global__ void g_rand_init(int size,hiprandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,hiprandState *states);
__global__ void g_S_init(int *S,int size,hiprandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag);


template <typename T>
class ising{
public:
    // host values
    int row;
    int col;
    int size;
    T J;
    // 交換相互作用エネルギー
    int block_x,block_y;
    int thread_x,thread_y;
    dim3 grid,block;
    int nthreads;
    int sumE;
    float invT;
    FILE *fp;
    
    T *S;
    // スピンの情報

    T *E;
    // 各スピンのエネルギー

    T *hE;
    // エネルギー計算用
    
    // device values
    hipError_t err;
    hiprandState *states;
    //乱数列生成用

    T *dS;
    // デバイス側のスピン

    T *dE;
    // デバイス側の各スピンのエネルギー


    //functions 
    ising(int row_,int col_,T J_,float temperature);
    ~ising();

    void devInit(int bx,int by,int tx,int ty);
    // デバイス側の初期化

    void toFile();
    // ファイルの書き出し

    void checkEnergy();
    // 系のエネルギーのチェック

    void run();
   //シミュレーションのスタート

    void devEnd();
    // デバイスの変数の解放
};

template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
    row = row_;
    col = col_;
    size = row_ * col_;
    J = J_;
    invT = 1.0/temperature_;
    sumE = 0;
    S = (T *) malloc(sizeof(T) * size);
    E = (T *) malloc(sizeof(T) * size);
    hE = (T *) malloc(sizeof(T) * size);
    
    if((fp = fopen("result.dat","w")) == NULL){
        printf("Error at opening file.\n");
        exit(0);
    }
    
    fprintf(fp,"#%9d%9d\n",row,col);
    for(int i=0;i<size;i++)
        S[i] = 0;
}

template <typename T>
ising<T>::~ising(){
    free(S);
    free(E);
    free(hE);
    fclose(fp);
}

template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
    nthreads = bx * by * tx * ty;
    dim3 grid_(bx,by),block_(tx,ty);
    grid = grid_;
    block = block_;

    printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
    hipMalloc((hiprandState **)&states,sizeof(hiprandState)*nthreads);
    hipMalloc((T **)&dS,sizeof(T)*size);
    hipMalloc((T **)&dE,sizeof(T)*size);

    g_rand_init<<<grid,block>>>(size,states);
    g_S_init<<<grid,block>>>(dS,size,states);
    D_CHECK(hipMemcpy(S,dS,sizeof(int)*size,hipMemcpyDeviceToHost));
}

template <typename T>
void ising<T>::devEnd(){
    hipFree(states);
    hipFree(dS);
    hipFree(dE);
    hipDeviceReset();
}

__global__ void g_rand_init(int size,hiprandState *states){
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    int idx = x + y*gridDim.x*blockDim.x;
    if(idx < size){
        hiprand_init(idx,0,0,&states[idx]);
    }
}

__global__ void g_S_init(int *S,int size,hiprandState *states){
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    int idx = x + y*gridDim.x*blockDim.x;
    if(idx < size){
        if(hiprand_uniform(&states[idx]) <= 0.5)
            S[idx] = -1;
        else
            S[idx] = 1;
    }
}


template <typename T>
void ising<T>::run(){
    int flag;
    flag = 0;
    g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
    flag = 1;
    g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}

template <typename T>
void ising<T>::toFile(){
    for(int i=0;i<size;i++)
        fprintf(fp,"%3d",S[i]);
    return;
}

__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag)
{
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;
    int idx = x + y*gridDim.x*blockDim.x;
    int nx;
    int ny;
    float prob;

    if( x < row && y < col){
        if((x+y)% 2 == flag){
            S[x*col+y] = -S[x*col+y];
            E[x*col+y] = 0;
            nx = x-1;
            ny = y;
            if(nx < 0)
                nx = col-1;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];

            nx = x;
            ny = y-1;
            if(ny < 0)
                ny = row-1;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];

            nx = x+1;
            ny = y;
            if(nx >= row)
                nx = 0;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];

            nx = x;
            ny = y+1;
            if(ny >= col)
                ny = 0;
            E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
            if( E[x*col+y]>=0){
                prob = hiprand_uniform(&states[idx]);
                if(prob > exp(-2.0*E[x*col+y]*invT)){
                    S[x*col+y] = -S[x*col+y];
                }
            }
        }
    }
    __syncthreads();
}

int main(void){
    int row = ROW;
    int col = COL;
    int J = 1;

    ising<int> ising2d(row,col,J,0.5);
    ising2d.devInit(64,64,32,32);

    ising2d.toFile();

    for(int i=0;i<100;i++){
        ising2d.run();
        //ising2d.checkEnergy();
        //ising2d.toFile();
    }
    ising2d.devEnd();
    return 0;
}


	.text
	.file	"2d_ising.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z26__device_stub__g_rand_initiP12hiprandState # -- Begin function _Z26__device_stub__g_rand_initiP12hiprandState
	.type	_Z26__device_stub__g_rand_initiP12hiprandState,@function
_Z26__device_stub__g_rand_initiP12hiprandState: # @_Z26__device_stub__g_rand_initiP12hiprandState
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11g_rand_initiP12hiprandState, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__g_rand_initiP12hiprandState, .Lfunc_end0-_Z26__device_stub__g_rand_initiP12hiprandState
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__g_S_initPiiP12hiprandState # -- Begin function _Z23__device_stub__g_S_initPiiP12hiprandState
	.type	_Z23__device_stub__g_S_initPiiP12hiprandState,@function
_Z23__device_stub__g_S_initPiiP12hiprandState: # @_Z23__device_stub__g_S_initPiiP12hiprandState
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8g_S_initPiiP12hiprandState, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__g_S_initPiiP12hiprandState, .Lfunc_end1-_Z23__device_stub__g_S_initPiiP12hiprandState
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei # -- Begin function _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
	.type	_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei,@function
_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei: # @_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movss	%xmm0, (%rdi)
	leaq	56(%rsp), %r10
	movq	%rsi, (%r10)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei, .Lfunc_end2-_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x3f000000                      # float 0.5
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$136, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movq	%rsp, %rbx
	movss	.LCPI3_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movq	%rbx, %rdi
	movl	$10752, %esi                    # imm = 0x2A00
	movl	$10752, %edx                    # imm = 0x2A00
	movl	$1, %ecx
	callq	_ZN5isingIiEC2Eiiif
.Ltmp0:
	movq	%rbx, %rdi
	movl	$64, %esi
	movl	$64, %edx
	movl	$32, %ecx
	movl	$32, %r8d
	callq	_ZN5isingIiE7devInitEiiii
.Ltmp1:
# %bb.1:
	cmpl	$0, 8(%rsp)
	jle	.LBB3_2
# %bb.7:                                # %.lr.ph.i
	xorl	%ebx, %ebx
.LBB3_8:                                # =>This Inner Loop Header: Depth=1
	movq	72(%rsp), %rdi
	movq	80(%rsp), %rax
	movl	(%rax,%rbx,4), %edx
	movl	$.L.str.6, %esi
	xorl	%eax, %eax
	callq	fprintf
	incq	%rbx
	movslq	8(%rsp), %rax
	cmpq	%rax, %rbx
	jl	.LBB3_8
.LBB3_2:                                # %_ZN5isingIiE6toFileEv.exit.preheader
	movl	$100, %ebp
	movq	%rsp, %rbx
.LBB3_3:                                # %_ZN5isingIiE6toFileEv.exit
                                        # =>This Inner Loop Header: Depth=1
.Ltmp2:
	movq	%rbx, %rdi
	callq	_ZN5isingIiE3runEv
.Ltmp3:
# %bb.4:                                #   in Loop: Header=BB3_3 Depth=1
	decl	%ebp
	jne	.LBB3_3
# %bb.5:
.Ltmp5:
	movq	%rsp, %rdi
	callq	_ZN5isingIiE6devEndEv
.Ltmp6:
# %bb.6:
	movq	%rsp, %rdi
	callq	_ZN5isingIiED2Ev
	xorl	%eax, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_10:
	.cfi_def_cfa_offset 160
.Ltmp7:
	jmp	.LBB3_11
.LBB3_9:
.Ltmp4:
.LBB3_11:
	movq	%rax, %rbx
	movq	%rsp, %rdi
	callq	_ZN5isingIiED2Ev
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table3:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp7-.Lfunc_begin0           #     jumps to .Ltmp7
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp2-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp2                  #   Call between .Ltmp2 and .Ltmp3
	.uleb128 .Ltmp4-.Lfunc_begin0           #     jumps to .Ltmp4
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp5-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp6-.Ltmp5                  #   Call between .Ltmp5 and .Ltmp6
	.uleb128 .Ltmp7-.Lfunc_begin0           #     jumps to .Ltmp7
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Lfunc_end3-.Ltmp6             #   Call between .Ltmp6 and .Lfunc_end3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _ZN5isingIiEC2Eiiif
.LCPI4_0:
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI4_1:
	.long	0x3f800000                      # float 1
	.section	.text._ZN5isingIiEC2Eiiif,"axG",@progbits,_ZN5isingIiEC2Eiiif,comdat
	.weak	_ZN5isingIiEC2Eiiif
	.p2align	1, 0x90
	.type	_ZN5isingIiEC2Eiiif,@function
_ZN5isingIiEC2Eiiif:                    # @_ZN5isingIiEC2Eiiif
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	movaps	.LCPI4_0(%rip), %xmm1           # xmm1 = [1,1,1,1]
	movups	%xmm1, 32(%rdi)
	movabsq	$4294967297, %rax               # imm = 0x100000001
	movq	%rax, 48(%rdi)
	movl	%esi, (%rdi)
	movl	%edx, 4(%rdi)
	imull	%esi, %edx
	movl	%edx, 8(%rdi)
	movl	%ecx, 12(%rdi)
	movss	.LCPI4_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, 64(%rdi)
	movl	$0, 60(%rdi)
	movslq	%edx, %r14
	shlq	$2, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 80(%rbx)
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 88(%rbx)
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 96(%rbx)
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, 72(%rbx)
	testq	%rax, %rax
	je	.LBB4_5
# %bb.1:
	movl	(%rbx), %edx
	movl	4(%rbx), %ecx
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	fprintf
	cmpl	$0, 8(%rbx)
	jle	.LBB4_4
# %bb.2:                                # %.lr.ph
	movq	80(%rbx), %rax
	xorl	%ecx, %ecx
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	movl	$0, (%rax,%rcx,4)
	incq	%rcx
	movslq	8(%rbx), %rdx
	cmpq	%rdx, %rcx
	jl	.LBB4_3
.LBB4_4:                                # %._crit_edge
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB4_5:
	.cfi_def_cfa_offset 32
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end4:
	.size	_ZN5isingIiEC2Eiiif, .Lfunc_end4-_ZN5isingIiEC2Eiiif
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN5isingIiE7devInitEiiii,"axG",@progbits,_ZN5isingIiE7devInitEiiii,comdat
	.weak	_ZN5isingIiE7devInitEiiii       # -- Begin function _ZN5isingIiE7devInitEiiii
	.p2align	1, 0x90
	.type	_ZN5isingIiE7devInitEiiii,@function
_ZN5isingIiE7devInitEiiii:              # @_ZN5isingIiE7devInitEiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movl	%edx, %eax
	imull	%esi, %eax
	movl	%ecx, %edi
	imull	%r8d, %edi
	imull	%eax, %edi
	movl	%edi, 56(%rbx)
	movl	%esi, 32(%rbx)
	movl	%edx, 36(%rbx)
	movl	$1, %eax
	movl	%eax, 40(%rbx)
	movl	%ecx, 44(%rbx)
	movl	%r8d, 48(%rbx)
	movl	%eax, 52(%rbx)
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	112(%rbx), %rdi
	movslq	56(%rbx), %rax
	shlq	$4, %rax
	leaq	(%rax,%rax,2), %rsi
	callq	hipMalloc
	leaq	120(%rbx), %rdi
	movslq	8(%rbx), %rsi
	shlq	$2, %rsi
	callq	hipMalloc
	leaq	128(%rbx), %rdi
	movslq	8(%rbx), %rsi
	shlq	$2, %rsi
	callq	hipMalloc
	movq	32(%rbx), %rdi
	movl	40(%rbx), %esi
	movq	44(%rbx), %rdx
	movl	52(%rbx), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movl	8(%rbx), %edi
	movq	112(%rbx), %rsi
	callq	_Z26__device_stub__g_rand_initiP12hiprandState
.LBB5_2:
	movq	32(%rbx), %rdi
	movl	40(%rbx), %esi
	movq	44(%rbx), %rdx
	movl	52(%rbx), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.3:
	movq	120(%rbx), %rdi
	movl	8(%rbx), %esi
	movq	112(%rbx), %rdx
	callq	_Z23__device_stub__g_S_initPiiP12hiprandState
.LBB5_4:
	movq	80(%rbx), %rdi
	movq	120(%rbx), %rsi
	movslq	8(%rbx), %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB5_5
# %bb.6:
	movq	80(%rbx), %rdi
	movq	120(%rbx), %rsi
	movslq	8(%rbx), %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	movl	$127, %edx
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB5_5:
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZN5isingIiE7devInitEiiii, .Lfunc_end5-_ZN5isingIiE7devInitEiiii
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN5isingIiE3runEv,"axG",@progbits,_ZN5isingIiE3runEv,comdat
	.weak	_ZN5isingIiE3runEv              # -- Begin function _ZN5isingIiE3runEv
	.p2align	1, 0x90
	.type	_ZN5isingIiE3runEv,@function
_ZN5isingIiE3runEv:                     # @_ZN5isingIiE3runEv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movq	32(%rdi), %rdi
	movl	40(%rbx), %esi
	movq	44(%rbx), %rdx
	movl	52(%rbx), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movl	12(%rbx), %edi
	movss	64(%rbx), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	movq	120(%rbx), %rsi
	movq	128(%rbx), %rdx
	movl	(%rbx), %ecx
	movl	4(%rbx), %r8d
	movq	112(%rbx), %r9
	movl	$0, (%rsp)
	callq	_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.LBB6_2:
	movq	32(%rbx), %rdi
	movl	40(%rbx), %esi
	movq	44(%rbx), %rdx
	movl	52(%rbx), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_4
# %bb.3:
	movl	12(%rbx), %edi
	movss	64(%rbx), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	movq	120(%rbx), %rsi
	movq	128(%rbx), %rdx
	movl	(%rbx), %ecx
	movl	4(%rbx), %r8d
	movq	112(%rbx), %r9
	movl	$1, (%rsp)
	callq	_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.LBB6_4:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_ZN5isingIiE3runEv, .Lfunc_end6-_ZN5isingIiE3runEv
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN5isingIiE6devEndEv,"axG",@progbits,_ZN5isingIiE6devEndEv,comdat
	.weak	_ZN5isingIiE6devEndEv           # -- Begin function _ZN5isingIiE6devEndEv
	.p2align	1, 0x90
	.type	_ZN5isingIiE6devEndEv,@function
_ZN5isingIiE6devEndEv:                  # @_ZN5isingIiE6devEndEv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movq	112(%rdi), %rdi
	callq	hipFree
	movq	120(%rbx), %rdi
	callq	hipFree
	movq	128(%rbx), %rdi
	callq	hipFree
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	hipDeviceReset                  # TAILCALL
.Lfunc_end7:
	.size	_ZN5isingIiE6devEndEv, .Lfunc_end7-_ZN5isingIiE6devEndEv
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED2Ev,comdat
	.weak	_ZN5isingIiED2Ev                # -- Begin function _ZN5isingIiED2Ev
	.p2align	1, 0x90
	.type	_ZN5isingIiED2Ev,@function
_ZN5isingIiED2Ev:                       # @_ZN5isingIiED2Ev
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movq	80(%rdi), %rdi
	callq	free
	movq	88(%rbx), %rdi
	callq	free
	movq	96(%rbx), %rdi
	callq	free
	movq	72(%rbx), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end8:
	.size	_ZN5isingIiED2Ev, .Lfunc_end8-_ZN5isingIiED2Ev
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11g_rand_initiP12hiprandState, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8g_S_initPiiP12hiprandState, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10g_simulateifPiS_iiP12hiprandStatei, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11g_rand_initiP12hiprandState,@object # @_Z11g_rand_initiP12hiprandState
	.section	.rodata,"a",@progbits
	.globl	_Z11g_rand_initiP12hiprandState
	.p2align	3, 0x0
_Z11g_rand_initiP12hiprandState:
	.quad	_Z26__device_stub__g_rand_initiP12hiprandState
	.size	_Z11g_rand_initiP12hiprandState, 8

	.type	_Z8g_S_initPiiP12hiprandState,@object # @_Z8g_S_initPiiP12hiprandState
	.globl	_Z8g_S_initPiiP12hiprandState
	.p2align	3, 0x0
_Z8g_S_initPiiP12hiprandState:
	.quad	_Z23__device_stub__g_S_initPiiP12hiprandState
	.size	_Z8g_S_initPiiP12hiprandState, 8

	.type	_Z10g_simulateifPiS_iiP12hiprandStatei,@object # @_Z10g_simulateifPiS_iiP12hiprandStatei
	.globl	_Z10g_simulateifPiS_iiP12hiprandStatei
	.p2align	3, 0x0
_Z10g_simulateifPiS_iiP12hiprandStatei:
	.quad	_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
	.size	_Z10g_simulateifPiS_iiP12hiprandStatei, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"result.dat"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w"
	.size	.L.str.1, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"#%9d%9d\n"
	.size	.L.str.3, 9

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"grid=[%d,%d],block[%d,%d]\n"
	.size	.L.str.4, 27

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"error %s,at %d\n"
	.size	.L.str.5, 16

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%3d"
	.size	.L.str.6, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11g_rand_initiP12hiprandState"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8g_S_initPiiP12hiprandState"
	.size	.L__unnamed_2, 30

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10g_simulateifPiS_iiP12hiprandStatei"
	.size	.L__unnamed_3, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Error at opening file."
	.size	.Lstr, 23

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__g_rand_initiP12hiprandState
	.addrsig_sym _Z23__device_stub__g_S_initPiiP12hiprandState
	.addrsig_sym _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z11g_rand_initiP12hiprandState
	.addrsig_sym _Z8g_S_initPiiP12hiprandState
	.addrsig_sym _Z10g_simulateifPiS_iiP12hiprandStatei
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11g_rand_initiP12hiprandState ; -- Begin function _Z11g_rand_initiP12hiprandState
	.globl	_Z11g_rand_initiP12hiprandState
	.p2align	8
	.type	_Z11g_rand_initiP12hiprandState,@function
_Z11g_rand_initiP12hiprandState:        ; @_Z11g_rand_initiP12hiprandState
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_load_b32 s4, s[0:1], 0x0
	v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x8
	v_xor_b32_e32 v2, 0x2c7f967f, v0
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v1, 0x8a5d614f
	v_cmp_lt_i32_e32 vcc_lo, -1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, 0x493c4aa1, v2
	v_dual_mov_b32 v6, v5 :: v_dual_cndmask_b32 v1, 0xfa091aa4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, 0x1f123bb5, v1
	v_add3_u32 v4, v9, v1, 0x64f0c9
	v_xor_b32_e32 v3, 0x5491333, v1
	v_xor_b32_e32 v1, 0x159a55e5, v9
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[7:8], null, v0, 48, s[0:1]
	v_add_nc_u32_e32 v0, 0x75bcd15, v9
	v_add_nc_u32_e32 v9, 0x583f19, v9
	s_clause 0x2
	global_store_b96 v[7:8], v[4:6], off
	global_store_b128 v[7:8], v[0:3], off offset:24
	global_store_b32 v[7:8], v9, off offset:40
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11g_rand_initiP12hiprandState
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11g_rand_initiP12hiprandState, .Lfunc_end0-_Z11g_rand_initiP12hiprandState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8g_S_initPiiP12hiprandState ; -- Begin function _Z8g_S_initPiiP12hiprandState
	.globl	_Z8g_S_initPiiP12hiprandState
	.p2align	8
	.type	_Z8g_S_initPiiP12hiprandState,@function
_Z8g_S_initPiiP12hiprandState:          ; @_Z8g_S_initPiiP12hiprandState
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_load_b32 s4, s[0:1], 0x8
	v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB1_2
; %bb.1:                                ; %.sink.split
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[6:7], null, v0, 48, s[2:3]
	s_clause 0x2
	global_load_b128 v[1:4], v[6:7], off offset:24
	global_load_b32 v5, v[6:7], off offset:40
	global_load_b32 v8, v[6:7], off
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v9, 2, v1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, 0x587c5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v9, v1
	v_lshlrev_b32_e32 v9, 4, v5
	v_lshlrev_b32_e32 v10, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v10, v9
	v_xor3_b32 v9, v9, v1, v5
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v8, v9
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v10, v10
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_fmaak_f32 v10, 0x2f800000, v10, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nge_f32_e32 vcc_lo, 0.5, v10
	v_cndmask_b32_e64 v10, -1, 1, vcc_lo
	s_clause 0x2
	global_store_b32 v[6:7], v9, off offset:40
	global_store_b128 v[6:7], v[2:5], off offset:24
	global_store_b32 v[6:7], v8, off
	global_store_b32 v[0:1], v10, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8g_S_initPiiP12hiprandState
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8g_S_initPiiP12hiprandState, .Lfunc_end1-_Z8g_S_initPiiP12hiprandState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10g_simulateifPiS_iiP12hiprandStatei ; -- Begin function _Z10g_simulateifPiS_iiP12hiprandStatei
	.globl	_Z10g_simulateifPiS_iiP12hiprandStatei
	.p2align	8
	.type	_Z10g_simulateifPiS_iiP12hiprandStatei,@function
_Z10g_simulateifPiS_iiP12hiprandStatei: ; @_Z10g_simulateifPiS_iiP12hiprandStatei
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[10:11], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_add_u32 s8, s0, 48
	s_addc_u32 s9, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s13, s2, 0xffff
	s_lshr_b32 s3, s2, 16
	v_mad_u64_u32 v[2:3], null, s14, s13, v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s10, v2
	v_cmp_gt_i32_e64 s2, s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s12, s2
	s_cbranch_execz .LBB2_5
; %bb.1:
	v_add_nc_u32_e32 v0, v3, v2
	s_load_b32 s2, s[0:1], 0x28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 31, v0
	v_add_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, -2, v1
	v_sub_nc_u32_e32 v0, v0, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, s2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.2:
	v_mul_lo_u32 v11, v2, s11
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v11, v3
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s2, 0, s2
	v_add_co_u32 v0, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 1, v2
	global_load_b32 v8, v[0:1], off
	v_cndmask_b32_e64 v6, v2, s11, vcc_lo
	v_add_nc_u32_e32 v9, -1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[6:7], null, v9, s11, v[3:4]
	v_mov_b32_e32 v9, 0
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 1, v3
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v8, 0, v8
	global_store_b32 v[0:1], v8, off
	global_store_b32 v[4:5], v9, off
	s_clause 0x1
	global_load_b32 v8, v[0:1], off
	global_load_b32 v9, v[6:7], off
	v_cndmask_b32_e64 v6, v3, s10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v11, v6, -1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v8, v8, s2
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v8, v8, v9
	global_store_b32 v[4:5], v8, off
	s_clause 0x1
	global_load_b32 v9, v[0:1], off
	global_load_b32 v12, v[6:7], off
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s10, v6
	v_cndmask_b32_e32 v10, 0, v6, vcc_lo
	v_mad_u64_u32 v[6:7], null, v10, s11, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v13, v9, s2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, v12, v[8:9]
	global_store_b32 v[4:5], v9, off
	s_clause 0x1
	global_load_b32 v8, v[0:1], off
	global_load_b32 v7, v[6:7], off
	v_add_nc_u32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s11, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_add_nc_u32_e32 v6, v6, v11
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v8, v8, s2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v8, v7, v[9:10]
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	global_store_b32 v[4:5], v10, off
	global_load_b32 v8, v[0:1], off
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v8, v8, s2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, v9, v[10:11]
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	global_store_b32 v[4:5], v6, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.3:
	s_load_b32 s2, s[8:9], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s2, v3, v[2:3]
	v_mad_i64_i32 v[2:3], null, v6, 48, s[0:1]
	s_mov_b32 s0, 0x652b82fe
	s_mov_b32 s1, 0x3ff71547
	s_clause 0x2
	global_load_b128 v[6:9], v[2:3], off offset:24
	global_load_b32 v10, v[2:3], off offset:40
	global_load_b32 v11, v[2:3], off
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v12, 2, v6
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v11, 0x587c5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v12, v6
	v_lshlrev_b32_e32 v12, 4, v10
	v_lshlrev_b32_e32 v13, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v12, v13, v12
	v_xor3_b32 v12, v12, v6, v10
	s_clause 0x2
	global_store_b32 v[2:3], v11, off
	global_store_b128 v[2:3], v[7:10], off offset:24
	global_store_b32 v[2:3], v12, off offset:40
	global_load_b32 v2, v[4:5], off
	v_cvt_f64_f32_e32 v[4:5], s3
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	s_waitcnt vmcnt(0)
	v_cvt_f64_i32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], -2.0
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], v[2:3], s[0:1]
	s_mov_b32 s0, 0xfefa39ef
	s_mov_b32 s1, 0xbfe62e42
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
	v_rndne_f64_e32 v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
	s_mov_b32 s0, 0x3b39803f
	s_mov_b32 s1, 0xbc7abc9e
	v_cvt_i32_f64_e32 v10, v[4:5]
	v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
	s_mov_b32 s0, 0xfca7ab0c
	s_mov_b32 s1, 0x3e928af3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
	v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
	v_add_nc_u32_e32 v6, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v6, v6
	v_fmaak_f32 v2, 0x2f800000, v6, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[2:3], v2
	v_ldexp_f64 v[4:5], v[4:5], v10
	v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, v5, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[2:3]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.4:
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v2, 0, v2
	global_store_b32 v[0:1], v2, off
.LBB2_5:
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10g_simulateifPiS_iiP12hiprandStatei
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10g_simulateifPiS_iiP12hiprandStatei, .Lfunc_end2-_Z10g_simulateifPiS_iiP12hiprandStatei
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1444
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11g_rand_initiP12hiprandState
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11g_rand_initiP12hiprandState.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8g_S_initPiiP12hiprandState
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8g_S_initPiiP12hiprandState.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10g_simulateifPiS_iiP12hiprandStatei
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10g_simulateifPiS_iiP12hiprandStatei.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
