#define CUDA_SAFE_CALL(func) \
do { \
        cudaError_t err = (func); \
        if (err != cudaSuccess) { \
                fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", cudaGetErrorString(err), err, __FILE__, __LINE__); \
                exit(err); \
        } \
} while (0)

__global__ void
cudaProcessUnsignedChar0(unsigned char *dst, unsigned char *src, int imgW, int imgH)
{
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int bw = blockDim.x;
    int bh = blockDim.y;
    int x = blockIdx.x*bw + tx * 2;
    int y = blockIdx.y*bh + ty * 2;
    int px = y * imgW + x;

    bool flag = 0 < y && y < (imgH - 2) && 0 < x && x < (imgW - 2);
    int sx1 = flag ? px - imgW : 0;
    int sx2 = flag ? px - imgW + 1 : 0;
    int sx3 = flag ? px - imgW + 2 : 0;
    int sx4 = flag ? px - 1 : 0;
    int sx5 = flag ? px : 0;
    int sx6 = flag ? px + 1 : 0;
    int sx7 = flag ? px + 2 : 0;
    int sx8 = flag ? px + imgW - 1 : 0;
    int sx9 = flag ? px + imgW : 0;
    int sxa = flag ? px + imgW + 1 : 0;
    int sxb = flag ? px + imgW + 2 : 0;
    int sxc = flag ? px + imgW * 2 - 1 : 0;
    int sxd = flag ? px + imgW * 2     : 0;
    int sxe = flag ? px + imgW * 2 + 1 : 0;

    // G0 R0 G1 R1    x0 x1 x2 x3
    // B0 G2 B1 G3    x4 x5 x6 x7
    // G4 R2 G5 R3    x8 x9 xA xB
    // B2 G6 B3 G7    xC xD xE xF

    int g1 = (int)src[sx2];
    int g2 = (int)src[sx5];
    int g3 = (int)src[sx7];
    int g4 = (int)src[sx8];
    int g5 = (int)src[sxa];
    int g6 = (int)src[sxd];
    int b0 = (int)src[sx4];
    int b1 = (int)src[sx6];
    int b2 = (int)src[sxc];
    int b3 = (int)src[sxe];
    int r0 = (int)src[sx1];
    int r1 = (int)src[sx3];
    int r2 = (int)src[sx9];
    int r3 = (int)src[sxb];

    int db0 = (b0 + b1) >> 1;
    int dg0 = g2;
    int dr0 = (r0 + r1) >> 1;
    int db1 = b1;
    int dg1 = (g1 + g2 + g3 + g5) >> 2;
    int dr1 = (r0 + r1 + r2 + r3) >> 2;
    int db2 = (b0 + b1 + b2 + b3) >> 2;
    int dg2 = (g2 + g4 + g5 + g6) >> 2;
    int dr2 = r2;
    int db3 = (b1 + b3) >> 1;
    int dg3 = g5;
    int dr3 = (r2 + r3) >> 1;

    int dx = px * 3;
    int dst0 = dx;
    int dst1 = dx + 3;
    int dst2 = dx + imgW * 3;
    int dst3 = dx + (imgW + 1) * 3;
    dst[dst0 + 0 < imgW * imgH * 3 ? dst0 + 0 : 0] = (unsigned char)db0;
    dst[dst0 + 1 < imgW * imgH * 3 ? dst0 + 1 : 0] = (unsigned char)dg0;
    dst[dst0 + 2 < imgW * imgH * 3 ? dst0 + 2 : 0] = (unsigned char)dr0;
    dst[dst1 + 0 < imgW * imgH * 3 ? dst1 + 0 : 0] = (unsigned char)db1;
    dst[dst1 + 1 < imgW * imgH * 3 ? dst1 + 1 : 0] = (unsigned char)dg1;
    dst[dst1 + 2 < imgW * imgH * 3 ? dst1 + 2 : 0] = (unsigned char)dr1;
    dst[dst2 + 0 < imgW * imgH * 3 ? dst2 + 0 : 0] = (unsigned char)db2;
    dst[dst2 + 1 < imgW * imgH * 3 ? dst2 + 1 : 0] = (unsigned char)dg2;
    dst[dst2 + 2 < imgW * imgH * 3 ? dst2 + 2 : 0] = (unsigned char)dr2;
    dst[dst3 + 0 < imgW * imgH * 3 ? dst3 + 0 : 0] = (unsigned char)db3;
    dst[dst3 + 1 < imgW * imgH * 3 ? dst3 + 1 : 0] = (unsigned char)dg3;
    dst[dst3 + 2 < imgW * imgH * 3 ? dst3 + 2 : 0] = (unsigned char)dr3;
}

extern "C" void
launchCudaProcessUnsignedChar(dim3 grid, dim3 block, unsigned char* srcImage, unsigned char* dstImage, int imgW, int imgH)
{
    cudaProcessUnsignedChar0 <<< grid, block>>>(dstImage, srcImage, imgW, imgH);
}

	.file	"tmpxft_0025d956_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii
	.type	_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii, @function
_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24cudaProcessUnsignedChar0PhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii, .-_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii
	.globl	_Z24cudaProcessUnsignedChar0PhS_ii
	.type	_Z24cudaProcessUnsignedChar0PhS_ii, @function
_Z24cudaProcessUnsignedChar0PhS_ii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii
	.cfi_endproc
.LFE2034:
	.size	_Z24cudaProcessUnsignedChar0PhS_ii, .-_Z24cudaProcessUnsignedChar0PhS_ii
	.globl	launchCudaProcessUnsignedChar
	.type	launchCudaProcessUnsignedChar, @function
launchCudaProcessUnsignedChar:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%r8, %rbp
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%r9, %rbx
	xorl	%r9d, %r9d
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	80(%rsp), %r12d
	movl	88(%rsp), %r13d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z48__device_stub__Z24cudaProcessUnsignedChar0PhS_iiPhS_ii
.L8:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	launchCudaProcessUnsignedChar, .-launchCudaProcessUnsignedChar
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24cudaProcessUnsignedChar0PhS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24cudaProcessUnsignedChar0PhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define CUDA_SAFE_CALL(func) \
do { \
        hipError_t err = (func); \
        if (err != hipSuccess) { \
                fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", hipGetErrorString(err), err, __FILE__, __LINE__); \
                exit(err); \
        } \
} while (0)

__global__ void
cudaProcessUnsignedChar0(unsigned char *dst, unsigned char *src, int imgW, int imgH)
{
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int bw = blockDim.x;
    int bh = blockDim.y;
    int x = blockIdx.x*bw + tx * 2;
    int y = blockIdx.y*bh + ty * 2;
    int px = y * imgW + x;

    bool flag = 0 < y && y < (imgH - 2) && 0 < x && x < (imgW - 2);
    int sx1 = flag ? px - imgW : 0;
    int sx2 = flag ? px - imgW + 1 : 0;
    int sx3 = flag ? px - imgW + 2 : 0;
    int sx4 = flag ? px - 1 : 0;
    int sx5 = flag ? px : 0;
    int sx6 = flag ? px + 1 : 0;
    int sx7 = flag ? px + 2 : 0;
    int sx8 = flag ? px + imgW - 1 : 0;
    int sx9 = flag ? px + imgW : 0;
    int sxa = flag ? px + imgW + 1 : 0;
    int sxb = flag ? px + imgW + 2 : 0;
    int sxc = flag ? px + imgW * 2 - 1 : 0;
    int sxd = flag ? px + imgW * 2     : 0;
    int sxe = flag ? px + imgW * 2 + 1 : 0;

    // G0 R0 G1 R1    x0 x1 x2 x3
    // B0 G2 B1 G3    x4 x5 x6 x7
    // G4 R2 G5 R3    x8 x9 xA xB
    // B2 G6 B3 G7    xC xD xE xF

    int g1 = (int)src[sx2];
    int g2 = (int)src[sx5];
    int g3 = (int)src[sx7];
    int g4 = (int)src[sx8];
    int g5 = (int)src[sxa];
    int g6 = (int)src[sxd];
    int b0 = (int)src[sx4];
    int b1 = (int)src[sx6];
    int b2 = (int)src[sxc];
    int b3 = (int)src[sxe];
    int r0 = (int)src[sx1];
    int r1 = (int)src[sx3];
    int r2 = (int)src[sx9];
    int r3 = (int)src[sxb];

    int db0 = (b0 + b1) >> 1;
    int dg0 = g2;
    int dr0 = (r0 + r1) >> 1;
    int db1 = b1;
    int dg1 = (g1 + g2 + g3 + g5) >> 2;
    int dr1 = (r0 + r1 + r2 + r3) >> 2;
    int db2 = (b0 + b1 + b2 + b3) >> 2;
    int dg2 = (g2 + g4 + g5 + g6) >> 2;
    int dr2 = r2;
    int db3 = (b1 + b3) >> 1;
    int dg3 = g5;
    int dr3 = (r2 + r3) >> 1;

    int dx = px * 3;
    int dst0 = dx;
    int dst1 = dx + 3;
    int dst2 = dx + imgW * 3;
    int dst3 = dx + (imgW + 1) * 3;
    dst[dst0 + 0 < imgW * imgH * 3 ? dst0 + 0 : 0] = (unsigned char)db0;
    dst[dst0 + 1 < imgW * imgH * 3 ? dst0 + 1 : 0] = (unsigned char)dg0;
    dst[dst0 + 2 < imgW * imgH * 3 ? dst0 + 2 : 0] = (unsigned char)dr0;
    dst[dst1 + 0 < imgW * imgH * 3 ? dst1 + 0 : 0] = (unsigned char)db1;
    dst[dst1 + 1 < imgW * imgH * 3 ? dst1 + 1 : 0] = (unsigned char)dg1;
    dst[dst1 + 2 < imgW * imgH * 3 ? dst1 + 2 : 0] = (unsigned char)dr1;
    dst[dst2 + 0 < imgW * imgH * 3 ? dst2 + 0 : 0] = (unsigned char)db2;
    dst[dst2 + 1 < imgW * imgH * 3 ? dst2 + 1 : 0] = (unsigned char)dg2;
    dst[dst2 + 2 < imgW * imgH * 3 ? dst2 + 2 : 0] = (unsigned char)dr2;
    dst[dst3 + 0 < imgW * imgH * 3 ? dst3 + 0 : 0] = (unsigned char)db3;
    dst[dst3 + 1 < imgW * imgH * 3 ? dst3 + 1 : 0] = (unsigned char)dg3;
    dst[dst3 + 2 < imgW * imgH * 3 ? dst3 + 2 : 0] = (unsigned char)dr3;
}

extern "C" void
launchCudaProcessUnsignedChar(dim3 grid, dim3 block, unsigned char* srcImage, unsigned char* dstImage, int imgW, int imgH)
{
    cudaProcessUnsignedChar0 <<< grid, block>>>(dstImage, srcImage, imgW, imgH);
}

	.text
	.file	"kernel.hip"
	.globl	_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii # -- Begin function _Z39__device_stub__cudaProcessUnsignedChar0PhS_ii
	.type	_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii,@function
_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii: # @_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24cudaProcessUnsignedChar0PhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii, .Lfunc_end0-_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii
	.cfi_endproc
                                        # -- End function
	.globl	launchCudaProcessUnsignedChar   # -- Begin function launchCudaProcessUnsignedChar
	.type	launchCudaProcessUnsignedChar,@function
launchCudaProcessUnsignedChar:          # @launchCudaProcessUnsignedChar
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %r14
	movq	%r8, %rbx
	movl	56(%rsp), %ebp
	movl	48(%rsp), %r15d
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 48
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii # TAILCALL
.Lfunc_end1:
	.size	launchCudaProcessUnsignedChar, .Lfunc_end1-launchCudaProcessUnsignedChar
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24cudaProcessUnsignedChar0PhS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24cudaProcessUnsignedChar0PhS_ii,@object # @_Z24cudaProcessUnsignedChar0PhS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z24cudaProcessUnsignedChar0PhS_ii
	.p2align	3, 0x0
_Z24cudaProcessUnsignedChar0PhS_ii:
	.quad	_Z39__device_stub__cudaProcessUnsignedChar0PhS_ii
	.size	_Z24cudaProcessUnsignedChar0PhS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24cudaProcessUnsignedChar0PhS_ii"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__cudaProcessUnsignedChar0PhS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24cudaProcessUnsignedChar0PhS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24cudaProcessUnsignedChar0PhS_ii ; -- Begin function _Z24cudaProcessUnsignedChar0PhS_ii
	.globl	_Z24cudaProcessUnsignedChar0PhS_ii
	.p2align	8
	.type	_Z24cudaProcessUnsignedChar0PhS_ii,@function
_Z24cudaProcessUnsignedChar0PhS_ii:     ; @_Z24cudaProcessUnsignedChar0PhS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_lshrrev_b32_e32 v1, 9, v0
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0x7fe, v1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	s_mul_i32 s14, s14, s2
	s_mov_b32 s3, 0
	v_lshl_add_u32 v3, v0, 1, s14
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 0, v2
; %bb.1:
	s_add_i32 s2, s5, -2
	s_add_i32 s3, s4, -2
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	v_cmp_gt_i32_e64 s2, s3, v3
	v_cmp_lt_i32_e64 s3, 0, v3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s2, exec_lo
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v2, s4, v0
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v5
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v19, v5
	v_dual_mov_b32 v18, v4 :: v_dual_mov_b32 v27, v5
	v_dual_mov_b32 v26, v4 :: v_dual_mov_b32 v21, v5
	v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v25, v5
	v_dual_mov_b32 v24, v4 :: v_dual_mov_b32 v15, v5
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v31, v5
	v_dual_mov_b32 v30, v4 :: v_dual_mov_b32 v23, v5
	v_dual_mov_b32 v22, v4 :: v_dual_mov_b32 v13, v5
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v29, v5
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v11, v5
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v17, v5
	v_mov_b32_e32 v16, v4
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_subrev_nc_u32_e32 v10, s4, v0
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v4, s4, v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v6, 2, v2
	v_add_nc_u32_e32 v18, 1, v2
	v_add_nc_u32_e32 v20, -1, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v31, v1 :: v_dual_add_nc_u32 v24, 2, v0
	v_add_nc_u32_e32 v14, 1, v0
	v_add_nc_u32_e32 v28, 1, v10
	v_add_nc_u32_e32 v22, -1, v0
	v_dual_mov_b32 v27, v3 :: v_dual_add_nc_u32 v12, 2, v10
	v_add_nc_u32_e32 v8, -1, v4
	v_add_nc_u32_e32 v16, 1, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v29, 31, v28
	v_ashrrev_i32_e32 v25, 31, v24
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v19, 31, v18
	v_ashrrev_i32_e32 v23, 31, v22
	v_ashrrev_i32_e32 v15, 31, v14
	v_ashrrev_i32_e32 v17, 31, v16
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v26, v2
	v_mov_b32_e32 v30, v0
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v0, v0, 1, v0
	v_lshl_add_u32 v1, v2, 1, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v28, vcc_lo, s2, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
	v_add_co_u32 v30, vcc_lo, s2, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
	v_add_co_u32 v24, vcc_lo, s2, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	v_add_co_u32 v18, vcc_lo, s2, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, s2, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
	s_clause 0x1
	global_load_u8 v30, v[30:31], off
	global_load_u8 v31, v[18:19], off
	v_add_co_u32 v18, vcc_lo, s2, v22
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v23, vcc_lo
	v_add_co_u32 v14, vcc_lo, s2, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	v_add_co_u32 v16, vcc_lo, s2, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	v_add_co_u32 v22, vcc_lo, s2, v26
	v_add_co_ci_u32_e32 v23, vcc_lo, s3, v27, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_clause 0x5
	global_load_u8 v26, v[18:19], off
	global_load_u8 v27, v[14:15], off
	global_load_u8 v32, v[16:17], off
	global_load_u8 v33, v[10:11], off
	global_load_u8 v34, v[12:13], off
	global_load_u8 v35, v[22:23], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_u8 v36, v[6:7], off
	v_add_co_u32 v3, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
	s_clause 0x4
	global_load_u8 v28, v[28:29], off
	global_load_u8 v24, v[24:25], off
	global_load_u8 v25, v[20:21], off
	global_load_u8 v29, v[8:9], off
	global_load_u8 v37, v[3:4], off
	s_mul_i32 s2, s4, 3
	v_add_nc_u32_e32 v7, 1, v1
	s_mul_i32 s3, s2, s5
	v_add_nc_u32_e32 v6, 4, v0
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_add_nc_u32_e32 v4, 1, v0
	v_add_nc_u32_e32 v5, 2, v0
	v_cndmask_b32_e32 v3, 0, v0, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	v_cndmask_b32_e32 v12, 0, v1, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v9, 31, v3
	v_ashrrev_i32_e32 v14, 31, v12
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v5
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_add_nc_u32 v2, 3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, s2, v2
	v_cmp_gt_i32_e32 vcc_lo, s3, v2
	v_add_nc_u32_e32 v38, 2, v8
	v_add_nc_u32_e32 v0, 5, v0
	v_cndmask_b32_e32 v10, 0, v2, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v17, 31, v10
	v_cndmask_b32_e32 v11, 0, v6, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_ashrrev_i32_e32 v6, 31, v4
	v_ashrrev_i32_e32 v18, 31, v11
	v_cndmask_b32_e32 v13, 0, v0, vcc_lo
	v_add_nc_u32_e32 v1, 2, v1
	v_cmp_gt_i32_e32 vcc_lo, s3, v7
	v_add_nc_u32_e32 v23, 1, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v19, 31, v13
	v_cndmask_b32_e32 v15, 0, v7, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	v_ashrrev_i32_e32 v7, 31, v5
	v_ashrrev_i32_e32 v20, 31, v15
	v_cndmask_b32_e32 v16, 0, v1, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v21, 31, v16
	v_cndmask_b32_e32 v22, 0, v8, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v17, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v18, vcc_lo
	v_add_co_u32 v10, vcc_lo, s0, v13
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v19, vcc_lo
	v_add_co_u32 v12, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v14, vcc_lo
	v_add_co_u32 v14, vcc_lo, s0, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v20, vcc_lo
	v_add_co_u32 v16, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v21, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v23
	v_ashrrev_i32_e32 v19, 31, v22
	v_cndmask_b32_e32 v20, 0, v23, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v38
	v_cndmask_b32_e32 v23, 0, v38, vcc_lo
	v_add_co_u32 v18, vcc_lo, s0, v22
	v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v38, 31, v23
	s_waitcnt vmcnt(13)
	v_and_b32_e32 v39, 0xff, v30
	s_waitcnt vmcnt(12)
	v_and_b32_e32 v40, 0xff, v31
	v_ashrrev_i32_e32 v21, 31, v20
	v_add_co_u32 v20, vcc_lo, s0, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo
	v_add_co_u32 v22, vcc_lo, s0, v23
	v_add_co_ci_u32_e32 v23, vcc_lo, s1, v38, vcc_lo
	s_waitcnt vmcnt(10)
	v_and_b32_e32 v41, 0xff, v27
	s_waitcnt vmcnt(7)
	v_add_nc_u32_e32 v33, v34, v33
	s_waitcnt vmcnt(6)
	v_and_b32_e32 v42, 0xff, v35
	v_add_nc_u32_e32 v34, v40, v39
	v_add_nc_u32_e32 v26, v41, v26
	v_add_nc_u32_e32 v39, v32, v41
	v_lshrrev_b32_e32 v38, 1, v33
	s_waitcnt vmcnt(5)
	v_add_nc_u32_e32 v36, v36, v42
	v_lshrrev_b32_e32 v40, 1, v26
	s_waitcnt vmcnt(3)
	v_add3_u32 v24, v34, v28, v24
	s_waitcnt vmcnt(1)
	v_add3_u32 v26, v26, v29, v32
	v_add_nc_u32_e32 v28, v36, v33
	s_waitcnt vmcnt(0)
	v_add3_u32 v25, v34, v25, v37
	v_lshrrev_b32_e32 v24, 2, v24
	v_lshrrev_b32_e32 v29, 1, v39
	v_lshrrev_b32_e32 v32, 1, v36
	v_lshrrev_b32_e32 v28, 2, v28
	v_lshrrev_b32_e32 v26, 2, v26
	v_lshrrev_b32_e32 v25, 2, v25
	s_clause 0xb
	global_store_b8 v[0:1], v40, off
	global_store_b8 v[2:3], v30, off
	global_store_b8 v[4:5], v38, off
	global_store_b8 v[6:7], v27, off
	global_store_b8 v[8:9], v24, off
	global_store_b8 v[10:11], v28, off
	global_store_b8 v[12:13], v26, off
	global_store_b8 v[14:15], v25, off
	global_store_b8 v[16:17], v35, off
	global_store_b8 v[18:19], v29, off
	global_store_b8 v[20:21], v31, off
	global_store_b8 v[22:23], v32, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24cudaProcessUnsignedChar0PhS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 43
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24cudaProcessUnsignedChar0PhS_ii, .Lfunc_end0-_Z24cudaProcessUnsignedChar0PhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1360
; NumSgprs: 18
; NumVgprs: 43
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 43
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24cudaProcessUnsignedChar0PhS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24cudaProcessUnsignedChar0PhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     43
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
