//##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research																														//
//																																																				//
//Copyright (c) <2012>, <Martin Peniak - www.martinpeniak.com>																																					//
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#include <cuda.h>
#include <cuda_runtime.h>

/*!
 * \brief Forward pass.
 * \note Used with forwardPassV21Kernel - faster version for networks of up to 1024 neurons.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] activity - activations
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] buffer - buffer used for storing new activations
 */
__global__ void forwardPassV2Kernel(int step, int sequenceOffset, float *activity, float *input, float *weight, int numNeurons, int numIONeurons, float *buffer)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;

    if(idx<numNeurons && j<numNeurons)
    {
        if(j<numIONeurons)
        {
            buffer[(j*numNeurons)+idx] = input[sequenceOffset+(numIONeurons*(step-1))+j] * weight[(j*numNeurons)+idx];
        }
        else
        {
            buffer[(j*numNeurons)+idx] = activity[(numNeurons*(step-1))+j] * weight[(j*numNeurons)+idx];
        }
    }
}

/*!
 * \brief Forward pass.
 * \note Used with forwardPassV2Kernel. Faster version for networks of up to 1024 neurons.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] deltaT - delta-t values
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] activity - activities
 * \param[out] error - errors
 */
__global__ void forwardPassV21Kernel(int step, int sequenceOffset, float *activity, float *input, float *buffer, float *potential, float *weight, float *previousPotential, float *error, int *deltaT, int numNeurons, int numIONeurons)
{
    extern __shared__ float sdata[];

    int tid = threadIdx.x;
    int i = blockDim.x/2;

    //init to zero
    sdata[tid] = 0.0;

    if(tid < numNeurons)
    {
        //load data
        sdata[tid] = buffer[(tid * numNeurons)+blockIdx.x];
        __syncthreads();

        while (i != 0)
        {
            if(tid < i)
            {
                //each thread puts its local sum into shared memory
                sdata[tid] += sdata[tid + i];
                __syncthreads();
            }
            i /= 2;
        }

        //write result for this block to global mem
        if (tid == 0)
        {
            potential[blockIdx.x] = sdata[0];

            //add bias to the activity
            potential[blockIdx.x] += weight[(numNeurons*numNeurons)+blockIdx.x];

            //calculate current membrane potential taking delta-t value as well as the previous membrane potential into account
            potential[blockIdx.x] = ((1.0f-(1.0f/(float)deltaT[blockIdx.x])) * previousPotential[blockIdx.x]) + ((1.0f/(float)deltaT[blockIdx.x])*potential[blockIdx.x]);

            //save current membrane potential for the next time step where it will be used as the previous membrane potential
            previousPotential[blockIdx.x] = potential[blockIdx.x];

            //sigmoid activation
            activity[(numNeurons*step)+blockIdx.x] = 1.0f/(1.0f+__expf(-potential[blockIdx.x]));

            //save error
            if(blockIdx.x<numIONeurons)
            {
                error[(numNeurons*step)+blockIdx.x] = activity[(numNeurons*step)+blockIdx.x] - input[sequenceOffset+(numIONeurons*(step+1))+blockIdx.x];
            }
        }
    }
}

/*!
 * \brief Forward pass.
 * \note Slower version for larger networks.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] deltaT - delta-t values
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] activity - activities
 * \param[out] error - errors
 */
__global__ void forwardPassV1Kernel(int step, int sequenceOffset, float *activity, float *input, float *weight, float *previousPotential, float *error, float *potential, int *deltaT, int numNeurons, int numIONeurons)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;
    float sum = 0.0;

    if(idx<numNeurons)
    {
        potential[idx] = 0.0;

        //calculates membrabe potential of a particular neuron given by the idx index
        for(int i=0; i<numNeurons; i++)
        {
            if(i<numIONeurons)
            {
                sum += input[sequenceOffset+(numIONeurons*(step-1))+i] * weight[(i*numNeurons)+idx];
            }
            else
            {
                sum += activity[(numNeurons*(step-1))+i] * weight[(i*numNeurons)+idx];
            }
        }

        //add bias to the activity
        sum += weight[(numNeurons*numNeurons)+idx];

        //calculate current membrane potential taking delta-t value as well as the previous membrane potential into account
        potential[idx] = ((1.0f-(1.0f/(float)deltaT[idx])) * previousPotential[idx]) + ((1.0f/(float)deltaT[idx])*sum);

        //save current membrane potential for the next time step where it will be used as the previous membrane potential
        previousPotential[idx] = potential[idx];

        //Sigmoid activation function
        activity[(numNeurons*step)+idx] = 1.0f/(1.0f+__expf(-potential[idx]));

        //save error
        if(idx<numIONeurons)
        {
            error[(numNeurons*step)+idx] = activity[(numNeurons*step)+idx] - input[sequenceOffset+(numIONeurons*(step+1))+idx];
        }

        sum = 0.0;
    }
}

/*!
 * \brief Calculates deltas, deltas on weights and errors parts.
 * \note Slower version for larger networks over 1024 neurons.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 */
__global__ void backwardPassV1Kernel(int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;

    if(idx<numIONeurons && j<numNeurons)
    {
        if(j==0)
        {
            individualError[idx] += ((input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]) * (input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]))/2.0f;
        }

        delta[idx] = error[(numNeurons*step)+idx] + (1.0f - (1.0f/deltaT[idx])) * previousDelta[idx];

        if(weight[(j*numNeurons)+idx]!=0)
        {
            deltaWeight[(j*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx] * activity[(numNeurons*(step-1))+j];
        }
    }
}

/*!
 * \brief Calculates deltas on hidden neurons.
 * \note Slower version for larger networks over 1024 neurons.
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-ouput neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 */
__global__ void backwardPassV11Kernel(int step,  int numNeurons, int numIONeurons,  float *activity, float *delta, float *previousDelta, int *deltaT, float *weight)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int kroneckerDelta;

    if(idx<numNeurons && idx>=numIONeurons)
    {
        delta[idx] = 0.0;

        for(int j=0; j<numNeurons; j++)
        {
            if(weight[(j*numNeurons)+idx]!=0)
            {
                //set Kronecker's delta
                if (idx==j)
                {
                    kroneckerDelta = 1;
                }
                else
                {
                    kroneckerDelta = 0;
                }

                //see bottom part of the equation 11 in Yamashita & Tani 2008 - SUM(k->N) of prev_hidden_delta * kroneckerDelta * (1-1/hidden-delta) + (1/delta-on-unit-k) * weight(ki) * derivative of activation of neuron i
                delta[idx] += previousDelta[j] * (kroneckerDelta * (1.0f - (1.0f/deltaT[idx])) + (1.0f/deltaT[j]) * weight[(idx*numNeurons)+j] * (activity[(numNeurons*step)+idx] * (1.0f - activity[(numNeurons*step)+idx])));
            }
        }
    }
}

/*!
 * \brief Loads the buffer with deltas on weights fractions calculate deltas, deltas on weights and errors parts.
 * \note Deltas on weights and errors are later summed by parallel reduction.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] previousDelta - previous deltas
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 * \param[out] buffer - buffer used for storing delta weights
 */
__global__ void backwardPassV2Kernel(int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight, float *buffer)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    int kroneckerDelta;

    if(idx<numNeurons && j<numNeurons)
    {
        if(idx<numIONeurons)
        {
            if(j==0)
            {
                individualError[idx] += ((input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]) * (input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]))/2.0f;
            }

            delta[idx] = error[(numNeurons*step)+idx] + (1.0f - (1.0f/deltaT[idx])) * previousDelta[idx];

            if(weight[(j*numNeurons)+idx]!=0)
            {
                //see eqaution 10 in Yamashita & Tani 2008 - SUM(t) of (1/fast-unit-delta)*delta-output(t) * fast-neuron-activity(t-1)
                deltaWeight[(j*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx] * activity[(numNeurons*(step-1))+j];
            }
        }
        else //load the buffer with deltas on weights fractions
        {
            buffer[(j*numNeurons)+idx] = 0.0;

            //calculate delta on weight if the two neurons are connected
            if(weight[(j*numNeurons)+idx]!=0)
            {
                //set Kronecker's delta
                if (idx==j)
                {
                    kroneckerDelta = 1;
                }
                else
                {
                    kroneckerDelta = 0;
                }

                //see bottom part of the equation 11 in Yamashita & Tani 2008 - SUM(k->N) of prev_hidden_delta * kroneckerDelta * (1-1/hidden-delta) + (1/delta-on-unit-k) * weight(ki) * derivative of activation of neuron i
                buffer[(j*numNeurons)+idx] = previousDelta[j] * (kroneckerDelta * (1.0f - (1.0f/deltaT[idx])) + (1.0f/deltaT[j]) * weight[(idx*numNeurons)+j] * (activity[(numNeurons*step)+idx] * (1.0f - activity[(numNeurons*step)+idx])));
            }
        }
    }
}

/*!
 * \brief Calculates deltas on hidden neurons.
 * \note Used together with backwardPassV2Kerne. Faster version for networks of up to 1024 neurons.
 * \param[in] input - input
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] output - output
 */
__global__ void backwardPassV21Kernel(float *input, float *output, int numNeurons, int numIONeurons)
{
    extern __shared__ float sdata[];

    int tid = threadIdx.x;
    int i = blockDim.x/2;

    //init to zero
    sdata[tid] = 0.0;

    if(tid<numNeurons)
    {
        //load data
        sdata[tid] = input[(tid * numNeurons)+(numIONeurons+blockIdx.x)];
        __syncthreads();

        while(i!=0)
        {
            if(tid<i)
            {
                //each thread puts its local sum into shared memory
                sdata[tid] += sdata[tid+i];
                __syncthreads();
            }
            i/=2;
        }

        //write result for this block to global memory
        if(tid==0)
        {
            output[numIONeurons+blockIdx.x] = sdata[0];
        }
    }
}

/*!
 * \brief Calculates deltas on weights on hidden neurons and biases.
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] deltaWeight - delta weights
 */
__global__ void backwardPassV3Kernel(int step, int numNeurons, int numIONeurons, float *activity, float *delta, float *previousDelta, float *deltaWeight, int *deltaT, float *weight)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;

    if(j<numNeurons && idx<numNeurons)
    {
        //calculate delta on weights for those neurons that are directly connected to hidden neurons
        if(idx>=numIONeurons)
        {
            if(weight[(j*numNeurons)+idx]!=0)
            {
                //see eqaution 10 in Yamashita & Tani 2008 - SUM(t) of (1/fast-unit-delta)*delta-output(t) * fast-neuron-activity(t-1)
                deltaWeight[(j*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx] * activity[(numNeurons*(step-1))+j];
            }
        }

        //calculate deltas on bias weights connecting to each neuron
        if(j==0)
        {
            deltaWeight[(numNeurons*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx];
            previousDelta[idx] = delta[idx];
        }
    }
}

/*!
 * \brief Updates weights.
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] numWeights - number of weights
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] weight - weights
 */
__global__ void updateWeightsKernel(float learningRate, float momentum, float *weight, float *deltaWeight, float *previousDeltaWeight, int numWeights)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        weight[idx] -= ((learningRate * deltaWeight[idx]) + (momentum * previousDeltaWeight[idx]));
        previousDeltaWeight[idx] = deltaWeight[idx];
    }
}

/*!
 * \brief Sums delta weights on the master device.
 * \param[in] numWeights - number of weights
 * \param[in] peerDeltaWeight - delta weights from peer device
 * \param[out] masterDeltaWeight - delta weights from master device
 */
__global__ void sumDeltaWeightsP2PKernel(int numWeights, float *masterDeltaWeight, float *peerDeltaWeight)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        masterDeltaWeight[idx] += peerDeltaWeight[idx];
    }
}

/*!
 * \brief Modifies weights on the master device and copies to the peer device.
 * \param[in] numWeights - number of weights
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] masterWeight - weigths from master device
 * \param[out] peerWeight - weights from peer device
 */
__global__ void updateWeightsP2PKernel(int numWeights, float learningRate, float momentum, float *masterWeight, float *peerWeight, float *deltaWeight, float *previousDeltaWeight)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        masterWeight[idx] -= ((learningRate * deltaWeight[idx]) + (momentum * previousDeltaWeight[idx]));
        peerWeight[idx] = masterWeight[idx];
        previousDeltaWeight[idx] = deltaWeight[idx];
    }
}

/*!
 * \brief Modifies weights on the master device and copies to the peer device.
 * \param[in] peerError - error from peer device
 * \param[out] masterError - error from master device
 */
__global__ void sumErrorP2PKernel(float *masterError, float *peerError)
{
    if(threadIdx.x==0)
    {
        masterError[0] += peerError[0];
    }
}

/*!
 * \brief Sets the initial states for all the units on device.
 * \note Slow context units will be initialised with a specific value.
 * \param[in] initState - initial state
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] numFastNeurons - number of fast neurons
 * \param[out] activity - activities
 */
__global__  void setInitStatesKernel(float initState, float *activity, int numNeurons, int numIONeurons, int numFastNeurons)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;

    if(idx<numNeurons)
    {
        if(idx>=numIONeurons+numFastNeurons && idx<numIONeurons+numFastNeurons+5)
        {
            activity[idx] = initState;
        }
        else
        {
            activity[idx] = 0.0;
        }
    }
}

/*!
 * \brief Resets delta and error parameters.
 * \param[in] numNeurons - number of neurons
 * \param[in] maxSequenceSteps - maximum number of sequence steps
 * \param[out] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] error - errors
 */
__global__ void resetParametersKernel(int numNeurons, int maxSequenceSteps, float *delta, float *previousDelta, float *potential, float *previousPotential, float *error)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;

    if(idx<(numNeurons*maxSequenceSteps))
    {
        if(idx<numNeurons)
        {
            delta[idx] = 0.0;
            previousDelta[idx] = 0.0;
            potential[idx] = 0.0;
            previousPotential[idx] = 0.0;
        }

        error[idx] = 0.0;
    }
}

/*!
 * \brief Resets delta weights and errors.
 * \param[in] numWeights - number of weights
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] deltaWeight - delta weights
 * \param[out] individualError - error buffer
 */
__global__ void resetDeltaWeightsKernel(int numWeights, int numIONeurons, float *deltaWeight, float *individualError)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        deltaWeight[idx] = 0.0;

        if(idx<numIONeurons)
        {
            individualError[idx] = 0.0;
        }
    }
}

/*!
 * \brief Parallel reduction sum modified from NVIDIA SDK.
 * \note Number of threads are not known at a compile time, however, we always stick to power of 2 sizes
 * \note so here we are using templates to allow compilation for all known size, which results in higher throughput.
 * \param[in] input - input
 * \param[in] n - number of elements to sum
 * \param[in] nIsPow2 - determines if the number is of power of two
 * \param[out] output - output
 */
template <unsigned int blockSize> __global__ void reduceKernel(float *input, float *output, unsigned int n, bool nIsPow2)
{
    extern __shared__ float sdata[];

    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*blockSize*2 + threadIdx.x;
    unsigned int gridSize = blockSize*2*gridDim.x;

    float sum = 0.0;

    //perform first level of reduction, reading from global memory, writing to shared memory
    //we reduce multiple elements per thread.  The number is determined by the number of active thread blocks (via gridDim).
    //More blocks will result in a larger gridSize and therefore fewer elements per thread
    while(i<n)
    {
        sum += input[i];

        //ensure we don't read out of bounds -- this is optimised away for powerOf2 sized arrays
        if (nIsPow2 || (i+blockSize)<n)
        {
            sum += input[i+blockSize];
        }

        i+=gridSize;
    }

    //each thread puts its local sum into shared memory
    sdata[tid] = sum;
    __syncthreads();

    //do reduction in shared mem
    if (blockSize >= 512) { if (tid < 256) { sdata[tid] = sum = sum + sdata[tid + 256]; } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128) { sdata[tid] = sum = sum + sdata[tid + 128]; } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64) { sdata[tid] = sum = sum + sdata[tid +  64]; } __syncthreads(); }

    if(tid<32)
    {
        //now that we are using warp-synchronous programming (below) we need to declare our shared memory
        //volatile so that the compiler doesn't reorder stores to it and induce incorrect behavior
        volatile float* smem = sdata;
        if (blockSize>=64)
        {
            smem[tid] = sum = sum + smem[tid+32];
        }

        if (blockSize>=32)
        {
            smem[tid] = sum = sum + smem[tid+16];
        }

        if (blockSize>=16)
        {
            smem[tid] = sum = sum + smem[tid+8];
        }

        if (blockSize>=8)
        {
            smem[tid] = sum = sum + smem[tid+4];
        }

        if (blockSize>=4)
        {
            smem[tid] = sum = sum + smem[tid+2];
        }

        if (blockSize>=2)
        {
            smem[tid] = sum = sum + smem[tid+1];
        }
    }

    //write result for this block to global mem
    if(tid==0)
    {
        output[blockIdx.x] = sdata[0];
    }
}

/*!
 * \brief Wrapper for resetDeltaWeightsKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] numWeights - number of weights
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] deltaWeight - delta weights
 * \param[out] individualError - error buffer
 */
void resetDeltaWeightsOnDevice(dim3 grid, dim3 block, cudaStream_t stream, int numWeights, int numIONeurons, float *deltaWeight, float *individualError)
{
    resetDeltaWeightsKernel<<<grid,block,0,stream>>>(numWeights, numIONeurons, deltaWeight, individualError);
}

/*!
 * \brief Wrapper for setInitStatesKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] initState - initial state
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] numFastNeurons - number of fast neurons
 * \param[out] activity - activities
 */
void setInitStatesOnDevice(dim3 grid, dim3 block, cudaStream_t stream, float initState, float *activity, int numNeurons, int numIONeurons, int numFastNeurons)
{
    setInitStatesKernel<<<grid,block,0,stream>>>(initState, activity, numNeurons, numIONeurons, numFastNeurons);
}

/*!
 * \brief Wrapper for resetParametersKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] numNeurons - number of neurons
 * \param[in] maxSequenceSteps - maximum number of sequence steps
 * \param[out] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] error - errors
 */
void resetParametersOnDevice(dim3 grid, dim3 block, cudaStream_t stream, int numNeurons, int maxSequenceSteps, float *delta, float *previousDelta, float *potential, float *previousPotential, float *error)
{
    resetParametersKernel<<<grid,block,0,stream>>>(numNeurons, maxSequenceSteps, delta, previousDelta, potential, previousPotential, error);
}

/*!
 * \brief Wrapper for updateWeightsKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] numWeights - number of weights
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] weight - weights
 */
void updateWeightsOnDevice(dim3 grid, dim3 block, float learningRate, float momentum, float *weight, float *deltaWeight, float *previousDeltaWeight, int numWeights)
{
    updateWeightsKernel<<<grid,block>>>(learningRate, momentum, weight, deltaWeight, previousDeltaWeight, numWeights);
}

/*!
 * \brief Wrapper for forwardPassV1Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] deltaT - delta-t values
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] activity - activities
 * \param[out] error - errors
 */
void forwardPassV1onDevice(dim3 grid, dim3 block, cudaStream_t stream, int step, int sequenceOffset, float *activity, float *input, float *weight, float *previousPotential, float *error, float *potential, int *deltaT, int numNeurons, int numIONeurons)
{
    forwardPassV1Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, activity, input, weight, previousPotential, error, potential, deltaT, numNeurons, numIONeurons);
}

/*!
 * \brief Wrapper for forwardPassV2Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] activity - activations
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] buffer - buffer used for storing new activations
 */
void forwardPassV2onDevice(dim3 grid, dim3 block, cudaStream_t stream, int step, int sequenceOffset, float *activity, float *input, float *weight, int numNeurons, int numIONeurons, float *buffer)
{
    forwardPassV2Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, activity, input, weight, numNeurons, numIONeurons, buffer);
}

/*!
 * \brief Wrapper for forwardPassV21Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] smemSize - CUDA shared memory size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] activity - activations
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] buffer - buffer used for storing new activations
 */
void forwardPassV21onDevice(dim3 grid, dim3 block, int smemSize, cudaStream_t stream, int step, int sequenceOffset, float *activity, float *input, float *buffer, float *potential, float *weight, float *previousPotential, float *error, int *deltaT, int numNeurons, int numIONeurons)
{
    forwardPassV21Kernel<<<grid,block,smemSize,stream>>>(step, sequenceOffset, activity, input, buffer, potential, weight, previousPotential, error, deltaT, numNeurons, numIONeurons);
}

/*!
 * \brief Wrapper for backwardPassV1Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 */
void backwardPassV1onDevice(dim3 grid, dim3 block, cudaStream_t stream, int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight)
{
    backwardPassV1Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, numNeurons, numIONeurons, input, activity, delta, deltaWeight, previousDelta, error, individualError, deltaT, weight);
}

/*!
 * \brief Wrapper for backwardPassV11Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-ouput neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 */
void backwardPassV11onDevice(dim3 grid, dim3 block, cudaStream_t stream, int step,  int numNeurons, int numIONeurons,  float *activity, float *delta, float *previousDelta, int *deltaT, float *weight)
{
    backwardPassV11Kernel<<<grid,block,0,stream>>>(step,  numNeurons, numIONeurons,  activity, delta, previousDelta, deltaT, weight);
}

/*!
 * \brief Wrapper for backwardPassV2Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] previousDelta - previous deltas
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 * \param[out] buffer - buffer used for storing delta weights
 */
void backwardPassV2onDevice(dim3 grid, dim3 block, cudaStream_t stream, int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight, float *buffer)
{
    backwardPassV2Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, numNeurons, numIONeurons, input, activity, delta, deltaWeight, previousDelta, error, individualError, deltaT, weight, buffer);
}

/*!
 * \brief Wrapper for backwardPassV21Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] smemSize - CUDA shared memory size
 * \param[in] stream - CUDA stream
 * \param[in] input - input
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] output - output
 */
void backwardPassV21onDevice(dim3 grid, dim3 block, int smemSize, cudaStream_t stream, float *input, float *output, int numNeurons, int numIONeurons)
{
    backwardPassV21Kernel<<<grid,block,smemSize,stream>>>(input, output, numNeurons, numIONeurons);
}

/*!
 * \brief Wrapper for backwardPassV3Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] deltaWeight - delta weights
 */
void backwardPassV3onDevice(dim3 grid, dim3 block, cudaStream_t stream, int step, int numNeurons, int numIONeurons, float *activity, float *delta, float *previousDelta, float *deltaWeight, int *deltaT, float *weight)
{
    backwardPassV3Kernel<<<grid,block,0,stream>>>(step, numNeurons, numIONeurons, activity, delta, previousDelta, deltaWeight, deltaT, weight);
}

/*!
 * \brief Wrapper for reduceKernel.
 * \param[in] size - number of elements to sum
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] smemSize - CUDA shared memory size
 * \param[in] stream - CUDA stream
 * \param[in] input - input
 * \param[in] n - number of elements to sum
 * \param[in] nIsPow2 - determines if the number is of power of two
 * \param[out] output - output
 */
void reduceOnDevice(int size, dim3 grid, dim3 block, int smemSize, cudaStream_t stream, float *input, float *output, unsigned int n, bool nIsPow2)
{
    switch(size)
    {
        case 512:
            reduceKernel<512><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 256:
            reduceKernel<256><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 128:
            reduceKernel<128><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 64:
            reduceKernel<64><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 32:
            reduceKernel<32><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 16:
            reduceKernel<16><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  8:
            reduceKernel<8><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  4:
            reduceKernel<4><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  2:
            reduceKernel<2><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  1:
            reduceKernel<1><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;
    }
}

/*!
 * \brief Wrapper for sumDeltaWeightsP2PKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] numWeights - number of weights
 * \param[in] peerDeltaWeight - delta weights from peer device
 * \param[out] masterDeltaWeight - delta weights from master device
 */
void sumDeltaWeightsP2PonDevice(dim3 grid, dim3 block, int numWeights, float *masterDeltaWeight, float *peerDeltaWeight)
{
    sumDeltaWeightsP2PKernel<<<grid,block>>>(numWeights, masterDeltaWeight, peerDeltaWeight);
}

/*!
 * \brief Wrapper for updateWeightsP2PKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] numWeights - number of weights
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] masterWeight - weigths from master device
 * \param[out] peerWeight - weights from peer device
 */
void updateWeightsP2PonDevice(dim3 grid, dim3 block, int numWeights, float learningRate, float momentum, float *masterWeight, float *peerWeight, float *deltaWeight, float *previousDeltaWeight)
{
    updateWeightsP2PKernel<<<grid,block>>>(numWeights, learningRate, momentum, masterWeight, peerWeight, deltaWeight, previousDeltaWeight);
}

/*!
 * \brief Wrapper for sumErrorP2PKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] peerError - error from peer device
 * \param[out] masterError - error from master device
 */
void sumErrorP2PonDevice(dim3 grid, dim3 block, float *masterError, float *peerError)
{
    sumErrorP2PKernel<<<grid,block>>>(masterError, peerError);
}


	.file	"tmpxft_00347772_00000000-6_mtrnnKernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2028:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2227:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2227:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.type	_ZL44__device_stub__Z12reduceKernelILj1EEvPfS0_jbPfS_jb, @function
_ZL44__device_stub__Z12reduceKernelILj1EEvPfS0_jbPfS_jb:
.LFB2098:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj1EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2098:
	.size	_ZL44__device_stub__Z12reduceKernelILj1EEvPfS0_jbPfS_jb, .-_ZL44__device_stub__Z12reduceKernelILj1EEvPfS0_jbPfS_jb
	.type	_ZL44__device_stub__Z12reduceKernelILj2EEvPfS0_jbPfS_jb, @function
_ZL44__device_stub__Z12reduceKernelILj2EEvPfS0_jbPfS_jb:
.LFB2096:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj2EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2096:
	.size	_ZL44__device_stub__Z12reduceKernelILj2EEvPfS0_jbPfS_jb, .-_ZL44__device_stub__Z12reduceKernelILj2EEvPfS0_jbPfS_jb
	.type	_ZL44__device_stub__Z12reduceKernelILj4EEvPfS0_jbPfS_jb, @function
_ZL44__device_stub__Z12reduceKernelILj4EEvPfS0_jbPfS_jb:
.LFB2094:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj4EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2094:
	.size	_ZL44__device_stub__Z12reduceKernelILj4EEvPfS0_jbPfS_jb, .-_ZL44__device_stub__Z12reduceKernelILj4EEvPfS0_jbPfS_jb
	.type	_ZL44__device_stub__Z12reduceKernelILj8EEvPfS0_jbPfS_jb, @function
_ZL44__device_stub__Z12reduceKernelILj8EEvPfS0_jbPfS_jb:
.LFB2092:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj8EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2092:
	.size	_ZL44__device_stub__Z12reduceKernelILj8EEvPfS0_jbPfS_jb, .-_ZL44__device_stub__Z12reduceKernelILj8EEvPfS0_jbPfS_jb
	.type	_ZL45__device_stub__Z12reduceKernelILj16EEvPfS0_jbPfS_jb, @function
_ZL45__device_stub__Z12reduceKernelILj16EEvPfS0_jbPfS_jb:
.LFB2090:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj16EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L20:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2090:
	.size	_ZL45__device_stub__Z12reduceKernelILj16EEvPfS0_jbPfS_jb, .-_ZL45__device_stub__Z12reduceKernelILj16EEvPfS0_jbPfS_jb
	.type	_ZL45__device_stub__Z12reduceKernelILj32EEvPfS0_jbPfS_jb, @function
_ZL45__device_stub__Z12reduceKernelILj32EEvPfS0_jbPfS_jb:
.LFB2088:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj32EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L24:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2088:
	.size	_ZL45__device_stub__Z12reduceKernelILj32EEvPfS0_jbPfS_jb, .-_ZL45__device_stub__Z12reduceKernelILj32EEvPfS0_jbPfS_jb
	.type	_ZL45__device_stub__Z12reduceKernelILj64EEvPfS0_jbPfS_jb, @function
_ZL45__device_stub__Z12reduceKernelILj64EEvPfS0_jbPfS_jb:
.LFB2086:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj64EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L28:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2086:
	.size	_ZL45__device_stub__Z12reduceKernelILj64EEvPfS0_jbPfS_jb, .-_ZL45__device_stub__Z12reduceKernelILj64EEvPfS0_jbPfS_jb
	.type	_ZL46__device_stub__Z12reduceKernelILj128EEvPfS0_jbPfS_jb, @function
_ZL46__device_stub__Z12reduceKernelILj128EEvPfS0_jbPfS_jb:
.LFB2084:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj128EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L32:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2084:
	.size	_ZL46__device_stub__Z12reduceKernelILj128EEvPfS0_jbPfS_jb, .-_ZL46__device_stub__Z12reduceKernelILj128EEvPfS0_jbPfS_jb
	.type	_ZL46__device_stub__Z12reduceKernelILj256EEvPfS0_jbPfS_jb, @function
_ZL46__device_stub__Z12reduceKernelILj256EEvPfS0_jbPfS_jb:
.LFB2082:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj256EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L36:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2082:
	.size	_ZL46__device_stub__Z12reduceKernelILj256EEvPfS0_jbPfS_jb, .-_ZL46__device_stub__Z12reduceKernelILj256EEvPfS0_jbPfS_jb
	.type	_ZL46__device_stub__Z12reduceKernelILj512EEvPfS0_jbPfS_jb, @function
_ZL46__device_stub__Z12reduceKernelILj512EEvPfS0_jbPfS_jb:
.LFB2080:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movb	%cl, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12reduceKernelILj512EEvPfS0_jb(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L40:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2080:
	.size	_ZL46__device_stub__Z12reduceKernelILj512EEvPfS0_jbPfS_jb, .-_ZL46__device_stub__Z12reduceKernelILj512EEvPfS0_jbPfS_jb
	.section	.text._Z12reduceKernelILj1EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj1EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj1EEvPfS0_jb
	.type	_Z12reduceKernelILj1EEvPfS0_jb, @function
_Z12reduceKernelILj1EEvPfS0_jb:
.LFB2156:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL44__device_stub__Z12reduceKernelILj1EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2156:
	.size	_Z12reduceKernelILj1EEvPfS0_jb, .-_Z12reduceKernelILj1EEvPfS0_jb
	.section	.text._Z12reduceKernelILj512EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj512EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj512EEvPfS0_jb
	.type	_Z12reduceKernelILj512EEvPfS0_jb, @function
_Z12reduceKernelILj512EEvPfS0_jb:
.LFB2147:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL46__device_stub__Z12reduceKernelILj512EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2147:
	.size	_Z12reduceKernelILj512EEvPfS0_jb, .-_Z12reduceKernelILj512EEvPfS0_jb
	.section	.text._Z12reduceKernelILj256EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj256EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj256EEvPfS0_jb
	.type	_Z12reduceKernelILj256EEvPfS0_jb, @function
_Z12reduceKernelILj256EEvPfS0_jb:
.LFB2148:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL46__device_stub__Z12reduceKernelILj256EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2148:
	.size	_Z12reduceKernelILj256EEvPfS0_jb, .-_Z12reduceKernelILj256EEvPfS0_jb
	.section	.text._Z12reduceKernelILj128EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj128EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj128EEvPfS0_jb
	.type	_Z12reduceKernelILj128EEvPfS0_jb, @function
_Z12reduceKernelILj128EEvPfS0_jb:
.LFB2149:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL46__device_stub__Z12reduceKernelILj128EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2149:
	.size	_Z12reduceKernelILj128EEvPfS0_jb, .-_Z12reduceKernelILj128EEvPfS0_jb
	.section	.text._Z12reduceKernelILj64EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj64EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj64EEvPfS0_jb
	.type	_Z12reduceKernelILj64EEvPfS0_jb, @function
_Z12reduceKernelILj64EEvPfS0_jb:
.LFB2150:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL45__device_stub__Z12reduceKernelILj64EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2150:
	.size	_Z12reduceKernelILj64EEvPfS0_jb, .-_Z12reduceKernelILj64EEvPfS0_jb
	.section	.text._Z12reduceKernelILj32EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj32EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj32EEvPfS0_jb
	.type	_Z12reduceKernelILj32EEvPfS0_jb, @function
_Z12reduceKernelILj32EEvPfS0_jb:
.LFB2151:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL45__device_stub__Z12reduceKernelILj32EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2151:
	.size	_Z12reduceKernelILj32EEvPfS0_jb, .-_Z12reduceKernelILj32EEvPfS0_jb
	.section	.text._Z12reduceKernelILj16EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj16EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj16EEvPfS0_jb
	.type	_Z12reduceKernelILj16EEvPfS0_jb, @function
_Z12reduceKernelILj16EEvPfS0_jb:
.LFB2152:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL45__device_stub__Z12reduceKernelILj16EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2152:
	.size	_Z12reduceKernelILj16EEvPfS0_jb, .-_Z12reduceKernelILj16EEvPfS0_jb
	.section	.text._Z12reduceKernelILj8EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj8EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj8EEvPfS0_jb
	.type	_Z12reduceKernelILj8EEvPfS0_jb, @function
_Z12reduceKernelILj8EEvPfS0_jb:
.LFB2153:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL44__device_stub__Z12reduceKernelILj8EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2153:
	.size	_Z12reduceKernelILj8EEvPfS0_jb, .-_Z12reduceKernelILj8EEvPfS0_jb
	.section	.text._Z12reduceKernelILj4EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj4EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj4EEvPfS0_jb
	.type	_Z12reduceKernelILj4EEvPfS0_jb, @function
_Z12reduceKernelILj4EEvPfS0_jb:
.LFB2154:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL44__device_stub__Z12reduceKernelILj4EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2154:
	.size	_Z12reduceKernelILj4EEvPfS0_jb, .-_Z12reduceKernelILj4EEvPfS0_jb
	.section	.text._Z12reduceKernelILj2EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj2EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj2EEvPfS0_jb
	.type	_Z12reduceKernelILj2EEvPfS0_jb, @function
_Z12reduceKernelILj2EEvPfS0_jb:
.LFB2155:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	jmp	_ZL44__device_stub__Z12reduceKernelILj2EEvPfS0_jbPfS_jb
	.cfi_endproc
.LFE2155:
	.size	_Z12reduceKernelILj2EEvPfS0_jb, .-_Z12reduceKernelILj2EEvPfS0_jb
	.text
	.globl	_Z14reduceOnDevicei4dim3S_iP11CUstream_stPfS2_jb
	.type	_Z14reduceOnDevicei4dim3S_iP11CUstream_stPfS2_jb, @function
_Z14reduceOnDevicei4dim3S_iP11CUstream_stPfS2_jb:
.LFB2022:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edi, %r10d
	movl	%r9d, %eax
	movq	%rsi, %rdi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%edx, %esi
	movq	%rcx, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	80(%rsp), %r9
	movq	88(%rsp), %rbp
	movl	%r8d, 8(%rsp)
	movq	96(%rsp), %r12
	movl	104(%rsp), %r13d
	movl	112(%rsp), %ebx
	cmpl	$32, %r10d
	je	.L55
	jg	.L56
	cmpl	$4, %r10d
	je	.L57
	jg	.L58
	cmpl	$1, %r10d
	je	.L59
	cmpl	$2, %r10d
	je	.L60
	jmp	.L54
.L58:
	cmpl	$8, %r10d
	je	.L62
	cmpl	$16, %r10d
	je	.L63
	jmp	.L54
.L56:
	cmpl	$256, %r10d
	je	.L64
	jg	.L65
	cmpl	$64, %r10d
	je	.L66
	cmpl	$128, %r10d
	je	.L67
	jmp	.L54
.L65:
	cmpl	$512, %r10d
	jne	.L54
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z12reduceKernelILj512EEvPfS0_jbPfS_jb
.L64:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z12reduceKernelILj256EEvPfS0_jbPfS_jb
.L67:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z12reduceKernelILj128EEvPfS0_jbPfS_jb
.L66:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z12reduceKernelILj64EEvPfS0_jbPfS_jb
.L55:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z12reduceKernelILj32EEvPfS0_jbPfS_jb
.L63:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z12reduceKernelILj16EEvPfS0_jbPfS_jb
.L62:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z12reduceKernelILj8EEvPfS0_jbPfS_jb
.L57:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z12reduceKernelILj4EEvPfS0_jbPfS_jb
.L60:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z12reduceKernelILj2EEvPfS0_jbPfS_jb
.L59:
	.cfi_restore_state
	movl	8(%rsp), %ecx
	movslq	%eax, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movzbl	%bl, %ecx
	movl	%r13d, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z12reduceKernelILj1EEvPfS0_jbPfS_jb
.L54:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2022:
	.size	_Z14reduceOnDevicei4dim3S_iP11CUstream_stPfS2_jb, .-_Z14reduceOnDevicei4dim3S_iP11CUstream_stPfS2_jb
	.globl	_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_
	.type	_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_, @function
_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_:
.LFB2050:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	184(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z19forwardPassV2KerneliiPfS_S_iiS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L71:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L73
	call	__stack_chk_fail@PLT
.L73:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_, .-_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_
	.globl	_Z19forwardPassV2KerneliiPfS_S_iiS_
	.type	_Z19forwardPassV2KerneliiPfS_S_iiS_, @function
_Z19forwardPassV2KerneliiPfS_S_iiS_:
.LFB2051:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_
	.cfi_endproc
.LFE2051:
	.size	_Z19forwardPassV2KerneliiPfS_S_iiS_, .-_Z19forwardPassV2KerneliiPfS_S_iiS_
	.globl	_Z21forwardPassV2onDevice4dim3S_P11CUstream_stiiPfS2_S2_iiS2_
	.type	_Z21forwardPassV2onDevice4dim3S_P11CUstream_stiiPfS2_S2_iiS2_, @function
_Z21forwardPassV2onDevice4dim3S_P11CUstream_stiiPfS2_S2_iiS2_:
.LFB2015:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	112(%rsp), %eax
	movl	%r9d, 8(%rsp)
	movq	%r8, %r9
	xorl	%r8d, %r8d
	movq	120(%rsp), %r12
	movq	128(%rsp), %r13
	movl	%eax, 12(%rsp)
	movq	136(%rsp), %r14
	movl	144(%rsp), %r15d
	movl	152(%rsp), %ebx
	movq	160(%rsp), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	movq	%rbp, 120(%rsp)
	movl	12(%rsp), %esi
	movl	%r15d, %r9d
	movq	%r14, %r8
	movl	%ebx, 112(%rsp)
	movl	8(%rsp), %edi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%r12, %rdx
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z49__device_stub__Z19forwardPassV2KerneliiPfS_S_iiS_iiPfS_S_iiS_
.L76:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2015:
	.size	_Z21forwardPassV2onDevice4dim3S_P11CUstream_stiiPfS2_S2_iiS2_, .-_Z21forwardPassV2onDevice4dim3S_P11CUstream_stiiPfS2_S2_iiS2_
	.globl	_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii
	.type	_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii, @function
_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 64(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 56(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	264(%rsp), %rax
	movq	%r8, 48(%rsp)
	movq	%r9, 40(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 120(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	136(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L79:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L81
	call	__stack_chk_fail@PLT
.L81:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii, .-_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii
	.globl	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.type	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, @function
_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii
	.cfi_endproc
.LFE2053:
	.size	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, .-_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.globl	_Z22forwardPassV21onDevice4dim3S_iP11CUstream_stiiPfS2_S2_S2_S2_S2_S2_Piii
	.type	_Z22forwardPassV21onDevice4dim3S_iP11CUstream_stiiPfS2_S2_S2_S2_S2_S2_Piii, @function
_Z22forwardPassV21onDevice4dim3S_iP11CUstream_stiiPfS2_S2_S2_S2_S2_S2_Piii:
.LFB2016:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	movslq	%r8d, %r8
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	144(%rsp), %eax
	movq	192(%rsp), %r12
	movq	200(%rsp), %r13
	movq	208(%rsp), %r14
	movl	%eax, 8(%rsp)
	movl	152(%rsp), %eax
	movq	216(%rsp), %r15
	movl	224(%rsp), %ebx
	movl	%eax, 12(%rsp)
	movq	160(%rsp), %rax
	movl	232(%rsp), %ebp
	movq	%rax, 16(%rsp)
	movq	168(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	176(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	184(%rsp), %rax
	movq	%rax, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L84
	movl	%ebp, 184(%rsp)
	movq	40(%rsp), %r9
	movl	%ebx, 176(%rsp)
	movq	32(%rsp), %r8
	movq	%r15, 168(%rsp)
	movq	24(%rsp), %rcx
	movq	%r14, 160(%rsp)
	movq	16(%rsp), %rdx
	movl	12(%rsp), %esi
	movl	8(%rsp), %edi
	movq	%r13, 152(%rsp)
	movq	%r12, 144(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z58__device_stub__Z20forwardPassV21KerneliiPfS_S_S_S_S_S_PiiiiiPfS_S_S_S_S_S_Piii
.L84:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2016:
	.size	_Z22forwardPassV21onDevice4dim3S_iP11CUstream_stiiPfS2_S2_S2_S2_S2_S2_Piii, .-_Z22forwardPassV21onDevice4dim3S_iP11CUstream_stiiPfS2_S2_S2_S2_S2_S2_Piii
	.globl	_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii
	.type	_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii, @function
_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	240(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L87
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L87:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L89
	call	__stack_chk_fail@PLT
.L89:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii, .-_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii
	.globl	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.type	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii, @function
_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii
	.cfi_endproc
.LFE2055:
	.size	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii, .-_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.globl	_Z21forwardPassV1onDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_S2_Piii
	.type	_Z21forwardPassV1onDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_S2_Piii, @function
_Z21forwardPassV1onDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_S2_Piii:
.LFB2014:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	128(%rsp), %eax
	movl	%r9d, (%rsp)
	movq	%r8, %r9
	xorl	%r8d, %r8d
	movq	160(%rsp), %r12
	movq	168(%rsp), %r13
	movl	%eax, 4(%rsp)
	movq	136(%rsp), %rax
	movq	176(%rsp), %r14
	movq	184(%rsp), %r15
	movq	%rax, 8(%rsp)
	movq	144(%rsp), %rax
	movl	192(%rsp), %ebx
	movl	200(%rsp), %ebp
	movq	%rax, 16(%rsp)
	movq	152(%rsp), %rax
	movq	%rax, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L92
	movl	%ebp, 160(%rsp)
	movq	24(%rsp), %r8
	movq	%r12, %r9
	movl	%ebx, 152(%rsp)
	movq	16(%rsp), %rcx
	movq	%r15, 144(%rsp)
	movq	8(%rsp), %rdx
	movl	4(%rsp), %esi
	movl	(%rsp), %edi
	movq	%r14, 136(%rsp)
	movq	%r13, 128(%rsp)
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z19forwardPassV1KerneliiPfS_S_S_S_S_PiiiiiPfS_S_S_S_S_Piii
.L92:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2014:
	.size	_Z21forwardPassV1onDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_S2_Piii, .-_Z21forwardPassV1onDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_S2_Piii
	.globl	_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_
	.type	_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_, @function
_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	296(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	304(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	320(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L95
	pushq	112(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 288
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	160(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L95:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L97
	call	__stack_chk_fail@PLT
.L97:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_, .-_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_
	.globl	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.type	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, @function
_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_
	.cfi_endproc
.LFE2057:
	.size	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, .-_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.globl	_Z22backwardPassV1onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_
	.type	_Z22backwardPassV1onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_, @function
_Z22backwardPassV1onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_:
.LFB2017:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	144(%rsp), %eax
	movq	232(%rsp), %r11
	movl	%r9d, 8(%rsp)
	movq	%r8, %r9
	xorl	%r8d, %r8d
	movq	184(%rsp), %rbx
	movq	192(%rsp), %r12
	movl	%eax, 12(%rsp)
	movl	152(%rsp), %eax
	movq	200(%rsp), %r13
	movq	208(%rsp), %r14
	movl	%eax, 16(%rsp)
	movl	160(%rsp), %eax
	movq	216(%rsp), %r15
	movq	224(%rsp), %rbp
	movl	%eax, 20(%rsp)
	movq	168(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	176(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	%r11, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	40(%rsp), %r11
	testl	%eax, %eax
	jne	.L100
	movq	%rbp, 184(%rsp)
	movq	32(%rsp), %r9
	movq	%r15, 176(%rsp)
	movq	24(%rsp), %r8
	movq	%r14, 168(%rsp)
	movl	20(%rsp), %ecx
	movq	%r13, 160(%rsp)
	movl	16(%rsp), %edx
	movl	12(%rsp), %esi
	movl	8(%rsp), %edi
	movq	%r12, 152(%rsp)
	movq	%rbx, 144(%rsp)
	movq	%r11, 192(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z60__device_stub__Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_iiiiPfS_S_S_S_S_S_PiS_
.L100:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2017:
	.size	_Z22backwardPassV1onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_, .-_Z22backwardPassV1onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_
	.globl	_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_
	.type	_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_, @function
_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	200(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 104(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L103
	pushq	72(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21backwardPassV11KerneliiiPfS_S_PiS_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 208
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	120(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L103:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L105
	call	__stack_chk_fail@PLT
.L105:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_, .-_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_
	.globl	_Z21backwardPassV11KerneliiiPfS_S_PiS_
	.type	_Z21backwardPassV11KerneliiiPfS_S_PiS_, @function
_Z21backwardPassV11KerneliiiPfS_S_PiS_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_
	.cfi_endproc
.LFE2059:
	.size	_Z21backwardPassV11KerneliiiPfS_S_PiS_, .-_Z21backwardPassV11KerneliiiPfS_S_PiS_
	.globl	_Z23backwardPassV11onDevice4dim3S_P11CUstream_stiiiPfS2_S2_PiS2_
	.type	_Z23backwardPassV11onDevice4dim3S_P11CUstream_stiiiPfS2_S2_PiS2_, @function
_Z23backwardPassV11onDevice4dim3S_P11CUstream_stiiiPfS2_S2_PiS2_:
.LFB2018:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	112(%rsp), %eax
	movl	%r9d, 8(%rsp)
	movq	%r8, %r9
	xorl	%r8d, %r8d
	movl	120(%rsp), %r12d
	movq	128(%rsp), %r13
	movl	%eax, 12(%rsp)
	movq	136(%rsp), %r14
	movq	144(%rsp), %r15
	movq	152(%rsp), %rbx
	movq	160(%rsp), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L108
	movq	%rbp, 120(%rsp)
	movl	12(%rsp), %esi
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%rbx, 112(%rsp)
	movl	8(%rsp), %edi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	%r12d, %edx
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z52__device_stub__Z21backwardPassV11KerneliiiPfS_S_PiS_iiiPfS_S_PiS_
.L108:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2018:
	.size	_Z23backwardPassV11onDevice4dim3S_P11CUstream_stiiiPfS2_S2_PiS2_, .-_Z23backwardPassV11onDevice4dim3S_P11CUstream_stiiiPfS2_S2_PiS2_
	.globl	_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_
	.type	_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_, @function
_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	112(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	96(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	104(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	296(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	304(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	320(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	328(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L111
	pushq	104(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 288
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	152(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L111:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L113
	call	__stack_chk_fail@PLT
.L113:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_, .-_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_
	.globl	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.type	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, @function
_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_
	.cfi_endproc
.LFE2061:
	.size	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, .-_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.globl	_Z22backwardPassV2onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_
	.type	_Z22backwardPassV2onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_, @function
_Z22backwardPassV2onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_:
.LFB2019:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	144(%rsp), %eax
	movq	232(%rsp), %r10
	movl	%r9d, (%rsp)
	movq	%r8, %r9
	movq	184(%rsp), %rbx
	movq	192(%rsp), %rbp
	xorl	%r8d, %r8d
	movl	%eax, 4(%rsp)
	movl	152(%rsp), %eax
	movq	200(%rsp), %r12
	movq	208(%rsp), %r13
	movl	%eax, 8(%rsp)
	movl	160(%rsp), %eax
	movq	216(%rsp), %r14
	movq	224(%rsp), %r15
	movl	%eax, 12(%rsp)
	movq	168(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	176(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	%r10, 40(%rsp)
	movq	240(%rsp), %r11
	movq	%r11, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	32(%rsp), %r11
	movq	40(%rsp), %r10
	testl	%eax, %eax
	jne	.L116
	movq	%r15, 184(%rsp)
	movq	24(%rsp), %r9
	movq	%r14, 176(%rsp)
	movq	16(%rsp), %r8
	movq	%r13, 168(%rsp)
	movl	12(%rsp), %ecx
	movq	%r12, 160(%rsp)
	movl	8(%rsp), %edx
	movq	%rbp, 152(%rsp)
	movl	4(%rsp), %esi
	movq	%rbx, 144(%rsp)
	movl	(%rsp), %edi
	movq	%r11, 200(%rsp)
	movq	%r10, 192(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z62__device_stub__Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_iiiiPfS_S_S_S_S_S_PiS_S_
.L116:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2019:
	.size	_Z22backwardPassV2onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_, .-_Z22backwardPassV2onDevice4dim3S_P11CUstream_stiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_
	.globl	_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii
	.type	_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii, @function
_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L119
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z21backwardPassV21KernelPfS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L119:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L121
	call	__stack_chk_fail@PLT
.L121:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii, .-_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii
	.globl	_Z21backwardPassV21KernelPfS_ii
	.type	_Z21backwardPassV21KernelPfS_ii, @function
_Z21backwardPassV21KernelPfS_ii:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii
	.cfi_endproc
.LFE2063:
	.size	_Z21backwardPassV21KernelPfS_ii, .-_Z21backwardPassV21KernelPfS_ii
	.globl	_Z23backwardPassV21onDevice4dim3S_iP11CUstream_stPfS2_ii
	.type	_Z23backwardPassV21onDevice4dim3S_iP11CUstream_stPfS2_ii, @function
_Z23backwardPassV21onDevice4dim3S_iP11CUstream_stPfS2_ii:
.LFB2020:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %ecx
	movslq	%r8d, %r8
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	80(%rsp), %rbx
	movq	88(%rsp), %rbp
	movl	96(%rsp), %r12d
	movl	104(%rsp), %r13d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L124
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z45__device_stub__Z21backwardPassV21KernelPfS_iiPfS_ii
.L124:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2020:
	.size	_Z23backwardPassV21onDevice4dim3S_iP11CUstream_stPfS2_ii, .-_Z23backwardPassV21onDevice4dim3S_iP11CUstream_stPfS2_ii
	.globl	_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_
	.type	_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_, @function
_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	216(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	224(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L127
	pushq	80(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 224
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L127:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L129
	call	__stack_chk_fail@PLT
.L129:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_, .-_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_
	.globl	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.type	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_, @function
_Z20backwardPassV3KerneliiiPfS_S_S_PiS_:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_
	.cfi_endproc
.LFE2065:
	.size	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_, .-_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.globl	_Z22backwardPassV3onDevice4dim3S_P11CUstream_stiiiPfS2_S2_S2_PiS2_
	.type	_Z22backwardPassV3onDevice4dim3S_P11CUstream_stiiiPfS2_S2_S2_PiS2_, @function
_Z22backwardPassV3onDevice4dim3S_P11CUstream_stiiiPfS2_S2_S2_PiS2_:
.LFB2021:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	112(%rsp), %eax
	movl	%r9d, 4(%rsp)
	movq	%r8, %r9
	xorl	%r8d, %r8d
	movq	128(%rsp), %r12
	movq	136(%rsp), %r13
	movl	%eax, 8(%rsp)
	movl	120(%rsp), %eax
	movq	144(%rsp), %r14
	movq	152(%rsp), %r15
	movl	%eax, 12(%rsp)
	movq	160(%rsp), %rbx
	movq	168(%rsp), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L132
	movq	%rbx, 120(%rsp)
	movl	12(%rsp), %edx
	movq	%r14, %r9
	movq	%r13, %r8
	movl	8(%rsp), %esi
	movl	4(%rsp), %edi
	movq	%r15, 112(%rsp)
	movq	%r12, %rcx
	movq	%rbp, 128(%rsp)
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z53__device_stub__Z20backwardPassV3KerneliiiPfS_S_S_PiS_iiiPfS_S_S_PiS_
.L132:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2021:
	.size	_Z22backwardPassV3onDevice4dim3S_P11CUstream_stiiiPfS2_S2_S2_PiS2_, .-_Z22backwardPassV3onDevice4dim3S_P11CUstream_stiiiPfS2_S2_S2_PiS2_
	.globl	_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i
	.type	_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i, @function
_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 32(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L135
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19updateWeightsKernelffPfS_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L135:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L137
	call	__stack_chk_fail@PLT
.L137:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i, .-_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i
	.globl	_Z19updateWeightsKernelffPfS_S_i
	.type	_Z19updateWeightsKernelffPfS_S_i, @function
_Z19updateWeightsKernelffPfS_S_i:
.LFB2067:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i
	.cfi_endproc
.LFE2067:
	.size	_Z19updateWeightsKernelffPfS_S_i, .-_Z19updateWeightsKernelffPfS_S_i
	.globl	_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i
	.type	_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i, @function
_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i:
.LFB2013:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%r9, %rbp
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%r8, %rbx
	xorl	%r8d, %r8d
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movq	96(%rsp), %r12
	movl	104(%rsp), %r13d
	movss	%xmm1, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L140
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z46__device_stub__Z19updateWeightsKernelffPfS_S_iffPfS_S_i
.L140:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2013:
	.size	_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i, .-_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i
	.globl	_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_
	.type	_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_, @function
_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L143
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z24sumDeltaWeightsP2PKerneliPfS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L143:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L145
	call	__stack_chk_fail@PLT
.L145:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_, .-_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_
	.globl	_Z24sumDeltaWeightsP2PKerneliPfS_
	.type	_Z24sumDeltaWeightsP2PKerneliPfS_, @function
_Z24sumDeltaWeightsP2PKerneliPfS_:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_
	.cfi_endproc
.LFE2069:
	.size	_Z24sumDeltaWeightsP2PKerneliPfS_, .-_Z24sumDeltaWeightsP2PKerneliPfS_
	.globl	_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_
	.type	_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_, @function
_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_:
.LFB2023:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	%ecx, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%r9, %rbp
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%r8d, %ebx
	xorl	%r8d, %r8d
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	64(%rsp), %r12
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L148
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z47__device_stub__Z24sumDeltaWeightsP2PKerneliPfS_iPfS_
.L148:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2023:
	.size	_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_, .-_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_
	.globl	_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_
	.type	_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_, @function
_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, (%rsp)
	movss	%xmm0, 40(%rsp)
	movss	%xmm1, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L151
	pushq	64(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z22updateWeightsP2PKerneliffPfS_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 192
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L151:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L153
	call	__stack_chk_fail@PLT
.L153:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_, .-_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_
	.globl	_Z22updateWeightsP2PKerneliffPfS_S_S_
	.type	_Z22updateWeightsP2PKerneliffPfS_S_S_, @function
_Z22updateWeightsP2PKerneliffPfS_S_S_:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_
	.cfi_endproc
.LFE2071:
	.size	_Z22updateWeightsP2PKerneliffPfS_S_S_, .-_Z22updateWeightsP2PKerneliffPfS_S_S_
	.globl	_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_
	.type	_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_, @function
_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_:
.LFB2024:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%ecx, %ecx
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%r9, %rbp
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%r8d, %ebx
	xorl	%r8d, %r8d
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movq	96(%rsp), %r12
	movq	104(%rsp), %r13
	movss	%xmm1, 8(%rsp)
	movq	112(%rsp), %r14
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L156
	addq	$48, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movq	%r14, %r8
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__Z22updateWeightsP2PKerneliffPfS_S_S_iffPfS_S_S_
.L156:
	.cfi_restore_state
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2024:
	.size	_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_, .-_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_
	.globl	_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_
	.type	_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_, @function
_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_:
.LFB2072:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z17sumErrorP2PKernelPfS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L159:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L161
	call	__stack_chk_fail@PLT
.L161:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2072:
	.size	_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_, .-_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_
	.globl	_Z17sumErrorP2PKernelPfS_
	.type	_Z17sumErrorP2PKernelPfS_, @function
_Z17sumErrorP2PKernelPfS_:
.LFB2073:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_
	.cfi_endproc
.LFE2073:
	.size	_Z17sumErrorP2PKernelPfS_, .-_Z17sumErrorP2PKernelPfS_
	.globl	_Z19sumErrorP2PonDevice4dim3S_PfS0_
	.type	_Z19sumErrorP2PonDevice4dim3S_PfS0_, @function
_Z19sumErrorP2PonDevice4dim3S_PfS0_:
.LFB2025:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ecx
	movq	%r9, %rbp
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%r8, %rbx
	xorl	%r8d, %r8d
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L164
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__Z17sumErrorP2PKernelPfS_PfS_
.L164:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2025:
	.size	_Z19sumErrorP2PonDevice4dim3S_PfS0_, .-_Z19sumErrorP2PonDevice4dim3S_PfS0_
	.globl	_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii
	.type	_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii, @function
_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii:
.LFB2074:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movss	%xmm0, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L167
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19setInitStatesKernelfPfiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L167:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L169
	call	__stack_chk_fail@PLT
.L169:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2074:
	.size	_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii, .-_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii
	.globl	_Z19setInitStatesKernelfPfiii
	.type	_Z19setInitStatesKernelfPfiii, @function
_Z19setInitStatesKernelfPfiii:
.LFB2075:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii
	.cfi_endproc
.LFE2075:
	.size	_Z19setInitStatesKernelfPfiii, .-_Z19setInitStatesKernelfPfiii
	.globl	_Z21setInitStatesOnDevice4dim3S_P11CUstream_stfPfiii
	.type	_Z21setInitStatesOnDevice4dim3S_P11CUstream_stfPfiii, @function
_Z21setInitStatesOnDevice4dim3S_P11CUstream_stfPfiii:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%r9, %rbx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movl	96(%rsp), %ebp
	movl	104(%rsp), %r12d
	movl	112(%rsp), %r13d
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L172
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movl	%ebp, %esi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z43__device_stub__Z19setInitStatesKernelfPfiiifPfiii
.L172:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	_Z21setInitStatesOnDevice4dim3S_P11CUstream_stfPfiii, .-_Z21setInitStatesOnDevice4dim3S_P11CUstream_stfPfiii
	.globl	_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_
	.type	_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_, @function
_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_:
.LFB2076:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	176(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L175
	pushq	64(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z21resetParametersKerneliiPfS_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 192
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L175:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L177
	call	__stack_chk_fail@PLT
.L177:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2076:
	.size	_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_, .-_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_
	.globl	_Z21resetParametersKerneliiPfS_S_S_S_
	.type	_Z21resetParametersKerneliiPfS_S_S_S_, @function
_Z21resetParametersKerneliiPfS_S_S_S_:
.LFB2077:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_
	.cfi_endproc
.LFE2077:
	.size	_Z21resetParametersKerneliiPfS_S_S_S_, .-_Z21resetParametersKerneliiPfS_S_S_S_
	.globl	_Z23resetParametersOnDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_
	.type	_Z23resetParametersOnDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_, @function
_Z23resetParametersOnDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_:
.LFB2012:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	112(%rsp), %ebp
	movl	%r9d, 12(%rsp)
	movq	%r8, %r9
	xorl	%r8d, %r8d
	movq	120(%rsp), %r12
	movq	128(%rsp), %r13
	movq	136(%rsp), %r14
	movq	144(%rsp), %r15
	movq	152(%rsp), %rbx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L180
	movq	%rbx, 112(%rsp)
	movl	12(%rsp), %edi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%r14, %r8
	movq	%r13, %rcx
	movq	%r12, %rdx
	movl	%ebp, %esi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__Z21resetParametersKerneliiPfS_S_S_S_iiPfS_S_S_S_
.L180:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2012:
	.size	_Z23resetParametersOnDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_, .-_Z23resetParametersOnDevice4dim3S_P11CUstream_stiiPfS2_S2_S2_S2_
	.globl	_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_
	.type	_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_, @function
_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_:
.LFB2078:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L183
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z23resetDeltaWeightsKerneliiPfS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L183:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L185
	call	__stack_chk_fail@PLT
.L185:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2078:
	.size	_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_, .-_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_
	.globl	_Z23resetDeltaWeightsKerneliiPfS_
	.type	_Z23resetDeltaWeightsKerneliiPfS_, @function
_Z23resetDeltaWeightsKerneliiPfS_:
.LFB2079:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_
	.cfi_endproc
.LFE2079:
	.size	_Z23resetDeltaWeightsKerneliiPfS_, .-_Z23resetDeltaWeightsKerneliiPfS_
	.globl	_Z25resetDeltaWeightsOnDevice4dim3S_P11CUstream_stiiPfS2_
	.type	_Z25resetDeltaWeightsOnDevice4dim3S_P11CUstream_stiiPfS2_, @function
_Z25resetDeltaWeightsOnDevice4dim3S_P11CUstream_stiiPfS2_:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	80(%rsp), %ebp
	movq	88(%rsp), %r12
	movq	96(%rsp), %r13
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L188
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movq	%r13, %rcx
	movq	%r12, %rdx
	movl	%ebp, %esi
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z47__device_stub__Z23resetDeltaWeightsKerneliiPfS_iiPfS_
.L188:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	_Z25resetDeltaWeightsOnDevice4dim3S_P11CUstream_stiiPfS2_, .-_Z25resetDeltaWeightsOnDevice4dim3S_P11CUstream_stiiPfS2_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12reduceKernelILj1EEvPfS0_jb"
.LC1:
	.string	"_Z12reduceKernelILj2EEvPfS0_jb"
.LC2:
	.string	"_Z12reduceKernelILj4EEvPfS0_jb"
.LC3:
	.string	"_Z12reduceKernelILj8EEvPfS0_jb"
.LC4:
	.string	"_Z12reduceKernelILj16EEvPfS0_jb"
.LC5:
	.string	"_Z12reduceKernelILj32EEvPfS0_jb"
.LC6:
	.string	"_Z12reduceKernelILj64EEvPfS0_jb"
.LC7:
	.string	"_Z12reduceKernelILj128EEvPfS0_jb"
.LC8:
	.string	"_Z12reduceKernelILj256EEvPfS0_jb"
.LC9:
	.string	"_Z12reduceKernelILj512EEvPfS0_jb"
.LC10:
	.string	"_Z23resetDeltaWeightsKerneliiPfS_"
.LC11:
	.string	"_Z21resetParametersKerneliiPfS_S_S_S_"
.LC12:
	.string	"_Z19setInitStatesKernelfPfiii"
.LC13:
	.string	"_Z17sumErrorP2PKernelPfS_"
.LC14:
	.string	"_Z22updateWeightsP2PKerneliffPfS_S_S_"
.LC15:
	.string	"_Z24sumDeltaWeightsP2PKerneliPfS_"
.LC16:
	.string	"_Z19updateWeightsKernelffPfS_S_i"
.LC17:
	.string	"_Z20backwardPassV3KerneliiiPfS_S_S_PiS_"
.LC18:
	.string	"_Z21backwardPassV21KernelPfS_ii"
.LC19:
	.string	"_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_"
.LC20:
	.string	"_Z21backwardPassV11KerneliiiPfS_S_PiS_"
.LC21:
	.string	"_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_"
.LC22:
	.string	"_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii"
.LC23:
	.string	"_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii"
.LC24:
	.string	"_Z19forwardPassV2KerneliiPfS_S_iiS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12reduceKernelILj1EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj2EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj4EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj8EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj16EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj32EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj64EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj128EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z12reduceKernelILj256EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12reduceKernelILj512EEvPfS0_jb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z23resetDeltaWeightsKerneliiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z21resetParametersKerneliiPfS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19setInitStatesKernelfPfiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17sumErrorP2PKernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z22updateWeightsP2PKerneliffPfS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z24sumDeltaWeightsP2PKerneliPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC16(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z19updateWeightsKernelffPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z21backwardPassV21KernelPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z21backwardPassV11KerneliiiPfS_S_PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC24(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z19forwardPassV2KerneliiPfS_S_iiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2101:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research																														//
//																																																				//
//Copyright (c) <2012>, <Martin Peniak - www.martinpeniak.com>																																					//
//All rights reserved.																																															//
//																																																				//
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:																//
//																																																				//
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.																				//
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.	//
//																																																				//
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR	//
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT	//
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR	//
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.																//
//                                                                                                                                                                                                              //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted                                                                                  //
//as representing official policies,either expressed or implied, of the FreeBSD Project.                                                                                                                        //
//##############################################################################################################################################################################################################//

#include <hip/hip_runtime.h>


/*!
 * \brief Forward pass.
 * \note Used with forwardPassV21Kernel - faster version for networks of up to 1024 neurons.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] activity - activations
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] buffer - buffer used for storing new activations
 */
__global__ void forwardPassV2Kernel(int step, int sequenceOffset, float *activity, float *input, float *weight, int numNeurons, int numIONeurons, float *buffer)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;

    if(idx<numNeurons && j<numNeurons)
    {
        if(j<numIONeurons)
        {
            buffer[(j*numNeurons)+idx] = input[sequenceOffset+(numIONeurons*(step-1))+j] * weight[(j*numNeurons)+idx];
        }
        else
        {
            buffer[(j*numNeurons)+idx] = activity[(numNeurons*(step-1))+j] * weight[(j*numNeurons)+idx];
        }
    }
}

/*!
 * \brief Forward pass.
 * \note Used with forwardPassV2Kernel. Faster version for networks of up to 1024 neurons.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] deltaT - delta-t values
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] activity - activities
 * \param[out] error - errors
 */
__global__ void forwardPassV21Kernel(int step, int sequenceOffset, float *activity, float *input, float *buffer, float *potential, float *weight, float *previousPotential, float *error, int *deltaT, int numNeurons, int numIONeurons)
{
    extern __shared__ float sdata[];

    int tid = threadIdx.x;
    int i = blockDim.x/2;

    //init to zero
    sdata[tid] = 0.0;

    if(tid < numNeurons)
    {
        //load data
        sdata[tid] = buffer[(tid * numNeurons)+blockIdx.x];
        __syncthreads();

        while (i != 0)
        {
            if(tid < i)
            {
                //each thread puts its local sum into shared memory
                sdata[tid] += sdata[tid + i];
                __syncthreads();
            }
            i /= 2;
        }

        //write result for this block to global mem
        if (tid == 0)
        {
            potential[blockIdx.x] = sdata[0];

            //add bias to the activity
            potential[blockIdx.x] += weight[(numNeurons*numNeurons)+blockIdx.x];

            //calculate current membrane potential taking delta-t value as well as the previous membrane potential into account
            potential[blockIdx.x] = ((1.0f-(1.0f/(float)deltaT[blockIdx.x])) * previousPotential[blockIdx.x]) + ((1.0f/(float)deltaT[blockIdx.x])*potential[blockIdx.x]);

            //save current membrane potential for the next time step where it will be used as the previous membrane potential
            previousPotential[blockIdx.x] = potential[blockIdx.x];

            //sigmoid activation
            activity[(numNeurons*step)+blockIdx.x] = 1.0f/(1.0f+__expf(-potential[blockIdx.x]));

            //save error
            if(blockIdx.x<numIONeurons)
            {
                error[(numNeurons*step)+blockIdx.x] = activity[(numNeurons*step)+blockIdx.x] - input[sequenceOffset+(numIONeurons*(step+1))+blockIdx.x];
            }
        }
    }
}

/*!
 * \brief Forward pass.
 * \note Slower version for larger networks.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] deltaT - delta-t values
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] activity - activities
 * \param[out] error - errors
 */
__global__ void forwardPassV1Kernel(int step, int sequenceOffset, float *activity, float *input, float *weight, float *previousPotential, float *error, float *potential, int *deltaT, int numNeurons, int numIONeurons)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;
    float sum = 0.0;

    if(idx<numNeurons)
    {
        potential[idx] = 0.0;

        //calculates membrabe potential of a particular neuron given by the idx index
        for(int i=0; i<numNeurons; i++)
        {
            if(i<numIONeurons)
            {
                sum += input[sequenceOffset+(numIONeurons*(step-1))+i] * weight[(i*numNeurons)+idx];
            }
            else
            {
                sum += activity[(numNeurons*(step-1))+i] * weight[(i*numNeurons)+idx];
            }
        }

        //add bias to the activity
        sum += weight[(numNeurons*numNeurons)+idx];

        //calculate current membrane potential taking delta-t value as well as the previous membrane potential into account
        potential[idx] = ((1.0f-(1.0f/(float)deltaT[idx])) * previousPotential[idx]) + ((1.0f/(float)deltaT[idx])*sum);

        //save current membrane potential for the next time step where it will be used as the previous membrane potential
        previousPotential[idx] = potential[idx];

        //Sigmoid activation function
        activity[(numNeurons*step)+idx] = 1.0f/(1.0f+__expf(-potential[idx]));

        //save error
        if(idx<numIONeurons)
        {
            error[(numNeurons*step)+idx] = activity[(numNeurons*step)+idx] - input[sequenceOffset+(numIONeurons*(step+1))+idx];
        }

        sum = 0.0;
    }
}

/*!
 * \brief Calculates deltas, deltas on weights and errors parts.
 * \note Slower version for larger networks over 1024 neurons.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 */
__global__ void backwardPassV1Kernel(int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;

    if(idx<numIONeurons && j<numNeurons)
    {
        if(j==0)
        {
            individualError[idx] += ((input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]) * (input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]))/2.0f;
        }

        delta[idx] = error[(numNeurons*step)+idx] + (1.0f - (1.0f/deltaT[idx])) * previousDelta[idx];

        if(weight[(j*numNeurons)+idx]!=0)
        {
            deltaWeight[(j*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx] * activity[(numNeurons*(step-1))+j];
        }
    }
}

/*!
 * \brief Calculates deltas on hidden neurons.
 * \note Slower version for larger networks over 1024 neurons.
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-ouput neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 */
__global__ void backwardPassV11Kernel(int step,  int numNeurons, int numIONeurons,  float *activity, float *delta, float *previousDelta, int *deltaT, float *weight)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int kroneckerDelta;

    if(idx<numNeurons && idx>=numIONeurons)
    {
        delta[idx] = 0.0;

        for(int j=0; j<numNeurons; j++)
        {
            if(weight[(j*numNeurons)+idx]!=0)
            {
                //set Kronecker's delta
                if (idx==j)
                {
                    kroneckerDelta = 1;
                }
                else
                {
                    kroneckerDelta = 0;
                }

                //see bottom part of the equation 11 in Yamashita & Tani 2008 - SUM(k->N) of prev_hidden_delta * kroneckerDelta * (1-1/hidden-delta) + (1/delta-on-unit-k) * weight(ki) * derivative of activation of neuron i
                delta[idx] += previousDelta[j] * (kroneckerDelta * (1.0f - (1.0f/deltaT[idx])) + (1.0f/deltaT[j]) * weight[(idx*numNeurons)+j] * (activity[(numNeurons*step)+idx] * (1.0f - activity[(numNeurons*step)+idx])));
            }
        }
    }
}

/*!
 * \brief Loads the buffer with deltas on weights fractions calculate deltas, deltas on weights and errors parts.
 * \note Deltas on weights and errors are later summed by parallel reduction.
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] previousDelta - previous deltas
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 * \param[out] buffer - buffer used for storing delta weights
 */
__global__ void backwardPassV2Kernel(int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight, float *buffer)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    int kroneckerDelta;

    if(idx<numNeurons && j<numNeurons)
    {
        if(idx<numIONeurons)
        {
            if(j==0)
            {
                individualError[idx] += ((input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]) * (input[sequenceOffset+(numIONeurons*(step+1))+idx] - activity[(numNeurons*step)+idx]))/2.0f;
            }

            delta[idx] = error[(numNeurons*step)+idx] + (1.0f - (1.0f/deltaT[idx])) * previousDelta[idx];

            if(weight[(j*numNeurons)+idx]!=0)
            {
                //see eqaution 10 in Yamashita & Tani 2008 - SUM(t) of (1/fast-unit-delta)*delta-output(t) * fast-neuron-activity(t-1)
                deltaWeight[(j*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx] * activity[(numNeurons*(step-1))+j];
            }
        }
        else //load the buffer with deltas on weights fractions
        {
            buffer[(j*numNeurons)+idx] = 0.0;

            //calculate delta on weight if the two neurons are connected
            if(weight[(j*numNeurons)+idx]!=0)
            {
                //set Kronecker's delta
                if (idx==j)
                {
                    kroneckerDelta = 1;
                }
                else
                {
                    kroneckerDelta = 0;
                }

                //see bottom part of the equation 11 in Yamashita & Tani 2008 - SUM(k->N) of prev_hidden_delta * kroneckerDelta * (1-1/hidden-delta) + (1/delta-on-unit-k) * weight(ki) * derivative of activation of neuron i
                buffer[(j*numNeurons)+idx] = previousDelta[j] * (kroneckerDelta * (1.0f - (1.0f/deltaT[idx])) + (1.0f/deltaT[j]) * weight[(idx*numNeurons)+j] * (activity[(numNeurons*step)+idx] * (1.0f - activity[(numNeurons*step)+idx])));
            }
        }
    }
}

/*!
 * \brief Calculates deltas on hidden neurons.
 * \note Used together with backwardPassV2Kerne. Faster version for networks of up to 1024 neurons.
 * \param[in] input - input
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] output - output
 */
__global__ void backwardPassV21Kernel(float *input, float *output, int numNeurons, int numIONeurons)
{
    extern __shared__ float sdata[];

    int tid = threadIdx.x;
    int i = blockDim.x/2;

    //init to zero
    sdata[tid] = 0.0;

    if(tid<numNeurons)
    {
        //load data
        sdata[tid] = input[(tid * numNeurons)+(numIONeurons+blockIdx.x)];
        __syncthreads();

        while(i!=0)
        {
            if(tid<i)
            {
                //each thread puts its local sum into shared memory
                sdata[tid] += sdata[tid+i];
                __syncthreads();
            }
            i/=2;
        }

        //write result for this block to global memory
        if(tid==0)
        {
            output[numIONeurons+blockIdx.x] = sdata[0];
        }
    }
}

/*!
 * \brief Calculates deltas on weights on hidden neurons and biases.
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] deltaWeight - delta weights
 */
__global__ void backwardPassV3Kernel(int step, int numNeurons, int numIONeurons, float *activity, float *delta, float *previousDelta, float *deltaWeight, int *deltaT, float *weight)
{
    int idx = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;

    if(j<numNeurons && idx<numNeurons)
    {
        //calculate delta on weights for those neurons that are directly connected to hidden neurons
        if(idx>=numIONeurons)
        {
            if(weight[(j*numNeurons)+idx]!=0)
            {
                //see eqaution 10 in Yamashita & Tani 2008 - SUM(t) of (1/fast-unit-delta)*delta-output(t) * fast-neuron-activity(t-1)
                deltaWeight[(j*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx] * activity[(numNeurons*(step-1))+j];
            }
        }

        //calculate deltas on bias weights connecting to each neuron
        if(j==0)
        {
            deltaWeight[(numNeurons*numNeurons)+idx] += (1.0f/deltaT[idx]) * delta[idx];
            previousDelta[idx] = delta[idx];
        }
    }
}

/*!
 * \brief Updates weights.
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] numWeights - number of weights
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] weight - weights
 */
__global__ void updateWeightsKernel(float learningRate, float momentum, float *weight, float *deltaWeight, float *previousDeltaWeight, int numWeights)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        weight[idx] -= ((learningRate * deltaWeight[idx]) + (momentum * previousDeltaWeight[idx]));
        previousDeltaWeight[idx] = deltaWeight[idx];
    }
}

/*!
 * \brief Sums delta weights on the master device.
 * \param[in] numWeights - number of weights
 * \param[in] peerDeltaWeight - delta weights from peer device
 * \param[out] masterDeltaWeight - delta weights from master device
 */
__global__ void sumDeltaWeightsP2PKernel(int numWeights, float *masterDeltaWeight, float *peerDeltaWeight)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        masterDeltaWeight[idx] += peerDeltaWeight[idx];
    }
}

/*!
 * \brief Modifies weights on the master device and copies to the peer device.
 * \param[in] numWeights - number of weights
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] masterWeight - weigths from master device
 * \param[out] peerWeight - weights from peer device
 */
__global__ void updateWeightsP2PKernel(int numWeights, float learningRate, float momentum, float *masterWeight, float *peerWeight, float *deltaWeight, float *previousDeltaWeight)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        masterWeight[idx] -= ((learningRate * deltaWeight[idx]) + (momentum * previousDeltaWeight[idx]));
        peerWeight[idx] = masterWeight[idx];
        previousDeltaWeight[idx] = deltaWeight[idx];
    }
}

/*!
 * \brief Modifies weights on the master device and copies to the peer device.
 * \param[in] peerError - error from peer device
 * \param[out] masterError - error from master device
 */
__global__ void sumErrorP2PKernel(float *masterError, float *peerError)
{
    if(threadIdx.x==0)
    {
        masterError[0] += peerError[0];
    }
}

/*!
 * \brief Sets the initial states for all the units on device.
 * \note Slow context units will be initialised with a specific value.
 * \param[in] initState - initial state
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] numFastNeurons - number of fast neurons
 * \param[out] activity - activities
 */
__global__  void setInitStatesKernel(float initState, float *activity, int numNeurons, int numIONeurons, int numFastNeurons)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;

    if(idx<numNeurons)
    {
        if(idx>=numIONeurons+numFastNeurons && idx<numIONeurons+numFastNeurons+5)
        {
            activity[idx] = initState;
        }
        else
        {
            activity[idx] = 0.0;
        }
    }
}

/*!
 * \brief Resets delta and error parameters.
 * \param[in] numNeurons - number of neurons
 * \param[in] maxSequenceSteps - maximum number of sequence steps
 * \param[out] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] error - errors
 */
__global__ void resetParametersKernel(int numNeurons, int maxSequenceSteps, float *delta, float *previousDelta, float *potential, float *previousPotential, float *error)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;

    if(idx<(numNeurons*maxSequenceSteps))
    {
        if(idx<numNeurons)
        {
            delta[idx] = 0.0;
            previousDelta[idx] = 0.0;
            potential[idx] = 0.0;
            previousPotential[idx] = 0.0;
        }

        error[idx] = 0.0;
    }
}

/*!
 * \brief Resets delta weights and errors.
 * \param[in] numWeights - number of weights
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] deltaWeight - delta weights
 * \param[out] individualError - error buffer
 */
__global__ void resetDeltaWeightsKernel(int numWeights, int numIONeurons, float *deltaWeight, float *individualError)
{
    int idx = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;

    if(idx<numWeights)
    {
        deltaWeight[idx] = 0.0;

        if(idx<numIONeurons)
        {
            individualError[idx] = 0.0;
        }
    }
}

/*!
 * \brief Parallel reduction sum modified from NVIDIA SDK.
 * \note Number of threads are not known at a compile time, however, we always stick to power of 2 sizes
 * \note so here we are using templates to allow compilation for all known size, which results in higher throughput.
 * \param[in] input - input
 * \param[in] n - number of elements to sum
 * \param[in] nIsPow2 - determines if the number is of power of two
 * \param[out] output - output
 */
template <unsigned int blockSize> __global__ void reduceKernel(float *input, float *output, unsigned int n, bool nIsPow2)
{
    extern __shared__ float sdata[];

    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*blockSize*2 + threadIdx.x;
    unsigned int gridSize = blockSize*2*gridDim.x;

    float sum = 0.0;

    //perform first level of reduction, reading from global memory, writing to shared memory
    //we reduce multiple elements per thread.  The number is determined by the number of active thread blocks (via gridDim).
    //More blocks will result in a larger gridSize and therefore fewer elements per thread
    while(i<n)
    {
        sum += input[i];

        //ensure we don't read out of bounds -- this is optimised away for powerOf2 sized arrays
        if (nIsPow2 || (i+blockSize)<n)
        {
            sum += input[i+blockSize];
        }

        i+=gridSize;
    }

    //each thread puts its local sum into shared memory
    sdata[tid] = sum;
    __syncthreads();

    //do reduction in shared mem
    if (blockSize >= 512) { if (tid < 256) { sdata[tid] = sum = sum + sdata[tid + 256]; } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128) { sdata[tid] = sum = sum + sdata[tid + 128]; } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64) { sdata[tid] = sum = sum + sdata[tid +  64]; } __syncthreads(); }

    if(tid<32)
    {
        //now that we are using warp-synchronous programming (below) we need to declare our shared memory
        //volatile so that the compiler doesn't reorder stores to it and induce incorrect behavior
        volatile float* smem = sdata;
        if (blockSize>=64)
        {
            smem[tid] = sum = sum + smem[tid+32];
        }

        if (blockSize>=32)
        {
            smem[tid] = sum = sum + smem[tid+16];
        }

        if (blockSize>=16)
        {
            smem[tid] = sum = sum + smem[tid+8];
        }

        if (blockSize>=8)
        {
            smem[tid] = sum = sum + smem[tid+4];
        }

        if (blockSize>=4)
        {
            smem[tid] = sum = sum + smem[tid+2];
        }

        if (blockSize>=2)
        {
            smem[tid] = sum = sum + smem[tid+1];
        }
    }

    //write result for this block to global mem
    if(tid==0)
    {
        output[blockIdx.x] = sdata[0];
    }
}

/*!
 * \brief Wrapper for resetDeltaWeightsKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] numWeights - number of weights
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] deltaWeight - delta weights
 * \param[out] individualError - error buffer
 */
void resetDeltaWeightsOnDevice(dim3 grid, dim3 block, hipStream_t stream, int numWeights, int numIONeurons, float *deltaWeight, float *individualError)
{
    resetDeltaWeightsKernel<<<grid,block,0,stream>>>(numWeights, numIONeurons, deltaWeight, individualError);
}

/*!
 * \brief Wrapper for setInitStatesKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] initState - initial state
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] numFastNeurons - number of fast neurons
 * \param[out] activity - activities
 */
void setInitStatesOnDevice(dim3 grid, dim3 block, hipStream_t stream, float initState, float *activity, int numNeurons, int numIONeurons, int numFastNeurons)
{
    setInitStatesKernel<<<grid,block,0,stream>>>(initState, activity, numNeurons, numIONeurons, numFastNeurons);
}

/*!
 * \brief Wrapper for resetParametersKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] numNeurons - number of neurons
 * \param[in] maxSequenceSteps - maximum number of sequence steps
 * \param[out] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] error - errors
 */
void resetParametersOnDevice(dim3 grid, dim3 block, hipStream_t stream, int numNeurons, int maxSequenceSteps, float *delta, float *previousDelta, float *potential, float *previousPotential, float *error)
{
    resetParametersKernel<<<grid,block,0,stream>>>(numNeurons, maxSequenceSteps, delta, previousDelta, potential, previousPotential, error);
}

/*!
 * \brief Wrapper for updateWeightsKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] numWeights - number of weights
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] weight - weights
 */
void updateWeightsOnDevice(dim3 grid, dim3 block, float learningRate, float momentum, float *weight, float *deltaWeight, float *previousDeltaWeight, int numWeights)
{
    updateWeightsKernel<<<grid,block>>>(learningRate, momentum, weight, deltaWeight, previousDeltaWeight, numWeights);
}

/*!
 * \brief Wrapper for forwardPassV1Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] deltaT - delta-t values
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] potential - potentials
 * \param[out] previousPotential - previous potentials
 * \param[out] activity - activities
 * \param[out] error - errors
 */
void forwardPassV1onDevice(dim3 grid, dim3 block, hipStream_t stream, int step, int sequenceOffset, float *activity, float *input, float *weight, float *previousPotential, float *error, float *potential, int *deltaT, int numNeurons, int numIONeurons)
{
    forwardPassV1Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, activity, input, weight, previousPotential, error, potential, deltaT, numNeurons, numIONeurons);
}

/*!
 * \brief Wrapper for forwardPassV2Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] activity - activations
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] buffer - buffer used for storing new activations
 */
void forwardPassV2onDevice(dim3 grid, dim3 block, hipStream_t stream, int step, int sequenceOffset, float *activity, float *input, float *weight, int numNeurons, int numIONeurons, float *buffer)
{
    forwardPassV2Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, activity, input, weight, numNeurons, numIONeurons, buffer);
}

/*!
 * \brief Wrapper for forwardPassV21Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] smemSize - CUDA shared memory size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] activity - activations
 * \param[in] input - input
 * \param[in] weight - weights
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] buffer - buffer used for storing new activations
 */
void forwardPassV21onDevice(dim3 grid, dim3 block, int smemSize, hipStream_t stream, int step, int sequenceOffset, float *activity, float *input, float *buffer, float *potential, float *weight, float *previousPotential, float *error, int *deltaT, int numNeurons, int numIONeurons)
{
    forwardPassV21Kernel<<<grid,block,smemSize,stream>>>(step, sequenceOffset, activity, input, buffer, potential, weight, previousPotential, error, deltaT, numNeurons, numIONeurons);
}

/*!
 * \brief Wrapper for backwardPassV1Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 */
void backwardPassV1onDevice(dim3 grid, dim3 block, hipStream_t stream, int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight)
{
    backwardPassV1Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, numNeurons, numIONeurons, input, activity, delta, deltaWeight, previousDelta, error, individualError, deltaT, weight);
}

/*!
 * \brief Wrapper for backwardPassV11Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-ouput neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] previousDelta - previous deltas
 * \param[out] delta - deltas
 */
void backwardPassV11onDevice(dim3 grid, dim3 block, hipStream_t stream, int step,  int numNeurons, int numIONeurons,  float *activity, float *delta, float *previousDelta, int *deltaT, float *weight)
{
    backwardPassV11Kernel<<<grid,block,0,stream>>>(step,  numNeurons, numIONeurons,  activity, delta, previousDelta, deltaT, weight);
}

/*!
 * \brief Wrapper for backwardPassV2Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] sequenceOffset - sequence offsets
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] input - input
 * \param[in] activity - activities
 * \param[in] previousDelta - previous deltas
 * \param[in] error - errors
 * \param[in] individualError - error buffer
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[out] delta - deltas
 * \param[out] deltaWeight - delta weights
 * \param[out] buffer - buffer used for storing delta weights
 */
void backwardPassV2onDevice(dim3 grid, dim3 block, hipStream_t stream, int step, int sequenceOffset, int numNeurons, int numIONeurons, float *input, float *activity, float *delta, float *deltaWeight, float *previousDelta, float *error, float *individualError, int *deltaT, float *weight, float *buffer)
{
    backwardPassV2Kernel<<<grid,block,0,stream>>>(step, sequenceOffset, numNeurons, numIONeurons, input, activity, delta, deltaWeight, previousDelta, error, individualError, deltaT, weight, buffer);
}

/*!
 * \brief Wrapper for backwardPassV21Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] smemSize - CUDA shared memory size
 * \param[in] stream - CUDA stream
 * \param[in] input - input
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[out] output - output
 */
void backwardPassV21onDevice(dim3 grid, dim3 block, int smemSize, hipStream_t stream, float *input, float *output, int numNeurons, int numIONeurons)
{
    backwardPassV21Kernel<<<grid,block,smemSize,stream>>>(input, output, numNeurons, numIONeurons);
}

/*!
 * \brief Wrapper for backwardPassV3Kernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] stream - CUDA stream
 * \param[in] step - current step
 * \param[in] numNeurons - number of neurons
 * \param[in] numIONeurons - number of input-output neurons
 * \param[in] activity - activities
 * \param[in] deltaT - delta-t values
 * \param[in] weight - weights
 * \param[in] delta - deltas
 * \param[out] previousDelta - previous deltas
 * \param[out] deltaWeight - delta weights
 */
void backwardPassV3onDevice(dim3 grid, dim3 block, hipStream_t stream, int step, int numNeurons, int numIONeurons, float *activity, float *delta, float *previousDelta, float *deltaWeight, int *deltaT, float *weight)
{
    backwardPassV3Kernel<<<grid,block,0,stream>>>(step, numNeurons, numIONeurons, activity, delta, previousDelta, deltaWeight, deltaT, weight);
}

/*!
 * \brief Wrapper for reduceKernel.
 * \param[in] size - number of elements to sum
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] smemSize - CUDA shared memory size
 * \param[in] stream - CUDA stream
 * \param[in] input - input
 * \param[in] n - number of elements to sum
 * \param[in] nIsPow2 - determines if the number is of power of two
 * \param[out] output - output
 */
void reduceOnDevice(int size, dim3 grid, dim3 block, int smemSize, hipStream_t stream, float *input, float *output, unsigned int n, bool nIsPow2)
{
    switch(size)
    {
        case 512:
            reduceKernel<512><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 256:
            reduceKernel<256><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 128:
            reduceKernel<128><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 64:
            reduceKernel<64><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 32:
            reduceKernel<32><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case 16:
            reduceKernel<16><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  8:
            reduceKernel<8><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  4:
            reduceKernel<4><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  2:
            reduceKernel<2><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;

        case  1:
            reduceKernel<1><<<grid,block,smemSize,stream>>>(input, output, n, nIsPow2);
        break;
    }
}

/*!
 * \brief Wrapper for sumDeltaWeightsP2PKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] numWeights - number of weights
 * \param[in] peerDeltaWeight - delta weights from peer device
 * \param[out] masterDeltaWeight - delta weights from master device
 */
void sumDeltaWeightsP2PonDevice(dim3 grid, dim3 block, int numWeights, float *masterDeltaWeight, float *peerDeltaWeight)
{
    sumDeltaWeightsP2PKernel<<<grid,block>>>(numWeights, masterDeltaWeight, peerDeltaWeight);
}

/*!
 * \brief Wrapper for updateWeightsP2PKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] numWeights - number of weights
 * \param[in] learningRate - learning rate
 * \param[in] momentum - momentum
 * \param[in] deltaWeight - delta weights
 * \param[out] previousDeltaWeight - previous delta weights
 * \param[out] masterWeight - weigths from master device
 * \param[out] peerWeight - weights from peer device
 */
void updateWeightsP2PonDevice(dim3 grid, dim3 block, int numWeights, float learningRate, float momentum, float *masterWeight, float *peerWeight, float *deltaWeight, float *previousDeltaWeight)
{
    updateWeightsP2PKernel<<<grid,block>>>(numWeights, learningRate, momentum, masterWeight, peerWeight, deltaWeight, previousDeltaWeight);
}

/*!
 * \brief Wrapper for sumErrorP2PKernel.
 * \param[in] grid - CUDA grid size
 * \param[in] block - CUDA block size
 * \param[in] peerError - error from peer device
 * \param[out] masterError - error from master device
 */
void sumErrorP2PonDevice(dim3 grid, dim3 block, float *masterError, float *peerError)
{
    sumErrorP2PKernel<<<grid,block>>>(masterError, peerError);
}


	.text
	.file	"mtrnnKernels.hip"
	.globl	_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_ # -- Begin function _Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_
	.type	_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_,@function
_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_: # @_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19forwardPassV2KerneliiPfS_S_iiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_, .Lfunc_end0-_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii # -- Begin function _Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.type	_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii,@function
_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii: # @_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, .Lfunc_end1-_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii # -- Begin function _Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.type	_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii,@function
_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii: # @_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii, .Lfunc_end2-_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_ # -- Begin function _Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.type	_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_,@function
_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_: # @_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, .Lfunc_end3-_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_ # -- Begin function _Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_
	.type	_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_,@function
_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_: # @_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21backwardPassV11KerneliiiPfS_S_PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_, .Lfunc_end4-_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_ # -- Begin function _Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.type	_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_,@function
_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_: # @_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, .Lfunc_end5-_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__backwardPassV21KernelPfS_ii # -- Begin function _Z36__device_stub__backwardPassV21KernelPfS_ii
	.type	_Z36__device_stub__backwardPassV21KernelPfS_ii,@function
_Z36__device_stub__backwardPassV21KernelPfS_ii: # @_Z36__device_stub__backwardPassV21KernelPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21backwardPassV21KernelPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z36__device_stub__backwardPassV21KernelPfS_ii, .Lfunc_end6-_Z36__device_stub__backwardPassV21KernelPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_ # -- Begin function _Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_
	.type	_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_,@function
_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_: # @_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20backwardPassV3KerneliiiPfS_S_S_PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_, .Lfunc_end7-_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__updateWeightsKernelffPfS_S_i # -- Begin function _Z34__device_stub__updateWeightsKernelffPfS_S_i
	.type	_Z34__device_stub__updateWeightsKernelffPfS_S_i,@function
_Z34__device_stub__updateWeightsKernelffPfS_S_i: # @_Z34__device_stub__updateWeightsKernelffPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	16(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r8, 8(%rbx)
	movq	%r9, 16(%rbx)
	movq	%rdi, 24(%rbx)
	movq	%rsi, 32(%rbx)
	movq	%rdx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19updateWeightsKernelffPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z34__device_stub__updateWeightsKernelffPfS_S_i, .Lfunc_end8-_Z34__device_stub__updateWeightsKernelffPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_ # -- Begin function _Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_
	.type	_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_,@function
_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_: # @_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24sumDeltaWeightsP2PKerneliPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_, .Lfunc_end9-_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_ # -- Begin function _Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_
	.type	_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_,@function
_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_: # @_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movss	%xmm0, (%rdi)
	leaq	4(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	56(%rsp), %r10
	movq	%rsi, (%r10)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r9, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%rsi, 32(%rbx)
	movq	%rdx, 40(%rbx)
	movq	%rcx, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22updateWeightsP2PKerneliffPfS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_, .Lfunc_end10-_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__sumErrorP2PKernelPfS_ # -- Begin function _Z32__device_stub__sumErrorP2PKernelPfS_
	.type	_Z32__device_stub__sumErrorP2PKernelPfS_,@function
_Z32__device_stub__sumErrorP2PKernelPfS_: # @_Z32__device_stub__sumErrorP2PKernelPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17sumErrorP2PKernelPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z32__device_stub__sumErrorP2PKernelPfS_, .Lfunc_end11-_Z32__device_stub__sumErrorP2PKernelPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__setInitStatesKernelfPfiii # -- Begin function _Z34__device_stub__setInitStatesKernelfPfiii
	.type	_Z34__device_stub__setInitStatesKernelfPfiii,@function
_Z34__device_stub__setInitStatesKernelfPfiii: # @_Z34__device_stub__setInitStatesKernelfPfiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	40(%rsp), %r8
	movq	%rdi, (%r8)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r8, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19setInitStatesKernelfPfiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z34__device_stub__setInitStatesKernelfPfiii, .Lfunc_end12-_Z34__device_stub__setInitStatesKernelfPfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_ # -- Begin function _Z36__device_stub__resetParametersKerneliiPfS_S_S_S_
	.type	_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_,@function
_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_: # @_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21resetParametersKerneliiPfS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_, .Lfunc_end13-_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__resetDeltaWeightsKerneliiPfS_ # -- Begin function _Z38__device_stub__resetDeltaWeightsKerneliiPfS_
	.type	_Z38__device_stub__resetDeltaWeightsKerneliiPfS_,@function
_Z38__device_stub__resetDeltaWeightsKerneliiPfS_: # @_Z38__device_stub__resetDeltaWeightsKerneliiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23resetDeltaWeightsKerneliiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z38__device_stub__resetDeltaWeightsKerneliiPfS_, .Lfunc_end14-_Z38__device_stub__resetDeltaWeightsKerneliiPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_ # -- Begin function _Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_
	.type	_Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_,@function
_Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_: # @_Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	movq	64(%rsp), %r14
	movq	56(%rsp), %r15
	movl	48(%rsp), %ebp
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB15_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB15_2:
	.cfi_def_cfa_offset 48
	movl	%ebx, %edi
	movl	%ebp, %esi
	movq	%r15, %rdx
	movq	%r14, %rcx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z38__device_stub__resetDeltaWeightsKerneliiPfS_ # TAILCALL
.Lfunc_end15:
	.size	_Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_, .Lfunc_end15-_Z25resetDeltaWeightsOnDevice4dim3S_P12ihipStream_tiiPfS2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii # -- Begin function _Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii
	.type	_Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii,@function
_Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii: # @_Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%r8, %r9
	movl	64(%rsp), %ebp
	movl	56(%rsp), %r14d
	movl	48(%rsp), %r15d
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB16_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB16_2:
	.cfi_def_cfa_offset 48
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__setInitStatesKernelfPfiii # TAILCALL
.Lfunc_end16:
	.size	_Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii, .Lfunc_end16-_Z21setInitStatesOnDevice4dim3S_P12ihipStream_tfPfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_ # -- Begin function _Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_
	.type	_Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_,@function
_Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_: # @_Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB17_2
# %bb.1:
	movq	72(%rsp), %rax
	movq	64(%rsp), %r9
	movq	56(%rsp), %r8
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movl	32(%rsp), %esi
	movq	%rax, (%rsp)
	movl	%ebx, %edi
	callq	_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_
.LBB17_2:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_, .Lfunc_end17-_Z23resetParametersOnDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i # -- Begin function _Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i
	.type	_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i,@function
_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i: # @_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movl	56(%rsp), %ebp
	movq	48(%rsp), %r15
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB18_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB18_2:
	.cfi_def_cfa_offset 48
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	%ebp, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__updateWeightsKernelffPfS_S_i # TAILCALL
.Lfunc_end18:
	.size	_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i, .Lfunc_end18-_Z21updateWeightsOnDevice4dim3S_ffPfS0_S0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii # -- Begin function _Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii
	.type	_Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii,@function
_Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii: # @_Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB19_2
# %bb.1:
	movl	88(%rsp), %eax
	movl	80(%rsp), %r10d
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movl	16(%rsp), %esi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%ebx, %edi
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB19_2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii, .Lfunc_end19-_Z21forwardPassV1onDevice4dim3S_P12ihipStream_tiiPfS2_S2_S2_S2_S2_Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_ # -- Begin function _Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_
	.type	_Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_,@function
_Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_: # @_Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB20_2
# %bb.1:
	movl	56(%rsp), %eax
	movl	48(%rsp), %r9d
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movl	16(%rsp), %esi
	movl	%ebx, %edi
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB20_2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_, .Lfunc_end20-_Z21forwardPassV2onDevice4dim3S_P12ihipStream_tiiPfS2_S2_iiS2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii # -- Begin function _Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii
	.type	_Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii,@function
_Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii: # @_Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movslq	%r8d, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB21_2
# %bb.1:
	movl	104(%rsp), %eax
	movl	96(%rsp), %r10d
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	24(%rsp), %esi
	movl	16(%rsp), %edi
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB21_2:
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii, .Lfunc_end21-_Z22forwardPassV21onDevice4dim3S_iP12ihipStream_tiiPfS2_S2_S2_S2_S2_S2_Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_ # -- Begin function _Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_
	.type	_Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_,@function
_Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_: # @_Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB22_2
# %bb.1:
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movl	32(%rsp), %ecx
	movl	24(%rsp), %edx
	movl	16(%rsp), %esi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%ebx, %edi
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB22_2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	_Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_, .Lfunc_end22-_Z22backwardPassV1onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_ # -- Begin function _Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_
	.type	_Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_,@function
_Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_: # @_Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_2
# %bb.1:
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movl	24(%rsp), %edx
	movl	16(%rsp), %esi
	movl	%ebx, %edi
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB23_2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	_Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_, .Lfunc_end23-_Z23backwardPassV11onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_PiS2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_ # -- Begin function _Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_
	.type	_Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_,@function
_Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_: # @_Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB24_2
# %bb.1:
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movl	32(%rsp), %ecx
	movl	24(%rsp), %edx
	movl	16(%rsp), %esi
	movl	%ebx, %edi
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB24_2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	_Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_, .Lfunc_end24-_Z22backwardPassV2onDevice4dim3S_P12ihipStream_tiiiiPfS2_S2_S2_S2_S2_S2_PiS2_S2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii # -- Begin function _Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii
	.type	_Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii,@function
_Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii: # @_Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	72(%rsp), %ebx
	movl	64(%rsp), %ebp
	movq	56(%rsp), %r14
	movq	48(%rsp), %r15
	movslq	%r8d, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB25_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB25_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z36__device_stub__backwardPassV21KernelPfS_ii # TAILCALL
.Lfunc_end25:
	.size	_Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii, .Lfunc_end25-_Z23backwardPassV21onDevice4dim3S_iP12ihipStream_tPfS2_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_ # -- Begin function _Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_
	.type	_Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_,@function
_Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_: # @_Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%r9d, %ebx
	movq	%r8, %r9
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB26_2
# %bb.1:
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movl	24(%rsp), %edx
	movl	16(%rsp), %esi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%ebx, %edi
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB26_2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end26:
	.size	_Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_, .Lfunc_end26-_Z22backwardPassV3onDevice4dim3S_P12ihipStream_tiiiPfS2_S2_S2_PiS2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb # -- Begin function _Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb
	.type	_Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb,@function
_Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb: # @_Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %eax
                                        # kill: def $edi killed $edi def $rdi
	movb	80(%rsp), %bpl
	movl	72(%rsp), %ebx
	movq	64(%rsp), %r14
	movq	56(%rsp), %r15
	movq	48(%rsp), %r9
	cmpl	$31, %edi
	jg	.LBB27_6
# %bb.1:
	leal	-1(%rdi), %r10d
	cmpl	$7, %r10d
	ja	.LBB27_2
# %bb.5:
	jmpq	*.LJTI27_0(,%r10,8)
.LBB27_28:
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.30:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj1EEvPfS0_jb # TAILCALL
.LBB27_6:
	.cfi_def_cfa_offset 48
	cmpl	$127, %edi
	jle	.LBB27_7
# %bb.11:
	cmpl	$128, %edi
	je	.LBB27_18
# %bb.12:
	cmpl	$256, %edi                      # imm = 0x100
	je	.LBB27_16
# %bb.13:
	cmpl	$512, %edi                      # imm = 0x200
	jne	.LBB27_29
# %bb.14:
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.15:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj512EEvPfS0_jb # TAILCALL
.LBB27_7:
	.cfi_def_cfa_offset 48
	cmpl	$32, %edi
	je	.LBB27_20
# %bb.8:
	cmpl	$64, %edi
	jne	.LBB27_29
# %bb.9:
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.10:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj64EEvPfS0_jb # TAILCALL
.LBB27_2:
	.cfi_def_cfa_offset 48
	cmpl	$16, %edi
	jne	.LBB27_29
# %bb.3:
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.4:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj16EEvPfS0_jb # TAILCALL
.LBB27_24:
	.cfi_def_cfa_offset 48
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.25:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj4EEvPfS0_jb # TAILCALL
.LBB27_26:
	.cfi_def_cfa_offset 48
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.27:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj2EEvPfS0_jb # TAILCALL
.LBB27_22:
	.cfi_def_cfa_offset 48
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.23:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj8EEvPfS0_jb # TAILCALL
.LBB27_20:
	.cfi_def_cfa_offset 48
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.21:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj32EEvPfS0_jb # TAILCALL
.LBB27_18:
	.cfi_def_cfa_offset 48
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB27_29
# %bb.19:
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj128EEvPfS0_jb # TAILCALL
.LBB27_16:
	.cfi_def_cfa_offset 48
	cltq
	movq	%rsi, %rdi
	movl	%edx, %esi
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	movq	%rax, %r8
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB27_17
.LBB27_29:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB27_17:
	.cfi_def_cfa_offset 48
	movzbl	%bpl, %ecx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__reduceKernelILj256EEvPfS0_jb # TAILCALL
.Lfunc_end27:
	.size	_Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb, .Lfunc_end27-_Z14reduceOnDevicei4dim3S_iP12ihipStream_tPfS2_jb
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI27_0:
	.quad	.LBB27_28
	.quad	.LBB27_26
	.quad	.LBB27_29
	.quad	.LBB27_24
	.quad	.LBB27_29
	.quad	.LBB27_29
	.quad	.LBB27_29
	.quad	.LBB27_22
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj512EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj512EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj512EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj512EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj512EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj512EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj512EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj512EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end28:
	.size	_Z27__device_stub__reduceKernelILj512EEvPfS0_jb, .Lfunc_end28-_Z27__device_stub__reduceKernelILj512EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj256EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj256EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj256EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj256EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj256EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj256EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj256EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj256EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end29:
	.size	_Z27__device_stub__reduceKernelILj256EEvPfS0_jb, .Lfunc_end29-_Z27__device_stub__reduceKernelILj256EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj128EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj128EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj128EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj128EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj128EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj128EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj128EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj128EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end30:
	.size	_Z27__device_stub__reduceKernelILj128EEvPfS0_jb, .Lfunc_end30-_Z27__device_stub__reduceKernelILj128EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj64EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj64EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj64EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj64EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj64EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj64EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj64EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj64EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end31:
	.size	_Z27__device_stub__reduceKernelILj64EEvPfS0_jb, .Lfunc_end31-_Z27__device_stub__reduceKernelILj64EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj32EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj32EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj32EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj32EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj32EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj32EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj32EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj32EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end32:
	.size	_Z27__device_stub__reduceKernelILj32EEvPfS0_jb, .Lfunc_end32-_Z27__device_stub__reduceKernelILj32EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj16EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj16EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj16EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj16EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj16EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj16EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj16EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj16EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end33:
	.size	_Z27__device_stub__reduceKernelILj16EEvPfS0_jb, .Lfunc_end33-_Z27__device_stub__reduceKernelILj16EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj8EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj8EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj8EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj8EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj8EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj8EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj8EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj8EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end34:
	.size	_Z27__device_stub__reduceKernelILj8EEvPfS0_jb, .Lfunc_end34-_Z27__device_stub__reduceKernelILj8EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj4EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj4EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj4EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj4EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj4EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj4EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj4EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj4EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end35:
	.size	_Z27__device_stub__reduceKernelILj4EEvPfS0_jb, .Lfunc_end35-_Z27__device_stub__reduceKernelILj4EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj2EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj2EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj2EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj2EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj2EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj2EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj2EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj2EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end36:
	.size	_Z27__device_stub__reduceKernelILj2EEvPfS0_jb, .Lfunc_end36-_Z27__device_stub__reduceKernelILj2EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__reduceKernelILj1EEvPfS0_jb,"axG",@progbits,_Z27__device_stub__reduceKernelILj1EEvPfS0_jb,comdat
	.weak	_Z27__device_stub__reduceKernelILj1EEvPfS0_jb # -- Begin function _Z27__device_stub__reduceKernelILj1EEvPfS0_jb
	.type	_Z27__device_stub__reduceKernelILj1EEvPfS0_jb,@function
_Z27__device_stub__reduceKernelILj1EEvPfS0_jb: # @_Z27__device_stub__reduceKernelILj1EEvPfS0_jb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	11(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12reduceKernelILj1EEvPfS0_jb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end37:
	.size	_Z27__device_stub__reduceKernelILj1EEvPfS0_jb, .Lfunc_end37-_Z27__device_stub__reduceKernelILj1EEvPfS0_jb
	.cfi_endproc
                                        # -- End function
	.text
	.globl	_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_ # -- Begin function _Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_
	.type	_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_,@function
_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_: # @_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movl	%r8d, %ebp
	movq	32(%rsp), %r14
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB38_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB38_2:
	.cfi_def_cfa_offset 32
	movl	%ebp, %edi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_ # TAILCALL
.Lfunc_end38:
	.size	_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_, .Lfunc_end38-_Z26sumDeltaWeightsP2PonDevice4dim3S_iPfS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_ # -- Begin function _Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_
	.type	_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_,@function
_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_: # @_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movl	%r8d, %ebp
	movq	80(%rsp), %r14
	movq	72(%rsp), %r15
	movq	64(%rsp), %r12
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB39_2
# %bb.1:
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB39_2:
	.cfi_def_cfa_offset 64
	movl	%ebp, %edi
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_ # TAILCALL
.Lfunc_end39:
	.size	_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_, .Lfunc_end39-_Z24updateWeightsP2PonDevice4dim3S_iffPfS0_S0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19sumErrorP2PonDevice4dim3S_PfS0_ # -- Begin function _Z19sumErrorP2PonDevice4dim3S_PfS0_
	.type	_Z19sumErrorP2PonDevice4dim3S_PfS0_,@function
_Z19sumErrorP2PonDevice4dim3S_PfS0_:    # @_Z19sumErrorP2PonDevice4dim3S_PfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB40_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB40_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z32__device_stub__sumErrorP2PKernelPfS_ # TAILCALL
.Lfunc_end40:
	.size	_Z19sumErrorP2PonDevice4dim3S_PfS0_, .Lfunc_end40-_Z19sumErrorP2PonDevice4dim3S_PfS0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB41_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB41_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19forwardPassV2KerneliiPfS_S_iiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21backwardPassV11KerneliiiPfS_S_PiS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21backwardPassV21KernelPfS_ii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20backwardPassV3KerneliiiPfS_S_S_PiS_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19updateWeightsKernelffPfS_S_i, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24sumDeltaWeightsP2PKerneliPfS_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22updateWeightsP2PKerneliffPfS_S_S_, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17sumErrorP2PKernelPfS_, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19setInitStatesKernelfPfiii, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21resetParametersKerneliiPfS_S_S_S_, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23resetDeltaWeightsKerneliiPfS_, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj512EEvPfS0_jb, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj256EEvPfS0_jb, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj128EEvPfS0_jb, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj64EEvPfS0_jb, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj32EEvPfS0_jb, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj16EEvPfS0_jb, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj8EEvPfS0_jb, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj4EEvPfS0_jb, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj2EEvPfS0_jb, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12reduceKernelILj1EEvPfS0_jb, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end41:
	.size	__hip_module_ctor, .Lfunc_end41-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB42_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB42_2:
	retq
.Lfunc_end42:
	.size	__hip_module_dtor, .Lfunc_end42-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19forwardPassV2KerneliiPfS_S_iiS_,@object # @_Z19forwardPassV2KerneliiPfS_S_iiS_
	.section	.rodata,"a",@progbits
	.globl	_Z19forwardPassV2KerneliiPfS_S_iiS_
	.p2align	3, 0x0
_Z19forwardPassV2KerneliiPfS_S_iiS_:
	.quad	_Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_
	.size	_Z19forwardPassV2KerneliiPfS_S_iiS_, 8

	.type	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii,@object # @_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.globl	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.p2align	3, 0x0
_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii:
	.quad	_Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.size	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, 8

	.type	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii,@object # @_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.globl	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.p2align	3, 0x0
_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii:
	.quad	_Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.size	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii, 8

	.type	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_,@object # @_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.globl	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.p2align	3, 0x0
_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_:
	.quad	_Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.size	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, 8

	.type	_Z21backwardPassV11KerneliiiPfS_S_PiS_,@object # @_Z21backwardPassV11KerneliiiPfS_S_PiS_
	.globl	_Z21backwardPassV11KerneliiiPfS_S_PiS_
	.p2align	3, 0x0
_Z21backwardPassV11KerneliiiPfS_S_PiS_:
	.quad	_Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_
	.size	_Z21backwardPassV11KerneliiiPfS_S_PiS_, 8

	.type	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_,@object # @_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.globl	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.p2align	3, 0x0
_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_:
	.quad	_Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.size	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, 8

	.type	_Z21backwardPassV21KernelPfS_ii,@object # @_Z21backwardPassV21KernelPfS_ii
	.globl	_Z21backwardPassV21KernelPfS_ii
	.p2align	3, 0x0
_Z21backwardPassV21KernelPfS_ii:
	.quad	_Z36__device_stub__backwardPassV21KernelPfS_ii
	.size	_Z21backwardPassV21KernelPfS_ii, 8

	.type	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_,@object # @_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.globl	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.p2align	3, 0x0
_Z20backwardPassV3KerneliiiPfS_S_S_PiS_:
	.quad	_Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_
	.size	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_, 8

	.type	_Z19updateWeightsKernelffPfS_S_i,@object # @_Z19updateWeightsKernelffPfS_S_i
	.globl	_Z19updateWeightsKernelffPfS_S_i
	.p2align	3, 0x0
_Z19updateWeightsKernelffPfS_S_i:
	.quad	_Z34__device_stub__updateWeightsKernelffPfS_S_i
	.size	_Z19updateWeightsKernelffPfS_S_i, 8

	.type	_Z24sumDeltaWeightsP2PKerneliPfS_,@object # @_Z24sumDeltaWeightsP2PKerneliPfS_
	.globl	_Z24sumDeltaWeightsP2PKerneliPfS_
	.p2align	3, 0x0
_Z24sumDeltaWeightsP2PKerneliPfS_:
	.quad	_Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_
	.size	_Z24sumDeltaWeightsP2PKerneliPfS_, 8

	.type	_Z22updateWeightsP2PKerneliffPfS_S_S_,@object # @_Z22updateWeightsP2PKerneliffPfS_S_S_
	.globl	_Z22updateWeightsP2PKerneliffPfS_S_S_
	.p2align	3, 0x0
_Z22updateWeightsP2PKerneliffPfS_S_S_:
	.quad	_Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_
	.size	_Z22updateWeightsP2PKerneliffPfS_S_S_, 8

	.type	_Z17sumErrorP2PKernelPfS_,@object # @_Z17sumErrorP2PKernelPfS_
	.globl	_Z17sumErrorP2PKernelPfS_
	.p2align	3, 0x0
_Z17sumErrorP2PKernelPfS_:
	.quad	_Z32__device_stub__sumErrorP2PKernelPfS_
	.size	_Z17sumErrorP2PKernelPfS_, 8

	.type	_Z19setInitStatesKernelfPfiii,@object # @_Z19setInitStatesKernelfPfiii
	.globl	_Z19setInitStatesKernelfPfiii
	.p2align	3, 0x0
_Z19setInitStatesKernelfPfiii:
	.quad	_Z34__device_stub__setInitStatesKernelfPfiii
	.size	_Z19setInitStatesKernelfPfiii, 8

	.type	_Z21resetParametersKerneliiPfS_S_S_S_,@object # @_Z21resetParametersKerneliiPfS_S_S_S_
	.globl	_Z21resetParametersKerneliiPfS_S_S_S_
	.p2align	3, 0x0
_Z21resetParametersKerneliiPfS_S_S_S_:
	.quad	_Z36__device_stub__resetParametersKerneliiPfS_S_S_S_
	.size	_Z21resetParametersKerneliiPfS_S_S_S_, 8

	.type	_Z23resetDeltaWeightsKerneliiPfS_,@object # @_Z23resetDeltaWeightsKerneliiPfS_
	.globl	_Z23resetDeltaWeightsKerneliiPfS_
	.p2align	3, 0x0
_Z23resetDeltaWeightsKerneliiPfS_:
	.quad	_Z38__device_stub__resetDeltaWeightsKerneliiPfS_
	.size	_Z23resetDeltaWeightsKerneliiPfS_, 8

	.type	_Z12reduceKernelILj512EEvPfS0_jb,@object # @_Z12reduceKernelILj512EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj512EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj512EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj512EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj512EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj512EEvPfS0_jb
	.size	_Z12reduceKernelILj512EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj256EEvPfS0_jb,@object # @_Z12reduceKernelILj256EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj256EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj256EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj256EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj256EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj256EEvPfS0_jb
	.size	_Z12reduceKernelILj256EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj128EEvPfS0_jb,@object # @_Z12reduceKernelILj128EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj128EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj128EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj128EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj128EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj128EEvPfS0_jb
	.size	_Z12reduceKernelILj128EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj64EEvPfS0_jb,@object # @_Z12reduceKernelILj64EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj64EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj64EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj64EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj64EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj64EEvPfS0_jb
	.size	_Z12reduceKernelILj64EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj32EEvPfS0_jb,@object # @_Z12reduceKernelILj32EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj32EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj32EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj32EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj32EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj32EEvPfS0_jb
	.size	_Z12reduceKernelILj32EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj16EEvPfS0_jb,@object # @_Z12reduceKernelILj16EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj16EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj16EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj16EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj16EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj16EEvPfS0_jb
	.size	_Z12reduceKernelILj16EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj8EEvPfS0_jb,@object # @_Z12reduceKernelILj8EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj8EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj8EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj8EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj8EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj8EEvPfS0_jb
	.size	_Z12reduceKernelILj8EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj4EEvPfS0_jb,@object # @_Z12reduceKernelILj4EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj4EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj4EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj4EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj4EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj4EEvPfS0_jb
	.size	_Z12reduceKernelILj4EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj2EEvPfS0_jb,@object # @_Z12reduceKernelILj2EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj2EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj2EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj2EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj2EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj2EEvPfS0_jb
	.size	_Z12reduceKernelILj2EEvPfS0_jb, 8

	.type	_Z12reduceKernelILj1EEvPfS0_jb,@object # @_Z12reduceKernelILj1EEvPfS0_jb
	.section	.rodata._Z12reduceKernelILj1EEvPfS0_jb,"aG",@progbits,_Z12reduceKernelILj1EEvPfS0_jb,comdat
	.weak	_Z12reduceKernelILj1EEvPfS0_jb
	.p2align	3, 0x0
_Z12reduceKernelILj1EEvPfS0_jb:
	.quad	_Z27__device_stub__reduceKernelILj1EEvPfS0_jb
	.size	_Z12reduceKernelILj1EEvPfS0_jb, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19forwardPassV2KerneliiPfS_S_iiS_"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii"
	.size	.L__unnamed_2, 45

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii"
	.size	.L__unnamed_3, 42

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_"
	.size	.L__unnamed_4, 47

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z21backwardPassV11KerneliiiPfS_S_PiS_"
	.size	.L__unnamed_5, 39

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_"
	.size	.L__unnamed_6, 49

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z21backwardPassV21KernelPfS_ii"
	.size	.L__unnamed_7, 32

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z20backwardPassV3KerneliiiPfS_S_S_PiS_"
	.size	.L__unnamed_8, 40

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z19updateWeightsKernelffPfS_S_i"
	.size	.L__unnamed_9, 33

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z24sumDeltaWeightsP2PKerneliPfS_"
	.size	.L__unnamed_10, 34

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z22updateWeightsP2PKerneliffPfS_S_S_"
	.size	.L__unnamed_11, 38

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z17sumErrorP2PKernelPfS_"
	.size	.L__unnamed_12, 26

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z19setInitStatesKernelfPfiii"
	.size	.L__unnamed_13, 30

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z21resetParametersKerneliiPfS_S_S_S_"
	.size	.L__unnamed_14, 38

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"_Z23resetDeltaWeightsKerneliiPfS_"
	.size	.L__unnamed_15, 34

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"_Z12reduceKernelILj512EEvPfS0_jb"
	.size	.L__unnamed_16, 33

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"_Z12reduceKernelILj256EEvPfS0_jb"
	.size	.L__unnamed_17, 33

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"_Z12reduceKernelILj128EEvPfS0_jb"
	.size	.L__unnamed_18, 33

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"_Z12reduceKernelILj64EEvPfS0_jb"
	.size	.L__unnamed_19, 32

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"_Z12reduceKernelILj32EEvPfS0_jb"
	.size	.L__unnamed_20, 32

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"_Z12reduceKernelILj16EEvPfS0_jb"
	.size	.L__unnamed_21, 32

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"_Z12reduceKernelILj8EEvPfS0_jb"
	.size	.L__unnamed_22, 31

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"_Z12reduceKernelILj4EEvPfS0_jb"
	.size	.L__unnamed_23, 31

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"_Z12reduceKernelILj2EEvPfS0_jb"
	.size	.L__unnamed_24, 31

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"_Z12reduceKernelILj1EEvPfS0_jb"
	.size	.L__unnamed_25, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__forwardPassV2KerneliiPfS_S_iiS_
	.addrsig_sym _Z35__device_stub__forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.addrsig_sym _Z34__device_stub__forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.addrsig_sym _Z35__device_stub__backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.addrsig_sym _Z36__device_stub__backwardPassV11KerneliiiPfS_S_PiS_
	.addrsig_sym _Z35__device_stub__backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.addrsig_sym _Z36__device_stub__backwardPassV21KernelPfS_ii
	.addrsig_sym _Z35__device_stub__backwardPassV3KerneliiiPfS_S_S_PiS_
	.addrsig_sym _Z34__device_stub__updateWeightsKernelffPfS_S_i
	.addrsig_sym _Z39__device_stub__sumDeltaWeightsP2PKerneliPfS_
	.addrsig_sym _Z37__device_stub__updateWeightsP2PKerneliffPfS_S_S_
	.addrsig_sym _Z32__device_stub__sumErrorP2PKernelPfS_
	.addrsig_sym _Z34__device_stub__setInitStatesKernelfPfiii
	.addrsig_sym _Z36__device_stub__resetParametersKerneliiPfS_S_S_S_
	.addrsig_sym _Z38__device_stub__resetDeltaWeightsKerneliiPfS_
	.addrsig_sym _Z27__device_stub__reduceKernelILj512EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj256EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj128EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj64EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj32EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj16EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj8EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj4EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj2EEvPfS0_jb
	.addrsig_sym _Z27__device_stub__reduceKernelILj1EEvPfS0_jb
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19forwardPassV2KerneliiPfS_S_iiS_
	.addrsig_sym _Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.addrsig_sym _Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.addrsig_sym _Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.addrsig_sym _Z21backwardPassV11KerneliiiPfS_S_PiS_
	.addrsig_sym _Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.addrsig_sym _Z21backwardPassV21KernelPfS_ii
	.addrsig_sym _Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.addrsig_sym _Z19updateWeightsKernelffPfS_S_i
	.addrsig_sym _Z24sumDeltaWeightsP2PKerneliPfS_
	.addrsig_sym _Z22updateWeightsP2PKerneliffPfS_S_S_
	.addrsig_sym _Z17sumErrorP2PKernelPfS_
	.addrsig_sym _Z19setInitStatesKernelfPfiii
	.addrsig_sym _Z21resetParametersKerneliiPfS_S_S_S_
	.addrsig_sym _Z23resetDeltaWeightsKerneliiPfS_
	.addrsig_sym _Z12reduceKernelILj512EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj256EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj128EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj64EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj32EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj16EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj8EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj4EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj2EEvPfS0_jb
	.addrsig_sym _Z12reduceKernelILj1EEvPfS0_jb
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19forwardPassV2KerneliiPfS_S_iiS_ ; -- Begin function _Z19forwardPassV2KerneliiPfS_S_iiS_
	.globl	_Z19forwardPassV2KerneliiPfS_S_iiS_
	.p2align	8
	.type	_Z19forwardPassV2KerneliiPfS_S_iiS_,@function
_Z19forwardPassV2KerneliiPfS_S_iiS_:    ; @_Z19forwardPassV2KerneliiPfS_S_iiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x20
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
	s_mov_b32 s4, exec_lo
	v_max_i32_e32 v2, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_clause 0x2
	s_load_b64 s[10:11], s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[8:9], s[0:1], 0x18
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr2
	s_waitcnt lgkmcnt(0)
	s_add_i32 s10, s10, -1
	v_cmpx_le_i32_e64 s3, v1
	s_xor_b32 s12, exec_lo, s12
; %bb.2:
	v_mad_u64_u32 v[2:3], null, s10, s2, v[1:2]
; %bb.3:                                ; %Flow
	s_or_saveexec_b32 s12, s12
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
	s_xor_b32 exec_lo, exec_lo, s12
; %bb.4:
	s_mul_i32 s10, s10, s3
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
	v_add3_u32 v2, s10, s11, v1
; %bb.5:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s12
	v_mad_u64_u32 v[6:7], null, v1, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b64 s[0:1], s[0:1], 0x28
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[6:7]
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v0, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19forwardPassV2KerneliiPfS_S_iiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19forwardPassV2KerneliiPfS_S_iiS_, .Lfunc_end0-_Z19forwardPassV2KerneliiPfS_S_iiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii ; -- Begin function _Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.globl	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
	.p2align	8
	.type	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii,@function
_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii: ; @_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
; %bb.0:
	s_load_b64 s[20:21], s[0:1], 0x48
	v_lshl_add_u32 v1, v0, 2, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s20, v0
	s_cbranch_execz .LBB1_9
; %bb.1:
	s_mov_b32 s2, s15
	s_load_b512 s[4:19], s[0:1], 0x8
	v_mad_u64_u32 v[3:4], null, v0, s20, s[2:3]
	v_mov_b32_e32 v4, v2
	s_load_b32 s3, s[0:1], 0x5c
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_and_b32 s3, s3, 0xffff
	s_cmp_lt_u32 s3, 2
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_6
; %bb.2:                                ; %.lr.ph.preheader
	s_lshr_b32 s3, s3, 1
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	v_lshl_add_u32 v2, s3, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_5:                                ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_lshr_b32 s8, s3, 1
	s_cmp_gt_u32 s3, 1
	s_mov_b32 s3, s8
	s_cbranch_scc1 .LBB1_3
.LBB1_6:                                ; %._crit_edge
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_9
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_mul_i32 s22, s20, s20
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s23, s3
	ds_load_b32 v1, v0
	s_add_u32 s10, s10, s8
	s_addc_u32 s11, s11, s9
	s_add_i32 s22, s22, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	s_lshl_b64 s[22:23], s[22:23], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s12, s22
	s_addc_u32 s13, s13, s23
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[10:11]
	global_load_b32 v2, v0, s[12:13]
	s_add_u32 s12, s18, s8
	s_addc_u32 s13, s19, s9
	s_add_u32 s8, s14, s8
	s_addc_u32 s9, s15, s9
	s_load_b32 s12, s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v3, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v3, v3, 1.0
	v_div_scale_f32 v7, vcc_lo, 1.0, v3, 1.0
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v6, v7
	v_div_fmas_f32 v4, v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v4, v3, 1.0
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v4, 1.0, v3 :: v_dual_add_f32 v1, v1, v2
	global_store_b32 v0, v1, s[10:11]
	global_load_b32 v2, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, v1, v3
	s_clause 0x1
	global_store_b32 v0, v2, s[10:11]
	global_store_b32 v0, v2, s[8:9]
	global_load_b32 v1, v0, s[10:11]
	s_mul_i32 s8, s20, s0
	s_mov_b32 s9, s3
	s_add_i32 s8, s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_ge_u32 s2, s21
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v1, 0xbfb8aa3b, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_add_f32_e32 v1, 1.0, v1
	v_div_scale_f32 v2, null, v1, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v4, v3
	v_div_scale_f32 v4, vcc_lo, 1.0, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v4, v3
	v_fma_f32 v6, -v2, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v3
	v_fma_f32 v2, -v2, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v3, v5
	v_div_fixup_f32 v1, v2, v1, 1.0
	global_store_b32 v0, v1, s[4:5]
	s_cbranch_scc1 .LBB1_9
; %bb.8:
	s_add_i32 s0, s0, 1
	s_add_i32 s1, s2, s1
	s_mul_i32 s0, s0, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s1, s0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_load_b32 v2, v0, s[0:1]
	s_add_u32 s0, s16, s8
	s_addc_u32 s1, s17, s9
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v1, v1, v2
	global_store_b32 v0, v1, s[0:1]
.LBB1_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii, .Lfunc_end1-_Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 26
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii ; -- Begin function _Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.globl	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
	.p2align	8
	.type	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii,@function
_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii: ; @_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x54
	s_load_b64 s[2:3], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB2_6
; %bb.1:
	s_clause 0x3
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b64 s[16:17], s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x38
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, 0
	s_cmp_lt_i32 s2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v5, vcc_lo
	global_store_b32 v[2:3], v0, off
	s_cbranch_scc1 .LBB2_4
; %bb.2:                                ; %.lr.ph
	s_add_i32 s14, s16, -1
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v6, v1
	v_mov_b32_e32 v0, 0
	s_mul_i32 s19, s14, s3
	s_mul_i32 s18, s14, s2
	s_add_i32 s19, s19, s17
	s_mov_b64 s[14:15], 0
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v7, 31, v6
	s_cmp_lt_i32 s14, s3
	s_cselect_b32 s20, s19, s18
	s_cselect_b32 s22, s7, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	s_cselect_b32 s23, s6, s4
	s_ashr_i32 s21, s20, 31
	s_add_u32 s20, s14, s20
	s_addc_u32 s21, s15, s21
	v_add_nc_u32_e32 v6, s2, v6
	v_add_co_u32 v9, vcc_lo, s8, v9
	s_lshl_b64 s[20:21], s[20:21], 2
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	s_add_u32 s20, s23, s20
	s_addc_u32 s21, s22, s21
	global_load_b32 v7, v8, s[20:21]
	global_load_b32 v9, v[9:10], off
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_eq_u32 s2, s14
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v7, v9
	s_cbranch_scc0 .LBB2_3
.LBB2_4:                                ; %Flow120
	v_add_co_u32 v6, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v8, v[6:7], off
	v_mad_u64_u32 v[6:7], null, s2, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v9, null, v8, v8, 1.0
	v_div_scale_f32 v12, vcc_lo, 1.0, v8, 1.0
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v11, v10
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v0, v6
	v_mul_f32_e32 v11, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v9, v11, v12
	v_fmac_f32_e32 v11, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v9, v11, v12
	v_div_fmas_f32 v9, v9, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v8, v9, v8, 1.0
	v_sub_f32_e32 v9, 1.0, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v9
	v_fmac_f32_e32 v6, v0, v8
	global_store_b32 v[2:3], v6, off
	global_store_b32 v[4:5], v6, off
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, 0xbfb8aa3b, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_add_f32_e32 v0, 1.0, v0
	v_div_scale_f32 v4, null, v0, v0, 1.0
	v_div_scale_f32 v6, vcc_lo, 1.0, v0, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v2, v5
	v_mad_u64_u32 v[2:3], null, s2, s16, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v6, v5
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v4, v7, v6
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v7
	v_div_fixup_f32 v0, v4, v0, 1.0
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	global_store_b32 v[4:5], v0, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_6
; %bb.5:
	s_add_i32 s0, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s3
	v_add3_u32 v4, s0, s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v0, v1
	v_add_co_u32 v0, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB2_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii, .Lfunc_end2-_Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 816
; NumSgprs: 26
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_ ; -- Begin function _Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.globl	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
	.p2align	8
	.type	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_,@function
_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_: ; @_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b128 s[20:23], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s23, v2
	v_cmp_gt_i32_e64 s2, s22, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_7
; %bb.1:
	s_load_b512 s[4:19], s[0:1], 0x10
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
	v_cmpx_ne_u32_e32 0, v0
	s_xor_b32 s2, exec_lo, s2
; %bb.2:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s22, s20, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
; %bb.3:                                ; %Flow108
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_5
; %bb.4:
	s_add_i32 s3, s20, 1
	v_mad_u64_u32 v[4:5], null, s22, s20, v[2:3]
	s_mul_i32 s3, s3, s23
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_add3_u32 v6, s3, s21, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b32 v1, v[6:7], off
	global_load_b32 v8, v[8:9], off
	v_add_co_u32 v6, vcc_lo, s16, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v11, vcc_lo
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v1
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, 0.5, v1
	global_store_b32 v[6:7], v9, off
.LBB3_5:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	s_load_b64 s[0:1], s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s18, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v1, v[8:9], off
	v_add_co_u32 v8, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v10, v[8:9], off
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v1, v1, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v1, 1.0
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v5
	v_mul_f32_e32 v11, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v11, v9
	v_fmac_f32_e32 v11, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v4, v11, v9
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[8:9], null, v0, s22, v[2:3]
	v_div_fmas_f32 v2, v4, v5, v11
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v9, 31, v8
	v_div_fixup_f32 v4, v2, v1, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[8:9]
	v_sub_f32_e32 v8, 1.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s0, v1
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, v10, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[5:6], v3, off
	global_load_b32 v5, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, 0, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_7
; %bb.6:
	s_add_i32 s0, s20, -1
	v_mul_f32_e32 v3, v4, v3
	v_mad_u64_u32 v[5:6], null, s0, s22, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	global_load_b32 v2, v[5:6], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v3, v2
	global_store_b32 v[0:1], v5, off
.LBB3_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_, .Lfunc_end3-_Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 728
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21backwardPassV11KerneliiiPfS_S_PiS_ ; -- Begin function _Z21backwardPassV11KerneliiiPfS_S_PiS_
	.globl	_Z21backwardPassV11KerneliiiPfS_S_PiS_
	.p2align	8
	.type	_Z21backwardPassV11KerneliiiPfS_S_PiS_,@function
_Z21backwardPassV11KerneliiiPfS_S_PiS_: ; @_Z21backwardPassV11KerneliiiPfS_S_PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s17, v1
	v_cmp_le_i32_e64 s2, s18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_6
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, 0
	s_cmp_lt_i32 s17, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	global_store_b32 v[2:3], v0, off
	s_cbranch_scc1 .LBB4_6
; %bb.2:                                ; %.lr.ph
	v_mad_u64_u32 v[6:7], null, s17, s16, v[1:2]
	s_load_b64 s[2:3], s[0:1], 0x30
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	v_mul_lo_u32 v8, v1, s17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v9, 0
	s_mov_b32 s1, 0
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s4, 0
.LBB4_3:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v10, s1, v1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v10
	s_cbranch_execz .LBB4_5
; %bb.4:                                ;   in Loop: Header=BB4_3 Depth=1
	global_load_b32 v12, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v15, null, v12, v12, 1.0
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v15, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v17, v19, v17 :: v_dual_add_nc_u32 v10, s4, v8
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	v_div_scale_f32 v21, vcc_lo, 1.0, v12, 1.0
	global_load_b32 v13, v[6:7], off
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v0, s[8:9]
	s_load_b32 s0, s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v14, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v16, null, v14, v14, 1.0
	v_div_scale_f32 v19, s0, 1.0, v14, 1.0
	v_rcp_f32_e32 v18, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v16, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v20, v18
	v_mul_f32_e32 v20, v21, v17
	v_mul_f32_e32 v22, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, -v15, v20, v21
	v_fma_f32 v24, -v16, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v23, v17
	v_fmac_f32_e32 v22, v24, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v15, v20, v21
	v_fma_f32 v16, -v16, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v15, v15, v17, v20
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v16, v16, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v12, v15, v12, 1.0
	v_cmp_eq_u32_e32 vcc_lo, s4, v1
	v_div_fixup_f32 v14, v16, v14, 1.0
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v12, 1.0, v12
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v16, 1.0, v13
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v10, v10, v14
	v_cndmask_b32_e64 v14, 0, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v13, v16
	v_mul_f32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v14, v12
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v11, v10
	global_store_b32 v[2:3], v9, off
.LBB4_5:                                ;   in Loop: Header=BB4_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s4, s4, 1
	s_add_i32 s1, s1, s17
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s17, s4
	s_cbranch_scc1 .LBB4_3
.LBB4_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21backwardPassV11KerneliiiPfS_S_PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z21backwardPassV11KerneliiiPfS_S_PiS_, .Lfunc_end4-_Z21backwardPassV11KerneliiiPfS_S_PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 684
; NumSgprs: 22
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_ ; -- Begin function _Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.globl	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
	.p2align	8
	.type	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_,@function
_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_: ; @_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x6c
	s_load_b128 s[20:23], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v2, v0
	v_cmpx_gt_i32_e64 s22, v1
	s_cbranch_execz .LBB5_12
; %bb.1:
	s_clause 0x1
	s_load_b512 s[4:19], s[0:1], 0x10
	s_load_b128 s[24:27], s[0:1], 0x50
	s_mov_b32 s0, exec_lo
	v_cmpx_le_i32_e64 s23, v2
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB5_5
; %bb.2:
	v_mad_u64_u32 v[3:4], null, v0, s22, v[2:3]
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[6:7], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s26, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	global_store_b32 v[4:5], v1, off
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v1
	s_cbranch_execz .LBB5_4
; %bb.3:
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s18, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s18, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s19, v9, vcc_lo
	s_clause 0x1
	global_load_b32 v1, v[6:7], off
	global_load_b32 v3, v[10:11], off
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[10:11], null, v2, s22, v[0:1]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, s22, s20, v[2:3]
	v_cvt_f32_i32_e32 v1, v1
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s24, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s25, v11, vcc_lo
	global_load_b32 v12, v[6:7], off
	global_load_b32 v10, v[10:11], off
	v_add_co_u32 v6, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v9, vcc_lo
	v_div_scale_f32 v8, null, v3, v3, 1.0
	v_div_scale_f32 v15, vcc_lo, 1.0, v1, 1.0
	global_load_b32 v6, v[6:7], off
	v_div_scale_f32 v7, null, v1, v1, 1.0
	v_rcp_f32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v8, v11, 1.0
	v_fma_f32 v13, -v7, v9, 1.0
	v_fmac_f32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v13, v9
	v_div_scale_f32 v13, s0, 1.0, v3, 1.0
	v_mul_f32_e32 v16, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v8, v16, v13
	v_fmac_f32_e32 v16, v18, v11
	v_mul_f32_e32 v14, v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v8, v16, v13
	v_fma_f32 v17, -v7, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v17, v9
	v_fma_f32 v7, -v7, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v7, v7, v9, v14
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v8, v8, v11, v16
	v_cmp_eq_u32_e32 vcc_lo, v2, v0
	v_div_fixup_f32 v1, v7, v1, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v3, v8, v3, 1.0
	v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v1, 1.0, v1 :: v_dual_sub_f32 v8, 1.0, v12
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v3, v10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v12, v8
	v_mul_f32_e32 v2, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v0, v1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v6, v2
	global_store_b32 v[4:5], v0, off
.LBB5_4:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr0_vgpr1
.LBB5_5:                                ; %Flow151
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB5_12
; %bb.6:
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
	v_cmpx_ne_u32_e32 0, v0
	s_xor_b32 s0, exec_lo, s0
; %bb.7:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s22, s20, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
; %bb.8:                                ; %Flow150
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB5_10
; %bb.9:
	s_add_i32 s1, s20, 1
	v_mad_u64_u32 v[4:5], null, s22, s20, v[2:3]
	s_mul_i32 s1, s1, s23
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_add3_u32 v6, s1, s21, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b32 v1, v[6:7], off
	global_load_b32 v8, v[8:9], off
	v_add_co_u32 v6, vcc_lo, s16, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v11, vcc_lo
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v1
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, 0.5, v1
	global_store_b32 v[6:7], v9, off
.LBB5_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s18, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v1, v[8:9], off
	v_add_co_u32 v8, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v10, v[8:9], off
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v1, v1, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v1, 1.0
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v5
	v_mul_f32_e32 v11, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v11, v9
	v_fmac_f32_e32 v11, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v4, v11, v9
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[8:9], null, v0, s22, v[2:3]
	v_div_fmas_f32 v2, v4, v5, v11
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v9, 31, v8
	v_div_fixup_f32 v4, v2, v1, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[8:9]
	v_sub_f32_e32 v8, 1.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s24, v1
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, v10, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v2, vcc_lo
	global_store_b32 v[5:6], v3, off
	global_load_b32 v5, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v5
	s_cbranch_execz .LBB5_12
; %bb.11:
	s_add_i32 s0, s20, -1
	v_mul_f32_e32 v3, v4, v3
	v_mad_u64_u32 v[5:6], null, s0, s22, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	global_load_b32 v2, v[5:6], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v3, v2
	global_store_b32 v[0:1], v5, off
.LBB5_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_, .Lfunc_end5-_Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1308
; NumSgprs: 30
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21backwardPassV21KernelPfS_ii ; -- Begin function _Z21backwardPassV21KernelPfS_ii
	.globl	_Z21backwardPassV21KernelPfS_ii
	.p2align	8
	.type	_Z21backwardPassV21KernelPfS_ii,@function
_Z21backwardPassV21KernelPfS_ii:        ; @_Z21backwardPassV21KernelPfS_ii
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x10
	v_lshl_add_u32 v1, v0, 2, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s8, v0
	s_cbranch_execz .LBB6_8
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s2, s15, s9
	s_load_b32 s0, s[0:1], 0x24
	v_mad_u64_u32 v[3:4], null, v0, s8, s[2:3]
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_and_b32 s0, s0, 0xffff
	s_cmp_lt_u32 s0, 2
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_6
; %bb.2:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s0, 1
.LBB6_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB6_5
; %bb.4:                                ;   in Loop: Header=BB6_3 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB6_5:                                ;   in Loop: Header=BB6_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_cbranch_scc1 .LBB6_3
.LBB6_6:                                ; %._crit_edge
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s3, 0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB6_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB6_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21backwardPassV21KernelPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z21backwardPassV21KernelPfS_ii, .Lfunc_end6-_Z21backwardPassV21KernelPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_ ; -- Begin function _Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.globl	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
	.p2align	8
	.type	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_,@function
_Z20backwardPassV3KerneliiiPfS_S_S_PiS_: ; @_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v0, v2
	v_cmpx_gt_i32_e64 s17, v1
	s_cbranch_execz .LBB7_6
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x30
	s_mov_b32 s12, exec_lo
	v_cmpx_le_i32_e64 s18, v0
	s_cbranch_execz .LBB7_4
; %bb.2:
	v_mad_u64_u32 v[3:4], null, v2, s17, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_4
; %bb.3:
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s2, s16, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_co_u32 v7, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v1, v[7:8], off
	v_mad_u64_u32 v[7:8], null, s2, s17, v[2:3]
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v9, v[5:6], off
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v5, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v7, v[3:4], off
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(3)
	v_cvt_f32_i32_e32 v1, v1
	v_div_scale_f32 v6, null, v1, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v6, v8, 1.0
	v_fmac_f32_e32 v8, v10, v8
	v_div_scale_f32 v10, vcc_lo, 1.0, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v10, v8
	v_fma_f32 v12, -v6, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v8
	v_fma_f32 v6, -v6, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v8, v11
	v_div_fixup_f32 v1, v6, v1, 1.0
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v9, v1
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, v5, v1
	global_store_b32 v[3:4], v7, off
.LBB7_4:
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_6
; %bb.5:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v7, v[3:4], off
	v_mad_u64_u32 v[3:4], null, s17, s17, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v0, v[5:6], off
	global_load_b32 v8, v[3:4], off
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v7, v7
	v_div_scale_f32 v9, null, v7, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, 1.0, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v10
	v_fma_f32 v9, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v10, v12
	v_div_fixup_f32 v7, v9, v7, 1.0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v8, v0, v7
	v_add_co_u32 v0, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[3:4], v8, off
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB7_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20backwardPassV3KerneliiiPfS_S_S_PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z20backwardPassV3KerneliiiPfS_S_S_PiS_, .Lfunc_end7-_Z20backwardPassV3KerneliiiPfS_S_S_PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 748
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19updateWeightsKernelffPfS_S_i ; -- Begin function _Z19updateWeightsKernelffPfS_S_i
	.globl	_Z19updateWeightsKernelffPfS_S_i
	.p2align	8
	.type	_Z19updateWeightsKernelffPfS_S_i,@function
_Z19updateWeightsKernelffPfS_S_i:       ; @_Z19updateWeightsKernelffPfS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x28
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s4, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	global_load_b32 v6, v[2:3], off
	global_load_b32 v7, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v8, v[0:1], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v6, s1, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, s0, v7
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, v8, v6
	global_store_b32 v[0:1], v6, off
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v0, off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19updateWeightsKernelffPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z19updateWeightsKernelffPfS_S_i, .Lfunc_end8-_Z19updateWeightsKernelffPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24sumDeltaWeightsP2PKerneliPfS_ ; -- Begin function _Z24sumDeltaWeightsP2PKerneliPfS_
	.globl	_Z24sumDeltaWeightsP2PKerneliPfS_
	.p2align	8
	.type	_Z24sumDeltaWeightsP2PKerneliPfS_,@function
_Z24sumDeltaWeightsP2PKerneliPfS_:      ; @_Z24sumDeltaWeightsP2PKerneliPfS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB9_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB9_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24sumDeltaWeightsP2PKerneliPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z24sumDeltaWeightsP2PKerneliPfS_, .Lfunc_end9-_Z24sumDeltaWeightsP2PKerneliPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22updateWeightsP2PKerneliffPfS_S_S_ ; -- Begin function _Z22updateWeightsP2PKerneliffPfS_S_S_
	.globl	_Z22updateWeightsP2PKerneliffPfS_S_S_
	.p2align	8
	.type	_Z22updateWeightsP2PKerneliffPfS_S_S_,@function
_Z22updateWeightsP2PKerneliffPfS_S_S_:  ; @_Z22updateWeightsP2PKerneliffPfS_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x30
	s_load_b32 s3, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB10_2
; %bb.1:
	s_load_b256 s[8:15], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s14, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v1, vcc_lo
	global_load_b32 v8, v[2:3], off
	v_add_co_u32 v6, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v9, v[4:5], off
	global_load_b32 v10, v[6:7], off
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v8, s6, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, s5, v9
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v8, v10, v8
	global_store_b32 v[6:7], v8, off
	global_store_b32 v[0:1], v8, off
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v0, off
.LBB10_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22updateWeightsP2PKerneliffPfS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z22updateWeightsP2PKerneliffPfS_S_S_, .Lfunc_end10-_Z22updateWeightsP2PKerneliffPfS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17sumErrorP2PKernelPfS_ ; -- Begin function _Z17sumErrorP2PKernelPfS_
	.globl	_Z17sumErrorP2PKernelPfS_
	.p2align	8
	.type	_Z17sumErrorP2PKernelPfS_,@function
_Z17sumErrorP2PKernelPfS_:              ; @_Z17sumErrorP2PKernelPfS_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB11_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s2, s3
	global_store_b32 v0, v1, s[0:1]
.LBB11_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17sumErrorP2PKernelPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 4
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z17sumErrorP2PKernelPfS_, .Lfunc_end11-_Z17sumErrorP2PKernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 76
; NumSgprs: 4
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 4
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19setInitStatesKernelfPfiii ; -- Begin function _Z19setInitStatesKernelfPfiii
	.globl	_Z19setInitStatesKernelfPfiii
	.p2align	8
	.type	_Z19setInitStatesKernelfPfiii,@function
_Z19setInitStatesKernelfPfiii:          ; @_Z19setInitStatesKernelfPfiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB12_2
; %bb.1:                                ; %.sink.split
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s0, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_add_i32 s1, s0, 5
	v_cmp_le_i32_e32 vcc_lo, s0, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_cmp_gt_i32_e64 s0, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, s1, s2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s1, s3, v3, s1
	v_cndmask_b32_e64 v2, 0, s4, s0
	global_store_b32 v[0:1], v2, off
.LBB12_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19setInitStatesKernelfPfiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z19setInitStatesKernelfPfiii, .Lfunc_end12-_Z19setInitStatesKernelfPfiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21resetParametersKerneliiPfS_S_S_S_ ; -- Begin function _Z21resetParametersKerneliiPfS_S_S_S_
	.globl	_Z21resetParametersKerneliiPfS_S_S_S_
	.p2align	8
	.type	_Z21resetParametersKerneliiPfS_S_S_S_,@function
_Z21resetParametersKerneliiPfS_S_S_S_:  ; @_Z21resetParametersKerneliiPfS_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s3, s3, s2
	v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB13_4
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x28
	v_ashrrev_i32_e32 v3, 31, v2
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB13_3
; %bb.2:
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	v_mov_b32_e32 v10, 0
	v_add_co_u32 v8, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[6:7], v10, off
	global_store_b32 v[4:5], v10, off
	global_store_b32 v[2:3], v10, off
	global_store_b32 v[8:9], v10, off
.LBB13_3:                               ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB13_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21resetParametersKerneliiPfS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	_Z21resetParametersKerneliiPfS_S_S_S_, .Lfunc_end13-_Z21resetParametersKerneliiPfS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23resetDeltaWeightsKerneliiPfS_ ; -- Begin function _Z23resetDeltaWeightsKerneliiPfS_
	.globl	_Z23resetDeltaWeightsKerneliiPfS_
	.p2align	8
	.type	_Z23resetDeltaWeightsKerneliiPfS_,@function
_Z23resetDeltaWeightsKerneliiPfS_:      ; @_Z23resetDeltaWeightsKerneliiPfS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB14_3
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	global_store_b32 v[4:5], v0, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB14_3
; %bb.2:
	v_add_co_u32 v1, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB14_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23resetDeltaWeightsKerneliiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end14:
	.size	_Z23resetDeltaWeightsKerneliiPfS_, .Lfunc_end14-_Z23resetDeltaWeightsKerneliiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj512EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj512EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj512EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj512EEvPfS0_jb
	.globl	_Z12reduceKernelILj512EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj512EEvPfS0_jb,@function
_Z12reduceKernelILj512EEvPfS0_jb:       ; @_Z12reduceKernelILj512EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_or_b32 v1, s2, 10, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB15_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 10
	s_mov_b32 s1, 0
.LBB15_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 0x200, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB15_4
; %bb.3:                                ;   in Loop: Header=BB15_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB15_4:                               ;   in Loop: Header=BB15_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB15_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB15_6:                               ; %Flow78
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB15_8
; %bb.7:
	ds_load_b32 v2, v1 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v2
	ds_store_b32 v1, v5
.LBB15_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB15_10
; %bb.9:
	ds_load_b32 v2, v1 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v2
	ds_store_b32 v1, v5
.LBB15_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB15_12
; %bb.11:
	ds_load_b32 v2, v1 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v2
	ds_store_b32 v1, v5
.LBB15_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB15_14
; %bb.13:
	v_lshlrev_b32_e32 v2, 2, v0
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 64, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, 0, v2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB15_14:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB15_16
; %bb.15:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB15_16:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj512EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj512EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj512EEvPfS0_jb,comdat
.Lfunc_end15:
	.size	_Z12reduceKernelILj512EEvPfS0_jb, .Lfunc_end15-_Z12reduceKernelILj512EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 920
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj256EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj256EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj256EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj256EEvPfS0_jb
	.globl	_Z12reduceKernelILj256EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj256EEvPfS0_jb,@function
_Z12reduceKernelILj256EEvPfS0_jb:       ; @_Z12reduceKernelILj256EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 9, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB16_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 9
	s_mov_b32 s1, 0
.LBB16_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 0x100, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB16_4
; %bb.3:                                ;   in Loop: Header=BB16_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB16_4:                               ;   in Loop: Header=BB16_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB16_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB16_6:                               ; %Flow73
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB16_8
; %bb.7:
	ds_load_b32 v2, v1 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v2
	ds_store_b32 v1, v5
.LBB16_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB16_10
; %bb.9:
	ds_load_b32 v2, v1 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v2
	ds_store_b32 v1, v5
.LBB16_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB16_12
; %bb.11:
	v_lshlrev_b32_e32 v2, 2, v0
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 64, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, 0, v2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB16_12:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB16_14
; %bb.13:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB16_14:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj256EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj256EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj256EEvPfS0_jb,comdat
.Lfunc_end16:
	.size	_Z12reduceKernelILj256EEvPfS0_jb, .Lfunc_end16-_Z12reduceKernelILj256EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 856
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj128EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj128EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj128EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj128EEvPfS0_jb
	.globl	_Z12reduceKernelILj128EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj128EEvPfS0_jb,@function
_Z12reduceKernelILj128EEvPfS0_jb:       ; @_Z12reduceKernelILj128EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 8, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB17_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 8
	s_mov_b32 s1, 0
.LBB17_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 0x80, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB17_4
; %bb.3:                                ;   in Loop: Header=BB17_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB17_4:                               ;   in Loop: Header=BB17_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB17_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB17_6:                               ; %Flow68
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB17_8
; %bb.7:
	ds_load_b32 v2, v1 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v2
	ds_store_b32 v1, v5
.LBB17_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB17_10
; %bb.9:
	v_lshlrev_b32_e32 v2, 2, v0
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 64, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, 0, v2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB17_10:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB17_12
; %bb.11:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB17_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj128EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj128EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj128EEvPfS0_jb,comdat
.Lfunc_end17:
	.size	_Z12reduceKernelILj128EEvPfS0_jb, .Lfunc_end17-_Z12reduceKernelILj128EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 792
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj64EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj64EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj64EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj64EEvPfS0_jb
	.globl	_Z12reduceKernelILj64EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj64EEvPfS0_jb,@function
_Z12reduceKernelILj64EEvPfS0_jb:        ; @_Z12reduceKernelILj64EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 7, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB18_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 7
	s_mov_b32 s1, 0
.LBB18_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 64, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB18_4
; %bb.3:                                ;   in Loop: Header=BB18_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB18_4:                               ;   in Loop: Header=BB18_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB18_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB18_6:                               ; %Flow63
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s1, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB18_8
; %bb.7:
	v_lshlrev_b32_e32 v2, 2, v0
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 64, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, 0, v2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB18_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB18_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s6, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB18_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj64EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj64EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj64EEvPfS0_jb,comdat
.Lfunc_end18:
	.size	_Z12reduceKernelILj64EEvPfS0_jb, .Lfunc_end18-_Z12reduceKernelILj64EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 732
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj32EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj32EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj32EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj32EEvPfS0_jb
	.globl	_Z12reduceKernelILj32EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj32EEvPfS0_jb,@function
_Z12reduceKernelILj32EEvPfS0_jb:        ; @_Z12reduceKernelILj32EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 6, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB19_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 6
	s_mov_b32 s1, 0
.LBB19_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB19_4
; %bb.3:                                ;   in Loop: Header=BB19_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB19_4:                               ;   in Loop: Header=BB19_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB19_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB19_6:                               ; %Flow58
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s1, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB19_8
; %bb.7:
	v_add_nc_u32_e32 v2, 64, v1
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cmp_ne_u32_e64 s0, -1, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v4, 0, v4, s0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB19_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB19_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s6, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB19_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj32EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj32EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj32EEvPfS0_jb,comdat
.Lfunc_end19:
	.size	_Z12reduceKernelILj32EEvPfS0_jb, .Lfunc_end19-_Z12reduceKernelILj32EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj16EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj16EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj16EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj16EEvPfS0_jb
	.globl	_Z12reduceKernelILj16EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj16EEvPfS0_jb,@function
_Z12reduceKernelILj16EEvPfS0_jb:        ; @_Z12reduceKernelILj16EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 5, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB20_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 5
	s_mov_b32 s1, 0
.LBB20_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB20_4
; %bb.3:                                ;   in Loop: Header=BB20_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB20_4:                               ;   in Loop: Header=BB20_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB20_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB20_6:                               ; %Flow53
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s1, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB20_8
; %bb.7:
	v_add_nc_u32_e32 v2, 32, v1
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cmp_ne_u32_e64 s0, -1, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v4, 0, v4, s0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB20_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB20_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s6, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB20_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj16EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj16EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj16EEvPfS0_jb,comdat
.Lfunc_end20:
	.size	_Z12reduceKernelILj16EEvPfS0_jb, .Lfunc_end20-_Z12reduceKernelILj16EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj8EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj8EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj8EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj8EEvPfS0_jb
	.globl	_Z12reduceKernelILj8EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj8EEvPfS0_jb,@function
_Z12reduceKernelILj8EEvPfS0_jb:         ; @_Z12reduceKernelILj8EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 4, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB21_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 4
	s_mov_b32 s1, 0
.LBB21_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 8, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB21_4
; %bb.3:                                ;   in Loop: Header=BB21_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB21_4:                               ;   in Loop: Header=BB21_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB21_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB21_6:                               ; %Flow48
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s1, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB21_8
; %bb.7:
	v_add_nc_u32_e32 v2, 16, v1
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cmp_ne_u32_e64 s0, -1, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v4, 0, v4, s0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v5, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v4
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v6, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB21_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB21_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s6, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB21_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj8EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj8EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj8EEvPfS0_jb,comdat
.Lfunc_end21:
	.size	_Z12reduceKernelILj8EEvPfS0_jb, .Lfunc_end21-_Z12reduceKernelILj8EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj4EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj4EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj4EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj4EEvPfS0_jb
	.globl	_Z12reduceKernelILj4EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj4EEvPfS0_jb,@function
_Z12reduceKernelILj4EEvPfS0_jb:         ; @_Z12reduceKernelILj4EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 3, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB22_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 3
	s_mov_b32 s1, 0
.LBB22_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB22_4
; %bb.3:                                ;   in Loop: Header=BB22_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB22_4:                               ;   in Loop: Header=BB22_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB22_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB22_6:                               ; %Flow43
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s1, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB22_8
; %bb.7:
	v_add_nc_u32_e32 v2, 8, v1
	s_mov_b64 s[4:5], src_shared_base
	v_add_nc_u32_e32 v4, 4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cmp_ne_u32_e64 s0, -1, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	flat_load_b32 v3, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v2, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v3
	v_cndmask_b32_e64 v3, 0, v4, s0
	v_cndmask_b32_e64 v4, 0, s5, s0
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB22_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB22_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s6, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB22_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj4EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj4EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj4EEvPfS0_jb,comdat
.Lfunc_end22:
	.size	_Z12reduceKernelILj4EEvPfS0_jb, .Lfunc_end22-_Z12reduceKernelILj4EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj2EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj2EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj2EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj2EEvPfS0_jb
	.globl	_Z12reduceKernelILj2EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj2EEvPfS0_jb,@function
_Z12reduceKernelILj2EEvPfS0_jb:         ; @_Z12reduceKernelILj2EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 2, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB23_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 2
	s_mov_b32 s1, 0
.LBB23_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_add_nc_u32_e32 v3, 2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB23_4
; %bb.3:                                ;   in Loop: Header=BB23_2 Depth=1
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB23_4:                               ;   in Loop: Header=BB23_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB23_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB23_6:                               ; %Flow38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB23_8
; %bb.7:
	v_add_nc_u32_e32 v2, 4, v1
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	flat_load_b32 v3, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v2, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB23_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB23_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s6, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB23_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj2EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj2EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj2EEvPfS0_jb,comdat
.Lfunc_end23:
	.size	_Z12reduceKernelILj2EEvPfS0_jb, .Lfunc_end23-_Z12reduceKernelILj2EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12reduceKernelILj1EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj1EEvPfS0_jb,comdat
	.protected	_Z12reduceKernelILj1EEvPfS0_jb ; -- Begin function _Z12reduceKernelILj1EEvPfS0_jb
	.globl	_Z12reduceKernelILj1EEvPfS0_jb
	.p2align	8
	.type	_Z12reduceKernelILj1EEvPfS0_jb,@function
_Z12reduceKernelILj1EEvPfS0_jb:         ; @_Z12reduceKernelILj1EEvPfS0_jb
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 1, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB24_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s1, s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_bitcmp1_b32 s9, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s1, 1
	s_mov_b32 s1, 0
.LBB24_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v7, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_u32_e32 vcc_lo, s8, v7
	global_load_b32 v6, v[3:4], off
	s_or_b32 s11, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v6
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB24_4
; %bb.3:                                ;   in Loop: Header=BB24_2 Depth=1
	global_load_b32 v3, v[3:4], off offset:4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v3
.LBB24_4:                               ;   in Loop: Header=BB24_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB24_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB24_6:                               ; %Flow32
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB24_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB24_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12reduceKernelILj1EEvPfS0_jb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12reduceKernelILj1EEvPfS0_jb,"axG",@progbits,_Z12reduceKernelILj1EEvPfS0_jb,comdat
.Lfunc_end24:
	.size	_Z12reduceKernelILj1EEvPfS0_jb, .Lfunc_end24-_Z12reduceKernelILj1EEvPfS0_jb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym sdata
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19forwardPassV2KerneliiPfS_S_iiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19forwardPassV2KerneliiPfS_S_iiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         200
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z20forwardPassV21KerneliiPfS_S_S_S_S_S_Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z19forwardPassV1KerneliiPfS_S_S_S_S_Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z20backwardPassV1KerneliiiiPfS_S_S_S_S_S_PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21backwardPassV11KerneliiiPfS_S_PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z21backwardPassV11KerneliiiPfS_S_PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z20backwardPassV2KerneliiiiPfS_S_S_S_S_S_PiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21backwardPassV21KernelPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21backwardPassV21KernelPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20backwardPassV3KerneliiiPfS_S_S_PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z20backwardPassV3KerneliiiPfS_S_S_PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19updateWeightsKernelffPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19updateWeightsKernelffPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24sumDeltaWeightsP2PKerneliPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24sumDeltaWeightsP2PKerneliPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22updateWeightsP2PKerneliffPfS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22updateWeightsP2PKerneliffPfS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17sumErrorP2PKernelPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     4
    .sgpr_spill_count: 0
    .symbol:         _Z17sumErrorP2PKernelPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19setInitStatesKernelfPfiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19setInitStatesKernelfPfiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21resetParametersKerneliiPfS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21resetParametersKerneliiPfS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23resetDeltaWeightsKerneliiPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23resetDeltaWeightsKerneliiPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj512EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj512EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj256EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj256EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj128EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj128EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj64EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj64EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj32EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj32EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj16EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj16EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj8EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj8EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj4EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj4EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj2EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj2EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           1
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12reduceKernelILj1EEvPfS0_jb
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12reduceKernelILj1EEvPfS0_jb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
