#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>

#define E 2.71828182845904523536


__global__ void euler_gpu(float * array, float y0, float dt, int n){
    // Initial condition
    int tId = threadIdx.x + blockIdx.x * blockDim.x;
    if (tId < n) {
    	float initial_value = y0; 
	    for(size_t i = 1; i < tId; i++){
	        initial_value = initial_value + dt*powf(E, -dt*i);
	    };
	    array[tId] = initial_value;

	};
};



int main(int argc, char const *argv[]){
	cudaEvent_t start, stop;
	float dts[6] = {0.1, 0.01, 0.001, 0.0001, 0.00001, 0.000001};
    float y0 = -1.0;
    int block_size = 256;

    for(size_t i = 0; i < 6; i++){
    	int n = (int)(10/dts[i]);
    	float elapsed=0;
    	double error = 0;

    	float * resultados = (float *) malloc(n * sizeof(float));
    	float * d_r;

    	int grid_size = (int) ceil((float)n / block_size);

    	cudaEventCreate(&start);
		cudaEventCreate(&stop);

		cudaMalloc(&d_r, n * sizeof(float));
		cudaMemcpy(d_r, resultados, n * sizeof(float), cudaMemcpyHostToDevice);
		cudaEventRecord(start, 0);
		euler_gpu<<<grid_size, block_size>>>(d_r, y0, dts[i], n);
		cudaEventRecord(stop, 0);
		cudaEventSynchronize(stop);
		cudaEventElapsedTime(&elapsed, start, stop);
		cudaEventDestroy(start);
		cudaEventDestroy(stop);

		cudaMemcpy(resultados, d_r, n  * sizeof(float), cudaMemcpyDeviceToHost);
		for(int g = 0; g < n; g++){
			float real =  -powf(E, -dts[i]*g);
			error = error + powf((resultados[g]-real),2);
		}

		printf("Executed with %f dt\n", dts[i]);
		printf("The elapsed time in gpu was %.2f ms \n", elapsed);
		printf("Mean squared error: %.16f \n", error/n);		

		free(resultados);
		cudaFree(d_r);
    }
    return 0;
};




	.file	"tmpxft_0021aa7a_00000000-6_1b.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z9euler_gpuPfffiPfffi
	.type	_Z31__device_stub__Z9euler_gpuPfffiPfffi, @function
_Z31__device_stub__Z9euler_gpuPfffiPfffi:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	40(%rsp), %rdx
	movl	%esi, 12(%rsp)
	leaq	56(%rsp), %rdi
	leaq	68(%rsp), %rsi
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9euler_gpuPfffi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z31__device_stub__Z9euler_gpuPfffiPfffi, .-_Z31__device_stub__Z9euler_gpuPfffiPfffi
	.globl	_Z9euler_gpuPfffi
	.type	_Z9euler_gpuPfffi, @function
_Z9euler_gpuPfffi:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9euler_gpuPfffiPfffi
	.cfi_endproc
.LFE2053:
	.size	_Z9euler_gpuPfffi, .-_Z9euler_gpuPfffi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC7:
	.string	"Executed with %f dt\n"
.LC8:
	.string	"The elapsed time in gpu was %.2f ms \n"
.LC9:
	.string	"Mean squared error: %.16f \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$120, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	movabsq	$4333543705447025869, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4094254846650290799, %rax
	movq	%rax, 88(%rsp)
	movabsq	$3856831416703108524, %rax
	movq	%rax, 96(%rsp)
.L12:
	movss	80(%rsp,%r12,4), %xmm2
	movss	.LC1(%rip), %xmm0
	movl	$0x00000000, 28(%rsp)
	divss	%xmm2, %xmm0
	movss	%xmm2, 4(%rsp)
	cvttss2sil	%xmm0, %ebp
	movslq	%ebp, %r13
	salq	$2, %r13
	movq	%r13, %rdi
	call	malloc@PLT
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC3(%rip), %xmm0
	movq	%rax, %rbx
	call	ceilf@PLT
	leaq	32(%rsp), %rdi
	movss	%xmm0, 8(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	movq	%r13, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movss	8(%rsp), %xmm0
	salq	$8, %rdx
	movl	$1, %ecx
	movl	$1, 76(%rsp)
	movq	%rdx, 68(%rsp)
	cvttss2sil	%xmm0, %eax
	movl	%eax, 56(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	movq	56(%rsp), %rdi
	movl	64(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movss	4(%rsp), %xmm1
	movss	.LC4(%rip), %xmm0
	movl	%ebp, %esi
	movq	48(%rsp), %rdi
	call	_Z31__device_stub__Z9euler_gpuPfffiPfffi
.L9:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rsi
	movq	%r13, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	xorl	%r13d, %r13d
	call	cudaMemcpy@PLT
	movq	$0x000000000, 8(%rsp)
.L10:
	cmpl	%r13d, %ebp
	jle	.L16
	cvtsi2ssl	%r13d, %xmm0
	movss	4(%rsp), %xmm1
	xorps	.LC5(%rip), %xmm1
	mulss	%xmm0, %xmm1
	movss	.LC6(%rip), %xmm0
	call	powf@PLT
	addss	(%rbx,%r13,4), %xmm0
	incq	%r13
	mulss	%xmm0, %xmm0
	cvtss2sd	%xmm0, %xmm0
	addsd	8(%rsp), %xmm0
	movsd	%xmm0, 8(%rsp)
	jmp	.L10
.L16:
	movl	$2, %edi
	leaq	.LC7(%rip), %rsi
	movb	$1, %al
	incq	%r12
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC8(%rip), %rsi
	cvtss2sd	28(%rsp), %xmm0
	call	__printf_chk@PLT
	cvtsi2sdl	%ebp, %xmm1
	movl	$2, %edi
	movb	$1, %al
	movsd	8(%rsp), %xmm0
	leaq	.LC9(%rip), %rsi
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	cmpq	$6, %r12
	jne	.L12
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$120, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z9euler_gpuPfffi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9euler_gpuPfffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1092616192
	.align 4
.LC3:
	.long	998244352
	.align 4
.LC4:
	.long	-1082130432
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC5:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4
	.align 4
.LC6:
	.long	1076754516
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>

#define E 2.71828182845904523536


__global__ void euler_gpu(float * array, float y0, float dt, int n){
    // Initial condition
    int tId = threadIdx.x + blockIdx.x * blockDim.x;
    if (tId < n) {
    	float initial_value = y0; 
	    for(size_t i = 1; i < tId; i++){
	        initial_value = initial_value + dt*powf(E, -dt*i);
	    };
	    array[tId] = initial_value;

	};
};



int main(int argc, char const *argv[]){
	hipEvent_t start, stop;
	float dts[6] = {0.1, 0.01, 0.001, 0.0001, 0.00001, 0.000001};
    float y0 = -1.0;
    int block_size = 256;

    for(size_t i = 0; i < 6; i++){
    	int n = (int)(10/dts[i]);
    	float elapsed=0;
    	double error = 0;

    	float * resultados = (float *) malloc(n * sizeof(float));
    	float * d_r;

    	int grid_size = (int) ceil((float)n / block_size);

    	hipEventCreate(&start);
		hipEventCreate(&stop);

		hipMalloc(&d_r, n * sizeof(float));
		hipMemcpy(d_r, resultados, n * sizeof(float), hipMemcpyHostToDevice);
		hipEventRecord(start, 0);
		euler_gpu<<<grid_size, block_size>>>(d_r, y0, dts[i], n);
		hipEventRecord(stop, 0);
		hipEventSynchronize(stop);
		hipEventElapsedTime(&elapsed, start, stop);
		hipEventDestroy(start);
		hipEventDestroy(stop);

		hipMemcpy(resultados, d_r, n  * sizeof(float), hipMemcpyDeviceToHost);
		for(int g = 0; g < n; g++){
			float real =  -powf(E, -dts[i]*g);
			error = error + powf((resultados[g]-real),2);
		}

		printf("Executed with %f dt\n", dts[i]);
		printf("The elapsed time in gpu was %.2f ms \n", elapsed);
		printf("Mean squared error: %.16f \n", error/n);		

		free(resultados);
		hipFree(d_r);
    }
    return 0;
};




	.text
	.file	"1b.hip"
	.globl	_Z24__device_stub__euler_gpuPfffi # -- Begin function _Z24__device_stub__euler_gpuPfffi
	.type	_Z24__device_stub__euler_gpuPfffi,@function
_Z24__device_stub__euler_gpuPfffi:      # @_Z24__device_stub__euler_gpuPfffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	16(%rsp), %rdx
	movss	%xmm1, (%rdx)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rdi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9euler_gpuPfffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__euler_gpuPfffi, .Lfunc_end0-_Z24__device_stub__euler_gpuPfffi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3dcccccd                      # float 0.100000001
	.long	0x3c23d70a                      # float 0.00999999977
	.long	0x3a83126f                      # float 0.00100000005
	.long	0x38d1b717                      # float 9.99999974E-5
.LCPI1_4:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI1_1:
	.long	0x41200000                      # float 10
.LCPI1_2:
	.long	0x3b800000                      # float 0.00390625
.LCPI1_3:
	.long	0xbf800000                      # float -1
.LCPI1_5:
	.long	0x402df854                      # float 2.71828175
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	movapd	.LCPI1_0(%rip), %xmm0           # xmm0 = [1.00000001E-1,9.99999977E-3,1.00000005E-3,9.99999974E-5]
	movapd	%xmm0, 80(%rsp)
	movabsq	$3856831416703108524, %rax      # imm = 0x358637BD3727C5AC
	movq	%rax, 96(%rsp)
	xorl	%r13d, %r13d
	leaq	256(%rcx), %r12
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
	movss	80(%rsp,%r13,4), %xmm1          # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm1, 48(%rsp)                 # 16-byte Spill
	divss	%xmm1, %xmm0
	movaps	%xmm0, 32(%rsp)                 # 16-byte Spill
	cvttss2si	%xmm0, %ebx
	movl	$0, 4(%rsp)
	movslq	%ebx, %r14
	shlq	$2, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %rbp
	cvttps2dq	32(%rsp), %xmm0         # 16-byte Folded Reload
	cvtdq2ps	%xmm0, %xmm0
	mulss	.LCPI1_2(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r15d
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	8(%rsp), %rdi
	movq	%rbp, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %r15
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	8(%rsp), %rdi
	movss	.LCPI1_3(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	48(%rsp), %xmm1                 # 16-byte Reload
	movl	%ebx, %esi
	callq	_Z24__device_stub__euler_gpuPfffi
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	4(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rsi
	movq	%rbp, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%ebx, %ebx
	jle	.LBB1_4
# %bb.7:                                # %.lr.ph
                                        #   in Loop: Header=BB1_1 Depth=1
	movaps	48(%rsp), %xmm0                 # 16-byte Reload
	xorps	.LCPI1_4(%rip), %xmm0
	movaps	%xmm0, 64(%rsp)                 # 16-byte Spill
	movl	%ebx, %r14d
	xorps	%xmm0, %xmm0
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
	xorl	%r15d, %r15d
.LBB1_8:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r15d, %xmm1
	mulss	64(%rsp), %xmm1                 # 16-byte Folded Reload
	movss	.LCPI1_5(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	callq	powf
	addss	(%rbp,%r15,4), %xmm0
	mulss	%xmm0, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movsd	32(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 32(%rsp)                 # 8-byte Spill
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB1_8
	jmp	.LBB1_5
.LBB1_4:                                #   in Loop: Header=BB1_1 Depth=1
	xorps	%xmm0, %xmm0
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_1 Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	48(%rsp), %xmm0                 # 16-byte Folded Reload
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm1, %xmm1
	cvtsi2sd	%ebx, %xmm1
	movsd	32(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	%rbp, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	incq	%r13
	cmpq	$6, %r13
	jne	.LBB1_1
# %bb.6:
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9euler_gpuPfffi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9euler_gpuPfffi,@object       # @_Z9euler_gpuPfffi
	.section	.rodata,"a",@progbits
	.globl	_Z9euler_gpuPfffi
	.p2align	3, 0x0
_Z9euler_gpuPfffi:
	.quad	_Z24__device_stub__euler_gpuPfffi
	.size	_Z9euler_gpuPfffi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Executed with %f dt\n"
	.size	.L.str, 21

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"The elapsed time in gpu was %.2f ms \n"
	.size	.L.str.1, 38

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Mean squared error: %.16f \n"
	.size	.L.str.2, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9euler_gpuPfffi"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__euler_gpuPfffi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9euler_gpuPfffi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9euler_gpuPfffi       ; -- Begin function _Z9euler_gpuPfffi
	.globl	_Z9euler_gpuPfffi
	.p2align	8
	.type	_Z9euler_gpuPfffi,@function
_Z9euler_gpuPfffi:                      ; @_Z9euler_gpuPfffi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, s4
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_u32_e32 1, v1
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.lr.ph
	v_mov_b32_e32 v0, s4
	s_mov_b64 s[6:7], 1
	s_mov_b32 s4, 0
	s_mov_b32 s8, 0x3e76c4e1
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_clz_i32_u32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s2, s2, 32
	s_lshl_b64 s[10:11], s[6:7], s2
	s_sub_i32 s2, 32, s2
	s_min_u32 s9, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 s9, s11, s9
	s_add_u32 s6, s6, 1
	v_cvt_f32_u32_e32 v3, s9
	s_addc_u32 s7, s7, 0
	v_ldexp_f32 v3, v3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e64 v3, -s5, v3
	v_cmp_eq_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v4, 0x402df854, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v5, v4
	v_frexp_exp_i32_f32_e32 v4, v4
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, 0, 1, s2
	v_subrev_co_ci_u32_e64 v4, s2, 0, v4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v5, v5, v6
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, -1.0, v5 :: v_dual_mul_f32 v10, 0x3f317218, v4
	v_add_f32_e32 v6, 1.0, v5
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v7, v8
	v_add_f32_e32 v9, -1.0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v9
	v_fma_f32 v9, 0x3f317218, v4, -v10
	v_dual_fmac_f32 v9, 0xb102e308, v4 :: v_dual_mul_f32 v4, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v11, v6, -v4
	v_fmac_f32_e32 v6, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v4, v6
	v_sub_f32_e32 v12, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v12
	v_dual_sub_f32 v4, v5, v4 :: v_dual_sub_f32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v6
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v12, v4
	v_mul_f32_e32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v11, v4
	v_sub_f32_e32 v6, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v4, v4, v6 :: v_dual_mul_f32 v7, v5, v5
	v_ldexp_f32 v8, v5, 1
	v_add_f32_e32 v11, v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v5, v5, -v7
	v_ldexp_f32 v12, v4, 1
	v_fmac_f32_e32 v6, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v7, v6
	v_fmaak_f32 v13, s8, v11, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v5, v11 :: v_dual_fmaak_f32 v13, v11, v13, 0x3ecccdef
	v_sub_f32_e32 v7, v11, v7
	v_dual_mul_f32 v15, v11, v13 :: v_dual_sub_f32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v11, v5, -v14
	v_fmac_f32_e32 v7, v11, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v11, v13, -v15
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v6, v13
	v_add_f32_e32 v6, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v6, v15
	v_dual_add_f32 v5, v14, v7 :: v_dual_sub_f32 v4, v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v5, v14
	v_add_f32_e32 v14, 0x3f2aaaaa, v6
	v_dual_add_f32 v4, 0x31739010, v4 :: v_dual_sub_f32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, 0xbf2aaaaa, v14
	v_sub_f32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v6
	v_add_f32_e32 v6, v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v14, v6
	v_dual_mul_f32 v13, v5, v6 :: v_dual_add_f32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v5, v6, -v13
	v_fmac_f32_e32 v11, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v7, v6
	v_add_f32_e32 v4, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v4, v13
	v_dual_add_f32 v5, v8, v4 :: v_dual_sub_f32 v6, v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v5, v8 :: v_dual_add_f32 v6, v12, v6
	v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v7, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v4
	v_add_f32_e32 v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v7, v10 :: v_dual_sub_f32 v5, v8, v5
	v_dual_sub_f32 v6, v9, v6 :: v_dual_add_f32 v9, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v9, v7
	v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v7, v5 :: v_dual_sub_f32 v8, v8, v10
	v_dual_add_f32 v10, v6, v4 :: v_dual_add_f32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v10, v6
	v_add_f32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v10, v7
	v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v7, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_sub_f32_e32 v8, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v4, v4, v6
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v4
	v_dual_sub_f32 v6, v5, v7 :: v_dual_mul_f32 v7, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v6
	v_fma_f32 v5, v3, v5, -v7
	v_cmp_class_f32_e64 s2, v7, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v3, v4
	v_add_f32_e32 v4, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v4, v7, s2
	v_sub_f32_e32 v4, v4, v7
	v_cmp_eq_f32_e64 s2, 0x42b17218, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v5, v4
	v_cndmask_b32_e64 v8, 0, 0x37000000, s2
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v6, v8
	v_cndmask_b32_e64 v4, 0, v4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v9
	v_add_f32_e32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v12, v10
	v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
	v_cvt_i32_f32_e32 v7, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v11
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0, v5, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v9
	v_cndmask_b32_e64 v5, 0x7f800000, v5, s2
	v_cmp_eq_f32_e64 s2, |v3|, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v5, v4, v5
	v_cndmask_b32_e64 v6, 0, |v3|, s2
	v_cmp_class_f32_e64 s2, v3, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v6, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	v_cndmask_b32_e64 v4, |v4|, v6, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
	v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[1:2]
	v_fmac_f32_e32 v0, s5, v3
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:                                ; %Flow29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9euler_gpuPfffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9euler_gpuPfffi, .Lfunc_end0-_Z9euler_gpuPfffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1236
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9euler_gpuPfffi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9euler_gpuPfffi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
