#include "includes.h"
__global__ void compute_G_cols_kernel(int N_i, int N_r, int N_c, int* p_ptr, double* exp_V_ptr, double* N_ptr, int N_ld, double* G_ptr, int G_ld, double* G_cols_ptr, int G_cols_ld) {
int I = threadIdx.x + blockIdx.x * BLOCK_SIZE_x;  // blockDim.x;

int l_MIN = BLOCK_SIZE_y * (blockIdx.y + 0);
int l_MAX = BLOCK_SIZE_y * (blockIdx.y + 1);

l_MIN = max(l_MIN, 0);
l_MAX = min(l_MAX, N_i);

if (I < N_r) {
// for(int l=0; l<N_i; ++l)
for (int l = l_MIN; l < l_MAX; ++l) {
if (p_ptr[l] >= N_c) {
G_cols_ptr[I + l * G_cols_ld] = G_ptr[I + (p_ptr[l] - N_c) * G_ld];
}
else {
double alpha = exp_V_ptr[l] / (exp_V_ptr[l] - 1.);

G_cols_ptr[I + l * G_cols_ld] = alpha * N_ptr[I + p_ptr[l] * N_ld];
}
}

// for(int l=0; l<N_i; ++l)
for (int l = l_MIN; l < l_MAX; ++l)
if (p_ptr[l] < N_c and I == p_ptr[l])
G_cols_ptr[I + l * G_cols_ld] -= 1. / (exp_V_ptr[l] - 1.);
}
}
	.file	"tmpxft_003403f0_00000000-6_compute_G_cols_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z58__device_stub__Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_iiiiPiPdS0_iS0_iS0_i
	.type	_Z58__device_stub__Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_iiiiPiPdS0_iS0_iS0_i, @function
_Z58__device_stub__Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_iiiiPiPdS0_iS0_iS0_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	248(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	264(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z58__device_stub__Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_iiiiPiPdS0_iS0_iS0_i, .-_Z58__device_stub__Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_iiiiPiPdS0_iS0_iS0_i
	.globl	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.type	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, @function
_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_iiiiPiPdS0_iS0_iS0_i
	.cfi_endproc
.LFE2033:
	.size	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, .-_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_G_cols_kernel(int N_i, int N_r, int N_c, int* p_ptr, double* exp_V_ptr, double* N_ptr, int N_ld, double* G_ptr, int G_ld, double* G_cols_ptr, int G_cols_ld) {
int I = threadIdx.x + blockIdx.x * BLOCK_SIZE_x;  // blockDim.x;

int l_MIN = BLOCK_SIZE_y * (blockIdx.y + 0);
int l_MAX = BLOCK_SIZE_y * (blockIdx.y + 1);

l_MIN = max(l_MIN, 0);
l_MAX = min(l_MAX, N_i);

if (I < N_r) {
// for(int l=0; l<N_i; ++l)
for (int l = l_MIN; l < l_MAX; ++l) {
if (p_ptr[l] >= N_c) {
G_cols_ptr[I + l * G_cols_ld] = G_ptr[I + (p_ptr[l] - N_c) * G_ld];
}
else {
double alpha = exp_V_ptr[l] / (exp_V_ptr[l] - 1.);

G_cols_ptr[I + l * G_cols_ld] = alpha * N_ptr[I + p_ptr[l] * N_ld];
}
}

// for(int l=0; l<N_i; ++l)
for (int l = l_MIN; l < l_MAX; ++l)
if (p_ptr[l] < N_c and I == p_ptr[l])
G_cols_ptr[I + l * G_cols_ld] -= 1. / (exp_V_ptr[l] - 1.);
}
}
	.text
	.file	"compute_G_cols_kernel.hip"
	.globl	_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i # -- Begin function _Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.type	_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i,@function
_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i: # @_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, .Lfunc_end0-_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i,@object # @_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.section	.rodata,"a",@progbits
	.globl	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.p2align	3, 0x0
_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i:
	.quad	_Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.size	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i"
	.size	.L__unnamed_1, 45

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i ; -- Begin function _Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.globl	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
	.p2align	8
	.type	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i,@function
_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i: ; @_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_lshl_b32 s8, s14, 5
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v1, s8, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s5, v1
	s_cbranch_execz .LBB0_13
; %bb.1:                                ; %.preheader62
	s_lshl_b32 s2, s15, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s3, s2, 8
	s_max_i32 s2, s2, 0
	s_min_i32 s7, s3, s4
	s_mov_b32 s3, 0
	s_cmp_ge_i32 s2, s7
	s_cbranch_scc1 .LBB0_13
; %bb.2:                                ; %.lr.ph.preheader
	s_clause 0x6
	s_load_b32 s18, s[0:1], 0x48
	s_load_b128 s[24:27], s[0:1], 0x10
	s_load_b64 s[10:11], s[0:1], 0x20
	s_load_b32 s19, s[0:1], 0x28
	s_load_b64 s[12:13], s[0:1], 0x30
	s_load_b32 s20, s[0:1], 0x38
	s_load_b64 s[0:1], s[0:1], 0x40
	s_lshl_b64 s[4:5], s[2:3], 3
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s9, s18, s2
	s_add_u32 s4, s26, s4
	v_add3_u32 v2, s8, s9, v0
	s_addc_u32 s5, s27, s5
	s_lshl_b64 s[8:9], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s8, s24, s8
	v_mov_b32_e32 v3, v2
	s_addc_u32 s9, s25, s9
	s_mov_b64 s[16:17], s[4:5]
	s_mov_b64 s[14:15], s[8:9]
	s_mov_b32 s3, s2
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s21, s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s21, s6
	s_cbranch_scc1 .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_sub_i32 s22, s21, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s22, s20, v[1:2]
	s_mov_b32 s22, 0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_load_b64 v[5:6], v[4:5], off
	s_branch .LBB0_6
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_6:                                ; %Flow110
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[4:5], v0, s[16:17]
	v_mad_u64_u32 v[10:11], null, s21, s19, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[4:5], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
	v_rcp_f64_e32 v[12:13], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[6:7], v[4:5]
	v_mul_f64 v[16:17], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[5:6], v[10:11], v[4:5]
.LBB0_8:                                ;   in Loop: Header=BB0_3 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s3, s3, 1
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s14, s14, 4
	v_lshlrev_b64 v[7:8], 3, v[3:4]
	v_add_nc_u32_e32 v3, s18, v3
	s_addc_u32 s15, s15, 0
	s_cmp_ge_i32 s3, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
	s_cbranch_scc0 .LBB0_3
; %bb.9:
	v_mov_b32_e32 v0, 0
.LBB0_10:                               ; %.lr.ph65
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s3, s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s3, v1
	s_cmp_lt_i32 s3, s6
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, s3, vcc_lo
	s_and_saveexec_b32 s3, s10
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	global_load_b64 v[3:4], v0, s[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[3:4], -1.0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[2:3]
	v_add_co_u32 v10, vcc_lo, s0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	global_load_b64 v[12:13], v[10:11], off
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], -1.0
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9]
	v_fma_f64 v[14:15], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9]
	v_div_scale_f64 v[14:15], vcc_lo, -1.0, v[4:5], -1.0
	v_mul_f64 v[16:17], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[6:7], v[4:5], -1.0
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[12:13], v[3:4]
	global_store_b64 v[10:11], v[3:4], off
.LBB0_12:                               ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s2, s2, 1
	s_add_u32 s4, s4, 8
	v_add_nc_u32_e32 v2, s18, v2
	s_addc_u32 s5, s5, 0
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_lt_i32 s2, s7
	s_cbranch_scc1 .LBB0_10
.LBB0_13:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 76
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i, .Lfunc_end0-_Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 828
; NumSgprs: 30
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 76
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z21compute_G_cols_kerneliiiPiPdS0_iS0_iS0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
