//n<=4096, m<=1024
__global__ void approxmatch(int b,int n,int m,const float * __restrict__ xyz1,const float * __restrict__ xyz2,float * __restrict__ match){
	const int MaxN=4096,MaxM=1024;
	__shared__ float remainL[MaxN],remainR[MaxM],ratioR[MaxM],ratioL[MaxN];
	__shared__ int listR[MaxM],lc;
	float multiL,multiR;
	if (n>=m){
		multiL=1;
		multiR=n/m;
	}else{
		multiL=m/n;
		multiR=1;
	}
	for (int i=blockIdx.x;i<b;i+=gridDim.x){
		for (int j=threadIdx.x;j<n*m;j+=blockDim.x)
			match[i*n*m+j]=0;
		for (int j=threadIdx.x;j<n;j+=blockDim.x)
			remainL[j]=multiL;
		for (int j=threadIdx.x;j<m;j+=blockDim.x)
			remainR[j]=multiR;
		__syncthreads();
		for (int j=7;j>=-2;j--){
			float level=-powf(4.0f,j);
			if (j==-2){
				level=0;
			}
			if (threadIdx.x==0){
				lc=0;
				for (int k=0;k<m;k++)
					if (remainR[k]>0)
						listR[lc++]=k;
			}
			__syncthreads();
			int _lc=lc;
			for (int k=threadIdx.x;k<n;k+=blockDim.x){
				float suml=1e-9f;
				float x1=xyz1[(i*n+k)*3+0];
				float y1=xyz1[(i*n+k)*3+1];
				float z1=xyz1[(i*n+k)*3+2];
				//for (int l=0;l<m;l++){
				for (int _l=0;_l<_lc;_l++){
					int l=listR[_l];
					float x2=xyz2[(i*m+l)*3+0]-x1;
					float y2=xyz2[(i*m+l)*3+1]-y1;
					float z2=xyz2[(i*m+l)*3+2]-z1;
					float w=expf(level*(x2*x2+y2*y2+z2*z2))*remainR[l];
					suml+=w;
				}
				ratioL[k]=remainL[k]/suml;
			}
			__syncthreads();
			//for (int k=threadIdx.x;k<m;k+=blockDim.x){
			for (int _k=threadIdx.x;_k<lc;_k+=blockDim.x){
				int k=listR[_k];
				float sumr=0;
				float x2=xyz2[(i*m+k)*3+0];
				float y2=xyz2[(i*m+k)*3+1];
				float z2=xyz2[(i*m+k)*3+2];
				for (int l=0;l<n;l++){
					float x1=xyz1[(i*n+l)*3+0]-x2;
					float y1=xyz1[(i*n+l)*3+1]-y2;
					float z1=xyz1[(i*n+l)*3+2]-z2;
					float w=expf(level*(x1*x1+y1*y1+z1*z1))*ratioL[l];
					sumr+=w;
				}
				sumr*=remainR[k];
				float consumption=fminf(remainR[k]/(sumr+1e-9f),1.0f);
				ratioR[k]=consumption*remainR[k];
				remainR[k]=fmaxf(0.0f,remainR[k]-sumr);
			}
			__syncthreads();
			for (int k=threadIdx.x;k<n;k+=blockDim.x){
				float suml=0;
				float x1=xyz1[(i*n+k)*3+0];
				float y1=xyz1[(i*n+k)*3+1];
				float z1=xyz1[(i*n+k)*3+2];
				for (int _l=0;_l<_lc;_l++){
					int l=listR[_l];
					float x2=xyz2[(i*m+l)*3+0]-x1;
					float y2=xyz2[(i*m+l)*3+1]-y1;
					float z2=xyz2[(i*m+l)*3+2]-z1;
					float w=expf(level*(x2*x2+y2*y2+z2*z2))*ratioL[k]*ratioR[l];
					match[i*n*m+l*n+k]+=w;
					suml+=w;
				}
				remainL[k]=fmaxf(0.0f,remainL[k]-suml);
			}
			__syncthreads();
		}
	}
}
void approxmatchLauncher(int b,int n,int m,const float * xyz1,const float * xyz2,float * match){
	approxmatch<<<32,512>>>(b,n,m,xyz1,xyz2,match);
}
__global__ void matchcost(int b,int n,int m,const float * __restrict__ xyz1,const float * __restrict__ xyz2,const float * __restrict__ match,float * __restrict__ out){
	__shared__ float allsum[512];
	const int Block=256;
	__shared__ float buf[Block*3];
	for (int i=blockIdx.x;i<b;i+=gridDim.x){
		float subsum=0;
		for (int k0=0;k0<m;k0+=Block){
			int endk=min(m,k0+Block);
			for (int k=threadIdx.x;k<(endk-k0)*3;k+=blockDim.x){
				buf[k]=xyz2[i*m*3+k0*3+k];
			}
			__syncthreads();
			for (int j=threadIdx.x;j<n;j+=blockDim.x){
				float x1=xyz1[(i*n+j)*3+0];
				float y1=xyz1[(i*n+j)*3+1];
				float z1=xyz1[(i*n+j)*3+2];
				for (int k=0;k<endk-k0;k++){
					//float x2=xyz2[(i*m+k)*3+0]-x1;
					//float y2=xyz2[(i*m+k)*3+1]-y1;
					//float z2=xyz2[(i*m+k)*3+2]-z1;
					float x2=buf[k*3+0]-x1;
					float y2=buf[k*3+1]-y1;
					float z2=buf[k*3+2]-z1;
					float d=sqrtf(x2*x2+y2*y2+z2*z2);
					subsum+=match[i*n*m+(k0+k)*n+j]*d;
				}
			}
			__syncthreads();
		}
		allsum[threadIdx.x]=subsum;
		for (int j=1;j<blockDim.x;j<<=1){
			__syncthreads();
			if ((threadIdx.x&j)==0 && threadIdx.x+j<blockDim.x){
				allsum[threadIdx.x]+=allsum[threadIdx.x+j];
			}
		}
		if (threadIdx.x==0)
			out[i]=allsum[0];
		__syncthreads();
	}
}
void matchcostLauncher(int b,int n,int m,const float * xyz1,const float * xyz2,const float * match,float * out){
	matchcost<<<32,512>>>(b,n,m,xyz1,xyz2,match,out);
}
__global__ void matchcostgrad(int b,int n,int m,const float * __restrict__ xyz1,const float * __restrict__ xyz2,const float * __restrict__ match,float * grad2){
	__shared__ float sum_grad[256*3];
	for (int i=blockIdx.x;i<b;i+=gridDim.x){
		int kbeg=m*blockIdx.y/gridDim.y;
		int kend=m*(blockIdx.y+1)/gridDim.y;
		for (int k=kbeg;k<kend;k++){
			float x2=xyz2[(i*m+k)*3+0];
			float y2=xyz2[(i*m+k)*3+1];
			float z2=xyz2[(i*m+k)*3+2];
			float subsumx=0,subsumy=0,subsumz=0;
			for (int j=threadIdx.x;j<n;j+=blockDim.x){
				float x1=x2-xyz1[(i*n+j)*3+0];
				float y1=y2-xyz1[(i*n+j)*3+1];
				float z1=z2-xyz1[(i*n+j)*3+2];
				float d=match[i*n*m+k*n+j]/fmaxf(sqrtf(x1*x1+y1*y1+z1*z1),1e-20f);
				subsumx+=x1*d;
				subsumy+=y1*d;
				subsumz+=z1*d;
			}
			sum_grad[threadIdx.x*3+0]=subsumx;
			sum_grad[threadIdx.x*3+1]=subsumy;
			sum_grad[threadIdx.x*3+2]=subsumz;
			for (int j=1;j<blockDim.x;j<<=1){
				__syncthreads();
				int j1=threadIdx.x;
				int j2=threadIdx.x+j;
				if ((j1&j)==0 && j2<blockDim.x){
					sum_grad[j1*3+0]+=sum_grad[j2*3+0];
					sum_grad[j1*3+1]+=sum_grad[j2*3+1];
					sum_grad[j1*3+2]+=sum_grad[j2*3+2];
				}
			}
			if (threadIdx.x==0){
				grad2[(i*m+k)*3+0]=sum_grad[0];
				grad2[(i*m+k)*3+1]=sum_grad[1];
				grad2[(i*m+k)*3+2]=sum_grad[2];
			}
			__syncthreads();
		}
	}
}
void matchcostgradLauncher(int b,int n,int m,const float * xyz1,const float * xyz2,const float * match,float * grad2){
	matchcostgrad<<<dim3(32,32),256>>>(b,n,m,xyz1,xyz2,match,grad2);
}


	.file	"tmpxft_003a031d_00000000-6_approxmatch.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf
	.type	_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf, @function
_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 12(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 8(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 4(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rcx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 24(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z11approxmatchiiiPKfS0_Pf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf, .-_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf
	.globl	_Z11approxmatchiiiPKfS0_Pf
	.type	_Z11approxmatchiiiPKfS0_Pf, @function
_Z11approxmatchiiiPKfS0_Pf:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf
	.cfi_endproc
.LFE2036:
	.size	_Z11approxmatchiiiPKfS0_Pf, .-_Z11approxmatchiiiPKfS0_Pf
	.globl	_Z19approxmatchLauncheriiiPKfS0_Pf
	.type	_Z19approxmatchLauncheriiiPKfS0_Pf, @function
_Z19approxmatchLauncheriiiPKfS0_Pf:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movl	$8388609, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$9, %rdx
	movl	%esi, %ebp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movl	$134217729, %edi
	salq	$5, %rdi
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%r12d, %edx
	movl	%ebp, %esi
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z40__device_stub__Z11approxmatchiiiPKfS0_PfiiiPKfS0_Pf
.L8:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z19approxmatchLauncheriiiPKfS0_Pf, .-_Z19approxmatchLauncheriiiPKfS0_Pf
	.globl	_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
	.type	_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf, @function
_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 12(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 8(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 4(%rsp)
	leaq	48(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	192(%rsp), %rax
	movq	%r8, 24(%rsp)
	movq	%rax, 40(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%r9, 32(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9matchcostiiiPKfS0_S0_Pf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L11:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf, .-_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
	.globl	_Z9matchcostiiiPKfS0_S0_Pf
	.type	_Z9matchcostiiiPKfS0_S0_Pf, @function
_Z9matchcostiiiPKfS0_S0_Pf:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
	.cfi_endproc
.LFE2038:
	.size	_Z9matchcostiiiPKfS0_S0_Pf, .-_Z9matchcostiiiPKfS0_S0_Pf
	.globl	_Z17matchcostLauncheriiiPKfS0_S0_Pf
	.type	_Z17matchcostLauncheriiiPKfS0_S0_Pf, @function
_Z17matchcostLauncheriiiPKfS0_S0_Pf:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movl	$8388609, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$9, %rdx
	movl	%esi, %ebp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%edi, 12(%rsp)
	movl	$134217729, %edi
	movq	112(%rsp), %rbx
	salq	$5, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	%rbx, 112(%rsp)
	movl	12(%rsp), %edi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%r12d, %edx
	movl	%ebp, %esi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z40__device_stub__Z9matchcostiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
.L16:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z17matchcostLauncheriiiPKfS0_S0_Pf, .-_Z17matchcostLauncheriiiPKfS0_S0_Pf
	.globl	_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
	.type	_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf, @function
_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movl	%edi, 28(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	92(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	72(%rsp), %rcx
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 48(%rsp)
	movq	%r9, 56(%rsp)
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z13matchcostgradiiiPKfS0_S0_Pf(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L19:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf, .-_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
	.globl	_Z13matchcostgradiiiPKfS0_S0_Pf
	.type	_Z13matchcostgradiiiPKfS0_S0_Pf, @function
_Z13matchcostgradiiiPKfS0_S0_Pf:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
	.cfi_endproc
.LFE2040:
	.size	_Z13matchcostgradiiiPKfS0_S0_Pf, .-_Z13matchcostgradiiiPKfS0_S0_Pf
	.globl	_Z21matchcostgradLauncheriiiPKfS0_S0_Pf
	.type	_Z21matchcostgradLauncheriiiPKfS0_S0_Pf, @function
_Z21matchcostgradLauncheriiiPKfS0_S0_Pf:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movl	$16777217, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$8, %rdx
	movl	%esi, %ebp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%edi, 12(%rsp)
	movq	112(%rsp), %rbx
	movabsq	$137438953504, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	%rbx, 112(%rsp)
	movl	12(%rsp), %edi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%r12d, %edx
	movl	%ebp, %esi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z45__device_stub__Z13matchcostgradiiiPKfS0_S0_PfiiiPKfS0_S0_Pf
.L24:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	_Z21matchcostgradLauncheriiiPKfS0_S0_Pf, .-_Z21matchcostgradLauncheriiiPKfS0_S0_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13matchcostgradiiiPKfS0_S0_Pf"
.LC1:
	.string	"_Z9matchcostiiiPKfS0_S0_Pf"
.LC2:
	.string	"_Z11approxmatchiiiPKfS0_Pf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13matchcostgradiiiPKfS0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9matchcostiiiPKfS0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11approxmatchiiiPKfS0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2042:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//n<=4096, m<=1024
__global__ void approxmatch(int b,int n,int m,const float * __restrict__ xyz1,const float * __restrict__ xyz2,float * __restrict__ match){
	const int MaxN=4096,MaxM=1024;
	__shared__ float remainL[MaxN],remainR[MaxM],ratioR[MaxM],ratioL[MaxN];
	__shared__ int listR[MaxM],lc;
	float multiL,multiR;
	if (n>=m){
		multiL=1;
		multiR=n/m;
	}else{
		multiL=m/n;
		multiR=1;
	}
	for (int i=blockIdx.x;i<b;i+=gridDim.x){
		for (int j=threadIdx.x;j<n*m;j+=blockDim.x)
			match[i*n*m+j]=0;
		for (int j=threadIdx.x;j<n;j+=blockDim.x)
			remainL[j]=multiL;
		for (int j=threadIdx.x;j<m;j+=blockDim.x)
			remainR[j]=multiR;
		__syncthreads();
		for (int j=7;j>=-2;j--){
			float level=-powf(4.0f,j);
			if (j==-2){
				level=0;
			}
			if (threadIdx.x==0){
				lc=0;
				for (int k=0;k<m;k++)
					if (remainR[k]>0)
						listR[lc++]=k;
			}
			__syncthreads();
			int _lc=lc;
			for (int k=threadIdx.x;k<n;k+=blockDim.x){
				float suml=1e-9f;
				float x1=xyz1[(i*n+k)*3+0];
				float y1=xyz1[(i*n+k)*3+1];
				float z1=xyz1[(i*n+k)*3+2];
				//for (int l=0;l<m;l++){
				for (int _l=0;_l<_lc;_l++){
					int l=listR[_l];
					float x2=xyz2[(i*m+l)*3+0]-x1;
					float y2=xyz2[(i*m+l)*3+1]-y1;
					float z2=xyz2[(i*m+l)*3+2]-z1;
					float w=expf(level*(x2*x2+y2*y2+z2*z2))*remainR[l];
					suml+=w;
				}
				ratioL[k]=remainL[k]/suml;
			}
			__syncthreads();
			//for (int k=threadIdx.x;k<m;k+=blockDim.x){
			for (int _k=threadIdx.x;_k<lc;_k+=blockDim.x){
				int k=listR[_k];
				float sumr=0;
				float x2=xyz2[(i*m+k)*3+0];
				float y2=xyz2[(i*m+k)*3+1];
				float z2=xyz2[(i*m+k)*3+2];
				for (int l=0;l<n;l++){
					float x1=xyz1[(i*n+l)*3+0]-x2;
					float y1=xyz1[(i*n+l)*3+1]-y2;
					float z1=xyz1[(i*n+l)*3+2]-z2;
					float w=expf(level*(x1*x1+y1*y1+z1*z1))*ratioL[l];
					sumr+=w;
				}
				sumr*=remainR[k];
				float consumption=fminf(remainR[k]/(sumr+1e-9f),1.0f);
				ratioR[k]=consumption*remainR[k];
				remainR[k]=fmaxf(0.0f,remainR[k]-sumr);
			}
			__syncthreads();
			for (int k=threadIdx.x;k<n;k+=blockDim.x){
				float suml=0;
				float x1=xyz1[(i*n+k)*3+0];
				float y1=xyz1[(i*n+k)*3+1];
				float z1=xyz1[(i*n+k)*3+2];
				for (int _l=0;_l<_lc;_l++){
					int l=listR[_l];
					float x2=xyz2[(i*m+l)*3+0]-x1;
					float y2=xyz2[(i*m+l)*3+1]-y1;
					float z2=xyz2[(i*m+l)*3+2]-z1;
					float w=expf(level*(x2*x2+y2*y2+z2*z2))*ratioL[k]*ratioR[l];
					match[i*n*m+l*n+k]+=w;
					suml+=w;
				}
				remainL[k]=fmaxf(0.0f,remainL[k]-suml);
			}
			__syncthreads();
		}
	}
}
void approxmatchLauncher(int b,int n,int m,const float * xyz1,const float * xyz2,float * match){
	approxmatch<<<32,512>>>(b,n,m,xyz1,xyz2,match);
}
__global__ void matchcost(int b,int n,int m,const float * __restrict__ xyz1,const float * __restrict__ xyz2,const float * __restrict__ match,float * __restrict__ out){
	__shared__ float allsum[512];
	const int Block=256;
	__shared__ float buf[Block*3];
	for (int i=blockIdx.x;i<b;i+=gridDim.x){
		float subsum=0;
		for (int k0=0;k0<m;k0+=Block){
			int endk=min(m,k0+Block);
			for (int k=threadIdx.x;k<(endk-k0)*3;k+=blockDim.x){
				buf[k]=xyz2[i*m*3+k0*3+k];
			}
			__syncthreads();
			for (int j=threadIdx.x;j<n;j+=blockDim.x){
				float x1=xyz1[(i*n+j)*3+0];
				float y1=xyz1[(i*n+j)*3+1];
				float z1=xyz1[(i*n+j)*3+2];
				for (int k=0;k<endk-k0;k++){
					//float x2=xyz2[(i*m+k)*3+0]-x1;
					//float y2=xyz2[(i*m+k)*3+1]-y1;
					//float z2=xyz2[(i*m+k)*3+2]-z1;
					float x2=buf[k*3+0]-x1;
					float y2=buf[k*3+1]-y1;
					float z2=buf[k*3+2]-z1;
					float d=sqrtf(x2*x2+y2*y2+z2*z2);
					subsum+=match[i*n*m+(k0+k)*n+j]*d;
				}
			}
			__syncthreads();
		}
		allsum[threadIdx.x]=subsum;
		for (int j=1;j<blockDim.x;j<<=1){
			__syncthreads();
			if ((threadIdx.x&j)==0 && threadIdx.x+j<blockDim.x){
				allsum[threadIdx.x]+=allsum[threadIdx.x+j];
			}
		}
		if (threadIdx.x==0)
			out[i]=allsum[0];
		__syncthreads();
	}
}
void matchcostLauncher(int b,int n,int m,const float * xyz1,const float * xyz2,const float * match,float * out){
	matchcost<<<32,512>>>(b,n,m,xyz1,xyz2,match,out);
}
__global__ void matchcostgrad(int b,int n,int m,const float * __restrict__ xyz1,const float * __restrict__ xyz2,const float * __restrict__ match,float * grad2){
	__shared__ float sum_grad[256*3];
	for (int i=blockIdx.x;i<b;i+=gridDim.x){
		int kbeg=m*blockIdx.y/gridDim.y;
		int kend=m*(blockIdx.y+1)/gridDim.y;
		for (int k=kbeg;k<kend;k++){
			float x2=xyz2[(i*m+k)*3+0];
			float y2=xyz2[(i*m+k)*3+1];
			float z2=xyz2[(i*m+k)*3+2];
			float subsumx=0,subsumy=0,subsumz=0;
			for (int j=threadIdx.x;j<n;j+=blockDim.x){
				float x1=x2-xyz1[(i*n+j)*3+0];
				float y1=y2-xyz1[(i*n+j)*3+1];
				float z1=z2-xyz1[(i*n+j)*3+2];
				float d=match[i*n*m+k*n+j]/fmaxf(sqrtf(x1*x1+y1*y1+z1*z1),1e-20f);
				subsumx+=x1*d;
				subsumy+=y1*d;
				subsumz+=z1*d;
			}
			sum_grad[threadIdx.x*3+0]=subsumx;
			sum_grad[threadIdx.x*3+1]=subsumy;
			sum_grad[threadIdx.x*3+2]=subsumz;
			for (int j=1;j<blockDim.x;j<<=1){
				__syncthreads();
				int j1=threadIdx.x;
				int j2=threadIdx.x+j;
				if ((j1&j)==0 && j2<blockDim.x){
					sum_grad[j1*3+0]+=sum_grad[j2*3+0];
					sum_grad[j1*3+1]+=sum_grad[j2*3+1];
					sum_grad[j1*3+2]+=sum_grad[j2*3+2];
				}
			}
			if (threadIdx.x==0){
				grad2[(i*m+k)*3+0]=sum_grad[0];
				grad2[(i*m+k)*3+1]=sum_grad[1];
				grad2[(i*m+k)*3+2]=sum_grad[2];
			}
			__syncthreads();
		}
	}
}
void matchcostgradLauncher(int b,int n,int m,const float * xyz1,const float * xyz2,const float * match,float * grad2){
	matchcostgrad<<<dim3(32,32),256>>>(b,n,m,xyz1,xyz2,match,grad2);
}


	.text
	.file	"approxmatch.hip"
	.globl	_Z26__device_stub__approxmatchiiiPKfS0_Pf # -- Begin function _Z26__device_stub__approxmatchiiiPKfS0_Pf
	.type	_Z26__device_stub__approxmatchiiiPKfS0_Pf,@function
_Z26__device_stub__approxmatchiiiPKfS0_Pf: # @_Z26__device_stub__approxmatchiiiPKfS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11approxmatchiiiPKfS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__approxmatchiiiPKfS0_Pf, .Lfunc_end0-_Z26__device_stub__approxmatchiiiPKfS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z19approxmatchLauncheriiiPKfS0_Pf # -- Begin function _Z19approxmatchLauncheriiiPKfS0_Pf
	.type	_Z19approxmatchLauncheriiiPKfS0_Pf,@function
_Z19approxmatchLauncheriiiPKfS0_Pf:     # @_Z19approxmatchLauncheriiiPKfS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movl	%esi, %r12d
	movl	%edi, %r13d
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	leaq	480(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z26__device_stub__approxmatchiiiPKfS0_Pf # TAILCALL
.Lfunc_end1:
	.size	_Z19approxmatchLauncheriiiPKfS0_Pf, .Lfunc_end1-_Z19approxmatchLauncheriiiPKfS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__matchcostiiiPKfS0_S0_Pf # -- Begin function _Z24__device_stub__matchcostiiiPKfS0_S0_Pf
	.type	_Z24__device_stub__matchcostiiiPKfS0_S0_Pf,@function
_Z24__device_stub__matchcostiiiPKfS0_S0_Pf: # @_Z24__device_stub__matchcostiiiPKfS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9matchcostiiiPKfS0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__matchcostiiiPKfS0_S0_Pf, .Lfunc_end2-_Z24__device_stub__matchcostiiiPKfS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z17matchcostLauncheriiiPKfS0_S0_Pf # -- Begin function _Z17matchcostLauncheriiiPKfS0_S0_Pf
	.type	_Z17matchcostLauncheriiiPKfS0_S0_Pf,@function
_Z17matchcostLauncheriiiPKfS0_S0_Pf:    # @_Z17matchcostLauncheriiiPKfS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movl	%esi, %r12d
	movl	%edi, %r13d
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	leaq	480(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z24__device_stub__matchcostiiiPKfS0_S0_Pf # TAILCALL
.Lfunc_end3:
	.size	_Z17matchcostLauncheriiiPKfS0_S0_Pf, .Lfunc_end3-_Z17matchcostLauncheriiiPKfS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf # -- Begin function _Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf
	.type	_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf,@function
_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf: # @_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matchcostgradiiiPKfS0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf, .Lfunc_end4-_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z21matchcostgradLauncheriiiPKfS0_S0_Pf # -- Begin function _Z21matchcostgradLauncheriiiPKfS0_S0_Pf
	.type	_Z21matchcostgradLauncheriiiPKfS0_S0_Pf,@function
_Z21matchcostgradLauncheriiiPKfS0_S0_Pf: # @_Z21matchcostgradLauncheriiiPKfS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movl	%esi, %r12d
	movl	%edi, %r13d
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf # TAILCALL
.Lfunc_end5:
	.size	_Z21matchcostgradLauncheriiiPKfS0_S0_Pf, .Lfunc_end5-_Z21matchcostgradLauncheriiiPKfS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11approxmatchiiiPKfS0_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9matchcostiiiPKfS0_S0_Pf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matchcostgradiiiPKfS0_S0_Pf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11approxmatchiiiPKfS0_Pf,@object # @_Z11approxmatchiiiPKfS0_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z11approxmatchiiiPKfS0_Pf
	.p2align	3, 0x0
_Z11approxmatchiiiPKfS0_Pf:
	.quad	_Z26__device_stub__approxmatchiiiPKfS0_Pf
	.size	_Z11approxmatchiiiPKfS0_Pf, 8

	.type	_Z9matchcostiiiPKfS0_S0_Pf,@object # @_Z9matchcostiiiPKfS0_S0_Pf
	.globl	_Z9matchcostiiiPKfS0_S0_Pf
	.p2align	3, 0x0
_Z9matchcostiiiPKfS0_S0_Pf:
	.quad	_Z24__device_stub__matchcostiiiPKfS0_S0_Pf
	.size	_Z9matchcostiiiPKfS0_S0_Pf, 8

	.type	_Z13matchcostgradiiiPKfS0_S0_Pf,@object # @_Z13matchcostgradiiiPKfS0_S0_Pf
	.globl	_Z13matchcostgradiiiPKfS0_S0_Pf
	.p2align	3, 0x0
_Z13matchcostgradiiiPKfS0_S0_Pf:
	.quad	_Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf
	.size	_Z13matchcostgradiiiPKfS0_S0_Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11approxmatchiiiPKfS0_Pf"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9matchcostiiiPKfS0_S0_Pf"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13matchcostgradiiiPKfS0_S0_Pf"
	.size	.L__unnamed_3, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__approxmatchiiiPKfS0_Pf
	.addrsig_sym _Z24__device_stub__matchcostiiiPKfS0_S0_Pf
	.addrsig_sym _Z28__device_stub__matchcostgradiiiPKfS0_S0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11approxmatchiiiPKfS0_Pf
	.addrsig_sym _Z9matchcostiiiPKfS0_S0_Pf
	.addrsig_sym _Z13matchcostgradiiiPKfS0_S0_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11approxmatchiiiPKfS0_Pf ; -- Begin function _Z11approxmatchiiiPKfS0_Pf
	.globl	_Z11approxmatchiiiPKfS0_Pf
	.p2align	8
	.type	_Z11approxmatchiiiPKfS0_Pf,@function
_Z11approxmatchiiiPKfS0_Pf:             ; @_Z11approxmatchiiiPKfS0_Pf
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s9, s10
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	s_ashr_i32 s2, s10, 31
	s_ashr_i32 s6, s9, 31
	s_add_i32 s3, s10, s2
	s_add_i32 s7, s9, s6
	s_xor_b32 s3, s3, s2
	s_xor_b32 s7, s7, s6
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s5, 0, s3
	s_xor_b32 s2, s6, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s4, v1
	s_mul_i32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s5, s4, s5
	s_add_i32 s4, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s4, s7, s4
	s_mul_i32 s5, s4, s3
	s_add_i32 s6, s4, 1
	s_sub_i32 s5, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, s5, s3
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s3, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_mov_b32 s3, 1.0
	v_cvt_f32_i32_e32 v5, s2
	s_mov_b32 s2, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr5
.LBB0_3:                                ; %Flow329
	v_mov_b32_e32 v6, s3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	s_ashr_i32 s2, s9, 31
	s_ashr_i32 s6, s10, 31
	s_add_i32 s3, s9, s2
	s_add_i32 s7, s10, s6
	s_xor_b32 s3, s3, s2
	s_xor_b32 s7, s7, s6
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s5, 0, s3
	s_xor_b32 s2, s6, s2
	v_mov_b32_e32 v5, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s4, v1
	s_mul_i32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s5, s4, s5
	s_add_i32 s4, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s4, s7, s4
	s_mul_i32 s5, s4, s3
	s_add_i32 s6, s4, 1
	s_sub_i32 s5, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, s5, s3
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s3, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_i32_e32 v6, s2
.LBB0_5:
	s_cmp_ge_i32 s15, s8
	s_cbranch_scc1 .LBB0_46
; %bb.6:                                ; %.lr.ph255
	s_clause 0x2
	s_load_b32 s11, s[0:1], 0x28
	s_load_b128 s[16:19], s[0:1], 0x10
	s_load_b64 s[6:7], s[0:1], 0x20
	v_lshlrev_b32_e32 v1, 2, v0
	s_add_u32 s12, s0, 40
	s_mul_i32 s14, s10, s9
	s_addc_u32 s13, s1, 0
	s_cmp_gt_i32 s10, 0
	v_cmp_gt_i32_e64 s0, s9, v0
	v_cmp_gt_i32_e64 s2, s10, v0
	v_cmp_eq_u32_e64 s3, 0, v0
	v_mov_b32_e32 v7, 0
	v_cmp_gt_i32_e64 s1, s14, v0
	v_or_b32_e32 v8, 0x4000, v1
	v_or_b32_e32 v9, 0xa000, v1
	s_mul_i32 s4, s15, s9
	s_cselect_b32 s21, -1, 0
	s_cmp_gt_i32 s9, 0
	s_mul_i32 s20, s4, s10
	s_cselect_b32 s22, -1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s25, s11, s9
	s_mul_i32 s24, s4, 3
	s_mul_i32 s23, s25, s10
	s_mul_i32 s25, s25, 3
	s_mov_b32 s26, 0x3e76c4e1
.LBB0_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
                                        ;     Child Loop BB0_15 Depth 2
                                        ;     Child Loop BB0_17 Depth 2
                                        ;       Child Loop BB0_20 Depth 3
                                        ;       Child Loop BB0_25 Depth 3
                                        ;         Child Loop BB0_27 Depth 4
                                        ;       Child Loop BB0_32 Depth 3
                                        ;         Child Loop BB0_34 Depth 4
                                        ;       Child Loop BB0_39 Depth 3
                                        ;         Child Loop BB0_41 Depth 4
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_10
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_load_b32 s4, s[12:13], 0xc
	v_mov_b32_e32 v1, v0
	s_mov_b32 s28, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s27, s4, 0xffff
.LBB0_9:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, s20, v1
	v_add_nc_u32_e32 v1, s27, v1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e32 vcc_lo, s14, v1
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s4, s6, v2
	v_add_co_ci_u32_e64 v3, s4, s7, v3, s4
	global_store_b32 v[2:3], v7, off
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_9
.LBB0_10:                               ; %Flow326
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_13
; %bb.11:                               ; %.lr.ph217
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_load_b32 s5, s[12:13], 0xc
	v_mov_b32_e32 v1, v8
	v_mov_b32_e32 v2, v0
	s_mov_b32 s28, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s27, s5, 2
.LBB0_12:                               ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v2, s5, v2
	ds_store_b32 v1, v6
	v_add_nc_u32_e32 v1, s27, v1
	v_cmp_le_i32_e32 vcc_lo, s9, v2
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_12
.LBB0_13:                               ; %Flow324
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_16
; %bb.14:                               ; %.lr.ph219
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_load_b32 s5, s[12:13], 0xc
	v_dual_mov_b32 v1, v9 :: v_dual_mov_b32 v2, v0
	s_mov_b32 s28, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s27, s5, 2
.LBB0_15:                               ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v2, s5, v2
	ds_store_b32 v1, v5
	v_add_nc_u32_e32 v1, s27, v1
	v_cmp_le_i32_e32 vcc_lo, s10, v2
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_15
.LBB0_16:                               ; %Flow322
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_mul_i32 s27, s15, s9
	s_mul_i32 s28, s15, s10
	s_mul_i32 s29, s27, s10
	s_mov_b32 s30, 7
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_17:                               ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_20 Depth 3
                                        ;       Child Loop BB0_25 Depth 3
                                        ;         Child Loop BB0_27 Depth 4
                                        ;       Child Loop BB0_32 Depth 3
                                        ;         Child Loop BB0_34 Depth 4
                                        ;       Child Loop BB0_39 Depth 3
                                        ;         Child Loop BB0_41 Depth 4
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB0_23
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=2
	s_and_not1_b32 vcc_lo, exec_lo, s21
	ds_store_b32 v7, v7 offset:45056
	s_cbranch_vccnz .LBB0_23
; %bb.19:                               ; %.lr.ph222.preheader
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_mov_b32 s5, 0
	s_mov_b32 s31, 0xa000
	s_mov_b32 s33, 0
.LBB0_20:                               ; %.lr.ph222
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, s31
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, 0, v1
	s_cbranch_vccnz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=3
	s_add_i32 s34, s33, 1
	s_lshl_b32 s33, s33, 2
	v_dual_mov_b32 v1, s34 :: v_dual_mov_b32 v2, s5
	v_mov_b32_e32 v3, s33
	s_mov_b32 s33, s34
	ds_store_b32 v7, v1 offset:45056
	ds_store_b32 v3, v2 offset:32768
.LBB0_22:                               ;   in Loop: Header=BB0_20 Depth=3
	s_add_i32 s5, s5, 1
	s_add_i32 s31, s31, 4
	s_cmp_lg_u32 s10, s5
	s_cbranch_scc1 .LBB0_20
.LBB0_23:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_cmp_eq_u32 s30, 0
	s_cselect_b32 s4, -1, 0
	s_cmp_lg_u32 s30, -2
	v_cndmask_b32_e64 v1, 4.0, 1.0, s4
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v2, v1
	v_frexp_exp_i32_f32_e32 v1, v1
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_ldexp_f32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v1, v1
	v_add_f32_e32 v3, 1.0, v2
	v_add_f32_e32 v10, -1.0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, -1.0, v3
	v_sub_f32_e32 v2, v2, v12
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v3, v11
	v_fma_f32 v3, v11, v3, -v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v11, v2
	v_add_f32_e32 v2, v13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v2, v13
	v_dual_sub_f32 v12, v10, v2 :: v_dual_sub_f32 v3, v13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v12
	v_sub_f32_e32 v2, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v2
	v_add_f32_e32 v2, v12, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v4, v2
	v_add_f32_e32 v3, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v3, v11
	v_mul_f32_e32 v10, v3, v3
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v3, v3, -v10
	v_add_f32_e32 v11, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v3, v11
	v_add_f32_e32 v11, v10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v3, v11
	v_fmaak_f32 v12, s26, v11, 0x3e91f4c4
	v_sub_f32_e32 v10, v11, v10
	v_fma_f32 v16, v11, v3, -v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, v11, v12, 0x3ecccdef
	v_dual_sub_f32 v4, v4, v10 :: v_dual_mul_f32 v13, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v11, v12, -v13
	v_fmac_f32_e32 v10, v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v13, v10
	v_dual_sub_f32 v13, v12, v13 :: v_dual_add_f32 v14, 0x3f2aaaaa, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v13, 0xbf2aaaaa, v14
	v_fmac_f32_e32 v16, v11, v2
	v_ldexp_f32 v2, v2, 1
	v_add_f32_e32 v10, 0x31739010, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v12, v12, v13
	v_fmac_f32_e32 v16, v4, v3
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v12
	v_dual_add_f32 v11, v15, v16 :: v_dual_add_f32 v4, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v14, v4
	v_mul_f32_e32 v13, v11, v4
	v_sub_f32_e32 v14, v11, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v12
	v_fma_f32 v12, v11, v4, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v16, v14
	v_fmac_f32_e32 v12, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v4
	v_add_f32_e32 v4, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v3, v4 :: v_dual_sub_f32 v11, v4, v13
	v_mul_f32_e32 v13, 0x3f317218, v1
	v_sub_f32_e32 v3, v10, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v12, v11
	v_fma_f32 v12, 0x3f317218, v1, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v4, v3
	v_add_f32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, 0xb102e308, v1 :: v_dual_add_f32 v1, v2, v3
	v_dual_add_f32 v2, v13, v12 :: v_dual_add_f32 v3, v10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v2, v13
	v_add_f32_e32 v4, v2, v3
	v_sub_f32_e32 v10, v3, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v12, v13
	v_sub_f32_e32 v11, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v1, v10 :: v_dual_sub_f32 v14, v4, v11
	v_dual_sub_f32 v3, v3, v11 :: v_dual_add_f32 v10, v12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v14
	v_dual_add_f32 v2, v3, v2 :: v_dual_sub_f32 v3, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v10, v2
	v_sub_f32_e32 v10, v10, v3
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v4, v2
	v_dual_sub_f32 v3, v12, v10 :: v_dual_sub_f32 v4, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v1, v3
	v_cvt_f32_i32_e32 v3, s30
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v2, v11
	v_dual_mul_f32 v10, v2, v3 :: v_dual_sub_f32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v3, v2, -v10
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_fmac_f32_e32 v2, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v10, v2
	v_cndmask_b32_e32 v3, v1, v10, vcc_lo
	v_sub_f32_e32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v3
	v_sub_f32_e32 v1, v2, v1
	v_cndmask_b32_e64 v4, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v3|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v3, v4
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_mul_f32 v12, 0x3fb8aa3b, v11
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v4, v1
	v_fma_f32 v13, 0x3fb8aa3b, v11, -v12
	v_rndne_f32_e32 v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, 0x32a5705f, v11 :: v_dual_sub_f32 v12, v12, v14
	v_cvt_i32_f32_e32 v10, v14
	v_add_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v12, v12
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v12, v10
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_fma_f32 v1, v2, v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v7 offset:45056
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, 0, -|v1|, s4
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s31, v3
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_30
; %bb.24:                               ; %.lr.ph230
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_load_b32 s34, s[12:13], 0xc
	v_mov_b32_e32 v4, v0
	s_cmp_gt_i32 s31, 0
	s_mov_b32 s33, 0
	s_cselect_b32 s5, -1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s34, s34, 0xffff
.LBB0_25:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_27 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_28
; %bb.26:                               ; %.lr.ph226.preheader
                                        ;   in Loop: Header=BB0_25 Depth=3
	v_add_nc_u32_e32 v1, s27, v4
	v_mov_b32_e32 v11, 0x3089705f
	s_mov_b32 s35, 0x8000
	s_mov_b32 s36, s31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s16, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v2, vcc_lo
	global_load_b96 v[1:3], v[1:2], off
.LBB0_27:                               ; %.lr.ph226
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ;       Parent Loop BB0_25 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v12, s35
	ds_load_b32 v12, v12
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s37, v12
	v_lshlrev_b32_e32 v12, 2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s37, s37, s28
	s_mul_i32 s38, s37, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s39, s38, 31
	s_lshl_b64 s[38:39], s[38:39], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s18, s38
	s_addc_u32 s39, s19, s39
	s_clause 0x1
	s_load_b64 s[40:41], s[38:39], 0x0
	s_load_b32 s37, s[38:39], 0x8
	s_add_i32 s36, s36, -1
	s_add_i32 s35, s35, 4
	s_cmp_eq_u32 s36, 0
	ds_load_b32 v12, v12 offset:40960
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_sub_f32 v13, s41, v2 :: v_dual_sub_f32 v14, s40, v1
	v_sub_f32_e32 v15, s37, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v13, v13
	v_fmac_f32_e32 v13, v14, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v15
	v_mul_f32_e32 v13, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fb8aa3b, v13
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	v_fma_f32 v15, 0x3fb8aa3b, v13, -v14
	v_rndne_f32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v15, 0x32a5705f, v13 :: v_dual_sub_f32 v14, v14, v16
	v_add_f32_e32 v14, v14, v15
	v_cvt_i32_f32_e32 v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v14, v14
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v14, v14, v15
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, 0x7f800000, v14, vcc_lo
	v_fmac_f32_e32 v11, v12, v13
	s_cbranch_scc0 .LBB0_27
	s_branch .LBB0_29
.LBB0_28:                               ;   in Loop: Header=BB0_25 Depth=3
	v_mov_b32_e32 v11, 0x3089705f
.LBB0_29:                               ; %._crit_edge227
                                        ;   in Loop: Header=BB0_25 Depth=3
	v_lshlrev_b32_e32 v1, 2, v4
	v_add_nc_u32_e32 v4, s34, v4
	ds_load_b32 v2, v1 offset:16384
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v3, null, v11, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v3, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	v_div_scale_f32 v13, vcc_lo, v2, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v13, v12
	v_fma_f32 v15, -v3, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v15, v12
	v_fma_f32 v3, -v3, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v12, v14
	v_cmp_le_i32_e32 vcc_lo, s9, v4
	v_div_fixup_f32 v2, v3, v11, v2
	s_or_b32 s33, vcc_lo, s33
	ds_store_b32 v1, v2
	s_and_not1_b32 exec_lo, exec_lo, s33
	s_cbranch_execnz .LBB0_25
.LBB0_30:                               ; %Flow318
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v4, v7 offset:45056
	s_mov_b32 s33, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e64 v0, v4
	s_cbranch_execz .LBB0_37
; %bb.31:                               ; %.lr.ph240
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_load_b32 s4, s[12:13], 0xc
	v_mov_b32_e32 v11, v0
	s_mov_b32 s35, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s34, s4, 0xffff
.LBB0_32:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_34 Depth 4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 2, v11
	s_and_not1_b32 vcc_lo, exec_lo, s22
	ds_load_b32 v13, v1 offset:32768
	s_cbranch_vccnz .LBB0_35
; %bb.33:                               ; %.lr.ph235.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v1, s28, v13
	s_mov_b32 s36, 0
	s_mov_b32 s4, s24
	s_mov_b32 s37, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s18, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v2, vcc_lo
	global_load_b96 v[1:3], v[1:2], off
.LBB0_34:                               ; %.lr.ph235
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[38:39], s[4:5], 2
	s_add_u32 s38, s16, s38
	s_addc_u32 s39, s17, s39
	s_add_i32 s37, s37, -1
	s_clause 0x1
	s_load_b64 s[40:41], s[38:39], 0x0
	s_load_b32 s5, s[38:39], 0x8
	s_add_i32 s4, s4, 3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_sub_f32 v14, s41, v2 :: v_dual_sub_f32 v15, s40, v1
	v_sub_f32_e32 v16, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v14, v14
	v_fmac_f32_e32 v14, v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v16, v16
	v_mul_f32_e32 v14, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, 0x3fb8aa3b, v14
	v_fma_f32 v16, 0x3fb8aa3b, v14, -v15
	v_rndne_f32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v16, 0x32a5705f, v14 :: v_dual_sub_f32 v15, v15, v17
	v_cvt_i32_f32_e32 v17, v17
	v_dual_add_f32 v15, v15, v16 :: v_dual_mov_b32 v16, s36
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	s_add_i32 s36, s36, 4
	s_cmp_eq_u32 s37, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v15, v15
	ds_load_b32 v16, v16
	v_ldexp_f32 v15, v15, v17
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, 0x7f800000, v15, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v12, v16, v14
	s_cbranch_scc0 .LBB0_34
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v12, 0
.LBB0_36:                               ; %._crit_edge236
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v1, 2, v13
	v_add_nc_u32_e32 v11, s34, v11
	ds_load_b32 v2, v1 offset:40960
	s_waitcnt lgkmcnt(0)
	v_fmaak_f32 v3, v12, v2, 0x3089705f
	v_fma_f32 v12, -v12, v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v13, null, v3, v3, v2
	v_div_scale_f32 v16, vcc_lo, v2, v3, v2
	v_rcp_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v13, v14, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v15, v14
	v_mul_f32_e32 v15, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v13, v15, v16
	v_fmac_f32_e32 v15, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v13, v15, v16
	v_div_fmas_f32 v13, v13, v14, v15
	v_cmp_ge_i32_e32 vcc_lo, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v13, v3, v2
	s_or_b32 s35, vcc_lo, s35
	v_min_f32_e32 v3, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v2, v2, v3 :: v_dual_max_f32 v3, 0, v12
	ds_store_2addr_stride64_b32 v1, v2, v3 offset0:144 offset1:160
	s_and_not1_b32 exec_lo, exec_lo, s35
	s_cbranch_execnz .LBB0_32
.LBB0_37:                               ; %Flow314
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s33
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_44
; %bb.38:                               ; %.lr.ph250
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_load_b32 s34, s[12:13], 0xc
	v_mov_b32_e32 v11, v0
	s_cmp_gt_i32 s31, 0
	s_mov_b32 s5, 0
	s_cselect_b32 s33, -1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s34, s34, 0xffff
.LBB0_39:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_41 Depth 4
	v_lshlrev_b32_e32 v12, 2, v11
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB0_42
; %bb.40:                               ; %.lr.ph245
                                        ;   in Loop: Header=BB0_39 Depth=3
	v_add_nc_u32_e32 v1, s27, v11
	ds_load_b32 v14, v12
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v4, s29, v11
	s_mov_b32 s35, 0x8000
	v_lshl_add_u32 v1, v1, 1, v1
	s_mov_b32 s36, s31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v2, vcc_lo
	global_load_b96 v[1:3], v[1:2], off
.LBB0_41:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ;       Parent Loop BB0_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v15, s35
	ds_load_b32 v17, v15
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[15:16], null, v17, s9, v[4:5]
	v_readfirstlane_b32 s37, v17
	v_lshlrev_b32_e32 v17, 2, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_add_i32 s37, s37, s28
	v_ashrrev_i32_e32 v16, 31, v15
	s_mul_i32 s38, s37, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s39, s38, 31
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_lshl_b64 s[38:39], s[38:39], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_add_u32 s38, s18, s38
	s_addc_u32 s39, s19, s39
	s_add_i32 s36, s36, -1
	v_add_co_u32 v15, vcc_lo, s6, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
	s_add_i32 s35, s35, 4
	s_cmp_eq_u32 s36, 0
	global_load_b32 v18, v[15:16], off
	s_clause 0x1
	s_load_b64 s[40:41], s[38:39], 0x0
	s_load_b32 s37, s[38:39], 0x8
	ds_load_b32 v17, v17 offset:36864
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_dual_sub_f32 v20, s40, v1 :: v_dual_sub_f32 v19, s41, v2
	v_sub_f32_e32 v21, s37, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v19, v19
	v_fmac_f32_e32 v19, v20, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v21, v21
	v_mul_f32_e32 v19, v10, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fb8aa3b, v19
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v19
	v_fma_f32 v21, 0x3fb8aa3b, v19, -v20
	v_rndne_f32_e32 v22, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v21, 0x32a5705f, v19 :: v_dual_sub_f32 v20, v20, v22
	v_add_f32_e32 v20, v20, v21
	v_cvt_i32_f32_e32 v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v20, v20
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v20, v20, v21
	v_cndmask_b32_e32 v20, 0, v20, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v19, 0x7f800000, v20, vcc_lo
	v_mul_f32_e32 v19, v14, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v13, v17, v19
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v18, v17, v19
	global_store_b32 v[15:16], v18, off
	s_cbranch_scc0 .LBB0_41
	s_branch .LBB0_43
.LBB0_42:                               ;   in Loop: Header=BB0_39 Depth=3
	v_mov_b32_e32 v13, 0
.LBB0_43:                               ; %._crit_edge246
                                        ;   in Loop: Header=BB0_39 Depth=3
	ds_load_b32 v1, v12 offset:16384
	v_add_nc_u32_e32 v11, s34, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s9, v11
	s_or_b32 s5, vcc_lo, s5
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v1, v1, v13
	v_max_f32_e32 v1, 0, v1
	ds_store_b32 v12, v1 offset:16384
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_39
.LBB0_44:                               ; %Flow310
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s4, s30, -1
	s_cmp_lt_i32 s30, -1
	s_mov_b32 s30, s4
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_17
; %bb.45:                               ;   in Loop: Header=BB0_7 Depth=1
	s_add_i32 s15, s11, s15
	s_add_i32 s20, s20, s23
	s_add_i32 s24, s24, s25
	s_cmp_ge_i32 s15, s8
	s_cbranch_scc0 .LBB0_7
.LBB0_46:                               ; %._crit_edge256
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11approxmatchiiiPKfS0_Pf
		.amdhsa_group_segment_fixed_size 45060
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 42
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11approxmatchiiiPKfS0_Pf, .Lfunc_end0-_Z11approxmatchiiiPKfS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3600
; NumSgprs: 44
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 45060 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 44
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9matchcostiiiPKfS0_S0_Pf ; -- Begin function _Z9matchcostiiiPKfS0_S0_Pf
	.globl	_Z9matchcostiiiPKfS0_S0_Pf
	.p2align	8
	.type	_Z9matchcostiiiPKfS0_S0_Pf,@function
_Z9matchcostiiiPKfS0_S0_Pf:             ; @_Z9matchcostiiiPKfS0_S0_Pf
; %bb.0:
	s_mov_b32 s16, s15
	s_load_b128 s[12:15], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s16, s12
	s_cbranch_scc1 .LBB1_23
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x30
	s_load_b256 s[4:11], s[0:1], 0x10
	v_lshlrev_b32_e32 v7, 2, v0
	s_mul_i32 s17, s16, s14
	s_cmp_gt_i32 s14, 0
	v_mad_u64_u32 v[4:5], null, s17, s13, v[0:1]
	s_cselect_b32 s18, -1, 0
	v_cmp_gt_i32_e64 s0, s13, v0
	v_cmp_eq_u32_e64 s1, 0, v0
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, 0xc00, v7
	s_mul_i32 s15, s17, 3
	s_waitcnt lgkmcnt(0)
	s_and_b32 s19, s2, 0xffff
	s_mul_i32 s23, s3, s14
	s_cmp_gt_u32 s19, 1
	s_mul_i32 s20, s23, 3
	s_cselect_b32 s21, -1, 0
	s_lshl_b32 s22, s19, 2
	s_mul_i32 s23, s23, s13
	s_lshl_b32 s24, s13, 8
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;       Child Loop BB1_9 Depth 3
                                        ;         Child Loop BB1_11 Depth 4
                                        ;     Child Loop BB1_17 Depth 2
	v_mov_b32_e32 v10, 0
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_15
; %bb.3:                                ; %.lr.ph94
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, v4
	s_mul_i32 s17, s16, s13
	s_mov_b32 s26, 0
	s_mov_b32 s25, s15
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;       Child Loop BB1_9 Depth 3
                                        ;         Child Loop BB1_11 Depth 4
	s_mov_b32 s2, s26
	s_addk_i32 s26, 0x100
	s_mov_b32 s28, exec_lo
	s_min_i32 s27, s14, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s27, s27, s2
	s_mul_i32 s2, s27, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB1_7
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v1, v7 :: v_dual_mov_b32 v2, v0
	s_mov_b32 s29, 0
.LBB1_6:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s25, v2
	v_add_nc_u32_e32 v2, s19, v2
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s2, v2
	global_load_b32 v3, v[5:6], off
	s_or_b32 s29, vcc_lo, s29
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v3
	v_add_nc_u32_e32 v1, s22, v1
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB1_6
.LBB1_7:                                ; %Flow133
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s28, s0
	s_cbranch_execz .LBB1_14
; %bb.8:                                ; %.lr.ph89
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v12, v11 :: v_dual_mov_b32 v13, v0
	s_cmp_gt_i32 s27, 0
	s_mov_b32 s30, 0
	s_cselect_b32 s29, -1, 0
.LBB1_9:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_11 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccnz .LBB1_12
; %bb.10:                               ; %.lr.ph83
                                        ;   in Loop: Header=BB1_9 Depth=3
	v_add_nc_u32_e32 v1, s17, v13
	v_mov_b32_e32 v5, v12
	s_mov_b32 s31, 0
	s_mov_b32 s33, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b96 v[1:3], v[1:2], off
.LBB1_11:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_9 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_ashrrev_i32_e32 v6, 31, v5
	v_mov_b32_e32 v16, s31
	s_add_i32 s33, s33, 1
	s_add_i32 s31, s31, 12
	s_cmp_ge_i32 s33, s27
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	v_add_nc_u32_e32 v5, s13, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
	global_load_b32 v6, v[14:15], off
	ds_load_2addr_b32 v[14:15], v16 offset1:1
	ds_load_b32 v16, v16 offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_dual_sub_f32 v15, v15, v2 :: v_dual_sub_f32 v14, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v15, v15
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v16, v16, v3 :: v_dual_fmac_f32 v15, v14, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v16
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v15
	v_mul_f32_e32 v14, 0x4f800000, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, v15, v14, vcc_lo
	v_sqrt_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, 1, v15
	v_add_nc_u32_e32 v16, -1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v17, v15, v14
	v_fma_f32 v18, -v16, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v18
	v_cndmask_b32_e64 v15, v15, v16, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v19
	v_cndmask_b32_e64 v15, v15, v17, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, 0x37800000, v15
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v14, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, v15, v14, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v10, v6, v14
	s_cbranch_scc0 .LBB1_11
.LBB1_12:                               ; %._crit_edge84
                                        ;   in Loop: Header=BB1_9 Depth=3
	v_add_nc_u32_e32 v13, s19, v13
	v_add_nc_u32_e32 v12, s19, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v13
	s_or_b32 s30, vcc_lo, s30
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB1_9
; %bb.13:                               ; %Flow130
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
.LBB1_14:                               ; %Flow131
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s28
	v_add_nc_u32_e32 v11, s24, v11
	s_addk_i32 s25, 0x300
	s_cmp_ge_i32 s26, s14
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_4
.LBB1_15:                               ; %._crit_edge95
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s21
	ds_store_b32 v8, v10
	s_cbranch_vccnz .LBB1_20
; %bb.16:                               ; %.lr.ph98.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s17, 1
.LBB1_17:                               ; %.lr.ph98
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_and_b32_e32 v1, s17, v0
	v_add_nc_u32_e32 v2, s17, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_cmp_gt_u32_e64 s2, s19, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, vcc_lo, s2
	s_and_saveexec_b32 s2, s25
	s_cbranch_execz .LBB1_19
; %bb.18:                               ;   in Loop: Header=BB1_17 Depth=2
	v_lshl_add_u32 v1, s17, 2, v8
	ds_load_b32 v1, v1
	ds_load_b32 v2, v8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v8, v1
.LBB1_19:                               ;   in Loop: Header=BB1_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_lshl_b32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s17, s19
	s_cbranch_scc0 .LBB1_17
.LBB1_20:                               ; %._crit_edge99
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_22
; %bb.21:                               ;   in Loop: Header=BB1_2 Depth=1
	ds_load_b32 v1, v9 offset:3072
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[26:27], s[16:17], 2
	s_add_u32 s26, s10, s26
	s_addc_u32 s27, s11, s27
	s_waitcnt lgkmcnt(0)
	global_store_b32 v9, v1, s[26:27]
.LBB1_22:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v4, s23, v4
	s_add_i32 s16, s3, s16
	s_add_i32 s15, s15, s20
	s_cmp_ge_i32 s16, s12
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_23:                               ; %._crit_edge102
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9matchcostiiiPKfS0_S0_Pf
		.amdhsa_group_segment_fixed_size 5120
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9matchcostiiiPKfS0_S0_Pf, .Lfunc_end1-_Z9matchcostiiiPKfS0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1008
; NumSgprs: 36
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 5120 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13matchcostgradiiiPKfS0_S0_Pf ; -- Begin function _Z13matchcostgradiiiPKfS0_S0_Pf
	.globl	_Z13matchcostgradiiiPKfS0_S0_Pf
	.p2align	8
	.type	_Z13matchcostgradiiiPKfS0_S0_Pf,@function
_Z13matchcostgradiiiPKfS0_S0_Pf:        ; @_Z13matchcostgradiiiPKfS0_S0_Pf
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc1 .LBB2_17
; %bb.1:                                ; %.lr.ph119
	s_load_b64 s[12:13], s[0:1], 0x30
	v_mul_u32_u24_e32 v4, 3, v0
	s_add_u32 s20, s0, 48
	s_addc_u32 s21, s1, 0
	s_mul_i32 s15, s15, s18
	s_load_b256 s[4:11], s[0:1], 0x10
	v_cmp_gt_i32_e64 s0, s17, v0
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v4, 2, v4
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s13
	s_sub_i32 s3, 0, s13
	s_mul_i32 s27, s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s26, s27, s18
	v_rcp_iflag_f32_e32 v1, v1
	s_mul_i32 s27, s27, 3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s2, v1
	v_mad_u64_u32 v[1:2], null, s14, s17, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s2
	s_mul_hi_u32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v5, v1, 1, v1
	s_add_i32 s2, s2, s3
	s_mul_hi_u32 s3, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s19, s3, s13
	s_sub_i32 s1, s15, s19
	s_add_i32 s19, s3, 1
	s_sub_i32 s22, s1, s13
	s_cmp_ge_u32 s1, s13
	s_cselect_b32 s3, s19, s3
	s_cselect_b32 s1, s22, s1
	s_add_i32 s19, s3, 1
	s_cmp_ge_u32 s1, s13
	v_cmp_eq_u32_e64 s1, 0, v0
	s_cselect_b32 s3, s19, s3
	s_add_i32 s15, s15, s18
	s_mul_i32 s19, s14, s18
	s_mul_hi_u32 s2, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s22, s2, s13
	s_sub_i32 s15, s15, s22
	s_add_i32 s22, s2, 1
	s_sub_i32 s23, s15, s13
	s_cmp_ge_u32 s15, s13
	s_cselect_b32 s2, s22, s2
	s_cselect_b32 s15, s23, s15
	s_add_i32 s22, s2, 1
	s_cmp_ge_u32 s15, s13
	s_cselect_b32 s13, s22, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, s13
	s_cselect_b32 s15, -1, 0
	s_add_i32 s2, s3, s19
	s_mul_i32 s19, s17, s2
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
                                        ;       Child Loop BB2_6 Depth 3
                                        ;       Child Loop BB2_10 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccnz .LBB2_16
; %bb.3:                                ; %.lr.ph115
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_load_b32 s2, s[20:21], 0xc
	s_mul_i32 s29, s14, s18
	s_mov_b32 s33, s19
	s_mov_b32 s34, s3
	s_waitcnt lgkmcnt(0)
	s_and_b32 s28, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s28, 1
	s_mul_i32 s31, s28, 3
	s_cselect_b32 s30, -1, 0
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_6 Depth 3
                                        ;       Child Loop BB2_10 Depth 3
	s_add_i32 s2, s34, s29
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
	v_mov_b32_e32 v8, 0
	s_mul_i32 s22, s2, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s23, s22, 31
	s_and_saveexec_b32 s35, s0
	s_cbranch_execz .LBB2_8
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_lshl_b64 s[24:25], s[22:23], 2
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v1, v5
	s_add_u32 s36, s6, s24
	s_addc_u32 s37, s7, s25
	s_clause 0x1
	s_load_b64 s[24:25], s[36:37], 0x0
	s_load_b32 s36, s[36:37], 0x8
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	v_mov_b32_e32 v9, v0
	s_mov_b32 s37, 0
.LBB2_6:                                ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[1:2]
	v_add_nc_u32_e32 v1, s31, v1
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	global_load_b96 v[10:12], v[10:11], off
	v_add_nc_u32_e32 v13, s33, v9
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_sub_f32 v10, s24, v10 :: v_dual_add_nc_u32 v9, s28, v9
	v_ashrrev_i32_e32 v14, 31, v13
	v_dual_sub_f32 v11, s25, v11 :: v_dual_sub_f32 v12, s36, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
	global_load_b32 v2, v[13:14], off
	v_mul_f32_e32 v13, v11, v11
	v_fmac_f32_e32 v13, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v12, v12
	v_mul_f32_e32 v14, 0x4f800000, v13
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	v_sqrt_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v15, -1, v14
	v_add_nc_u32_e32 v16, 1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v15, v14, v13
	v_fma_f32 v18, -v16, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v17
	v_cndmask_b32_e64 v14, v14, v15, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v18
	v_cndmask_b32_e64 v14, v14, v16, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, 0x37800000, v14
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v14, v13, vcc_lo
	v_max_f32_e32 v13, 0x1e3ce508, v13
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v14, null, v13, v13, v2
	v_div_scale_f32 v17, vcc_lo, v2, v13, v2
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v15
	v_mul_f32_e32 v16, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v14, v16, v17
	v_fmac_f32_e32 v16, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v14, v16, v17
	v_div_fmas_f32 v14, v14, v15, v16
	v_cmp_le_i32_e32 vcc_lo, s17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v14, v13, v2
	s_or_b32 s37, vcc_lo, s37
	v_fmac_f32_e32 v6, v10, v2
	v_fmac_f32_e32 v7, v11, v2
	v_fmac_f32_e32 v8, v12, v2
	s_and_not1_b32 exec_lo, exec_lo, s37
	s_cbranch_execnz .LBB2_6
; %bb.7:                                ; %Flow154
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s37
.LBB2_8:                                ; %Flow155
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_and_not1_b32 vcc_lo, exec_lo, s30
	ds_store_2addr_b32 v4, v6, v7 offset1:1
	ds_store_b32 v4, v8 offset:8
	s_cbranch_vccnz .LBB2_13
; %bb.9:                                ; %.lr.ph111.preheader
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_mov_b32 s24, 1
.LBB2_10:                               ; %.lr.ph111
                                        ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_and_b32_e32 v2, s24, v0
	v_add_nc_u32_e32 v1, s24, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cmp_gt_u32_e64 s2, s28, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, vcc_lo, s2
	s_and_saveexec_b32 s2, s25
	s_cbranch_execz .LBB2_12
; %bb.11:                               ;   in Loop: Header=BB2_10 Depth=3
	v_mul_lo_u32 v6, v1, 12
	ds_load_2addr_b32 v[1:2], v4 offset1:1
	ds_load_b32 v7, v6
	ds_load_b32 v8, v4 offset:8
	s_waitcnt lgkmcnt(1)
	v_add_f32_e32 v1, v7, v1
	ds_store_b32 v4, v1
	ds_load_b32 v1, v6 offset:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v4, v1 offset:4
	ds_load_b32 v1, v6 offset:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v8
	ds_store_b32 v4, v1 offset:8
.LBB2_12:                               ;   in Loop: Header=BB2_10 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	s_lshl_b32 s24, s24, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s24, s28
	s_cbranch_scc0 .LBB2_10
.LBB2_13:                               ; %._crit_edge112
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB2_15
; %bb.14:                               ;   in Loop: Header=BB2_4 Depth=2
	ds_load_b96 v[6:8], v3
	s_lshl_b64 s[22:23], s[22:23], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s10, s22
	s_addc_u32 s23, s11, s23
	s_waitcnt lgkmcnt(0)
	global_store_b96 v3, v[6:8], s[22:23]
.LBB2_15:                               ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s34, s34, 1
	s_add_i32 s33, s33, s17
	s_cmp_ge_i32 s34, s13
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_4
.LBB2_16:                               ; %._crit_edge116
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v5, s27, v5
	s_add_i32 s14, s12, s14
	s_add_i32 s19, s19, s26
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc0 .LBB2_2
.LBB2_17:                               ; %._crit_edge120
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matchcostgradiiiPKfS0_S0_Pf
		.amdhsa_group_segment_fixed_size 3072
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 38
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13matchcostgradiiiPKfS0_S0_Pf, .Lfunc_end2-_Z13matchcostgradiiiPKfS0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1156
; NumSgprs: 40
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3072 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 40
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
