#include "includes.h"
__global__ void MakeSplits_Large(int baseAggregateIdx, int* splitting, int* aggregation, int* aggMapAdjIndices, int* aggMapAdjacency, int* adjIndices, int* adjacency) {
int currentAgg = splitting[blockIdx.x];
int aggBegin = aggMapAdjIndices[currentAgg];
int aggSize = aggMapAdjIndices[currentAgg + 1] - aggBegin;
int newAgg = baseAggregateIdx + blockIdx.x;

__shared__ int nodeIds[256];
__shared__ int scratchA[256];
__shared__ int scratchB[256];
__shared__ int rootA;
__shared__ int rootB;
__shared__ int aCount, bCount;
__shared__ bool incomplete;
incomplete = true;
aCount = 1;
bCount = 1;

// Load in the node Id's from the aggregate map to the shared array:
if (threadIdx.x < aggSize)
nodeIds[threadIdx.x] = aggMapAdjacency[aggBegin + threadIdx.x];
__syncthreads();

// Each thread loads it's neighbors list into registers, translating into
// aggregate offsets.
int neighbors[40];
int nextNeighbor = 0;
int nodeId = -1;
if (threadIdx.x < aggSize)
{
nodeId = nodeIds[threadIdx.x];
int start = adjIndices[nodeId];
int end = adjIndices[nodeId + 1];
for (int i = start; i < end; i++)
{
int neighborId = adjacency[i];
int a = 0, b = aggSize - 1, midpoint;
while (a < b)
{
midpoint = a + ((b - a) / 2);
if (nodeIds[midpoint] < neighborId)
a = midpoint + 1;
else
b = midpoint;
}

if (nodeIds[a] == neighborId)
{
neighbors[nextNeighbor++] = a;
}
}
}
__syncthreads();

// Find the farthest node from the lowest indexed node (first root point)
// Start by marking the first node and threads without a node as seen
// Mark initial distances in scratch vector
if (threadIdx.x < aggSize)
scratchA[threadIdx.x] = threadIdx.x == 0 ? 0 : -1;
int myDist = threadIdx.x == 0 ? 0 : -1;
bool swapped = false;
incomplete = true;
__syncthreads();

while (incomplete)
{
// Set the incomplete flag to false
incomplete = false;
__syncthreads();

// Check if a neighbor has a positive distance
if (threadIdx.x < aggSize && myDist == -1)
{
for (int i = 0; i < nextNeighbor; i++)
{
int neighborDist = scratchA[neighbors[i]];
if (neighborDist > -1)
myDist = neighborDist + 1;
}
}
__syncthreads();

if (threadIdx.x < aggSize && myDist > 0 && !swapped)
{
swapped = true;
scratchA[threadIdx.x] = myDist;
rootA = threadIdx.x;
incomplete = true;
}
__syncthreads();
}

// Find the farthest node from the first root point (second root point)
// Start by marking the first node and threads without a node as seen
// Mark initial distances in scratch vector
if (threadIdx.x < aggSize)
scratchA[threadIdx.x] = threadIdx.x == rootA ? 0 : -1;
myDist = threadIdx.x == rootA ? 0 : -1;
swapped = false;
incomplete = true;
__syncthreads();

while (incomplete)
{
// Set the incomplete flag to false
incomplete = false;
__syncthreads();

// Check if a neighbor has a positive distance
if (threadIdx.x < aggSize && myDist == -1)
{
for (int i = 0; i < nextNeighbor; i++)
{
int neighborDist = scratchA[neighbors[i]];
if (neighborDist > -1)
{
myDist = neighborDist + 1;
}
}
}
__syncthreads();

if (threadIdx.x < aggSize && myDist > 0 && !swapped)
{
swapped = true;
scratchA[threadIdx.x] = myDist;
rootB = threadIdx.x;
incomplete = true;
}
__syncthreads();
}

// Setting an assigned aggregate label (In ScratchA) for every node with the node at
// rootA being assigned the current aggregate ID and the node at rootB
// being assigned the newAgg ID and set initial distances from a root node
// (In ScratchB) for each node, -1 for unknown and 0 for the roots
int myAggregate = -1;
if (threadIdx.x == rootA)
myAggregate = currentAgg;
if (threadIdx.x == rootB)
myAggregate = newAgg;
if (threadIdx.x < aggSize)
{
scratchA[threadIdx.x] = myAggregate;
scratchB[threadIdx.x] = myAggregate > -1 ? 0 : -1;
}
incomplete = true;
__syncthreads();

// Assign nodes to each aggregate until no unassigned nodes remain.
while (incomplete)
{
// Set the incomplete flag to false
incomplete = false;
__syncthreads();

if (threadIdx.x < aggSize && myAggregate == -1)
{
for (int i = 0; i < nextNeighbor; i++)
{
int neighborAgg = scratchA[neighbors[i]];
if (neighborAgg > -1)
{
myDist = scratchB[neighbors[i]] + 1;
myAggregate = neighborAgg;
}
}
if (myAggregate == -1)
incomplete = true;
if (myAggregate == newAgg)
atomicAdd((unsigned int*)&bCount, (unsigned)1);
if (myAggregate == currentAgg)
atomicAdd((unsigned int*)&aCount, (unsigned)1);
}
__syncthreads();

if (threadIdx.x < aggSize)
{
scratchA[threadIdx.x] = myAggregate;
scratchB[threadIdx.x] = myDist;
}
__syncthreads();
}

// If the split was uneven try to repair it
int sizeDifference = aCount > bCount ? aCount - bCount : bCount - aCount;
bool moveToA = aCount < bCount;
__shared__ int moved;
moved = 0;
int toMove = sizeDifference / 2;
incomplete = true;
__syncthreads();

while (incomplete && moved < toMove)
{
incomplete = false;
__syncthreads();
bool swapping = false;
int newDist = INT_MAX;
if (threadIdx.x < aggSize)
{
bool canSwap = moveToA ? myAggregate == newAgg : myAggregate == currentAgg;
bool borderNode = false;

// Check if this node has no same aggregate neighbors of higher distance
// and on a border
for (int i = 0; i < nextNeighbor; i++)
{
int neighborAgg = scratchA[neighbors[i]];
int neighborDist = scratchB[neighbors[i]];
if (neighborAgg == myAggregate && neighborDist > myDist)
canSwap = false;

if (neighborAgg != myAggregate)
{
if (neighborDist + 1 < newDist)
newDist = neighborDist + 1;
borderNode = true;
}
}

// If a node could swap see if it will
if (borderNode && canSwap && atomicAdd((unsigned int*)&moved, 1) < toMove)
{
swapping = true;
}
}
__syncthreads();
if (swapping)
{
int a = moveToA ? 1 : -1;
atomicAdd((unsigned int*)&bCount, -a);
atomicAdd((unsigned int*)&aCount, a);
scratchA[threadIdx.x] = moveToA ? currentAgg : newAgg;
scratchB[threadIdx.x] = newDist;
incomplete = true;
}
__syncthreads();
}

// Write out the values to the aggregation array
if (threadIdx.x < aggSize)
{
aggregation[nodeId] = scratchA[threadIdx.x];
}

}
	.file	"tmpxft_00325fed_00000000-6_MakeSplits_Large.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z16MakeSplits_LargeiPiS_S_S_S_S_iPiS_S_S_S_S_
	.type	_Z47__device_stub__Z16MakeSplits_LargeiPiS_S_S_S_S_iPiS_S_S_S_S_, @function
_Z47__device_stub__Z16MakeSplits_LargeiPiS_S_S_S_S_iPiS_S_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z16MakeSplits_LargeiPiS_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z16MakeSplits_LargeiPiS_S_S_S_S_iPiS_S_S_S_S_, .-_Z47__device_stub__Z16MakeSplits_LargeiPiS_S_S_S_S_iPiS_S_S_S_S_
	.globl	_Z16MakeSplits_LargeiPiS_S_S_S_S_
	.type	_Z16MakeSplits_LargeiPiS_S_S_S_S_, @function
_Z16MakeSplits_LargeiPiS_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z16MakeSplits_LargeiPiS_S_S_S_S_iPiS_S_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z16MakeSplits_LargeiPiS_S_S_S_S_, .-_Z16MakeSplits_LargeiPiS_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16MakeSplits_LargeiPiS_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16MakeSplits_LargeiPiS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MakeSplits_Large(int baseAggregateIdx, int* splitting, int* aggregation, int* aggMapAdjIndices, int* aggMapAdjacency, int* adjIndices, int* adjacency) {
int currentAgg = splitting[blockIdx.x];
int aggBegin = aggMapAdjIndices[currentAgg];
int aggSize = aggMapAdjIndices[currentAgg + 1] - aggBegin;
int newAgg = baseAggregateIdx + blockIdx.x;

__shared__ int nodeIds[256];
__shared__ int scratchA[256];
__shared__ int scratchB[256];
__shared__ int rootA;
__shared__ int rootB;
__shared__ int aCount, bCount;
__shared__ bool incomplete;
incomplete = true;
aCount = 1;
bCount = 1;

// Load in the node Id's from the aggregate map to the shared array:
if (threadIdx.x < aggSize)
nodeIds[threadIdx.x] = aggMapAdjacency[aggBegin + threadIdx.x];
__syncthreads();

// Each thread loads it's neighbors list into registers, translating into
// aggregate offsets.
int neighbors[40];
int nextNeighbor = 0;
int nodeId = -1;
if (threadIdx.x < aggSize)
{
nodeId = nodeIds[threadIdx.x];
int start = adjIndices[nodeId];
int end = adjIndices[nodeId + 1];
for (int i = start; i < end; i++)
{
int neighborId = adjacency[i];
int a = 0, b = aggSize - 1, midpoint;
while (a < b)
{
midpoint = a + ((b - a) / 2);
if (nodeIds[midpoint] < neighborId)
a = midpoint + 1;
else
b = midpoint;
}

if (nodeIds[a] == neighborId)
{
neighbors[nextNeighbor++] = a;
}
}
}
__syncthreads();

// Find the farthest node from the lowest indexed node (first root point)
// Start by marking the first node and threads without a node as seen
// Mark initial distances in scratch vector
if (threadIdx.x < aggSize)
scratchA[threadIdx.x] = threadIdx.x == 0 ? 0 : -1;
int myDist = threadIdx.x == 0 ? 0 : -1;
bool swapped = false;
incomplete = true;
__syncthreads();

while (incomplete)
{
// Set the incomplete flag to false
incomplete = false;
__syncthreads();

// Check if a neighbor has a positive distance
if (threadIdx.x < aggSize && myDist == -1)
{
for (int i = 0; i < nextNeighbor; i++)
{
int neighborDist = scratchA[neighbors[i]];
if (neighborDist > -1)
myDist = neighborDist + 1;
}
}
__syncthreads();

if (threadIdx.x < aggSize && myDist > 0 && !swapped)
{
swapped = true;
scratchA[threadIdx.x] = myDist;
rootA = threadIdx.x;
incomplete = true;
}
__syncthreads();
}

// Find the farthest node from the first root point (second root point)
// Start by marking the first node and threads without a node as seen
// Mark initial distances in scratch vector
if (threadIdx.x < aggSize)
scratchA[threadIdx.x] = threadIdx.x == rootA ? 0 : -1;
myDist = threadIdx.x == rootA ? 0 : -1;
swapped = false;
incomplete = true;
__syncthreads();

while (incomplete)
{
// Set the incomplete flag to false
incomplete = false;
__syncthreads();

// Check if a neighbor has a positive distance
if (threadIdx.x < aggSize && myDist == -1)
{
for (int i = 0; i < nextNeighbor; i++)
{
int neighborDist = scratchA[neighbors[i]];
if (neighborDist > -1)
{
myDist = neighborDist + 1;
}
}
}
__syncthreads();

if (threadIdx.x < aggSize && myDist > 0 && !swapped)
{
swapped = true;
scratchA[threadIdx.x] = myDist;
rootB = threadIdx.x;
incomplete = true;
}
__syncthreads();
}

// Setting an assigned aggregate label (In ScratchA) for every node with the node at
// rootA being assigned the current aggregate ID and the node at rootB
// being assigned the newAgg ID and set initial distances from a root node
// (In ScratchB) for each node, -1 for unknown and 0 for the roots
int myAggregate = -1;
if (threadIdx.x == rootA)
myAggregate = currentAgg;
if (threadIdx.x == rootB)
myAggregate = newAgg;
if (threadIdx.x < aggSize)
{
scratchA[threadIdx.x] = myAggregate;
scratchB[threadIdx.x] = myAggregate > -1 ? 0 : -1;
}
incomplete = true;
__syncthreads();

// Assign nodes to each aggregate until no unassigned nodes remain.
while (incomplete)
{
// Set the incomplete flag to false
incomplete = false;
__syncthreads();

if (threadIdx.x < aggSize && myAggregate == -1)
{
for (int i = 0; i < nextNeighbor; i++)
{
int neighborAgg = scratchA[neighbors[i]];
if (neighborAgg > -1)
{
myDist = scratchB[neighbors[i]] + 1;
myAggregate = neighborAgg;
}
}
if (myAggregate == -1)
incomplete = true;
if (myAggregate == newAgg)
atomicAdd((unsigned int*)&bCount, (unsigned)1);
if (myAggregate == currentAgg)
atomicAdd((unsigned int*)&aCount, (unsigned)1);
}
__syncthreads();

if (threadIdx.x < aggSize)
{
scratchA[threadIdx.x] = myAggregate;
scratchB[threadIdx.x] = myDist;
}
__syncthreads();
}

// If the split was uneven try to repair it
int sizeDifference = aCount > bCount ? aCount - bCount : bCount - aCount;
bool moveToA = aCount < bCount;
__shared__ int moved;
moved = 0;
int toMove = sizeDifference / 2;
incomplete = true;
__syncthreads();

while (incomplete && moved < toMove)
{
incomplete = false;
__syncthreads();
bool swapping = false;
int newDist = INT_MAX;
if (threadIdx.x < aggSize)
{
bool canSwap = moveToA ? myAggregate == newAgg : myAggregate == currentAgg;
bool borderNode = false;

// Check if this node has no same aggregate neighbors of higher distance
// and on a border
for (int i = 0; i < nextNeighbor; i++)
{
int neighborAgg = scratchA[neighbors[i]];
int neighborDist = scratchB[neighbors[i]];
if (neighborAgg == myAggregate && neighborDist > myDist)
canSwap = false;

if (neighborAgg != myAggregate)
{
if (neighborDist + 1 < newDist)
newDist = neighborDist + 1;
borderNode = true;
}
}

// If a node could swap see if it will
if (borderNode && canSwap && atomicAdd((unsigned int*)&moved, 1) < toMove)
{
swapping = true;
}
}
__syncthreads();
if (swapping)
{
int a = moveToA ? 1 : -1;
atomicAdd((unsigned int*)&bCount, -a);
atomicAdd((unsigned int*)&aCount, a);
scratchA[threadIdx.x] = moveToA ? currentAgg : newAgg;
scratchB[threadIdx.x] = newDist;
incomplete = true;
}
__syncthreads();
}

// Write out the values to the aggregation array
if (threadIdx.x < aggSize)
{
aggregation[nodeId] = scratchA[threadIdx.x];
}

}
	.text
	.file	"MakeSplits_Large.hip"
	.globl	_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_ # -- Begin function _Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_
	.type	_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_,@function
_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_: # @_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16MakeSplits_LargeiPiS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_, .Lfunc_end0-_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16MakeSplits_LargeiPiS_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16MakeSplits_LargeiPiS_S_S_S_S_,@object # @_Z16MakeSplits_LargeiPiS_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z16MakeSplits_LargeiPiS_S_S_S_S_
	.p2align	3, 0x0
_Z16MakeSplits_LargeiPiS_S_S_S_S_:
	.quad	_Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_
	.size	_Z16MakeSplits_LargeiPiS_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16MakeSplits_LargeiPiS_S_S_S_S_"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__MakeSplits_LargeiPiS_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16MakeSplits_LargeiPiS_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16MakeSplits_LargeiPiS_S_S_S_S_ ; -- Begin function _Z16MakeSplits_LargeiPiS_S_S_S_S_
	.globl	_Z16MakeSplits_LargeiPiS_S_S_S_S_
	.p2align	8
	.type	_Z16MakeSplits_LargeiPiS_S_S_S_S_,@function
_Z16MakeSplits_LargeiPiS_S_S_S_S_:      ; @_Z16MakeSplits_LargeiPiS_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	s_mov_b32 s18, s15
	s_mov_b32 s19, 0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, 1
	s_lshl_b64 s[2:3], s[18:19], 2
	v_dual_mov_b32 v2, 0xc0c :: v_dual_lshlrev_b32 v7, 2, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_load_b32 s16, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[16:17], 2
	s_add_u32 s2, s8, s2
	s_addc_u32 s3, s9, s3
	s_load_b64 s[4:5], s[2:3], 0x0
	s_load_b128 s[12:15], s[0:1], 0x28
	ds_store_b8 v8, v1 offset:3092
	ds_store_2addr_b32 v2, v1, v1 offset1:1
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s8, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s8, v0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v1
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v1, -1
	v_mov_b32_e32 v2, -1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_14
; %bb.3:
	ds_load_b32 v1, v7
	v_mov_b32_e32 v8, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v3, v4
	s_cbranch_execz .LBB0_13
; %bb.4:                                ; %.lr.ph207
	s_add_i32 s5, s8, -1
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v3
	s_cmp_gt_i32 s8, 1
	s_mov_b32 s9, 0
	s_cselect_b32 s8, -1, 0
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_mov_b32_e32 v3, 0
	v_lshlrev_b64 v[9:10], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s14, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s8
	global_load_b32 v6, v[9:10], off
	s_cbranch_vccnz .LBB0_9
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v9, s5
	s_mov_b32 s10, 0
.LBB0_7:                                ; %.lr.ph
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v9, v3
	v_lshrrev_b32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v11
	v_ashrrev_i32_e32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v3
	v_lshlrev_b32_e32 v11, 2, v10
	ds_load_b32 v11, v11
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v11, v6
	v_dual_cndmask_b32 v9, v10, v9 :: v_dual_add_nc_u32 v12, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v12, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v3, v9
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ; %Flow325
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_lshlrev_b32_e32 v9, 2, v3
	s_mov_b32 s10, exec_lo
	ds_load_b32 v9, v9
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_eq_u32_e64 v9, v6
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=1
	v_lshl_add_u32 v6, v8, 2, 16
	v_add_nc_u32_e32 v8, 1, v8
	scratch_store_b32 v6, v3, off
.LBB0_11:                               ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v5, v4
	s_or_b32 s9, vcc_lo, s9
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_5
; %bb.12:                               ; %Flow328
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_13:                               ; %Flow329
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_14:                               ; %.loopexit201
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	ds_store_b32 v7, v3 offset:1024
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v5, 1
	v_cmp_gt_i32_e64 s3, 1, v8
	s_mov_b32 s5, 0
	ds_store_b8 v3, v5 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v4, v3 offset:3092
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v4
	v_lshl_add_u32 v4, v0, 2, 0x400
	s_cbranch_vccnz .LBB0_25
; %bb.17:                               ; %.lr.ph217
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_xor_b32 s8, s2, -1
	v_cndmask_b32_e64 v6, 0, -1, vcc_lo
.LBB0_18:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_20 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	ds_store_b8 v3, v3 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_or_b32 s4, s8, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s4, s3
	s_xor_b32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s4
	s_cbranch_execz .LBB0_22
; %bb.19:                               ; %.lr.ph211.preheader
                                        ;   in Loop: Header=BB0_18 Depth=1
	v_dual_mov_b32 v9, 16 :: v_dual_mov_b32 v6, -1
	v_mov_b32_e32 v10, v8
	s_mov_b32 s10, 0
.LBB0_20:                               ; %.lr.ph211
                                        ;   Parent Loop BB0_18 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v11, v9, off
	v_add_nc_u32_e32 v10, -1, v10
	v_add_nc_u32_e32 v9, 4, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v11, 2, v11
	ds_load_b32 v11, v11 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, 1, v11
	v_cmp_gt_i32_e64 s4, 0, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v12, v6, s4
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_20
; %bb.21:                               ; %Flow319
                                        ;   in Loop: Header=BB0_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_22:                               ; %Flow320
                                        ;   in Loop: Header=BB0_18 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_cmp_gt_i32_e32 vcc_lo, 1, v6
	s_barrier
	buffer_gl0_inv
	s_or_b32 s4, s8, vcc_lo
	s_or_b32 s4, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s9, s4, -1
	s_and_saveexec_b32 s4, s9
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_18 Depth=1
	s_or_b32 s5, s5, exec_lo
	ds_store_b32 v3, v0 offset:3076
	ds_store_b32 v4, v6
	ds_store_b8 v3, v5 offset:3092
.LBB0_24:                               ;   in Loop: Header=BB0_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v9, v3 offset:3092
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v9
	s_cbranch_vccnz .LBB0_18
.LBB0_25:                               ; %._crit_edge218
	ds_load_b32 v3, v3 offset:3076
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_27
; %bb.26:
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v0, v3
	v_cndmask_b32_e64 v5, 0, -1, vcc_lo
	ds_store_b32 v7, v5 offset:1024
.LBB0_27:                               ; %._crit_edge218._crit_edge
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 1
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e64 s3, v0, v3
	s_mov_b32 s5, 0
	ds_store_b8 v5, v6 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v9, v5 offset:3092
	v_cndmask_b32_e64 v3, 0, -1, s3
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v9
	s_cbranch_vccnz .LBB0_36
; %bb.28:                               ; %.lr.ph227
	v_cmp_gt_i32_e64 s3, 1, v8
	s_xor_b32 s8, s2, -1
.LBB0_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_31 Depth 2
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	ds_store_b8 v5, v5 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_or_b32 s4, s8, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s4, s3
	s_xor_b32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s4
	s_cbranch_execz .LBB0_33
; %bb.30:                               ; %.lr.ph221.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	v_dual_mov_b32 v9, 16 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v3, -1
	s_mov_b32 s10, 0
.LBB0_31:                               ; %.lr.ph221
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v11, v9, off
	v_add_nc_u32_e32 v10, -1, v10
	v_add_nc_u32_e32 v9, 4, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v11, 2, v11
	ds_load_b32 v11, v11 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, 1, v11
	v_cmp_gt_i32_e64 s4, 0, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v12, v3, s4
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_31
; %bb.32:                               ; %Flow314
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_33:                               ; %Flow315
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_cmp_gt_i32_e32 vcc_lo, 1, v3
	s_barrier
	buffer_gl0_inv
	s_or_b32 s4, s8, vcc_lo
	s_or_b32 s4, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s9, s4, -1
	s_and_saveexec_b32 s4, s9
	s_cbranch_execz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 s5, s5, exec_lo
	ds_store_b32 v5, v0 offset:3080
	ds_store_b32 v4, v3
	ds_store_b8 v5, v6 offset:3092
.LBB0_35:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v9, v5 offset:3092
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v9
	s_cbranch_vccnz .LBB0_29
.LBB0_36:                               ; %._crit_edge228
	v_mov_b32_e32 v4, 0xc04
	s_load_b32 s0, s[0:1], 0x0
	ds_load_2addr_b32 v[4:5], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s1, s18, s0
	v_cmp_eq_u32_e32 vcc_lo, v0, v4
	v_cndmask_b32_e64 v4, -1, s16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v4, s1, vcc_lo
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_38
; %bb.37:
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v0
	ds_store_2addr_stride64_b32 v7, v0, v4 offset0:4 offset1:8
.LBB0_38:
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 1
	v_cmp_lt_i32_e64 s0, 0, v8
	ds_store_b8 v4, v5 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v6, v4 offset:3092
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v6
	s_cbranch_vccnz .LBB0_60
; %bb.39:                               ; %.lr.ph241
	v_add_nc_u32_e32 v6, 0x800, v7
	v_add_nc_u32_e32 v9, 0x400, v7
.LBB0_40:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_43 Depth 2
	v_cmp_eq_u32_e32 vcc_lo, -1, v0
	ds_store_b8 v4, v4 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s4, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s4
	s_cbranch_execz .LBB0_57
; %bb.41:                               ; %.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v0, -1
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_47
; %bb.42:                               ; %.lr.ph233.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	v_dual_mov_b32 v10, 16 :: v_dual_mov_b32 v11, v8
	v_mov_b32_e32 v0, -1
	s_mov_b32 s5, 0
.LBB0_43:                               ; %.lr.ph233
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v12, v10, off
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v13, 2, v12
	ds_load_b32 v12, v13 offset:1024
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 -1, v12
	s_cbranch_execz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_43 Depth=2
	ds_load_b32 v0, v13 offset:2048
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, v12 :: v_dual_add_nc_u32 v3, 1, v0
.LBB0_45:                               ;   in Loop: Header=BB0_43 Depth=2
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v11, -1, v11
	v_add_nc_u32_e32 v10, 4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_or_b32 s5, vcc_lo, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_43
; %bb.46:                               ; %Flow308
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_47:                               ; %Flow309
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e32 -1, v0
	s_cbranch_execz .LBB0_49
; %bb.48:                               ;   in Loop: Header=BB0_40 Depth=1
	ds_store_b8 v4, v5 offset:3092
.LBB0_49:                               ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e64 s1, v0
	s_cbranch_execz .LBB0_52
; %bb.50:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v10, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_and_b32 s8, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s8
	s_cbranch_execz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_40 Depth=1
	s_bcnt1_i32_b32 s5, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v10, s5
	ds_add_u32 v4, v10 offset:3088
.LBB0_52:                               ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e64 s16, v0
	s_cbranch_execz .LBB0_56
; %bb.53:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_40 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s8
	ds_add_u32 v4, v0 offset:3084
.LBB0_55:                               ; %Flow305
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v0, s16
.LBB0_56:                               ; %Flow306
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_57:                               ; %Flow310
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_59
; %bb.58:                               ;   in Loop: Header=BB0_40 Depth=1
	ds_store_b32 v9, v0
	ds_store_b32 v6, v3
.LBB0_59:                               ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v10, v4 offset:3092
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v10
	s_cbranch_vccnz .LBB0_40
.LBB0_60:                               ; %._crit_edge242
	v_dual_mov_b32 v4, 0xc0c :: v_dual_mov_b32 v5, 1
	ds_load_2addr_b32 v[9:10], v4 offset1:1
	v_mov_b32_e32 v4, 0
	ds_store_b32 v4, v4 offset:3072
	ds_store_b8 v4, v5 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v6, v4 offset:3092
	ds_load_b32 v11, v4 offset:3072
	v_readfirstlane_b32 s3, v9
	v_readfirstlane_b32 s5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s3, s5
	s_abs_i32 s0, s0
	s_waitcnt lgkmcnt(1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v6
	s_lshr_b32 s4, s0, 1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, s4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_79
; %bb.61:                               ; %.lr.ph256
	s_cmp_lt_i32 s3, s5
	v_cmp_lt_i32_e64 s0, 0, v8
	s_cselect_b32 s3, s1, s16
	v_add_nc_u32_e32 v6, 0x400, v7
	v_cmp_eq_u32_e64 s5, s3, v0
	v_add_nc_u32_e32 v9, 0x800, v7
	s_cselect_b32 s8, -1, 1
	s_cselect_b32 s9, 1, -1
	s_cselect_b32 s10, s16, s1
.LBB0_62:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_65 Depth 2
	v_bfrev_b32_e32 v10, -2
	s_mov_b32 s3, 0
	ds_store_b8 v4, v4 offset:3092
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s11, s2
	s_cbranch_execz .LBB0_72
; %bb.63:                               ;   in Loop: Header=BB0_62 Depth=1
	v_bfrev_b32_e32 v10, -2
	s_mov_b32 s1, 0
	s_mov_b32 s3, s5
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_67
; %bb.64:                               ; %.lr.ph250.preheader
                                        ;   in Loop: Header=BB0_62 Depth=1
	v_dual_mov_b32 v11, 16 :: v_dual_mov_b32 v12, v8
	v_bfrev_b32_e32 v10, -2
	s_mov_b32 s15, 0
	s_mov_b32 s14, 0
	s_mov_b32 s16, s5
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $sgpr17
.LBB0_65:                               ; %.lr.ph250
                                        ;   Parent Loop BB0_62 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v13, v11, off
	v_add_nc_u32_e32 v12, -1, v12
	v_add_nc_u32_e32 v11, 4, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v13, 2, v13
	ds_load_2addr_stride64_b32 v[13:14], v13 offset0:4 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, 1, v14
	v_cmp_le_i32_e64 s1, v14, v3
	v_cmp_ne_u32_e64 s3, v13, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_i32_e32 v14, v15, v10
	s_or_b32 s1, s3, s1
	s_or_b32 s15, s3, s15
	s_and_b32 s16, s1, s16
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v10, v14, s3
	s_or_b32 s14, vcc_lo, s14
	s_and_not1_b32 s1, s17, exec_lo
	s_and_b32 s3, s16, exec_lo
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s18, s15, exec_lo
	s_or_b32 s17, s1, s3
	s_or_b32 s13, s13, s18
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_65
; %bb.66:                               ; %Flow300
                                        ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s14, s17, exec_lo
	s_and_b32 s1, s13, exec_lo
	s_or_b32 s3, s3, s14
.LBB0_67:                               ; %Flow301
                                        ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_and_b32 s12, s1, s3
	s_mov_b32 s3, 0
	s_and_saveexec_b32 s1, s12
	s_cbranch_execz .LBB0_71
; %bb.68:                               ;   in Loop: Header=BB0_62 Depth=1
	s_mov_b32 s12, exec_lo
	s_mov_b32 s3, exec_lo
	v_mbcnt_lo_u32_b32 v11, s12, 0
                                        ; implicit-def: $vgpr12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB0_70
; %bb.69:                               ;   in Loop: Header=BB0_62 Depth=1
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v12, s12
	ds_add_rtn_u32 v12, v4, v12 offset:3072
.LBB0_70:                               ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, s3, v11
	v_cmp_gt_u32_e32 vcc_lo, s4, v11
	s_and_b32 s3, vcc_lo, exec_lo
.LBB0_71:                               ; %Flow299
                                        ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
.LBB0_72:                               ; %Flow302
                                        ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB0_78
; %bb.73:                               ;   in Loop: Header=BB0_62 Depth=1
	s_mov_b32 s11, exec_lo
	s_mov_b32 s3, exec_lo
	v_mbcnt_lo_u32_b32 v11, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB0_75
; %bb.74:                               ;   in Loop: Header=BB0_62 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s8, s11
	v_mov_b32_e32 v11, s11
	ds_add_u32 v4, v11 offset:3088
.LBB0_75:                               ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s11, exec_lo
	s_mov_b32 s3, exec_lo
	v_mbcnt_lo_u32_b32 v11, s11, 0
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_62 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s9, s11
	v_mov_b32_e32 v11, s11
	ds_add_u32 v4, v11 offset:3084
.LBB0_77:                               ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v11, s10
	ds_store_b32 v6, v11
	ds_store_b32 v9, v10
	ds_store_b8 v4, v5 offset:3092
.LBB0_78:                               ; %Flow
                                        ;   in Loop: Header=BB0_62 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v10, v4 offset:3092
	ds_load_b32 v11, v4 offset:3072
	s_waitcnt lgkmcnt(1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v10
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s1, s4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_62
.LBB0_79:                               ; %._crit_edge257
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_81
; %bb.80:
	ds_load_b32 v3, v7 offset:1024
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB0_81:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16MakeSplits_LargeiPiS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 3096
		.amdhsa_private_segment_fixed_size 176
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16MakeSplits_LargeiPiS_S_S_S_S_, .Lfunc_end0-_Z16MakeSplits_LargeiPiS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2856
; NumSgprs: 22
; NumVgprs: 16
; ScratchSize: 176
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 3096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16MakeSplits_LargeiPiS_S_S_S_S_
    .private_segment_fixed_size: 176
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z16MakeSplits_LargeiPiS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
