// write your code into this file
#define TILE_X 16
#define TILE_Y 8
#define TILE_Z 8
#define PADDING 1

__global__ void compute_cell(int* in_array, int* out_array, int dim);

void solveGPU(int **dCells, int dim, int iters)
{
	dim3 threadsPerBlock(TILE_X, TILE_Y, TILE_Z);
	dim3 numBlocks((int)ceil(dim/(float)(TILE_X-2)), (int)ceil(dim/(float)(TILE_Y-2)), (int)ceil(dim/(float)(TILE_Z-2)));
	
	int* result_array;
	cudaMalloc((void**)&result_array, dim*dim*dim*sizeof(int));
    int* tmp;
	int* array_in;
	int* array_out;

    array_in = *dCells;
    array_out = (int*)result_array;

	cudaFuncSetCacheConfig(compute_cell, cudaFuncCachePreferShared);

	
	for (int i = 0; i < iters; i++)
	{
		compute_cell<<<numBlocks, threadsPerBlock>>>(array_in, array_out, dim);
		result_array = array_out;
        tmp = array_in;
        array_in = array_out;
        array_out = tmp;
	}

    *dCells = result_array; // result array from loop above
    cudaFree(array_out);
}


__global__ void compute_cell(int* in_array, int* out_array, int dim)
{
	__shared__ int tile[TILE_Z][TILE_Y][TILE_X];

    int mat_idx_x = blockIdx.x*(blockDim.x-2) + threadIdx.x-1;
    int mat_idx_y = blockIdx.y*(blockDim.y-2) + threadIdx.y-1;
    int mat_idx_z = blockIdx.z*(blockDim.z-2) + threadIdx.z-1;
	
	int dim2 = dim*dim;
	
	unsigned short thread_exceeds_matrix = 1;
	if ((mat_idx_x < dim) && (mat_idx_y < dim) && (mat_idx_z < dim) && (mat_idx_x >= 0) && (mat_idx_y >= 0) && (mat_idx_z >= 0))
	{
		thread_exceeds_matrix = 0;
		tile[threadIdx.z][threadIdx.y][threadIdx.x] = in_array[mat_idx_x+(mat_idx_y*dim)+(mat_idx_z*dim2)];
	}
	else
		tile[threadIdx.z][threadIdx.y][threadIdx.x] = 0;
	__syncthreads();
	
	
	int result = 0;
	int shared_value = tile[threadIdx.z][threadIdx.y][threadIdx.x];
	
	int is_hull = 1;
	if (threadIdx.x > 0 && threadIdx.y > 0 && threadIdx.z > 0
		&& threadIdx.x < (TILE_X-1) && threadIdx.y < (TILE_Y-1) && threadIdx.z < (TILE_Z-1) )
	{
		is_hull = 0;
	}
	
	if (!is_hull)
	{
		for (int i = -1; i < 2; i++)
		{
			for (int j = -1; j < 2; j++)
			{
				for (int k = -1; k < 2; k++)
				{
					result += tile[threadIdx.z+i][threadIdx.y+j][threadIdx.x+k];
				}
			}
		}
		result -= shared_value;
		
		if ((result < 4) || (result > 5))
		{
			result = 0;
		}
		else if (result == 5)
		{
			result = 1;
		}
		else
		{
			result = shared_value;
		}
	}
	__syncthreads();
	
	// loading back to global
	if (!is_hull && !thread_exceeds_matrix)
	{
		out_array[mat_idx_x+(mat_idx_y*dim)+(mat_idx_z*dim2)] = result;
	}

/*	__syncthreads();
	if (mat_idx_x == 0  && mat_idx_y == 0 && mat_idx_z == 0)
	{
		
	printf("gpu:\n");
	
	for (int i = 0; i<TILE_X;i++)
		for (int j = 0; j<TILE_Y; j++)
		{
			for (int k = 0;k< TILE_Z; k++)
				printf("%d ", tile[i][j][k]);
		
		printf("\n");
		}	
			
	}
*/
	
	// cell life computation
}

	.file	"tmpxft_002c3ada_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z12compute_cellPiS_iPiS_i
	.type	_Z35__device_stub__Z12compute_cellPiS_iPiS_i, @function
_Z35__device_stub__Z12compute_cellPiS_iPiS_i:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12compute_cellPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z35__device_stub__Z12compute_cellPiS_iPiS_i, .-_Z35__device_stub__Z12compute_cellPiS_iPiS_i
	.globl	_Z12compute_cellPiS_i
	.type	_Z12compute_cellPiS_i, @function
_Z12compute_cellPiS_i:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z12compute_cellPiS_iPiS_i
	.cfi_endproc
.LFE2034:
	.size	_Z12compute_cellPiS_i, .-_Z12compute_cellPiS_i
	.globl	_Z8solveGPUPPiii
	.type	_Z8solveGPUPPiii, @function
_Z8solveGPUPPiii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	cvtsi2ssl	%esi, %xmm1
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movaps	%xmm1, %xmm0
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	divss	.LC0(%rip), %xmm0
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	movabsq	$34359738384, %rax
	movss	%xmm1, 12(%rsp)
	movl	$8, 40(%rsp)
	movq	%rax, 32(%rsp)
	call	ceilf@PLT
	movss	12(%rsp), %xmm1
	divss	.LC1(%rip), %xmm1
	cvttss2sil	%xmm0, %r13d
	movaps	%xmm1, %xmm0
	call	ceilf@PLT
	movl	%ebx, %esi
	leaq	24(%rsp), %rdi
	imull	%ebx, %esi
	cvttss2sil	%xmm0, %eax
	movl	%r13d, 48(%rsp)
	imull	%ebx, %esi
	movl	%r13d, 52(%rsp)
	movl	%eax, 44(%rsp)
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1, %esi
	movq	0(%rbp), %r15
	leaq	_Z12compute_cellPiS_i(%rip), %rdi
	movq	24(%rsp), %r13
	call	cudaFuncSetCacheConfig@PLT
.L9:
	cmpl	%r12d, %r14d
	jge	.L14
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movl	%ebx, %edx
	movq	%r13, %rsi
	movq	%r15, %rdi
	call	_Z35__device_stub__Z12compute_cellPiS_iPiS_i
.L10:
	movq	%r13, 24(%rsp)
	incl	%r14d
	xchgq	%r13, %r15
	jmp	.L9
.L14:
	movq	24(%rsp), %rax
	movq	%r13, %rdi
	movq	%rax, 0(%rbp)
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z8solveGPUPPiii, .-_Z8solveGPUPPiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z12compute_cellPiS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12compute_cellPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1086324736
	.align 4
.LC1:
	.long	1096810496
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// write your code into this file
#define TILE_X 16
#define TILE_Y 8
#define TILE_Z 8
#define PADDING 1

__global__ void compute_cell(int* in_array, int* out_array, int dim);

void solveGPU(int **dCells, int dim, int iters)
{
	dim3 threadsPerBlock(TILE_X, TILE_Y, TILE_Z);
	dim3 numBlocks((int)ceil(dim/(float)(TILE_X-2)), (int)ceil(dim/(float)(TILE_Y-2)), (int)ceil(dim/(float)(TILE_Z-2)));
	
	int* result_array;
	hipMalloc((void**)&result_array, dim*dim*dim*sizeof(int));
    int* tmp;
	int* array_in;
	int* array_out;

    array_in = *dCells;
    array_out = (int*)result_array;

	hipFuncSetCacheConfig(reinterpret_cast<const void*>(compute_cell), hipFuncCachePreferShared);

	
	for (int i = 0; i < iters; i++)
	{
		compute_cell<<<numBlocks, threadsPerBlock>>>(array_in, array_out, dim);
		result_array = array_out;
        tmp = array_in;
        array_in = array_out;
        array_out = tmp;
	}

    *dCells = result_array; // result array from loop above
    hipFree(array_out);
}


__global__ void compute_cell(int* in_array, int* out_array, int dim)
{
	__shared__ int tile[TILE_Z][TILE_Y][TILE_X];

    int mat_idx_x = blockIdx.x*(blockDim.x-2) + threadIdx.x-1;
    int mat_idx_y = blockIdx.y*(blockDim.y-2) + threadIdx.y-1;
    int mat_idx_z = blockIdx.z*(blockDim.z-2) + threadIdx.z-1;
	
	int dim2 = dim*dim;
	
	unsigned short thread_exceeds_matrix = 1;
	if ((mat_idx_x < dim) && (mat_idx_y < dim) && (mat_idx_z < dim) && (mat_idx_x >= 0) && (mat_idx_y >= 0) && (mat_idx_z >= 0))
	{
		thread_exceeds_matrix = 0;
		tile[threadIdx.z][threadIdx.y][threadIdx.x] = in_array[mat_idx_x+(mat_idx_y*dim)+(mat_idx_z*dim2)];
	}
	else
		tile[threadIdx.z][threadIdx.y][threadIdx.x] = 0;
	__syncthreads();
	
	
	int result = 0;
	int shared_value = tile[threadIdx.z][threadIdx.y][threadIdx.x];
	
	int is_hull = 1;
	if (threadIdx.x > 0 && threadIdx.y > 0 && threadIdx.z > 0
		&& threadIdx.x < (TILE_X-1) && threadIdx.y < (TILE_Y-1) && threadIdx.z < (TILE_Z-1) )
	{
		is_hull = 0;
	}
	
	if (!is_hull)
	{
		for (int i = -1; i < 2; i++)
		{
			for (int j = -1; j < 2; j++)
			{
				for (int k = -1; k < 2; k++)
				{
					result += tile[threadIdx.z+i][threadIdx.y+j][threadIdx.x+k];
				}
			}
		}
		result -= shared_value;
		
		if ((result < 4) || (result > 5))
		{
			result = 0;
		}
		else if (result == 5)
		{
			result = 1;
		}
		else
		{
			result = shared_value;
		}
	}
	__syncthreads();
	
	// loading back to global
	if (!is_hull && !thread_exceeds_matrix)
	{
		out_array[mat_idx_x+(mat_idx_y*dim)+(mat_idx_z*dim2)] = result;
	}

/*	__syncthreads();
	if (mat_idx_x == 0  && mat_idx_y == 0 && mat_idx_z == 0)
	{
		
	printf("gpu:\n");
	
	for (int i = 0; i<TILE_X;i++)
		for (int j = 0; j<TILE_Y; j++)
		{
			for (int k = 0;k< TILE_Z; k++)
				printf("%d ", tile[i][j][k]);
		
		printf("\n");
		}	
			
	}
*/
	
	// cell life computation
}

	.text
	.file	"kernel.hip"
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z8solveGPUPPiii
.LCPI0_0:
	.long	0x41600000                      # float 14
.LCPI0_1:
	.long	0x40c00000                      # float 6
	.text
	.globl	_Z8solveGPUPPiii
	.type	_Z8solveGPUPPiii,@function
_Z8solveGPUPPiii:                       # @_Z8solveGPUPPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%esi, %ebx
	cvtsi2ss	%esi, %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%rdi, %r14
	divss	.LCPI0_0(%rip), %xmm0
	callq	ceilf@PLT
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI0_1(%rip), %xmm0
	callq	ceilf@PLT
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	movl	%ebx, %eax
	imull	%ebx, %eax
	movl	%ebx, 12(%rsp)                  # 4-byte Spill
	imull	%ebx, %eax
	movslq	%eax, %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	%r14, 32(%rsp)                  # 8-byte Spill
	movq	(%r14), %r14
	movq	(%rbx), %r15
	movl	$_Z12compute_cellPiS_i, %edi
	movl	$1, %esi
	callq	hipFuncSetCacheConfig
	testl	%ebp, %ebp
	jle	.LBB0_5
# %bb.1:
	cvttss2si	20(%rsp), %eax          # 4-byte Folded Reload
	cvttss2si	16(%rsp), %r12d         # 4-byte Folded Reload
	movq	%r12, %r13
	shlq	$32, %r13
	orq	%rax, %r13
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rbx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movabsq	$34359738384, %rdx              # imm = 0x800000010
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:                                #   in Loop: Header=BB0_2 Depth=1
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	12(%rsp), %edx                  # 4-byte Reload
	callq	_Z27__device_stub__compute_cellPiS_i
.LBB0_4:                                #   in Loop: Header=BB0_2 Depth=1
	movq	%r15, 24(%rsp)
	movq	%r15, %rax
	movq	%r15, %r14
	movq	%rbx, %r15
	decl	%ebp
	jne	.LBB0_2
	jmp	.LBB0_6
.LBB0_5:                                # %.._crit_edge_crit_edge
	movq	24(%rsp), %rax
	movq	%r15, %rbx
.LBB0_6:                                # %._crit_edge
	movq	32(%rsp), %rcx                  # 8-byte Reload
	movq	%rax, (%rcx)
	movq	%rbx, %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z8solveGPUPPiii, .Lfunc_end0-_Z8solveGPUPPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__compute_cellPiS_i # -- Begin function _Z27__device_stub__compute_cellPiS_i
	.type	_Z27__device_stub__compute_cellPiS_i,@function
_Z27__device_stub__compute_cellPiS_i:   # @_Z27__device_stub__compute_cellPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12compute_cellPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__compute_cellPiS_i, .Lfunc_end1-_Z27__device_stub__compute_cellPiS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12compute_cellPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12compute_cellPiS_i,@object   # @_Z12compute_cellPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z12compute_cellPiS_i
	.p2align	3, 0x0
_Z12compute_cellPiS_i:
	.quad	_Z27__device_stub__compute_cellPiS_i
	.size	_Z12compute_cellPiS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12compute_cellPiS_i"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__compute_cellPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12compute_cellPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12compute_cellPiS_i   ; -- Begin function _Z12compute_cellPiS_i
	.globl	_Z12compute_cellPiS_i
	.p2align	8
	.type	_Z12compute_cellPiS_i,@function
_Z12compute_cellPiS_i:                  ; @_Z12compute_cellPiS_i
; %bb.0:
	s_clause 0x2
	s_load_b64 s[8:9], s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x10
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_mov_b32 s10, -1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_lshr_b32 s1, s8, 16
	s_add_i32 s0, s0, -2
	s_add_i32 s1, s1, -2
	s_mul_i32 s0, s0, s13
	s_mul_i32 s1, s1, s14
	v_add3_u32 v1, v5, s0, -1
	v_add3_u32 v2, v4, s1, -1
	s_and_b32 s0, s9, 0xffff
	s_mov_b32 s9, -1
	s_add_i32 s0, s0, -2
	s_mul_i32 s8, s3, s3
	v_max_i32_e32 v6, v1, v2
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v3, s0, -1
	v_cmp_gt_i32_e32 vcc_lo, s3, v6
	v_mov_b32_e32 v6, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_or3_b32 v6, v1, v2, v0
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	s_mov_b32 s2, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s0, -1, v6
	v_mov_b32_e32 v6, 0
	s_and_b32 s10, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s10
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mul_lo_u32 v6, v2, s3
	v_mul_lo_u32 v7, v0, s8
	s_xor_b32 s2, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v6, v1, v7
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
.LBB0_3:                                ; %Flow100
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s10, s2, exec_lo
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b32_e32 v7, 2, v5
	v_lshlrev_b32_e32 v8, 6, v4
	v_lshlrev_b32_e32 v9, 9, v3
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	v_cmp_ne_u32_e64 s0, 0, v4
	v_cmp_ne_u32_e64 s1, 0, v3
	v_cmp_gt_u32_e64 s2, 15, v5
	v_add3_u32 v9, v9, v8, v7
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s1, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v9
	s_and_b32 s1, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
; %bb.5:
	v_max_u32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 6, v4
	s_or_not1_b32 s9, vcc_lo, exec_lo
; %bb.6:
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v4, 0
	s_mov_b32 s1, -1
	s_xor_b32 s2, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_12
; %bb.7:                                ; %.preheader74.preheader
	v_lshl_add_u32 v3, v3, 9, v8
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v3, v3, v7, 0xfffffdbc
.LBB0_8:                                ; %.preheader74
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	s_mov_b32 s2, 0
.LBB0_9:                                ; %.preheader
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v5, s2, v3
	s_add_i32 s2, s2, 64
	ds_load_2addr_b32 v[7:8], v5 offset1:1
	ds_load_b32 v5, v5 offset:8
	s_cmpk_lg_i32 s2, 0xc0
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v8, v4, v5
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	v_add_nc_u32_e32 v3, 0x200, v3
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 2
	s_cbranch_scc0 .LBB0_8
; %bb.11:
	v_sub_nc_u32_e32 v3, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 5, v3
	v_dual_cndmask_b32 v3, 1, v6 :: v_dual_add_nc_u32 v4, -6, v3
	v_cmp_lt_u32_e32 vcc_lo, -3, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v3, vcc_lo
.LBB0_12:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_or_b32 s0, s10, s9
	s_waitcnt lgkmcnt(0)
	s_xor_b32 s0, s0, -1
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_mul_lo_u32 v2, v2, s3
	v_mul_lo_u32 v0, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v2, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12compute_cellPiS_i
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12compute_cellPiS_i, .Lfunc_end0-_Z12compute_cellPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 716
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12compute_cellPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12compute_cellPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
