#include <time.h>
#include <cuda.h>
#include <stdio.h>
#define STOP 0
#define START 1

#define BLOCK_X 16
#define BLOCK_Y 16

extern "C" void chrono (int kind, float *time);

__global__ void kconvol (float *gpu_a, float *gpu_b, int pitch, int n) {
  int ig, jg, lg, il, jl, ll;
  __shared__ float la[(BLOCK_X+2)*(BLOCK_Y+2)];
  __shared__ float lb[(BLOCK_X+2)*(BLOCK_Y+2)];
 
 // A thread now has two sets of coordinates : 
  // (ig, jg) in the global array
  // (il, jl) in the local array (shared) of size (BLOCK_X+2)*(BLOCK_Y+2)
  ig = blockDim.x*blockIdx.x+threadIdx.x;
  jg = blockDim.y*blockIdx.y+threadIdx.y;
  lg = ig+jg*pitch;
  // UP TO YOU : write below the indices il and jl
  il = threadIdx.x+1;
  jl = threadIdx.y+1;
  ll = il+jl*(BLOCK_X+2);
 
 // What does the following line correspond to ?
  la[ll] = gpu_a[lg];
  if ((il == 1) && (ig > 0)) // What does the following line correespond to ?
    la[ll-1] = gpu_a[lg-1];
  if ((jl == 1) && (jg > 0))
    la[ll-BLOCK_X-2] = gpu_a[lg-pitch];
  if ((il == BLOCK_X) && (ig < n-1)) // UP TO YOU The following line is missing. Find out what was intended
    la[ll-BLOCK_X-2]= gpu_a[lg+pitch];
  if ((jl == BLOCK_Y) && (jg < n-1)) // UP TO YOU Find out the missing offset of local array below
    la[ll+BLOCK_X+2] = gpu_a[lg+pitch];
  __syncthreads ();
  if ((ig >= n) || (jg >= n)) return;
  if ((ig == 0) || (jg == 0) || (ig == n-1) || (jg == n-1))  {
    lb[ll] = la[ll];
  }
  else
    /* UP TO YOU : fill up below the missing indices */
    lb[ll]=(1.f/5.f)*(                +la[ll-BLOCK_X-2]+	     \
		      la[ll-1]        +la[ll]             +la[ll+1]+ \
		                      +la[ll+BLOCK_X+2]);
if((ig<n) &&(ig>0))  
gpu_b[lg] = lb[ll];
}

extern "C" void gpu_convol (float *a, float *b, int n) {
  float *gpu_a;
  float *gpu_b;
  cudaError_t err;
  size_t pitch;
  float time;
  err = cudaMallocPitch (&gpu_a, &pitch, n*sizeof(float), n);
  if (err != 0) {
    printf ("Error allocating gpu_a: %s\n", cudaGetErrorString (err));
    exit (1);
  }
  err = cudaMallocPitch (&gpu_b, &pitch, n*sizeof(float), n);
  if (err != 0) {
    printf ("Error allocating gpu_b: %s\n", cudaGetErrorString (err));
    exit (1);
  }
  dim3 block (BLOCK_X, BLOCK_Y);
  dim3 grid;
  grid.x = (n-1)/BLOCK_X+1;
  grid.y = (n-1)/BLOCK_Y+1;
  cudaMemcpy2D (gpu_a, pitch, a, n*sizeof(float), n*sizeof(float), n, cudaMemcpyHostToDevice);
  chrono (START, &time);
  kconvol <<<grid, block>>> (gpu_a, gpu_b, pitch/sizeof(float), n);
  err=cudaThreadSynchronize ();
  chrono (STOP, &time);
  printf ("Convolution took  %f sec. on GPU\n", time);
  cudaMemcpy2D (b, n*sizeof(float), gpu_b, pitch, n*sizeof(float), n, cudaMemcpyDeviceToHost);
  
  if (err != 0) {
    printf ("%s\n", cudaGetErrorString (err));
    exit (1);
  }
  cudaFree (gpu_a);
  cudaFree (gpu_b);
}

	.file	"tmpxft_003a18d0_00000000-6_convol.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z7kconvolPfS_iiPfS_ii
	.type	_Z30__device_stub__Z7kconvolPfS_iiPfS_ii, @function
_Z30__device_stub__Z7kconvolPfS_iiPfS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7kconvolPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z30__device_stub__Z7kconvolPfS_iiPfS_ii, .-_Z30__device_stub__Z7kconvolPfS_iiPfS_ii
	.globl	_Z7kconvolPfS_ii
	.type	_Z7kconvolPfS_ii, @function
_Z7kconvolPfS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7kconvolPfS_iiPfS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z7kconvolPfS_ii, .-_Z7kconvolPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Error allocating gpu_a: %s\n"
.LC1:
	.string	"Error allocating gpu_b: %s\n"
.LC2:
	.string	"Convolution took  %f sec. on GPU\n"
.LC3:
	.string	"%s\n"
	.text
	.globl	gpu_convol
	.type	gpu_convol, @function
gpu_convol:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movslq	%edx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	0(,%rbp,4), %rbx
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %r15
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	call	cudaMallocPitch@PLT
	testl	%eax, %eax
	je	.L9
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdx
	jmp	.L15
.L9:
	leaq	16(%rsp), %rdi
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	movq	%r15, %rsi
	call	cudaMallocPitch@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L10
	call	cudaGetErrorString@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdx
.L15:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L10:
	movabsq	$68719476752, %rax
	movl	$16, %ecx
	movq	%rbp, %r9
	movl	$1, 40(%rsp)
	movq	%rax, 32(%rsp)
	leal	-1(%rbp), %eax
	movq	%rbx, %r8
	cltd
	movl	$1, 52(%rsp)
	idivl	%ecx
	movq	%r14, %rdx
	movq	%rbx, %rcx
	incl	%eax
	movl	%eax, 44(%rsp)
	movl	%eax, 48(%rsp)
	pushq	%rsi
	.cfi_def_cfa_offset 136
	pushq	$1
	.cfi_def_cfa_offset 144
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	cudaMemcpy2D@PLT
	popq	%rdi
	.cfi_def_cfa_offset 136
	popq	%r8
	.cfi_def_cfa_offset 128
	movl	$1, %edi
	leaq	4(%rsp), %r14
	movq	%r14, %rsi
	call	chrono@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movq	32(%rsp), %rdx
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebp, %ecx
	movq	8(%rsp), %rdi
	shrq	$2, %rdx
	call	_Z30__device_stub__Z7kconvolPfS_iiPfS_ii
.L11:
	call	cudaThreadSynchronize@PLT
	movq	%r14, %rsi
	xorl	%edi, %edi
	movl	%eax, %r12d
	call	chrono@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %r9
	movq	%rbx, %r8
	pushq	%rax
	.cfi_def_cfa_offset 136
	movq	%rbx, %rsi
	movq	%r13, %rdi
	pushq	$2
	.cfi_def_cfa_offset 144
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	call	cudaMemcpy2D@PLT
	popq	%rdx
	.cfi_def_cfa_offset 136
	popq	%rcx
	.cfi_def_cfa_offset 128
	testl	%r12d, %r12d
	je	.L12
	movl	%r12d, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdx
	jmp	.L15
.L12:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	gpu_convol, .-gpu_convol
	.section	.rodata.str1.1
.LC4:
	.string	"_Z7kconvolPfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7kconvolPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <time.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define STOP 0
#define START 1

#define BLOCK_X 16
#define BLOCK_Y 16

extern "C" void chrono (int kind, float *time);

__global__ void kconvol (float *gpu_a, float *gpu_b, int pitch, int n) {
  int ig, jg, lg, il, jl, ll;
  __shared__ float la[(BLOCK_X+2)*(BLOCK_Y+2)];
  __shared__ float lb[(BLOCK_X+2)*(BLOCK_Y+2)];
 
 // A thread now has two sets of coordinates : 
  // (ig, jg) in the global array
  // (il, jl) in the local array (shared) of size (BLOCK_X+2)*(BLOCK_Y+2)
  ig = blockDim.x*blockIdx.x+threadIdx.x;
  jg = blockDim.y*blockIdx.y+threadIdx.y;
  lg = ig+jg*pitch;
  // UP TO YOU : write below the indices il and jl
  il = threadIdx.x+1;
  jl = threadIdx.y+1;
  ll = il+jl*(BLOCK_X+2);
 
 // What does the following line correspond to ?
  la[ll] = gpu_a[lg];
  if ((il == 1) && (ig > 0)) // What does the following line correespond to ?
    la[ll-1] = gpu_a[lg-1];
  if ((jl == 1) && (jg > 0))
    la[ll-BLOCK_X-2] = gpu_a[lg-pitch];
  if ((il == BLOCK_X) && (ig < n-1)) // UP TO YOU The following line is missing. Find out what was intended
    la[ll-BLOCK_X-2]= gpu_a[lg+pitch];
  if ((jl == BLOCK_Y) && (jg < n-1)) // UP TO YOU Find out the missing offset of local array below
    la[ll+BLOCK_X+2] = gpu_a[lg+pitch];
  __syncthreads ();
  if ((ig >= n) || (jg >= n)) return;
  if ((ig == 0) || (jg == 0) || (ig == n-1) || (jg == n-1))  {
    lb[ll] = la[ll];
  }
  else
    /* UP TO YOU : fill up below the missing indices */
    lb[ll]=(1.f/5.f)*(                +la[ll-BLOCK_X-2]+	     \
		      la[ll-1]        +la[ll]             +la[ll+1]+ \
		                      +la[ll+BLOCK_X+2]);
if((ig<n) &&(ig>0))  
gpu_b[lg] = lb[ll];
}

extern "C" void gpu_convol (float *a, float *b, int n) {
  float *gpu_a;
  float *gpu_b;
  hipError_t err;
  size_t pitch;
  float time;
  err = hipMallocPitch (&gpu_a, &pitch, n*sizeof(float), n);
  if (err != 0) {
    printf ("Error allocating gpu_a: %s\n", hipGetErrorString (err));
    exit (1);
  }
  err = hipMallocPitch (&gpu_b, &pitch, n*sizeof(float), n);
  if (err != 0) {
    printf ("Error allocating gpu_b: %s\n", hipGetErrorString (err));
    exit (1);
  }
  dim3 block (BLOCK_X, BLOCK_Y);
  dim3 grid;
  grid.x = (n-1)/BLOCK_X+1;
  grid.y = (n-1)/BLOCK_Y+1;
  hipMemcpy2D (gpu_a, pitch, a, n*sizeof(float), n*sizeof(float), n, hipMemcpyHostToDevice);
  chrono (START, &time);
  kconvol <<<grid, block>>> (gpu_a, gpu_b, pitch/sizeof(float), n);
  err=hipDeviceSynchronize ();
  chrono (STOP, &time);
  printf ("Convolution took  %f sec. on GPU\n", time);
  hipMemcpy2D (b, n*sizeof(float), gpu_b, pitch, n*sizeof(float), n, hipMemcpyDeviceToHost);
  
  if (err != 0) {
    printf ("%s\n", hipGetErrorString (err));
    exit (1);
  }
  hipFree (gpu_a);
  hipFree (gpu_b);
}

	.text
	.file	"convol.hip"
	.globl	_Z22__device_stub__kconvolPfS_ii # -- Begin function _Z22__device_stub__kconvolPfS_ii
	.type	_Z22__device_stub__kconvolPfS_ii,@function
_Z22__device_stub__kconvolPfS_ii:       # @_Z22__device_stub__kconvolPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7kconvolPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__kconvolPfS_ii, .Lfunc_end0-_Z22__device_stub__kconvolPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	gpu_convol                      # -- Begin function gpu_convol
	.type	gpu_convol,@function
gpu_convol:                             # @gpu_convol
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %r15
	movq	%rdi, %r12
	movslq	%edx, %rbx
	leaq	(,%rbx,4), %r14
	leaq	24(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	hipMallocPitch
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.1:
	leaq	16(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	hipMallocPitch
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.2:
	leal	-1(%rbx), %eax
	leal	14(%rbx), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$4, %ecx
	incl	%ecx
	movq	%rcx, %r13
	shlq	$32, %r13
	orq	%rcx, %r13
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1, (%rsp)
	movq	%r12, %rdx
	movq	%r14, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	callq	hipMemcpy2D
	leaq	36(%rsp), %rsi
	movl	$1, %edi
	callq	chrono
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r13, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	shrq	$2, %rdx
                                        # kill: def $edx killed $edx killed $rdx
	movl	%ebp, %ecx
	callq	_Z22__device_stub__kconvolPfS_ii
.LBB1_4:
	callq	hipDeviceSynchronize
	movl	%eax, %ebp
	leaq	36(%rsp), %r12
	xorl	%edi, %edi
	movq	%r12, %rsi
	callq	chrono
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	$2, (%rsp)
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%r14, %r8
	movq	%rbx, %r9
	callq	hipMemcpy2D
	testl	%ebp, %ebp
	jne	.LBB1_10
# %bb.5:
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_6:
	.cfi_def_cfa_offset 96
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	jmp	.LBB1_8
.LBB1_7:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
.LBB1_8:
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB1_9
.LBB1_10:
	movl	%ebp, %edi
	callq	hipGetErrorString
	movq	%rax, %rdi
	callq	puts@PLT
.LBB1_9:
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	gpu_convol, .Lfunc_end1-gpu_convol
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7kconvolPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7kconvolPfS_ii,@object        # @_Z7kconvolPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z7kconvolPfS_ii
	.p2align	3, 0x0
_Z7kconvolPfS_ii:
	.quad	_Z22__device_stub__kconvolPfS_ii
	.size	_Z7kconvolPfS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error allocating gpu_a: %s\n"
	.size	.L.str, 28

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Error allocating gpu_b: %s\n"
	.size	.L.str.1, 28

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Convolution took  %f sec. on GPU\n"
	.size	.L.str.2, 34

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7kconvolPfS_ii"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__kconvolPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7kconvolPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7kconvolPfS_ii        ; -- Begin function _Z7kconvolPfS_ii
	.globl	_Z7kconvolPfS_ii
	.p2align	8
	.type	_Z7kconvolPfS_ii,@function
_Z7kconvolPfS_ii:                       ; @_Z7kconvolPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v6, 0x3ff, v0
	v_bfe_u32 v9, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, s4, v[6:7]
	v_mad_u64_u32 v[3:4], null, s15, s5, v[9:10]
	s_load_b128 s[4:7], s[0:1], 0x0
	v_add_nc_u32_e32 v10, 1, v9
	v_cmp_eq_u32_e64 s0, 0, v6
	v_mul_u32_u24_e32 v11, 18, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, s2, v[2:3]
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 2, v[7:8]
	v_add_lshl_u32 v8, v11, v6, 2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 0, v2
	global_load_b32 v12, v[4:5], off
	s_and_b32 s1, s0, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v12 offset:4
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_2
; %bb.1:
	global_load_b32 v12, v[4:5], off offset:-4
	v_lshlrev_b32_e32 v11, 2, v11
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v12
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e64 s0, 0, v9
	v_cmp_lt_i32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_subrev_nc_u32_e32 v11, s2, v7
	v_add_nc_u32_e32 v9, 0xffffffbc, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, s4, v11
	v_add_co_ci_u32_e64 v12, s0, s5, v12, s0
	global_load_b32 v7, v[11:12], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v7
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s4, s3, -1
	v_cmp_eq_u32_e64 s0, 15, v6
	v_cmp_gt_i32_e64 s1, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_ashr_i32 s9, s2, 31
	s_mov_b32 s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
	v_add_co_u32 v6, s0, v4, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s9, v5, s0
	global_load_b32 v6, v[6:7], off
	v_add_nc_u32_e32 v7, 0xffffffbc, v8
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s0, 16, v10
	v_cmp_gt_i32_e64 s1, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_8
; %bb.7:
	s_ashr_i32 s9, s2, 31
	s_mov_b32 s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
	v_add_co_u32 v4, s0, v4, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v4 offset:76
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s1
	v_max_i32_e32 v4, v2, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_i32_e64 s3, v4
	s_cbranch_execz .LBB0_17
; %bb.9:
	v_cmp_eq_u32_e64 s0, 0, v2
	v_cmp_eq_u32_e64 s1, 0, v3
	s_mov_b32 s5, -1
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s1
	s_xor_b32 s0, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_13
; %bb.10:
	v_cmp_ne_u32_e64 s0, s4, v2
	v_cmp_ne_u32_e64 s1, s4, v3
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_add_nc_u32_e32 v2, 0xffffffbc, v8
	s_xor_b32 s5, exec_lo, -1
	ds_load_b32 v6, v2
	ds_load_2addr_b32 v[2:3], v8 offset1:1
	ds_load_2addr_b32 v[4:5], v8 offset0:2 offset1:19
	s_waitcnt lgkmcnt(1)
	v_add_f32_e32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v5
	v_mul_f32_e32 v4, 0x3e4ccccd, v2
.LBB0_12:                               ; %Flow93
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s1, s5, exec_lo
	s_or_b32 s2, s0, s1
.LBB0_13:                               ; %Flow92
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_15
; %bb.14:
	ds_load_b32 v4, v8 offset:4
.LBB0_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB0_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7kconvolPfS_ii
		.amdhsa_group_segment_fixed_size 1296
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7kconvolPfS_ii, .Lfunc_end0-_Z7kconvolPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 796
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1296 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1296
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7kconvolPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7kconvolPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
