#include "includes.h"
__global__ void HessianPositiveDefiniteKernel( char *d_hessian_pd, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[HES_BLOCKDIM_Z+2][HES_BLOCKDIM_Y+2][(HES_RESULT_STEPS + 2 * HES_HALO_STEPS) * HES_BLOCKDIM_X];

//Offset to the left halo edge
const int baseX = (blockIdx.x * HES_RESULT_STEPS - HES_HALO_STEPS) * HES_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * HES_BLOCKDIM_Y + threadIdx.y-1;
const int baseZ = blockIdx.z * HES_BLOCKDIM_Z + threadIdx.z-1;
const int idx = (baseZ * imageH + baseY) * imageW + baseX;

d_Src += idx;  d_hessian_pd += idx;

if(baseZ < 0 || baseZ >= imageD || baseY < 0 || baseY >= imageH) {
for (int i = 0; i < HES_HALO_STEPS + HES_RESULT_STEPS + HES_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = 0;
}
return;
}

//Load main data
#pragma unroll

for (int i = HES_HALO_STEPS; i < HES_HALO_STEPS + HES_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = (float)d_Src[i * HES_BLOCKDIM_X];
}

//Load left halo
#pragma unroll

for (int i = 0; i < HES_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = (baseX + i * HES_BLOCKDIM_X >= 0) ? (float)d_Src[i * HES_BLOCKDIM_X] : 0;
}

//Load right halo
#pragma unroll

for (int i = HES_HALO_STEPS + HES_RESULT_STEPS; i < HES_HALO_STEPS + HES_RESULT_STEPS + HES_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = (baseX + i * HES_BLOCKDIM_X < imageW) ? (float)d_Src[i * HES_BLOCKDIM_X] : 0;
}

// yz edge is no need to compute
if (threadIdx.z == 0 || threadIdx.z == HES_BLOCKDIM_Z+1 || threadIdx.y == 0 || threadIdx.y == HES_BLOCKDIM_Y+1)
return;

//Compute and store results
__syncthreads();
#pragma unroll

for (int i = HES_HALO_STEPS; i < HES_HALO_STEPS + HES_RESULT_STEPS; i++)
{
float xx,xy,xz,yy,yz,zz;
xx = s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X - 1]
+ s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X + 1]
- s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] * 2;
xy = s_Data[threadIdx.z][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X + 1]
+ s_Data[threadIdx.z][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X + 1];
xz = s_Data[threadIdx.z + 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X + 1]
+ s_Data[threadIdx.z - 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z + 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z - 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X + 1];
yy = s_Data[threadIdx.z][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X]
+ s_Data[threadIdx.z][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] * 2;
yz = s_Data[threadIdx.z + 1][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X]
+ s_Data[threadIdx.z - 1][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z + 1][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z - 1][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X];
zz = s_Data[threadIdx.z + 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X]
+ s_Data[threadIdx.z - 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] * 2;

xy *= 0.25; xz *= 0.25; yz *= 0.25;

d_hessian_pd[i * HES_BLOCKDIM_X] = (xx < 0 && xx*yy-xy*xy < 0 && xx*yy*zz + 2*xy*yz*xz - xx*yz*yz - yy*xz*xz - zz*xy*xy < 0) ? 1 : 0;
}
}
	.file	"tmpxft_0023ae43_00000000-6_HessianPositiveDefiniteKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z54__device_stub__Z29HessianPositiveDefiniteKernelPcPfiiiPcPfiii
	.type	_Z54__device_stub__Z29HessianPositiveDefiniteKernelPcPfiiiPcPfiii, @function
_Z54__device_stub__Z29HessianPositiveDefiniteKernelPcPfiiiPcPfiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z29HessianPositiveDefiniteKernelPcPfiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z54__device_stub__Z29HessianPositiveDefiniteKernelPcPfiiiPcPfiii, .-_Z54__device_stub__Z29HessianPositiveDefiniteKernelPcPfiiiPcPfiii
	.globl	_Z29HessianPositiveDefiniteKernelPcPfiii
	.type	_Z29HessianPositiveDefiniteKernelPcPfiii, @function
_Z29HessianPositiveDefiniteKernelPcPfiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z29HessianPositiveDefiniteKernelPcPfiiiPcPfiii
	.cfi_endproc
.LFE2033:
	.size	_Z29HessianPositiveDefiniteKernelPcPfiii, .-_Z29HessianPositiveDefiniteKernelPcPfiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z29HessianPositiveDefiniteKernelPcPfiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z29HessianPositiveDefiniteKernelPcPfiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void HessianPositiveDefiniteKernel( char *d_hessian_pd, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[HES_BLOCKDIM_Z+2][HES_BLOCKDIM_Y+2][(HES_RESULT_STEPS + 2 * HES_HALO_STEPS) * HES_BLOCKDIM_X];

//Offset to the left halo edge
const int baseX = (blockIdx.x * HES_RESULT_STEPS - HES_HALO_STEPS) * HES_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * HES_BLOCKDIM_Y + threadIdx.y-1;
const int baseZ = blockIdx.z * HES_BLOCKDIM_Z + threadIdx.z-1;
const int idx = (baseZ * imageH + baseY) * imageW + baseX;

d_Src += idx;  d_hessian_pd += idx;

if(baseZ < 0 || baseZ >= imageD || baseY < 0 || baseY >= imageH) {
for (int i = 0; i < HES_HALO_STEPS + HES_RESULT_STEPS + HES_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = 0;
}
return;
}

//Load main data
#pragma unroll

for (int i = HES_HALO_STEPS; i < HES_HALO_STEPS + HES_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = (float)d_Src[i * HES_BLOCKDIM_X];
}

//Load left halo
#pragma unroll

for (int i = 0; i < HES_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = (baseX + i * HES_BLOCKDIM_X >= 0) ? (float)d_Src[i * HES_BLOCKDIM_X] : 0;
}

//Load right halo
#pragma unroll

for (int i = HES_HALO_STEPS + HES_RESULT_STEPS; i < HES_HALO_STEPS + HES_RESULT_STEPS + HES_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] = (baseX + i * HES_BLOCKDIM_X < imageW) ? (float)d_Src[i * HES_BLOCKDIM_X] : 0;
}

// yz edge is no need to compute
if (threadIdx.z == 0 || threadIdx.z == HES_BLOCKDIM_Z+1 || threadIdx.y == 0 || threadIdx.y == HES_BLOCKDIM_Y+1)
return;

//Compute and store results
__syncthreads();
#pragma unroll

for (int i = HES_HALO_STEPS; i < HES_HALO_STEPS + HES_RESULT_STEPS; i++)
{
float xx,xy,xz,yy,yz,zz;
xx = s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X - 1]
+ s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X + 1]
- s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] * 2;
xy = s_Data[threadIdx.z][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X + 1]
+ s_Data[threadIdx.z][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X + 1];
xz = s_Data[threadIdx.z + 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X + 1]
+ s_Data[threadIdx.z - 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z + 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X - 1]
- s_Data[threadIdx.z - 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X + 1];
yy = s_Data[threadIdx.z][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X]
+ s_Data[threadIdx.z][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] * 2;
yz = s_Data[threadIdx.z + 1][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X]
+ s_Data[threadIdx.z - 1][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z + 1][threadIdx.y - 1][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z - 1][threadIdx.y + 1][threadIdx.x + i * HES_BLOCKDIM_X];
zz = s_Data[threadIdx.z + 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X]
+ s_Data[threadIdx.z - 1][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X]
- s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * HES_BLOCKDIM_X] * 2;

xy *= 0.25; xz *= 0.25; yz *= 0.25;

d_hessian_pd[i * HES_BLOCKDIM_X] = (xx < 0 && xx*yy-xy*xy < 0 && xx*yy*zz + 2*xy*yz*xz - xx*yz*yz - yy*xz*xz - zz*xy*xy < 0) ? 1 : 0;
}
}
	.text
	.file	"HessianPositiveDefiniteKernel.hip"
	.globl	_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii # -- Begin function _Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii
	.type	_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii,@function
_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii: # @_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29HessianPositiveDefiniteKernelPcPfiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii, .Lfunc_end0-_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29HessianPositiveDefiniteKernelPcPfiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z29HessianPositiveDefiniteKernelPcPfiii,@object # @_Z29HessianPositiveDefiniteKernelPcPfiii
	.section	.rodata,"a",@progbits
	.globl	_Z29HessianPositiveDefiniteKernelPcPfiii
	.p2align	3, 0x0
_Z29HessianPositiveDefiniteKernelPcPfiii:
	.quad	_Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii
	.size	_Z29HessianPositiveDefiniteKernelPcPfiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z29HessianPositiveDefiniteKernelPcPfiii"
	.size	.L__unnamed_1, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z44__device_stub__HessianPositiveDefiniteKernelPcPfiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z29HessianPositiveDefiniteKernelPcPfiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z29HessianPositiveDefiniteKernelPcPfiii ; -- Begin function _Z29HessianPositiveDefiniteKernelPcPfiii
	.globl	_Z29HessianPositiveDefiniteKernelPcPfiii
	.p2align	8
	.type	_Z29HessianPositiveDefiniteKernelPcPfiii,@function
_Z29HessianPositiveDefiniteKernelPcPfiii: ; @_Z29HessianPositiveDefiniteKernelPcPfiii
; %bb.0:
	v_bfe_u32 v5, v0, 20, 10
	s_lshl_b32 s2, s15, 2
	v_and_b32_e32 v6, 0x3ff, v0
	v_bfe_u32 v7, v0, 10, 10
	s_mov_b32 s5, -1
	v_add3_u32 v1, v5, s2, -1
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, 0, v1
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB0_55
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x10
	s_lshl_b32 s2, s14, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v7, s2, -1
	v_cmp_lt_i32_e64 s4, -1, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s10, v1
	v_cmp_gt_i32_e64 s3, s9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_b32 s3, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_54
; %bb.2:                                ; %.preheader101.preheader
	v_mad_u64_u32 v[2:3], null, v1, s9, v[0:1]
	s_lshl_b32 s3, s13, 7
	s_load_b128 s[4:7], s[0:1], 0x0
	v_add3_u32 v4, v6, s3, 0xffffffe0
	v_lshlrev_b32_e32 v8, 2, v6
	v_mul_u32_u24_e32 v9, 0x300, v7
	v_mul_u32_u24_e32 v10, 0x1200, v5
	s_mov_b32 s1, exec_lo
	v_mad_u64_u32 v[0:1], null, v2, s8, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v8, v10, v9, v8
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, s0, s6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	s_clause 0x7
	global_load_b32 v11, v[2:3], off offset:128
	global_load_b32 v12, v[2:3], off offset:192
	global_load_b32 v13, v[2:3], off offset:256
	global_load_b32 v14, v[2:3], off offset:320
	global_load_b32 v15, v[2:3], off offset:384
	global_load_b32 v16, v[2:3], off offset:448
	global_load_b32 v17, v[2:3], off offset:512
	global_load_b32 v18, v[2:3], off offset:576
	s_waitcnt vmcnt(6)
	ds_store_2addr_b32 v8, v11, v12 offset0:32 offset1:48
	s_waitcnt vmcnt(4)
	ds_store_2addr_b32 v8, v13, v14 offset0:64 offset1:80
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v8, v15, v16 offset0:96 offset1:112
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v8, v17, v18 offset0:128 offset1:144
	v_cmpx_lt_i32_e32 -1, v4
	s_cbranch_execz .LBB0_4
; %bb.3:
	global_load_b32 v10, v[2:3], off
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v10
	v_cmpx_lt_i32_e32 0xffffffef, v4
	s_cbranch_execz .LBB0_6
; %bb.5:
	global_load_b32 v9, v[2:3], off offset:64
.LBB0_6:                                ; %.preheader.preheader
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v10, 0xa0, v4
	v_mov_b32_e32 v16, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v9 offset:64
	v_cmp_gt_i32_e64 s0, s8, v10
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_8
; %bb.7:
	global_load_b32 v10, v[2:3], off offset:640
.LBB0_8:                                ; %.preheader.1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v4, 0xb0, v4
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v10 offset:640
	v_cmpx_gt_i32_e64 s8, v4
	s_cbranch_execz .LBB0_10
; %bb.9:
	global_load_b32 v16, v[2:3], off offset:704
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v15, 0x80, v8
	v_add_nc_u32_e32 v14, 0xc0, v8
	v_add_nc_u32_e32 v13, 0x100, v8
	v_add_nc_u32_e32 v12, 0x140, v8
	v_add_nc_u32_e32 v11, 0x180, v8
	v_add_nc_u32_e32 v10, 0x1c0, v8
	v_add_nc_u32_e32 v9, 0x200, v8
	v_add_nc_u32_e32 v4, 0x240, v8
	s_mov_b32 s3, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v16 offset:704
	v_cmpx_lt_i32_e32 4, v5
	s_xor_b32 s1, exec_lo, s1
; %bb.11:                               ; %LeafBlock227
	v_cmp_ne_u32_e64 s0, 5, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, s0, exec_lo
; %bb.12:                               ; %Flow245
	s_and_not1_saveexec_b32 s1, s1
; %bb.13:                               ; %LeafBlock
	v_cmp_ne_u32_e64 s0, 0, v5
	s_and_not1_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s3, s3, s0
; %bb.14:                               ; %Flow246
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB0_53
; %bb.15:                               ; %NodeBlock233
	s_mov_b32 s3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_lt_i32_e32 4, v7
	s_xor_b32 s6, exec_lo, s6
; %bb.16:                               ; %LeafBlock231
	v_cmp_ne_u32_e64 s0, 5, v7
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, s0, exec_lo
; %bb.17:                               ; %Flow242
	s_and_not1_saveexec_b32 s6, s6
; %bb.18:                               ; %LeafBlock229
	v_cmp_ne_u32_e64 s0, 0, v7
	s_and_not1_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s3, s3, s0
; %bb.19:                               ; %Flow243
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_53
; %bb.20:
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v8 offset0:31 offset1:32
	ds_load_b32 v16, v8 offset:132
	s_mov_b32 s3, 0
	s_mov_b32 s7, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, -2.0, v3
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_24
; %bb.21:
	v_add_nc_u32_e32 v19, 0x7c, v8
	v_add_nc_u32_e32 v20, 0x84, v8
	s_mov_b32 s8, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v16, 0xfffffd00, v19
	v_add_nc_u32_e32 v21, 0xfffffd00, v20
	ds_load_b32 v23, v8 offset:900
	ds_load_2addr_b32 v[17:18], v16 offset1:1
	ds_load_b32 v16, v21
	ds_load_2addr_b32 v[21:22], v8 offset0:223 offset1:224
	s_waitcnt lgkmcnt(2)
	v_add_f32_e32 v23, v23, v17
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v17, v3, v3 :: v_dual_add_f32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v23, v21
	v_dual_sub_f32 v3, v3, v16 :: v_dual_sub_f32 v16, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v18, v2, v16
	v_fma_f32 v21, -v3, v3, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f32_e32 0, v21
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_add_nc_u32_e32 v21, 0x127c, v8
	v_add_nc_u32_e32 v22, 0xffffee00, v20
	v_add_nc_u32_e32 v15, 0xffffeb00, v15
	v_add_nc_u32_e32 v23, 0xf00, v8
	v_add_nc_u32_e32 v24, 0xffffee00, v19
	ds_load_2addr_b32 v[19:20], v21 offset1:1
	ds_load_b32 v25, v22
	ds_load_b32 v26, v8 offset:5504
	ds_load_b32 v15, v15
	ds_load_2addr_b32 v[21:22], v24 offset1:1
	ds_load_2addr_b32 v[23:24], v23 offset0:32 offset1:225
	s_waitcnt lgkmcnt(1)
	v_dual_add_f32 v15, v26, v15 :: v_dual_add_f32 v20, v20, v22
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v21, v24, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v15, v23
	v_sub_f32_e32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v21, v19
	v_add_f32_e32 v21, v3, v3
	v_dual_mul_f32 v18, v18, v17 :: v_dual_add_nc_u32 v27, 0xfffff180, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v19, v19, v25
	ds_load_b32 v27, v27
	v_mul_f32_e32 v19, 0x3e800000, v19
	v_mul_f32_e32 v16, v19, v16
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v15, v15, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, 0x3e800000, v15
	v_mul_f32_e32 v20, v21, v15
	v_mul_f32_e32 v2, v2, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v20
	v_fma_f32 v2, -v15, v2, v18
	v_mul_f32_e32 v15, v3, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v19, v16, v2
	v_fma_f32 v2, -v3, v15, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0, v2
	s_and_b32 s8, s0, exec_lo
.LBB0_23:                               ; %Flow241
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s7, s8, exec_lo
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s6
	ds_load_2addr_b32 v[2:3], v8 offset0:47 offset1:48
	ds_load_b32 v15, v8 offset:196
	v_add_co_u32 v0, s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v15
	v_cndmask_b32_e64 v15, 0, 1, s7
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v15, off offset:32
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_28
; %bb.25:
	v_add_nc_u32_e32 v18, 0xbc, v8
	v_add_nc_u32_e32 v19, 0xc4, v8
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v15, 0xfffffd00, v18
	v_add_nc_u32_e32 v20, 0xfffffd00, v19
	ds_load_b32 v22, v8 offset:964
	ds_load_2addr_b32 v[16:17], v15 offset1:1
	ds_load_b32 v15, v20
	ds_load_2addr_b32 v[20:21], v8 offset0:239 offset1:240
	s_waitcnt lgkmcnt(2)
	v_add_f32_e32 v22, v22, v16
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v16, v3, v3 :: v_dual_add_f32 v17, v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v22, v20
	v_sub_f32_e32 v3, v3, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v17, v16
	v_mul_f32_e32 v3, 0x3e800000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v2, v15
	v_fma_f32 v20, -v3, v3, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f32_e32 0, v20
	s_cbranch_execz .LBB0_27
; %bb.26:
	v_add_nc_u32_e32 v20, 0x12bc, v8
	v_add_nc_u32_e32 v21, 0xffffee00, v19
	v_add_nc_u32_e32 v14, 0xffffeb00, v14
	v_add_nc_u32_e32 v22, 0xf00, v8
	v_add_nc_u32_e32 v23, 0xffffee00, v18
	ds_load_2addr_b32 v[18:19], v20 offset1:1
	ds_load_b32 v24, v21
	ds_load_b32 v25, v8 offset:5568
	ds_load_b32 v14, v14
	ds_load_2addr_b32 v[20:21], v23 offset1:1
	ds_load_2addr_b32 v[22:23], v22 offset0:48 offset1:241
	s_waitcnt lgkmcnt(1)
	v_dual_add_f32 v14, v25, v14 :: v_dual_add_f32 v19, v19, v21
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v14, v22
	v_sub_f32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v20, v18
	v_dual_add_f32 v20, v3, v3 :: v_dual_mul_f32 v17, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v18, v24
	v_mul_f32_e32 v18, 0x3e800000, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, v18, v15 :: v_dual_add_nc_u32 v26, 0xfffff1c0, v8
	ds_load_b32 v26, v26
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v14, v14, v26
	v_mul_f32_e32 v14, 0x3e800000, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, v20, v14
	v_mul_f32_e32 v2, v2, v14
	v_fmac_f32_e32 v17, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v14, v2, v17
	v_mul_f32_e32 v14, v3, v16
	v_fma_f32 v2, -v18, v15, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v3, v14, v2
	v_cmp_gt_f32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s5, s0, exec_lo
.LBB0_27:                               ; %Flow240
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s5, exec_lo
.LBB0_28:
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_2addr_b32 v[2:3], v8 offset0:63 offset1:64
	ds_load_b32 v14, v8 offset:260
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v14
	v_cndmask_b32_e64 v14, 0, 1, s3
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v14, off offset:48
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_32
; %bb.29:
	v_add_nc_u32_e32 v17, 0xfc, v8
	v_add_nc_u32_e32 v18, 0x104, v8
	v_add_nc_u32_e32 v19, 0x3fc, v8
	s_mov_b32 s6, 0
	s_mov_b32 s5, exec_lo
	v_add_nc_u32_e32 v14, 0xfffffd00, v17
	ds_load_b32 v21, v8 offset:1028
	ds_load_2addr_b32 v[15:16], v14 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v21, v21, v15
	v_dual_add_f32 v15, v3, v3 :: v_dual_add_nc_u32 v14, 0xfffffd00, v18
	ds_load_2addr_b32 v[19:20], v19 offset1:1
	ds_load_b32 v14, v14
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v3, v21, v19 :: v_dual_add_f32 v16, v20, v16
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v3, v14 :: v_dual_sub_f32 v14, v16, v15
	v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v16, v2, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v3, v3, v16
	v_cmpx_gt_f32_e32 0, v19
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_add_nc_u32_e32 v19, 0x12fc, v8
	v_add_nc_u32_e32 v20, 0xffffee00, v18
	v_add_nc_u32_e32 v13, 0xffffeb00, v13
	v_add_nc_u32_e32 v21, 0x1000, v8
	v_add_nc_u32_e32 v22, 0xffffee00, v17
	ds_load_2addr_b32 v[17:18], v19 offset1:1
	ds_load_b32 v23, v20
	ds_load_b32 v24, v8 offset:5632
	ds_load_b32 v13, v13
	ds_load_2addr_b32 v[19:20], v22 offset1:1
	ds_load_2addr_b32 v[21:22], v21 offset1:193
	v_add_nc_u32_e32 v25, 0xfffff200, v8
	ds_load_b32 v25, v25
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v13, v24, v13 :: v_dual_add_f32 v18, v18, v20
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v21
	v_sub_f32_e32 v15, v18, v15
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v13, v13, v25 :: v_dual_mul_f32 v16, v16, v15
	v_add_f32_e32 v19, v22, v19
	v_mul_f32_e32 v13, 0x3e800000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v19, v17
	v_dual_add_f32 v19, v3, v3 :: v_dual_mul_f32 v2, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v17, v23 :: v_dual_mul_f32 v18, v19, v13
	v_mul_f32_e32 v17, 0x3e800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, v17, v18
	v_mul_f32_e32 v14, v17, v14
	v_fma_f32 v2, -v13, v2, v16
	v_mul_f32_e32 v13, v3, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v17, v14, v2
	v_fma_f32 v2, -v3, v13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0, v2
	s_and_b32 s6, s0, exec_lo
.LBB0_31:                               ; %Flow239
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s6, exec_lo
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_2addr_b32 v[2:3], v8 offset0:79 offset1:80
	ds_load_b32 v13, v8 offset:324
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v13
	v_cndmask_b32_e64 v13, 0, 1, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v13, off offset:64
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_36
; %bb.33:
	v_add_nc_u32_e32 v16, 0x13c, v8
	v_add_nc_u32_e32 v17, 0x144, v8
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v13, 0xfffffd00, v16
	ds_load_b32 v20, v8 offset:1092
	ds_load_2addr_b32 v[14:15], v13 offset1:1
	v_add_nc_u32_e32 v18, 0x43c, v8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v20, v20, v14
	v_dual_add_f32 v14, v3, v3 :: v_dual_add_nc_u32 v13, 0xfffffd00, v17
	ds_load_2addr_b32 v[18:19], v18 offset1:1
	ds_load_b32 v13, v13
	s_waitcnt lgkmcnt(1)
	v_add_f32_e32 v15, v19, v15
	v_sub_f32_e32 v3, v20, v18
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v13
	v_sub_f32_e32 v13, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x3e800000, v3
	v_mul_f32_e32 v15, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v3, v3, v15
	v_cmpx_gt_f32_e32 0, v18
	s_cbranch_execz .LBB0_35
; %bb.34:
	v_add_nc_u32_e32 v18, 0x133c, v8
	v_add_nc_u32_e32 v19, 0xffffee00, v17
	v_add_nc_u32_e32 v12, 0xffffeb00, v12
	v_add_nc_u32_e32 v20, 0x1000, v8
	v_add_nc_u32_e32 v21, 0xffffee00, v16
	ds_load_2addr_b32 v[16:17], v18 offset1:1
	ds_load_b32 v22, v19
	ds_load_b32 v23, v8 offset:5696
	ds_load_b32 v12, v12
	ds_load_2addr_b32 v[18:19], v21 offset1:1
	ds_load_2addr_b32 v[20:21], v20 offset0:16 offset1:209
	s_waitcnt lgkmcnt(1)
	v_dual_add_f32 v12, v23, v12 :: v_dual_add_f32 v17, v17, v19
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v18, v21, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v12, v20
	v_sub_f32_e32 v16, v18, v16
	v_add_f32_e32 v18, v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v16, v22
	v_mul_f32_e32 v16, 0x3e800000, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v13, v16, v13 :: v_dual_add_nc_u32 v24, 0xfffff240, v8
	ds_load_b32 v24, v24
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v12, v12, v24
	v_mul_f32_e32 v12, 0x3e800000, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v17, v14 :: v_dual_mul_f32 v17, v18, v12
	v_dual_mul_f32 v15, v15, v14 :: v_dual_mul_f32 v2, v2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v17
	v_fma_f32 v2, -v12, v2, v15
	v_mul_f32_e32 v12, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v16, v13, v2
	v_fma_f32 v2, -v3, v12, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0, v2
	s_and_b32 s5, s0, exec_lo
.LBB0_35:                               ; %Flow238
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s5, exec_lo
.LBB0_36:
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_2addr_b32 v[2:3], v8 offset0:95 offset1:96
	ds_load_b32 v12, v8 offset:388
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v12
	v_cndmask_b32_e64 v12, 0, 1, s3
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v12, off offset:80
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_40
; %bb.37:
	v_add_nc_u32_e32 v15, 0x17c, v8
	v_add_nc_u32_e32 v16, 0x184, v8
	s_mov_b32 s6, 0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 0xfffffd00, v15
	ds_load_b32 v19, v8 offset:1156
	ds_load_2addr_b32 v[13:14], v12 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v19, v19, v13
	v_add_f32_e32 v13, v3, v3
	v_add_nc_u32_e32 v17, 0x47c, v8
	v_add_nc_u32_e32 v12, 0xfffffd00, v16
	ds_load_2addr_b32 v[17:18], v17 offset1:1
	ds_load_b32 v12, v12
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v3, v19, v17 :: v_dual_add_f32 v14, v18, v14
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v3, v12 :: v_dual_sub_f32 v12, v14, v13
	v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v14, v2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v3, v3, v14
	v_cmpx_gt_f32_e32 0, v17
	s_cbranch_execz .LBB0_39
; %bb.38:
	v_add_nc_u32_e32 v17, 0x137c, v8
	v_add_nc_u32_e32 v18, 0xffffee00, v16
	v_add_nc_u32_e32 v11, 0xffffeb00, v11
	v_add_nc_u32_e32 v19, 0x1000, v8
	v_add_nc_u32_e32 v20, 0xffffee00, v15
	ds_load_2addr_b32 v[15:16], v17 offset1:1
	ds_load_b32 v21, v18
	ds_load_b32 v22, v8 offset:5760
	ds_load_b32 v11, v11
	ds_load_2addr_b32 v[17:18], v20 offset1:1
	ds_load_2addr_b32 v[19:20], v19 offset0:32 offset1:225
	s_waitcnt lgkmcnt(1)
	v_dual_add_f32 v11, v22, v11 :: v_dual_add_f32 v16, v16, v18
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v11, v19
	v_sub_f32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v17, v15
	v_add_f32_e32 v17, v3, v3
	v_dual_mul_f32 v14, v14, v13 :: v_dual_add_nc_u32 v23, 0xfffff280, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v21
	ds_load_b32 v23, v23
	v_mul_f32_e32 v15, 0x3e800000, v15
	v_mul_f32_e32 v12, v15, v12
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v11, v11, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x3e800000, v11
	v_mul_f32_e32 v16, v17, v11
	v_mul_f32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v15, v16
	v_fma_f32 v2, -v11, v2, v14
	v_mul_f32_e32 v11, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v15, v12, v2
	v_fma_f32 v2, -v3, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0, v2
	s_and_b32 s6, s0, exec_lo
.LBB0_39:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s6, exec_lo
.LBB0_40:
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_2addr_b32 v[2:3], v8 offset0:111 offset1:112
	ds_load_b32 v11, v8 offset:452
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v11
	v_cndmask_b32_e64 v11, 0, 1, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v11, off offset:96
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_44
; %bb.41:
	v_add_nc_u32_e32 v14, 0x1bc, v8
	v_add_nc_u32_e32 v15, 0x1c4, v8
	v_add_nc_u32_e32 v16, 0x4bc, v8
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	v_add_nc_u32_e32 v11, 0xfffffd00, v14
	ds_load_b32 v18, v8 offset:1220
	ds_load_2addr_b32 v[12:13], v11 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v18, v18, v12
	v_add_f32_e32 v12, v3, v3
	v_add_nc_u32_e32 v11, 0xfffffd00, v15
	ds_load_2addr_b32 v[16:17], v16 offset1:1
	ds_load_b32 v11, v11
	s_waitcnt lgkmcnt(1)
	v_sub_f32_e32 v3, v18, v16
	v_add_f32_e32 v13, v17, v13
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v11
	v_sub_f32_e32 v11, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x3e800000, v3
	v_mul_f32_e32 v13, v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v3, v3, v13
	v_cmpx_gt_f32_e32 0, v16
	s_cbranch_execz .LBB0_43
; %bb.42:
	v_add_nc_u32_e32 v16, 0x13bc, v8
	v_add_nc_u32_e32 v17, 0xffffee00, v15
	v_add_nc_u32_e32 v10, 0xffffeb00, v10
	v_add_nc_u32_e32 v18, 0x1000, v8
	v_add_nc_u32_e32 v19, 0xffffee00, v14
	ds_load_2addr_b32 v[14:15], v16 offset1:1
	ds_load_b32 v20, v17
	ds_load_b32 v21, v8 offset:5824
	ds_load_b32 v10, v10
	ds_load_2addr_b32 v[16:17], v19 offset1:1
	ds_load_2addr_b32 v[18:19], v18 offset0:48 offset1:241
	s_waitcnt lgkmcnt(1)
	v_dual_add_f32 v10, v21, v10 :: v_dual_add_f32 v15, v15, v17
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v10, v18
	v_sub_f32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v16, v14
	v_dual_add_f32 v16, v3, v3 :: v_dual_mul_f32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v20
	v_mul_f32_e32 v14, 0x3e800000, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v14, v11 :: v_dual_add_nc_u32 v22, 0xfffff2c0, v8
	ds_load_b32 v22, v22
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v10, v10, v22
	v_mul_f32_e32 v10, 0x3e800000, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v16, v10
	v_mul_f32_e32 v2, v2, v10
	v_fmac_f32_e32 v13, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v10, v2, v13
	v_mul_f32_e32 v10, v3, v12
	v_fma_f32 v2, -v14, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v3, v10, v2
	v_cmp_gt_f32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s5, s0, exec_lo
.LBB0_43:                               ; %Flow236
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s5, exec_lo
.LBB0_44:
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_2addr_b32 v[2:3], v8 offset0:127 offset1:128
	ds_load_b32 v10, v8 offset:516
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v10
	v_cndmask_b32_e64 v10, 0, 1, s3
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v10, off offset:112
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_48
; %bb.45:
	v_add_nc_u32_e32 v13, 0x1fc, v8
	v_add_nc_u32_e32 v14, 0x204, v8
	v_add_nc_u32_e32 v15, 0x4fc, v8
	s_mov_b32 s6, 0
	s_mov_b32 s5, exec_lo
	v_add_nc_u32_e32 v10, 0xfffffd00, v13
	ds_load_b32 v17, v8 offset:1284
	ds_load_2addr_b32 v[11:12], v10 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v17, v17, v11
	v_dual_add_f32 v11, v3, v3 :: v_dual_add_nc_u32 v10, 0xfffffd00, v14
	ds_load_2addr_b32 v[15:16], v15 offset1:1
	ds_load_b32 v10, v10
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v3, v17, v15 :: v_dual_add_f32 v12, v16, v12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v3, v10 :: v_dual_sub_f32 v10, v12, v11
	v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v12, v2, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, -v3, v3, v12
	v_cmpx_gt_f32_e32 0, v15
	s_cbranch_execz .LBB0_47
; %bb.46:
	v_add_nc_u32_e32 v15, 0x13fc, v8
	v_add_nc_u32_e32 v16, 0xffffee00, v14
	v_add_nc_u32_e32 v9, 0xffffeb00, v9
	v_add_nc_u32_e32 v17, 0x1100, v8
	v_add_nc_u32_e32 v18, 0xffffee00, v13
	ds_load_2addr_b32 v[13:14], v15 offset1:1
	ds_load_b32 v19, v16
	ds_load_b32 v20, v8 offset:5888
	ds_load_b32 v9, v9
	ds_load_2addr_b32 v[15:16], v18 offset1:1
	ds_load_2addr_b32 v[17:18], v17 offset1:193
	v_add_nc_u32_e32 v21, 0xfffff300, v8
	ds_load_b32 v21, v21
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v9, v20, v9 :: v_dual_add_f32 v14, v14, v16
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v17
	v_sub_f32_e32 v11, v14, v11
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v21 :: v_dual_mul_f32 v12, v12, v11
	v_add_f32_e32 v15, v18, v15
	v_mul_f32_e32 v9, 0x3e800000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v15, v13
	v_dual_add_f32 v15, v3, v3 :: v_dual_mul_f32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v13, v19 :: v_dual_mul_f32 v14, v15, v9
	v_mul_f32_e32 v13, 0x3e800000, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v13, v14
	v_mul_f32_e32 v10, v13, v10
	v_fma_f32 v2, -v9, v2, v12
	v_mul_f32_e32 v9, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v13, v10, v2
	v_fma_f32 v2, -v3, v9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0, v2
	s_and_b32 s6, s0, exec_lo
.LBB0_47:                               ; %Flow235
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s6, exec_lo
.LBB0_48:
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_2addr_b32 v[2:3], v8 offset0:143 offset1:144
	ds_load_b32 v9, v8 offset:580
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v9
	v_cndmask_b32_e64 v9, 0, 1, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, -2.0, v3
	global_store_b8 v[0:1], v9, off offset:128
	v_cmpx_gt_f32_e32 0, v2
	s_cbranch_execz .LBB0_52
; %bb.49:
	v_add_nc_u32_e32 v12, 0x23c, v8
	v_add_nc_u32_e32 v13, 0x244, v8
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 0xfffffd00, v12
	ds_load_b32 v16, v8 offset:1348
	ds_load_2addr_b32 v[10:11], v9 offset1:1
	v_add_nc_u32_e32 v14, 0x53c, v8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v16, v16, v10
	v_dual_add_f32 v10, v3, v3 :: v_dual_add_nc_u32 v9, 0xfffffd00, v13
	ds_load_2addr_b32 v[14:15], v14 offset1:1
	ds_load_b32 v9, v9
	s_waitcnt lgkmcnt(1)
	v_add_f32_e32 v11, v15, v11
	v_sub_f32_e32 v3, v16, v14
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v9
	v_sub_f32_e32 v9, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x3e800000, v3
	v_mul_f32_e32 v11, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v3, v3, v11
	v_cmpx_gt_f32_e32 0, v14
	s_cbranch_execz .LBB0_51
; %bb.50:
	v_add_nc_u32_e32 v14, 0x143c, v8
	v_add_nc_u32_e32 v15, 0xffffee00, v13
	v_add_nc_u32_e32 v4, 0xffffeb00, v4
	v_add_nc_u32_e32 v16, 0x1100, v8
	v_add_nc_u32_e32 v17, 0xffffee00, v12
	ds_load_2addr_b32 v[12:13], v14 offset1:1
	ds_load_b32 v18, v15
	ds_load_b32 v19, v8 offset:5952
	ds_load_b32 v4, v4
	ds_load_2addr_b32 v[14:15], v17 offset1:1
	ds_load_2addr_b32 v[16:17], v16 offset0:16 offset1:209
	v_add_nc_u32_e32 v8, 0xfffff340, v8
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v4, v19, v4 :: v_dual_add_f32 v13, v13, v15
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v16
	v_sub_f32_e32 v10, v13, v10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v8
	v_add_f32_e32 v8, v3, v3
	v_dual_mul_f32 v11, v11, v10 :: v_dual_mul_f32 v4, 0x3e800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, v8, v4
	v_add_f32_e32 v14, v17, v14
	v_mul_f32_e32 v2, v2, v4
	v_sub_f32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v18
	v_mul_f32_e32 v12, 0x3e800000, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v12, v8
	v_mul_f32_e32 v8, v12, v9
	v_fma_f32 v2, -v4, v2, v11
	v_mul_f32_e32 v4, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v12, v8, v2
	v_fma_f32 v2, -v3, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0, v2
	s_and_b32 s5, s0, exec_lo
.LBB0_51:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s5, exec_lo
.LBB0_52:                               ; %.loopexit.loopexit107
	s_or_b32 exec_lo, exec_lo, s4
	v_cndmask_b32_e64 v2, 0, 1, s3
	global_store_b8 v[0:1], v2, off offset:144
.LBB0_53:                               ; %Flow247
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, -1
.LBB0_54:                               ; %Flow250
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, vcc_lo, exec_lo
	s_and_b32 s1, s5, exec_lo
	s_or_b32 vcc_lo, s0, s1
.LBB0_55:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s12
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_58
; %bb.56:                               ; %.preheader
	v_mul_u32_u24_e32 v0, 0x1200, v5
	v_mul_u32_u24_e32 v1, 0x300, v7
	v_lshlrev_b32_e32 v2, 2, v6
	s_movk_i32 s0, 0xfd00
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, v2
	v_mov_b32_e32 v1, 0
.LBB0_57:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s0, v0
	s_add_i32 s0, s0, 64
	s_cmp_eq_u32 s0, 0
	ds_store_b32 v2, v1 offset:768
	s_cbranch_scc0 .LBB0_57
.LBB0_58:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29HessianPositiveDefiniteKernelPcPfiii
		.amdhsa_group_segment_fixed_size 27648
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z29HessianPositiveDefiniteKernelPcPfiii, .Lfunc_end0-_Z29HessianPositiveDefiniteKernelPcPfiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4860
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 27648 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 27648
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z29HessianPositiveDefiniteKernelPcPfiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z29HessianPositiveDefiniteKernelPcPfiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
