/* The code is described in this paper: Ouyang M, Sorting sixteen
 * numbers.  Proceedings of IEEE High Performance Extreme Computing
 * Conference (HPEC), 2015, 1-6.
 *
 * Copyright (c) 2015 Ming Ouyang
 *
 * Permission is hereby granted, free of charge, to any person
 * obtaining a copy of this software and associated documentation
 * files (the "Software"), to deal in the Software without
 * restriction, including without limitation the rights to use, copy,
 * modify, merge, publish, distribute, sublicense, and/or sell copies
 * of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be
 * included in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>

#define NoOP      0xFFFFFFFFu
#define TwoTo16   0x00010000u
#define BlockSize 256

#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))

int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;

void initGPU(void) {
  cudaSetDevice(deviceNum);
  cudaMalloc((void**) &gpuData, sizeof(int) * dataSize);
}

void init(int argc, char *argv[]) {
  unsigned i, j, k, tmp;
  int c;

  while ((c = getopt(argc, argv, "d:")) != -1)
    switch (c) {
    case 'd':
      sscanf(optarg, "%d", &deviceNum);
      break;
    default:
      break;
    }

  data   = (int*) malloc(sizeof(int) * dataSize);
  sorted = (int*) malloc(sizeof(int) * dataSize);

  j = 0;
  for (i = 0; i < TwoTo16; i++) {
    tmp = i;
    for (k = 0; k < 16; k++) {
      data[j++] = tmp & 0x00000001u;
      tmp = tmp >> 1;
    }
  }

  initGPU();
}

void verify(void) {
  unsigned i, j, k, count;

  count = 0;
  for (i = 0; i < TwoTo16; i++) {
    for (j = 0; j < 15; j++) {
      if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
	printf("not sorted %d:", i);

	for (k = 0; k < 16; k++)
	  printf(" %d", sorted[i * 16 + k]);
	printf("\n");

	if (count++ == 10)
	  exit(1);
      }
    }
  }
}

__device__ inline void IntComparator(int &A, int &B) {
  int t;

  if (A > B) {
    t = A;
    A = B;
    B = t;
  }
}

__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
  unsigned t;

  if (A > B) {
    t = A;
    A = B;
    B = t;
  }
}

//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
  __shared__ int sX[BlockSize * 2];
  unsigned pos, size, stride, offset;
  unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;

  sX[threadIdx.x] = X[base];
  sX[threadIdx.x + BlockSize] = X[base + BlockSize];
  __syncthreads();

#pragma unroll
  for (size = 2; size <= 16; size <<= 1) {
    stride = size >> 1;
    offset = threadIdx.x & (stride - 1);
    pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
    IntComparator(sX[pos], sX[pos + stride]);
    stride >>= 1;
    for (; stride > 0; stride >>= 1) {
      pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
      if (offset >= stride) //divergent computation
	IntComparator(sX[pos - stride], sX[pos]);
    }
  }
  __syncthreads();

  X[base] = sX[threadIdx.x];
  X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}

//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
  __shared__ int sX[BlockSize * 2];
  unsigned pos, size, stride, offset;
  unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;

  sX[threadIdx.x] = X[base];
  sX[threadIdx.x + BlockSize] = X[base + BlockSize];
  __syncthreads();

#pragma unroll
  for (size = 2; size <= 16; size <<= 1) {
    stride = size >> 1;
    offset = threadIdx.x & (stride - 1);
    pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
    IntComparator(sX[pos], sX[pos+stride]);
    stride >>= 1;
    for (; stride > 0; stride >>= 1) {
      pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
      //non-divergent computation
      IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
    }
  }
  __syncthreads();

  X[base] = sX[threadIdx.x];
  X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}

//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
  __shared__ int sX[BlockSize * 2];
  unsigned wire1, wire2, our16tuple;
  unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;

  sX[threadIdx.x] = X[base];
  sX[threadIdx.x + BlockSize] = X[base + BlockSize];
  our16tuple = (threadIdx.x >> 3) << 4;
  __syncthreads();

  //step I
  wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
  wire2 = wire1 + 1;
  IntComparator(sX[wire1], sX[wire2]);

  //step II
  wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
  wire2 = wire1 + 2;
  IntComparator(sX[wire1], sX[wire2]);

  //step III
  wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
  wire2 = wire1 + 4;
  IntComparator(sX[wire1], sX[wire2]);

  //step IV
  wire1 = (threadIdx.x & 7) + our16tuple;
  wire2 = wire1 + 8;
  IntComparator(sX[wire1], sX[wire2]);

  //step V
  wire1 = threadIdx.x & 7;
  wire1 = (wire1 == 2) ? 13 : wire1;
  wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
  wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
  wire1 += our16tuple;
  wire2 += our16tuple;
  IntComparator(sX[wire1], sX[wire2]);

  //step VI
  wire1 = threadIdx.x & 7;
  wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
  wire2 = (wire1 == 0) ? 15 : wire2;
  wire2 = (wire1 == 1) ? 4 : wire2;
  if (wire1 == 4){
    wire1 = wire1 ^ 15;
    wire2 = wire1 + 3;
  }
  wire1 += our16tuple;
  wire2 += our16tuple;
  IntComparator(sX[wire1], sX[wire2]);

  //step VII
  wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
  wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
    + our16tuple;
  UnsignedComparator(wire1, wire2);
  IntComparator(sX[wire1], sX[wire2]);

  //step VIII
  wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
  wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
  UnsignedComparator(wire1, wire2);
  IntComparator(sX[wire1], sX[wire2]);

  //step IX
  wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
  wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
  UnsignedComparator(wire1, wire2);
  IntComparator(sX[wire1], sX[wire2]);

  __syncthreads();
  X[base] = sX[threadIdx.x];
  X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}

int main(int argc, char *argv[]) {
  cudaEvent_t start;
  cudaEvent_t stop;
  float msec;

  init(argc, argv);
  cudaEventCreate(&start);
  cudaEventCreate(&stop);

  cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
  cudaEventRecord(start, NULL);
  nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
  cudaDeviceSynchronize();
  cudaEventRecord(stop, NULL);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&msec, start, stop);
  printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
	 BlockSize, deviceNum, msec);
  cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
  verify();

  cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
  cudaEventRecord(start, NULL);
  VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
  cudaDeviceSynchronize();
  cudaEventRecord(stop, NULL);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&msec, start, stop);
  printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
	 BlockSize, deviceNum, msec);
  cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
  verify();

  cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
  cudaEventRecord(start, NULL);
  newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
  cudaDeviceSynchronize();
  cudaEventRecord(stop, NULL);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&msec, start, stop);
  printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
	 BlockSize, deviceNum, msec);
  cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
  verify();

  return 0;
}

	.file	"tmpxft_00348c0c_00000000-6_sort16.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2048:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2048:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7initGPUv
	.type	_Z7initGPUv, @function
_Z7initGPUv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	deviceNum(%rip), %edi
	call	cudaSetDevice@PLT
	movslq	dataSize(%rip), %rsi
	popq	%rdx
	.cfi_def_cfa_offset 8
	leaq	gpuData(%rip), %rdi
	salq	$2, %rsi
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2040:
	.size	_Z7initGPUv, .-_Z7initGPUv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
.LC1:
	.string	"d:"
	.text
	.globl	_Z4initiPPc
	.type	_Z4initiPPc, @function
_Z4initiPPc:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC1(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%edi, %ebx
.L6:
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movl	%ebx, %edi
	call	getopt@PLT
	cmpl	$-1, %eax
	je	.L15
	cmpl	$100, %eax
	jne	.L6
	movq	optarg(%rip), %rdi
	leaq	deviceNum(%rip), %rdx
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	call	__isoc23_sscanf@PLT
	jmp	.L6
.L15:
	movslq	dataSize(%rip), %rbp
	salq	$2, %rbp
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, data(%rip)
	movq	%rax, %rbx
	call	malloc@PLT
	xorl	%edx, %edx
	xorl	%esi, %esi
	movq	%rax, sorted(%rip)
.L8:
	movl	%esi, %ecx
	leal	16(%rdx), %eax
.L9:
	movl	%ecx, %r8d
	movl	%edx, %edi
	incl	%edx
	shrl	%ecx
	andl	$1, %r8d
	movl	%r8d, (%rbx,%rdi,4)
	cmpl	%edx, %eax
	jne	.L9
	incl	%esi
	cmpl	$1048576, %eax
	je	.L10
	movl	%eax, %edx
	jmp	.L8
.L10:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z7initGPUv
	.cfi_endproc
.LFE2041:
	.size	_Z4initiPPc, .-_Z4initiPPc
	.section	.rodata.str1.1
.LC2:
	.string	"not sorted %d:"
.LC3:
	.string	" %d"
.LC4:
	.string	"\n"
	.text
	.globl	_Z6verifyv
	.type	_Z6verifyv, @function
_Z6verifyv:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
.L17:
	movq	%rbp, %r12
	movl	%ebp, 12(%rsp)
	salq	$6, %r12
	leaq	60(%r12), %r14
	movq	%r12, %rbx
.L20:
	movq	sorted(%rip), %rax
	movl	(%rax,%rbx), %edx
	addq	$4, %rbx
	cmpl	(%rax,%rbx), %edx
	jle	.L18
	movl	12(%rsp), %edx
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	xorl	%r15d, %r15d
	movl	$2, %edi
	call	__printf_chk@PLT
.L19:
	leaq	0(,%r15,4), %rax
	addq	sorted(%rip), %rax
	movl	$2, %edi
	incq	%r15
	movl	(%rax,%r12), %edx
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$16, %r15
	jne	.L19
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leal	1(%r13), %eax
	cmpl	$10, %r13d
	jne	.L22
	movl	$1, %edi
	call	exit@PLT
.L22:
	movl	%eax, %r13d
.L18:
	cmpq	%r14, %rbx
	jne	.L20
	incq	%rbp
	cmpq	$65536, %rbp
	jne	.L17
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z6verifyv, .-_Z6verifyv
	.globl	_Z33__device_stub__Z13nvidiaBatcherPiPi
	.type	_Z33__device_stub__Z13nvidiaBatcherPiPi, @function
_Z33__device_stub__Z13nvidiaBatcherPiPi:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z13nvidiaBatcherPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L26:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z33__device_stub__Z13nvidiaBatcherPiPi, .-_Z33__device_stub__Z13nvidiaBatcherPiPi
	.globl	_Z13nvidiaBatcherPi
	.type	_Z13nvidiaBatcherPi, @function
_Z13nvidiaBatcherPi:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z13nvidiaBatcherPiPi
	.cfi_endproc
.LFE2071:
	.size	_Z13nvidiaBatcherPi, .-_Z13nvidiaBatcherPi
	.globl	_Z30__device_stub__Z10newBatcherPiPi
	.type	_Z30__device_stub__Z10newBatcherPiPi, @function
_Z30__device_stub__Z10newBatcherPiPi:
.LFB2072:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10newBatcherPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L31:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2072:
	.size	_Z30__device_stub__Z10newBatcherPiPi, .-_Z30__device_stub__Z10newBatcherPiPi
	.globl	_Z10newBatcherPi
	.type	_Z10newBatcherPi, @function
_Z10newBatcherPi:
.LFB2073:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10newBatcherPiPi
	.cfi_endproc
.LFE2073:
	.size	_Z10newBatcherPi, .-_Z10newBatcherPi
	.globl	_Z30__device_stub__Z10VanVoorhisPiPi
	.type	_Z30__device_stub__Z10VanVoorhisPiPi, @function
_Z30__device_stub__Z10VanVoorhisPiPi:
.LFB2074:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10VanVoorhisPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L36:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2074:
	.size	_Z30__device_stub__Z10VanVoorhisPiPi, .-_Z30__device_stub__Z10VanVoorhisPiPi
	.globl	_Z10VanVoorhisPi
	.type	_Z10VanVoorhisPi, @function
_Z10VanVoorhisPi:
.LFB2075:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10VanVoorhisPiPi
	.cfi_endproc
.LFE2075:
	.size	_Z10VanVoorhisPi, .-_Z10VanVoorhisPi
	.section	.rodata.str1.1
.LC5:
	.string	"Nvd Batcher, blocksize %d, device %d, %.3f ms\n"
.LC6:
	.string	"Van Voorhis, blocksize %d, device %d, %.3f ms\n"
.LC7:
	.string	"new Batcher, blocksize %d, device %d, %.3f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2045:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	subq	$64, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Z4initiPPc
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movslq	dataSize(%rip), %rdx
	movl	$1, %ecx
	movq	data(%rip), %rsi
	movq	gpuData(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$512, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	dataSize(%rip), %eax
	movl	$16777217, %ecx
	movl	$1, 52(%rsp)
	salq	$8, %rcx
	cltd
	movq	%rcx, 44(%rsp)
	idivl	%esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	gpuData(%rip), %rdi
	call	_Z33__device_stub__Z13nvidiaBatcherPiPi
.L42:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	leaq	12(%rsp), %rbx
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	movl	deviceNum(%rip), %ecx
	movl	$256, %edx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	movslq	dataSize(%rip), %rdx
	movl	$2, %ecx
	movq	gpuData(%rip), %rsi
	movq	sorted(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	_Z6verifyv
	movslq	dataSize(%rip), %rdx
	movl	$1, %ecx
	movq	data(%rip), %rsi
	movq	gpuData(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$512, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	dataSize(%rip), %eax
	movl	$16777217, %ecx
	movl	$1, 52(%rsp)
	salq	$8, %rcx
	cltd
	movq	%rcx, 44(%rsp)
	idivl	%esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	gpuData(%rip), %rdi
	call	_Z30__device_stub__Z10VanVoorhisPiPi
.L43:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	movl	deviceNum(%rip), %ecx
	movl	$256, %edx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	movslq	dataSize(%rip), %rdx
	movl	$2, %ecx
	movq	gpuData(%rip), %rsi
	movq	sorted(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	_Z6verifyv
	movslq	dataSize(%rip), %rdx
	movl	$1, %ecx
	movq	data(%rip), %rsi
	movq	gpuData(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$512, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	dataSize(%rip), %eax
	movl	$16777217, %ecx
	movl	$1, 52(%rsp)
	salq	$8, %rcx
	cltd
	movq	%rcx, 44(%rsp)
	idivl	%esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movq	gpuData(%rip), %rdi
	call	_Z30__device_stub__Z10newBatcherPiPi
.L44:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	movl	deviceNum(%rip), %ecx
	movl	$256, %edx
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	movslq	dataSize(%rip), %rdx
	movl	$2, %ecx
	movq	gpuData(%rip), %rsi
	movq	sorted(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	_Z6verifyv
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z10VanVoorhisPi"
.LC9:
	.string	"_Z10newBatcherPi"
.LC10:
	.string	"_Z13nvidiaBatcherPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10VanVoorhisPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10newBatcherPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13nvidiaBatcherPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2077:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	gpuData
	.bss
	.align 8
	.type	gpuData, @object
	.size	gpuData, 8
gpuData:
	.zero	8
	.globl	sorted
	.align 8
	.type	sorted, @object
	.size	sorted, 8
sorted:
	.zero	8
	.globl	data
	.align 8
	.type	data, @object
	.size	data, 8
data:
	.zero	8
	.globl	dataSize
	.data
	.align 4
	.type	dataSize, @object
	.size	dataSize, 4
dataSize:
	.long	1048576
	.globl	deviceNum
	.bss
	.align 4
	.type	deviceNum, @object
	.size	deviceNum, 4
deviceNum:
	.zero	4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* The code is described in this paper: Ouyang M, Sorting sixteen
 * numbers.  Proceedings of IEEE High Performance Extreme Computing
 * Conference (HPEC), 2015, 1-6.
 *
 * Copyright (c) 2015 Ming Ouyang
 *
 * Permission is hereby granted, free of charge, to any person
 * obtaining a copy of this software and associated documentation
 * files (the "Software"), to deal in the Software without
 * restriction, including without limitation the rights to use, copy,
 * modify, merge, publish, distribute, sublicense, and/or sell copies
 * of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be
 * included in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>

#define NoOP      0xFFFFFFFFu
#define TwoTo16   0x00010000u
#define BlockSize 256

#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))

int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;

void initGPU(void) {
  hipSetDevice(deviceNum);
  hipMalloc((void**) &gpuData, sizeof(int) * dataSize);
}

void init(int argc, char *argv[]) {
  unsigned i, j, k, tmp;
  int c;

  while ((c = getopt(argc, argv, "d:")) != -1)
    switch (c) {
    case 'd':
      sscanf(optarg, "%d", &deviceNum);
      break;
    default:
      break;
    }

  data   = (int*) malloc(sizeof(int) * dataSize);
  sorted = (int*) malloc(sizeof(int) * dataSize);

  j = 0;
  for (i = 0; i < TwoTo16; i++) {
    tmp = i;
    for (k = 0; k < 16; k++) {
      data[j++] = tmp & 0x00000001u;
      tmp = tmp >> 1;
    }
  }

  initGPU();
}

void verify(void) {
  unsigned i, j, k, count;

  count = 0;
  for (i = 0; i < TwoTo16; i++) {
    for (j = 0; j < 15; j++) {
      if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
	printf("not sorted %d:", i);

	for (k = 0; k < 16; k++)
	  printf(" %d", sorted[i * 16 + k]);
	printf("\n");

	if (count++ == 10)
	  exit(1);
      }
    }
  }
}

__device__ inline void IntComparator(int &A, int &B) {
  int t;

  if (A > B) {
    t = A;
    A = B;
    B = t;
  }
}

__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
  unsigned t;

  if (A > B) {
    t = A;
    A = B;
    B = t;
  }
}

//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
  __shared__ int sX[BlockSize * 2];
  unsigned pos, size, stride, offset;
  unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;

  sX[threadIdx.x] = X[base];
  sX[threadIdx.x + BlockSize] = X[base + BlockSize];
  __syncthreads();

#pragma unroll
  for (size = 2; size <= 16; size <<= 1) {
    stride = size >> 1;
    offset = threadIdx.x & (stride - 1);
    pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
    IntComparator(sX[pos], sX[pos + stride]);
    stride >>= 1;
    for (; stride > 0; stride >>= 1) {
      pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
      if (offset >= stride) //divergent computation
	IntComparator(sX[pos - stride], sX[pos]);
    }
  }
  __syncthreads();

  X[base] = sX[threadIdx.x];
  X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}

//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
  __shared__ int sX[BlockSize * 2];
  unsigned pos, size, stride, offset;
  unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;

  sX[threadIdx.x] = X[base];
  sX[threadIdx.x + BlockSize] = X[base + BlockSize];
  __syncthreads();

#pragma unroll
  for (size = 2; size <= 16; size <<= 1) {
    stride = size >> 1;
    offset = threadIdx.x & (stride - 1);
    pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
    IntComparator(sX[pos], sX[pos+stride]);
    stride >>= 1;
    for (; stride > 0; stride >>= 1) {
      pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
      //non-divergent computation
      IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
    }
  }
  __syncthreads();

  X[base] = sX[threadIdx.x];
  X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}

//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
  __shared__ int sX[BlockSize * 2];
  unsigned wire1, wire2, our16tuple;
  unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;

  sX[threadIdx.x] = X[base];
  sX[threadIdx.x + BlockSize] = X[base + BlockSize];
  our16tuple = (threadIdx.x >> 3) << 4;
  __syncthreads();

  //step I
  wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
  wire2 = wire1 + 1;
  IntComparator(sX[wire1], sX[wire2]);

  //step II
  wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
  wire2 = wire1 + 2;
  IntComparator(sX[wire1], sX[wire2]);

  //step III
  wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
  wire2 = wire1 + 4;
  IntComparator(sX[wire1], sX[wire2]);

  //step IV
  wire1 = (threadIdx.x & 7) + our16tuple;
  wire2 = wire1 + 8;
  IntComparator(sX[wire1], sX[wire2]);

  //step V
  wire1 = threadIdx.x & 7;
  wire1 = (wire1 == 2) ? 13 : wire1;
  wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
  wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
  wire1 += our16tuple;
  wire2 += our16tuple;
  IntComparator(sX[wire1], sX[wire2]);

  //step VI
  wire1 = threadIdx.x & 7;
  wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
  wire2 = (wire1 == 0) ? 15 : wire2;
  wire2 = (wire1 == 1) ? 4 : wire2;
  if (wire1 == 4){
    wire1 = wire1 ^ 15;
    wire2 = wire1 + 3;
  }
  wire1 += our16tuple;
  wire2 += our16tuple;
  IntComparator(sX[wire1], sX[wire2]);

  //step VII
  wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
  wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
    + our16tuple;
  UnsignedComparator(wire1, wire2);
  IntComparator(sX[wire1], sX[wire2]);

  //step VIII
  wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
  wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
  UnsignedComparator(wire1, wire2);
  IntComparator(sX[wire1], sX[wire2]);

  //step IX
  wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
  wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
  UnsignedComparator(wire1, wire2);
  IntComparator(sX[wire1], sX[wire2]);

  __syncthreads();
  X[base] = sX[threadIdx.x];
  X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}

int main(int argc, char *argv[]) {
  hipEvent_t start;
  hipEvent_t stop;
  float msec;

  init(argc, argv);
  hipEventCreate(&start);
  hipEventCreate(&stop);

  hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
  hipEventRecord(start, NULL);
  nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
  hipDeviceSynchronize();
  hipEventRecord(stop, NULL);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&msec, start, stop);
  printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
	 BlockSize, deviceNum, msec);
  hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
  verify();

  hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
  hipEventRecord(start, NULL);
  VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
  hipDeviceSynchronize();
  hipEventRecord(stop, NULL);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&msec, start, stop);
  printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
	 BlockSize, deviceNum, msec);
  hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
  verify();

  hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
  hipEventRecord(start, NULL);
  newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
  hipDeviceSynchronize();
  hipEventRecord(stop, NULL);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&msec, start, stop);
  printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
	 BlockSize, deviceNum, msec);
  hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
  verify();

  return 0;
}

	.text
	.file	"sort16.hip"
	.globl	_Z7initGPUv                     # -- Begin function _Z7initGPUv
	.type	_Z7initGPUv,@function
_Z7initGPUv:                            # @_Z7initGPUv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	deviceNum(%rip), %edi
	callq	hipSetDevice
	movslq	dataSize(%rip), %rsi
	shlq	$2, %rsi
	movl	$gpuData, %edi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	hipMalloc                       # TAILCALL
.Lfunc_end0:
	.size	_Z7initGPUv, .Lfunc_end0-_Z7initGPUv
	.cfi_endproc
                                        # -- End function
	.globl	_Z4initiPPc                     # -- Begin function _Z4initiPPc
	.type	_Z4initiPPc,@function
_Z4initiPPc:                            # @_Z4initiPPc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edx
	movl	%ebp, %edi
	movq	%rbx, %rsi
	callq	getopt
	cmpl	$100, %eax
	je	.LBB1_8
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	cmpl	$-1, %eax
	jne	.LBB1_1
	jmp	.LBB1_3
.LBB1_8:                                #   in Loop: Header=BB1_1 Depth=1
	movq	optarg(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$deviceNum, %edx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	jmp	.LBB1_1
.LBB1_3:
	movslq	dataSize(%rip), %r14
	shlq	$2, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%rax, data(%rip)
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, sorted(%rip)
	xorl	%eax, %eax
.LBB1_4:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_5 Depth 2
	xorl	%ecx, %ecx
	movl	%eax, %edx
.LBB1_5:                                #   Parent Loop BB1_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%edx, %esi
	andl	$1, %esi
	movl	%esi, (%rbx,%rcx,4)
	shrl	%edx
	incq	%rcx
	cmpl	$16, %ecx
	jne	.LBB1_5
# %bb.6:                                #   in Loop: Header=BB1_4 Depth=1
	incl	%eax
	addq	$64, %rbx
	cmpl	$65536, %eax                    # imm = 0x10000
	jne	.LBB1_4
# %bb.7:
	movl	deviceNum(%rip), %edi
	callq	hipSetDevice
	movslq	dataSize(%rip), %rsi
	shlq	$2, %rsi
	movl	$gpuData, %edi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipMalloc                       # TAILCALL
.Lfunc_end1:
	.size	_Z4initiPPc, .Lfunc_end1-_Z4initiPPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z6verifyv                      # -- Begin function _Z6verifyv
	.type	_Z6verifyv,@function
_Z6verifyv:                             # @_Z6verifyv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	sorted(%rip), %rax
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	xorl	%ebp, %ebp
.LBB2_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
                                        #       Child Loop BB2_4 Depth 3
	movq	%rbx, %r15
	shlq	$4, %r15
	xorl	%r12d, %r12d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_4 Depth 3
	movq	%r12, %rcx
	orq	%r15, %rcx
	movl	(%rax,%rcx,4), %edx
	cmpl	4(%rax,%rcx,4), %edx
	jle	.LBB2_7
# %bb.3:                                #   in Loop: Header=BB2_2 Depth=2
	movl	$.L.str.2, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	xorl	%r13d, %r13d
.LBB2_4:                                #   Parent Loop BB2_1 Depth=1
                                        #     Parent Loop BB2_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	sorted(%rip), %rax
	addq	%r14, %rax
	movl	(%rax,%r13,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r13
	cmpq	$16, %r13
	jne	.LBB2_4
# %bb.5:                                #   in Loop: Header=BB2_2 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
	cmpl	$10, %ebp
	je	.LBB2_10
# %bb.6:                                #   in Loop: Header=BB2_2 Depth=2
	incl	%ebp
	movq	sorted(%rip), %rax
.LBB2_7:                                #   in Loop: Header=BB2_2 Depth=2
	incq	%r12
	cmpq	$15, %r12
	jne	.LBB2_2
# %bb.8:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%rbx
	addq	$64, %r14
	cmpq	$65536, %rbx                    # imm = 0x10000
	jne	.LBB2_1
# %bb.9:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_10:
	.cfi_def_cfa_offset 64
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z6verifyv, .Lfunc_end2-_Z6verifyv
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__nvidiaBatcherPi # -- Begin function _Z28__device_stub__nvidiaBatcherPi
	.type	_Z28__device_stub__nvidiaBatcherPi,@function
_Z28__device_stub__nvidiaBatcherPi:     # @_Z28__device_stub__nvidiaBatcherPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13nvidiaBatcherPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__nvidiaBatcherPi, .Lfunc_end3-_Z28__device_stub__nvidiaBatcherPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__newBatcherPi # -- Begin function _Z25__device_stub__newBatcherPi
	.type	_Z25__device_stub__newBatcherPi,@function
_Z25__device_stub__newBatcherPi:        # @_Z25__device_stub__newBatcherPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10newBatcherPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__newBatcherPi, .Lfunc_end4-_Z25__device_stub__newBatcherPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__VanVoorhisPi # -- Begin function _Z25__device_stub__VanVoorhisPi
	.type	_Z25__device_stub__VanVoorhisPi,@function
_Z25__device_stub__VanVoorhisPi:        # @_Z25__device_stub__VanVoorhisPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10VanVoorhisPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z25__device_stub__VanVoorhisPi, .Lfunc_end5-_Z25__device_stub__VanVoorhisPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294967296, %r15               # imm = 0x100000000
	callq	_Z4initiPPc
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	gpuData(%rip), %rdi
	movq	data(%rip), %rsi
	movslq	dataSize(%rip), %rdx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	dataSize(%rip), %eax
	leal	511(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$9, %edi
	btsq	$32, %rdi
	leaq	256(%r15), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	gpuData(%rip), %rdi
	callq	_Z28__device_stub__nvidiaBatcherPi
.LBB6_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	deviceNum(%rip), %edx
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.5, %edi
	movl	$256, %esi                      # imm = 0x100
	movb	$1, %al
	callq	printf
	movq	sorted(%rip), %rdi
	movq	gpuData(%rip), %rsi
	movslq	dataSize(%rip), %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	_Z6verifyv
	movq	gpuData(%rip), %rdi
	movq	data(%rip), %rsi
	movslq	dataSize(%rip), %rdx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	dataSize(%rip), %eax
	leal	511(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$9, %edi
	orq	%r15, %rdi
	leaq	256(%r15), %rbx
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_4
# %bb.3:
	movq	gpuData(%rip), %rdi
	callq	_Z25__device_stub__VanVoorhisPi
.LBB6_4:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	deviceNum(%rip), %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.6, %edi
	movl	$256, %esi                      # imm = 0x100
	movb	$1, %al
	callq	printf
	movq	sorted(%rip), %rdi
	movq	gpuData(%rip), %rsi
	movslq	dataSize(%rip), %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	_Z6verifyv
	movq	gpuData(%rip), %rdi
	movq	data(%rip), %rsi
	movslq	dataSize(%rip), %rdx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	dataSize(%rip), %eax
	leal	511(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$9, %edi
	orq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_6
# %bb.5:
	movq	gpuData(%rip), %rdi
	callq	_Z25__device_stub__newBatcherPi
.LBB6_6:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	deviceNum(%rip), %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.7, %edi
	movl	$256, %esi                      # imm = 0x100
	movb	$1, %al
	callq	printf
	movq	sorted(%rip), %rdi
	movq	gpuData(%rip), %rsi
	movslq	dataSize(%rip), %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	_Z6verifyv
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13nvidiaBatcherPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10newBatcherPi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10VanVoorhisPi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	deviceNum,@object               # @deviceNum
	.bss
	.globl	deviceNum
	.p2align	2, 0x0
deviceNum:
	.long	0                               # 0x0
	.size	deviceNum, 4

	.type	dataSize,@object                # @dataSize
	.data
	.globl	dataSize
	.p2align	2, 0x0
dataSize:
	.long	1048576                         # 0x100000
	.size	dataSize, 4

	.type	data,@object                    # @data
	.bss
	.globl	data
	.p2align	3, 0x0
data:
	.quad	0
	.size	data, 8

	.type	sorted,@object                  # @sorted
	.globl	sorted
	.p2align	3, 0x0
sorted:
	.quad	0
	.size	sorted, 8

	.type	gpuData,@object                 # @gpuData
	.globl	gpuData
	.p2align	3, 0x0
gpuData:
	.quad	0
	.size	gpuData, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"d:"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"not sorted %d:"
	.size	.L.str.2, 15

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" %d"
	.size	.L.str.3, 4

	.type	_Z13nvidiaBatcherPi,@object     # @_Z13nvidiaBatcherPi
	.section	.rodata,"a",@progbits
	.globl	_Z13nvidiaBatcherPi
	.p2align	3, 0x0
_Z13nvidiaBatcherPi:
	.quad	_Z28__device_stub__nvidiaBatcherPi
	.size	_Z13nvidiaBatcherPi, 8

	.type	_Z10newBatcherPi,@object        # @_Z10newBatcherPi
	.globl	_Z10newBatcherPi
	.p2align	3, 0x0
_Z10newBatcherPi:
	.quad	_Z25__device_stub__newBatcherPi
	.size	_Z10newBatcherPi, 8

	.type	_Z10VanVoorhisPi,@object        # @_Z10VanVoorhisPi
	.globl	_Z10VanVoorhisPi
	.p2align	3, 0x0
_Z10VanVoorhisPi:
	.quad	_Z25__device_stub__VanVoorhisPi
	.size	_Z10VanVoorhisPi, 8

	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	"Nvd Batcher, blocksize %d, device %d, %.3f ms\n"
	.size	.L.str.5, 47

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Van Voorhis, blocksize %d, device %d, %.3f ms\n"
	.size	.L.str.6, 47

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"new Batcher, blocksize %d, device %d, %.3f ms\n"
	.size	.L.str.7, 47

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13nvidiaBatcherPi"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10newBatcherPi"
	.size	.L__unnamed_2, 17

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10VanVoorhisPi"
	.size	.L__unnamed_3, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__nvidiaBatcherPi
	.addrsig_sym _Z25__device_stub__newBatcherPi
	.addrsig_sym _Z25__device_stub__VanVoorhisPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym deviceNum
	.addrsig_sym gpuData
	.addrsig_sym _Z13nvidiaBatcherPi
	.addrsig_sym _Z10newBatcherPi
	.addrsig_sym _Z10VanVoorhisPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13nvidiaBatcherPi     ; -- Begin function _Z13nvidiaBatcherPi
	.globl	_Z13nvidiaBatcherPi
	.p2align	8
	.type	_Z13nvidiaBatcherPi,@function
_Z13nvidiaBatcherPi:                    ; @_Z13nvidiaBatcherPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v1, s15, 9, v0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0x100, v1
	v_add_nc_u32_e32 v9, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	global_load_b32 v5, v[1:2], off
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v7, v5, v6 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[5:6], v9
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v11, v5
	ds_store_b64 v9, v[10:11]
.LBB0_2:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v8, 1, v0
	v_and_b32_e32 v10, 1, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v10
	v_lshlrev_b32_e32 v11, 2, v5
	ds_load_2addr_b32 v[5:6], v11 offset1:2
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB0_4
; %bb.3:
	ds_store_2addr_b32 v11, v6, v5 offset1:2
.LBB0_4:                                ; %.lr.ph.preheader.1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB0_7
; %bb.5:
	v_add_nc_u32_e32 v9, -4, v9
	ds_load_2addr_b32 v[5:6], v9 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v5, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.6:
	ds_store_2addr_b32 v9, v6, v5 offset1:1
.LBB0_7:                                ; %._crit_edge.1
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v9, 3, v0
	s_mov_b32 s0, 2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v9
	v_lshlrev_b32_e32 v10, 2, v5
	ds_load_2addr_b32 v[5:6], v10 offset1:4
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB0_9
; %bb.8:
	ds_store_2addr_b32 v10, v6, v5 offset1:4
.LBB0_9:                                ; %.lr.ph.2.preheader
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_10:                               ; %.lr.ph.2
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_le_u32_e64 s0, v9
	s_cbranch_execz .LBB0_13
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	s_add_i32 s2, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, s2, v0
	v_sub_nc_u32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s0, v6
	v_lshlrev_b32_e32 v6, 2, v6
	v_lshlrev_b32_e32 v5, 2, v5
	ds_load_b32 v10, v5
	ds_load_b32 v11, v6
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v10, v11
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_10 Depth=1
	ds_store_b32 v5, v11
	ds_store_b32 v6, v10
.LBB0_13:                               ; %_Z13IntComparatorRiS_.exit27.2
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_cbranch_scc1 .LBB0_10
; %bb.14:                               ; %._crit_edge.2
	v_and_b32_e32 v9, 7, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v9
	v_lshlrev_b32_e32 v10, 2, v5
	ds_load_2addr_b32 v[5:6], v10 offset1:8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB0_16
; %bb.15:
	ds_store_2addr_b32 v10, v6, v5 offset1:8
.LBB0_16:                               ; %.lr.ph.3.preheader
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 4
.LBB0_17:                               ; %.lr.ph.3
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_le_u32_e64 s0, v9
	s_cbranch_execz .LBB0_20
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	s_add_i32 s2, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, s2, v0
	v_sub_nc_u32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s0, v6
	v_lshlrev_b32_e32 v6, 2, v6
	v_lshlrev_b32_e32 v5, 2, v5
	ds_load_b32 v10, v5
	ds_load_b32 v11, v6
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v10, v11
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	ds_store_b32 v5, v11
	ds_store_b32 v6, v10
.LBB0_20:                               ; %_Z13IntComparatorRiS_.exit27.3
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_cbranch_scc1 .LBB0_17
; %bb.21:                               ; %._crit_edge.3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_stride64_b32 v[5:6], v7 offset1:4
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v[1:2], v5, off
	global_store_b32 v[3:4], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13nvidiaBatcherPi
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13nvidiaBatcherPi, .Lfunc_end0-_Z13nvidiaBatcherPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 720
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10newBatcherPi        ; -- Begin function _Z10newBatcherPi
	.globl	_Z10newBatcherPi
	.p2align	8
	.type	_Z10newBatcherPi,@function
_Z10newBatcherPi:                       ; @_Z10newBatcherPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v1, s15, 9, v0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0x100, v1
	v_add_nc_u32_e32 v9, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	global_load_b32 v5, v[1:2], off
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v7, v5, v6 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[5:6], v9
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v11, v5
	ds_store_b64 v9, v[10:11]
.LBB1_2:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v8, 1, v0
	v_and_b32_e32 v5, 1, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v5
	v_lshlrev_b32_e32 v10, 2, v5
	ds_load_2addr_b32 v[5:6], v10 offset1:2
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB1_4
; %bb.3:
	ds_store_2addr_b32 v10, v6, v5 offset1:2
.LBB1_4:                                ; %.lr.ph.preheader.1
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v5, v10
	ds_load_b32 v6, v9
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB1_6
; %bb.5:
	ds_store_b32 v10, v6
	ds_store_b32 v9, v5
.LBB1_6:                                ; %._crit_edge.1
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v9, 3, v0
	s_mov_b32 s0, 2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v9
	v_lshlrev_b32_e32 v10, 2, v5
	ds_load_2addr_b32 v[5:6], v10 offset1:4
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB1_8
; %bb.7:
	ds_store_2addr_b32 v10, v6, v5 offset1:4
.LBB1_8:                                ; %.lr.ph.2.preheader
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_9:                                ; %.lr.ph.2
                                        ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, -1
	v_cmp_le_u32_e32 vcc_lo, s0, v9
	v_and_b32_e32 v5, s1, v0
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e64 v6, 0, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v8, v5
	v_sub_nc_u32_e32 v5, v10, v6
	v_lshlrev_b32_e32 v6, 2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v5, 2, v5
	ds_load_b32 v10, v5
	ds_load_b32 v11, v6
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v10, v11
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=1
	ds_store_b32 v5, v11
	ds_store_b32 v6, v10
.LBB1_11:                               ; %_Z13IntComparatorRiS_.exit27.2
                                        ;   in Loop: Header=BB1_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_cbranch_scc1 .LBB1_9
; %bb.12:                               ; %._crit_edge.2
	v_and_b32_e32 v9, 7, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v9
	v_lshlrev_b32_e32 v10, 2, v5
	ds_load_2addr_b32 v[5:6], v10 offset1:8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB1_14
; %bb.13:
	ds_store_2addr_b32 v10, v6, v5 offset1:8
.LBB1_14:                               ; %.lr.ph.3.preheader
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 4
.LBB1_15:                               ; %.lr.ph.3
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_add_i32 s1, s0, -1
	v_cmp_le_u32_e32 vcc_lo, s0, v9
	v_and_b32_e32 v5, s1, v0
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e64 v6, 0, s0, vcc_lo
	v_sub_nc_u32_e32 v10, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v10, v6
	v_lshlrev_b32_e32 v6, 2, v10
	v_lshlrev_b32_e32 v5, 2, v5
	ds_load_b32 v10, v5
	ds_load_b32 v11, v6
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v10, v11
	s_cbranch_execz .LBB1_17
; %bb.16:                               ;   in Loop: Header=BB1_15 Depth=1
	ds_store_b32 v5, v11
	ds_store_b32 v6, v10
.LBB1_17:                               ; %_Z13IntComparatorRiS_.exit27.3
                                        ;   in Loop: Header=BB1_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_cbranch_scc1 .LBB1_15
; %bb.18:                               ; %._crit_edge.3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_stride64_b32 v[5:6], v7 offset1:4
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v[1:2], v5, off
	global_store_b32 v[3:4], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10newBatcherPi
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10newBatcherPi, .Lfunc_end1-_Z10newBatcherPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 716
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10VanVoorhisPi        ; -- Begin function _Z10VanVoorhisPi
	.globl	_Z10VanVoorhisPi
	.p2align	8
	.type	_Z10VanVoorhisPi,@function
_Z10VanVoorhisPi:                       ; @_Z10VanVoorhisPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v1, s15, 9, v0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0x100, v1
	v_add_nc_u32_e32 v8, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	global_load_b32 v5, v[1:2], off
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v7, v5, v6 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[5:6], v8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v5
	ds_store_b64 v8, v[9:10]
.LBB2_2:                                ; %_Z13IntComparatorRiS_.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v8, 1, v0
	v_and_b32_e32 v12, 1, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v9, 0x7f0, v8
	v_and_or_b32 v10, v8, 12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v11, v10, v9
	v_lshlrev_b32_e32 v13, 2, v11
	ds_load_2addr_b32 v[5:6], v13 offset1:2
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB2_4
; %bb.3:
	ds_store_2addr_b32 v13, v6, v5 offset1:2
.LBB2_4:                                ; %_Z13IntComparatorRiS_.exit22
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v5, 8, v8
	v_and_b32_e32 v6, 3, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v5, v5, v6, v9
	v_lshlrev_b32_e32 v13, 2, v5
	ds_load_2addr_b32 v[5:6], v13 offset1:4
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB2_6
; %bb.5:
	ds_store_2addr_b32 v13, v6, v5 offset1:4
.LBB2_6:                                ; %_Z13IntComparatorRiS_.exit23
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v0, 7, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v9, v0
	v_lshlrev_b32_e32 v13, 2, v5
	ds_load_2addr_b32 v[5:6], v13 offset1:8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v5, v6
	s_cbranch_execz .LBB2_8
; %bb.7:
	ds_store_2addr_b32 v13, v6, v5 offset1:8
.LBB2_8:                                ; %_Z13IntComparatorRiS_.exit24
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_ne_u32_e32 vcc_lo, 2, v0
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e32 v5, 13, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 1, v5
	v_and_b32_e32 v6, 5, v6
	v_lshlrev_b32_e32 v13, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v6, v13, 10, v6
	v_xor_b32_e32 v13, 15, v6
	v_cmp_eq_u32_e32 vcc_lo, v5, v6
	v_or_b32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v13, vcc_lo
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v9
	v_lshlrev_b32_e32 v6, 2, v6
	ds_load_b32 v13, v5
	ds_load_b32 v14, v6
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v13, v14
	s_cbranch_execz .LBB2_10
; %bb.9:
	ds_store_b32 v5, v14
	ds_store_b32 v6, v13
.LBB2_10:                               ; %_Z13IntComparatorRiS_.exit25
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v5, 1, v0
	v_cmp_gt_u32_e32 vcc_lo, 4, v0
	v_cmp_ne_u32_e64 s0, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v12
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_lshlrev_b32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, 15, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v0
	v_cndmask_b32_e64 v6, v0, 11, vcc_lo
	v_cndmask_b32_e64 v0, 4, v5, s0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v5, v6, v9
	v_cndmask_b32_e64 v6, v0, 14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v0, 2, v5
	v_add_lshl_u32 v5, v6, v9, 2
	ds_load_b32 v6, v0
	ds_load_b32 v12, v5
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v6, v12
	s_cbranch_execz .LBB2_12
; %bb.11:
	ds_store_b32 v0, v12
	ds_store_b32 v5, v6
.LBB2_12:                               ; %_Z13IntComparatorRiS_.exit26
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v0, 4, v10
	v_or_b32_e32 v5, 2, v11
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v0, 13, v9
	v_min_u32_e32 v6, v5, v0
	v_max_u32_e32 v5, v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v0, 2, v6
	v_lshlrev_b32_e32 v5, 2, v5
	ds_load_b32 v6, v0
	ds_load_b32 v10, v5
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v6, v10
	s_cbranch_execz .LBB2_14
; %bb.13:
	ds_store_b32 v0, v10
	ds_store_b32 v5, v6
.LBB2_14:                               ; %_Z13IntComparatorRiS_.exit27
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v0, 4, v8
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v5, v0, 14, v9
	v_or_b32_e32 v0, 1, v8
	v_cmp_lt_u32_e32 vcc_lo, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v5, v0, vcc_lo
	v_dual_cndmask_b32 v10, v0, v5 :: v_dual_lshlrev_b32 v5, 2, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 2, v10
	ds_load_b32 v10, v5
	ds_load_b32 v11, v6
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v10, v11
	s_cbranch_execz .LBB2_16
; %bb.15:
	ds_store_b32 v5, v11
	ds_store_b32 v6, v10
.LBB2_16:                               ; %_Z13IntComparatorRiS_.exit29
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v5, 2, v8
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v5, v5, 14, v9
	v_cmp_lt_u32_e32 vcc_lo, v8, v5
	v_dual_cndmask_b32 v6, v5, v0 :: v_dual_cndmask_b32 v5, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v0, 2, v6
	v_lshlrev_b32_e32 v5, 2, v5
	ds_load_b32 v6, v0
	ds_load_b32 v8, v5
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v6, v8
	s_cbranch_execz .LBB2_18
; %bb.17:
	ds_store_b32 v0, v8
	ds_store_b32 v5, v6
.LBB2_18:                               ; %_Z13IntComparatorRiS_.exit31
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_stride64_b32 v[5:6], v7 offset1:4
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v[1:2], v5, off
	global_store_b32 v[3:4], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10VanVoorhisPi
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10VanVoorhisPi, .Lfunc_end2-_Z10VanVoorhisPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1028
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13nvidiaBatcherPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13nvidiaBatcherPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10newBatcherPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10newBatcherPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10VanVoorhisPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10VanVoorhisPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
