

#include <stdio.h> 
#include <stdlib.h> 
#include <stdint.h> 

// Experiment with 3 part scans. 


__global__ void silly_kernel(int n, int* in, int* out) {
  
  if (threadIdx.x == 0){ 
    int acc = 0; 
    
    for (int i = 0; i < n; ++i){ 
      acc += in[blockIdx.x * n + i]; 
      out[blockIdx.x * n + i] = acc; 
    }
  }
}


__global__ void mid_kernel(int n, int *in, int *out) { 
  
  if (threadIdx.x == 0){ 
    int acc = 0; 
    
    for (int i = 0; i < n; ++i){ 
      acc += in[(i+1)*32 - 1]; 
      out[i] = acc; 
    }
  }
}


__global__ void post_kernel(int n, int *imm, int *aux, int *out) { 
  
 
  if (threadIdx.x == 0){
    
    int val = aux[blockIdx.x-1]; 
    if (blockIdx.x == 0) val = 0; 
    
    for (int i = 0; i < n; ++i){ 
      
      out[blockIdx.x * n + i] = imm[blockIdx.x * n + i] + val; 
    }
  }
} 




#define ELT_PER_BLOCK 32
#define NUM_BLOCKS    32

#define SIZE (ELT_PER_BLOCK * NUM_BLOCKS)
int main(int argc, char **argv) {
 
  int *in = NULL; 
  int *out = NULL; 
  
  // debug 
  int *imm = NULL; 
  int *aux = NULL; 
  
  in = (int*)malloc(SIZE*sizeof(int)); 
  out = (int*)malloc(SIZE*sizeof(int)); 

  // debug 
  imm = (int*)malloc(SIZE*sizeof(int)); 
  aux = (int*)malloc(NUM_BLOCKS*sizeof(int)); 

  int *din = NULL; 
  
  int *imm1 = NULL; 
  int *aux1 = NULL; 

  int *dout = NULL;
  

  // Allocate all GPU Storage
  cudaMalloc((void**)&din,SIZE*sizeof(int)); 
  cudaMalloc((void**)&imm1,SIZE*sizeof(int)); 
  cudaMalloc((void**)&aux1,NUM_BLOCKS*sizeof(int));
  cudaMalloc((void**)&dout,SIZE*sizeof(int)); 

  // Generate some data 
  for (int i = 0; i < SIZE; i ++) { 
    in[i] = i+1;
  }
  
  
  cudaMemcpy(din,in,SIZE*sizeof(int),cudaMemcpyHostToDevice);

  // silly_kernel<<<1,1,0>>>(SIZE,din,dout); 

  silly_kernel<<<NUM_BLOCKS,ELT_PER_BLOCK,0>>>(ELT_PER_BLOCK,din,imm1);
  mid_kernel<<<1,NUM_BLOCKS,0>>>(ELT_PER_BLOCK,imm1,aux1); 
  post_kernel<<<NUM_BLOCKS,ELT_PER_BLOCK,0>>>(ELT_PER_BLOCK,imm1,aux1,dout); 
  
  cudaMemcpy(out,dout, SIZE*sizeof(int),cudaMemcpyDeviceToHost); 

  //debug 
  cudaMemcpy(imm,imm1, SIZE*sizeof(int),cudaMemcpyDeviceToHost); 
  cudaMemcpy(aux,aux1, NUM_BLOCKS*sizeof(int),cudaMemcpyDeviceToHost); 

  cudaFree(din);
  cudaFree(dout);
  cudaFree(aux1);
  cudaFree(imm1);
  
  for (int i = 0; i < SIZE; ++i) {
    printf("%d ", out[i]);
  }
  printf("\n---------------------------------------------------------------------------\n"); 


  for (int i = 0; i < NUM_BLOCKS; ++i) {
    printf("%d ", aux[i]);
  }
  printf("\n---------------------------------------------------------------------------\n"); 

  for (int i = 0; i < SIZE; ++i) {
    printf("%d ", imm[i]);
  }
  printf("\n---------------------------------------------------------------------------\n"); 

  
  

  return 0;
} 

	.file	"tmpxft_00384f31_00000000-6_scan.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z12silly_kerneliPiS_iPiS_
	.type	_Z35__device_stub__Z12silly_kerneliPiS_iPiS_, @function
_Z35__device_stub__Z12silly_kerneliPiS_iPiS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12silly_kerneliPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z35__device_stub__Z12silly_kerneliPiS_iPiS_, .-_Z35__device_stub__Z12silly_kerneliPiS_iPiS_
	.globl	_Z12silly_kerneliPiS_
	.type	_Z12silly_kerneliPiS_, @function
_Z12silly_kerneliPiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z12silly_kerneliPiS_iPiS_
	.cfi_endproc
.LFE2053:
	.size	_Z12silly_kerneliPiS_, .-_Z12silly_kerneliPiS_
	.globl	_Z33__device_stub__Z10mid_kerneliPiS_iPiS_
	.type	_Z33__device_stub__Z10mid_kerneliPiS_iPiS_, @function
_Z33__device_stub__Z10mid_kerneliPiS_iPiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10mid_kerneliPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z33__device_stub__Z10mid_kerneliPiS_iPiS_, .-_Z33__device_stub__Z10mid_kerneliPiS_iPiS_
	.globl	_Z10mid_kerneliPiS_
	.type	_Z10mid_kerneliPiS_, @function
_Z10mid_kerneliPiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10mid_kerneliPiS_iPiS_
	.cfi_endproc
.LFE2055:
	.size	_Z10mid_kerneliPiS_, .-_Z10mid_kerneliPiS_
	.globl	_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_
	.type	_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_, @function
_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11post_kerneliPiS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_, .-_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_
	.globl	_Z11post_kerneliPiS_S_
	.type	_Z11post_kerneliPiS_S_, @function
_Z11post_kerneliPiS_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_
	.cfi_endproc
.LFE2057:
	.size	_Z11post_kerneliPiS_S_, .-_Z11post_kerneliPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
.LC1:
	.string	"\n---------------------------------------------------------------------------\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$4096, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$128, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rsp, %rdi
	movl	$4096, %esi
	movq	%rax, %r12
	xorl	%eax, %eax
	movq	%rax, (%rsp)
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$128, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$1, %eax
.L19:
	movl	%eax, -4(%rbx,%rax,4)
	incq	%rax
	cmpq	$1025, %rax
	jne	.L19
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$4096, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	8(%rsp), %rdx
	movq	(%rsp), %rsi
	movl	$32, %edi
	call	_Z35__device_stub__Z12silly_kerneliPiS_iPiS_
.L20:
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 52(%rsp)
	movq	%rdx, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$32, %edi
	call	_Z33__device_stub__Z10mid_kerneliPiS_iPiS_
.L21:
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdi
	movl	$1, %esi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$32, %edi
	movq	8(%rsp), %rsi
	call	_Z36__device_stub__Z11post_kerneliPiS_S_iPiS_S_
.L22:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	xorl	%ebx, %ebx
	movl	$4096, %edx
	leaq	.LC0(%rip), %r13
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$128, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
.L23:
	movl	(%r14,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$1024, %rbx
	jne	.L23
	leaq	.LC1(%rip), %r14
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	movq	%r14, %rsi
	call	__printf_chk@PLT
.L24:
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$32, %rbx
	jne	.L24
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
.L25:
	movl	0(%rbp,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$1024, %rbx
	jne	.L25
	xorl	%eax, %eax
	movq	%r14, %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z11post_kerneliPiS_S_"
.LC3:
	.string	"_Z10mid_kerneliPiS_"
.LC4:
	.string	"_Z12silly_kerneliPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11post_kerneliPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10mid_kerneliPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12silly_kerneliPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:




#include <hip/hip_runtime.h>
#include <stdio.h> 
#include <stdlib.h> 
#include <stdint.h> 

// Experiment with 3 part scans. 


__global__ void silly_kernel(int n, int* in, int* out) {
  
  if (threadIdx.x == 0){ 
    int acc = 0; 
    
    for (int i = 0; i < n; ++i){ 
      acc += in[blockIdx.x * n + i]; 
      out[blockIdx.x * n + i] = acc; 
    }
  }
}


__global__ void mid_kernel(int n, int *in, int *out) { 
  
  if (threadIdx.x == 0){ 
    int acc = 0; 
    
    for (int i = 0; i < n; ++i){ 
      acc += in[(i+1)*32 - 1]; 
      out[i] = acc; 
    }
  }
}


__global__ void post_kernel(int n, int *imm, int *aux, int *out) { 
  
 
  if (threadIdx.x == 0){
    
    int val = aux[blockIdx.x-1]; 
    if (blockIdx.x == 0) val = 0; 
    
    for (int i = 0; i < n; ++i){ 
      
      out[blockIdx.x * n + i] = imm[blockIdx.x * n + i] + val; 
    }
  }
} 




#define ELT_PER_BLOCK 32
#define NUM_BLOCKS    32

#define SIZE (ELT_PER_BLOCK * NUM_BLOCKS)
int main(int argc, char **argv) {
 
  int *in = NULL; 
  int *out = NULL; 
  
  // debug 
  int *imm = NULL; 
  int *aux = NULL; 
  
  in = (int*)malloc(SIZE*sizeof(int)); 
  out = (int*)malloc(SIZE*sizeof(int)); 

  // debug 
  imm = (int*)malloc(SIZE*sizeof(int)); 
  aux = (int*)malloc(NUM_BLOCKS*sizeof(int)); 

  int *din = NULL; 
  
  int *imm1 = NULL; 
  int *aux1 = NULL; 

  int *dout = NULL;
  

  // Allocate all GPU Storage
  hipMalloc((void**)&din,SIZE*sizeof(int)); 
  hipMalloc((void**)&imm1,SIZE*sizeof(int)); 
  hipMalloc((void**)&aux1,NUM_BLOCKS*sizeof(int));
  hipMalloc((void**)&dout,SIZE*sizeof(int)); 

  // Generate some data 
  for (int i = 0; i < SIZE; i ++) { 
    in[i] = i+1;
  }
  
  
  hipMemcpy(din,in,SIZE*sizeof(int),hipMemcpyHostToDevice);

  // silly_kernel<<<1,1,0>>>(SIZE,din,dout); 

  silly_kernel<<<NUM_BLOCKS,ELT_PER_BLOCK,0>>>(ELT_PER_BLOCK,din,imm1);
  mid_kernel<<<1,NUM_BLOCKS,0>>>(ELT_PER_BLOCK,imm1,aux1); 
  post_kernel<<<NUM_BLOCKS,ELT_PER_BLOCK,0>>>(ELT_PER_BLOCK,imm1,aux1,dout); 
  
  hipMemcpy(out,dout, SIZE*sizeof(int),hipMemcpyDeviceToHost); 

  //debug 
  hipMemcpy(imm,imm1, SIZE*sizeof(int),hipMemcpyDeviceToHost); 
  hipMemcpy(aux,aux1, NUM_BLOCKS*sizeof(int),hipMemcpyDeviceToHost); 

  hipFree(din);
  hipFree(dout);
  hipFree(aux1);
  hipFree(imm1);
  
  for (int i = 0; i < SIZE; ++i) {
    printf("%d ", out[i]);
  }
  printf("\n---------------------------------------------------------------------------\n"); 


  for (int i = 0; i < NUM_BLOCKS; ++i) {
    printf("%d ", aux[i]);
  }
  printf("\n---------------------------------------------------------------------------\n"); 

  for (int i = 0; i < SIZE; ++i) {
    printf("%d ", imm[i]);
  }
  printf("\n---------------------------------------------------------------------------\n"); 

  
  

  return 0;
} 

	.text
	.file	"scan.hip"
	.globl	_Z27__device_stub__silly_kerneliPiS_ # -- Begin function _Z27__device_stub__silly_kerneliPiS_
	.type	_Z27__device_stub__silly_kerneliPiS_,@function
_Z27__device_stub__silly_kerneliPiS_:   # @_Z27__device_stub__silly_kerneliPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12silly_kerneliPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__silly_kerneliPiS_, .Lfunc_end0-_Z27__device_stub__silly_kerneliPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__mid_kerneliPiS_ # -- Begin function _Z25__device_stub__mid_kerneliPiS_
	.type	_Z25__device_stub__mid_kerneliPiS_,@function
_Z25__device_stub__mid_kerneliPiS_:     # @_Z25__device_stub__mid_kerneliPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10mid_kerneliPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__mid_kerneliPiS_, .Lfunc_end1-_Z25__device_stub__mid_kerneliPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__post_kerneliPiS_S_ # -- Begin function _Z26__device_stub__post_kerneliPiS_S_
	.type	_Z26__device_stub__post_kerneliPiS_S_,@function
_Z26__device_stub__post_kerneliPiS_S_:  # @_Z26__device_stub__post_kerneliPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11post_kerneliPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__post_kerneliPiS_S_, .Lfunc_end2-_Z26__device_stub__post_kerneliPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r12
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r15
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %rbx
	movl	$128, %edi
	callq	malloc
	movq	%rax, %r14
	xorl	%ebp, %ebp
	leaq	32(%rsp), %rdi
	movq	%rbp, (%rdi)
	leaq	16(%rsp), %r13
	movq	%rbp, (%r13)
	leaq	8(%rsp), %rax
	movq	%rbp, (%rax)
	leaq	24(%rsp), %rax
	movq	%rbp, (%rax)
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r13, %rdi
	callq	hipMalloc
	movl	$128, %esi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movl	$4096, %esi                     # imm = 0x1000
	leaq	24(%rsp), %rdi
	callq	hipMalloc
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%rbp), %rax
	movl	%eax, (%r12,%rbp,4)
	movq	%rax, %rbp
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB3_1
# %bb.2:
	movabsq	$4294967328, %r13               # imm = 0x100000020
	movq	32(%rsp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$32, %edi
	callq	_Z27__device_stub__silly_kerneliPiS_
.LBB3_4:
	leaq	-31(%r13), %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$32, %edi
	callq	_Z25__device_stub__mid_kerneliPiS_
.LBB3_6:
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	$32, %edi
	callq	_Z26__device_stub__post_kerneliPiS_S_
.LBB3_8:
	movq	24(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$128, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%r12d, %r12d
.LBB3_9:                                # =>This Inner Loop Header: Depth=1
	movl	(%r15,%r12,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r12
	cmpq	$1024, %r12                     # imm = 0x400
	jne	.LBB3_9
# %bb.10:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%r15d, %r15d
.LBB3_11:                               # =>This Inner Loop Header: Depth=1
	movl	(%r14,%r15,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$32, %r15
	jne	.LBB3_11
# %bb.12:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB3_13:                               # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB3_13
# %bb.14:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12silly_kerneliPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10mid_kerneliPiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11post_kerneliPiS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12silly_kerneliPiS_,@object   # @_Z12silly_kerneliPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z12silly_kerneliPiS_
	.p2align	3, 0x0
_Z12silly_kerneliPiS_:
	.quad	_Z27__device_stub__silly_kerneliPiS_
	.size	_Z12silly_kerneliPiS_, 8

	.type	_Z10mid_kerneliPiS_,@object     # @_Z10mid_kerneliPiS_
	.globl	_Z10mid_kerneliPiS_
	.p2align	3, 0x0
_Z10mid_kerneliPiS_:
	.quad	_Z25__device_stub__mid_kerneliPiS_
	.size	_Z10mid_kerneliPiS_, 8

	.type	_Z11post_kerneliPiS_S_,@object  # @_Z11post_kerneliPiS_S_
	.globl	_Z11post_kerneliPiS_S_
	.p2align	3, 0x0
_Z11post_kerneliPiS_S_:
	.quad	_Z26__device_stub__post_kerneliPiS_S_
	.size	_Z11post_kerneliPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d "
	.size	.L.str, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12silly_kerneliPiS_"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10mid_kerneliPiS_"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11post_kerneliPiS_S_"
	.size	.L__unnamed_3, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr.2,@object                 # @str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
	.asciz	"\n---------------------------------------------------------------------------"
	.size	.Lstr.2, 77

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__silly_kerneliPiS_
	.addrsig_sym _Z25__device_stub__mid_kerneliPiS_
	.addrsig_sym _Z26__device_stub__post_kerneliPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12silly_kerneliPiS_
	.addrsig_sym _Z10mid_kerneliPiS_
	.addrsig_sym _Z11post_kerneliPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12silly_kerneliPiS_   ; -- Begin function _Z12silly_kerneliPiS_
	.globl	_Z12silly_kerneliPiS_
	.p2align	8
	.type	_Z12silly_kerneliPiS_,@function
_Z12silly_kerneliPiS_:                  ; @_Z12silly_kerneliPiS_
; %bb.0:
	s_load_b32 s6, s[0:1], 0x0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b128 s[0:3], s[0:1], 0x8
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
	s_mul_i32 s4, s15, s6
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[4:5], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s10, s0, s8
	s_addc_u32 s11, s1, s9
	s_add_u32 s8, s2, s8
	global_load_b32 v2, v0, s[10:11]
	s_addc_u32 s9, s3, s9
	s_add_i32 s6, s6, -1
	s_add_i32 s4, s4, 1
	s_cmp_lg_u32 s6, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12silly_kerneliPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12silly_kerneliPiS_, .Lfunc_end0-_Z12silly_kerneliPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10mid_kerneliPiS_     ; -- Begin function _Z10mid_kerneliPiS_
	.globl	_Z10mid_kerneliPiS_
	.p2align	8
	.type	_Z10mid_kerneliPiS_,@function
_Z10mid_kerneliPiS_:                    ; @_Z10mid_kerneliPiS_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.preheader
	s_load_b32 s4, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b128 s[0:3], s[0:1], 0x8
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, 0x7c
	s_addc_u32 s1, s1, 0
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v2, v0, s[0:1]
	s_add_i32 s4, s4, -1
	s_add_u32 s0, s0, 0x80
	s_addc_u32 s1, s1, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[2:3]
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s4, 0
	s_cbranch_scc1 .LBB1_3
.LBB1_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10mid_kerneliPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 5
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10mid_kerneliPiS_, .Lfunc_end1-_Z10mid_kerneliPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 5
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 5
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11post_kerneliPiS_S_  ; -- Begin function _Z11post_kerneliPiS_S_
	.globl	_Z11post_kerneliPiS_S_
	.p2align	8
	.type	_Z11post_kerneliPiS_S_,@function
_Z11post_kerneliPiS_S_:                 ; @_Z11post_kerneliPiS_S_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_load_b32 s8, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB2_4
; %bb.2:                                ; %.lr.ph
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_i32 s2, s15, -1
	s_mov_b32 s3, 0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_lshl_b64 s[10:11], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_cmp_lg_u32 s15, 0
	s_load_b32 s2, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s6, s2, 0
	s_mul_i32 s2, s15, s8
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[2:3], 2
	s_add_u32 s12, s4, s10
	s_addc_u32 s13, s5, s11
	s_add_u32 s10, s0, s10
	global_load_b32 v1, v0, s[12:13]
	s_addc_u32 s11, s1, s11
	s_add_i32 s8, s8, -1
	s_add_i32 s2, s2, 1
	s_cmp_lg_u32 s8, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, s6, v1
	global_store_b32 v0, v1, s[10:11]
	s_cbranch_scc1 .LBB2_3
.LBB2_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11post_kerneliPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11post_kerneliPiS_S_, .Lfunc_end2-_Z11post_kerneliPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12silly_kerneliPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12silly_kerneliPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10mid_kerneliPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     5
    .sgpr_spill_count: 0
    .symbol:         _Z10mid_kerneliPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11post_kerneliPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z11post_kerneliPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
