#include "includes.h"
__global__ void convolution_backward_kernel(float *y_h, float *filters, float *vbias, float *target, float *y_v, int input_size, int lu_padding, int channel_num, int feature_map_size, int filter_num, int filter_size, float *rnd_array, int rnd_num){
int imgIdx = blockIdx.y / (input_size / 16);
int channelIdx = blockIdx.x / (input_size / 16);
int tx = (blockIdx.x % (input_size / 16)) * 16 + threadIdx.x;
int ty = (blockIdx.y % (input_size / 16)) * 16 + threadIdx.y;
int padding = (filter_size - 1);

int rnd_index = ((blockIdx.y * blockDim.y + threadIdx.y) * (blockIdx.x * blockDim.x)  + threadIdx.x ) % rnd_num;
float rnd = rnd_array[rnd_index];

__shared__ float shHidden[16+2*(MAX_FILETER_SIZE-1)][16+2*(MAX_FILETER_SIZE-1)];
__shared__ float shFlipFilter[MAX_FILETER_SIZE][MAX_FILETER_SIZE];
float local_target = 0.0f;

target = target + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;

float *target_y_v = y_v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;

__syncthreads();


for(int f = 0; f < filter_num; f++){
float *cur_y_h = y_h + imgIdx * filter_num * feature_map_size * feature_map_size +
f * feature_map_size * feature_map_size;

float *cur_filter = filters + f * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;

if(threadIdx.x < filter_size && threadIdx.y < filter_size){
shFlipFilter[threadIdx.y][threadIdx.x] =
cur_filter[(filter_size-1-threadIdx.y)*filter_size + filter_size-1-threadIdx.x];
}

float *shHiddenLoad = &shHidden[threadIdx.y][threadIdx.x];
if(tx < padding || ty < padding){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty-padding) * input_size +
(tx-padding)];
}

if(threadIdx.x < 2 * padding){
shHiddenLoad = &shHidden[threadIdx.y][threadIdx.x+16];
if(ty < padding || (tx+16) >= (feature_map_size+padding)){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty-padding) * feature_map_size +
(tx+16-padding)];
}
}

if(threadIdx.y < 2 * padding){
shHiddenLoad = &shHidden[threadIdx.y+16][threadIdx.x];
if(tx < padding || (ty+16) >= (feature_map_size+padding)){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty+16-padding) * feature_map_size +
(tx-padding)];
}

if(threadIdx.x < 2 * padding){
shHiddenLoad = &shHidden[threadIdx.y+16][threadIdx.x+16];
if((ty+16) >= (feature_map_size+padding) ||
(tx+16) >= (feature_map_size+padding)){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty+16-padding) * feature_map_size +
(tx+16-padding)];
}
}
}

__syncthreads();

for(int i = 0; i < filter_size; i++){
for(int j = 0; j < filter_size; j++){
target[ty*input_size+tx] +=
local_target +=
shHidden[threadIdx.y+i+lu_padding][threadIdx.x+j+lu_padding] *
shFlipFilter[i][j];
}
}

__syncthreads();
}
local_target += vbias[channelIdx];
//local_target = expf(-local_target);
//local_target = __fdividef(1.0f , (1.0f + local_target));
if(rnd < local_target){
target_y_v[ty*input_size+tx] = 1;
}else{
target_y_v[ty*input_size+tx] = 0;
}
target[ty*input_size+tx] = local_target;
}
	.file	"tmpxft_0032d786_00000000-6_convolution_backward_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z64__device_stub__Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_iPfS_S_S_S_iiiiiiS_i
	.type	_Z64__device_stub__Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_iPfS_S_S_S_iiiiiiS_i, @function
_Z64__device_stub__Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_iPfS_S_S_S_iiiiiiS_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	296(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 272
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z64__device_stub__Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_iPfS_S_S_S_iiiiiiS_i, .-_Z64__device_stub__Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_iPfS_S_S_S_iiiiiiS_i
	.globl	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.type	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, @function
_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_iPfS_S_S_S_iiiiiiS_i
	.cfi_endproc
.LFE2033:
	.size	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, .-_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_backward_kernel(float *y_h, float *filters, float *vbias, float *target, float *y_v, int input_size, int lu_padding, int channel_num, int feature_map_size, int filter_num, int filter_size, float *rnd_array, int rnd_num){
int imgIdx = blockIdx.y / (input_size / 16);
int channelIdx = blockIdx.x / (input_size / 16);
int tx = (blockIdx.x % (input_size / 16)) * 16 + threadIdx.x;
int ty = (blockIdx.y % (input_size / 16)) * 16 + threadIdx.y;
int padding = (filter_size - 1);

int rnd_index = ((blockIdx.y * blockDim.y + threadIdx.y) * (blockIdx.x * blockDim.x)  + threadIdx.x ) % rnd_num;
float rnd = rnd_array[rnd_index];

__shared__ float shHidden[16+2*(MAX_FILETER_SIZE-1)][16+2*(MAX_FILETER_SIZE-1)];
__shared__ float shFlipFilter[MAX_FILETER_SIZE][MAX_FILETER_SIZE];
float local_target = 0.0f;

target = target + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;

float *target_y_v = y_v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;

__syncthreads();


for(int f = 0; f < filter_num; f++){
float *cur_y_h = y_h + imgIdx * filter_num * feature_map_size * feature_map_size +
f * feature_map_size * feature_map_size;

float *cur_filter = filters + f * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;

if(threadIdx.x < filter_size && threadIdx.y < filter_size){
shFlipFilter[threadIdx.y][threadIdx.x] =
cur_filter[(filter_size-1-threadIdx.y)*filter_size + filter_size-1-threadIdx.x];
}

float *shHiddenLoad = &shHidden[threadIdx.y][threadIdx.x];
if(tx < padding || ty < padding){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty-padding) * input_size +
(tx-padding)];
}

if(threadIdx.x < 2 * padding){
shHiddenLoad = &shHidden[threadIdx.y][threadIdx.x+16];
if(ty < padding || (tx+16) >= (feature_map_size+padding)){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty-padding) * feature_map_size +
(tx+16-padding)];
}
}

if(threadIdx.y < 2 * padding){
shHiddenLoad = &shHidden[threadIdx.y+16][threadIdx.x];
if(tx < padding || (ty+16) >= (feature_map_size+padding)){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty+16-padding) * feature_map_size +
(tx-padding)];
}

if(threadIdx.x < 2 * padding){
shHiddenLoad = &shHidden[threadIdx.y+16][threadIdx.x+16];
if((ty+16) >= (feature_map_size+padding) ||
(tx+16) >= (feature_map_size+padding)){
*shHiddenLoad = 0;
}else{
*shHiddenLoad = cur_y_h[(ty+16-padding) * feature_map_size +
(tx+16-padding)];
}
}
}

__syncthreads();

for(int i = 0; i < filter_size; i++){
for(int j = 0; j < filter_size; j++){
target[ty*input_size+tx] +=
local_target +=
shHidden[threadIdx.y+i+lu_padding][threadIdx.x+j+lu_padding] *
shFlipFilter[i][j];
}
}

__syncthreads();
}
local_target += vbias[channelIdx];
//local_target = expf(-local_target);
//local_target = __fdividef(1.0f , (1.0f + local_target));
if(rnd < local_target){
target_y_v[ty*input_size+tx] = 1;
}else{
target_y_v[ty*input_size+tx] = 0;
}
target[ty*input_size+tx] = local_target;
}
	.text
	.file	"convolution_backward_kernel.hip"
	.globl	_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i # -- Begin function _Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.type	_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i,@function
_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i: # @_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, .Lfunc_end0-_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i,@object # @_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.p2align	3, 0x0
_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i:
	.quad	_Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.size	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i"
	.size	.L__unnamed_1, 51

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z42__device_stub__convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i ; -- Begin function _Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.globl	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
	.p2align	8
	.type	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i,@function
_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i: ; @_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x28
	s_load_b32 s4, s[0:1], 0x48
	s_load_b32 s5, s[0:1], 0x5c
	v_bfe_u32 v3, v0, 10, 10
	s_mov_b32 s13, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s16, 31
	v_cvt_f32_u32_e32 v2, s4
	s_lshr_b32 s2, s2, 28
	s_mul_i32 s26, s16, s16
	s_add_i32 s2, s16, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 4
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s6, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v1
	v_rcp_iflag_f32_e32 v1, v2
	s_mul_i32 s6, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s2, s6
	s_add_i32 s2, s2, s6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_mul_hi_u32 s6, s15, s2
	s_mul_hi_u32 s10, s14, s2
	s_mul_i32 s7, s6, s3
	s_add_i32 s8, s6, 1
	s_sub_i32 s7, s15, s7
	v_cvt_u32_f32_e32 v7, v1
	s_sub_i32 s9, s7, s3
	s_cmp_ge_u32 s7, s3
	s_cselect_b32 s2, s8, s6
	s_cselect_b32 s6, s9, s7
	s_add_i32 s7, s2, 1
	s_cmp_ge_u32 s6, s3
	s_mul_i32 s6, s10, s3
	s_cselect_b32 s2, s7, s2
	s_sub_i32 s6, s14, s6
	s_add_i32 s7, s10, 1
	s_sub_i32 s8, s6, s3
	s_cmp_ge_u32 s6, s3
	s_cselect_b32 s7, s7, s10
	s_cselect_b32 s6, s8, s6
	s_add_i32 s8, s7, 1
	s_cmp_ge_u32 s6, s3
	s_cselect_b32 s12, s8, s7
	s_sub_i32 s6, 0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_lo_u32 v5, s6, v7
	s_lshr_b32 s6, s5, 16
	s_and_b32 s5, s5, 0xffff
	v_mad_u64_u32 v[1:2], null, s15, s6, v[3:4]
	v_and_b32_e32 v4, 0x3ff, v0
	s_mul_i32 s5, s14, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v7, v5
	v_mad_u64_u32 v[5:6], null, s5, v1, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v7, v0
	v_mul_hi_u32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s4
	v_sub_nc_u32_e32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v1, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v1, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v1, vcc_lo
	global_load_b32 v13, v[0:1], off
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[22:23], s[0:1], 0x20
	s_mul_i32 s0, s26, s18
	s_mul_i32 s1, s12, s3
	s_mul_i32 s0, s0, s2
	s_sub_i32 s14, s14, s1
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s3, s2, s3
	s_lshl_b64 s[24:25], s[0:1], 2
	s_sub_i32 s3, s15, s3
	s_mul_i32 s0, s26, s12
	v_lshl_add_u32 v0, s14, 4, v4
	v_lshl_add_u32 v14, s3, 4, v3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_add_u32 s15, s10, s24
	s_addc_u32 s26, s11, s25
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[0:1], 2
	s_add_u32 s14, s15, s10
	s_addc_u32 s15, s26, s11
	s_cmp_lt_i32 s20, 1
	s_cbranch_scc1 .LBB0_24
; %bb.1:                                ; %.lr.ph179
	v_sub_nc_u32_e32 v1, s21, v3
	s_mul_i32 s26, s19, s19
	s_add_i32 s29, s21, -1
	s_mul_i32 s0, s26, s20
	s_sub_i32 s30, 1, s21
	v_mul_lo_u32 v1, v1, s21
	s_mul_i32 s0, s0, s2
	v_max_u32_e32 v5, v4, v3
	s_ashr_i32 s1, s0, 31
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 5, v3
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_nc_u32_e32 v19, 16, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_xad_u32 v1, v4, -1, v1
	s_add_u32 s27, s4, s0
	s_mul_i32 s4, s21, s21
	s_addc_u32 s28, s5, s1
	s_mul_i32 s2, s4, s12
	v_cmp_gt_u32_e64 s0, s21, v5
	s_ashr_i32 s3, s2, 31
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_lshl_b64 s[2:3], s[2:3], 2
	v_lshlrev_b32_e32 v18, 2, v4
	s_add_u32 s1, s6, s2
	v_subrev_nc_u32_e32 v11, s29, v14
	v_add_nc_u32_e32 v20, 16, v14
	v_add_co_u32 v1, vcc_lo, s1, v5
	v_add_nc_u32_e32 v5, s30, v0
	s_addc_u32 s2, s7, s3
	v_add_nc_u32_e32 v8, s30, v19
	v_add_co_ci_u32_e32 v15, vcc_lo, s2, v6, vcc_lo
	v_add3_u32 v16, v7, v18, 0xe10
	v_mad_u64_u32 v[6:7], null, v11, s16, v[5:6]
	v_subrev_nc_u32_e32 v7, s29, v20
	v_mad_u64_u32 v[9:10], null, v11, s19, v[8:9]
	v_mad_u64_u32 v[11:12], null, v14, s16, v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v21, v7, s19
	v_cmp_gt_i32_e32 vcc_lo, s29, v0
	v_cmp_gt_i32_e64 s3, s29, v14
	s_lshl_b32 s2, s29, 1
	s_add_i32 s29, s29, s19
	s_mul_i32 s18, s4, s18
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v12, 31, v11
	v_cmp_le_i32_e64 s4, s29, v19
	v_add_nc_u32_e32 v19, v5, v21
	v_add_nc_u32_e32 v21, v8, v21
	s_or_b32 s1, vcc_lo, s3
	v_mad_u32_u24 v17, 0x78, v3, v18
	v_mul_u32_u24_e32 v23, 0x78, v3
	s_xor_b32 s6, s1, -1
	v_cmp_gt_u32_e64 s1, s2, v4
	v_cmp_gt_u32_e64 s2, s2, v3
	v_lshlrev_b64 v[3:4], 2, v[11:12]
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v10, 31, v9
	v_cmp_le_i32_e64 s5, s29, v20
	v_ashrrev_i32_e32 v20, 31, v19
	v_ashrrev_i32_e32 v22, 31, v21
	s_cmp_gt_i32 s21, 0
	s_mulk_i32 s17, 0x7c
	s_cselect_b32 s7, -1, 0
	s_or_b32 s19, s3, s4
	v_add_co_u32 v3, s3, s14, v3
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	v_lshlrev_b64 v[7:8], 2, v[9:10]
	v_lshlrev_b64 v[9:10], 2, v[19:20]
	v_lshlrev_b64 v[11:12], 2, v[21:22]
	v_add_co_ci_u32_e64 v4, s3, s15, v4, s3
	v_add3_u32 v18, s17, v23, v18
	s_xor_b32 s3, s19, -1
	s_or_b32 s19, vcc_lo, s5
	s_or_b32 s5, s5, s4
	s_xor_b32 s4, s19, -1
	s_xor_b32 s5, s5, -1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_19 Depth 2
                                        ;       Child Loop BB0_20 Depth 3
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mul_i32 s30, s18, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s31, s30, 31
	s_lshl_b64 s[30:31], s[30:31], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v19, vcc_lo, v1, s30
	v_add_co_ci_u32_e32 v20, vcc_lo, s31, v15, vcc_lo
	global_load_b32 v19, v[19:20], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v16, v19
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_mul_i32 s30, s26, s13
	v_mov_b32_e32 v19, 0
	s_ashr_i32 s31, s30, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[30:31], s[30:31], 2
	s_add_u32 s17, s27, s30
	s_addc_u32 s19, s28, s31
	s_and_saveexec_b32 s29, s6
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v19, vcc_lo, s17, v5
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v6, vcc_lo
	global_load_b32 v19, v[19:20], off
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	s_waitcnt vmcnt(0)
	ds_store_b32 v17, v19
	s_and_saveexec_b32 s29, s1
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	s_and_saveexec_b32 s30, s3
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v19, vcc_lo, s17, v7
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v8, vcc_lo
	global_load_b32 v19, v[19:20], off
.LBB0_9:                                ; %.sink.split
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s30
	s_waitcnt vmcnt(0)
	ds_store_b32 v17, v19 offset:64
.LBB0_10:                               ; %Flow251
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	s_and_saveexec_b32 s29, s2
	s_cbranch_execz .LBB0_17
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	s_and_saveexec_b32 s30, s4
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v19, vcc_lo, s17, v9
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v10, vcc_lo
	global_load_b32 v19, v[19:20], off
.LBB0_13:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s30
	s_waitcnt vmcnt(0)
	ds_store_b32 v17, v19 offset:1920
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	s_and_saveexec_b32 s30, s5
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v19, vcc_lo, s17, v11
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v12, vcc_lo
	global_load_b32 v19, v[19:20], off
.LBB0_16:                               ; %.sink.split193
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s30
	s_waitcnt vmcnt(0)
	ds_store_b32 v17, v19 offset:1984
.LBB0_17:                               ; %Flow250
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_23
; %bb.18:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v19, v[3:4], off
	v_mov_b32_e32 v20, v18
	s_mov_b32 s17, 0
	s_movk_i32 s19, 0xe10
.LBB0_19:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_20 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v21, v20
	s_mov_b32 s29, s19
	s_mov_b32 s30, s21
.LBB0_20:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_19 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v22, s29
	s_add_i32 s30, s30, -1
	s_add_i32 s29, s29, 4
	s_cmp_eq_u32 s30, 0
	ds_load_b32 v23, v21
	ds_load_b32 v22, v22
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v2, v23, v22 :: v_dual_add_nc_u32 v21, 4, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v19, v19, v2
	s_cbranch_scc0 .LBB0_20
; %bb.21:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_19 Depth=2
	v_add_nc_u32_e32 v20, 0x78, v20
	s_add_i32 s17, s17, 1
	s_add_i32 s19, s19, 32
	s_cmp_eq_u32 s17, s21
	s_cbranch_scc0 .LBB0_19
; %bb.22:                               ; %._crit_edge174.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_store_b32 v[3:4], v19, off
.LBB0_23:                               ; %._crit_edge174
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s13, s13, 1
	s_waitcnt_vscnt null, 0x0
	s_cmp_eq_u32 s13, s20
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_25
.LBB0_24:
	v_mov_b32_e32 v2, 0
.LBB0_25:                               ; %Flow253
	s_add_u32 s0, s22, s24
	s_addc_u32 s1, s23, s25
	s_add_u32 s2, s0, s10
	s_addc_u32 s3, s1, s11
	s_ashr_i32 s13, s12, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	v_mad_u64_u32 v[3:4], null, v14, s16, v[0:1]
	global_load_b32 v5, v1, s[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v2, v5
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, v13, v4
	v_cndmask_b32_e64 v5, 0, 1.0, vcc_lo
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_store_b32 v[2:3], v5, off
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
		.amdhsa_group_segment_fixed_size 3856
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i, .Lfunc_end0-_Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1600
; NumSgprs: 34
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3856 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 3856
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z27convolution_backward_kernelPfS_S_S_S_iiiiiiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
