#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <cuda.h>

void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
    int i;
    for(i=0; i<=n; i++) {
        menacc[i] = -1;
        womenacc[i] = -1;
        menpre[i] = 1;
        womenlock[i] = 0;
    }
}

__global__ void stable_matching(int n, int *d_men, int *d_women,
        int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
    int j = threadIdx.x + 1, idx, ct=0;
    while(1) {
        __syncthreads();
        if(*d_matched_ == 0) break;
        if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
            idx = d_men[j*(n+1) + d_menpre[j]];
            *d_matched = 0;
            // locking mechanism
            bool isSet = false;
            do {
                if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
                    if(d_womenacc[idx] == -1) {
                        d_womenacc[idx] = j;
                        d_menacc[j] = idx;
                    }
                    else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
                        d_menacc[d_womenacc[idx]] = -1;
                        d_menacc[j] = idx;
                        d_womenacc[idx] = j;
                    }
                }
                if(isSet) {
                    atomicCAS(&d_womenlock[idx], 1, 0);
                }
            } while(!isSet);
            d_menpre[j]++;
        }
        __syncthreads();
        if(j == 1 && *d_matched == 1) {
            *d_matched_ = 0;
        }
        else if(j == 1 && *d_matched == 0) {
            *d_matched = 1;
        }
        ct++;
    }
    __syncthreads();
}

int main()
{
    int n,i,j,k;
    int *d_matched, *d_matched_;
    int *men, *women;
    int *menacc, *womenacc, *menpre, *womenlock;
    int *d_men, *d_women;
    int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
    clock_t beg, end;
    double time_taken;

    scanf("%d",&n);
    men = (int *) malloc((n+1)*(n+1)*sizeof(int));
    women = (int *) malloc((n+1)*(n+1)*sizeof(int));
    menacc = (int *) malloc((n+1)*sizeof(int));
    womenacc = (int *) malloc((n+1)*sizeof(int));
    womenlock = (int *) malloc((n+1)*sizeof(int));
    menpre = (int *) malloc((n+1)*sizeof(int));

    cudaMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
    cudaMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
    cudaMalloc(&d_menacc, (n+1)*sizeof(int));
    cudaMalloc(&d_womenacc, (n+1)*sizeof(int));
    cudaMalloc(&d_womenlock, (n+1)*sizeof(int));
    cudaMalloc(&d_menpre, (n+1)*sizeof(int));
    cudaMalloc(&d_matched, sizeof(int));
    cudaMalloc(&d_matched_, sizeof(int));

    initialize(menacc, womenacc, menpre, womenlock, n);

    beg = clock();
    for(i=1; i<=n; i++) {
        for(j=0; j<=n; j++) {
            scanf("%d", &men[i*(n+1) + j]);
        }
    }

    for(i=1; i<=n; i++) {
        for(j=0; j<=n; j++) {
            scanf("%d", &k);
            women[i*(n+1) + k] = j;
        }
    }
    end = clock();
    time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
    printf("read time : %f us, ", time_taken);

    cudaMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_menacc, menacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_menpre, menpre, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
    int matched = 1;
    cudaMemcpy(d_matched, &matched, sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_matched_, &matched, sizeof(int), cudaMemcpyHostToDevice);

    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    float milliseconds = 0;
    cudaEventRecord(start,0);

    stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);

    cudaEventRecord(stop,0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&milliseconds, start, stop);

    cudaMemcpy(menacc, d_menacc, (n+1)*sizeof(int), cudaMemcpyDeviceToHost);
    printf("compute time : %f us\n", milliseconds*1000);

    for(j=1;j<=n;j++)
        printf("%d %d\n", j, menacc[j]);

    free(men); free(women);
    free(menacc); free(womenacc); free(menpre); free(womenlock);
    cudaFree(&d_men); cudaFree(&d_women); cudaFree(&d_matched); cudaFree(&d_matched_);
    cudaFree(&d_menacc); cudaFree(&d_womenacc); cudaFree(&d_menpre); cudaFree(&d_womenlock);

    return 0;
}
	.file	"tmpxft_0031002d_00000000-6_parallel_final.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0:
.LFB2173:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2173:
	.size	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	.globl	_Z10initializePiS_S_S_i
	.type	_Z10initializePiS_S_S_i, @function
_Z10initializePiS_S_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L4:
	cmpl	%eax, %r8d
	jl	.L7
	xorl	%r9d, %r9d
	movl	$-1, (%rdi,%rax,4)
	movl	$-1, (%rsi,%rax,4)
	movl	$1, (%rdx,%rax,4)
	movl	%r9d, (%rcx,%rax,4)
	incq	%rax
	jmp	.L4
.L7:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z10initializePiS_S_S_i, .-_Z10initializePiS_S_S_i
	.globl	_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
	.type	_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, @function
_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z15stable_matchingiPiS_S_S_S_S_S_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L8:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, .-_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
	.globl	_Z15stable_matchingiPiS_S_S_S_S_S_S_
	.type	_Z15stable_matchingiPiS_S_S_S_S_S_S_, @function
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
	.cfi_endproc
.LFE2054:
	.size	_Z15stable_matchingiPiS_S_S_S_S_S_S_, .-_Z15stable_matchingiPiS_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
.LC2:
	.string	"read time : %f us, "
.LC5:
	.string	"compute time : %f us\n"
.LC6:
	.string	"%d %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rdi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	64(%rsp), %rsi
	call	__isoc23_scanf@PLT
	movl	64(%rsp), %eax
	leal	1(%rax), %ebx
	movl	%ebx, %r12d
	imull	%ebx, %r12d
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movslq	%r12d, %r12
	salq	$2, %r12
	movq	%r12, %rdi
	call	malloc@PLT
	movq	%r12, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	%r12, %rsi
	movl	$1, %r12d
	movq	%rax, 24(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	leal	1(%rax), %esi
	leaq	104(%rsp), %rax
	imull	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	leal	1(%rax), %esi
	leaq	112(%rsp), %rax
	movslq	%esi, %rsi
	movq	%rax, %rdi
	movq	%rax, 48(%rsp)
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	leaq	120(%rsp), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	leaq	136(%rsp), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	leaq	128(%rsp), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	80(%rsp), %rdi
	movl	$4, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	88(%rsp), %rdi
	movl	$4, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %r8d
	movq	16(%rsp), %rcx
	movq	%rbp, %rdi
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rsi
	call	_Z10initializePiS_S_S_i
	call	clock@PLT
	movq	%rax, %rbx
.L14:
	cmpl	%r12d, 64(%rsp)
	jl	.L27
	xorl	%r15d, %r15d
.L16:
	movl	64(%rsp), %eax
	cmpl	%r15d, %eax
	jl	.L28
	incl	%eax
	leaq	.LC0(%rip), %rdi
	imull	%r12d, %eax
	addl	%r15d, %eax
	incl	%r15d
	cltq
	leaq	(%r14,%rax,4), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	jmp	.L16
.L28:
	incl	%r12d
	jmp	.L14
.L27:
	leaq	68(%rsp), %rax
	movl	$1, %r12d
	movq	%rax, 56(%rsp)
.L17:
	cmpl	%r12d, 64(%rsp)
	jl	.L29
	xorl	%r15d, %r15d
.L19:
	cmpl	%r15d, 64(%rsp)
	jl	.L30
	movq	56(%rsp), %rsi
	leaq	.LC0(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	64(%rsp), %eax
	incl	%eax
	imull	%r12d, %eax
	addl	68(%rsp), %eax
	cltq
	movl	%r15d, 0(%r13,%rax,4)
	incl	%r15d
	jmp	.L19
.L30:
	incl	%r12d
	jmp	.L17
.L29:
	call	clock@PLT
	movsd	.LC1(%rip), %xmm1
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	subq	%rbx, %rax
	leaq	72(%rsp), %rbx
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	mulsd	%xmm1, %xmm0
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movl	64(%rsp), %eax
	movq	96(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	leal	1(%rax), %edx
	imull	%edx, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movq	104(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	leal	1(%rax), %edx
	imull	%edx, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movq	112(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	136(%rsp), %rdi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	120(%rsp), %rdi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4, %edx
	movl	$1, 72(%rsp)
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	leaq	144(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	152(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	144(%rsp), %rdi
	xorl	%esi, %esi
	movl	$0x00000000, 76(%rsp)
	call	cudaEventRecord@PLT
	movl	64(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, 176(%rsp)
	movl	180(%rsp), %ecx
	movl	%eax, 172(%rsp)
	movq	172(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	%rax
	.cfi_def_cfa_offset 264
	pushq	144(%rsp)
	.cfi_def_cfa_offset 272
	pushq	104(%rsp)
	.cfi_def_cfa_offset 280
	pushq	104(%rsp)
	.cfi_def_cfa_offset 288
	movq	160(%rsp), %r9
	movq	152(%rsp), %r8
	movq	144(%rsp), %rcx
	movq	136(%rsp), %rdx
	movq	128(%rsp), %rsi
	movl	96(%rsp), %edi
	call	_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 256
.L20:
	movq	152(%rsp), %rdi
	xorl	%esi, %esi
	movl	$1, %r12d
	leaq	.LC6(%rip), %rbx
	call	cudaEventRecord@PLT
	movq	152(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	152(%rsp), %rdx
	leaq	76(%rsp), %rdi
	movq	144(%rsp), %rsi
	call	cudaEventElapsedTime@PLT
	movl	64(%rsp), %eax
	movq	112(%rsp), %rsi
	movq	%rbp, %rdi
	movl	$2, %ecx
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movss	.LC4(%rip), %xmm0
	mulss	76(%rsp), %xmm0
	movb	$1, %al
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
.L21:
	movl	%r12d, %edx
	cmpl	%r12d, 64(%rsp)
	jl	.L31
	movl	0(%rbp,%r12,4), %ecx
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	jmp	.L21
.L31:
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	80(%rsp), %rdi
	call	cudaFree@PLT
	leaq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	leaq	120(%rsp), %rdi
	call	cudaFree@PLT
	leaq	128(%rsp), %rdi
	call	cudaFree@PLT
	leaq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z15stable_matchingiPiS_S_S_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15stable_matchingiPiS_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <hip/hip_runtime.h>

void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
    int i;
    for(i=0; i<=n; i++) {
        menacc[i] = -1;
        womenacc[i] = -1;
        menpre[i] = 1;
        womenlock[i] = 0;
    }
}

__global__ void stable_matching(int n, int *d_men, int *d_women,
        int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
    int j = threadIdx.x + 1, idx, ct=0;
    while(1) {
        __syncthreads();
        if(*d_matched_ == 0) break;
        if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
            idx = d_men[j*(n+1) + d_menpre[j]];
            *d_matched = 0;
            // locking mechanism
            bool isSet = false;
            do {
                if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
                    if(d_womenacc[idx] == -1) {
                        d_womenacc[idx] = j;
                        d_menacc[j] = idx;
                    }
                    else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
                        d_menacc[d_womenacc[idx]] = -1;
                        d_menacc[j] = idx;
                        d_womenacc[idx] = j;
                    }
                }
                if(isSet) {
                    atomicCAS(&d_womenlock[idx], 1, 0);
                }
            } while(!isSet);
            d_menpre[j]++;
        }
        __syncthreads();
        if(j == 1 && *d_matched == 1) {
            *d_matched_ = 0;
        }
        else if(j == 1 && *d_matched == 0) {
            *d_matched = 1;
        }
        ct++;
    }
    __syncthreads();
}

int main()
{
    int n,i,j,k;
    int *d_matched, *d_matched_;
    int *men, *women;
    int *menacc, *womenacc, *menpre, *womenlock;
    int *d_men, *d_women;
    int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
    clock_t beg, end;
    double time_taken;

    scanf("%d",&n);
    men = (int *) malloc((n+1)*(n+1)*sizeof(int));
    women = (int *) malloc((n+1)*(n+1)*sizeof(int));
    menacc = (int *) malloc((n+1)*sizeof(int));
    womenacc = (int *) malloc((n+1)*sizeof(int));
    womenlock = (int *) malloc((n+1)*sizeof(int));
    menpre = (int *) malloc((n+1)*sizeof(int));

    hipMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
    hipMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
    hipMalloc(&d_menacc, (n+1)*sizeof(int));
    hipMalloc(&d_womenacc, (n+1)*sizeof(int));
    hipMalloc(&d_womenlock, (n+1)*sizeof(int));
    hipMalloc(&d_menpre, (n+1)*sizeof(int));
    hipMalloc(&d_matched, sizeof(int));
    hipMalloc(&d_matched_, sizeof(int));

    initialize(menacc, womenacc, menpre, womenlock, n);

    beg = clock();
    for(i=1; i<=n; i++) {
        for(j=0; j<=n; j++) {
            scanf("%d", &men[i*(n+1) + j]);
        }
    }

    for(i=1; i<=n; i++) {
        for(j=0; j<=n; j++) {
            scanf("%d", &k);
            women[i*(n+1) + k] = j;
        }
    }
    end = clock();
    time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
    printf("read time : %f us, ", time_taken);

    hipMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_menacc, menacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_menpre, menpre, (n+1)*sizeof(int), hipMemcpyHostToDevice);
    int matched = 1;
    hipMemcpy(d_matched, &matched, sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_matched_, &matched, sizeof(int), hipMemcpyHostToDevice);

    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);
    float milliseconds = 0;
    hipEventRecord(start,0);

    stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);

    hipEventRecord(stop,0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&milliseconds, start, stop);

    hipMemcpy(menacc, d_menacc, (n+1)*sizeof(int), hipMemcpyDeviceToHost);
    printf("compute time : %f us\n", milliseconds*1000);

    for(j=1;j<=n;j++)
        printf("%d %d\n", j, menacc[j]);

    free(men); free(women);
    free(menacc); free(womenacc); free(menpre); free(womenlock);
    hipFree(&d_men); hipFree(&d_women); hipFree(&d_matched); hipFree(&d_matched_);
    hipFree(&d_menacc); hipFree(&d_womenacc); hipFree(&d_menpre); hipFree(&d_womenlock);

    return 0;
}
	.text
	.file	"parallel_final.hip"
	.globl	_Z10initializePiS_S_S_i         # -- Begin function _Z10initializePiS_S_S_i
	.type	_Z10initializePiS_S_S_i,@function
_Z10initializePiS_S_S_i:                # @_Z10initializePiS_S_S_i
	.cfi_startproc
# %bb.0:
                                        # kill: def $r8d killed $r8d def $r8
	testl	%r8d, %r8d
	js	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	incl	%r8d
	xorl	%eax, %eax
	movl	$-1, %r9d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%r9d, (%rdi,%rax,4)
	movl	%r9d, (%rsi,%rax,4)
	movl	$1, (%rdx,%rax,4)
	movl	$0, (%rcx,%rax,4)
	incq	%rax
	cmpq	%rax, %r8
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z10initializePiS_S_S_i, .Lfunc_end0-_Z10initializePiS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_ # -- Begin function _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
	.type	_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_,@function
_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_: # @_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15stable_matchingiPiS_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_, .Lfunc_end1-_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI2_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	4(%rsp), %r12
	movl	$.L.str, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%r12), %r15
	leaq	1(%r15), %r13
	imull	%r13d, %r13d
	shlq	$2, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r14
	leaq	4(,%r15,4), %rbp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leaq	72(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movl	(%r12), %esi
	incl	%esi
	imull	%esi, %esi
	shlq	$2, %rsi
	leaq	64(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rax
	leaq	4(,%rax,4), %rsi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rax
	leaq	4(,%rax,4), %rsi
	leaq	56(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rax
	leaq	4(,%rax,4), %rsi
	leaq	40(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rax
	leaq	4(,%rax,4), %rsi
	leaq	48(%rsp), %rdi
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	movl	(%r12), %r13d
	testl	%r13d, %r13d
	js	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader.i
	leaq	4(,%r13,4), %r12
	incq	%r13
	movq	%r15, %rdi
	movl	$255, %esi
	movq	%r12, %rdx
	callq	memset@PLT
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$255, %esi
	movq	%r12, %rdx
	callq	memset@PLT
	xorl	%ebp, %ebp
	movq	104(%rsp), %rdi                 # 8-byte Reload
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	memset@PLT
	movq	16(%rsp), %rax                  # 8-byte Reload
.LBB2_2:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movl	$1, (%rax,%rbp,4)
	incq	%rbp
	cmpq	%rbp, %r13
	jne	.LBB2_2
.LBB2_3:                                # %_Z10initializePiS_S_S_i.exit
	callq	clock
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movl	4(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB2_15
# %bb.4:                                # %.preheader52.preheader
	movl	$1, %r13d
.LBB2_5:                                # %.preheader52
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_7 Depth 2
	testl	%eax, %eax
	js	.LBB2_8
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_5 Depth=1
	xorl	%r12d, %r12d
.LBB2_7:                                # %.lr.ph
                                        #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	incl	%eax
	imull	%r13d, %eax
	cltq
	addq	%r12, %rax
	leaq	(%rbx,%rax,4), %rsi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	4(%rsp), %eax
	incq	%r12
	leal	-1(%r12), %ecx
	cmpl	%eax, %ecx
	jl	.LBB2_7
.LBB2_8:                                # %._crit_edge
                                        #   in Loop: Header=BB2_5 Depth=1
	leal	1(%r13), %ecx
	cmpl	%eax, %r13d
	movl	%ecx, %r13d
	jl	.LBB2_5
# %bb.9:                                # %.preheader51
	testl	%eax, %eax
	jle	.LBB2_15
# %bb.10:                               # %.preheader.preheader
	movl	$1, %r12d
	leaq	100(%rsp), %r13
.LBB2_11:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_13 Depth 2
	testl	%eax, %eax
	js	.LBB2_14
# %bb.12:                               # %.lr.ph59.preheader
                                        #   in Loop: Header=BB2_11 Depth=1
	movl	$-1, %ebp
.LBB2_13:                               # %.lr.ph59
                                        #   Parent Loop BB2_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	incl	%ebp
	movl	$.L.str, %edi
	movq	%r13, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	4(%rsp), %eax
	leal	1(%rax), %ecx
	imull	%r12d, %ecx
	movslq	100(%rsp), %rdx
	movslq	%ecx, %rcx
	addq	%rdx, %rcx
	movl	%ebp, (%r14,%rcx,4)
	cmpl	%eax, %ebp
	jl	.LBB2_13
.LBB2_14:                               # %._crit_edge60
                                        #   in Loop: Header=BB2_11 Depth=1
	leal	1(%r12), %ecx
	cmpl	%eax, %r12d
	movl	%ecx, %r12d
	jl	.LBB2_11
.LBB2_15:                               # %._crit_edge63
	callq	clock
	subq	112(%rsp), %rax                 # 8-byte Folded Reload
	cvtsi2sd	%rax, %xmm0
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	divsd	%xmm1, %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	72(%rsp), %rdi
	movl	4(%rsp), %edx
	incl	%edx
	imull	%edx, %edx
	shlq	$2, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rdi
	movl	4(%rsp), %edx
	incl	%edx
	imull	%edx, %edx
	shlq	$2, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	104(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	56(%rsp), %rdi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	132(%rsp), %r12
	movl	$1, (%r12)
	movq	88(%rsp), %rdi
	movl	$4, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rdi
	movl	$4, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	120(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	movl	$0, 96(%rsp)
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	4(%rsp), %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_17
# %bb.16:
	movl	4(%rsp), %edi
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdx
	movq	8(%rsp), %rcx
	movq	56(%rsp), %r8
	movq	48(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB2_17:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rdi
	callq	hipEventSynchronize
	movq	120(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	96(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movq	8(%rsp), %rsi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r12), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	mulss	.LCPI2_1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	cmpl	$0, 4(%rsp)
	jle	.LBB2_20
# %bb.18:                               # %.lr.ph67.preheader
	movl	$1, %r12d
.LBB2_19:                               # %.lr.ph67
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r15,%r12,4), %edx
	movl	$.L.str.3, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	leaq	1(%r12), %rax
	movslq	4(%rsp), %rcx
	cmpq	%rcx, %r12
	movq	%rax, %r12
	jl	.LBB2_19
.LBB2_20:                               # %._crit_edge68
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	leaq	72(%rsp), %rdi
	callq	hipFree
	leaq	64(%rsp), %rdi
	callq	hipFree
	leaq	88(%rsp), %rdi
	callq	hipFree
	leaq	80(%rsp), %rdi
	callq	hipFree
	leaq	8(%rsp), %rdi
	callq	hipFree
	leaq	56(%rsp), %rdi
	callq	hipFree
	leaq	48(%rsp), %rdi
	callq	hipFree
	leaq	40(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15stable_matchingiPiS_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15stable_matchingiPiS_S_S_S_S_S_S_,@object # @_Z15stable_matchingiPiS_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z15stable_matchingiPiS_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
	.quad	_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
	.size	_Z15stable_matchingiPiS_S_S_S_S_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"read time : %f us, "
	.size	.L.str.1, 20

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"compute time : %f us\n"
	.size	.L.str.2, 22

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d %d\n"
	.size	.L.str.3, 7

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15stable_matchingiPiS_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15stable_matchingiPiS_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15stable_matchingiPiS_S_S_S_S_S_S_ ; -- Begin function _Z15stable_matchingiPiS_S_S_S_S_S_S_
	.globl	_Z15stable_matchingiPiS_S_S_S_S_S_S_
	.p2align	8
	.type	_Z15stable_matchingiPiS_S_S_S_S_S_S_,@function
_Z15stable_matchingiPiS_S_S_S_S_S_S_:   ; @_Z15stable_matchingiPiS_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x0
	s_load_b512 s[4:19], s[0:1], 0x8
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
	v_add_nc_u32_e32 v14, 1, v0
	v_mov_b32_e32 v16, -1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, s2, v0
	s_add_i32 s2, s2, 1
	v_add_co_u32 v3, s1, s8, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, null, s9, 0, s1
	v_add_co_u32 v5, s1, s12, v1
	v_mov_b32_e32 v1, 1
	v_mul_lo_u32 v15, s2, v14
	v_add_co_ci_u32_e64 v6, null, s13, 0, s1
	v_cmp_eq_u32_e64 s1, 0, v0
	s_add_u32 s3, s6, 4
	s_addc_u32 s12, s7, 0
.LBB0_1:                                ; %.critedge66
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v17, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v17
	s_cbranch_vccnz .LBB0_16
; %bb.2:                                ; %LeafBlock97
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 1, v17
	s_cbranch_vccz .LBB0_15
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_14
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v7, v[3:4], off offset:4
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, -1, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.5:                                ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v7, v[5:6], off offset:4
	s_mov_b32 s20, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v9, v[7:8], off
	global_store_b32 v2, v2, s[14:15]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[9:10]
	v_add_co_u32 v7, vcc_lo, s18, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v11, vcc_lo
.LBB0_6:                                ; %.critedge64
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_atomic_cmpswap_b32 v12, v[7:8], v[1:2], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	s_mov_b32 s20, exec_lo
	global_load_b32 v12, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v12
	s_xor_b32 s20, exec_lo, s20
	s_cbranch_execz .LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_1 Depth=1
	v_mul_lo_u32 v13, v9, s2
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, v12, v13
	v_ashrrev_i32_e32 v21, 31, v13
	v_add_co_u32 v20, vcc_lo, v13, v0
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v18, vcc_lo, s6, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, s3, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v21, vcc_lo, s12, v21, vcc_lo
	s_clause 0x1
	global_load_b32 v13, v[18:19], off
	global_load_b32 v18, v[20:21], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v13, v18
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_1 Depth=1
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	s_clause 0x1
	global_store_b32 v[12:13], v16, off
	global_store_b32 v[3:4], v9, off offset:4
	global_store_b32 v[10:11], v14, off
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr9
.LBB0_11:                               ; %Flow105
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_1 Depth=1
	global_store_b32 v[10:11], v14, off
	global_store_b32 v[3:4], v9, off offset:4
.LBB0_13:                               ; %.critedge
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v10, v1
	global_atomic_cmpswap_b32 v[7:8], v[9:10], off
	global_load_b32 v7, v[5:6], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, 1, v7
	global_store_b32 v[5:6], v7, off offset:4
.LBB0_14:                               ; %Flow107
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_15:                               ; %Flow108
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s20, 0
	s_mov_b32 s13, -1
	s_branch .LBB0_17
.LBB0_16:                               ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s20, -1
	s_mov_b32 s13, 0
.LBB0_17:                               ; %Flow114
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_19
; %bb.18:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_cmp_ne_u32_e64 s13, 0, v17
.LBB0_19:                               ; %Flow115
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_mov_b32 s13, -1
	s_cbranch_vccnz .LBB0_29
; %bb.20:                               ;   in Loop: Header=BB0_1 Depth=1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB0_28
; %bb.21:                               ; %NodeBlock103
                                        ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v7, v2, s[14:15]
	s_mov_b32 s21, -1
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v7
	v_readfirstlane_b32 s20, v7
	s_cbranch_vccnz .LBB0_25
; %bb.22:                               ; %LeafBlock101
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s20, 1
	s_cbranch_scc0 .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_1 Depth=1
	global_store_b32 v2, v2, s[16:17]
.LBB0_24:                               ; %Flow109
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s21, 0
.LBB0_25:                               ; %Flow111
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s21
	s_cbranch_vccnz .LBB0_28
; %bb.26:                               ; %LeafBlock99
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc0 .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_1 Depth=1
	global_store_b32 v2, v1, s[14:15]
.LBB0_28:                               ; %Flow113
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_mov_b32 s13, 0
.LBB0_29:                               ; %Flow116
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_cbranch_vccnz .LBB0_1
; %bb.30:
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15stable_matchingiPiS_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 72
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15stable_matchingiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z15stable_matchingiPiS_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 24
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 72
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15stable_matchingiPiS_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z15stable_matchingiPiS_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
