// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>

// CUDA runtime
#include <cuda.h>
#include <cuda_runtime.h>


#define CUDA_ERROR_CHECK

#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError()    __cudaCheckError( __FILE__, __LINE__ )

inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
    if ( cudaSuccess != err )
    {
        fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
                 file, line, cudaGetErrorString( err ) );
        exit( -1 );
    }
#endif

    return;
}

inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
    cudaError err = cudaGetLastError();
    if ( cudaSuccess != err )
    {
        fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
                 file, line, cudaGetErrorString( err ) );
        exit( -1 );
    }

    // More careful checking. However, this will affect performance.
    // Comment away if needed.
    err = cudaDeviceSynchronize();
    if( cudaSuccess != err )
    {
        fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
                 file, line, cudaGetErrorString( err ) );
        exit( -1 );
    }
#endif

    return;
}



// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
        const float *  __restrict__ matA,
        const float *  __restrict__ matB,
        float *  __restrict__ matC,
        int dim0,
        int dim1A, int dim2A,
        int dim1B, int dim2B,
        int dim1C, int dim2C){
    extern __shared__ float smem[];

    const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
    const unsigned long
            len_A = dim0*dim1A*dim2A,
            len_B = dim0*dim1B*dim2B,
            len_C = dim0*dim1C*dim2C;
    const unsigned long
            len_A_signleBatch = dim1A*dim2A,
            len_B_signleBatch = dim1B*dim2B,
            len_C_signleBatch = dim1C*dim2C;
    const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;

    //smemA = smem + 0;
    //smemB = smem + len_subA;


    // Block index
    unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
    unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
    unsigned int bz = blockIdx.z; // batch index

    // Thread index
    unsigned int  tx = threadIdx.x;
    unsigned int  ty = threadIdx.y;

    unsigned int  c_pos_x, c_pos_y;
    c_pos_x = bx*BLOCK_SIZE_X + tx;
    c_pos_y = by*BLOCK_SIZE_Y + ty;

    unsigned long gidx1,gidx2;
    unsigned int _d1,_d2;

    //printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);


    unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
    unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)

    // Load sub matrices from global memory into shared memory

    unsigned long idxA, idxB;
    idxA = ty* BLOCK_SIZE_X + tx;
    idxB = ty* BLOCK_SIZE_X + tx;

    //printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);

    while(idxA < len_subA){//Block-stride loop
        gidx1 = offsetA + idxA;
        if(idxA < len_subA && gidx1 < len_A) {
            smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
            /*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
        }else{
            smem[idxA] = 0;
        }
        idxA += BLOCKSIZE_P2;
    }

    ///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
    ///      But then we might get shared memory write conflict. (?)
    while(idxB < len_subB ){//Block-stride loop
        //gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
        _d2 = idxB%BLOCK_SIZE_X;
        _d1 = (idxB/BLOCK_SIZE_X);
        gidx2 = offsetB + _d1*dim2B + _d2;
        if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
            smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
            /*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
        }else{
            smem[len_subA+idxB] = 0;
        }
        idxB += BLOCKSIZE_P2;
    }





    __syncthreads();




    // Multiply and add each result to produce output element of current thread in the thread block.
    if(c_pos_x<dim2C && c_pos_y<dim1C){
        float output_element = 0.0f;

        //dim2A=dim1B is common equal dimension of 2 matrices  --- block-stride loop
        for (int k = 0; k < dim2A; k++) {
            output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
            /*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
                    bz,c_pos_x,c_pos_y,
                    ty*dim2A+k,smem[ty*dim2A+k],
                    len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
        }

        ///TODO: Check matC index to not to exceed the len of matC!
        matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;

    }



}

void batch_matmul(
        const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A,  dim1A  , *dim2A* )
        const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* ,  dim2B  )
        float * matC,		//row-major device ptr (batch, hB, wB) == (dim0B,  dim1A  ,  dim2B  )
        int dim0A, int dim1A, int dim2A,
        int dim0B, int dim1B, int dim2B){
    if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
    if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}

    const int BLOCK_DIM_X = 4;
    const int BLOCK_DIM_Y = 4;

    dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
    dim3 gridsize(0,0,0);
    gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
    gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
    gridsize.z = (dim0A);
    unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
    //printf("@batched_matmul:\n");
    //printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
    //printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
    //printf("\t SHARED: %d Bytes\n",sharedmemsize);

    if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
        kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
                matA,
                        matB,
                        matC,
                        dim0A,

                        dim1A, //hA
                        dim2A, //wA

                        dim1B, //hA
                        dim2B, //wA

                        dim1A,
                        dim2B);
        CudaCheckError();
    }else{
        printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
    }

}
	.file	"tmpxft_003825c1_00000000-6_mamul.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3681:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii, @function
_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii:
.LFB3703:
	.cfi_startproc
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3703:
	.size	_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii, .-_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
	.section	.text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
	.weak	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.type	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, @function
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
.LFB4006:
	.cfi_startproc
	endbr64
	jmp	_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
	.cfi_endproc
.LFE4006:
	.size	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .-_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.section	.rodata._Z16__cudaCheckErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaCheckError() failed at %s:%i : %s\n"
.LC1:
	.string	"cudaCheckError() with sync failed at %s:%i : %s\n"
	.section	.text._Z16__cudaCheckErrorPKci,"axG",@progbits,_Z16__cudaCheckErrorPKci,comdat
	.weak	_Z16__cudaCheckErrorPKci
	.type	_Z16__cudaCheckErrorPKci, @function
_Z16__cudaCheckErrorPKci:
.LFB3675:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L9
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	%ebp, %r8d
	movq	%rbx, %rcx
	leaq	.LC0(%rip), %rdx
	movq	%rax, %r9
	jmp	.L12
.L9:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L8
	call	cudaGetErrorString@PLT
	movl	%ebp, %r8d
	movq	%rbx, %rcx
	leaq	.LC1(%rip), %rdx
	movq	%rax, %r9
.L12:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L8:
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	_Z16__cudaCheckErrorPKci, .-_Z16__cudaCheckErrorPKci
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"ERR@batched_matmul: BAD SHAPE.\n"
.LC3:
	.string	"ERR@batched_matmul: BAD BATCH SIZES.\n"
.LC4:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/salehjg/DGCNN-GPGPU/master/kernels/cuda/mamul.cu"
	.text
	.globl	_Z12batch_matmulPKfS0_Pfiiiiii
	.type	_Z12batch_matmulPKfS0_Pfiiiiii, @function
_Z12batch_matmulPKfS0_Pfiiiiii:
.LFB3678:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	movl	112(%rsp), %r15d
	movl	128(%rsp), %r12d
	cmpl	120(%rsp), %r9d
	je	.L14
	leaq	.LC2(%rip), %rsi
	jmp	.L18
.L14:
	cmpl	%ecx, %r15d
	je	.L15
	leaq	.LC3(%rip), %rsi
.L18:
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L15:
	.cfi_restore_state
	leal	3(%r12), %eax
	movl	$4, %ecx
	movq	%rdx, %r14
	movq	%rsi, %r13
	cltd
	movl	%r8d, %ebp
	movl	%r9d, %ebx
	movl	%r15d, %esi
	idivl	%ecx
	movl	%eax, 36(%rsp)
	leal	3(%r8), %eax
	cltd
	idivl	%ecx
	movabsq	$17179869188, %rdx
	movl	$1, %ecx
	movl	%eax, 40(%rsp)
	leal	0(,%r9,8), %eax
	movq	36(%rsp), %rdi
	xorl	%r9d, %r9d
	cltq
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	%r12
	.cfi_def_cfa_offset 120
	movl	%ebx, %r9d
	movl	%ebp, %r8d
	movl	%r15d, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 128
	movq	%r14, %rdx
	movq	%r13, %rsi
	pushq	%r12
	.cfi_def_cfa_offset 136
	pushq	%rbx
	.cfi_def_cfa_offset 144
	movq	40(%rsp), %rdi
	call	_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 112
.L16:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	movl	$212, %esi
	leaq	.LC4(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z16__cudaCheckErrorPKci
	.cfi_endproc
.LFE3678:
	.size	_Z12batch_matmulPKfS0_Pfiiiiii, .-_Z12batch_matmulPKfS0_Pfiiiiii
	.section	.rodata.str1.1
.LC5:
	.string	"_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3706:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>

// CUDA runtime
#include <hip/hip_runtime.h>



#define CUDA_ERROR_CHECK

#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError()    __cudaCheckError( __FILE__, __LINE__ )

inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
    if ( hipSuccess != err )
    {
        fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
                 file, line, hipGetErrorString( err ) );
        exit( -1 );
    }
#endif

    return;
}

inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
    hipError_t err = hipGetLastError();
    if ( hipSuccess != err )
    {
        fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
                 file, line, hipGetErrorString( err ) );
        exit( -1 );
    }

    // More careful checking. However, this will affect performance.
    // Comment away if needed.
    err = hipDeviceSynchronize();
    if( hipSuccess != err )
    {
        fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
                 file, line, hipGetErrorString( err ) );
        exit( -1 );
    }
#endif

    return;
}



// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
        const float *  __restrict__ matA,
        const float *  __restrict__ matB,
        float *  __restrict__ matC,
        int dim0,
        int dim1A, int dim2A,
        int dim1B, int dim2B,
        int dim1C, int dim2C){
    extern __shared__ float smem[];

    const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
    const unsigned long
            len_A = dim0*dim1A*dim2A,
            len_B = dim0*dim1B*dim2B,
            len_C = dim0*dim1C*dim2C;
    const unsigned long
            len_A_signleBatch = dim1A*dim2A,
            len_B_signleBatch = dim1B*dim2B,
            len_C_signleBatch = dim1C*dim2C;
    const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;

    //smemA = smem + 0;
    //smemB = smem + len_subA;


    // Block index
    unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
    unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
    unsigned int bz = blockIdx.z; // batch index

    // Thread index
    unsigned int  tx = threadIdx.x;
    unsigned int  ty = threadIdx.y;

    unsigned int  c_pos_x, c_pos_y;
    c_pos_x = bx*BLOCK_SIZE_X + tx;
    c_pos_y = by*BLOCK_SIZE_Y + ty;

    unsigned long gidx1,gidx2;
    unsigned int _d1,_d2;

    //printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);


    unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
    unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)

    // Load sub matrices from global memory into shared memory

    unsigned long idxA, idxB;
    idxA = ty* BLOCK_SIZE_X + tx;
    idxB = ty* BLOCK_SIZE_X + tx;

    //printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);

    while(idxA < len_subA){//Block-stride loop
        gidx1 = offsetA + idxA;
        if(idxA < len_subA && gidx1 < len_A) {
            smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
            /*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
        }else{
            smem[idxA] = 0;
        }
        idxA += BLOCKSIZE_P2;
    }

    ///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
    ///      But then we might get shared memory write conflict. (?)
    while(idxB < len_subB ){//Block-stride loop
        //gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
        _d2 = idxB%BLOCK_SIZE_X;
        _d1 = (idxB/BLOCK_SIZE_X);
        gidx2 = offsetB + _d1*dim2B + _d2;
        if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
            smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
            /*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
        }else{
            smem[len_subA+idxB] = 0;
        }
        idxB += BLOCKSIZE_P2;
    }





    __syncthreads();




    // Multiply and add each result to produce output element of current thread in the thread block.
    if(c_pos_x<dim2C && c_pos_y<dim1C){
        float output_element = 0.0f;

        //dim2A=dim1B is common equal dimension of 2 matrices  --- block-stride loop
        for (int k = 0; k < dim2A; k++) {
            output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
            /*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
                    bz,c_pos_x,c_pos_y,
                    ty*dim2A+k,smem[ty*dim2A+k],
                    len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
        }

        ///TODO: Check matC index to not to exceed the len of matC!
        matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;

    }



}

void batch_matmul(
        const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A,  dim1A  , *dim2A* )
        const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* ,  dim2B  )
        float * matC,		//row-major device ptr (batch, hB, wB) == (dim0B,  dim1A  ,  dim2B  )
        int dim0A, int dim1A, int dim2A,
        int dim0B, int dim1B, int dim2B){
    if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
    if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}

    const int BLOCK_DIM_X = 4;
    const int BLOCK_DIM_Y = 4;

    dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
    dim3 gridsize(0,0,0);
    gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
    gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
    gridsize.z = (dim0A);
    unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
    //printf("@batched_matmul:\n");
    //printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
    //printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
    //printf("\t SHARED: %d Bytes\n",sharedmemsize);

    if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
        kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
                matA,
                        matB,
                        matC,
                        dim0A,

                        dim1A, //hA
                        dim2A, //wA

                        dim1B, //hA
                        dim2B, //wA

                        dim1A,
                        dim2B);
        CudaCheckError();
    }else{
        printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
    }

}
	.text
	.file	"mamul.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z12batch_matmulPKfS0_Pfiiiiii  # -- Begin function _Z12batch_matmulPKfS0_Pfiiiiii
	.type	_Z12batch_matmulPKfS0_Pfiiiiii,@function
_Z12batch_matmulPKfS0_Pfiiiiii:         # @_Z12batch_matmulPKfS0_Pfiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %r13
	movl	$.Lstr.1, %edi
	cmpl	72(%rsp), %r9d
	jne	.LBB0_9
# %bb.1:
	movl	64(%rsp), %ebp
	movl	$.Lstr, %edi
	cmpl	%ecx, %ebp
	jne	.LBB0_9
# %bb.2:
	movl	%r9d, %ebx
	movl	%r8d, %r14d
	movq	%rdx, %r15
	movq	%rsi, %r12
	movl	80(%rsp), %ecx
	leal	3(%rcx), %eax
	movq	%rcx, (%rsp)                    # 8-byte Spill
	addl	$6, %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	leal	3(%r14), %eax
	leal	6(%r14), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$2, %edi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	leal	(,%rbx,8), %eax
	movslq	%eax, %r8
	shlq	$2, %r8
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	%ebp, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	%ebp, %ecx
	movl	%r14d, %r8d
	movl	%ebx, %r9d
	movq	(%rsp), %rax                    # 8-byte Reload
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB0_4:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_5
# %bb.7:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB0_8
# %bb.10:                               # %_Z16__cudaCheckErrorPKci.exit
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_9:                                # %_Z16__cudaCheckErrorPKci.exit.sink.split
	.cfi_def_cfa_offset 64
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.LBB0_5:
	.cfi_def_cfa_offset 64
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.3, %esi
	jmp	.LBB0_6
.LBB0_8:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
.LBB0_6:
	movl	$.L.str.2, %edx
	movq	%rbx, %rdi
	movl	$212, %ecx
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z12batch_matmulPKfS0_Pfiiiiii, .Lfunc_end0-_Z12batch_matmulPKfS0_Pfiiiiii
	.cfi_endproc
                                        # -- End function
	.section	.text._Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
	.weak	_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii # -- Begin function _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.type	_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@function
_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii: # @_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .Lfunc_end1-_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@object # @_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.section	.rodata._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"aG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
	.weak	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.p2align	3, 0x0
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
	.quad	_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.size	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/salehjg/DGCNN-GPGPU/master/kernels/cuda/mamul.hip"
	.size	.L.str.2, 112

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"cudaCheckError() failed at %s:%i : %s\n"
	.size	.L.str.3, 39

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"cudaCheckError() with sync failed at %s:%i : %s\n"
	.size	.L.str.4, 49

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii"
	.size	.L__unnamed_1, 50

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"ERR@batched_matmul: BAD BATCH SIZES."
	.size	.Lstr, 37

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"ERR@batched_matmul: BAD SHAPE."
	.size	.Lstr.1, 31

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
	.protected	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii ; -- Begin function _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.globl	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
	.p2align	8
	.type	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@function
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii: ; @_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b128 s[16:19], s[0:1], 0x28
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v6, 0x3ff, v0
	v_bfe_u32 v7, v0, 10, 10
	s_lshl_b32 s14, s14, 2
	s_mov_b32 s3, 0
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v7, 2, v6
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s10, 2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_u32_e64 s2, v0
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 2, v7
	v_lshlrev_b32_e32 v4, 4, v7
	v_lshlrev_b32_e32 v5, 2, v6
	s_load_b64 s[20:21], s[0:1], 0x0
	s_mul_i32 s1, s14, s10
	s_mul_i32 s19, s10, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v4, v5, 0
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	v_add_co_u32 v2, s22, v2, v6
	v_add_co_ci_u32_e64 v3, null, 0, 0, s22
	s_ashr_i32 s0, s19, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, s1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_mul_i32 s0, s0, s15
	s_mul_hi_u32 s22, s19, s15
	s_mul_i32 s8, s19, s8
	s_add_i32 s23, s22, s0
	s_mul_i32 s22, s19, s15
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_lshl_b64 s[22:23], s[22:23], 2
	s_ashr_i32 s9, s8, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s20, s22
	s_addc_u32 s19, s21, s23
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	s_mov_b32 s19, s3
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v9, vcc_lo, s1, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[9:10]
	v_mov_b32_e32 v9, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v9, v[2:3], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v4, vcc_lo, v4, 16
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, s0, v2, 64
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v9
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[4:5]
	v_add_nc_u32_e32 v8, 64, v8
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_or_b32 s19, vcc_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow156
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b32 s12, s11, 2
	s_lshl_b32 s8, s13, 2
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s12, v0
	s_cbranch_execz .LBB0_10
; %bb.6:                                ; %.lr.ph101
	s_mov_b32 s13, 0
	s_mul_i32 s0, s16, s11
	s_mov_b32 s9, s13
	s_ashr_i32 s3, s0, 31
	s_lshl_b64 s[20:21], s[8:9], 2
	v_and_b32_e32 v2, 3, v6
	s_mul_i32 s3, s3, s15
	s_add_u32 s9, s4, s20
	s_mul_hi_u32 s4, s0, s15
	s_addc_u32 s19, s5, s21
	s_add_i32 s5, s4, s3
	s_mul_i32 s4, s0, s15
	v_lshrrev_b32_e32 v4, 2, v0
	v_lshlrev_b32_e32 v3, 2, v2
	s_lshl_b64 s[4:5], s[4:5], 2
	v_add_nc_u32_e32 v9, s2, v0
	s_add_u32 s0, s9, s4
	s_addc_u32 s3, s19, s5
	v_add_co_u32 v5, s0, s0, v3
	v_mov_b32_e32 v3, 0
	v_cmp_gt_u32_e32 vcc_lo, s16, v2
	v_mul_lo_u32 v2, s16, v4
	v_add_co_ci_u32_e64 v8, null, s3, 0, s0
	v_lshl_add_u32 v9, v9, 2, 0
	s_lshl_b32 s2, s16, 2
	s_mov_b32 s3, s13
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e64 s0, s11, v4
	v_mov_b32_e32 v10, 0
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v5, v10
	v_add_co_ci_u32_e64 v11, s0, v8, v11, s0
	global_load_b32 v10, v[10:11], off
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_add_co_u32 v0, s0, v0, 16
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v10
	v_add_nc_u32_e32 v9, 64, v9
	v_add_nc_u32_e32 v2, s2, v2
	v_cmp_le_u64_e64 s0, s[12:13], v[0:1]
	v_add_nc_u32_e32 v4, 4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s0, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_7
.LBB0_10:                               ; %Flow154
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v0, s8, v6
	v_add_nc_u32_e32 v1, s14, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u32_e32 vcc_lo, s18, v0
	v_cmp_gt_u32_e64 s0, s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ; %.preheader
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB0_14
; %bb.12:                               ; %.lr.ph104
	v_mul_lo_u32 v2, v7, s10
	v_lshlrev_b32_e32 v3, 2, v6
	s_lshl_b32 s0, s10, 4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v4, v2, 2, 0
	v_mov_b32_e32 v2, 0
	v_add3_u32 v3, 0, s0, v3
.LBB0_13:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v4
	ds_load_b32 v6, v3
	v_add_nc_u32_e32 v4, 4, v4
	v_add_nc_u32_e32 v3, 16, v3
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v5, v6
	s_cbranch_scc0 .LBB0_13
	s_branch .LBB0_15
.LBB0_14:
	v_mov_b32_e32 v2, 0
.LBB0_15:                               ; %Flow151
	v_mul_lo_u32 v3, v1, s18
	s_mul_i32 s0, s18, s17
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s1, s0, 31
	s_mul_hi_u32 s2, s0, s15
	s_mul_i32 s1, s1, s15
	s_mul_i32 s0, s0, s15
	s_add_i32 s1, s2, s1
	v_mov_b32_e32 v1, v4
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_u32 s0, s6, s0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_addc_u32 s1, s7, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 52
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.Lfunc_end0:
	.size	_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .Lfunc_end0-_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 916
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 52
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
