#include <stdlib.h>
#include <stdio.h>


__host__ void matrix_multiply_cpu(int n, float **a, float **b, float **c) {
	int i, j, k;
	float tc;
	for (i=0; i<n; i++) {
		for (j=0; j<n; j++) {
			tc = 0;
			for (k=0; k<n; k++) tc += a[i][k]*b[k][j];
			c[i][j] = tc;
		}
	}
}


__global__ void matrix_multiply_gpu(int n, float *a, float *b, float *c) {
	int i = blockIdx.x*blockDim.x + threadIdx.x;
	int j = blockIdx.y*blockDim.y + threadIdx.y;

	float tc = 0;
	for (int k=0; k<n; k++) tc += a[i*n+k]*b[k*n+j];
	c[i*n+j] = tc;
}


int main() {
	int n=256;	// n x n matrix; must be a multiple of 16
	int i,j;

	// Allocate matrices in the host memory
	float **a, **b, **c_cpu, **c_gpu;

	a = (float **) malloc(n*sizeof(float *));
	a[0] = (float *) malloc(n*n*sizeof(float));
	for (i=0; i<n; i++) a[i] = a[0] + i*n;

	b = (float **) malloc(n*sizeof(float *));
	b[0] = (float *) malloc(n*n*sizeof(float));
	for (i=0; i<n; i++) b[i] = b[0] + i*n;

	c_cpu = (float **) calloc(n, sizeof(float *));
	c_cpu[0] = (float *) calloc(n*n, sizeof(float));
	for (i=0; i<n; i++) c_cpu[i] = c_cpu[0] + i*n;

	c_gpu = (float **) calloc(n, sizeof(float *));
	c_gpu[0] = (float *) calloc(n*n, sizeof(float));
	for (i=0; i<n; i++) c_gpu[i] = c_gpu[0] + i*n;

	// Initialize the matrix a, b
	for (i=0; i<n*n; i++) {
		a[0][i] = (i/111)*(i%11)*0.1;
		b[0][i] = (i/113)*(i%13)*0.1;
	}

	// Allocate matrices in the device memory
	float *a_dev, *b_dev, *c_dev;
	cudaMalloc ( (void**) &a_dev, n*n*sizeof(float) );
	cudaMalloc ( (void**) &b_dev, n*n*sizeof(float) );
	cudaMalloc ( (void**) &c_dev, n*n*sizeof(float) );
	
	// Copy the a, b matrices from host to device
	cudaMemcpy ( a_dev, a[0], n*n*sizeof(float), cudaMemcpyHostToDevice );
	cudaMemcpy ( b_dev, b[0], n*n*sizeof(float), cudaMemcpyHostToDevice );
	cudaMemcpy ( c_dev, c_gpu[0], n*n*sizeof(float), cudaMemcpyHostToDevice );
	
	// CUDA Kernel execution
	dim3 dimBlock(16,16,1);
	dim3 dimGrid(n/16,n/16);
	matrix_multiply_gpu <<<dimGrid,dimBlock>>> (n, a_dev, b_dev, c_dev);

	// Copy the a, b matrices from host to device
	cudaMemcpy (c_gpu[0], c_dev, n*n*sizeof(float), cudaMemcpyDeviceToHost);


	// CPU Function execution
	matrix_multiply_cpu(n, a, b, c_cpu);


	// Verify two results
	float v;
	for (i=0; i<n; i++) {
		for (j=0; j<n; j++) {
			v = c_cpu[i][j] - c_gpu[i][j];
			if (v > 0.01) printf("c[%d][%d]=%g\n", i, j, v);
		}
	}
}

	.file	"tmpxft_00308f93_00000000-6_000_matrix_multiply.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z19matrix_multiply_cpuiPPfS0_S0_
	.type	_Z19matrix_multiply_cpuiPPfS0_S0_, @function
_Z19matrix_multiply_cpuiPPfS0_S0_:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	%rsi, %r9
	xorl	%esi, %esi
	cmpl	%esi, %edi
	jg	.L13
	ret
.L13:
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
.L11:
	movq	(%r9,%rsi,8), %r11
	movq	(%rcx,%rsi,8), %r10
	xorl	%eax, %eax
.L7:
	leaq	0(,%rax,4), %rbx
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
.L4:
	movq	(%rdx,%r8,8), %r14
	movss	(%r14,%rbx), %xmm1
	mulss	(%r11,%r8,4), %xmm1
	incq	%r8
	addss	%xmm1, %xmm0
	cmpl	%r8d, %edi
	jg	.L4
	movss	%xmm0, (%r10,%rax,4)
	incq	%rax
	cmpl	%eax, %edi
	jg	.L7
	incq	%rsi
	cmpl	%esi, %edi
	jg	.L11
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z19matrix_multiply_cpuiPPfS0_S0_, .-_Z19matrix_multiply_cpuiPPfS0_S0_
	.globl	_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_
	.type	_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_, @function
_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19matrix_multiply_gpuiPfS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_, .-_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_
	.globl	_Z19matrix_multiply_gpuiPfS_S_
	.type	_Z19matrix_multiply_gpuiPfS_S_, @function
_Z19matrix_multiply_gpuiPfS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_
	.cfi_endproc
.LFE2054:
	.size	_Z19matrix_multiply_gpuiPfS_S_, .-_Z19matrix_multiply_gpuiPfS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"c[%d][%d]=%g\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$2048, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$262144, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rax, (%r12)
	xorl	%eax, %eax
.L21:
	movq	%rax, %rdx
	salq	$10, %rdx
	addq	(%r12), %rdx
	movq	%rdx, (%r12,%rax,8)
	incq	%rax
	cmpq	$256, %rax
	jne	.L21
	movl	$2048, %edi
	call	malloc@PLT
	movl	$262144, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rax, 0(%r13)
	xorl	%eax, %eax
.L22:
	movq	%rax, %rdx
	salq	$10, %rdx
	addq	0(%r13), %rdx
	movq	%rdx, 0(%r13,%rax,8)
	incq	%rax
	cmpq	$256, %rax
	jne	.L22
	movl	$8, %esi
	movl	$256, %edi
	call	calloc@PLT
	movl	$4, %esi
	movl	$65536, %edi
	movq	%rax, %rbx
	call	calloc@PLT
	movq	%rax, (%rbx)
	xorl	%eax, %eax
.L23:
	movq	%rax, %rdx
	salq	$10, %rdx
	addq	(%rbx), %rdx
	movq	%rdx, (%rbx,%rax,8)
	incq	%rax
	cmpq	$256, %rax
	jne	.L23
	movl	$8, %esi
	movl	$256, %edi
	call	calloc@PLT
	movl	$4, %esi
	movl	$65536, %edi
	movq	%rax, %rbp
	call	calloc@PLT
	movq	%rax, 0(%rbp)
	xorl	%eax, %eax
.L24:
	movq	%rax, %rdx
	salq	$10, %rdx
	addq	0(%rbp), %rdx
	movq	%rdx, 0(%rbp,%rax,8)
	incq	%rax
	cmpq	$256, %rax
	jne	.L24
	movq	(%r12), %r15
	movq	0(%r13), %r14
	xorl	%esi, %esi
	movl	$111, %r10d
	movsd	.LC1(%rip), %xmm1
	movl	$11, %r9d
	movl	$113, %r8d
	movl	$13, %r11d
.L25:
	movl	%esi, %eax
	cltd
	idivl	%r10d
	movl	%eax, %edi
	movl	%esi, %eax
	cltd
	idivl	%r9d
	movl	%esi, %eax
	imull	%edx, %edi
	cltd
	idivl	%r8d
	cvtsi2sdl	%edi, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r15,%rsi,4)
	movl	%eax, %edi
	movl	%esi, %eax
	cltd
	idivl	%r11d
	imull	%edx, %edi
	cvtsi2sdl	%edi, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r14,%rsi,4)
	incq	%rsi
	cmpq	$65536, %rsi
	jne	.L25
	leaq	8(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	movq	0(%rbp), %r14
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$262144, %edx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdi
	movl	$1, %esi
	movl	$1, 40(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$256, %edi
	movq	8(%rsp), %rsi
	call	_Z44__device_stub__Z19matrix_multiply_gpuiPfS_S_iPfS_S_
.L26:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$262144, %edx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movq	%r13, %rdx
	movq	%rbx, %rcx
	movq	%r12, %rsi
	movl	$256, %edi
	xorl	%r13d, %r13d
	call	_Z19matrix_multiply_cpuiPPfS0_S0_
.L27:
	movl	%r13d, %r14d
	xorl	%r12d, %r12d
.L30:
	movq	(%rbx,%r13,8), %rdx
	movq	0(%rbp,%r13,8), %rax
	movss	(%rdx,%r12,4), %xmm0
	subss	(%rax,%r12,4), %xmm0
	cvtss2sd	%xmm0, %xmm0
	comisd	.LC2(%rip), %xmm0
	jbe	.L28
	movl	%r12d, %ecx
	movl	%r14d, %edx
	leaq	.LC3(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
.L28:
	incq	%r12
	cmpq	$256, %r12
	jne	.L30
	incq	%r13
	cmpq	$256, %r13
	jne	.L27
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z19matrix_multiply_gpuiPfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19matrix_multiply_gpuiPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	-1717986918
	.long	1069128089
	.align 8
.LC2:
	.long	1202590843
	.long	1065646817
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>


__host__ void matrix_multiply_cpu(int n, float **a, float **b, float **c) {
	int i, j, k;
	float tc;
	for (i=0; i<n; i++) {
		for (j=0; j<n; j++) {
			tc = 0;
			for (k=0; k<n; k++) tc += a[i][k]*b[k][j];
			c[i][j] = tc;
		}
	}
}


__global__ void matrix_multiply_gpu(int n, float *a, float *b, float *c) {
	int i = blockIdx.x*blockDim.x + threadIdx.x;
	int j = blockIdx.y*blockDim.y + threadIdx.y;

	float tc = 0;
	for (int k=0; k<n; k++) tc += a[i*n+k]*b[k*n+j];
	c[i*n+j] = tc;
}


int main() {
	int n=256;	// n x n matrix; must be a multiple of 16
	int i,j;

	// Allocate matrices in the host memory
	float **a, **b, **c_cpu, **c_gpu;

	a = (float **) malloc(n*sizeof(float *));
	a[0] = (float *) malloc(n*n*sizeof(float));
	for (i=0; i<n; i++) a[i] = a[0] + i*n;

	b = (float **) malloc(n*sizeof(float *));
	b[0] = (float *) malloc(n*n*sizeof(float));
	for (i=0; i<n; i++) b[i] = b[0] + i*n;

	c_cpu = (float **) calloc(n, sizeof(float *));
	c_cpu[0] = (float *) calloc(n*n, sizeof(float));
	for (i=0; i<n; i++) c_cpu[i] = c_cpu[0] + i*n;

	c_gpu = (float **) calloc(n, sizeof(float *));
	c_gpu[0] = (float *) calloc(n*n, sizeof(float));
	for (i=0; i<n; i++) c_gpu[i] = c_gpu[0] + i*n;

	// Initialize the matrix a, b
	for (i=0; i<n*n; i++) {
		a[0][i] = (i/111)*(i%11)*0.1;
		b[0][i] = (i/113)*(i%13)*0.1;
	}

	// Allocate matrices in the device memory
	float *a_dev, *b_dev, *c_dev;
	hipMalloc ( (void**) &a_dev, n*n*sizeof(float) );
	hipMalloc ( (void**) &b_dev, n*n*sizeof(float) );
	hipMalloc ( (void**) &c_dev, n*n*sizeof(float) );
	
	// Copy the a, b matrices from host to device
	hipMemcpy ( a_dev, a[0], n*n*sizeof(float), hipMemcpyHostToDevice );
	hipMemcpy ( b_dev, b[0], n*n*sizeof(float), hipMemcpyHostToDevice );
	hipMemcpy ( c_dev, c_gpu[0], n*n*sizeof(float), hipMemcpyHostToDevice );
	
	// CUDA Kernel execution
	dim3 dimBlock(16,16,1);
	dim3 dimGrid(n/16,n/16);
	matrix_multiply_gpu <<<dimGrid,dimBlock>>> (n, a_dev, b_dev, c_dev);

	// Copy the a, b matrices from host to device
	hipMemcpy (c_gpu[0], c_dev, n*n*sizeof(float), hipMemcpyDeviceToHost);


	// CPU Function execution
	matrix_multiply_cpu(n, a, b, c_cpu);


	// Verify two results
	float v;
	for (i=0; i<n; i++) {
		for (j=0; j<n; j++) {
			v = c_cpu[i][j] - c_gpu[i][j];
			if (v > 0.01) printf("c[%d][%d]=%g\n", i, j, v);
		}
	}
}

	.text
	.file	"000_matrix_multiply.hip"
	.globl	_Z19matrix_multiply_cpuiPPfS0_S0_ # -- Begin function _Z19matrix_multiply_cpuiPPfS0_S0_
	.type	_Z19matrix_multiply_cpuiPPfS0_S0_,@function
_Z19matrix_multiply_cpuiPPfS0_S0_:      # @_Z19matrix_multiply_cpuiPPfS0_S0_
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jle	.LBB0_8
# %bb.1:                                # %.preheader23.lr.ph
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%edi, %eax
	xorl	%edi, %edi
.LBB0_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_3 Depth 2
                                        #       Child Loop BB0_4 Depth 3
	movq	(%rcx,%rdi,8), %r8
	movq	(%rsi,%rdi,8), %r9
	xorl	%r10d, %r10d
.LBB0_3:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_4 Depth 3
	xorps	%xmm0, %xmm0
	xorl	%r11d, %r11d
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r9,%r11,4), %xmm1             # xmm1 = mem[0],zero,zero,zero
	movq	(%rdx,%r11,8), %rbx
	mulss	(%rbx,%r10,4), %xmm1
	addss	%xmm1, %xmm0
	incq	%r11
	cmpq	%r11, %rax
	jne	.LBB0_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_3 Depth=2
	movss	%xmm0, (%r8,%r10,4)
	incq	%r10
	cmpq	%rax, %r10
	jne	.LBB0_3
# %bb.6:                                # %._crit_edge27
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%rdi
	cmpq	%rax, %rdi
	jne	.LBB0_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
.LBB0_8:                                # %._crit_edge29
	retq
.Lfunc_end0:
	.size	_Z19matrix_multiply_cpuiPPfS0_S0_, .Lfunc_end0-_Z19matrix_multiply_cpuiPPfS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__matrix_multiply_gpuiPfS_S_ # -- Begin function _Z34__device_stub__matrix_multiply_gpuiPfS_S_
	.type	_Z34__device_stub__matrix_multiply_gpuiPfS_S_,@function
_Z34__device_stub__matrix_multiply_gpuiPfS_S_: # @_Z34__device_stub__matrix_multiply_gpuiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19matrix_multiply_gpuiPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__matrix_multiply_gpuiPfS_S_, .Lfunc_end1-_Z34__device_stub__matrix_multiply_gpuiPfS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
.LCPI2_1:
	.quad	0x3f847ae147ae147b              # double 0.01
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %rbx
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, (%rbx)
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movq	(%rbx), %rdx
	addq	%rax, %rdx
	movq	%rdx, (%rcx)
	addq	$1024, %rax                     # imm = 0x400
	addq	$8, %rcx
	cmpq	$262144, %rax                   # imm = 0x40000
	jne	.LBB2_1
# %bb.2:
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %r15
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, (%r15)
	xorl	%eax, %eax
	movq	%r15, %rcx
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movq	(%r15), %rdx
	addq	%rax, %rdx
	movq	%rdx, (%rcx)
	addq	$1024, %rax                     # imm = 0x400
	addq	$8, %rcx
	cmpq	$262144, %rax                   # imm = 0x40000
	jne	.LBB2_3
# %bb.4:
	movl	$256, %edi                      # imm = 0x100
	movl	$8, %esi
	callq	calloc
	movq	%rax, %r14
	movl	$65536, %edi                    # imm = 0x10000
	movl	$4, %esi
	callq	calloc
	movq	%rax, (%r14)
	xorl	%eax, %eax
	movq	%r14, %rcx
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movq	(%r14), %rdx
	addq	%rax, %rdx
	movq	%rdx, (%rcx)
	addq	$1024, %rax                     # imm = 0x400
	addq	$8, %rcx
	cmpq	$262144, %rax                   # imm = 0x40000
	jne	.LBB2_5
# %bb.6:
	movl	$256, %edi                      # imm = 0x100
	movl	$8, %esi
	callq	calloc
	movq	%rax, %r12
	movl	$65536, %edi                    # imm = 0x10000
	movl	$4, %esi
	callq	calloc
	movq	%rax, (%r12)
	xorl	%eax, %eax
	movq	%r12, %rcx
.LBB2_7:                                # =>This Inner Loop Header: Depth=1
	movq	(%r12), %rdx
	addq	%rax, %rdx
	movq	%rdx, (%rcx)
	addq	$1024, %rax                     # imm = 0x400
	addq	$8, %rcx
	cmpq	$262144, %rax                   # imm = 0x40000
	jne	.LBB2_7
# %bb.8:                                # %.preheader118
	movq	(%rbx), %rbp
	movq	(%r15), %r13
	xorl	%eax, %eax
	movl	$65535, %ecx                    # imm = 0xFFFF
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
.LBB2_9:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, %edx
	andl	%ecx, %edx
	imull	$47663, %edx, %esi              # imm = 0xBA2F
	shrl	$19, %esi
	imull	$-11, %esi, %esi
	imull	$20165, %edx, %edi              # imm = 0x4EC5
	imull	$37787, %edx, %r8d              # imm = 0x939B
	shrl	$22, %r8d
	addl	%eax, %esi
	imull	%r8d, %esi
	andl	%ecx, %esi
	xorps	%xmm1, %xmm1
	cvtsi2sd	%esi, %xmm1
	shrl	$18, %edi
	mulsd	%xmm0, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	imull	$-13, %edi, %esi
	imull	$18559, %edx, %edx              # imm = 0x487F
	shrl	$21, %edx
	addl	%eax, %esi
	imull	%edx, %esi
	andl	%ecx, %esi
	xorps	%xmm2, %xmm2
	cvtsi2sd	%esi, %xmm2
	mulsd	%xmm0, %xmm2
	cvtsd2ss	%xmm2, %xmm2
	movss	%xmm1, (%rbp,%rax,4)
	movss	%xmm2, (%r13,%rax,4)
	incq	%rax
	cmpq	$65536, %rax                    # imm = 0x10000
	jne	.LBB2_9
# %bb.10:
	leaq	16(%rsp), %rdi
	movl	$262144, %esi                   # imm = 0x40000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$262144, %esi                   # imm = 0x40000
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$262144, %esi                   # imm = 0x40000
	callq	hipMalloc
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movq	(%r12), %r13
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$68719476752, %rdi              # imm = 0x1000000010
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.11:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	$256, %edi                      # imm = 0x100
	callq	_Z34__device_stub__matrix_multiply_gpuiPfS_S_
.LBB2_12:
	movq	(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
.LBB2_13:                               # %.preheader.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_14 Depth 2
                                        #       Child Loop BB2_15 Depth 3
	movq	(%r14,%rax,8), %rcx
	movq	(%rbx,%rax,8), %rdx
	xorl	%esi, %esi
.LBB2_14:                               # %.preheader.i
                                        #   Parent Loop BB2_13 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_15 Depth 3
	xorpd	%xmm0, %xmm0
	xorl	%edi, %edi
.LBB2_15:                               #   Parent Loop BB2_13 Depth=1
                                        #     Parent Loop BB2_14 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rdx,%rdi,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	movq	(%r15,%rdi,8), %r8
	mulss	(%r8,%rsi,4), %xmm1
	addss	%xmm1, %xmm0
	incq	%rdi
	cmpq	$256, %rdi                      # imm = 0x100
	jne	.LBB2_15
# %bb.16:                               # %._crit_edge.i
                                        #   in Loop: Header=BB2_14 Depth=2
	movss	%xmm0, (%rcx,%rsi,4)
	incq	%rsi
	cmpq	$256, %rsi                      # imm = 0x100
	jne	.LBB2_14
# %bb.17:                               # %._crit_edge27.i
                                        #   in Loop: Header=BB2_13 Depth=1
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB2_13
# %bb.18:                               # %.preheader.preheader
	xorl	%ebx, %ebx
	movsd	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero
.LBB2_19:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_20 Depth 2
	movq	(%r14,%rbx,8), %r13
	movq	(%r12,%rbx,8), %rbp
	xorl	%r15d, %r15d
.LBB2_20:                               #   Parent Loop BB2_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r13,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	subss	(%rbp,%r15,4), %xmm0
	cvtss2sd	%xmm0, %xmm0
	ucomisd	%xmm1, %xmm0
	jbe	.LBB2_22
# %bb.21:                               #   in Loop: Header=BB2_20 Depth=2
	movl	$.L.str, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movb	$1, %al
	callq	printf
	movsd	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero
.LBB2_22:                               #   in Loop: Header=BB2_20 Depth=2
	incq	%r15
	cmpq	$256, %r15                      # imm = 0x100
	jne	.LBB2_20
# %bb.23:                               # %_Z19matrix_multiply_cpuiPPfS0_S0_.exit
                                        #   in Loop: Header=BB2_19 Depth=1
	incq	%rbx
	cmpq	$256, %rbx                      # imm = 0x100
	jne	.LBB2_19
# %bb.24:
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19matrix_multiply_gpuiPfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19matrix_multiply_gpuiPfS_S_,@object # @_Z19matrix_multiply_gpuiPfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z19matrix_multiply_gpuiPfS_S_
	.p2align	3, 0x0
_Z19matrix_multiply_gpuiPfS_S_:
	.quad	_Z34__device_stub__matrix_multiply_gpuiPfS_S_
	.size	_Z19matrix_multiply_gpuiPfS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"c[%d][%d]=%g\n"
	.size	.L.str, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19matrix_multiply_gpuiPfS_S_"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__matrix_multiply_gpuiPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19matrix_multiply_gpuiPfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19matrix_multiply_gpuiPfS_S_ ; -- Begin function _Z19matrix_multiply_gpuiPfS_S_
	.globl	_Z19matrix_multiply_gpuiPfS_S_
	.p2align	8
	.type	_Z19matrix_multiply_gpuiPfS_S_,@function
_Z19matrix_multiply_gpuiPfS_S_:         ; @_Z19matrix_multiply_gpuiPfS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s7, s[0:1], 0x2c
	s_load_b32 s6, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	s_load_b128 s[0:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s7, 0xffff
	s_lshr_b32 s7, s7, 16
	v_mad_u64_u32 v[2:3], null, s14, s8, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_cmp_lt_i32 s6, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, s15, s7, v[3:4]
	v_mul_lo_u32 v1, v2, s6
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_mov_b32 s0, s6
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s0, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_mov_b32_e32 v6, 0
.LBB0_4:                                ; %Flow40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19matrix_multiply_gpuiPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19matrix_multiply_gpuiPfS_S_, .Lfunc_end0-_Z19matrix_multiply_gpuiPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19matrix_multiply_gpuiPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19matrix_multiply_gpuiPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
