/**
 * demonstration of shared memory. Kernel performs task of contracting consecutive vector elements. example:
 * RADIUS = 1 (means three consecutive numbers, (current, left and right), are added up)
 * input:   1   3   4   2   8   1   2 
 * output:  4   8   9   14  11  11  3
 */

#include <stdio.h>
#include <stdlib.h>

#define THREADS_PER_BLOCK 4
#define RADIUS 1
 // length of input array
#define N 16


__global__ void contr_vec_1d(int *inp, int *out) {

    __shared__ int block_mem[THREADS_PER_BLOCK + 2 * RADIUS];

    int glob_index = threadIdx.x + blockIdx.x * blockDim.x; 
    int loc_index = threadIdx.x + RADIUS;

    // Read input elements into shared memory
    block_mem[loc_index] = inp[glob_index]; 

    // read borders of current block
    if (threadIdx.x < RADIUS) {

        int before_index = glob_index - RADIUS;
        int after_index = glob_index + THREADS_PER_BLOCK;

        block_mem[loc_index - RADIUS] = (before_index < 0) ? 0 : inp[before_index];
        block_mem[loc_index + THREADS_PER_BLOCK] = (after_index >= N) ? 0 : inp[after_index]; 
    }

    // Synchronize (ensure all the data in block_mem is available)
    __syncthreads();

 
    // caluclate result
    int res = 0;
    for (int offset = -RADIUS ; offset <= RADIUS ; offset++){
        res += block_mem[loc_index + offset];
    }

    // Store the result
    out[glob_index] = res;
}



void random_ints(int *start, int num) {
    for (unsigned int i = 0; i < num; i++) {
        start[i] = rand()%10;
    }
}


int main(void) {

    int *inp, *out; //host cpies
    int *d_inp, *d_out; //device copies

    int size = N * sizeof(int);

    // Alloc space for device copies
    cudaMalloc((void **)&d_inp, size);
    cudaMalloc((void **)&d_out, size);

    // Alloc space for host copies of a, b, c and setup input values
    inp = (int *)malloc(size); random_ints(inp, N);
    out = (int *)malloc(size);

    // Copy inputs to device
    cudaMemcpy(d_inp, inp, size, cudaMemcpyHostToDevice);


    //numb_block should be integer!
    int num_blocks = N/THREADS_PER_BLOCK;


    // Launch add() kernel on GPU with N blocks
    contr_vec_1d<<<num_blocks,THREADS_PER_BLOCK>>>(d_inp, d_out);

    // Copy result back to host
    cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);


    printf("kernel successfull finished \n %5s %5s \n", "inp", "out");

    for (unsigned int i = 0; i < N; i++) {

        printf("%5d %5d \n", inp[i], out[i]);
    }
    // Cleanup
    free(inp); free(out);
    cudaFree(d_inp); cudaFree(d_out);
    return 0;
}

	.file	"tmpxft_00388e4c_00000000-6_contr_vec.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11random_intsPii
	.type	_Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$10, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
.L3:
	cmpl	%ebp, %ebx
	jnb	.L7
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11random_intsPii, .-_Z11random_intsPii
	.globl	_Z34__device_stub__Z12contr_vec_1dPiS_PiS_
	.type	_Z34__device_stub__Z12contr_vec_1dPiS_PiS_, @function
_Z34__device_stub__Z12contr_vec_1dPiS_PiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12contr_vec_1dPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z34__device_stub__Z12contr_vec_1dPiS_PiS_, .-_Z34__device_stub__Z12contr_vec_1dPiS_PiS_
	.globl	_Z12contr_vec_1dPiS_
	.type	_Z12contr_vec_1dPiS_, @function
_Z12contr_vec_1dPiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z12contr_vec_1dPiS_PiS_
	.cfi_endproc
.LFE2054:
	.size	_Z12contr_vec_1dPiS_, .-_Z12contr_vec_1dPiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"out"
.LC1:
	.string	"inp"
.LC2:
	.string	"kernel successfull finished \n %5s %5s \n"
.LC3:
	.string	"%5d %5d \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$64, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movl	$64, %esi
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$64, %edi
	call	malloc@PLT
	movl	$16, %esi
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	_Z11random_intsPii
	movl	$64, %edi
	call	malloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$64, %edx
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z34__device_stub__Z12contr_vec_1dPiS_PiS_
.L14:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%r12d, %r12d
	movl	$64, %edx
	leaq	.LC3(%rip), %r13
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rcx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rdx
	leaq	.LC2(%rip), %rsi
	call	__printf_chk@PLT
.L15:
	movl	0(%rbp,%r12), %ecx
	movl	(%rbx,%r12), %edx
	movq	%r13, %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	addq	$4, %r12
	call	__printf_chk@PLT
	cmpq	$64, %r12
	jne	.L15
	movq	%rbx, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z12contr_vec_1dPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12contr_vec_1dPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * demonstration of shared memory. Kernel performs task of contracting consecutive vector elements. example:
 * RADIUS = 1 (means three consecutive numbers, (current, left and right), are added up)
 * input:   1   3   4   2   8   1   2 
 * output:  4   8   9   14  11  11  3
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

#define THREADS_PER_BLOCK 4
#define RADIUS 1
 // length of input array
#define N 16


__global__ void contr_vec_1d(int *inp, int *out) {

    __shared__ int block_mem[THREADS_PER_BLOCK + 2 * RADIUS];

    int glob_index = threadIdx.x + blockIdx.x * blockDim.x; 
    int loc_index = threadIdx.x + RADIUS;

    // Read input elements into shared memory
    block_mem[loc_index] = inp[glob_index]; 

    // read borders of current block
    if (threadIdx.x < RADIUS) {

        int before_index = glob_index - RADIUS;
        int after_index = glob_index + THREADS_PER_BLOCK;

        block_mem[loc_index - RADIUS] = (before_index < 0) ? 0 : inp[before_index];
        block_mem[loc_index + THREADS_PER_BLOCK] = (after_index >= N) ? 0 : inp[after_index]; 
    }

    // Synchronize (ensure all the data in block_mem is available)
    __syncthreads();

 
    // caluclate result
    int res = 0;
    for (int offset = -RADIUS ; offset <= RADIUS ; offset++){
        res += block_mem[loc_index + offset];
    }

    // Store the result
    out[glob_index] = res;
}



void random_ints(int *start, int num) {
    for (unsigned int i = 0; i < num; i++) {
        start[i] = rand()%10;
    }
}


int main(void) {

    int *inp, *out; //host cpies
    int *d_inp, *d_out; //device copies

    int size = N * sizeof(int);

    // Alloc space for device copies
    hipMalloc((void **)&d_inp, size);
    hipMalloc((void **)&d_out, size);

    // Alloc space for host copies of a, b, c and setup input values
    inp = (int *)malloc(size); random_ints(inp, N);
    out = (int *)malloc(size);

    // Copy inputs to device
    hipMemcpy(d_inp, inp, size, hipMemcpyHostToDevice);


    //numb_block should be integer!
    int num_blocks = N/THREADS_PER_BLOCK;


    // Launch add() kernel on GPU with N blocks
    contr_vec_1d<<<num_blocks,THREADS_PER_BLOCK>>>(d_inp, d_out);

    // Copy result back to host
    hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);


    printf("kernel successfull finished \n %5s %5s \n", "inp", "out");

    for (unsigned int i = 0; i < N; i++) {

        printf("%5d %5d \n", inp[i], out[i]);
    }
    // Cleanup
    free(inp); free(out);
    hipFree(d_inp); hipFree(d_out);
    return 0;
}

	.text
	.file	"contr_vec.hip"
	.globl	_Z27__device_stub__contr_vec_1dPiS_ # -- Begin function _Z27__device_stub__contr_vec_1dPiS_
	.type	_Z27__device_stub__contr_vec_1dPiS_,@function
_Z27__device_stub__contr_vec_1dPiS_:    # @_Z27__device_stub__contr_vec_1dPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12contr_vec_1dPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__contr_vec_1dPiS_, .Lfunc_end0-_Z27__device_stub__contr_vec_1dPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11random_intsPii              # -- Begin function _Z11random_intsPii
	.type	_Z11random_intsPii,@function
_Z11random_intsPii:                     # @_Z11random_intsPii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	je	.LBB1_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB1_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB1_4:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	8(%rsp), %rdi
	movl	$64, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$64, %esi
	callq	hipMalloc
	movl	$64, %edi
	callq	malloc
	movq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB2_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r14,4)
	incq	%r14
	cmpq	$16, %r14
	jne	.LBB2_1
# %bb.2:                                # %_Z11random_intsPii.exit
	movl	$64, %edi
	callq	malloc
	movq	%rax, %r14
	movq	8(%rsp), %rdi
	movl	$64, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z27__device_stub__contr_vec_1dPiS_
.LBB2_4:
	movq	(%rsp), %rsi
	movl	$64, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	movl	$.L.str.2, %edx
	xorl	%eax, %eax
	callq	printf
	xorl	%r15d, %r15d
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	(%r14,%r15,4), %edx
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$16, %r15
	jne	.LBB2_5
# %bb.6:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12contr_vec_1dPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12contr_vec_1dPiS_,@object    # @_Z12contr_vec_1dPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z12contr_vec_1dPiS_
	.p2align	3, 0x0
_Z12contr_vec_1dPiS_:
	.quad	_Z27__device_stub__contr_vec_1dPiS_
	.size	_Z12contr_vec_1dPiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"kernel successfull finished \n %5s %5s \n"
	.size	.L.str, 40

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"inp"
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"out"
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%5d %5d \n"
	.size	.L.str.3, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12contr_vec_1dPiS_"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__contr_vec_1dPiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12contr_vec_1dPiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12contr_vec_1dPiS_    ; -- Begin function _Z12contr_vec_1dPiS_
	.globl	_Z12contr_vec_1dPiS_
	.p2align	8
	.type	_Z12contr_vec_1dPiS_,@function
_Z12contr_vec_1dPiS_:                   ; @_Z12contr_vec_1dPiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v7, 2, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[5:6]
	v_add_co_u32 v3, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6 offset:4
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v6, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	v_add_co_u32 v8, vcc_lo, s0, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v6, v[8:9], off offset:-4
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s5
	v_cmp_gt_i32_e32 vcc_lo, 12, v5
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v6
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:
	global_load_b32 v5, v[3:4], off offset:16
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v5 offset:20
.LBB0_6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[3:4], v7 offset1:1
	ds_load_b32 v0, v7 offset:8
	s_waitcnt lgkmcnt(0)
	v_add3_u32 v3, v4, v3, v0
	v_add_co_u32 v0, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12contr_vec_1dPiS_
		.amdhsa_group_segment_fixed_size 24
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12contr_vec_1dPiS_, .Lfunc_end0-_Z12contr_vec_1dPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 24 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 24
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12contr_vec_1dPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12contr_vec_1dPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
