#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>

#define X 0
#define Y 1 

bool isSumOfLengthEqualtoD(int *, int *, int, int);
bool isPowerOfTwo(int);

__global__ void mergeSmallBatch_k(int * A, int * sizeA, int *B, int *sizeB, int *M, const int d, int N){

	// Question 4 : Indices importantes
	const int tidx = threadIdx.x % d;				// Numéro de la diagonal dans le tableau numéro Qt
	const int Qt = (threadIdx.x - tidx) / d;			// Numéro du tableau par rapport au tableau shared
	const int gbx = Qt + blockIdx.x * (blockDim.x / d);		// Numéro du tableau par rapport au tableau global

	const int sizeAi = sizeA[gbx];				// Taille du tableau considéré
	const int sizeBi = sizeB[gbx];				// Taille du tableau considéré

	__shared__ int Atemp[1024];				// Tableau partagé par les threads d'un bloc
	__shared__ int Btemp[1024];				// Tableau partagé par les threads d'un bloc

	Atemp[Qt * d + tidx] = A[gbx * d + tidx];		// Remplissage du tableau
	Btemp[Qt * d + tidx] = B[gbx * d + tidx];		// Remplissage du tableau

	__syncthreads();					// Attente de la synchronisation de tous les threads du bloc
//	printf("blockId.x = %d | threadIdx. x = %d | tidx = %d | Qt = %d | gbx = %d\n", blockIdx.x, threadIdx.x, tidx, Qt, gbx);

	if (gbx * d + tidx >= N * d){
		return;
	}
	// ======================== //
	//        Merge path        //
	// ======================== //
	int K[2];
	int P[2];

	if (tidx > sizeAi) {
		K[X] = tidx - sizeAi;
		K[Y] = sizeAi;
		P[X] = sizeAi;
		P[Y] = tidx - sizeAi;
	}
	else {
		K[X] = 0;
		K[Y] = tidx;
		P[X] = tidx;
		P[Y] = 0;
	}

	while (1) {
		int offset = (abs(K[Y] - P[Y]))/2;
		int Q[2] = {K[X] + offset, K[Y] - offset};

		if (Q[Y] >= 0 && Q[X] <= sizeBi && (Q[Y] == sizeAi || Q[X] == 0 || Atemp[Qt*d + Q[Y]] > Btemp[Qt*d + Q[X]-1])) {
			if (Q[X] == sizeBi || Q[Y] == 0 || Atemp[Qt*d + Q[Y]-1] <= Btemp[Qt*d + Q[X]]) {
				if (Q[Y] < sizeAi && (Q[X] == sizeBi || Atemp[Qt*d + Q[Y]] <= Btemp[Qt*d + Q[X]]) ) {
						M[gbx * d + tidx] = Atemp[Qt*d + Q[Y]];
				}
				else {
						M[gbx * d + tidx] = Btemp[Qt*d + Q[X]];
				}
				// printf("%d\n", M[gbx*d + tidx]);
				break ;
			}
			else {
				K[X] = Q[X] + 1;
				K[Y] = Q[Y] - 1;
			}
		}
		else {
			P[X] = Q[X] - 1;
			P[Y] = Q[Y] + 1 ;
		}
	}
}

int main() {

	// Graine aléatoire
	srand(0);

	// GPU Timer instructions
	float TimerV;
	cudaEvent_t start, stop;

	// ==================== //
	//      Parameters      //
	// ==================== //
	const int d = 32;
	int N = 100000;

	int threadsPerBlock = 1024;
	// ===================== //

	int numBlocks = (threadsPerBlock - 1 + N * d) / threadsPerBlock;
	// Allocation de la mémoire
	int * aHost = (int *) malloc(N*d * sizeof(int));
	int * bHost = (int *) malloc(N*d * sizeof(int));
	int * mHost = (int *) malloc(N*d * sizeof(int));

	int * sizeAHost = (int*) malloc(N * sizeof(int));
	int * sizeBHost = (int*) malloc(N * sizeof(int));

	// Remmplissage des tableaux Ai et Bi
	for (int i = 0; i < N; i++){

		// Taille aléatoire du tableau A[i]
		int alea = rand() % d;

		sizeAHost[i] = alea;
		sizeBHost[i] = d - sizeAHost[i];

		// Remplissage des tableaux avec des valeurs croissantes car le tab doit etre trié
		for (int j = 0; j < sizeAHost[i]; j ++){
			aHost[i*d+j] = 2*j;
		}
		for (int j = 0; j < sizeBHost[i]; j ++){
			bHost[i*d+j] = 2*j + 1;
		}
	}

	// Test
	{
		assert( isPowerOfTwo( d ) );
		assert( isPowerOfTwo( threadsPerBlock ) );
		assert( threadsPerBlock <= 1024 );
		assert( d <= 1024 );
		assert( threadsPerBlock % d == 0 );
		assert( isSumOfLengthEqualtoD(sizeAHost, sizeBHost, N, d) );
	}
	

	// Allouer la mémoire globale dans le GPU
	int * aDevice, * bDevice, * mDevice ;
	cudaMalloc( (void**) &aDevice, N*d * sizeof(int) );
	cudaMalloc( (void**) &bDevice, N*d * sizeof(int) );
	cudaMalloc( (void**) &mDevice, N*d * sizeof(int) );
	int * sizeADevice, * sizeBDevice;
	cudaMalloc( (void**) &sizeADevice, N * sizeof(int) );
	cudaMalloc( (void**) &sizeBDevice, N * sizeof(int) );

	// Copier les tableaux vers le GPU
	cudaMemcpy( aDevice, aHost, N*d * sizeof(int), cudaMemcpyHostToDevice );
	cudaMemcpy( bDevice, bHost, N*d * sizeof(int), cudaMemcpyHostToDevice );
	cudaMemcpy( sizeADevice, sizeAHost, N * sizeof(int), cudaMemcpyHostToDevice );
	cudaMemcpy( sizeBDevice, sizeBHost, N * sizeof(int), cudaMemcpyHostToDevice );

	// GPU Timer instructions
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventRecord(start, 0);

	// Lancer le kernel pour fusionner les tableaux 2 à 2
	mergeSmallBatch_k<<<numBlocks, threadsPerBlock>>>( aDevice, sizeADevice, bDevice, sizeBDevice, mDevice, d, N);

	// GPU timer instructions
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&TimerV, start, stop);
	printf("%d, %d, %f\n", N, d, TimerV);

	// Copier les tableaux du device vers host
	cudaMemcpy( mHost, mDevice, N*d * sizeof(int), cudaMemcpyDeviceToHost );

	
	// Show result for array (Ai, Bi)
	{
		int i = N-1;
		assert(i < N);

		for (int j = 0; j < d; j++){
			printf("Mhost[%d][%d] = %d\n", i, j, mHost[i*d+j]);
		}
		printf("============================\n");
		printf("Ci-dessus est le tableau M numero i=%d sur les N=%d.\n", i, N);
	        printf("C'est un tableau de taille %d, on a fusioné A et B.\n", d);
		if (sizeAHost[i] != 0)
			printf("A est le tableau de %d nombres PAIRS allant 0 à %d.\n", sizeAHost[i], aHost[d*i+sizeAHost[i]-1]);
		if (sizeBHost[i] != 0)
			printf("B est le tableau de %d nombres IMPAIRS allant 1 à %d.\n", sizeBHost[i], bHost[d*i+sizeBHost[i]-1]);
	}
	

	// Liberer la mémoire
	free(aHost);
	free(bHost);
	free(mHost);
	free(sizeAHost);
	free(sizeBHost);
	cudaFree(aDevice);
	cudaFree(bDevice);
	cudaFree(mDevice);
	cudaFree(sizeADevice);
	cudaFree(sizeBDevice);

	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	return 0;
}


bool isSumOfLengthEqualtoD(int *A, int *B, int N, int d){
	for (int i = 0; i < N; i ++){
		if (A[i] + B[i] != d){
			return false;
		}
	}
	return true;
}

// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2
bool isPowerOfTwo(int x)
{
	    return (x != 0) && ((x & (x - 1)) == 0);
}


	.file	"tmpxft_002eb091_00000000-6_batch_merge.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z21isSumOfLengthEqualtoDPiS_ii
	.type	_Z21isSumOfLengthEqualtoDPiS_ii, @function
_Z21isSumOfLengthEqualtoDPiS_ii:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	cmpl	%eax, %edx
	jle	.L8
	movl	(%rsi,%rax,4), %r8d
	addl	(%rdi,%rax,4), %r8d
	incq	%rax
	cmpl	%ecx, %r8d
	je	.L3
	xorl	%eax, %eax
	ret
.L8:
	movb	$1, %al
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z21isSumOfLengthEqualtoDPiS_ii, .-_Z21isSumOfLengthEqualtoDPiS_ii
	.globl	_Z12isPowerOfTwoi
	.type	_Z12isPowerOfTwoi, @function
_Z12isPowerOfTwoi:
.LFB2029:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	testl	%edi, %edi
	je	.L9
	leal	-1(%rdi), %eax
	testl	%edi, %eax
	sete	%al
.L9:
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z12isPowerOfTwoi, .-_Z12isPowerOfTwoi
	.globl	_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii
	.type	_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii, @function
_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17mergeSmallBatch_kPiS_S_S_S_ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii, .-_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii
	.globl	_Z17mergeSmallBatch_kPiS_S_S_S_ii
	.type	_Z17mergeSmallBatch_kPiS_S_S_S_ii, @function
_Z17mergeSmallBatch_kPiS_S_S_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii
	.cfi_endproc
.LFE2055:
	.size	_Z17mergeSmallBatch_kPiS_S_S_S_ii, .-_Z17mergeSmallBatch_kPiS_S_S_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d, %d, %f\n"
.LC1:
	.string	"Mhost[%d][%d] = %d\n"
.LC2:
	.string	"============================\n"
.LC3:
	.string	"Ci-dessus est le tableau M numero i=%d sur les N=%d.\n"
.LC4:
	.string	"C'est un tableau de taille %d, on a fusion\303\251 A et B.\n"
.LC5:
	.string	"A est le tableau de %d nombres PAIRS allant 0 \303\240 %d.\n"
.LC6:
	.string	"B est le tableau de %d nombres IMPAIRS allant 1 \303\240 %d.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	srand@PLT
	movl	$12800000, %edi
	call	malloc@PLT
	movl	$12800000, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$12800000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$400000, %edi
	movq	%rax, %r15
	call	malloc@PLT
	movl	$400000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
.L22:
	call	rand@PLT
	movl	$32, %esi
	movq	%r14, %rcx
	cltd
	movl	%esi, %edi
	salq	$5, %rcx
	idivl	%esi
	leaq	0(%r13,%rcx), %r8
	xorl	%eax, %eax
	subl	%edx, %edi
	movl	%edx, 0(%rbp,%r14)
	movl	%edi, (%rbx,%r14)
.L19:
	cmpl	%eax, %edx
	jle	.L38
	leal	(%rax,%rax), %r9d
	movl	%r9d, (%r8,%rax,4)
	incq	%rax
	jmp	.L19
.L38:
	addq	%r12, %rcx
	xorl	%eax, %eax
.L21:
	leal	1(%rax,%rax), %edx
	movl	%edx, (%rcx,%rax,4)
	incq	%rax
	cmpl	%eax, %edi
	jg	.L21
	addq	$4, %r14
	cmpq	$400000, %r14
	jne	.L22
	leaq	24(%rsp), %rdi
	movl	$12800000, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$12800000, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$12800000, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$400000, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$400000, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$12800000, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$12800000, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movabsq	$4294970421, %rdi
	movl	$1, %esi
	movq	%rdx, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	$32, %r9d
	pushq	$100000
	.cfi_def_cfa_offset 176
	movq	56(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z47__device_stub__Z17mergeSmallBatch_kPiS_S_S_S_iiPiS_S_S_S_ii
	popq	%rdx
	.cfi_def_cfa_offset 168
	popq	%rcx
	.cfi_def_cfa_offset 160
.L23:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%r14d, %r14d
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	76(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	$32, %ecx
	movl	$100000, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	76(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r15, %rdi
	movl	$12800000, %edx
	call	cudaMemcpy@PLT
.L24:
	movl	%r14d, %ecx
	movl	$99999, %edx
	movl	$2, %edi
	xorl	%eax, %eax
	movl	12799872(%r15,%r14,4), %r8d
	leaq	.LC1(%rip), %rsi
	incq	%r14
	call	__printf_chk@PLT
	cmpq	$32, %r14
	jne	.L24
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$100000, %ecx
	movl	$99999, %edx
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$32, %edx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	399996(%rbp), %edx
	testl	%edx, %edx
	je	.L25
	leal	3199968(%rdx), %eax
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	cltq
	movl	-4(%r13,%rax,4), %ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L25:
	movl	399996(%rbx), %edx
	testl	%edx, %edx
	je	.L26
	leal	3199968(%rdx), %eax
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	cltq
	movl	-4(%r12,%rax,4), %ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L26:
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%r15, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	16(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z17mergeSmallBatch_kPiS_S_S_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17mergeSmallBatch_kPiS_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>

#define X 0
#define Y 1 

bool isSumOfLengthEqualtoD(int *, int *, int, int);
bool isPowerOfTwo(int);

__global__ void mergeSmallBatch_k(int * A, int * sizeA, int *B, int *sizeB, int *M, const int d, int N){

	// Question 4 : Indices importantes
	const int tidx = threadIdx.x % d;				// Numéro de la diagonal dans le tableau numéro Qt
	const int Qt = (threadIdx.x - tidx) / d;			// Numéro du tableau par rapport au tableau shared
	const int gbx = Qt + blockIdx.x * (blockDim.x / d);		// Numéro du tableau par rapport au tableau global

	const int sizeAi = sizeA[gbx];				// Taille du tableau considéré
	const int sizeBi = sizeB[gbx];				// Taille du tableau considéré

	__shared__ int Atemp[1024];				// Tableau partagé par les threads d'un bloc
	__shared__ int Btemp[1024];				// Tableau partagé par les threads d'un bloc

	Atemp[Qt * d + tidx] = A[gbx * d + tidx];		// Remplissage du tableau
	Btemp[Qt * d + tidx] = B[gbx * d + tidx];		// Remplissage du tableau

	__syncthreads();					// Attente de la synchronisation de tous les threads du bloc
//	printf("blockId.x = %d | threadIdx. x = %d | tidx = %d | Qt = %d | gbx = %d\n", blockIdx.x, threadIdx.x, tidx, Qt, gbx);

	if (gbx * d + tidx >= N * d){
		return;
	}
	// ======================== //
	//        Merge path        //
	// ======================== //
	int K[2];
	int P[2];

	if (tidx > sizeAi) {
		K[X] = tidx - sizeAi;
		K[Y] = sizeAi;
		P[X] = sizeAi;
		P[Y] = tidx - sizeAi;
	}
	else {
		K[X] = 0;
		K[Y] = tidx;
		P[X] = tidx;
		P[Y] = 0;
	}

	while (1) {
		int offset = (abs(K[Y] - P[Y]))/2;
		int Q[2] = {K[X] + offset, K[Y] - offset};

		if (Q[Y] >= 0 && Q[X] <= sizeBi && (Q[Y] == sizeAi || Q[X] == 0 || Atemp[Qt*d + Q[Y]] > Btemp[Qt*d + Q[X]-1])) {
			if (Q[X] == sizeBi || Q[Y] == 0 || Atemp[Qt*d + Q[Y]-1] <= Btemp[Qt*d + Q[X]]) {
				if (Q[Y] < sizeAi && (Q[X] == sizeBi || Atemp[Qt*d + Q[Y]] <= Btemp[Qt*d + Q[X]]) ) {
						M[gbx * d + tidx] = Atemp[Qt*d + Q[Y]];
				}
				else {
						M[gbx * d + tidx] = Btemp[Qt*d + Q[X]];
				}
				// printf("%d\n", M[gbx*d + tidx]);
				break ;
			}
			else {
				K[X] = Q[X] + 1;
				K[Y] = Q[Y] - 1;
			}
		}
		else {
			P[X] = Q[X] - 1;
			P[Y] = Q[Y] + 1 ;
		}
	}
}

int main() {

	// Graine aléatoire
	srand(0);

	// GPU Timer instructions
	float TimerV;
	hipEvent_t start, stop;

	// ==================== //
	//      Parameters      //
	// ==================== //
	const int d = 32;
	int N = 100000;

	int threadsPerBlock = 1024;
	// ===================== //

	int numBlocks = (threadsPerBlock - 1 + N * d) / threadsPerBlock;
	// Allocation de la mémoire
	int * aHost = (int *) malloc(N*d * sizeof(int));
	int * bHost = (int *) malloc(N*d * sizeof(int));
	int * mHost = (int *) malloc(N*d * sizeof(int));

	int * sizeAHost = (int*) malloc(N * sizeof(int));
	int * sizeBHost = (int*) malloc(N * sizeof(int));

	// Remmplissage des tableaux Ai et Bi
	for (int i = 0; i < N; i++){

		// Taille aléatoire du tableau A[i]
		int alea = rand() % d;

		sizeAHost[i] = alea;
		sizeBHost[i] = d - sizeAHost[i];

		// Remplissage des tableaux avec des valeurs croissantes car le tab doit etre trié
		for (int j = 0; j < sizeAHost[i]; j ++){
			aHost[i*d+j] = 2*j;
		}
		for (int j = 0; j < sizeBHost[i]; j ++){
			bHost[i*d+j] = 2*j + 1;
		}
	}

	// Test
	{
		assert( isPowerOfTwo( d ) );
		assert( isPowerOfTwo( threadsPerBlock ) );
		assert( threadsPerBlock <= 1024 );
		assert( d <= 1024 );
		assert( threadsPerBlock % d == 0 );
		assert( isSumOfLengthEqualtoD(sizeAHost, sizeBHost, N, d) );
	}
	

	// Allouer la mémoire globale dans le GPU
	int * aDevice, * bDevice, * mDevice ;
	hipMalloc( (void**) &aDevice, N*d * sizeof(int) );
	hipMalloc( (void**) &bDevice, N*d * sizeof(int) );
	hipMalloc( (void**) &mDevice, N*d * sizeof(int) );
	int * sizeADevice, * sizeBDevice;
	hipMalloc( (void**) &sizeADevice, N * sizeof(int) );
	hipMalloc( (void**) &sizeBDevice, N * sizeof(int) );

	// Copier les tableaux vers le GPU
	hipMemcpy( aDevice, aHost, N*d * sizeof(int), hipMemcpyHostToDevice );
	hipMemcpy( bDevice, bHost, N*d * sizeof(int), hipMemcpyHostToDevice );
	hipMemcpy( sizeADevice, sizeAHost, N * sizeof(int), hipMemcpyHostToDevice );
	hipMemcpy( sizeBDevice, sizeBHost, N * sizeof(int), hipMemcpyHostToDevice );

	// GPU Timer instructions
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventRecord(start, 0);

	// Lancer le kernel pour fusionner les tableaux 2 à 2
	mergeSmallBatch_k<<<numBlocks, threadsPerBlock>>>( aDevice, sizeADevice, bDevice, sizeBDevice, mDevice, d, N);

	// GPU timer instructions
	hipEventRecord(stop, 0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&TimerV, start, stop);
	printf("%d, %d, %f\n", N, d, TimerV);

	// Copier les tableaux du device vers host
	hipMemcpy( mHost, mDevice, N*d * sizeof(int), hipMemcpyDeviceToHost );

	
	// Show result for array (Ai, Bi)
	{
		int i = N-1;
		assert(i < N);

		for (int j = 0; j < d; j++){
			printf("Mhost[%d][%d] = %d\n", i, j, mHost[i*d+j]);
		}
		printf("============================\n");
		printf("Ci-dessus est le tableau M numero i=%d sur les N=%d.\n", i, N);
	        printf("C'est un tableau de taille %d, on a fusioné A et B.\n", d);
		if (sizeAHost[i] != 0)
			printf("A est le tableau de %d nombres PAIRS allant 0 à %d.\n", sizeAHost[i], aHost[d*i+sizeAHost[i]-1]);
		if (sizeBHost[i] != 0)
			printf("B est le tableau de %d nombres IMPAIRS allant 1 à %d.\n", sizeBHost[i], bHost[d*i+sizeBHost[i]-1]);
	}
	

	// Liberer la mémoire
	free(aHost);
	free(bHost);
	free(mHost);
	free(sizeAHost);
	free(sizeBHost);
	hipFree(aDevice);
	hipFree(bDevice);
	hipFree(mDevice);
	hipFree(sizeADevice);
	hipFree(sizeBDevice);

	hipEventDestroy(start);
	hipEventDestroy(stop);

	return 0;
}


bool isSumOfLengthEqualtoD(int *A, int *B, int N, int d){
	for (int i = 0; i < N; i ++){
		if (A[i] + B[i] != d){
			return false;
		}
	}
	return true;
}

// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2
bool isPowerOfTwo(int x)
{
	    return (x != 0) && ((x & (x - 1)) == 0);
}


	.text
	.file	"batch_merge.hip"
	.globl	_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii # -- Begin function _Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii
	.type	_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii,@function
_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii: # @_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17mergeSmallBatch_kPiS_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii, .Lfunc_end0-_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	srand
	movl	$12800000, %edi                 # imm = 0xC35000
	callq	malloc
	movq	%rax, %r15
	movl	$12800000, %edi                 # imm = 0xC35000
	callq	malloc
	movq	%rax, %rbp
	movl	$12800000, %edi                 # imm = 0xC35000
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, %r12
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, %r13
	movl	$128, %r14d
	movq	%rbp, 80(%rsp)                  # 8-byte Spill
	movq	%r15, 88(%rsp)                  # 8-byte Spill
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
                                        #     Child Loop BB1_5 Depth 2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	31(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-32, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r12,%rbx,4)
	movl	$32, %ecx
	subl	%eax, %ecx
	movl	%ecx, (%r13,%rbx,4)
	testl	%eax, %eax
	jle	.LBB1_4
# %bb.2:                                # %.lr.ph
                                        #   in Loop: Header=BB1_1 Depth=1
	movl	%eax, %eax
	addq	%rax, %rax
	xorl	%edx, %edx
.LBB1_3:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%edx, (%r15,%rdx,2)
	addq	$2, %rdx
	cmpq	%rdx, %rax
	jne	.LBB1_3
.LBB1_4:                                # %.lr.ph98
                                        #   in Loop: Header=BB1_1 Depth=1
	movl	%ecx, %eax
	addq	%rax, %rax
	xorl	%ecx, %ecx
.LBB1_5:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	1(%rcx), %edx
	movl	%edx, (%rbp,%rcx,2)
	addq	$2, %rcx
	cmpq	%rcx, %rax
	jne	.LBB1_5
# %bb.6:                                # %._crit_edge
                                        #   in Loop: Header=BB1_1 Depth=1
	incq	%rbx
	addq	%r14, %r15
	addq	%r14, %rbp
	cmpq	$100000, %rbx                   # imm = 0x186A0
	jne	.LBB1_1
# %bb.7:
	leaq	56(%rsp), %r14
	movl	$12800000, %esi                 # imm = 0xC35000
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	48(%rsp), %r15
	movl	$12800000, %esi                 # imm = 0xC35000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$12800000, %esi                 # imm = 0xC35000
	callq	hipMalloc
	leaq	40(%rsp), %rbp
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rbx
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$12800000, %edx                 # imm = 0xC35000
	movq	88(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$12800000, %edx                 # imm = 0xC35000
	movq	80(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	2101(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:
	movq	56(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	24(%rsp), %r8
	movl	$100000, (%rsp)                 # imm = 0x186A0
	movl	$32, %r9d
	callq	_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii
.LBB1_9:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	64(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	100(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str, %edi
	movl	$100000, %esi                   # imm = 0x186A0
	movl	$32, %edx
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rsi
	movl	$12800000, %edx                 # imm = 0xC35000
	movq	72(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB1_10:                               # =>This Inner Loop Header: Depth=1
	movl	12799872(%rbp,%rbx,4), %ecx
	movl	$.L.str.1, %edi
	movl	$99999, %esi                    # imm = 0x1869F
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$32, %rbx
	jne	.LBB1_10
# %bb.11:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.L.str.3, %edi
	movl	$99999, %esi                    # imm = 0x1869F
	movl	$100000, %edx                   # imm = 0x186A0
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.4, %edi
	movl	$32, %esi
	xorl	%eax, %eax
	callq	printf
	movslq	399996(%r12), %rsi
	testq	%rsi, %rsi
	je	.LBB1_13
# %bb.12:
	movl	12799868(%r14,%rsi,4), %edx
	movl	$.L.str.5, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_13:
	movslq	399996(%r13), %rsi
	testq	%rsi, %rsi
	je	.LBB1_15
# %bb.14:
	movl	12799868(%r15,%rsi,4), %edx
	movl	$.L.str.6, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_15:
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z21isSumOfLengthEqualtoDPiS_ii # -- Begin function _Z21isSumOfLengthEqualtoDPiS_ii
	.type	_Z21isSumOfLengthEqualtoDPiS_ii,@function
_Z21isSumOfLengthEqualtoDPiS_ii:        # @_Z21isSumOfLengthEqualtoDPiS_ii
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB2_6
# %bb.1:                                # %.lr.ph.preheader
	movl	(%rsi), %eax
	addl	(%rdi), %eax
	cmpl	%ecx, %eax
	jne	.LBB2_8
# %bb.2:                                # %.lr.ph16.preheader
	movl	%edx, %eax
	movl	$1, %r8d
.LBB2_3:                                # %.lr.ph16
                                        # =>This Inner Loop Header: Depth=1
	movq	%r8, %rdx
	cmpq	%r8, %rax
	je	.LBB2_5
# %bb.4:                                # %.lr.ph
                                        #   in Loop: Header=BB2_3 Depth=1
	movl	(%rsi,%rdx,4), %r9d
	addl	(%rdi,%rdx,4), %r9d
	leaq	1(%rdx), %r8
	cmpl	%ecx, %r9d
	je	.LBB2_3
.LBB2_5:                                # %._crit_edge.loopexit
	cmpq	%rax, %rdx
	setae	%al
                                        # kill: def $al killed $al killed $eax
	retq
.LBB2_6:
	movb	$1, %al
                                        # kill: def $al killed $al killed $eax
	retq
.LBB2_8:
	xorl	%eax, %eax
                                        # kill: def $al killed $al killed $eax
	retq
.Lfunc_end2:
	.size	_Z21isSumOfLengthEqualtoDPiS_ii, .Lfunc_end2-_Z21isSumOfLengthEqualtoDPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z12isPowerOfTwoi               # -- Begin function _Z12isPowerOfTwoi
	.type	_Z12isPowerOfTwoi,@function
_Z12isPowerOfTwoi:                      # @_Z12isPowerOfTwoi
	.cfi_startproc
# %bb.0:
                                        # kill: def $edi killed $edi def $rdi
	testl	%edi, %edi
	je	.LBB3_1
# %bb.2:
	leal	-1(%rdi), %eax
	testl	%eax, %edi
	sete	%al
                                        # kill: def $al killed $al killed $eax
	retq
.LBB3_1:
	xorl	%eax, %eax
                                        # kill: def $al killed $al killed $eax
	retq
.Lfunc_end3:
	.size	_Z12isPowerOfTwoi, .Lfunc_end3-_Z12isPowerOfTwoi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17mergeSmallBatch_kPiS_S_S_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17mergeSmallBatch_kPiS_S_S_S_ii,@object # @_Z17mergeSmallBatch_kPiS_S_S_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z17mergeSmallBatch_kPiS_S_S_S_ii
	.p2align	3, 0x0
_Z17mergeSmallBatch_kPiS_S_S_S_ii:
	.quad	_Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii
	.size	_Z17mergeSmallBatch_kPiS_S_S_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d, %d, %f\n"
	.size	.L.str, 12

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Mhost[%d][%d] = %d\n"
	.size	.L.str.1, 20

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Ci-dessus est le tableau M numero i=%d sur les N=%d.\n"
	.size	.L.str.3, 54

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"C'est un tableau de taille %d, on a fusion\303\251 A et B.\n"
	.size	.L.str.4, 54

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"A est le tableau de %d nombres PAIRS allant 0 \303\240 %d.\n"
	.size	.L.str.5, 54

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"B est le tableau de %d nombres IMPAIRS allant 1 \303\240 %d.\n"
	.size	.L.str.6, 56

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17mergeSmallBatch_kPiS_S_S_S_ii"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"============================"
	.size	.Lstr, 29

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__mergeSmallBatch_kPiS_S_S_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17mergeSmallBatch_kPiS_S_S_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17mergeSmallBatch_kPiS_S_S_S_ii ; -- Begin function _Z17mergeSmallBatch_kPiS_S_S_S_ii
	.globl	_Z17mergeSmallBatch_kPiS_S_S_S_ii
	.p2align	8
	.type	_Z17mergeSmallBatch_kPiS_S_S_S_ii,@function
_Z17mergeSmallBatch_kPiS_S_S_S_ii:      ; @_Z17mergeSmallBatch_kPiS_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x28
	s_load_b32 s4, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s6, 0, s2
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v1
	s_mul_i32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s5, s6
	s_add_i32 s5, s5, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_hi_u32 v1, v0, s5
	s_mul_hi_u32 s5, s4, s5
	s_mul_i32 s6, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_sub_i32 s4, s4, s6
	s_add_i32 s6, s5, 1
	s_sub_i32 s7, s4, s2
	v_mul_lo_u32 v2, v1, s2
	v_add_nc_u32_e32 v3, 1, v1
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s5, s6, s5
	s_cselect_b32 s4, s7, s4
	s_add_i32 s6, s5, 1
	s_cmp_ge_u32 s4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	s_cselect_b32 s4, s6, s5
	v_subrev_nc_u32_e32 v4, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v1, s2
	v_mad_u64_u32 v[2:3], null, s4, s15, v[1:2]
	s_load_b256 s[4:11], s[0:1], 0x0
	v_sub_nc_u32_e32 v1, v0, v4
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_mad_u64_u32 v[7:8], null, v2, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_mov_b32 s2, 0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v14, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[12:13], off
	global_load_b32 v5, v[8:9], off
	global_load_b32 v6, v[14:15], off
	v_cmp_gt_i32_e32 vcc_lo, s3, v7
	s_waitcnt vmcnt(2)
	ds_store_2addr_stride64_b32 v0, v10, v11 offset1:16
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x20
	v_sub_nc_u32_e32 v0, v1, v5
	v_cmp_gt_i32_e32 vcc_lo, v1, v5
	v_min_i32_e32 v9, v1, v5
	v_add_nc_u32_e32 v7, -1, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, 0, v0, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	v_mov_b32_e32 v3, v8
                                        ; implicit-def: $vgpr2
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_sub_nc_u32_e32 v10, v9, v8
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, 0, v10
	v_max_i32_e32 v10, v10, v11
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v15, 1, v10
	v_sub_nc_u32_e32 v10, v9, v15
	v_add_nc_u32_e32 v12, v15, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, -1, v10
	v_cmp_le_i32_e64 s0, v12, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, vcc_lo, s0
                                        ; implicit-def: $sgpr0
	s_and_saveexec_b32 s3, s4
	s_cbranch_execz .LBB0_24
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, v10, v5
	v_cmp_eq_u32_e64 s0, 0, v12
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s5, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s5
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_lshl_u32 v11, v10, v4, 2
	v_add_lshl_u32 v13, v7, v12, 2
	s_and_not1_b32 s0, s0, exec_lo
	s_mov_b32 s4, exec_lo
	ds_load_b32 v11, v11
	ds_load_b32 v13, v13 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v11, v13
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s5
.LBB0_5:                                ; %Flow141
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_23
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u32_e64 s0, v12, v6
	v_cmp_eq_u32_e64 s1, v9, v15
	v_cmp_ne_u32_e32 vcc_lo, v12, v6
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s7, s1, s0
                                        ; implicit-def: $sgpr1
	s_xor_b32 s0, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_lshl_u32 v11, v7, v10, 2
	v_add_lshl_u32 v13, v12, v4, 2
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr14
	ds_load_b32 v11, v11
	ds_load_b32 v13, v13 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, v11, v13
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s9, s0
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v14, 1, v12
	v_add_nc_u32_e32 v13, -1, v10
	s_mov_b32 s1, -1
	s_xor_b32 s8, exec_lo, -1
; %bb.9:                                ; %Flow138
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v11, v2
	s_and_not1_b32 s0, s7, exec_lo
	s_and_b32 s7, s8, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s0, s7
.LBB0_10:                               ; %Flow137
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_and_saveexec_b32 s6, s7
	s_cbranch_execz .LBB0_22
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_ge_i32_e64 s0, v10, v5
	s_mov_b32 s8, 0
	s_mov_b32 s7, 0
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s0
	s_xor_b32 s0, exec_lo, s9
; %bb.12:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v13, v12, v4
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $vgpr12
; %bb.13:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s9, s0
	v_mov_b32_e32 v11, v2
	s_xor_b32 exec_lo, exec_lo, s9
	s_cbranch_execz .LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v11, v10, v4
	s_mov_b32 s0, -1
	s_mov_b32 s10, s7
                                        ; implicit-def: $vgpr13
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v13, v12, v4
	v_lshlrev_b32_e32 v12, 2, v11
	s_and_not1_b32 s10, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v14, 2, v13
	ds_load_b32 v12, v12
	ds_load_b32 v14, v14 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v12, v14
	v_cmp_le_i32_e64 s0, v12, v14
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_or_not1_b32 s0, s0, exec_lo
	s_or_b32 s10, s10, s11
.LBB0_16:                               ; %Flow134
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_and_b32 s8, s0, exec_lo
	s_or_b32 s7, s7, s10
.LBB0_17:                               ; %Flow133
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
                                        ; implicit-def: $sgpr0
	s_and_saveexec_b32 s9, s7
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b32_e32 v12, 2, v13
	s_mov_b32 s0, 0
	ds_load_b32 v12, v12 offset:4096
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v12, off
.LBB0_19:                               ; %Flow135
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_and_saveexec_b32 s7, s8
	s_cbranch_execz .LBB0_21
; %bb.20:                               ; %._crit_edge109
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b32_e32 v12, 2, v11
	s_and_not1_b32 s0, s0, exec_lo
	ds_load_b32 v12, v12
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v12, off
.LBB0_21:                               ; %Flow136
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v14, v3
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s0
.LBB0_22:                               ; %Flow139
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
	s_and_not1_b32 s4, s4, exec_lo
.LBB0_23:                               ; %Flow142
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s1, exec_lo
	s_or_not1_b32 s1, s4, exec_lo
.LBB0_24:                               ; %Flow140
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s1
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v11, v2 :: v_dual_add_nc_u32 v8, 1, v10
	v_dual_mov_b32 v14, v3 :: v_dual_mov_b32 v13, v9
	s_or_b32 s0, s0, exec_lo
; %bb.26:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_xor_b32 s0, s0, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v14
	v_mov_b32_e32 v9, v13
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_2
.LBB0_27:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17mergeSmallBatch_kPiS_S_S_S_ii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17mergeSmallBatch_kPiS_S_S_S_ii, .Lfunc_end0-_Z17mergeSmallBatch_kPiS_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1192
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17mergeSmallBatch_kPiS_S_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17mergeSmallBatch_kPiS_S_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
