extern "C"{
    // #include <stdio.h>
    // #define QUANTIZED_LEVEL 3
    #define WORKER_NUMBER 3
    /* BKDR Hash Function */
    __device__ unsigned int BKDR_hash(char *str){
        unsigned int seed = 131;
        unsigned int hash = 0;
        for(int i=0;i<4;i++){
            hash = hash * seed + (str[i]);
        }
        return (hash & 0x7FFFFFFF);
    }
    // change the type of keysInGroup_gpu, add quant_level,to add bit_unit
    __global__ void InsertKernel(float *lsstable_gpu, unsigned int *keysInGroup_gpu, float *grad_gpu, int *lsstable_size_gpu, float * cluster_center_gpu, int grad_num, int cluster_number, int quant_level, int max_table_size){
        int idx = blockIdx.x * blockDim.x + threadIdx.x;
        int bit_uint = int(32/quant_level);// how many code in one longlong int, should be pass by the parameter, to do
         
        if (idx < grad_num){
            int col = idx % bit_uint;
            int row = int(idx / bit_uint);// code cordination
            float tmp = fabsf(cluster_center_gpu[0] - grad_gpu[idx]);
            int i;
            unsigned int tmp_index = 0;//closest cluster index
            for(i=1;i<cluster_number;i++){
                float tmp_diff = fabsf(cluster_center_gpu[i] - grad_gpu[idx]);
                if(tmp_diff < tmp){
                    tmp = tmp_diff;
                    tmp_index = i;
                }	    
            }
            
            unsigned int tmp_bits = tmp_index;
            tmp_bits <<= (quant_level * col);
            
            atomicOr(&(keysInGroup_gpu[row]), tmp_bits);
            // if(idx==15){
            //     printf("id %d, quant %d\n", idx,tmp_index);
            //     printf("id %d, tmp_bits %d\n", idx,tmp_bits);
            //     printf("id %d, keysInGroup_gpu %d\n", idx,keysInGroup_gpu[row]);
            // }
            // printf("id %d, quant %d\n", idx,keysInGroup_gpu[row]);
            
            int hash_pos = (BKDR_hash((char *)&idx)) % (lsstable_size_gpu[tmp_index]);
            atomicAdd(&(lsstable_gpu[tmp_index*2*max_table_size + hash_pos]), grad_gpu[idx]);
            atomicAdd(&(lsstable_gpu[(tmp_index*2+1)*max_table_size + hash_pos]), 1.0);

        }
    }

    __global__ void get_lsstable_kernel(float *lsstable_gpu, int *lsstable_size_gpu, int cluster_number, int max_table_size){
        int idx = blockDim.x * blockIdx.x + threadIdx.x;
        int idy = blockIdx.y;
        if(idx < lsstable_size_gpu[idy]){
            if(lsstable_gpu[(idy*2+1)*max_table_size + idx]!=0){
                lsstable_gpu[(idy*2)*max_table_size + idx] /= lsstable_gpu[(idy*2+1)*max_table_size + idx];
            }
        }
    }	
    /****
    __global__ void DecodeKernel(float *lsstable_gpu, unsigned char *keysInGroup_gpu, float *grad_gpu, int *lsstable_size_gpu, int grad_num, int cluster_number, int max_table_size){
        __shared__ float cache[128][TOTAL_CLUSTER_NUMBER];
        int idx = threadIdx.x + blockIdx.x * blockDim.x;
        int idy = threadIdx.y;

        if (idx < grad_num){
            int group_times = keysInGroup_gpu[idx*cluster_number + idy];
            int hash_pos = (BKDR_hash((char *)&idx)) % (lsstable_size_gpu[idy]);
            cache[threadIdx.x][threadIdx.y] = lsstable_gpu[2*idy*max_table_size + hash_pos] * group_times;
        }
        __syncthreads();

        int i = TOTAL_CLUSTER_NUMBER/2;
        while(i != 0){
            if(threadIdx.y<i){
                cache[threadIdx.x][threadIdx.y] += cache[threadIdx.x][threadIdx.y+i];
            }
            __syncthreads();
            i /= 2;
        }

            if(idx < grad_num && threadIdx.y==0){
                grad_gpu[idx] = cache[threadIdx.x][0]/TOTAL_CLUSTER_NUMBER;
            }
    }
    ****/
    
    // change the type of keysInGroup_gpu, add int quant_level, int workers_number, int keysInGroup_size, to add bit_unit

    __global__ void Decode_Multi_Kernel(float *lsstable_gpu, unsigned int *keysInGroup_gpu, float *grad_gpu, int *lsstable_size_gpu, int grad_num, int workers_number, int keysInGroup_size, int quant_level, uint cluster_number, int max_table_size){
        extern __shared__ float cache[]; //each row save the decode value from the concatenate keysInGroup and compute one grad, 128*WORKER_NUMBER
        
        int idx = threadIdx.x + blockIdx.x * blockDim.x; //to find the grad id
        int idy = threadIdx.y; //to find which worker's keysInGroup
        int bit_uint = int(32/quant_level);// how many code in one longlong int, should be pass by the parameter, to do
        if (idx < grad_num){
            int col = idx % bit_uint;
            int row = int(idx / bit_uint);// code cordination
            unsigned int tmp_bits = (cluster_number-1) << (quant_level * col);//mask
            tmp_bits &= keysInGroup_gpu[idy * keysInGroup_size + row];
            
            int group = tmp_bits >> (quant_level * col);//get the code
            // if(idx==(grad_num-1)){
            //     printf("id %d, pos %d\n", idx,idy * keysInGroup_size + row);
            //     printf("id %d, tmp_bits %d\n", idx,tmp_bits);
            //     printf("id %d, quant %d\n", idx,group);
            // }
            int hash_pos = (BKDR_hash((char *)&idx)) % (lsstable_size_gpu[group]);
            cache[threadIdx.x* workers_number + threadIdx.y] = lsstable_gpu[2*group*max_table_size + hash_pos];
        }
        __syncthreads();

        int i = workers_number/2;
        while(i != 0){
            if(threadIdx.y<i){
                cache[threadIdx.x* workers_number + threadIdx.y] += cache[threadIdx.x * workers_number + (threadIdx.y+i)];
            }
            __syncthreads();
            i /= 2;
        }

        if(idx < grad_num && threadIdx.y==0){
            grad_gpu[idx] = cache[threadIdx.x * workers_number + 0]/workers_number;
        }
    }
}
	.file	"tmpxft_00390807_00000000-6_LSSkernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	BKDR_hash
	.type	BKDR_hash, @function
BKDR_hash:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	BKDR_hash, .-BKDR_hash
	.globl	_Z44__device_stub__Z12InsertKernelPfPjS_PiS_iiiiPfPjS_PiS_iiii
	.type	_Z44__device_stub__Z12InsertKernelPfPjS_PiS_iiiiPfPjS_PiS_iiii, @function
_Z44__device_stub__Z12InsertKernelPfPjS_PiS_iiiiPfPjS_PiS_iiii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	InsertKernel(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z44__device_stub__Z12InsertKernelPfPjS_PiS_iiiiPfPjS_PiS_iiii, .-_Z44__device_stub__Z12InsertKernelPfPjS_PiS_iiiiPfPjS_PiS_iiii
	.globl	InsertKernel
	.type	InsertKernel, @function
InsertKernel:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z12InsertKernelPfPjS_PiS_iiiiPfPjS_PiS_iiii
	.cfi_endproc
.LFE2034:
	.size	InsertKernel, .-InsertKernel
	.globl	_Z43__device_stub__Z19get_lsstable_kernelPfPiiiPfPiii
	.type	_Z43__device_stub__Z19get_lsstable_kernelPfPiiiPfPiii, @function
_Z43__device_stub__Z19get_lsstable_kernelPfPiiiPfPiii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	get_lsstable_kernel(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z43__device_stub__Z19get_lsstable_kernelPfPiiiPfPiii, .-_Z43__device_stub__Z19get_lsstable_kernelPfPiiiPfPiii
	.globl	get_lsstable_kernel
	.type	get_lsstable_kernel, @function
get_lsstable_kernel:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19get_lsstable_kernelPfPiiiPfPiii
	.cfi_endproc
.LFE2036:
	.size	get_lsstable_kernel, .-get_lsstable_kernel
	.globl	_Z51__device_stub__Z19Decode_Multi_KernelPfPjS_PiiiiijiPfPjS_Piiiiiji
	.type	_Z51__device_stub__Z19Decode_Multi_KernelPfPjS_PiiiiijiPfPjS_Piiiiiji, @function
_Z51__device_stub__Z19Decode_Multi_KernelPfPjS_PiiiiijiPfPjS_Piiiiiji:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	Decode_Multi_Kernel(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L15:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z51__device_stub__Z19Decode_Multi_KernelPfPjS_PiiiiijiPfPjS_Piiiiiji, .-_Z51__device_stub__Z19Decode_Multi_KernelPfPjS_PiiiiijiPfPjS_Piiiiiji
	.globl	Decode_Multi_Kernel
	.type	Decode_Multi_Kernel, @function
Decode_Multi_Kernel:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z19Decode_Multi_KernelPfPjS_PiiiiijiPfPjS_Piiiiiji
	.cfi_endproc
.LFE2038:
	.size	Decode_Multi_Kernel, .-Decode_Multi_Kernel
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Decode_Multi_Kernel"
.LC1:
	.string	"get_lsstable_kernel"
.LC2:
	.string	"InsertKernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	Decode_Multi_Kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	get_lsstable_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	InsertKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"{
    // #include <stdio.h>
    // #define QUANTIZED_LEVEL 3
    #define WORKER_NUMBER 3
    /* BKDR Hash Function */
    __device__ unsigned int BKDR_hash(char *str){
        unsigned int seed = 131;
        unsigned int hash = 0;
        for(int i=0;i<4;i++){
            hash = hash * seed + (str[i]);
        }
        return (hash & 0x7FFFFFFF);
    }
    // change the type of keysInGroup_gpu, add quant_level,to add bit_unit
    __global__ void InsertKernel(float *lsstable_gpu, unsigned int *keysInGroup_gpu, float *grad_gpu, int *lsstable_size_gpu, float * cluster_center_gpu, int grad_num, int cluster_number, int quant_level, int max_table_size){
        int idx = blockIdx.x * blockDim.x + threadIdx.x;
        int bit_uint = int(32/quant_level);// how many code in one longlong int, should be pass by the parameter, to do
         
        if (idx < grad_num){
            int col = idx % bit_uint;
            int row = int(idx / bit_uint);// code cordination
            float tmp = fabsf(cluster_center_gpu[0] - grad_gpu[idx]);
            int i;
            unsigned int tmp_index = 0;//closest cluster index
            for(i=1;i<cluster_number;i++){
                float tmp_diff = fabsf(cluster_center_gpu[i] - grad_gpu[idx]);
                if(tmp_diff < tmp){
                    tmp = tmp_diff;
                    tmp_index = i;
                }	    
            }
            
            unsigned int tmp_bits = tmp_index;
            tmp_bits <<= (quant_level * col);
            
            atomicOr(&(keysInGroup_gpu[row]), tmp_bits);
            // if(idx==15){
            //     printf("id %d, quant %d\n", idx,tmp_index);
            //     printf("id %d, tmp_bits %d\n", idx,tmp_bits);
            //     printf("id %d, keysInGroup_gpu %d\n", idx,keysInGroup_gpu[row]);
            // }
            // printf("id %d, quant %d\n", idx,keysInGroup_gpu[row]);
            
            int hash_pos = (BKDR_hash((char *)&idx)) % (lsstable_size_gpu[tmp_index]);
            atomicAdd(&(lsstable_gpu[tmp_index*2*max_table_size + hash_pos]), grad_gpu[idx]);
            atomicAdd(&(lsstable_gpu[(tmp_index*2+1)*max_table_size + hash_pos]), 1.0);

        }
    }

    __global__ void get_lsstable_kernel(float *lsstable_gpu, int *lsstable_size_gpu, int cluster_number, int max_table_size){
        int idx = blockDim.x * blockIdx.x + threadIdx.x;
        int idy = blockIdx.y;
        if(idx < lsstable_size_gpu[idy]){
            if(lsstable_gpu[(idy*2+1)*max_table_size + idx]!=0){
                lsstable_gpu[(idy*2)*max_table_size + idx] /= lsstable_gpu[(idy*2+1)*max_table_size + idx];
            }
        }
    }	
    /****
    __global__ void DecodeKernel(float *lsstable_gpu, unsigned char *keysInGroup_gpu, float *grad_gpu, int *lsstable_size_gpu, int grad_num, int cluster_number, int max_table_size){
        __shared__ float cache[128][TOTAL_CLUSTER_NUMBER];
        int idx = threadIdx.x + blockIdx.x * blockDim.x;
        int idy = threadIdx.y;

        if (idx < grad_num){
            int group_times = keysInGroup_gpu[idx*cluster_number + idy];
            int hash_pos = (BKDR_hash((char *)&idx)) % (lsstable_size_gpu[idy]);
            cache[threadIdx.x][threadIdx.y] = lsstable_gpu[2*idy*max_table_size + hash_pos] * group_times;
        }
        __syncthreads();

        int i = TOTAL_CLUSTER_NUMBER/2;
        while(i != 0){
            if(threadIdx.y<i){
                cache[threadIdx.x][threadIdx.y] += cache[threadIdx.x][threadIdx.y+i];
            }
            __syncthreads();
            i /= 2;
        }

            if(idx < grad_num && threadIdx.y==0){
                grad_gpu[idx] = cache[threadIdx.x][0]/TOTAL_CLUSTER_NUMBER;
            }
    }
    ****/
    
    // change the type of keysInGroup_gpu, add int quant_level, int workers_number, int keysInGroup_size, to add bit_unit

    __global__ void Decode_Multi_Kernel(float *lsstable_gpu, unsigned int *keysInGroup_gpu, float *grad_gpu, int *lsstable_size_gpu, int grad_num, int workers_number, int keysInGroup_size, int quant_level, uint cluster_number, int max_table_size){
        extern __shared__ float cache[]; //each row save the decode value from the concatenate keysInGroup and compute one grad, 128*WORKER_NUMBER
        
        int idx = threadIdx.x + blockIdx.x * blockDim.x; //to find the grad id
        int idy = threadIdx.y; //to find which worker's keysInGroup
        int bit_uint = int(32/quant_level);// how many code in one longlong int, should be pass by the parameter, to do
        if (idx < grad_num){
            int col = idx % bit_uint;
            int row = int(idx / bit_uint);// code cordination
            unsigned int tmp_bits = (cluster_number-1) << (quant_level * col);//mask
            tmp_bits &= keysInGroup_gpu[idy * keysInGroup_size + row];
            
            int group = tmp_bits >> (quant_level * col);//get the code
            // if(idx==(grad_num-1)){
            //     printf("id %d, pos %d\n", idx,idy * keysInGroup_size + row);
            //     printf("id %d, tmp_bits %d\n", idx,tmp_bits);
            //     printf("id %d, quant %d\n", idx,group);
            // }
            int hash_pos = (BKDR_hash((char *)&idx)) % (lsstable_size_gpu[group]);
            cache[threadIdx.x* workers_number + threadIdx.y] = lsstable_gpu[2*group*max_table_size + hash_pos];
        }
        __syncthreads();

        int i = workers_number/2;
        while(i != 0){
            if(threadIdx.y<i){
                cache[threadIdx.x* workers_number + threadIdx.y] += cache[threadIdx.x * workers_number + (threadIdx.y+i)];
            }
            __syncthreads();
            i /= 2;
        }

        if(idx < grad_num && threadIdx.y==0){
            grad_gpu[idx] = cache[threadIdx.x * workers_number + 0]/workers_number;
        }
    }
}
	.text
	.file	"LSSkernel.hip"
	.globl	__device_stub__InsertKernel     # -- Begin function __device_stub__InsertKernel
	.type	__device_stub__InsertKernel,@function
__device_stub__InsertKernel:            # @__device_stub__InsertKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$InsertKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__InsertKernel, .Lfunc_end0-__device_stub__InsertKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__get_lsstable_kernel # -- Begin function __device_stub__get_lsstable_kernel
	.type	__device_stub__get_lsstable_kernel,@function
__device_stub__get_lsstable_kernel:     # @__device_stub__get_lsstable_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$get_lsstable_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__get_lsstable_kernel, .Lfunc_end1-__device_stub__get_lsstable_kernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__Decode_Multi_Kernel # -- Begin function __device_stub__Decode_Multi_Kernel
	.type	__device_stub__Decode_Multi_Kernel,@function
__device_stub__Decode_Multi_Kernel:     # @__device_stub__Decode_Multi_Kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$Decode_Multi_Kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__Decode_Multi_Kernel, .Lfunc_end2-__device_stub__Decode_Multi_Kernel
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$InsertKernel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$get_lsstable_kernel, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$Decode_Multi_Kernel, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	InsertKernel,@object            # @InsertKernel
	.section	.rodata,"a",@progbits
	.globl	InsertKernel
	.p2align	3, 0x0
InsertKernel:
	.quad	__device_stub__InsertKernel
	.size	InsertKernel, 8

	.type	get_lsstable_kernel,@object     # @get_lsstable_kernel
	.globl	get_lsstable_kernel
	.p2align	3, 0x0
get_lsstable_kernel:
	.quad	__device_stub__get_lsstable_kernel
	.size	get_lsstable_kernel, 8

	.type	Decode_Multi_Kernel,@object     # @Decode_Multi_Kernel
	.globl	Decode_Multi_Kernel
	.p2align	3, 0x0
Decode_Multi_Kernel:
	.quad	__device_stub__Decode_Multi_Kernel
	.size	Decode_Multi_Kernel, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"InsertKernel"
	.size	.L__unnamed_1, 13

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"get_lsstable_kernel"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"Decode_Multi_Kernel"
	.size	.L__unnamed_3, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__InsertKernel
	.addrsig_sym __device_stub__get_lsstable_kernel
	.addrsig_sym __device_stub__Decode_Multi_Kernel
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym InsertKernel
	.addrsig_sym get_lsstable_kernel
	.addrsig_sym Decode_Multi_Kernel
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	InsertKernel            ; -- Begin function InsertKernel
	.globl	InsertKernel
	.p2align	8
	.type	InsertKernel,@function
InsertKernel:                           ; @InsertKernel
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x4
	s_clause 0x1
	s_load_b32 s4, s[2:3], 0x44
	s_load_b128 s[16:19], s[2:3], 0x28
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s1
	v_mul_lo_u32 v2, s0, v1
	s_and_b32 s0, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[1:2]
	v_mad_u32_u24 v1, v3, s1, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_store_b32 v1, v4
	v_cmpx_gt_i32_e64 s16, v4
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[2:3], 0x0
	s_load_b64 s[0:1], s[2:3], 0x20
	v_ashrrev_i32_e32 v5, 31, v4
	v_mov_b32_e32 v0, 0
	s_cmp_lt_i32 s17, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	global_load_b32 v6, v[2:3], off
	s_load_b32 s2, s[0:1], 0x0
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v0, s2, v6
	s_mov_b32 s2, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v7, 0x7fffffff, v0
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v8, s3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s3, |v8|, v7
	v_cndmask_b32_e64 v0, v0, s2, s3
	s_add_i32 s2, s2, 1
	v_cndmask_b32_e64 v7, v7, |v8|, s3
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s17, s2
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	s_ashr_i32 s0, s18, 31
	v_add_nc_u32_e32 v8, v4, v5
	s_add_i32 s1, s18, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s1, s1, s0
	v_xor_b32_e32 v8, v8, v5
	v_cvt_f32_u32_e32 v6, s1
	s_sub_i32 s3, 0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v6
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, s3
	s_add_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s2, 27
	s_mul_i32 s3, s2, s1
	s_add_i32 s8, s2, 1
	s_sub_i32 s3, 32, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s9, s3, s1
	s_cmp_ge_u32 s3, s1
	s_cselect_b32 s2, s8, s2
	s_cselect_b32 s3, s9, s3
	s_add_i32 s8, s2, 1
	s_cmp_ge_u32 s3, s1
	s_cselect_b32 s1, s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s1, s1, s0
	s_sub_i32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_add_i32 s2, s0, s1
	v_xor_b32_e32 v5, s1, v5
	s_xor_b32 s2, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v6, s2
	s_sub_i32 s3, 0, s2
	v_rcp_iflag_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v7, s3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v7
	v_add_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v8, v6
	v_mul_lo_u32 v7, v6, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v8, v7
	v_add_nc_u32_e32 v8, 1, v6
	v_subrev_nc_u32_e32 v9, s2, v7
	v_cmp_le_u32_e32 vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	v_cmp_le_u32_e32 vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, 1, v6
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v6, v5
	v_sub_nc_u32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v5, s0
	s_mov_b32 s0, 0
	v_sub_nc_u32_e32 v4, v4, v6
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v4, s18
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_lshlrev_b32_e32 v6, v7, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_atomic_or_b32 v[4:5], v6, off
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v4, s0, v1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 4
	ds_load_i8 v7, v4
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[4:5], null, 0x83, v6, v[7:8]
	v_mov_b32_e32 v6, v4
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ; %BKDR_hash.exit
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x7fffffff, v4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_mul_lo_u32 v0, v0, s19
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v6, v5
	v_sub_nc_u32_e32 v7, 0, v5
	v_rcp_iflag_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v7, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v7
	v_add_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v4, v6
	v_mul_lo_u32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v6, v4, v5
	v_cmp_ge_u32_e32 vcc_lo, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_sub_nc_u32_e32 v6, v4, v5
	v_cmp_ge_u32_e32 vcc_lo, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_lshl_add_u32 v0, v0, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v3, v[2:3], off
	global_load_b32 v2, v[4:5], off
.LBB0_7:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v2, v3
	global_atomic_cmpswap_b32 v1, v[4:5], v[1:2], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v2
	v_mov_b32_e32 v2, v1
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s19, v0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
.LBB0_9:                                ; %atomicrmw.start47
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, 1.0, v3
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_9
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel InsertKernel
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	InsertKernel, .Lfunc_end0-InsertKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1140
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	get_lsstable_kernel     ; -- Begin function get_lsstable_kernel
	.globl	get_lsstable_kernel
	.p2align	8
	.type	get_lsstable_kernel,@function
get_lsstable_kernel:                    ; @get_lsstable_kernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s10, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_ashr_i32 s3, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s10, 0xffff
	s_add_u32 s6, s6, s8
	s_addc_u32 s7, s7, s9
	v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
	s_load_b32 s6, s[6:7], 0x0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB1_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0x14
	s_lshl_b32 s1, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 s2, s1, 1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s2, s0, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mad_u64_u32 v[2:3], null, s1, s0, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v7
	v_div_fixup_f32 v0, v4, v0, v3
	global_store_b32 v[1:2], v0, off
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel get_lsstable_kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	get_lsstable_kernel, .Lfunc_end1-get_lsstable_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	Decode_Multi_Kernel     ; -- Begin function Decode_Multi_Kernel
	.globl	Decode_Multi_Kernel
	.p2align	8
	.type	Decode_Multi_Kernel,@function
Decode_Multi_Kernel:                    ; @Decode_Multi_Kernel
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
	s_mov_b32 s2, exec_lo
	scratch_store_b32 off, v2, off offset:4
	v_cmpx_gt_i32_e64 s16, v2
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_ashr_i32 s3, s19, 31
	v_ashrrev_i32_e32 v5, 31, v2
	s_add_i32 s12, s19, s3
	s_load_b64 s[0:1], s[0:1], 0x30
	s_xor_b32 s12, s12, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v3, s12
	s_sub_i32 s14, 0, s12
	v_add_nc_u32_e32 v6, v2, v5
	v_rcp_iflag_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v6, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s13, v3
	s_mul_i32 s14, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s14, s13, s14
	s_add_i32 s13, s13, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s13, s13, 27
	s_mul_i32 s14, s13, s12
	s_add_i32 s15, s13, 1
	s_sub_i32 s14, 32, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s20, s14, s12
	s_cmp_ge_u32 s14, s12
	s_cselect_b32 s13, s15, s13
	s_cselect_b32 s14, s20, s14
	s_add_i32 s15, s13, 1
	s_cmp_ge_u32 s14, s12
	s_cselect_b32 s12, s15, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s12, s12, s3
	s_sub_i32 s3, s12, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s12, s3, 31
	s_add_i32 s13, s3, s12
	v_xor_b32_e32 v5, s12, v5
	s_xor_b32 s13, s13, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s13
	s_sub_i32 s14, 0, s13
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v6, v3
	v_mul_lo_u32 v4, v3, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v4
	v_add_nc_u32_e32 v6, 1, v3
	v_subrev_nc_u32_e32 v7, s13, v4
	v_cmp_le_u32_e32 vcc_lo, s13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_mov_b32 v7, 0
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s13, v4
	v_add_nc_u32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_xor_b32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v3, v5
	v_mad_u64_u32 v[3:4], null, v0, s18, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_mov_b32 s6, 0
	global_load_b32 v6, v[3:4], off
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s7, s6, 4
	s_add_i32 s6, s6, 1
	scratch_load_i8 v8, off, s7
	s_cmp_lg_u32 s6, 4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, 0x83, v7, v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v3
	s_cbranch_scc1 .LBB2_2
; %bb.3:                                ; %BKDR_hash.exit
	v_mul_lo_u32 v4, v5, s3
	v_and_b32_e32 v3, 0x7fffffff, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v2, v4
	v_mul_lo_u32 v2, v2, s19
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v4, s0, -1, v2
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v4, v2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_mul_lo_u32 v4, s1, v4
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v2, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v5, v2
	v_sub_nc_u32_e32 v6, 0, v2
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v5, v5
	v_mul_lo_u32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v6
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v3, v5
	v_mul_lo_u32 v5, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v5
	v_sub_nc_u32_e32 v5, v3, v2
	v_cmp_ge_u32_e32 vcc_lo, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_sub_nc_u32_e32 v5, v3, v2
	v_cmp_ge_u32_e32 vcc_lo, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v3, v5, vcc_lo
	v_lshl_add_u32 v2, v4, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	v_mad_u64_u32 v[2:3], null, v1, s17, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, v2, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
.LBB2_4:                                ; %Flow71
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s0, s17, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_cmp_lt_u32 s0, 3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_9
; %bb.5:                                ; %.lr.ph
	v_mad_u64_u32 v[2:3], null, v1, s17, v[0:1]
	s_mov_b32 s0, s17
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, v2, 2, 0
.LBB2_6:                                ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s1
	s_mov_b32 s1, exec_lo
	s_ashr_i32 s0, s0, 1
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_6 Depth=1
	v_lshl_add_u32 v3, s0, 2, v2
	ds_load_b32 v3, v3
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	ds_store_b32 v2, v3
.LBB2_8:                                ;   in Loop: Header=BB2_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s1, s0, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_u32 s1, 2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_6
.LBB2_9:                                ; %._crit_edge
	scratch_load_b32 v2, off, off offset:4
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_11
; %bb.10:
	v_mul_lo_u32 v0, v1, s17
	v_cvt_f32_i32_e32 v5, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, v0, 2, 0
	ds_load_b32 v4, v0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v0, null, v5, v5, v4
	v_div_scale_f32 v6, vcc_lo, v4, v5, v4
	v_rcp_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v0, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v3, v1
	v_mul_f32_e32 v7, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v0, v7, v6
	v_fmac_f32_e32 v7, v3, v1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v0, v7, v6
	v_div_fmas_f32 v6, v0, v1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_div_fixup_f32 v2, v6, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel Decode_Multi_Kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	Decode_Multi_Kernel, .Lfunc_end2-Decode_Multi_Kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1204
; NumSgprs: 23
; NumVgprs: 10
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           InsertKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         InsertKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           get_lsstable_kernel
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         get_lsstable_kernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           Decode_Multi_Kernel
    .private_segment_fixed_size: 8
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         Decode_Multi_Kernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
