/* Voxel sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 */
#include <stdio.h>
#include <iostream>
#include <float.h>  // import FLT_EPSILON

__device__ int get_batch_id(int* accu_list, int batch_size, int id) {
    for (int b=0; b<batch_size-1; b++) {
        if (id >= accu_list[b]) {
            if(id < accu_list[b+1])
                return b;
        }
    }
    return batch_size - 1;
}


__global__ void output_init_gpu_kernel(int roi_num, int voxel_num, int channels, int pooling_size, float padding_value,
                                       float* output_features,
                                       int* output_idx) {
    int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (thread_id < roi_num * voxel_num) {
        for (int c=0; c<channels; c++) {
            output_features[thread_id * channels + c] = padding_value;
        }
        for (int p=0; p<pooling_size; p++) {
            output_idx[thread_id * pooling_size + p] = -1;
        }
    }
}


__global__ void grid_buffer_init_gpu_kernel(int batch_size, int input_point_num,
                                            float grid_buffer_resolution, int grid_buffer_size,
                                            int grid_dim_w, int grid_dim_l, int grid_dim_h,
                                            const float* input_coors,
                                            int* input_accu_list,
                                            int* grid_buffer,
                                            int* grid_buffer_count) {
    const int grid_dim_size = grid_dim_w * grid_dim_h * grid_dim_l;
    int point_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (point_id < input_point_num) {
        int grid_coor_x = __float2int_rz(input_coors[point_id*3 + 0] / grid_buffer_resolution);
        int grid_coor_y = __float2int_rz(input_coors[point_id*3 + 1] / grid_buffer_resolution);
        int grid_coor_z = __float2int_rz(input_coors[point_id*3 + 2] / grid_buffer_resolution);
        grid_coor_x = max(0, min(grid_coor_x, grid_dim_w - 1));
        grid_coor_y = max(0, min(grid_coor_y, grid_dim_l - 1));
        grid_coor_z = max(0, min(grid_coor_z, grid_dim_h - 1));
        int batch_id = get_batch_id(input_accu_list, batch_size, point_id);
        int grid_buffer_idx = batch_id * grid_dim_size + grid_coor_x * grid_dim_l * grid_dim_h + grid_coor_y * grid_dim_h + grid_coor_z;
        int count = atomicAdd(&grid_buffer_count[grid_buffer_idx], 1);
        if (count < grid_buffer_size)
            grid_buffer[grid_buffer_idx * grid_buffer_size + count] = point_id;
    }
}


__global__ void roi_pooling_register_gpu_kernel(int batch_size, int roi_num,
                                                int voxel_size, int pooling_size,
                                                float grid_buffer_resolution, int grid_buffer_size,
                                                float offset_w, float offset_l, float offset_h,
                                                int grid_dim_w, int grid_dim_l, int grid_dim_h,
                                                const float* input_coors,
                                                const float* roi_attrs,
                                                const int* input_num_lists,
                                                int* input_accu_list,
                                                int* roi_accu_list,
                                                int* temp_count,
                                                int* grid_buffer,
                                                int* grid_buffer_count,
                                                int* output_idx,
                                                float* output_weight) {
    const int voxel_num = voxel_size * voxel_size * voxel_size;
    const int grid_dim_size = grid_dim_w * grid_dim_l * grid_dim_h;
    const int half_voxel_size = (voxel_size - voxel_size % 2) / 2;
//    const int center_offset = voxel_size * voxel_size * half_voxel_size + \
//                              voxel_size * half_voxel_size + \
//                              half_voxel_size;
    int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (thread_id < roi_num * voxel_num) {
        int roi_id = thread_id / voxel_num;
        int voxel_id = thread_id % voxel_num;
        int voxel_coor = roi_id * voxel_num + voxel_id;
        int batch_id = get_batch_id(roi_accu_list, batch_size, roi_id);

        float roi_w = roi_attrs[roi_id*7 + 0];
        float roi_l = roi_attrs[roi_id*7 + 1];
        float roi_h = roi_attrs[roi_id*7 + 2];
        float roi_x = roi_attrs[roi_id*7 + 3] + offset_w;
        float roi_y = roi_attrs[roi_id*7 + 4] + offset_l;
        float roi_z = roi_attrs[roi_id*7 + 5] + offset_h;
        float roi_r = roi_attrs[roi_id*7 + 6];

//            printf("%d, %d, %d\n", grid_coor_x, grid_coor_y, grid_coor_z);

        float roi_grid_length_x = roi_w / voxel_size;
        float roi_grid_length_y = roi_l / voxel_size;
        float roi_grid_length_z = roi_h / voxel_size;
//

        int roi_grid_coor_x = voxel_id / (voxel_size * voxel_size);
        int roi_grid_coor_y = (voxel_id - roi_grid_coor_x * voxel_size * voxel_size) / voxel_size;
        int roi_grid_coor_z = voxel_id % voxel_size;

        roi_grid_coor_x -= half_voxel_size;
        roi_grid_coor_y -= half_voxel_size;
        roi_grid_coor_z -= half_voxel_size;

        float rel_roi_grid_x = (roi_grid_coor_x + 0.5 * (1 - voxel_size % 2)) * roi_grid_length_x;
        float rel_roi_grid_y = (roi_grid_coor_y + 0.5 * (1 - voxel_size % 2)) * roi_grid_length_y;
        float rel_roi_grid_z = (roi_grid_coor_z + 0.5 * (1 - voxel_size % 2)) * roi_grid_length_z;


        float rot_rel_roi_grid_x = rel_roi_grid_x*cosf(roi_r) - rel_roi_grid_y*sinf(roi_r);
        float rot_rel_roi_grid_y = rel_roi_grid_x*sinf(roi_r) + rel_roi_grid_y*cosf(roi_r);

        float act_roi_grid_x = rot_rel_roi_grid_x + roi_x;
        float act_roi_grid_y = rot_rel_roi_grid_y + roi_y;
        float act_roi_grid_z = rel_roi_grid_z + roi_z;

        int buffer_grid_coor_x = __float2int_rz(act_roi_grid_x / grid_buffer_resolution);
        int buffer_grid_coor_y = __float2int_rz(act_roi_grid_y / grid_buffer_resolution);
        int buffer_grid_coor_z = __float2int_rz(act_roi_grid_z / grid_buffer_resolution);

        int begin_buffer_grid_coor_x = max(0, buffer_grid_coor_x - 1);
        int begin_buffer_grid_coor_y = max(0, buffer_grid_coor_y - 1);
        int begin_buffer_grid_coor_z = max(0, buffer_grid_coor_z - 1);
        int stop_buffer_grid_coor_x = min(buffer_grid_coor_x + 1, grid_dim_w - 1);
        int stop_buffer_grid_coor_y = min(buffer_grid_coor_y + 1, grid_dim_l - 1);
        int stop_buffer_grid_coor_z = min(buffer_grid_coor_z + 1, grid_dim_h - 1);

        for (int x=begin_buffer_grid_coor_x; x<=stop_buffer_grid_coor_x; x++) {
            for (int y=begin_buffer_grid_coor_y; y<=stop_buffer_grid_coor_y; y++) {
                for (int z=begin_buffer_grid_coor_z; z<=stop_buffer_grid_coor_z; z++) {
                    if (temp_count[voxel_coor] >= pooling_size)
                        break;
                    int search_grid_id = batch_id * grid_dim_size + x * grid_dim_l * grid_dim_h + y * grid_dim_h + z;
                    int valid_buffer_count = min(grid_buffer_count[search_grid_id], grid_buffer_size);
//                    printf("grid buffer count = %d\n", grid_buffer_count[search_grid_id]);
                    for (int i=0; i<valid_buffer_count; i++) {
                        int point_id = grid_buffer[search_grid_id * grid_buffer_size + i];
                        float point_x = input_coors[point_id*3 + 0];
                        float point_y = input_coors[point_id*3 + 1];
                        float point_z = input_coors[point_id*3 + 2];

                        float rel_point_x = point_x - act_roi_grid_x;
                        float rel_point_y = point_y - act_roi_grid_y;
                        float rel_point_z = point_z - act_roi_grid_z;

                        float rel_rot_point_x = rel_point_x*cosf(-roi_r) - rel_point_y*sinf(-roi_r);
                        float rel_rot_point_y = rel_point_x*sinf(-roi_r) + rel_point_y*cosf(-roi_r);

//                        float dist_2 = pow(point_x - act_roi_grid_x, 2.) + pow(point_y - act_roi_grid_y, 2.) + pow(point_z - act_roi_grid_z, 2.);
//                        if (dist_2 < pow(radius, 2.)) {
                        if (abs(rel_rot_point_x) <= roi_grid_length_x * 1.25 &&
                            abs(rel_rot_point_y) <= roi_grid_length_y * 1.25 &&
                            abs(rel_point_z) <= roi_grid_length_z * 1.25) {
            //                printf("Yes\n");
                            float dist_2 = pow(point_x - act_roi_grid_x, 2.) + pow(point_y - act_roi_grid_y, 2.) + pow(point_z - act_roi_grid_z, 2.);
                            float dist = sqrt(dist_2);
                            float radius = max(max(roi_grid_length_x, roi_grid_length_y), roi_grid_length_z) / 2.;
                            float weight = 2.71828 / expf(dist / radius);
            //                float weight = 1.;

                            int pool_count = temp_count[voxel_coor];
                            if (pool_count < pooling_size) {
                                output_idx[voxel_coor * pooling_size + pool_count] = point_id;
                                output_weight[voxel_coor * pooling_size + pool_count] = weight;
                                temp_count[voxel_coor] += 1;
                            } else {
                                break;
                            }
                        }
                    }
                }
            }
        }
//        printf("Voxel Pooling = %d\n", temp_count[voxel_coor]);
    }
}

__global__ void roi_pooling_fill_gpu_kernel(int roi_num, int voxel_num, int channels, int pooling_size,
                                            const float* input_features,
                                            int* temp_count,
                                            float* output_features,
                                            int* output_idx,
                                            float* output_weight) {
    int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (thread_id < roi_num * voxel_num) {
        int pool_count = min(temp_count[thread_id], pooling_size);
        if (pool_count > 0) {
            float weight_sum = 0;
//            int pool_id;
            for (int p=0; p<pool_count; p++) {
//                pool_id = thread_id * pooling_size + p;
//                weight_sum += output_weight[pool_id];
                weight_sum += 1;
            }
            for (int p=0; p<pool_count; p++) {
                int pool_id = thread_id * pooling_size + p;
                int input_id = output_idx[pool_id];
                float weight = output_weight[pool_id] / weight_sum;
//                float weight = output_weight[pool_id];
//                printf("%d, %d, %f\n", input_id, pool_count, weight);
                output_weight[pool_id] = weight;
//                if (thread_id == 0)
//                    printf("Forward: %f\n", weight);
//                float temp_max = -1e6;
                for (int c=0; c < channels; c++) {
                    output_features[thread_id * channels + c] += input_features[input_id * channels + c] * weight;
//                    float features = input_features[input_id * channels + c] * weight;
//                    if (features > temp_max) {
//                        output_features[thread_id * channels + c] = features;
//                        temp_max = features;
//                    }
////                    printf("%d, %d\n", thread_id, input_id);
                }
            }
        }
    }
}


void roi_pooling_gpu_launcher(int batch_size, int input_point_num, int channels,
                              int roi_num, int voxel_size, int pooling_size, float padding_value,
                              float grid_buffer_resolution, int grid_buffer_size,
                              int grid_buffer_dim_w, int grid_buffer_dim_l, int grid_buffer_dim_h,
                              float offset_w, float offset_l, float offset_h,
                              const float* input_coors,
                              const float* input_features,
                              const float* roi_attrs,
                              const int* input_num_list,
                              const int* roi_num_list,
                              int* input_num_list_host,
                              int* input_accu_list,
                              int* roi_accu_list,
                              int* temp_count,
                              int* temp_grid_buffer,
                              int* temp_grid_buffer_count,
                              float* output_features,
                              int* output_idx,
                              float* output_weight) {

    if (batch_size * channels <= 0 || input_point_num <= 0) {
        printf("RoiPoolingFastOp ERROR: Invalid CUDA input dimensions.\n");
        return;
    }
    if (roi_num <= 0) {
        printf("RoiPoolingFastOp WARNING: No RoIs were found for the current batch.\n");
        return;
    }
//    printf("RoI Num: %d\n", roi_num);
    const int voxel_num = voxel_size * voxel_size * voxel_size;


    int blockSize;      // The launch configurator returned block size
    int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch
    int gridSize;       // The actual grid size needed, based on input size

    cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, roi_num * voxel_num);
    gridSize = (roi_num * voxel_num + blockSize - 1) / blockSize;
    output_init_gpu_kernel<<<gridSize,blockSize>>>(roi_num, voxel_num, channels, pooling_size, padding_value,
                                                   output_features,
                                                   output_idx);

    cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, grid_buffer_init_gpu_kernel, 0, input_point_num);
    gridSize = (input_point_num + blockSize - 1) / blockSize;
    grid_buffer_init_gpu_kernel<<<gridSize,blockSize>>>(batch_size, input_point_num,
                                                        grid_buffer_resolution, grid_buffer_size,
                                                        grid_buffer_dim_w, grid_buffer_dim_l, grid_buffer_dim_h,
                                                        input_coors,
                                                        input_accu_list,
                                                        temp_grid_buffer,
                                                        temp_grid_buffer_count);

    cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_pooling_register_gpu_kernel, 0, roi_num * voxel_num);
    gridSize = (roi_num * voxel_num + blockSize - 1) / blockSize;
    roi_pooling_register_gpu_kernel<<<gridSize,blockSize>>>(batch_size, roi_num,
                                                            voxel_size, pooling_size,
                                                            grid_buffer_resolution, grid_buffer_size,
                                                            offset_w, offset_l, offset_h,
                                                            grid_buffer_dim_w, grid_buffer_dim_l, grid_buffer_dim_h,
                                                            input_coors,
                                                            roi_attrs,
                                                            input_num_list,
                                                            input_accu_list,
                                                            roi_accu_list,
                                                            temp_count,
                                                            temp_grid_buffer,
                                                            temp_grid_buffer_count,
                                                            output_idx,
                                                            output_weight);

    cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_pooling_fill_gpu_kernel, 0, roi_num * voxel_num);
    gridSize = (roi_num * voxel_num + blockSize - 1) / blockSize;
    roi_pooling_fill_gpu_kernel<<<gridSize,blockSize>>>(roi_num, voxel_num, channels, pooling_size,
                                                        input_features,
                                                        temp_count,
                                                        output_features,
                                                        output_idx,
                                                        output_weight);
}

	.file	"tmpxft_00331b10_00000000-6_la_roi_pooling_fast.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0, @function
_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0:
.LFB4306:
	.cfi_startproc
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdx, (%rsp)
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	call	cudaGetDevice@PLT
	testl	%eax, %eax
	jne	.L2
	movl	32(%rsp), %edx
	leaq	36(%rsp), %rdi
	movl	$39, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L2
	movl	32(%rsp), %edx
	leaq	40(%rsp), %rdi
	movl	$10, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L2
	movl	32(%rsp), %edx
	leaq	44(%rsp), %rdi
	movl	$1, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L2
	movl	32(%rsp), %edx
	leaq	48(%rsp), %rdi
	movl	$16, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L2
	movq	(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaFuncGetAttributes@PLT
	testl	%eax, %eax
	jne	.L2
	movl	36(%rsp), %eax
	movl	80(%rsp), %ebp
	testl	%ebx, %ebx
	movl	40(%rsp), %r9d
	movl	%eax, 16(%rsp)
	movl	44(%rsp), %eax
	cmove	%eax, %ebx
	cmpl	%eax, %ebp
	cmovg	%eax, %ebp
	cmpl	%ebx, %ebp
	cmovg	%ebx, %ebp
	xorl	%r10d, %r10d
	xorl	%r12d, %r12d
	xorl	%r15d, %r15d
	leal	-1(%r9,%rbp), %ebx
	movl	%ebx, %eax
	cltd
	idivl	%r9d
	leaq	52(%rsp), %rax
	movq	%rax, 8(%rsp)
	subl	%edx, %ebx
.L7:
	testl	%ebx, %ebx
	jle	.L9
	cmpl	%ebx, %ebp
	movl	%ebx, %edx
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	cmovle	%ebp, %edx
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	movl	%r10d, 28(%rsp)
	movl	%r9d, 24(%rsp)
	movl	%edx, 20(%rsp)
	call	cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
	testl	%eax, %eax
	jne	.L2
	movl	20(%rsp), %edx
	movl	52(%rsp), %eax
	movl	28(%rsp), %r10d
	movl	24(%rsp), %r9d
	movl	%edx, %ecx
	imull	%eax, %ecx
	cmpl	%r10d, %ecx
	jle	.L8
	movl	%ecx, %r10d
	movl	%eax, %r12d
	movl	%edx, %r15d
.L8:
	cmpl	%r10d, 16(%rsp)
	je	.L9
	subl	%r9d, %ebx
	jmp	.L7
.L9:
	imull	48(%rsp), %r12d
	movl	%r12d, (%r14)
	movl	%r15d, 0(%r13)
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4306:
	.size	_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0, .-_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0
	.globl	_Z12get_batch_idPiii
	.type	_Z12get_batch_idPiii, @function
_Z12get_batch_idPiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z12get_batch_idPiii, .-_Z12get_batch_idPiii
	.globl	_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi
	.type	_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi, @function
_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z22output_init_gpu_kerneliiiifPfPi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L18:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi, .-_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi
	.globl	_Z22output_init_gpu_kerneliiiifPfPi
	.type	_Z22output_init_gpu_kerneliiiifPfPi, @function
_Z22output_init_gpu_kerneliiiifPfPi:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi
	.cfi_endproc
.LFE3662:
	.size	_Z22output_init_gpu_kerneliiiifPfPi, .-_Z22output_init_gpu_kerneliiiifPfPi
	.globl	_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_
	.type	_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_, @function
_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movl	%edx, 48(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movl	%ecx, 44(%rsp)
	leaq	72(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	264(%rsp), %rax
	movl	%r8d, 40(%rsp)
	movl	%r9d, 36(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 52(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L23:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_, .-_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_
	.globl	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.type	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, @function
_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_
	.cfi_endproc
.LFE3664:
	.size	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, .-_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.globl	_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.type	_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, @function
_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$392, %rsp
	.cfi_def_cfa_offset 400
	movq	416(%rsp), %rax
	movl	%edi, 124(%rsp)
	leaq	152(%rsp), %rdi
	movl	%esi, 120(%rsp)
	leaq	164(%rsp), %rsi
	movq	%rax, 80(%rsp)
	movq	424(%rsp), %rax
	movl	%edx, 116(%rsp)
	leaq	136(%rsp), %rdx
	movq	%rax, 72(%rsp)
	movq	432(%rsp), %rax
	movl	%ecx, 112(%rsp)
	leaq	144(%rsp), %rcx
	movq	%rax, 64(%rsp)
	movq	440(%rsp), %rax
	movl	%r8d, 104(%rsp)
	movq	%rax, 56(%rsp)
	movq	448(%rsp), %rax
	movl	%r9d, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	456(%rsp), %rax
	movss	%xmm0, 108(%rsp)
	movq	%rax, 40(%rsp)
	movq	464(%rsp), %rax
	movss	%xmm1, 100(%rsp)
	movq	%rax, 32(%rsp)
	movq	472(%rsp), %rax
	movss	%xmm2, 96(%rsp)
	movq	%rax, 24(%rsp)
	movq	480(%rsp), %rax
	movss	%xmm3, 92(%rsp)
	movq	%rax, 16(%rsp)
	movq	488(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 376(%rsp)
	xorl	%eax, %eax
	leaq	124(%rsp), %rax
	movl	$1, 160(%rsp)
	movq	%rax, 200(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	116(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	108(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	100(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	92(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 368(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 152(%rsp)
	movq	%rax, 164(%rsp)
	movl	$1, 172(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	144(%rsp)
	.cfi_def_cfa_offset 408
	leaq	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf(%rip), %rdi
	pushq	144(%rsp)
	.cfi_def_cfa_offset 416
	movq	180(%rsp), %rcx
	movl	188(%rsp), %r8d
	movq	168(%rsp), %rsi
	movl	176(%rsp), %edx
	leaq	216(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 408
	popq	%rdx
	.cfi_def_cfa_offset 400
.L28:
	movq	376(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$392, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, .-_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.globl	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.type	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, @function
_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.cfi_endproc
.LFE3666:
	.size	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, .-_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.globl	_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_
	.type	_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_, @function
_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_:
.LFB3667:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	240(%rsp), %rax
	movl	%ecx, 48(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L33:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_, .-_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_
	.globl	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.type	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, @function
_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_
	.cfi_endproc
.LFE3668:
	.size	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, .-_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"RoiPoolingFastOp ERROR: Invalid CUDA input dimensions.\n"
.LC1:
	.string	"RoiPoolingFastOp WARNING: No RoIs were found for the current batch.\n"
	.text
	.globl	_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_
	.type	_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_, @function
_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movl	256(%rsp), %eax
	movl	%edi, 16(%rsp)
	movl	%edx, 20(%rsp)
	movl	%eax, 40(%rsp)
	movl	264(%rsp), %eax
	movl	%r9d, 32(%rsp)
	movl	%eax, 44(%rsp)
	movl	272(%rsp), %eax
	movss	%xmm1, 36(%rsp)
	movl	%eax, 48(%rsp)
	movl	280(%rsp), %eax
	movss	%xmm2, 96(%rsp)
	movl	%eax, 52(%rsp)
	movq	288(%rsp), %rax
	movss	%xmm3, 100(%rsp)
	movq	%rax, 56(%rsp)
	movq	296(%rsp), %rax
	movss	%xmm4, 136(%rsp)
	movq	%rax, 104(%rsp)
	movq	304(%rsp), %rax
	movq	360(%rsp), %r14
	movq	368(%rsp), %r15
	movq	%rax, 112(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	336(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	344(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	352(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	376(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	movl	%edi, %eax
	imull	%edx, %eax
	testl	%eax, %eax
	jle	.L51
	movl	%esi, %r12d
	testl	%esi, %esi
	jg	.L39
.L51:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	leaq	.LC0(%rip), %rsi
	je	.L53
	jmp	.L54
.L39:
	movl	%ecx, %r13d
	testl	%ecx, %ecx
	jg	.L42
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	leaq	.LC1(%rip), %rsi
	jne	.L54
.L53:
	addq	$200, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L42:
	.cfi_restore_state
	movl	%r8d, %eax
	leaq	152(%rsp), %rsi
	movl	%r8d, %ebp
	movss	%xmm0, 140(%rsp)
	imull	%r8d, %eax
	leaq	156(%rsp), %rdi
	leaq	_Z22output_init_gpu_kerneliiiifPfPi(%rip), %rdx
	imull	%r8d, %eax
	movl	%eax, %ebx
	movl	%eax, 12(%rsp)
	imull	%ecx, %ebx
	xorl	%ecx, %ecx
	movl	%ebx, %r8d
	call	_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rsi
	leal	-1(%rbx,%rcx), %eax
	movq	%rsi, 176(%rsp)
	cltd
	movl	%ecx, 172(%rsp)
	idivl	%ecx
	movq	%rsi, 164(%rsp)
	movl	180(%rsp), %ecx
	movq	172(%rsp), %rdx
	movl	168(%rsp), %esi
	movl	%eax, 160(%rsp)
	movq	160(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	140(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L44
	movq	24(%rsp), %r9
	movq	80(%rsp), %r8
	movl	%r13d, %edi
	movl	32(%rsp), %ecx
	movl	20(%rsp), %edx
	movl	12(%rsp), %esi
	call	_Z49__device_stub__Z22output_init_gpu_kerneliiiifPfPiiiiifPfPi
.L44:
	xorl	%ecx, %ecx
	leaq	152(%rsp), %rsi
	movl	%r12d, %r8d
	leaq	156(%rsp), %rdi
	leaq	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_(%rip), %rdx
	call	_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rsi
	leal	-1(%rcx,%r12), %eax
	movq	%rsi, 176(%rsp)
	cltd
	movl	%ecx, 172(%rsp)
	idivl	%ecx
	movq	%rsi, 164(%rsp)
	movl	180(%rsp), %ecx
	movq	172(%rsp), %rdx
	movl	168(%rsp), %esi
	movl	%eax, 160(%rsp)
	movq	160(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	%r15
	.cfi_def_cfa_offset 264
	movl	%r12d, %esi
	pushq	%r14
	.cfi_def_cfa_offset 272
	pushq	80(%rsp)
	.cfi_def_cfa_offset 280
	pushq	80(%rsp)
	.cfi_def_cfa_offset 288
	movl	84(%rsp), %r9d
	movl	80(%rsp), %r8d
	movl	76(%rsp), %ecx
	movl	72(%rsp), %edx
	movss	68(%rsp), %xmm0
	movl	48(%rsp), %edi
	call	_Z63__device_stub__Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_iifiiiiPKfPiS1_S1_
	addq	$32, %rsp
	.cfi_def_cfa_offset 256
.L45:
	xorl	%ecx, %ecx
	leaq	152(%rsp), %rsi
	movl	%ebx, %r8d
	leaq	156(%rsp), %rdi
	leaq	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf(%rip), %rdx
	call	_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rsi
	leal	-1(%rbx,%rcx), %eax
	movq	%rsi, 176(%rsp)
	cltd
	movl	%ecx, 172(%rsp)
	idivl	%ecx
	movq	%rsi, 164(%rsp)
	movl	180(%rsp), %ecx
	movq	172(%rsp), %rdx
	movl	168(%rsp), %esi
	movl	%eax, 160(%rsp)
	movq	160(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	movl	%ebp, %edx
	movl	%r13d, %esi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 272
	pushq	%r15
	.cfi_def_cfa_offset 280
	pushq	%r14
	.cfi_def_cfa_offset 288
	pushq	104(%rsp)
	.cfi_def_cfa_offset 296
	pushq	168(%rsp)
	.cfi_def_cfa_offset 304
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	pushq	176(%rsp)
	.cfi_def_cfa_offset 320
	pushq	176(%rsp)
	.cfi_def_cfa_offset 328
	pushq	128(%rsp)
	.cfi_def_cfa_offset 336
	movl	132(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 344
	movl	136(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 352
	movl	140(%rsp), %r9d
	movss	232(%rsp), %xmm3
	movl	136(%rsp), %r8d
	movss	196(%rsp), %xmm2
	movl	128(%rsp), %ecx
	movss	192(%rsp), %xmm1
	movl	112(%rsp), %edi
	movss	132(%rsp), %xmm0
	call	_Z89__device_stub__Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_PfiiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	addq	$96, %rsp
	.cfi_def_cfa_offset 256
.L46:
	xorl	%ecx, %ecx
	leaq	152(%rsp), %rsi
	movl	%ebx, %r8d
	leaq	156(%rsp), %rdi
	leaq	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_(%rip), %rdx
	call	_Z55cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlagsI24__cudaOccupancyB2DHelperPFviiiifPfPiEE9cudaErrorS2_S2_T0_T_ij.constprop.0.isra.0
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rsi
	leal	-1(%rbx,%rcx), %eax
	movq	%rsi, 176(%rsp)
	cltd
	movl	%ecx, 172(%rsp)
	idivl	%ecx
	movq	%rsi, 164(%rsp)
	movl	180(%rsp), %ecx
	movq	172(%rsp), %rdx
	movl	168(%rsp), %esi
	movl	%eax, 160(%rsp)
	movq	160(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L54
	movq	88(%rsp), %rax
	movq	72(%rsp), %r9
	movl	%r13d, %edi
	movq	104(%rsp), %r8
	movl	32(%rsp), %ecx
	movl	20(%rsp), %edx
	movl	12(%rsp), %esi
	movq	%rax, 272(%rsp)
	movq	24(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	80(%rsp), %rax
	movq	%rax, 256(%rsp)
	addq	$200, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z62__device_stub__Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_iiiiPKfPiPfS1_S2_
.L38:
	.cfi_restore_state
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
.L54:
	call	__stack_chk_fail@PLT
.L50:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_, .-_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_
	.section	.rodata.str1.1
.LC2:
	.string	"_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_"
.LC3:
	.string	"_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf"
.LC4:
	.string	"_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_"
.LC5:
	.string	"_Z22output_init_gpu_kerneliiiifPfPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3670:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22output_init_gpu_kerneliiiifPfPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3670:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Voxel sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <float.h>  // import FLT_EPSILON

__device__ int get_batch_id(int* accu_list, int batch_size, int id) {
    for (int b=0; b<batch_size-1; b++) {
        if (id >= accu_list[b]) {
            if(id < accu_list[b+1])
                return b;
        }
    }
    return batch_size - 1;
}


__global__ void output_init_gpu_kernel(int roi_num, int voxel_num, int channels, int pooling_size, float padding_value,
                                       float* output_features,
                                       int* output_idx) {
    int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (thread_id < roi_num * voxel_num) {
        for (int c=0; c<channels; c++) {
            output_features[thread_id * channels + c] = padding_value;
        }
        for (int p=0; p<pooling_size; p++) {
            output_idx[thread_id * pooling_size + p] = -1;
        }
    }
}


__global__ void grid_buffer_init_gpu_kernel(int batch_size, int input_point_num,
                                            float grid_buffer_resolution, int grid_buffer_size,
                                            int grid_dim_w, int grid_dim_l, int grid_dim_h,
                                            const float* input_coors,
                                            int* input_accu_list,
                                            int* grid_buffer,
                                            int* grid_buffer_count) {
    const int grid_dim_size = grid_dim_w * grid_dim_h * grid_dim_l;
    int point_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (point_id < input_point_num) {
        int grid_coor_x = __float2int_rz(input_coors[point_id*3 + 0] / grid_buffer_resolution);
        int grid_coor_y = __float2int_rz(input_coors[point_id*3 + 1] / grid_buffer_resolution);
        int grid_coor_z = __float2int_rz(input_coors[point_id*3 + 2] / grid_buffer_resolution);
        grid_coor_x = max(0, min(grid_coor_x, grid_dim_w - 1));
        grid_coor_y = max(0, min(grid_coor_y, grid_dim_l - 1));
        grid_coor_z = max(0, min(grid_coor_z, grid_dim_h - 1));
        int batch_id = get_batch_id(input_accu_list, batch_size, point_id);
        int grid_buffer_idx = batch_id * grid_dim_size + grid_coor_x * grid_dim_l * grid_dim_h + grid_coor_y * grid_dim_h + grid_coor_z;
        int count = atomicAdd(&grid_buffer_count[grid_buffer_idx], 1);
        if (count < grid_buffer_size)
            grid_buffer[grid_buffer_idx * grid_buffer_size + count] = point_id;
    }
}


__global__ void roi_pooling_register_gpu_kernel(int batch_size, int roi_num,
                                                int voxel_size, int pooling_size,
                                                float grid_buffer_resolution, int grid_buffer_size,
                                                float offset_w, float offset_l, float offset_h,
                                                int grid_dim_w, int grid_dim_l, int grid_dim_h,
                                                const float* input_coors,
                                                const float* roi_attrs,
                                                const int* input_num_lists,
                                                int* input_accu_list,
                                                int* roi_accu_list,
                                                int* temp_count,
                                                int* grid_buffer,
                                                int* grid_buffer_count,
                                                int* output_idx,
                                                float* output_weight) {
    const int voxel_num = voxel_size * voxel_size * voxel_size;
    const int grid_dim_size = grid_dim_w * grid_dim_l * grid_dim_h;
    const int half_voxel_size = (voxel_size - voxel_size % 2) / 2;
//    const int center_offset = voxel_size * voxel_size * half_voxel_size + \
//                              voxel_size * half_voxel_size + \
//                              half_voxel_size;
    int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (thread_id < roi_num * voxel_num) {
        int roi_id = thread_id / voxel_num;
        int voxel_id = thread_id % voxel_num;
        int voxel_coor = roi_id * voxel_num + voxel_id;
        int batch_id = get_batch_id(roi_accu_list, batch_size, roi_id);

        float roi_w = roi_attrs[roi_id*7 + 0];
        float roi_l = roi_attrs[roi_id*7 + 1];
        float roi_h = roi_attrs[roi_id*7 + 2];
        float roi_x = roi_attrs[roi_id*7 + 3] + offset_w;
        float roi_y = roi_attrs[roi_id*7 + 4] + offset_l;
        float roi_z = roi_attrs[roi_id*7 + 5] + offset_h;
        float roi_r = roi_attrs[roi_id*7 + 6];

//            printf("%d, %d, %d\n", grid_coor_x, grid_coor_y, grid_coor_z);

        float roi_grid_length_x = roi_w / voxel_size;
        float roi_grid_length_y = roi_l / voxel_size;
        float roi_grid_length_z = roi_h / voxel_size;
//

        int roi_grid_coor_x = voxel_id / (voxel_size * voxel_size);
        int roi_grid_coor_y = (voxel_id - roi_grid_coor_x * voxel_size * voxel_size) / voxel_size;
        int roi_grid_coor_z = voxel_id % voxel_size;

        roi_grid_coor_x -= half_voxel_size;
        roi_grid_coor_y -= half_voxel_size;
        roi_grid_coor_z -= half_voxel_size;

        float rel_roi_grid_x = (roi_grid_coor_x + 0.5 * (1 - voxel_size % 2)) * roi_grid_length_x;
        float rel_roi_grid_y = (roi_grid_coor_y + 0.5 * (1 - voxel_size % 2)) * roi_grid_length_y;
        float rel_roi_grid_z = (roi_grid_coor_z + 0.5 * (1 - voxel_size % 2)) * roi_grid_length_z;


        float rot_rel_roi_grid_x = rel_roi_grid_x*cosf(roi_r) - rel_roi_grid_y*sinf(roi_r);
        float rot_rel_roi_grid_y = rel_roi_grid_x*sinf(roi_r) + rel_roi_grid_y*cosf(roi_r);

        float act_roi_grid_x = rot_rel_roi_grid_x + roi_x;
        float act_roi_grid_y = rot_rel_roi_grid_y + roi_y;
        float act_roi_grid_z = rel_roi_grid_z + roi_z;

        int buffer_grid_coor_x = __float2int_rz(act_roi_grid_x / grid_buffer_resolution);
        int buffer_grid_coor_y = __float2int_rz(act_roi_grid_y / grid_buffer_resolution);
        int buffer_grid_coor_z = __float2int_rz(act_roi_grid_z / grid_buffer_resolution);

        int begin_buffer_grid_coor_x = max(0, buffer_grid_coor_x - 1);
        int begin_buffer_grid_coor_y = max(0, buffer_grid_coor_y - 1);
        int begin_buffer_grid_coor_z = max(0, buffer_grid_coor_z - 1);
        int stop_buffer_grid_coor_x = min(buffer_grid_coor_x + 1, grid_dim_w - 1);
        int stop_buffer_grid_coor_y = min(buffer_grid_coor_y + 1, grid_dim_l - 1);
        int stop_buffer_grid_coor_z = min(buffer_grid_coor_z + 1, grid_dim_h - 1);

        for (int x=begin_buffer_grid_coor_x; x<=stop_buffer_grid_coor_x; x++) {
            for (int y=begin_buffer_grid_coor_y; y<=stop_buffer_grid_coor_y; y++) {
                for (int z=begin_buffer_grid_coor_z; z<=stop_buffer_grid_coor_z; z++) {
                    if (temp_count[voxel_coor] >= pooling_size)
                        break;
                    int search_grid_id = batch_id * grid_dim_size + x * grid_dim_l * grid_dim_h + y * grid_dim_h + z;
                    int valid_buffer_count = min(grid_buffer_count[search_grid_id], grid_buffer_size);
//                    printf("grid buffer count = %d\n", grid_buffer_count[search_grid_id]);
                    for (int i=0; i<valid_buffer_count; i++) {
                        int point_id = grid_buffer[search_grid_id * grid_buffer_size + i];
                        float point_x = input_coors[point_id*3 + 0];
                        float point_y = input_coors[point_id*3 + 1];
                        float point_z = input_coors[point_id*3 + 2];

                        float rel_point_x = point_x - act_roi_grid_x;
                        float rel_point_y = point_y - act_roi_grid_y;
                        float rel_point_z = point_z - act_roi_grid_z;

                        float rel_rot_point_x = rel_point_x*cosf(-roi_r) - rel_point_y*sinf(-roi_r);
                        float rel_rot_point_y = rel_point_x*sinf(-roi_r) + rel_point_y*cosf(-roi_r);

//                        float dist_2 = pow(point_x - act_roi_grid_x, 2.) + pow(point_y - act_roi_grid_y, 2.) + pow(point_z - act_roi_grid_z, 2.);
//                        if (dist_2 < pow(radius, 2.)) {
                        if (abs(rel_rot_point_x) <= roi_grid_length_x * 1.25 &&
                            abs(rel_rot_point_y) <= roi_grid_length_y * 1.25 &&
                            abs(rel_point_z) <= roi_grid_length_z * 1.25) {
            //                printf("Yes\n");
                            float dist_2 = pow(point_x - act_roi_grid_x, 2.) + pow(point_y - act_roi_grid_y, 2.) + pow(point_z - act_roi_grid_z, 2.);
                            float dist = sqrt(dist_2);
                            float radius = max(max(roi_grid_length_x, roi_grid_length_y), roi_grid_length_z) / 2.;
                            float weight = 2.71828 / expf(dist / radius);
            //                float weight = 1.;

                            int pool_count = temp_count[voxel_coor];
                            if (pool_count < pooling_size) {
                                output_idx[voxel_coor * pooling_size + pool_count] = point_id;
                                output_weight[voxel_coor * pooling_size + pool_count] = weight;
                                temp_count[voxel_coor] += 1;
                            } else {
                                break;
                            }
                        }
                    }
                }
            }
        }
//        printf("Voxel Pooling = %d\n", temp_count[voxel_coor]);
    }
}

__global__ void roi_pooling_fill_gpu_kernel(int roi_num, int voxel_num, int channels, int pooling_size,
                                            const float* input_features,
                                            int* temp_count,
                                            float* output_features,
                                            int* output_idx,
                                            float* output_weight) {
    int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (thread_id < roi_num * voxel_num) {
        int pool_count = min(temp_count[thread_id], pooling_size);
        if (pool_count > 0) {
            float weight_sum = 0;
//            int pool_id;
            for (int p=0; p<pool_count; p++) {
//                pool_id = thread_id * pooling_size + p;
//                weight_sum += output_weight[pool_id];
                weight_sum += 1;
            }
            for (int p=0; p<pool_count; p++) {
                int pool_id = thread_id * pooling_size + p;
                int input_id = output_idx[pool_id];
                float weight = output_weight[pool_id] / weight_sum;
//                float weight = output_weight[pool_id];
//                printf("%d, %d, %f\n", input_id, pool_count, weight);
                output_weight[pool_id] = weight;
//                if (thread_id == 0)
//                    printf("Forward: %f\n", weight);
//                float temp_max = -1e6;
                for (int c=0; c < channels; c++) {
                    output_features[thread_id * channels + c] += input_features[input_id * channels + c] * weight;
//                    float features = input_features[input_id * channels + c] * weight;
//                    if (features > temp_max) {
//                        output_features[thread_id * channels + c] = features;
//                        temp_max = features;
//                    }
////                    printf("%d, %d\n", thread_id, input_id);
                }
            }
        }
    }
}


void roi_pooling_gpu_launcher(int batch_size, int input_point_num, int channels,
                              int roi_num, int voxel_size, int pooling_size, float padding_value,
                              float grid_buffer_resolution, int grid_buffer_size,
                              int grid_buffer_dim_w, int grid_buffer_dim_l, int grid_buffer_dim_h,
                              float offset_w, float offset_l, float offset_h,
                              const float* input_coors,
                              const float* input_features,
                              const float* roi_attrs,
                              const int* input_num_list,
                              const int* roi_num_list,
                              int* input_num_list_host,
                              int* input_accu_list,
                              int* roi_accu_list,
                              int* temp_count,
                              int* temp_grid_buffer,
                              int* temp_grid_buffer_count,
                              float* output_features,
                              int* output_idx,
                              float* output_weight) {

    if (batch_size * channels <= 0 || input_point_num <= 0) {
        printf("RoiPoolingFastOp ERROR: Invalid CUDA input dimensions.\n");
        return;
    }
    if (roi_num <= 0) {
        printf("RoiPoolingFastOp WARNING: No RoIs were found for the current batch.\n");
        return;
    }
//    printf("RoI Num: %d\n", roi_num);
    const int voxel_num = voxel_size * voxel_size * voxel_size;


    int blockSize;      // The launch configurator returned block size
    int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch
    int gridSize;       // The actual grid size needed, based on input size

    hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, roi_num * voxel_num);
    gridSize = (roi_num * voxel_num + blockSize - 1) / blockSize;
    output_init_gpu_kernel<<<gridSize,blockSize>>>(roi_num, voxel_num, channels, pooling_size, padding_value,
                                                   output_features,
                                                   output_idx);

    hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, grid_buffer_init_gpu_kernel, 0, input_point_num);
    gridSize = (input_point_num + blockSize - 1) / blockSize;
    grid_buffer_init_gpu_kernel<<<gridSize,blockSize>>>(batch_size, input_point_num,
                                                        grid_buffer_resolution, grid_buffer_size,
                                                        grid_buffer_dim_w, grid_buffer_dim_l, grid_buffer_dim_h,
                                                        input_coors,
                                                        input_accu_list,
                                                        temp_grid_buffer,
                                                        temp_grid_buffer_count);

    hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_pooling_register_gpu_kernel, 0, roi_num * voxel_num);
    gridSize = (roi_num * voxel_num + blockSize - 1) / blockSize;
    roi_pooling_register_gpu_kernel<<<gridSize,blockSize>>>(batch_size, roi_num,
                                                            voxel_size, pooling_size,
                                                            grid_buffer_resolution, grid_buffer_size,
                                                            offset_w, offset_l, offset_h,
                                                            grid_buffer_dim_w, grid_buffer_dim_l, grid_buffer_dim_h,
                                                            input_coors,
                                                            roi_attrs,
                                                            input_num_list,
                                                            input_accu_list,
                                                            roi_accu_list,
                                                            temp_count,
                                                            temp_grid_buffer,
                                                            temp_grid_buffer_count,
                                                            output_idx,
                                                            output_weight);

    hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_pooling_fill_gpu_kernel, 0, roi_num * voxel_num);
    gridSize = (roi_num * voxel_num + blockSize - 1) / blockSize;
    roi_pooling_fill_gpu_kernel<<<gridSize,blockSize>>>(roi_num, voxel_num, channels, pooling_size,
                                                        input_features,
                                                        temp_count,
                                                        output_features,
                                                        output_idx,
                                                        output_weight);
}

	.text
	.file	"la_roi_pooling_fast.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z37__device_stub__output_init_gpu_kerneliiiifPfPi # -- Begin function _Z37__device_stub__output_init_gpu_kerneliiiifPfPi
	.type	_Z37__device_stub__output_init_gpu_kerneliiiifPfPi,@function
_Z37__device_stub__output_init_gpu_kerneliiiifPfPi: # @_Z37__device_stub__output_init_gpu_kerneliiiifPfPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	56(%rsp), %r10
	movq	%r8, (%r10)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22output_init_gpu_kerneliiiifPfPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__output_init_gpu_kerneliiiifPfPi, .Lfunc_end0-_Z37__device_stub__output_init_gpu_kerneliiiifPfPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_ # -- Begin function _Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.type	_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_,@function
_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_: # @_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	16(%rsp), %r10
	movl	%edx, (%r10)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, .Lfunc_end1-_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf # -- Begin function _Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.type	_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf,@function
_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf: # @_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	44(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	36(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	28(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	24(%rsp), %r10
	movl	%r8d, (%r10)
	leaq	20(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	16(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	12(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	8(%rsp), %r15
	movl	%r9d, (%r15)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	movq	%r15, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, .Lfunc_end2-_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_ # -- Begin function _Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.type	_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_,@function
_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_: # @_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, .Lfunc_end3-_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_ # -- Begin function _Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_
	.type	_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_,@function
_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_: # @_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%esi, %esi
	jle	.LBB4_2
# %bb.1:
	movl	%edi, %ebx
	movl	%edx, %eax
	imull	%edi, %eax
	testl	%eax, %eax
	jle	.LBB4_2
# %bb.4:
	testl	%ecx, %ecx
	jle	.LBB4_5
# %bb.6:
	movl	%r9d, %r12d
	movl	%esi, %r14d
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movss	%xmm1, 32(%rsp)                 # 4-byte Spill
	movss	%xmm2, 52(%rsp)                 # 4-byte Spill
	movss	%xmm3, 56(%rsp)                 # 4-byte Spill
	movss	%xmm4, 60(%rsp)                 # 4-byte Spill
	movl	%edx, 36(%rsp)                  # 4-byte Spill
	movq	360(%rsp), %rax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	352(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	344(%rsp), %rax
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movq	336(%rsp), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	328(%rsp), %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	320(%rsp), %rax
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movq	312(%rsp), %rax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movq	304(%rsp), %rax
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movq	280(%rsp), %rax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movq	272(%rsp), %rax
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movq	264(%rsp), %rax
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movq	256(%rsp), %rax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movl	248(%rsp), %eax
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movl	%r8d, %r15d
	imull	%r8d, %r15d
	movl	%r8d, 48(%rsp)                  # 4-byte Spill
	imull	%r8d, %r15d
	movl	%r15d, %r13d
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	imull	%ecx, %r13d
	movl	240(%rsp), %eax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	232(%rsp), %eax
	movl	%eax, 28(%rsp)                  # 4-byte Spill
	movl	224(%rsp), %eax
	movl	%eax, 24(%rsp)                  # 4-byte Spill
	leaq	16(%rsp), %rdi
	leaq	20(%rsp), %rbp
	movl	$_Z22output_init_gpu_kerneliiiifPfPi, %edx
	movq	%rbp, %rsi
	xorl	%ecx, %ecx
	movl	%r13d, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movl	(%rbp), %ecx
	leal	(%rcx,%r13), %eax
	decl	%eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	btsq	$32, %rax
	btsq	$32, %rcx
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movl	12(%rsp), %edi                  # 4-byte Reload
	movl	%r15d, %esi
	movl	36(%rsp), %edx                  # 4-byte Reload
	movl	%r12d, %ecx
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	128(%rsp), %r8                  # 8-byte Reload
	movq	40(%rsp), %r9                   # 8-byte Reload
	callq	_Z37__device_stub__output_init_gpu_kerneliiiifPfPi
.LBB4_8:
	movl	%r12d, 8(%rsp)                  # 4-byte Spill
	leal	-1(%r13), %ebp
	leaq	16(%rsp), %rdi
	leaq	20(%rsp), %r12
	movl	$_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, %edx
	movq	%r12, %rsi
	xorl	%ecx, %ecx
	movl	%r14d, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movl	(%r12), %ecx
	leal	(%r14,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	movabsq	$4294967296, %r12               # imm = 0x100000000
	orq	%r12, %rax
	orq	%r12, %rcx
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.9:
	movl	%ebx, %edi
	movl	%r14d, %esi
	movss	32(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	24(%rsp), %edx                  # 4-byte Reload
	movl	28(%rsp), %ecx                  # 4-byte Reload
	movq	64(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movq	104(%rsp), %r9                  # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB4_10:
	leaq	16(%rsp), %rdi
	leaq	20(%rsp), %r14
	movl	$_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, %edx
	movq	%r14, %rsi
	xorl	%ecx, %ecx
	movl	%r13d, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movl	(%r14), %ecx
	leal	(%rcx,%rbp), %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	orq	%r12, %rax
	orq	%r12, %rcx
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movl	8(%rsp), %r14d                  # 4-byte Reload
	jne	.LBB4_12
# %bb.11:
	movl	%ebx, %edi
	movl	12(%rsp), %esi                  # 4-byte Reload
	movl	48(%rsp), %edx                  # 4-byte Reload
	movl	%r14d, %ecx
	movss	32(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	24(%rsp), %r8d                  # 4-byte Reload
	movss	52(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	56(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	60(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movl	28(%rsp), %r9d                  # 4-byte Reload
	pushq	120(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	144(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	200(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
.LBB4_12:
	leaq	16(%rsp), %rdi
	leaq	20(%rsp), %rbx
	movl	$_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, %edx
	movq	%rbx, %rsi
	xorl	%ecx, %ecx
	movl	%r13d, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movl	(%rbx), %ecx
	addl	%ecx, %ebp
	movl	%ebp, %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	orq	%r12, %rax
	orq	%r12, %rcx
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.13:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	20(%rsp), %edi                  # 4-byte Reload
	movl	%r15d, %esi
	movl	44(%rsp), %edx                  # 4-byte Reload
	movl	%r14d, %ecx
	movq	168(%rsp), %r8                  # 8-byte Reload
	movq	120(%rsp), %r9                  # 8-byte Reload
	pushq	128(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB4_14:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 224
	movl	$.Lstr.1, %edi
	jmp	.LBB4_3
.LBB4_5:
	movl	$.Lstr, %edi
.LBB4_3:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end4:
	.size	_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_, .Lfunc_end4-_Z24roi_pooling_gpu_launcheriiiiiiffiiiifffPKfS0_S0_PKiS2_PiS3_S3_S3_S3_S3_PfS3_S4_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22output_init_gpu_kerneliiiifPfPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22output_init_gpu_kerneliiiifPfPi,@object # @_Z22output_init_gpu_kerneliiiifPfPi
	.section	.rodata,"a",@progbits
	.globl	_Z22output_init_gpu_kerneliiiifPfPi
	.p2align	3, 0x0
_Z22output_init_gpu_kerneliiiifPfPi:
	.quad	_Z37__device_stub__output_init_gpu_kerneliiiifPfPi
	.size	_Z22output_init_gpu_kerneliiiifPfPi, 8

	.type	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_,@object # @_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.globl	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.p2align	3, 0x0
_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_:
	.quad	_Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.size	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, 8

	.type	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf,@object # @_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.globl	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.p2align	3, 0x0
_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf:
	.quad	_Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.size	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, 8

	.type	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_,@object # @_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.globl	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.p2align	3, 0x0
_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_:
	.quad	_Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.size	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z22output_init_gpu_kerneliiiifPfPi"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_"
	.size	.L__unnamed_2, 50

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf"
	.size	.L__unnamed_3, 76

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_"
	.size	.L__unnamed_4, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"RoiPoolingFastOp WARNING: No RoIs were found for the current batch."
	.size	.Lstr, 68

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"RoiPoolingFastOp ERROR: Invalid CUDA input dimensions."
	.size	.Lstr.1, 55

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__output_init_gpu_kerneliiiifPfPi
	.addrsig_sym _Z42__device_stub__grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.addrsig_sym _Z46__device_stub__roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.addrsig_sym _Z42__device_stub__roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22output_init_gpu_kerneliiiifPfPi
	.addrsig_sym _Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.addrsig_sym _Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.addrsig_sym _Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22output_init_gpu_kerneliiiifPfPi ; -- Begin function _Z22output_init_gpu_kerneliiiifPfPi
	.globl	_Z22output_init_gpu_kerneliiiifPfPi
	.p2align	8
	.type	_Z22output_init_gpu_kerneliiiifPfPi,@function
_Z22output_init_gpu_kerneliiiifPfPi:    ; @_Z22output_init_gpu_kerneliiiifPfPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.preheader23
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x18
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s6
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_store_b32 v[2:3], v0, off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %.preheader
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB0_7
; %bb.5:                                ; %.lr.ph26
	v_mul_lo_u32 v0, v1, s7
	v_mov_b32_e32 v2, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	global_store_b32 v[0:1], v2, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s7, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s7, 0
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22output_init_gpu_kerneliiiifPfPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22output_init_gpu_kerneliiiifPfPi, .Lfunc_end0-_Z22output_init_gpu_kerneliiiifPfPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_ ; -- Begin function _Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.globl	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
	.p2align	8
	.type	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_,@function
_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_: ; @_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s17, v3
	s_cbranch_execz .LBB1_11
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x20
	v_lshl_add_u32 v0, v3, 1, v3
	s_load_b128 s[12:15], s[0:1], 0x10
	v_mov_b32_e32 v4, 0
	s_add_i32 s2, s16, -1
	s_cmp_lt_i32 s16, 2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b96 v[0:2], v[0:1], off
	s_cbranch_scc1 .LBB1_9
; %bb.2:                                ; %.lr.ph.i.preheader
	s_add_u32 s0, s6, 4
	s_addc_u32 s1, s7, 0
	s_mov_b32 s3, 0
	s_mov_b32 s4, 0
.LBB1_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_add_u32 s6, s0, -4
	s_addc_u32 s7, s1, -1
	s_load_b32 s6, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s5, s6, v3
	v_cmp_le_i32_e32 vcc_lo, s6, v3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	s_load_b32 s7, s[0:1], 0x0
	s_and_not1_b32 s5, s5, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, s7, v3
	s_and_b32 s7, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s5, s7
.LBB1_5:                                ; %Flow83
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v4, s4
	s_mov_b32 s7, -1
	s_and_saveexec_b32 s6, s5
; %bb.6:                                ;   in Loop: Header=BB1_3 Depth=1
	s_add_i32 s4, s4, 1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s2, s4
	v_mov_b32_e32 v4, s2
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s7, s5, exec_lo
; %bb.7:                                ; %Flow84
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s7
	s_or_b32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_3
; %bb.8:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_9:                                ; %_Z12get_batch_idPiii.exit
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v5, null, s18, s18, v0
	v_div_scale_f32 v10, null, s18, s18, v2
	v_div_scale_f32 v7, null, s18, s18, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v6, v5
	v_div_scale_f32 v11, vcc_lo, v0, s18, v0
	v_rcp_f32_e32 v8, v7
	v_div_scale_f32 v14, s0, v1, s18, v1
	v_div_scale_f32 v17, s1, v2, s18, v2
	v_min_i32_e32 v4, s2, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v5, v6, 1.0
	v_fma_f32 v12, -v7, v8, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v9, v6
	v_rcp_f32_e32 v9, v10
	v_fmac_f32_e32 v8, v12, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v10, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v15, v9
	v_mul_f32_e32 v13, v11, v6
	v_fma_f32 v12, -v5, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, v14, v8 :: v_dual_fmac_f32 v13, v12, v6
	v_fma_f32 v12, -v7, v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v5, v13, v11
	v_dual_mul_f32 v11, v17, v9 :: v_dual_fmac_f32 v16, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v5, v6, v13
	v_fma_f32 v6, -v10, v11, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v7, -v7, v16, v14
	s_mov_b32 vcc_lo, s0
	s_add_i32 s0, s12, -1
	v_div_fixup_f32 v0, v5, s18, v0
	v_fmac_f32_e32 v11, v6, v9
	v_div_fmas_f32 v5, v7, v8, v16
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v0, v0
	v_fma_f32 v6, -v10, v11, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v1, v5, s18, v1
	v_cvt_i32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v5, v6, v9, v11
	v_trunc_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_minmax_i32 v0, v0, s0, 0
	v_div_fixup_f32 v5, v5, s18, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v6, v1
	s_add_i32 s0, s13, -1
	v_mad_u64_u32 v[1:2], null, v4, s12, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v2, v5
	v_minmax_i32 v0, v6, s0, 0
	s_add_i32 s0, s14, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v2, v2
	v_mad_u64_u32 v[4:5], null, v1, s13, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v2, v2, s0, 0
	v_mad_u64_u32 v[0:1], null, v4, s14, v[2:3]
	v_mov_b32_e32 v4, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	global_atomic_add_u32 v1, v[1:2], v4, off glc
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s19, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_mad_u64_u32 v[4:5], null, v0, s19, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB1_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_, .Lfunc_end1-_Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 816
; NumSgprs: 22
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf ; -- Begin function _Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.globl	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
	.p2align	8
	.type	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf,@function
_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf: ; @_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8c
	s_load_b256 s[16:23], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s6, s18, s18
	v_mad_u64_u32 v[7:8], null, s15, s2, v[0:1]
	s_mul_i32 s4, s6, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s4, s17
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v7
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_46
; %bb.1:
	s_ashr_i32 s2, s4, 31
	v_ashrrev_i32_e32 v2, 31, v7
	s_add_i32 s3, s4, s2
	s_clause 0x1
	s_load_b128 s[24:27], s[0:1], 0x20
	s_load_b256 s[8:15], s[0:1], 0x50
	s_xor_b32 s3, s3, s2
	s_load_b128 s[28:31], s[0:1], 0x70
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s5, 0, s3
	s_mov_b32 s7, 0
	v_add_nc_u32_e32 v3, v7, v2
	v_mov_b32_e32 v13, 0
	v_rcp_iflag_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v2
	v_xor_b32_e32 v2, s2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s5, v0
	s_add_i32 s5, s16, -1
	s_cmp_lt_i32 s16, 2
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v0, s3
	v_sub_nc_u32_e32 v1, v3, v1
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v0, v2
	s_cbranch_scc1 .LBB2_9
; %bb.2:                                ; %.lr.ph.i.preheader
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s8, 4
	s_addc_u32 s3, s9, 0
	s_mov_b32 s8, 0
.LBB2_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_add_u32 s16, s2, -4
	s_addc_u32 s17, s3, -1
	s_load_b32 s16, s[16:17], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s9, s16, v12
	v_cmp_le_i32_e32 vcc_lo, s16, v12
	s_and_saveexec_b32 s16, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_3 Depth=1
	s_load_b32 s17, s[2:3], 0x0
	s_and_not1_b32 s9, s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, s17, v12
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s9, s9, s17
.LBB2_5:                                ; %Flow390
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_mov_b32_e32 v13, s8
	s_mov_b32 s17, -1
	s_and_saveexec_b32 s16, s9
; %bb.6:                                ;   in Loop: Header=BB2_3 Depth=1
	s_add_i32 s8, s8, 1
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s5, s8
	v_mov_b32_e32 v13, s5
	s_cselect_b32 s9, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s17, s9, exec_lo
; %bb.7:                                ; %Flow391
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, exec_lo, s17
	s_or_b32 s7, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB2_3
; %bb.8:                                ; %Flow392
	s_or_b32 exec_lo, exec_lo, s7
.LBB2_9:                                ; %_Z12get_batch_idPiii.exit
	s_load_b128 s[36:39], s[0:1], 0x30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v12, 7
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr18
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s38, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s39, v1, vcc_lo
	s_clause 0x1
	global_load_b96 v[4:6], v[0:1], off offset:16
	global_load_b128 v[0:3], v[0:1], off
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v15, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v14, 23, v15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB2_11
; %bb.10:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v11, v15, s0, 0x800000
	v_add_nc_u32_e32 v21, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v11, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0x3c439041, v11, v[9:10]
	v_dual_mov_b32 v9, v17 :: v_dual_add_nc_u32 v22, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v22
	v_mad_u64_u32 v[17:18], null, 0xdb629599, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, 0, 0xffffffe0, s0
	v_dual_cndmask_b32 v8, v17, v8 :: v_dual_add_nc_u32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v18
	v_cmp_lt_u32_e64 s1, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0xf534ddc0, v11, v[9:10]
	v_dual_mov_b32 v9, v19 :: v_dual_cndmask_b32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xfc2757d1, v11, v[9:10]
	v_cndmask_b32_e64 v8, v16, v8, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v20
	v_mad_u64_u32 v[20:21], null, 0x4e441529, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v21
	v_mad_u64_u32 v[21:22], null, 0xa2f9836e, v11, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v10, v20, v18 :: v_dual_add_nc_u32 v9, v9, v23
	v_dual_cndmask_b32 v11, v21, v19 :: v_dual_cndmask_b32 v20, v22, v20
	v_cndmask_b32_e32 v19, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v18, v11, v10, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v20, v11, s0
	v_cndmask_b32_e64 v10, v10, v19, s0
	v_sub_nc_u32_e32 v20, 32, v9
	v_cndmask_b32_e64 v19, v19, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v18, s1
	v_cndmask_b32_e64 v18, v18, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v19, s1
	v_cndmask_b32_e64 v8, v19, v8, s1
	v_alignbit_b32 v21, v11, v18, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v18, v10, v20
	v_alignbit_b32 v19, v10, v8, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v21, v11, vcc_lo
	v_cndmask_b32_e32 v11, v17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v19, v10, vcc_lo
	v_bfe_u32 v16, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v9, v11, 30
	v_alignbit_b32 v11, v11, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 0, v16
	v_xor_b32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v11, v18
	v_xor_b32_e32 v8, v8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v19, v17
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v19
	v_lshlrev_b32_e32 v21, 23, v19
	v_alignbit_b32 v17, v17, v10, v11
	v_alignbit_b32 v8, v10, v8, v11
	v_lshrrev_b32_e32 v11, 29, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v17, v8, 9
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v17, 9, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v18, v10
	v_or_b32_e32 v20, 0.5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v18, 32, v18
	v_sub_nc_u32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v22, 31, v18
	v_alignbit_b32 v8, v10, v8, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v17, v20
	v_add_lshl_u32 v17, v18, v19, 23
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v8, v8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, 0x3fc90fda, v10, -v18
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v10, v10, 0x33a22168, v17
	v_or_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v8
	v_lshrrev_b32_e32 v8, 30, v9
	v_dual_add_f32 v18, v18, v10 :: v_dual_add_nc_u32 v19, v16, v8
.LBB2_11:                               ; %Flow389
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v16, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.12:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v8, v16
	v_fma_f32 v9, 0xbfc90fda, v8, |v6|
	v_cvt_i32_f32_e32 v19, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	v_fmamk_f32 v18, v8, 0xa7c234c4, v9
; %bb.13:                               ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr21
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB2_15
; %bb.14:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v11, v15, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v11, 0
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v21
	v_mad_u64_u32 v[21:22], null, 0xdb629599, v11, v[9:10]
	v_add_nc_u32_e32 v17, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v17
	v_mov_b32_e32 v9, v22
	v_cndmask_b32_e64 v25, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[22:23], null, 0xf534ddc0, v11, v[9:10]
	v_cndmask_b32_e32 v8, v21, v8, vcc_lo
	v_add_nc_u32_e32 v17, v25, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v23
	v_cmp_lt_u32_e64 s0, 31, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[23:24], null, 0xfc2757d1, v11, v[9:10]
	v_cndmask_b32_e64 v26, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v17, v26, v17
	v_mov_b32_e32 v9, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v17
	v_mad_u64_u32 v[24:25], null, 0x4e441529, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v25
	v_mad_u64_u32 v[25:26], null, 0xa2f9836e, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v10, v24, v22 :: v_dual_add_nc_u32 v9, v9, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v11, v25, v23 :: v_dual_cndmask_b32 v24, v26, v24
	v_cndmask_b32_e32 v23, v23, v21, vcc_lo
	v_cndmask_b32_e32 v17, v22, v20, vcc_lo
	v_sub_nc_u32_e32 v22, 32, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v11, v10, s0
	v_cndmask_b32_e64 v11, v24, v11, s0
	v_cndmask_b32_e64 v10, v10, v23, s0
	v_cndmask_b32_e64 v23, v23, v17, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v8, v17, v8, s0
	v_cndmask_b32_e64 v11, v11, v20, s1
	v_cndmask_b32_e64 v20, v20, v10, s1
	v_cndmask_b32_e64 v10, v10, v23, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v23, v8, s1
	v_alignbit_b32 v24, v11, v20, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v20, v10, v22
	v_alignbit_b32 v22, v10, v8, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v24, v11, vcc_lo
	v_dual_cndmask_b32 v11, v21, v20 :: v_dual_cndmask_b32 v10, v22, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_u32 v17, v9, 29, 1
	v_alignbit_b32 v20, v9, v11, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v11, v11, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	v_sub_nc_u32_e32 v21, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v20, v21
	v_xor_b32_e32 v10, v11, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v21
	v_clz_i32_u32_e32 v22, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v22, 32, v22
	v_sub_nc_u32_e32 v11, 31, v22
	v_lshlrev_b32_e32 v24, 23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v20, v10, v11
	v_alignbit_b32 v8, v10, v8, v11
	v_lshrrev_b32_e32 v11, 29, v9
	v_alignbit_b32 v10, v20, v8, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v20, 9, v20
	v_clz_i32_u32_e32 v21, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v23, 0.5, v11
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v23, v23, v24
	v_sub_nc_u32_e32 v25, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v10, v8, v25
	v_or_b32_e32 v10, v20, v23
	v_add_lshl_u32 v20, v21, v22, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v8, 9, v8
	v_mul_f32_e32 v21, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v20
	v_fma_f32 v20, 0x3fc90fda, v10, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 0x33000000, v8
	v_fmamk_f32 v10, v10, 0x33a22168, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v8, v8, v11
	v_fmac_f32_e32 v10, 0x3fc90fda, v8
	v_lshrrev_b32_e32 v8, 30, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v21, v10
	v_add_nc_u32_e32 v24, v17, v8
.LBB2_15:                               ; %Flow388
	s_and_not1_saveexec_b32 s0, s3
; %bb.16:
	v_rndne_f32_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v8, |v6|
	v_cvt_i32_f32_e32 v24, v8
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v21, v8, 0xa7c234c4, v9
; %bb.17:                               ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr17
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB2_19
; %bb.18:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v11, v15, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v11, 0
	v_mad_u64_u32 v[22:23], null, 0x3c439041, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v23
	v_mad_u64_u32 v[25:26], null, 0xdb629599, v11, v[9:10]
	v_add_nc_u32_e32 v17, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v17
	v_mov_b32_e32 v9, v26
	v_cndmask_b32_e64 v20, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[26:27], null, 0xf534ddc0, v11, v[9:10]
	v_dual_cndmask_b32 v8, v25, v8 :: v_dual_add_nc_u32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v27
	v_cmp_lt_u32_e64 s0, 31, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, 0xfc2757d1, v11, v[9:10]
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v17, v20, v17
	v_mov_b32_e32 v9, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v27, v25, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, 0x4e441529, v11, v[9:10]
	v_mov_b32_e32 v9, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[29:30], null, 0xa2f9836e, v11, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v10, v28, v26 :: v_dual_add_nc_u32 v9, v9, v17
	v_dual_cndmask_b32 v11, v29, v27 :: v_dual_cndmask_b32 v20, v30, v28
	v_cndmask_b32_e32 v17, v26, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v22, v11, v10, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v20, v11, s0
	v_cndmask_b32_e64 v10, v10, v23, s0
	v_sub_nc_u32_e32 v20, 32, v9
	v_cndmask_b32_e64 v23, v23, v17, s0
	v_cndmask_b32_e64 v8, v17, v8, s0
	v_cndmask_b32_e64 v11, v11, v22, s1
	v_cndmask_b32_e64 v22, v22, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v23, s1
	v_cndmask_b32_e64 v8, v23, v8, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v26, v11, v22, v20
	v_alignbit_b32 v25, v22, v10, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v10, v8, v20
	v_cndmask_b32_e32 v9, v26, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v25, v22, vcc_lo
	v_cndmask_b32_e32 v10, v20, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v22, v9, 29, 1
	v_alignbit_b32 v17, v9, v11, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v11, v11, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	v_sub_nc_u32_e32 v23, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v17, v17, v23
	v_xor_b32_e32 v10, v11, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v23
	v_clz_i32_u32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v11, 31, v20
	v_lshlrev_b32_e32 v26, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v17, v17, v10, v11
	v_alignbit_b32 v8, v10, v8, v11
	v_lshrrev_b32_e32 v11, 29, v9
	v_alignbit_b32 v10, v17, v8, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v17, 9, v17
	v_clz_i32_u32_e32 v23, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v25, 0.5, v11
	v_min_u32_e32 v23, 32, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v25, v25, v26
	v_sub_nc_u32_e32 v27, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v10, v8, v27
	v_or_b32_e32 v10, v17, v25
	v_add_lshl_u32 v17, v23, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v8, 9, v8
	v_mul_f32_e32 v20, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v17
	v_fma_f32 v17, 0x3fc90fda, v10, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 0x33000000, v8
	v_fmamk_f32 v10, v10, 0x33a22168, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v8, v8, v11
	v_fmac_f32_e32 v10, 0x3fc90fda, v8
	v_lshrrev_b32_e32 v8, 30, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v17, v20, v10 :: v_dual_add_nc_u32 v28, v22, v8
.LBB2_19:                               ; %Flow387
	s_and_not1_saveexec_b32 s0, s3
; %bb.20:
	v_rndne_f32_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v8, |v6|
	v_cvt_i32_f32_e32 v28, v8
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v17, v8, 0xa7c234c4, v9
; %bb.21:                               ; %_ZL4sinff.exit219
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr20
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB2_23
; %bb.22:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v11, v15, s0, 0x800000
	v_add_nc_u32_e32 v20, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v11, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, 0x3c439041, v11, v[9:10]
	v_mov_b32_e32 v9, v23
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[25:26], null, 0xdb629599, v11, v[9:10]
	v_add_nc_u32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 31, v20
	v_dual_mov_b32 v9, v26 :: v_dual_cndmask_b32 v8, v25, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, 0xffffffe0, s0
	v_mad_u64_u32 v[26:27], null, 0xf534ddc0, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v27
	v_mad_u64_u32 v[29:30], null, 0xfc2757d1, v11, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v30
	v_cndmask_b32_e32 v27, v29, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[30:31], null, 0x4e441529, v11, v[9:10]
	v_mov_b32_e32 v9, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[31:32], null, 0xa2f9836e, v11, v[9:10]
	v_add_nc_u32_e32 v20, v23, v20
	v_cndmask_b32_e32 v10, v30, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v32, v30, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v20
	v_cndmask_b32_e32 v11, v31, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v20, v26, v22 :: v_dual_add_nc_u32 v9, v9, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v11, v10, s0
	v_cndmask_b32_e64 v11, v23, v11, s0
	v_cndmask_b32_e64 v10, v10, v27, s0
	v_sub_nc_u32_e32 v23, 32, v9
	v_cndmask_b32_e64 v26, v27, v20, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v11, v11, v22, s1
	v_cndmask_b32_e64 v22, v22, v10, s1
	v_cndmask_b32_e64 v8, v20, v8, s0
	v_cndmask_b32_e64 v10, v10, v26, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v11, v22, v23
	v_cndmask_b32_e64 v8, v26, v8, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v25, v22, v10, v23
	v_cndmask_b32_e32 v9, v27, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v10, v8, v23
	v_cndmask_b32_e32 v11, v25, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v22, v9, 29, 1
	v_cndmask_b32_e32 v10, v23, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v9, v11, 30
	v_sub_nc_u32_e32 v25, 0, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v11, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	v_xor_b32_e32 v20, v20, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v11, v25
	v_xor_b32_e32 v8, v8, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v23, v20
	v_min_u32_e32 v23, 32, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v23
	v_lshlrev_b32_e32 v27, 23, v23
	v_alignbit_b32 v20, v20, v10, v11
	v_alignbit_b32 v8, v10, v8, v11
	v_lshrrev_b32_e32 v11, 29, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v20, v8, 9
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v25, v10
	v_or_b32_e32 v26, 0.5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v25, 32, v25
	v_sub_nc_u32_e32 v26, v26, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v29, 31, v25
	v_alignbit_b32 v8, v10, v8, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v20, v26
	v_add_lshl_u32 v20, v25, v23, 23
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v8, v8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0x3fc90fda, v10, -v23
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v10, v10, 0x33a22168, v20
	v_or_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v8
	v_lshrrev_b32_e32 v8, 30, v9
	v_dual_add_f32 v20, v23, v10 :: v_dual_add_nc_u32 v31, v22, v8
.LBB2_23:                               ; %Flow386
	s_and_not1_saveexec_b32 s0, s2
; %bb.24:
	v_rndne_f32_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v8, |v6|
	v_cvt_i32_f32_e32 v31, v8
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v20, v8, 0xa7c234c4, v9
; %bb.25:                               ; %_ZL4cosff.exit225
	s_or_b32 exec_lo, exec_lo, s0
	s_ashr_i32 s0, s6, 31
	v_mul_lo_u32 v9, v12, s4
	s_add_i32 s1, s6, s0
	v_cvt_f32_i32_e32 v30, s18
	s_xor_b32 s1, s1, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, s22, v3
	v_cvt_f32_u32_e32 v8, s1
	s_sub_i32 s2, 0, s1
	v_div_scale_f32 v29, null, v30, v30, v1
	v_sub_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v8, v8
	v_rcp_f32_e32 v35, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v27, 31, v7
	v_add_nc_u32_e32 v10, v7, v27
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x4f7ffffe, v8
	v_xor_b32_e32 v22, s0, v27
	v_fma_f32 v26, -v29, v35, 1.0
	v_xor_b32_e32 v32, v10, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v8, v8
	v_fmac_f32_e32 v35, v26, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v9, s2, v8
	s_ashr_i32 s2, s18, 31
	s_add_i32 s3, s18, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_xor_b32 s9, s3, s2
	s_mov_b32 s3, 0xb94c1982
	s_sub_i32 s0, 0, s9
	v_mul_hi_u32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_hi_u32 v8, v32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v8, s1
	v_add_nc_u32_e32 v10, 1, v8
	v_sub_nc_u32_e32 v9, v32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v11, s1, v9
	v_cmp_le_u32_e32 vcc_lo, s1, v9
	v_cndmask_b32_e32 v9, v9, v11, vcc_lo
	v_cvt_f32_u32_e32 v11, s9
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s1, v9
	v_rcp_iflag_f32_e32 v9, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, 0x4f7ffffe, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v9, v9
	v_mul_lo_u32 v11, s0, v9
	s_lshr_b32 s0, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s18, s0
	s_and_b32 s1, s0, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s1, s1, s18
	v_mul_hi_u32 v11, v9, v11
	s_add_i32 s1, s1, 1
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v33, v9, v11
	v_add_nc_u32_e32 v10, 1, v8
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v22
	v_sub_nc_u32_e32 v8, v8, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v10, s6, v8
	s_mov_b32 s6, 0x37d75334
	v_sub_nc_u32_e32 v10, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v22, 31, v10
	v_add_nc_u32_e32 v10, v10, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v10, v22
	v_xor_b32_e32 v22, s2, v22
	s_ashr_i32 s2, s0, 1
	v_mul_hi_u32 v10, v9, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v10, s9
	v_sub_nc_u32_e32 v9, v9, v11
	v_add_nc_u32_e32 v11, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v23, s9, v9
	v_cmp_le_u32_e32 vcc_lo, s9, v9
	v_cndmask_b32_e32 v9, v9, v23, vcc_lo
	v_div_scale_f32 v23, null, v30, v30, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v34, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v23, v34, 1.0
	v_fmac_f32_e32 v34, v25, v34
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v9
	v_subrev_nc_u32_e32 v25, s2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, 1, v10
	v_cvt_f64_i32_e32 v[25:26], v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v9, v10, v11, vcc_lo
	v_cvt_f64_i32_e32 v[10:11], s1
	v_div_scale_f32 v36, vcc_lo, v0, v30, v0
	v_cmp_class_f32_e64 s1, v6, 0x1f8
	v_xor_b32_e32 v9, v9, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v37, v36, v34
	v_sub_nc_u32_e32 v9, v9, v22
	v_div_scale_f32 v22, s0, v1, v30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v39, -v23, v37, v36
	v_subrev_nc_u32_e32 v9, s2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v38, v22, v35 :: v_dual_fmac_f32 v37, v39, v34
	v_mul_f32_e32 v39, v21, v21
	v_cvt_f64_i32_e32 v[8:9], v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v40, -v29, v38, v22
	v_fma_f32 v23, -v23, v37, v36
	v_mul_f32_e32 v36, v18, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v38, v40, v35
	v_div_fmas_f32 v23, v23, v34, v37
	s_mov_b32 vcc_lo, s0
	v_and_b32_e32 v37, 1, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v22, -v29, v38, v22
	s_add_i32 s0, s25, -1
	v_div_fixup_f32 v23, v23, v30, v0
	v_div_fmas_f32 v22, v22, v35, v38
	v_cmp_eq_u32_e32 vcc_lo, 0, v37
	v_fma_f64 v[25:26], v[10:11], 0.5, v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v22, v22, v30, v1
	v_cvt_f64_f32_e32 v[0:1], v22
	v_fma_f64 v[34:35], v[10:11], 0.5, v[8:9]
	v_cvt_f64_f32_e32 v[8:9], v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[34:35], v[34:35], v[0:1]
	v_mul_f64 v[25:26], v[25:26], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v29, v[34:35]
	v_fmaak_f32 v35, s6, v39, 0xbab64f3b
	v_dual_fmaak_f32 v19, s3, v36, 0x3c0881c4 :: v_dual_lshlrev_b32 v38, 30, v19
	v_fmaak_f32 v42, v36, v19, 0xbe2aaa9d
	v_fmaak_f32 v34, s3, v39, 0x3c0881c4
	v_cvt_f32_f64_e32 v19, v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v26, v39, v35, 0x3d2aabf7 :: v_dual_mul_f32 v35, v36, v42
	v_fmaak_f32 v41, s6, v36, 0xbab64f3b
	v_dual_fmaak_f32 v25, v39, v34, 0xbe2aaa9d :: v_dual_fmac_f32 v18, v18, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v41, v36, v41, 0x3d2aabf7 :: v_dual_and_b32 v40, 1, v24
	v_dual_mul_f32 v25, v39, v25 :: v_dual_lshlrev_b32 v24, 30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, v21, v25 :: v_dual_and_b32 v24, 0x80000000, v24
	v_fmaak_f32 v26, v39, v26, 0xbf000004
	v_xor_b32_e32 v24, v15, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v39, v26, 1.0
	v_and_b32_e32 v34, 0x80000000, v38
	v_fmaak_f32 v38, v36, v41, 0xbf000004
	v_fma_f32 v35, v36, v38, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, -v18, v35, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v40
	v_cndmask_b32_e32 v21, v25, v21, vcc_lo
	v_xor_b32_e32 v18, v34, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v21, v24, v21, v6
	v_cndmask_b32_e64 v18, 0x7fc00000, v18, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0x7fc00000, v21, s1
	v_mul_f32_e32 v21, v21, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, v18, v19, -v21
	v_add_f32_e32 v24, v3, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, s20, s20, v24
	v_div_scale_f32 v25, vcc_lo, v24, s20, v24
	v_rcp_f32_e32 v18, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v3, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v21, v18
	v_mul_f32_e32 v21, v25, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v3, v21, v25
	v_fmac_f32_e32 v21, v26, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v21, v25
	v_div_fmas_f32 v3, v3, v18, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v3, s20, v24
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v3, v3
	v_max_i32_e32 v18, 1, v3
	v_add_nc_u32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, -1, v18
	v_min_i32_e32 v25, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, v26, v25
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_46
; %bb.26:                               ; %.preheader272.lr.ph
	v_mul_hi_u32 v3, v32, v33
	s_mov_b32 s0, 0x7fffff
	v_mul_f64 v[33:34], v[10:11], 0.5
	v_and_or_b32 v46, v15, s0, 0x800000
	v_lshlrev_b32_e32 v41, 30, v28
	v_dual_add_f32 v11, s23, v4 :: v_dual_lshlrev_b32 v44, 30, v31
	v_add_f32_e32 v4, s24, v5
	v_mul_lo_u32 v3, v3, s9
	v_div_scale_f32 v5, null, v30, v30, v2
	v_dual_mul_f32 v42, v20, v20 :: v_dual_and_b32 v43, 1, v31
	v_min_i32_e32 v45, s5, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v39, v5
	v_dual_mul_f32 v21, v17, v17 :: v_dual_and_b32 v40, 1, v28
	v_sub_nc_u32_e32 v3, v32, v3
	v_mad_u64_u32 v[31:32], null, v12, s4, v[7:8]
	v_mad_u64_u32 v[12:13], null, 0xfe5163ab, v46, 0
	v_subrev_nc_u32_e32 v10, s9, v3
	v_cmp_le_u32_e64 s0, s9, v3
	v_div_scale_f32 v38, vcc_lo, v2, v30, v2
	v_add_nc_u32_e32 v32, 0xffffff88, v14
	v_rndne_f32_e32 v16, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v3, v10, s0
	v_mov_b32_e32 v3, 0
	v_xor_b32_e32 v47, 0x80000000, v6
	s_add_i32 s8, s26, -1
	s_add_i32 s7, s27, -1
	v_subrev_nc_u32_e32 v7, s9, v10
	v_cmp_le_u32_e64 s0, s9, v10
	v_mov_b32_e32 v14, v3
	s_mul_i32 s33, s27, s21
	s_mov_b32 s16, 0x55555555
	s_mov_b32 s22, 0xfefa39ef
	v_cndmask_b32_e64 v10, v10, v7, s0
	v_mad_u64_u32 v[35:36], null, 0x3c439041, v46, v[13:14]
	v_fma_f32 v14, -v5, v39, 1.0
	v_mul_f64 v[7:8], 0x3ff40000, v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v28, v10, v27
	v_mul_f64 v[9:10], 0x3ff40000, v[0:1]
	v_mov_b32_e32 v1, v3
	v_dual_fmac_f32 v39, v14, v39 :: v_dual_mov_b32 v0, v36
	v_sub_nc_u32_e32 v13, v28, v27
	v_mov_b32_e32 v28, v3
	s_mov_b32 s34, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v48, v38, v39
	s_mov_b32 s38, 0x968915a9
	v_subrev_nc_u32_e32 v27, s2, v13
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v46, v[0:1]
	s_mov_b32 s40, 0x4222de17
	s_mov_b32 s42, 0x3abe935a
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[0:1], v27
	s_mov_b32 s44, 0x47e6c9c2
	s_mov_b32 s46, 0xcfa74449
	s_mov_b32 s48, 0x71bf3c30
	v_mov_b32_e32 v27, v14
	v_fma_f32 v14, -v5, v48, v38
	v_and_b32_e32 v41, 0x80000000, v41
	s_mov_b32 s50, 0x1c7792ce
	s_mov_b32 s52, 0x924920da
	s_mov_b32 s54, 0x9999999c
	v_fmac_f32_e32 v48, v14, v39
	s_mov_b32 s56, 0xd5df274d
	s_mov_b32 s58, 0x652b82fe
	s_mov_b32 s60, 0xfca7ab0c
	s_mov_b32 s62, 0x623fde64
	v_fma_f32 v5, -v5, v48, v38
	s_mov_b32 s64, 0x7c89e6b0
	s_mov_b32 s66, 0x14761f6e
	s_mov_b32 s68, 0x1852b7b0
	s_mov_b32 s70, 0x11122322
	v_div_fmas_f32 v5, v5, v39, v48
	v_cmp_lt_u32_e32 vcc_lo, 63, v32
	s_mov_b32 s72, 0x555502a1
	s_mov_b32 s74, 0x55555511
	s_mov_b32 s76, 11
	v_div_fixup_f32 v2, v5, v30, v2
	v_fmaak_f32 v30, s6, v21, 0xbab64f3b
	v_mad_u64_u32 v[36:37], null, 0xf534ddc0, v46, v[27:28]
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	v_fmaak_f32 v49, s6, v42, 0xbab64f3b
	v_fmaak_f32 v5, s3, v21, 0x3c0881c4
	s_mov_b32 s78, 0x95aaf790
	s_mov_b32 s17, 0x3fe55555
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v27, v37 :: v_dual_add_nc_u32 v14, v14, v32
	s_mov_b32 s23, 0x3fe62e42
	s_mov_b32 s35, 0x3c7abc9e
	v_add_f64 v[0:1], v[33:34], v[0:1]
	v_cmp_lt_u32_e64 s0, 31, v14
	v_mad_u64_u32 v[37:38], null, 0xfc2757d1, v46, v[27:28]
	v_fmaak_f32 v48, s3, v42, 0x3c0881c4
	s_mov_b32 s39, 0x3fba6564
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, 0, 0xffffffe0, s0
	v_fmaak_f32 v5, v21, v5, 0xbe2aaa9d
	s_mov_b32 s41, 0x3fbdee67
	s_mov_b32 s43, 0x3fbe25e4
	v_mov_b32_e32 v27, v38
	v_cvt_f64_f32_e32 v[38:39], v2
	v_add_nc_u32_e32 v14, v34, v14
	s_mov_b32 s45, 0x3fc110ef
	s_mov_b32 s47, 0x3fc3b13b
	v_mad_u64_u32 v[32:33], null, 0x4e441529, v46, v[27:28]
	v_and_b32_e32 v44, 0x80000000, v44
	v_cmp_lt_u32_e64 s2, 31, v14
	s_mov_b32 s49, 0x3fc745d1
	s_mov_b32 s51, 0x3fcc71c7
	v_cndmask_b32_e32 v12, v13, v12, vcc_lo
	s_mov_b32 s53, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v27, v33
	s_mov_b32 s55, 0x3fd99999
	s_mov_b32 s57, 0x3c8543b0
	v_mul_f32_e32 v5, v21, v5
	s_mov_b32 s59, 0x3ff71547
	v_mad_u64_u32 v[33:34], null, 0xa2f9836e, v46, v[27:28]
	v_fmaak_f32 v27, v21, v30, 0x3d2aabf7
	v_fmaak_f32 v30, v42, v48, 0xbe2aaa9d
	v_cndmask_b32_e64 v46, 0, 0xffffffe0, s2
	v_cndmask_b32_e32 v48, v32, v36, vcc_lo
	v_cndmask_b32_e32 v35, v36, v35, vcc_lo
	v_xor_b32_e32 v28, v15, v41
	v_dual_cndmask_b32 v33, v33, v37 :: v_dual_cndmask_b32 v32, v34, v32
	v_cndmask_b32_e32 v34, v37, v13, vcc_lo
	v_add_nc_u32_e32 v14, v46, v14
	v_fmaak_f32 v41, v42, v49, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v36, v33, v48, s0
	v_cndmask_b32_e64 v32, v32, v33, s0
	v_cndmask_b32_e64 v33, v48, v34, s0
	v_sub_nc_u32_e32 v37, 32, v14
	v_cndmask_b32_e64 v34, v34, v35, s0
	v_dual_fmaak_f32 v27, v21, v27, 0xbf000004 :: v_dual_mul_f32 v30, v42, v30
	v_cndmask_b32_e64 v32, v32, v36, s2
	v_cndmask_b32_e64 v36, v36, v33, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_mul_f64 v[0:1], v[0:1], v[38:39]
	v_cndmask_b32_e64 v33, v33, v34, s2
	v_dual_fmaak_f32 v41, v42, v41, 0xbf000004 :: v_dual_fmac_f32 v20, v20, v30
	v_alignbit_b32 v46, v32, v36, v37
	v_fmac_f32_e32 v17, v17, v5
	v_fma_f32 v5, v21, v27, 1.0
	v_cndmask_b32_e64 v12, v35, v12, s0
	v_cmp_eq_u32_e64 s0, 0, v40
	v_cndmask_b32_e32 v14, v46, v32, vcc_lo
	v_alignbit_b32 v13, v36, v33, v37
	v_fma_f32 v27, v42, v41, 1.0
	v_cndmask_b32_e64 v12, v34, v12, s2
	v_cndmask_b32_e64 v5, v5, v17, s0
	v_cmp_eq_u32_e64 s0, 0, v43
	v_bfe_u32 v21, v14, 29, 1
	v_cvt_i32_f32_e32 v34, v16
	s_mov_b32 s61, 0x3e928af3
	v_xor3_b32 v5, v28, v5, v6
	v_cndmask_b32_e64 v17, -v20, v27, s0
	v_alignbit_b32 v20, v33, v12, v37
	v_cndmask_b32_e32 v13, v13, v36, vcc_lo
	v_sub_nc_u32_e32 v32, 0, v21
	v_cndmask_b32_e64 v5, 0x7fc00000, v5, s1
	v_xor_b32_e32 v17, v44, v17
	v_cndmask_b32_e32 v20, v20, v33, vcc_lo
	v_alignbit_b32 v30, v14, v13, 30
	v_fma_f32 v33, 0xbfc90fda, v16, |v6|
	s_mov_b32 s63, 0x3ec71dee
	v_cndmask_b32_e64 v17, 0x7fc00000, v17, s1
	v_alignbit_b32 v13, v13, v20, 30
	v_xor_b32_e32 v27, v30, v32
	v_alignbit_b32 v12, v20, v12, 30
	v_fmamk_f32 v33, v16, 0xb3a22168, v33
	v_mul_f32_e32 v17, v17, v29
	s_mov_b32 s65, 0x3efa0199
	v_clz_i32_u32_e32 v28, v27
	v_xor_b32_e32 v12, v12, v32
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_xor_b32_e32 v1, v13, v32
	v_fmac_f32_e32 v17, v5, v19
	v_min_u32_e32 v30, 32, v28
	v_fmamk_f32 v16, v16, 0xa7c234c4, v33
	v_ashrrev_i32_e32 v32, 31, v31
	v_mul_lo_u32 v28, v45, s25
	s_mov_b32 s24, 0x6a5dcb37
	v_sub_nc_u32_e32 v13, 31, v30
	s_mov_b32 s25, 0x3e5ade15
	s_mov_b32 s67, 0x3f2a01a0
	s_mov_b32 s69, 0x3f56c16c
	s_mov_b32 s71, 0x3f811111
	v_alignbit_b32 v5, v27, v1, v13
	v_alignbit_b32 v1, v1, v12, v13
	v_add_f32_e32 v27, v11, v17
	v_lshrrev_b32_e32 v11, 29, v14
	v_add3_u32 v18, v18, v28, -1
	s_mov_b32 s73, 0x3fa55555
	v_alignbit_b32 v12, v5, v1, 9
	v_div_scale_f32 v13, null, s20, s20, v27
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_clz_i32_u32_e32 v17, v12
	v_rcp_f32_e32 v19, v13
	v_div_scale_f32 v36, vcc_lo, v27, s20, v27
	v_or_b32_e32 v20, 0.5, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_min_u32_e32 v17, 32, v17
	s_mov_b32 s75, 0x3fc55555
	s_mov_b32 s77, 0x3fe00000
	s_mov_b32 s79, 0x4005bf09
	s_mov_b32 s81, 0xbfe62e42
	v_sub_nc_u32_e32 v35, 31, v17
	s_mov_b32 s83, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_alignbit_b32 v1, v12, v1, v35
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v13, v19, 1.0
	v_lshrrev_b32_e32 v1, 9, v1
	v_fmac_f32_e32 v19, v12, v19
	v_lshlrev_b32_e32 v29, 23, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v20, v20, v29
	v_add_f32_e32 v29, v4, v0
	v_add_lshl_u32 v0, v17, v30, 23
	v_mul_lo_u32 v30, v31, s19
	v_or_b32_e32 v5, v5, v20
	v_mul_f32_e32 v20, v36, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v1, v0
	v_mul_f32_e32 v17, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v37, 0x33000000, v0
	v_lshlrev_b64 v[0:1], 2, v[31:32]
	v_fma_f32 v31, -v13, v20, v36
	v_fma_f32 v12, 0x3fc90fda, v5, -v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v11, v37, v11
	v_fmac_f32_e32 v20, v31, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v5, 0x33a22168, v12
	v_fmac_f32_e32 v5, 0x3fc90fda, v11
	v_add_co_u32 v11, s2, s10, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v0, -v13, v20, v36
	v_add_f32_e32 v5, v17, v5
	v_max3_f32 v17, v23, v22, v2
	v_lshrrev_b32_e32 v2, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v0, v0, v19, v20
	v_dual_mul_f32 v33, 0.5, v17 :: v_dual_add_nc_u32 v2, v21, v2
	v_div_scale_f32 v4, null, s20, s20, v29
	v_div_scale_f32 v31, s0, v29, s20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 vcc_lo, s0
	v_rcp_f32_e32 v35, v4
	v_div_fixup_f32 v0, v0, s20, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v4, v35, 1.0
	v_cvt_i32_f32_e32 v0, v0
	v_fmac_f32_e32 v35, v12, v35
	v_add_co_ci_u32_e64 v12, s2, s11, v1, s2
	v_cmp_gt_f32_e64 s2, 0x48000000, |v6|
	s_mov_b32 s11, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v1, v31, v35
	v_add_nc_u32_e32 v21, 1, v0
	v_cndmask_b32_e64 v16, v5, v16, s2
	v_cndmask_b32_e64 v2, v2, v34, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v4, v1, v31
	v_mul_f64 v[5:6], 0x3ff40000, v[38:39]
	v_dual_fmac_f32 v1, v13, v35 :: v_dual_and_b32 v20, 1, v2
	v_dual_mul_f32 v13, v16, v16 :: v_dual_lshlrev_b32 v2, 30, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v4, v1, v31
	v_fmaak_f32 v14, s3, v13, 0x3c0881c4
	v_min_i32_e32 v31, s8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v1, v4, v35, v1
	v_fmaak_f32 v4, v13, v14, 0xbe2aaa9d
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v1, v1, s20, v29
	v_mul_f32_e32 v4, v13, v4
	s_mul_i32 s20, s33, s26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v1, v1
	v_fmac_f32_e32 v16, v16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v4, v1
	v_fmaak_f32 v19, s6, v13, 0xbab64f3b
	v_fmaak_f32 v14, v13, v19, 0x3d2aabf7
	v_max_i32_e32 v19, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, v13, v14, 0xbf000004
	v_fma_f32 v0, v13, v14, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v13, -1, v19
	v_max_i32_e32 v14, 1, v4
	v_add_nc_u32_e32 v4, 1, v4
	v_cndmask_b32_e64 v19, -v16, v0, vcc_lo
	v_cndmask_b32_e32 v16, v0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, s26, v18, v[13:14]
	v_add_nc_u32_e32 v14, -1, v14
	v_and_b32_e32 v18, 0x80000000, v2
	v_xor_b32_e32 v16, v16, v47
	v_min_i32_e32 v32, s7, v4
	v_cmp_le_i32_e64 s0, v13, v31
	v_mad_u64_u32 v[1:2], null, s27, v0, v[14:15]
	v_xor_b32_e32 v19, v18, v19
	v_xor3_b32 v0, v16, v15, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, 0x7fc00000, v19, s1
	v_mul_lo_u32 v36, s21, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v35, 0x7fc00000, v0, s1
	v_cmp_le_i32_e64 s1, v14, v32
.LBB2_27:                               ; %.preheader272
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_29 Depth 2
                                        ;       Child Loop BB2_31 Depth 3
                                        ;         Child Loop BB2_34 Depth 4
	s_and_saveexec_b32 s84, s0
	s_cbranch_execz .LBB2_45
; %bb.28:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB2_27 Depth=1
	v_dual_mov_b32 v39, v13 :: v_dual_add_nc_u32 v0, v26, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v38, v36
	s_mov_b32 s85, 0
	v_mul_lo_u32 v37, v0, s26
.LBB2_29:                               ; %.preheader
                                        ;   Parent Loop BB2_27 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_31 Depth 3
                                        ;         Child Loop BB2_34 Depth 4
	s_and_saveexec_b32 s86, s1
	s_cbranch_execz .LBB2_44
; %bb.30:                               ; %.lr.ph277
                                        ;   in Loop: Header=BB2_29 Depth=2
	global_load_b32 v42, v[11:12], off
	v_dual_mov_b32 v15, v38 :: v_dual_add_nc_u32 v0, v37, v39
	v_mov_b32_e32 v41, v14
	s_mov_b32 s87, 0
                                        ; implicit-def: $sgpr88
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v40, v0, s27
.LBB2_31:                               ;   Parent Loop BB2_27 Depth=1
                                        ;     Parent Loop BB2_29 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB2_34 Depth 4
	s_or_b32 s88, s88, exec_lo
	s_mov_b32 s89, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 s19, v42
	s_cbranch_execz .LBB2_43
; %bb.32:                               ;   in Loop: Header=BB2_31 Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v41, v40
	s_mov_b32 s90, exec_lo
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s14, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v43, s21, v0
	v_cmpx_lt_i32_e32 0, v43
	s_cbranch_execz .LBB2_42
; %bb.33:                               ; %.lr.ph
                                        ;   in Loop: Header=BB2_31 Depth=3
	v_ashrrev_i32_e32 v16, 31, v15
	s_mov_b32 s92, 1
	s_mov_b32 s91, 0
                                        ; implicit-def: $sgpr93
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[15:16]
	v_add_co_u32 v16, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, s13, v1, vcc_lo
.LBB2_34:                               ; %_ZL4cosff.exit231
                                        ;   Parent Loop BB2_27 Depth=1
                                        ;     Parent Loop BB2_29 Depth=2
                                        ;       Parent Loop BB2_31 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v44, v[16:17], off
	s_or_b32 s93, s93, exec_lo
	s_mov_b32 s94, exec_lo
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v0, v44, 1, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s36, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s37, v1, vcc_lo
	global_load_b96 v[0:2], v[0:1], off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v45, v1, v27 :: v_dual_sub_f32 v46, v0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v45, v35
	v_fma_f32 v0, v46, v34, -v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e64 v[0:1], |v0|
	v_cmpx_ge_f64_e32 v[7:8], v[0:1]
	s_cbranch_execz .LBB2_40
; %bb.35:                               ;   in Loop: Header=BB2_34 Depth=4
	v_mul_f32_e32 v4, v45, v34
	v_sub_f32_e32 v2, v2, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v4, v46, v35
	v_cvt_f64_f32_e64 v[0:1], |v2|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e64 v[18:19], |v4|
	v_cmp_ge_f64_e32 vcc_lo, v[5:6], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f64_e64 s2, v[9:10], v[18:19]
	s_and_b32 s3, s2, vcc_lo
	s_mov_b32 s2, -1
	s_and_saveexec_b32 s95, s3
	s_cbranch_execz .LBB2_39
; %bb.36:                               ;   in Loop: Header=BB2_34 Depth=4
	s_mov_b32 s96, 0
	s_mov_b32 s97, exec_lo
	v_cmpx_gt_i32_e64 s19, v42
	s_cbranch_execz .LBB2_38
; %bb.37:                               ;   in Loop: Header=BB2_34 Depth=4
	v_cvt_f64_f32_e32 v[0:1], v46
	s_mov_b32 s10, s16
	s_mov_b32 s80, s22
	s_mov_b32 s82, s34
	s_mov_b32 s96, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[18:19], |v[0:1]|
	v_cmp_gt_f64_e32 vcc_lo, s[16:17], v[18:19]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[22:23], v[18:19], v4
	v_cvt_f64_f32_e32 v[18:19], v45
	v_add_f64 v[47:48], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_frexp_mant_f64_e64 v[20:21], |v[18:19]|
	v_add_f64 v[65:66], v[22:23], -1.0
	v_rcp_f64_e32 v[49:50], v[47:48]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e64 s2, s[16:17], v[20:21]
	v_add_f64 v[71:72], v[47:48], -1.0
	v_cndmask_b32_e64 v4, 0, 1, s2
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[53:54], -v[47:48], v[49:50], 1.0
	v_add_f64 v[22:23], v[22:23], -v[71:72]
	v_ldexp_f64 v[51:52], v[20:21], v4
	v_cvt_f64_f32_e32 v[20:21], v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[49:50], v[53:54], v[49:50], v[49:50]
	v_add_f64 v[55:56], v[51:52], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_frexp_mant_f64_e64 v[57:58], |v[20:21]|
	v_add_f64 v[75:76], v[51:52], -1.0
	v_fma_f64 v[59:60], -v[47:48], v[49:50], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[53:54], v[55:56]
	v_cmp_gt_f64_e64 s3, s[16:17], v[57:58]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[49:50], v[59:60], v[49:50], v[49:50]
	v_cndmask_b32_e64 v4, 0, 1, s3
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[61:62], -v[55:56], v[53:54], 1.0
	v_ldexp_f64 v[57:58], v[57:58], v4
	v_frexp_exp_i32_f64_e32 v4, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[53:54], v[61:62], v[53:54], v[53:54]
	v_mul_f64 v[61:62], v[65:66], v[49:50]
	v_add_f64 v[63:64], v[57:58], 1.0
	v_add_f64 v[77:78], v[57:58], -1.0
	v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_fma_f64 v[67:68], -v[55:56], v[53:54], 1.0
	v_mul_f64 v[73:74], v[47:48], v[61:62]
	v_rcp_f64_e32 v[59:60], v[63:64]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[53:54], v[67:68], v[53:54], v[53:54]
	v_fma_f64 v[47:48], v[61:62], v[47:48], -v[73:74]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[69:70], -v[63:64], v[59:60], 1.0
	v_mul_f64 v[67:68], v[75:76], v[53:54]
	v_fma_f64 v[22:23], v[61:62], v[22:23], v[47:48]
	v_add_f64 v[47:48], v[55:56], -1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[59:60], v[69:70], v[59:60], v[59:60]
	v_mul_f64 v[71:72], v[55:56], v[67:68]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[47:48], v[51:52], -v[47:48]
	v_fma_f64 v[69:70], -v[63:64], v[59:60], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[51:52], v[67:68], v[55:56], -v[71:72]
	v_fma_f64 v[59:60], v[69:70], v[59:60], v[59:60]
	v_add_f64 v[69:70], v[73:74], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[47:48], v[67:68], v[47:48], v[51:52]
	v_add_f64 v[51:52], v[63:64], -1.0
	v_mul_f64 v[55:56], v[77:78], v[59:60]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[79:80], v[65:66], -v[69:70]
	v_add_f64 v[73:74], v[69:70], -v[73:74]
	v_add_f64 v[83:84], v[71:72], v[47:48]
	v_add_f64 v[51:52], v[57:58], -v[51:52]
	v_mul_f64 v[81:82], v[63:64], v[55:56]
	v_add_f64 v[65:66], v[65:66], -v[79:80]
	v_add_f64 v[22:23], v[73:74], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[57:58], v[55:56], v[63:64], -v[81:82]
	v_add_f64 v[63:64], v[65:66], -v[69:70]
	v_add_f64 v[65:66], v[75:76], -v[83:84]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[51:52], v[55:56], v[51:52], v[57:58]
	v_add_f64 v[22:23], v[22:23], v[63:64]
	v_add_f64 v[57:58], v[83:84], -v[71:72]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[63:64], v[75:76], -v[65:66]
	v_add_f64 v[69:70], v[81:82], v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[79:80], v[22:23]
	v_add_f64 v[47:48], v[57:58], -v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[57:58], v[63:64], -v[83:84]
	v_add_f64 v[63:64], v[77:78], -v[69:70]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f64 v[22:23], v[49:50], v[22:23]
	v_add_f64 v[49:50], v[69:70], -v[81:82]
	v_add_f64 v[47:48], v[47:48], v[57:58]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[57:58], v[77:78], -v[63:64]
	v_add_f64 v[71:72], v[61:62], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[49:50], v[49:50], -v[51:52]
	v_add_f64 v[47:48], v[65:66], v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[51:52], v[57:58], -v[69:70]
	v_add_f64 v[57:58], v[71:72], -v[61:62]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[47:48], v[53:54], v[47:48]
	v_add_f64 v[49:50], v[49:50], v[51:52]
	v_mul_f64 v[51:52], v[71:72], v[71:72]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[57:58]
	v_add_f64 v[53:54], v[67:68], v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[49:50], v[63:64], v[49:50]
	v_fma_f64 v[57:58], v[71:72], v[71:72], -v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[61:62], v[22:23], v[22:23]
	v_add_f64 v[63:64], v[53:54], -v[67:68]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f64 v[49:50], v[59:60], v[49:50]
	v_mul_f64 v[59:60], v[53:54], v[53:54]
	v_fma_f64 v[57:58], v[71:72], v[61:62], v[57:58]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[47:48], v[47:48], -v[63:64]
	v_add_f64 v[61:62], v[55:56], v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[65:66], v[53:54], v[53:54], -v[59:60]
	v_add_f64 v[63:64], v[51:52], v[57:58]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[67:68], v[47:48], v[47:48]
	v_add_f64 v[55:56], v[61:62], -v[55:56]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[69:70], v[63:64], s[40:41], s[38:39]
	v_fma_f64 v[65:66], v[53:54], v[67:68], v[65:66]
	v_mul_f64 v[67:68], v[61:62], v[61:62]
	v_add_f64 v[51:52], v[63:64], -v[51:52]
	v_mul_f64 v[87:88], v[71:72], v[63:64]
	v_add_f64 v[49:50], v[49:50], -v[55:56]
	v_fma_f64 v[55:56], v[63:64], v[69:70], s[42:43]
	v_add_f64 v[69:70], v[59:60], v[65:66]
	v_fma_f64 v[73:74], v[61:62], v[61:62], -v[67:68]
	v_add_f64 v[51:52], v[57:58], -v[51:52]
	v_fma_f64 v[89:90], v[63:64], v[71:72], -v[87:88]
	v_add_f64 v[75:76], v[49:50], v[49:50]
	v_fma_f64 v[55:56], v[63:64], v[55:56], s[44:45]
	v_fma_f64 v[77:78], v[69:70], s[40:41], s[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[73:74], v[61:62], v[75:76], v[73:74]
	v_fma_f64 v[55:56], v[63:64], v[55:56], s[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[75:76], v[69:70], v[77:78], s[42:43]
	v_add_f64 v[77:78], v[67:68], v[73:74]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[55:56], v[63:64], v[55:56], s[48:49]
	v_fma_f64 v[75:76], v[69:70], v[75:76], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[79:80], v[77:78], s[40:41], s[38:39]
	v_add_f64 v[67:68], v[77:78], -v[67:68]
	v_fma_f64 v[55:56], v[63:64], v[55:56], s[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[75:76], v[69:70], v[75:76], s[46:47]
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[42:43]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[67:68], v[73:74], -v[67:68]
	v_fma_f64 v[55:56], v[63:64], v[55:56], s[52:53]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[75:76], v[69:70], v[75:76], s[48:49]
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[55:56], v[63:64], v[55:56], s[54:55]
	v_fma_f64 v[75:76], v[69:70], v[75:76], s[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[46:47]
	v_mul_f64 v[81:82], v[63:64], v[55:56]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[75:76], v[69:70], v[75:76], s[52:53]
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[57:58], v[63:64], v[55:56], -v[81:82]
	v_fma_f64 v[75:76], v[69:70], v[75:76], s[54:55]
	v_fma_f64 v[63:64], v[63:64], v[22:23], v[89:90]
	v_mul_f64 v[89:90], v[53:54], v[69:70]
	v_ldexp_f64 v[22:23], v[22:23], 1
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[50:51]
	v_fma_f64 v[55:56], v[51:52], v[55:56], v[57:58]
	v_add_f64 v[57:58], v[69:70], -v[59:60]
	v_mul_f64 v[59:60], v[69:70], v[75:76]
	v_fma_f64 v[51:52], v[51:52], v[71:72], v[63:64]
	v_ldexp_f64 v[71:72], v[71:72], 1
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[52:53]
	v_add_f64 v[83:84], v[81:82], v[55:56]
	v_add_f64 v[57:58], v[65:66], -v[57:58]
	v_fma_f64 v[65:66], v[69:70], v[75:76], -v[59:60]
	v_add_f64 v[93:94], v[87:88], v[51:52]
	v_fma_f64 v[79:80], v[77:78], v[79:80], s[54:55]
	v_add_f64 v[81:82], v[83:84], -v[81:82]
	v_add_f64 v[85:86], v[83:84], s[16:17]
	v_fma_f64 v[65:66], v[57:58], v[75:76], v[65:66]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[75:76], v[77:78], v[79:80]
	v_add_f64 v[55:56], v[55:56], -v[81:82]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[81:82], v[85:86], s[10:11]
	v_add_f64 v[91:92], v[59:60], v[65:66]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[73:74], v[77:78], v[79:80], -v[75:76]
	v_add_f64 v[55:56], v[55:56], s[56:57]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[81:82], v[83:84], -v[81:82]
	v_add_f64 v[59:60], v[91:92], -v[59:60]
	v_add_f64 v[83:84], v[91:92], s[16:17]
	v_fma_f64 v[73:74], v[67:68], v[79:80], v[73:74]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[55:56], v[55:56], v[81:82]
	v_add_f64 v[59:60], v[65:66], -v[59:60]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[63:64], v[83:84], s[10:11]
	v_fma_f64 v[65:66], v[69:70], v[53:54], -v[89:90]
	v_add_f64 v[79:80], v[75:76], v[73:74]
	v_add_f64 v[81:82], v[85:86], v[55:56]
	v_add_f64 v[59:60], v[59:60], s[56:57]
	v_add_f64 v[63:64], v[91:92], -v[63:64]
	v_fma_f64 v[65:66], v[69:70], v[47:48], v[65:66]
	v_mul_f64 v[91:92], v[61:62], v[77:78]
	v_ldexp_f64 v[47:48], v[47:48], 1
	v_add_f64 v[69:70], v[79:80], -v[75:76]
	v_add_f64 v[75:76], v[79:80], s[16:17]
	v_add_f64 v[85:86], v[85:86], -v[81:82]
	v_mul_f64 v[95:96], v[93:94], v[81:82]
	v_add_f64 v[59:60], v[59:60], v[63:64]
	v_fma_f64 v[57:58], v[57:58], v[53:54], v[65:66]
	v_ldexp_f64 v[53:54], v[53:54], 1
	v_add_f64 v[63:64], v[73:74], -v[69:70]
	v_add_f64 v[65:66], v[75:76], s[10:11]
	v_fma_f64 v[69:70], v[77:78], v[61:62], -v[91:92]
	v_add_f64 v[73:74], v[93:94], -v[87:88]
	v_add_f64 v[55:56], v[55:56], v[85:86]
	v_fma_f64 v[85:86], v[93:94], v[81:82], -v[95:96]
	v_add_f64 v[87:88], v[83:84], v[59:60]
	v_add_f64 v[97:98], v[89:90], v[57:58]
	v_add_f64 v[63:64], v[63:64], s[56:57]
	v_add_f64 v[65:66], v[79:80], -v[65:66]
	v_fma_f64 v[69:70], v[77:78], v[49:50], v[69:70]
	v_add_f64 v[51:52], v[51:52], -v[73:74]
	v_ldexp_f64 v[49:50], v[49:50], 1
	v_fma_f64 v[55:56], v[93:94], v[55:56], v[85:86]
	v_add_f64 v[73:74], v[83:84], -v[87:88]
	v_mul_f64 v[77:78], v[97:98], v[87:88]
	v_add_f64 v[63:64], v[63:64], v[65:66]
	v_fma_f64 v[65:66], v[67:68], v[61:62], v[69:70]
	v_ldexp_f64 v[61:62], v[61:62], 1
	v_fma_f64 v[51:52], v[51:52], v[81:82], v[55:56]
	v_add_f64 v[55:56], v[97:98], -v[89:90]
	v_add_f64 v[59:60], v[59:60], v[73:74]
	v_fma_f64 v[67:68], v[97:98], v[87:88], -v[77:78]
	v_add_f64 v[69:70], v[75:76], v[63:64]
	v_add_f64 v[73:74], v[91:92], v[65:66]
	v_add_f64 v[79:80], v[95:96], v[51:52]
	v_add_f64 v[55:56], v[57:58], -v[55:56]
	v_fma_f64 v[57:58], v[97:98], v[59:60], v[67:68]
	v_add_f64 v[59:60], v[75:76], -v[69:70]
	v_mul_f64 v[67:68], v[73:74], v[69:70]
	v_cvt_f64_i32_e32 v[75:76], v4
	v_frexp_exp_i32_f64_e32 v4, v[18:19]
	v_add_f64 v[81:82], v[79:80], -v[95:96]
	v_add_f64 v[83:84], v[71:72], v[79:80]
	v_fma_f64 v[55:56], v[55:56], v[87:88], v[57:58]
	v_add_f64 v[57:58], v[73:74], -v[91:92]
	v_add_f64 v[59:60], v[63:64], v[59:60]
	v_fma_f64 v[63:64], v[73:74], v[69:70], -v[67:68]
	v_mul_f64 v[85:86], v[75:76], s[22:23]
	v_subrev_co_ci_u32_e64 v4, vcc_lo, 0, v4, s2
	v_add_f64 v[51:52], v[51:52], -v[81:82]
	v_add_f64 v[71:72], v[83:84], -v[71:72]
	v_add_f64 v[81:82], v[77:78], v[55:56]
	v_add_f64 v[57:58], v[65:66], -v[57:58]
	v_cvt_f64_i32_e32 v[65:66], v4
	v_frexp_exp_i32_f64_e32 v4, v[20:21]
	v_cmp_eq_f32_e64 s2, 1.0, v45
	v_fma_f64 v[59:60], v[73:74], v[59:60], v[63:64]
	v_fma_f64 v[63:64], v[75:76], s[22:23], -v[85:86]
	v_add_f64 v[22:23], v[22:23], v[51:52]
	v_add_f64 v[51:52], v[79:80], -v[71:72]
	v_add_f64 v[71:72], v[81:82], -v[77:78]
	v_add_f64 v[73:74], v[53:54], v[81:82]
	v_subrev_co_ci_u32_e64 v4, vcc_lo, 0, v4, s3
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v46
	v_cmp_eq_f32_e64 s3, 1.0, v2
	v_fma_f64 v[57:58], v[57:58], v[69:70], v[59:60]
	v_fma_f64 v[59:60], v[75:76], s[34:35], v[63:64]
	v_add_f64 v[22:23], v[22:23], v[51:52]
	v_mul_f64 v[51:52], v[65:66], s[22:23]
	v_add_f64 v[55:56], v[55:56], -v[71:72]
	v_add_f64 v[53:54], v[73:74], -v[53:54]
	v_add_f64 v[63:64], v[67:68], v[57:58]
	v_add_f64 v[69:70], v[85:86], v[59:60]
	v_add_f64 v[71:72], v[83:84], v[22:23]
	v_fma_f64 v[75:76], v[65:66], s[22:23], -v[51:52]
	v_add_f64 v[47:48], v[47:48], v[55:56]
	v_add_f64 v[53:54], v[81:82], -v[53:54]
	v_cvt_f64_i32_e32 v[55:56], v4
	v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, vcc_lo
	v_add_f64 v[67:68], v[63:64], -v[67:68]
	v_add_f64 v[77:78], v[61:62], v[63:64]
	v_add_f64 v[79:80], v[69:70], v[71:72]
	v_fma_f64 v[65:66], v[65:66], s[34:35], v[75:76]
	v_add_f64 v[47:48], v[47:48], v[53:54]
	v_mul_f64 v[53:54], v[55:56], s[22:23]
	v_add_f64 v[57:58], v[57:58], -v[67:68]
	v_add_f64 v[61:62], v[77:78], -v[61:62]
	v_add_f64 v[67:68], v[79:80], -v[69:70]
	v_add_f64 v[75:76], v[51:52], v[65:66]
	v_add_f64 v[81:82], v[73:74], v[47:48]
	v_fma_f64 v[87:88], v[55:56], s[22:23], -v[53:54]
	v_add_f64 v[49:50], v[49:50], v[57:58]
	v_add_f64 v[57:58], v[63:64], -v[61:62]
	v_add_f64 v[61:62], v[69:70], -v[85:86]
	v_add_f64 v[63:64], v[71:72], -v[83:84]
	v_add_f64 v[83:84], v[79:80], -v[67:68]
	v_add_f64 v[51:52], v[75:76], -v[51:52]
	v_add_f64 v[85:86], v[75:76], v[81:82]
	v_fma_f64 v[55:56], v[55:56], s[34:35], v[87:88]
	v_add_f64 v[49:50], v[49:50], v[57:58]
	v_add_f64 v[57:58], v[59:60], -v[61:62]
	v_add_f64 v[22:23], v[22:23], -v[63:64]
	v_add_f64 v[59:60], v[71:72], -v[67:68]
	v_add_f64 v[61:62], v[69:70], -v[83:84]
	v_add_f64 v[51:52], v[65:66], -v[51:52]
	v_add_f64 v[63:64], v[85:86], -v[75:76]
	v_add_f64 v[67:68], v[53:54], v[55:56]
	v_add_f64 v[69:70], v[77:78], v[49:50]
	v_add_f64 v[71:72], v[57:58], v[22:23]
	v_add_f64 v[59:60], v[59:60], v[61:62]
	v_add_f64 v[61:62], v[81:82], -v[73:74]
	v_add_f64 v[73:74], v[85:86], -v[63:64]
	v_add_f64 v[53:54], v[67:68], -v[53:54]
	v_add_f64 v[83:84], v[67:68], v[69:70]
	v_add_f64 v[87:88], v[71:72], -v[57:58]
	v_add_f64 v[59:60], v[71:72], v[59:60]
	v_add_f64 v[47:48], v[47:48], -v[61:62]
	v_add_f64 v[61:62], v[81:82], -v[63:64]
	v_add_f64 v[63:64], v[75:76], -v[73:74]
	v_add_f64 v[53:54], v[55:56], -v[53:54]
	v_add_f64 v[65:66], v[83:84], -v[67:68]
	v_add_f64 v[71:72], v[71:72], -v[87:88]
	v_add_f64 v[22:23], v[22:23], -v[87:88]
	v_add_f64 v[73:74], v[79:80], v[59:60]
	v_add_f64 v[75:76], v[51:52], v[47:48]
	v_add_f64 v[61:62], v[61:62], v[63:64]
	v_add_f64 v[63:64], v[69:70], -v[77:78]
	v_add_f64 v[77:78], v[83:84], -v[65:66]
	v_add_f64 v[55:56], v[69:70], -v[65:66]
	v_add_f64 v[57:58], v[57:58], -v[71:72]
	v_add_f64 v[71:72], v[73:74], -v[79:80]
	v_add_f64 v[79:80], v[75:76], -v[51:52]
	v_add_f64 v[61:62], v[75:76], v[61:62]
	v_add_f64 v[49:50], v[49:50], -v[63:64]
	v_add_f64 v[63:64], v[67:68], -v[77:78]
	v_add_f64 v[22:23], v[22:23], v[57:58]
	v_add_f64 v[57:58], v[59:60], -v[71:72]
	v_add_f64 v[59:60], v[75:76], -v[79:80]
	v_add_f64 v[47:48], v[47:48], -v[79:80]
	v_add_f64 v[65:66], v[85:86], v[61:62]
	v_add_f64 v[67:68], v[53:54], v[49:50]
	v_add_f64 v[55:56], v[55:56], v[63:64]
	v_add_f64 v[22:23], v[22:23], v[57:58]
	v_add_f64 v[51:52], v[51:52], -v[59:60]
	v_add_f64 v[57:58], v[65:66], -v[85:86]
	v_add_f64 v[59:60], v[67:68], -v[53:54]
	v_add_f64 v[55:56], v[67:68], v[55:56]
	v_add_f64 v[63:64], v[73:74], v[22:23]
	v_add_f64 v[47:48], v[47:48], v[51:52]
	v_add_f64 v[51:52], v[61:62], -v[57:58]
	v_add_f64 v[57:58], v[67:68], -v[59:60]
	v_add_f64 v[49:50], v[49:50], -v[59:60]
	v_add_f64 v[61:62], v[83:84], v[55:56]
	v_add_f64 v[67:68], v[63:64], -v[73:74]
	v_mul_f64 v[69:70], v[3:4], v[63:64]
	v_add_f64 v[47:48], v[47:48], v[51:52]
	v_add_f64 v[51:52], v[53:54], -v[57:58]
	v_trunc_f64_e32 v[57:58], v[3:4]
	v_add_f64 v[53:54], v[61:62], -v[83:84]
	v_add_f64 v[22:23], v[22:23], -v[67:68]
	v_fma_f64 v[59:60], v[3:4], v[63:64], -v[69:70]
	v_add_f64 v[63:64], v[65:66], v[47:48]
	v_add_f64 v[49:50], v[49:50], v[51:52]
	v_cmp_eq_f64_e32 vcc_lo, v[57:58], v[3:4]
	v_add_f64 v[51:52], v[55:56], -v[53:54]
	v_mul_f64 v[53:54], v[3:4], 0.5
	v_fma_f64 v[22:23], v[3:4], v[22:23], v[59:60]
	v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, s2
	v_add_f64 v[55:56], v[63:64], -v[65:66]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f64 v[57:58], v[3:4], v[63:64]
	v_add_f64 v[49:50], v[49:50], v[51:52]
	v_trunc_f64_e32 v[51:52], v[3:4]
	v_add_f64 v[47:48], v[47:48], -v[55:56]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[55:56], v[3:4], v[63:64], -v[57:58]
	v_mul_f64 v[63:64], v[3:4], 0.5
	v_cmp_class_f64_e64 s4, v[57:58], 0x204
	v_add_f64 v[59:60], v[61:62], v[49:50]
	v_cmp_eq_f64_e64 s2, v[51:52], v[3:4]
	v_fma_f64 v[47:48], v[3:4], v[47:48], v[55:56]
	v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, s3
	v_cmp_class_f64_e64 s3, v[69:70], 0x204
	v_add_f64 v[51:52], v[59:60], -v[61:62]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[55:56], v[3:4], v[59:60]
	v_add_f64 v[61:62], v[57:58], v[47:48]
	v_add_f64 v[49:50], v[49:50], -v[51:52]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[51:52], v[3:4], v[59:60], -v[55:56]
	v_add_f64 v[59:60], v[69:70], v[22:23]
	v_cndmask_b32_e64 v68, v62, v58, s4
	v_cndmask_b32_e64 v67, v61, v57, s4
	v_add_f64 v[57:58], v[61:62], -v[57:58]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[73:74], v[67:68], s[58:59]
	v_cmp_nlt_f64_e64 s7, 0x40900000, v[67:68]
	v_cmp_ngt_f64_e64 s8, 0xc090cc00, v[67:68]
	v_cmp_neq_f64_e64 s6, 0x7ff00000, |v[67:68]|
	v_fma_f64 v[49:50], v[3:4], v[49:50], v[51:52]
	v_cndmask_b32_e64 v52, v60, v70, s3
	v_cndmask_b32_e64 v51, v59, v69, s3
	v_cmp_class_f64_e64 s3, v[55:56], 0x204
	v_add_f64 v[59:60], v[59:60], -v[69:70]
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[65:66], v[51:52], s[58:59]
	v_cmp_nlt_f64_e64 s4, 0x40900000, v[51:52]
	v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[51:52]
	v_add_f64 v[47:48], v[47:48], -v[57:58]
	v_mul_f64 v[57:58], v[3:4], 0.5
	v_rndne_f64_e32 v[73:74], v[73:74]
	v_add_f64 v[71:72], v[55:56], v[49:50]
	v_add_f64 v[22:23], v[22:23], -v[59:60]
	v_rndne_f64_e32 v[65:66], v[65:66]
	v_cndmask_b32_e64 v48, 0, v48, s6
	v_cndmask_b32_e64 v47, 0, v47, s6
	v_fma_f64 v[81:82], v[73:74], s[80:81], v[67:68]
	v_cndmask_b32_e64 v76, v72, v56, s3
	v_cndmask_b32_e64 v75, v71, v55, s3
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[51:52]|
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[77:78], v[75:76], s[58:59]
	v_fma_f64 v[79:80], v[65:66], s[80:81], v[51:52]
	v_cvt_i32_f64_e32 v91, v[65:66]
	v_add_f64 v[51:52], v[71:72], -v[55:56]
	v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[75:76]
	v_fma_f64 v[81:82], v[73:74], s[82:83], v[81:82]
	v_cndmask_b32_e64 v23, 0, v23, s3
	v_cndmask_b32_e64 v22, 0, v22, s3
	s_and_b32 s3, s5, s4
	v_rndne_f64_e32 v[77:78], v[77:78]
	v_fma_f64 v[79:80], v[65:66], s[82:83], v[79:80]
	v_add_f64 v[49:50], v[49:50], -v[51:52]
	v_fma_f64 v[87:88], v[81:82], s[24:25], s[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[83:84], v[77:78], s[80:81], v[75:76]
	v_fma_f64 v[85:86], v[79:80], s[24:25], s[60:61]
	v_cmp_class_f64_e64 s80, v[0:1], 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[62:63]
	v_fma_f64 v[83:84], v[77:78], s[82:83], v[83:84]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[62:63]
	v_cmp_class_f64_e64 s82, v[18:19], 0x204
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[89:90], v[83:84], s[24:25], s[60:61]
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[64:65]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[66:67]
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[66:67]
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[64:65]
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[70:71]
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[66:67]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[70:71]
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[68:69]
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[74:75]
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[70:71]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[74:75]
	v_fma_f64 v[87:88], v[81:82], v[87:88], s[76:77]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[72:73]
	v_fma_f64 v[85:86], v[79:80], v[85:86], s[76:77]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[87:88], v[81:82], v[87:88], 1.0
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[74:75]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[85:86], v[79:80], v[85:86], 1.0
	v_fma_f64 v[89:90], v[83:84], v[89:90], s[76:77]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[65:66], v[79:80], v[85:86], 1.0
	v_cvt_i32_f64_e32 v85, v[73:74]
	v_fma_f64 v[73:74], v[81:82], v[87:88], 1.0
	v_cvt_i32_f64_e32 v81, v[77:78]
	v_trunc_f64_e32 v[77:78], v[63:64]
	v_fma_f64 v[79:80], v[83:84], v[89:90], 1.0
	v_ldexp_f64 v[65:66], v[65:66], v91
	v_ldexp_f64 v[61:62], v[73:74], v85
	v_trunc_f64_e32 v[73:74], v[53:54]
	v_cmp_neq_f64_e64 s10, v[77:78], v[63:64]
	v_fma_f64 v[69:70], v[83:84], v[79:80], 1.0
	v_cndmask_b32_e64 v59, 0x7ff00000, v66, s4
	v_cndmask_b32_e64 v62, 0x7ff00000, v62, s7
	v_cmp_neq_f64_e64 s9, v[73:74], v[53:54]
	v_trunc_f64_e32 v[53:54], v[3:4]
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v60, 0, v59, s5
	s_and_b32 s5, s8, s7
	v_cndmask_b32_e64 v59, 0, v65, s3
	v_cndmask_b32_e64 v51, 0, v61, s5
	v_cmp_nlt_f64_e64 s5, 0x40900000, v[75:76]
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[75:76]|
	v_cndmask_b32_e64 v52, 0, v62, s8
	v_fma_f64 v[22:23], v[59:60], v[22:23], v[59:60]
	v_cmp_class_f64_e64 s4, v[59:60], 0x204
	v_trunc_f64_e32 v[61:62], v[57:58]
	v_cmp_eq_f32_e64 s8, 0, v46
	v_fma_f64 v[47:48], v[51:52], v[47:48], v[51:52]
	v_cmp_class_f64_e64 s7, v[51:52], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v63, 0x7ff00000, 0, s8
	v_ldexp_f64 v[55:56], v[69:70], v81
	s_and_b32 s9, vcc_lo, s9
	v_cndmask_b32_e64 v64, 0, v1, s9
	v_cndmask_b32_e64 v65, 0x3ff00000, v1, s9
	s_and_b32 s9, s2, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v66, 0, v19, s9
	v_cndmask_b32_e64 v1, 0, v50, s3
	v_cndmask_b32_e64 v0, 0, v49, s3
	s_and_b32 s3, s6, s5
	v_cndmask_b32_e64 v67, 0x3ff00000, v19, s9
	v_cmp_eq_f64_e64 s9, v[53:54], v[3:4]
	v_cndmask_b32_e64 v4, v22, v59, s4
	v_cndmask_b32_e64 v22, v23, v60, s4
	v_cndmask_b32_e64 v23, v47, v51, s7
	v_cndmask_b32_e64 v47, v48, v52, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v22, 0x7fffffff, v22, v65
	v_cndmask_b32_e64 v52, 0, v23, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v49, 0x7ff80000, v22, vcc_lo
	v_cndmask_b32_e64 v56, 0x7ff00000, v56, s5
	v_cndmask_b32_e64 v18, 0, v55, s3
	v_cmp_neq_f64_e64 s3, v[61:62], v[57:58]
	v_cmp_eq_f32_e64 s5, 0, v45
	v_cndmask_b32_e64 v19, 0, v56, s6
	v_cmp_class_f64_e64 s6, v[20:21], 0x204
	v_bfi_b32 v20, 0x7fffffff, v47, v67
	v_bfi_b32 v47, 0x7fffffff, v63, v64
	v_cndmask_b32_e32 v50, 0, v4, vcc_lo
	v_fma_f64 v[0:1], v[18:19], v[0:1], v[18:19]
	v_cmp_class_f64_e64 s4, v[18:19], 0x204
	v_cmp_gt_f32_e32 vcc_lo, 0, v46
	v_cndmask_b32_e64 v48, 0x7ff00000, 0, s5
	v_cndmask_b32_e64 v51, 0x7ff80000, v20, s2
	v_cmp_gt_f32_e64 s2, 0, v45
	v_cndmask_b32_e32 v4, v4, v50, vcc_lo
	v_cndmask_b32_e32 v22, v22, v49, vcc_lo
	v_bfi_b32 v48, 0x7fffffff, v48, v66
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v52, s2
	v_cndmask_b32_e64 v20, v20, v51, s2
	s_or_b32 vcc_lo, s8, s80
	v_cmp_o_f32_e64 s2, v46, v46
	v_cndmask_b32_e32 v47, v22, v47, vcc_lo
	v_cndmask_b32_e64 v4, v4, 0, vcc_lo
	s_or_b32 vcc_lo, s5, s82
	v_cndmask_b32_e32 v20, v20, v48, vcc_lo
	v_cndmask_b32_e64 v46, v23, 0, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v45, v45
	v_cndmask_b32_e64 v22, 0, v4, s2
	v_cndmask_b32_e64 v23, 0x7ff80000, v47, s2
	v_cmp_gt_f32_e64 s2, 0, v2
	v_cndmask_b32_e32 v45, 0, v46, vcc_lo
	v_cndmask_b32_e32 v46, 0x7ff80000, v20, vcc_lo
	s_and_b32 vcc_lo, s9, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], v[45:46]
	v_cndmask_b32_e32 v20, 0x3ff00000, v21, vcc_lo
	v_cndmask_b32_e32 v4, 0, v21, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v1, v1, v19, s4
	v_cndmask_b32_e64 v0, v0, v18, s4
	v_cndmask_b32_e64 v18, 0x7ff00000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v1, 0x7fffffff, v1, v20
	v_cndmask_b32_e64 v20, 0, v0, s9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v4, 0x7fffffff, v18, v4
	v_cndmask_b32_e64 v19, 0x7ff80000, v1, s9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, v20, s2
	v_cndmask_b32_e64 v1, v1, v19, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, 0, vcc_lo
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cndmask_b32_e32 v1, 0x7ff80000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[22:23], v[0:1]
	v_add_nc_u32_e32 v22, v42, v30
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_cvt_f32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v4, 1, v1
	v_fma_f32 v18, -v2, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v4, v1, v0
	v_cmp_ge_f32_e64 s2, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s2
	v_cmp_lt_f32_e64 s2, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v4, s2
	v_mul_f32_e32 v2, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, v33, v33, v0
	v_div_scale_f32 v18, vcc_lo, v0, v33, v0
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v4, v2
	v_mul_f32_e32 v4, v18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v1, v4, v18
	v_fmac_f32_e32 v4, v19, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v4, v18
	v_div_fmas_f32 v1, v1, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v33, v0
	v_mul_f32_e32 v1, 0x3fb8aa3b, v0
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0x3fb8aa3b, v0, -v1
	v_rndne_f32_e32 v4, v1
	v_fmac_f32_e32 v2, 0x32a5705f, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	v_cvt_i32_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v2
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
	v_add_co_u32 v47, vcc_lo, s28, v22
	v_add_co_ci_u32_e32 v48, vcc_lo, s29, v23, vcc_lo
	v_cvt_f64_f32_e32 v[0:1], v0
	global_store_b32 v[47:48], v44, off
	global_load_b32 v2, v[11:12], off
	v_div_scale_f64 v[18:19], null, v[0:1], v[0:1], s[78:79]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[20:21], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[45:46], -v[18:19], v[20:21], 1.0
	v_fma_f64 v[20:21], v[20:21], v[45:46], v[20:21]
	v_div_scale_f64 v[46:47], vcc_lo, s[78:79], v[0:1], s[78:79]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[18:19], v[20:21], 1.0
	v_fma_f64 v[20:21], v[20:21], v[44:45], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[44:45], v[46:47], v[20:21]
	v_fma_f64 v[18:19], -v[18:19], v[44:45], v[46:47]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v42, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[44:45]
	v_div_fixup_f64 v[0:1], v[18:19], v[0:1], s[78:79]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v4, v[0:1]
	v_add_co_u32 v0, vcc_lo, s30, v22
	v_add_co_ci_u32_e32 v1, vcc_lo, s31, v23, vcc_lo
	global_store_b32 v[0:1], v4, off
	global_store_b32 v[11:12], v42, off
.LBB2_38:                               ; %Flow
                                        ;   in Loop: Header=BB2_34 Depth=4
	s_or_b32 exec_lo, exec_lo, s97
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s2, s96, exec_lo
.LBB2_39:                               ; %Flow376
                                        ;   in Loop: Header=BB2_34 Depth=4
	s_or_b32 exec_lo, exec_lo, s95
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s93, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s93, s3, s2
.LBB2_40:                               ;   in Loop: Header=BB2_34 Depth=4
	s_or_b32 exec_lo, exec_lo, s94
	v_cmp_ge_i32_e32 vcc_lo, s92, v43
	s_xor_b32 s2, s93, -1
	s_add_i32 s92, s92, 1
	s_or_b32 s2, s2, vcc_lo
	v_add_co_u32 v16, vcc_lo, v16, 4
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	s_and_b32 s2, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s91, s2, s91
	s_and_not1_b32 exec_lo, exec_lo, s91
	s_cbranch_execnz .LBB2_34
; %bb.41:                               ; %Flow377
                                        ;   in Loop: Header=BB2_31 Depth=3
	s_or_b32 exec_lo, exec_lo, s91
.LBB2_42:                               ; %Flow378
                                        ;   in Loop: Header=BB2_31 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s90
	v_add_nc_u32_e32 v0, 1, v41
	v_cmp_ge_i32_e32 vcc_lo, v41, v32
	v_add_nc_u32_e32 v15, s21, v15
	s_and_not1_b32 s2, s88, exec_lo
	v_mov_b32_e32 v41, v0
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s88, s2, s3
.LBB2_43:                               ; %Flow379
                                        ;   in Loop: Header=BB2_31 Depth=3
	s_or_b32 exec_lo, exec_lo, s89
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s88
	s_or_b32 s87, s2, s87
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s87
	s_cbranch_execnz .LBB2_31
.LBB2_44:                               ; %Flow381
                                        ;   in Loop: Header=BB2_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s86
	v_add_nc_u32_e32 v0, 1, v39
	v_cmp_ge_i32_e32 vcc_lo, v39, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v39, v0 :: v_dual_add_nc_u32 v38, s33, v38
	s_or_b32 s85, vcc_lo, s85
	s_and_not1_b32 exec_lo, exec_lo, s85
	s_cbranch_execnz .LBB2_29
.LBB2_45:                               ; %Flow383
                                        ;   in Loop: Header=BB2_27 Depth=1
	s_or_b32 exec_lo, exec_lo, s84
	v_add_nc_u32_e32 v0, 1, v26
	v_cmp_ge_i32_e32 vcc_lo, v26, v25
	v_add_nc_u32_e32 v36, s20, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v26, v0
	s_or_b32 s18, vcc_lo, s18
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB2_27
.LBB2_46:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 99
		.amdhsa_next_free_sgpr 98
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf, .Lfunc_end2-_Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 12572
; NumSgprs: 100
; NumVgprs: 99
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 12
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 100
; NumVGPRsForWavesPerEU: 99
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_ ; -- Begin function _Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.globl	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
	.p2align	8
	.type	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_,@function
_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_: ; @_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s17, s16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_9
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v6, s19, v0
	v_cmp_lt_i32_e32 vcc_lo, 0, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_9
; %bb.2:                                ; %.preheader47.preheader
	s_load_b64 s[0:1], s[0:1], 0x30
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v0, v6
.LBB3_3:                                ; %.preheader47
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_nc_u32 v0, -1, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_3
; %bb.4:                                ; %.lr.ph52
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_lo_u32 v2, v1, s18
	v_mul_lo_u32 v8, v1, s19
	s_cmp_gt_i32 s18, 0
	s_mov_b32 s3, 0
	s_cselect_b32 s2, -1, 0
	s_mov_b32 s6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
.LBB3_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_7 Depth 2
	v_add_nc_u32_e32 v2, s6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v9, v[4:5], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v10, null, v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	v_div_scale_f32 v12, vcc_lo, v9, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v12, v11
	v_fma_f32 v14, -v10, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v14, v11
	v_fma_f32 v10, -v10, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v11, v13
	s_and_not1_b32 vcc_lo, exec_lo, s2
	v_div_fixup_f32 v9, v10, v7, v9
	global_store_b32 v[4:5], v9, off
	s_cbranch_vccnz .LBB3_8
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_5 Depth=1
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_mov_b32 s7, s18
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB3_7:                                ;   Parent Loop BB3_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v10, v[2:3], off
	global_load_b32 v11, v[4:5], off
	s_add_i32 s7, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v11, v9, v10
	global_store_b32 v[4:5], v11, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_cbranch_scc0 .LBB3_7
.LBB3_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s6, v6
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_5
.LBB3_9:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_, .Lfunc_end3-_Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 600
; NumSgprs: 22
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22output_init_gpu_kerneliiiifPfPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22output_init_gpu_kerneliiiifPfPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .value_kind:     global_buffer
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        .size:           4
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        .size:           4
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
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        .size:           2
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
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      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
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        .value_kind:     hidden_global_offset_z
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        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z27grid_buffer_init_gpu_kerneliifiiiiPKfPiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .group_segment_fixed_size: 0
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    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z31roi_pooling_register_gpu_kerneliiiififffiiiPKfS0_PKiPiS3_S3_S3_S3_S3_Pf
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
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    .uses_dynamic_stack: false
    .vgpr_count:     99
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .language_version:
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    .name:           _Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z27roi_pooling_fill_gpu_kerneliiiiPKfPiPfS1_S2_.kd
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    .vgpr_count:     15
    .vgpr_spill_count: 0
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    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
