#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__ void convolution_1D(float *N , float *M , float *P , int Mask_width,int width)
{
	int i = blockIdx.x*blockDim.x + threadIdx.x;
	float pvalue = 0.0;
	int N_start_point = i - ((Mask_width)/2);
	for(int j =0;j<Mask_width;j++)
	{
		if(((N_start_point+j)>=0)&& ((N_start_point + j)<width))
		{
			pvalue  += N[N_start_point + j] * M[j];
		}
	}
	P[i] = pvalue;
}

int main()
{
	float *a , *m , *t;
	float *d_a, *d_m, *d_t;
	int width , mask_width;
	printf("Enter the size of array \n");
	scanf("%d",&width);
	a = (float*)malloc(sizeof(float)*width);
	t = (float*)malloc(sizeof(float)*width);
	printf("Enter the array \n");
	int i = 0;
	for(i = 0;i<width;i++)
	{
		scanf("%f",&a[i]);
	}
	printf("Enter the size of mask \n");
	scanf("%d",&mask_width);
	m = (float*)malloc(sizeof(float)*mask_width);
	printf("Enter the mask \n");
	for(i = 0;i<mask_width;i++)
	{
		scanf("%f",&m[i]);
	}
	int size1 = sizeof(float)*width;
	int size2 = sizeof(float)*mask_width;
	cudaMalloc((void**)&d_a,size1);
	cudaMalloc((void**)&d_m,size2);
	cudaMalloc((void**)&d_t,size1);
	cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
	cudaMemcpy(d_m,m,size2,cudaMemcpyHostToDevice);
	dim3 dimGrid((width-1)/mask_width + 1,1,1);
	dim3 dimBlock(mask_width,1,1);
	convolution_1D<<<dimGrid,dimBlock>>>(d_a,d_m,d_t,mask_width,width);
	cudaMemcpy(t,d_t,size1,cudaMemcpyDeviceToHost);
	printf("The result array is \n");
	for(int i = 0;i<width;i++)
	{
		printf("%f ",t[i]);
	}
	printf("\n");
	cudaFree(d_a);
	cudaFree(d_m);
	cudaFree(d_t);


}
	.file	"tmpxft_00385287_00000000-6_conv1d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii
	.type	_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii, @function
_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14convolution_1DPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii, .-_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii
	.globl	_Z14convolution_1DPfS_S_ii
	.type	_Z14convolution_1DPfS_S_ii, @function
_Z14convolution_1DPfS_S_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2053:
	.size	_Z14convolution_1DPfS_S_ii, .-_Z14convolution_1DPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter the size of array \n"
.LC1:
	.string	"%d"
.LC2:
	.string	"Enter the array \n"
.LC3:
	.string	"%f"
.LC4:
	.string	"Enter the size of mask \n"
.LC5:
	.string	"Enter the mask \n"
.LC6:
	.string	"The result array is \n"
.LC7:
	.string	"%f "
.LC8:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	leaq	.LC3(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC1(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rsp, %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	(%rsp), %rbx
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	xorl	%ebx, %ebx
	movq	%rax, %r14
	call	malloc@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%r14, %r13
	movq	%rax, %r12
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L9:
	cmpl	%ebx, (%rsp)
	jle	.L18
	movq	%r13, %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	incl	%ebx
	call	__isoc23_scanf@PLT
	addq	$4, %r13
	jmp	.L9
.L18:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	4(%rsp), %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	4(%rsp), %rdi
	salq	$2, %rdi
	call	malloc@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %r13
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r13, %r15
.L11:
	movl	4(%rsp), %ebp
	cmpl	%ebx, %ebp
	jle	.L19
	movq	%r15, %rsi
	leaq	.LC3(%rip), %rdi
	xorl	%eax, %eax
	incl	%ebx
	call	__isoc23_scanf@PLT
	addq	$4, %r15
	jmp	.L11
.L19:
	movl	(%rsp), %eax
	sall	$2, %ebp
	leaq	8(%rsp), %rdi
	movslq	%ebp, %rbp
	leal	0(,%rax,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	(%rsp), %eax
	movl	4(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	decl	%eax
	movl	%ecx, 44(%rsp)
	cltd
	idivl	%ecx
	incl	%eax
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movq	%rax, 48(%rsp)
	movl	40(%rsp), %esi
	movl	52(%rsp), %ecx
	movq	44(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movl	(%rsp), %r8d
	movl	4(%rsp), %ecx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z40__device_stub__Z14convolution_1DPfS_S_iiPfS_S_ii
.L13:
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%ebx, %ebx
	leaq	.LC7(%rip), %rbp
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L14:
	cmpl	%ebx, (%rsp)
	jle	.L20
	movq	%rbp, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%r12,%rbx,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L14
.L20:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z14convolution_1DPfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14convolution_1DPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__ void convolution_1D(float *N , float *M , float *P , int Mask_width,int width)
{
	int i = blockIdx.x*blockDim.x + threadIdx.x;
	float pvalue = 0.0;
	int N_start_point = i - ((Mask_width)/2);
	for(int j =0;j<Mask_width;j++)
	{
		if(((N_start_point+j)>=0)&& ((N_start_point + j)<width))
		{
			pvalue  += N[N_start_point + j] * M[j];
		}
	}
	P[i] = pvalue;
}

int main()
{
	float *a , *m , *t;
	float *d_a, *d_m, *d_t;
	int width , mask_width;
	printf("Enter the size of array \n");
	scanf("%d",&width);
	a = (float*)malloc(sizeof(float)*width);
	t = (float*)malloc(sizeof(float)*width);
	printf("Enter the array \n");
	int i = 0;
	for(i = 0;i<width;i++)
	{
		scanf("%f",&a[i]);
	}
	printf("Enter the size of mask \n");
	scanf("%d",&mask_width);
	m = (float*)malloc(sizeof(float)*mask_width);
	printf("Enter the mask \n");
	for(i = 0;i<mask_width;i++)
	{
		scanf("%f",&m[i]);
	}
	int size1 = sizeof(float)*width;
	int size2 = sizeof(float)*mask_width;
	hipMalloc((void**)&d_a,size1);
	hipMalloc((void**)&d_m,size2);
	hipMalloc((void**)&d_t,size1);
	hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
	hipMemcpy(d_m,m,size2,hipMemcpyHostToDevice);
	dim3 dimGrid((width-1)/mask_width + 1,1,1);
	dim3 dimBlock(mask_width,1,1);
	convolution_1D<<<dimGrid,dimBlock>>>(d_a,d_m,d_t,mask_width,width);
	hipMemcpy(t,d_t,size1,hipMemcpyDeviceToHost);
	printf("The result array is \n");
	for(int i = 0;i<width;i++)
	{
		printf("%f ",t[i]);
	}
	printf("\n");
	hipFree(d_a);
	hipFree(d_m);
	hipFree(d_t);


}
	.text
	.file	"conv1d.hip"
	.globl	_Z29__device_stub__convolution_1DPfS_S_ii # -- Begin function _Z29__device_stub__convolution_1DPfS_S_ii
	.type	_Z29__device_stub__convolution_1DPfS_S_ii,@function
_Z29__device_stub__convolution_1DPfS_S_ii: # @_Z29__device_stub__convolution_1DPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14convolution_1DPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__convolution_1DPfS_S_ii, .Lfunc_end0-_Z29__device_stub__convolution_1DPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	%rsp, %r15
	movl	$.L.str.1, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%r15), %rbx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %rbx
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	cmpl	$0, (%r15)
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movq	%r12, %r15
	xorl	%r14d, %r14d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.3, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r14
	movslq	(%rsp), %rax
	addq	$4, %r15
	cmpq	%rax, %r14
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movq	%r12, 32(%rsp)                  # 8-byte Spill
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	leaq	4(%rsp), %r15
	movl	$.L.str.1, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%r15), %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %r12
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	(%r15), %r14d
	testl	%r14d, %r14d
	jle	.LBB1_6
# %bb.4:                                # %.lr.ph38.preheader
	movq	%r12, %r15
	xorl	%r13d, %r13d
.LBB1_5:                                # %.lr.ph38
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.3, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r13
	movslq	4(%rsp), %r14
	addq	$4, %r15
	cmpq	%r14, %r13
	jl	.LBB1_5
.LBB1_6:                                # %._crit_edge39
	movl	(%rsp), %eax
	shll	$2, %eax
	shll	$2, %r14d
	movslq	%eax, %r15
	leaq	24(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movslq	%r14d, %rbp
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	%r12, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	(%rsp), %eax
	decl	%eax
	movl	4(%rsp), %ecx
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	leal	1(%rax), %edi
	btsq	$32, %rdi
	btsq	$32, %rcx
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx
	movl	(%rsp), %r8d
	callq	_Z29__device_stub__convolution_1DPfS_S_ii
.LBB1_8:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	cmpl	$0, (%rsp)
	jle	.LBB1_11
# %bb.9:                                # %.lr.ph42.preheader
	xorl	%r14d, %r14d
.LBB1_10:                               # %.lr.ph42
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r14,4), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	movslq	(%rsp), %rax
	cmpq	%rax, %r14
	jl	.LBB1_10
.LBB1_11:                               # %._crit_edge43
	movl	$10, %edi
	callq	putchar@PLT
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14convolution_1DPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14convolution_1DPfS_S_ii,@object # @_Z14convolution_1DPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z14convolution_1DPfS_S_ii
	.p2align	3, 0x0
_Z14convolution_1DPfS_S_ii:
	.quad	_Z29__device_stub__convolution_1DPfS_S_ii
	.size	_Z14convolution_1DPfS_S_ii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%f"
	.size	.L.str.3, 3

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%f "
	.size	.L.str.7, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14convolution_1DPfS_S_ii"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Enter the size of array "
	.size	.Lstr, 25

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Enter the array "
	.size	.Lstr.1, 17

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Enter the size of mask "
	.size	.Lstr.2, 24

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Enter the mask "
	.size	.Lstr.3, 16

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"The result array is "
	.size	.Lstr.4, 21

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__convolution_1DPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14convolution_1DPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14convolution_1DPfS_S_ii ; -- Begin function _Z14convolution_1DPfS_S_ii
	.globl	_Z14convolution_1DPfS_S_ii
	.p2align	8
	.type	_Z14convolution_1DPfS_S_ii,@function
_Z14convolution_1DPfS_S_ii:             ; @_Z14convolution_1DPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_cmp_lt_i32 s10, 1
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s10, 31
	v_mov_b32_e32 v3, 0
	s_add_i32 s0, s10, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s0, s0, 1
	v_mov_b32_e32 v0, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_subrev_nc_u32_e32 v2, s0, v1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s11, v2
	s_and_b32 s1, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_load_b32 s1, s[6:7], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s1, v4
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s10, s10, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_6
.LBB0_5:
	v_mov_b32_e32 v0, 0
.LBB0_6:                                ; %Flow42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14convolution_1DPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14convolution_1DPfS_S_ii, .Lfunc_end0-_Z14convolution_1DPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14convolution_1DPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14convolution_1DPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
