#include "includes.h"
__global__ void SolveSmoothMedianGlobalKernel3(float* u, float* v, float* bku, float* bkv, int width, int height, int stride, float *outputu, float *outputv, float *outputbku, float* outputbkv)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * blockDim.y;

const int pos = ix + iy * stride;

if (ix >= width || iy >= height) return;

float mu[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };

float mv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };

for (int j = 0; j < 3; j++) {
for (int i = 0; i < 3; i++) {
//get values
int col = (ix + i - 1);
int row = (iy + j - 1);
int index = j * 3 + i;
if ((col >= 0) && (col < width) && (row >= 0) && (row < height)) {
mu[index] = u[col + stride*row];
mv[index] = v[col + stride*row];
}
else if ((col < 0) && (row >= 0) && (row < height)) {
mu[index] = u[stride*row];
mv[index] = v[stride*row];
}
else if ((col > width) && (row >= 0) && (row < height)) {
mu[index] = u[width - 1 + stride*row];
mv[index] = v[width - 1 + stride*row];
}
else if ((col >= 0) && (col < width) && (row < 0)) {
mu[index] = u[col];
mv[index] = v[col];
}
else if ((col >= 0) && (col < width) && (row > height)) {
mu[index] = u[col + stride*(height - 1)];
mv[index] = v[col + stride*(height - 1)];
}
//solve gaussian
}
}

float tmpu, tmpv;
for (int j = 0; j < 9; j++) {
for (int i = j + 1; i < 9; i++) {
if (mu[j] > mu[i]) {
//Swap the variables.
tmpu = mu[j];
mu[j] = mu[i];
mu[i] = tmpu;
}
if (mv[j] > mv[i]) {
//Swap the variables.
tmpv = mv[j];
mv[j] = mv[i];
mv[i] = tmpv;
}
}
}

outputu[pos] = mu[4];
outputv[pos] = mv[4];
outputbku[pos] = bku[pos] + u[pos] - mu[4];
outputbkv[pos] = bkv[pos] + v[pos] - mv[4];
}
	.file	"tmpxft_003b7a2b_00000000-6_SolveSmoothMedianGlobalKernel3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z67__device_stub__Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_PfS_S_S_iiiS_S_S_S_
	.type	_Z67__device_stub__Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_PfS_S_S_iiiS_S_S_S_, @function
_Z67__device_stub__Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_PfS_S_S_iiiS_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	264(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	272(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	280(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	288(%rsp), %rax
	movl	%r8d, 44(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z67__device_stub__Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_PfS_S_S_iiiS_S_S_S_, .-_Z67__device_stub__Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_PfS_S_S_iiiS_S_S_S_
	.globl	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.type	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, @function
_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_PfS_S_S_iiiS_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, .-_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SolveSmoothMedianGlobalKernel3(float* u, float* v, float* bku, float* bkv, int width, int height, int stride, float *outputu, float *outputv, float *outputbku, float* outputbkv)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * blockDim.y;

const int pos = ix + iy * stride;

if (ix >= width || iy >= height) return;

float mu[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };

float mv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };

for (int j = 0; j < 3; j++) {
for (int i = 0; i < 3; i++) {
//get values
int col = (ix + i - 1);
int row = (iy + j - 1);
int index = j * 3 + i;
if ((col >= 0) && (col < width) && (row >= 0) && (row < height)) {
mu[index] = u[col + stride*row];
mv[index] = v[col + stride*row];
}
else if ((col < 0) && (row >= 0) && (row < height)) {
mu[index] = u[stride*row];
mv[index] = v[stride*row];
}
else if ((col > width) && (row >= 0) && (row < height)) {
mu[index] = u[width - 1 + stride*row];
mv[index] = v[width - 1 + stride*row];
}
else if ((col >= 0) && (col < width) && (row < 0)) {
mu[index] = u[col];
mv[index] = v[col];
}
else if ((col >= 0) && (col < width) && (row > height)) {
mu[index] = u[col + stride*(height - 1)];
mv[index] = v[col + stride*(height - 1)];
}
//solve gaussian
}
}

float tmpu, tmpv;
for (int j = 0; j < 9; j++) {
for (int i = j + 1; i < 9; i++) {
if (mu[j] > mu[i]) {
//Swap the variables.
tmpu = mu[j];
mu[j] = mu[i];
mu[i] = tmpu;
}
if (mv[j] > mv[i]) {
//Swap the variables.
tmpv = mv[j];
mv[j] = mv[i];
mv[i] = tmpv;
}
}
}

outputu[pos] = mu[4];
outputv[pos] = mv[4];
outputbku[pos] = bku[pos] + u[pos] - mu[4];
outputbkv[pos] = bkv[pos] + v[pos] - mv[4];
}
	.text
	.file	"SolveSmoothMedianGlobalKernel3.hip"
	.globl	_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_ # -- Begin function _Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.type	_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_,@function
_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_: # @_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, .Lfunc_end0-_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_,@object # @_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.p2align	3, 0x0
_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_:
	.quad	_Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.size	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_"
	.size	.L__unnamed_1, 54

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z45__device_stub__SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_ ; -- Begin function _Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.globl	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
	.p2align	8
	.type	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_,@function
_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_: ; @_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b128 s[24:27], s[0:1], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[28:29], null, s15, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s24, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s25, v28
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_25
; %bb.1:                                ; %.preheader186.preheader
	s_load_b256 s[16:23], s[0:1], 0x0
	s_mov_b32 s5, 0
	v_mov_b32_e32 v30, 0
	s_mov_b32 s12, s5
	s_mov_b32 s4, s5
	s_mov_b32 s6, s5
	s_mov_b32 s7, s5
	s_mov_b32 s8, s5
	s_mov_b32 s9, s5
	s_mov_b32 s10, s5
	s_mov_b32 s11, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v16, s11
	v_mov_b32_e32 v9, s4
	v_dual_mov_b32 v15, s10 :: v_dual_mov_b32 v14, s9
	v_dual_mov_b32 v13, s8 :: v_dual_mov_b32 v12, s7
	v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v10, s5
	v_mov_b32_e32 v0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v4, v13 :: v_dual_mov_b32 v5, v14
	v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v1, v10 :: v_dual_mov_b32 v6, v15
	v_dual_mov_b32 v7, v16 :: v_dual_mov_b32 v8, v17
	s_mov_b64 s[6:7], 0
	s_mov_b32 s12, 0
.LBB0_2:                                ; %.preheader186
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v20, s12, v28
	s_mul_i32 s14, s12, 3
	s_mov_b64 s[8:9], 0
	v_add_nc_u32_e32 v18, -1, v20
	v_cmp_gt_i32_e64 s13, 1, v20
	v_cmp_lt_i32_e32 vcc_lo, s25, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v18, s26
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v31, s2, s16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v32, s2, s17, v19, s2
	v_add_co_u32 v33, s2, s18, v18
	v_add_co_ci_u32_e64 v34, s2, s19, v19, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v40, s2, v31, -4
	v_add_co_ci_u32_e64 v41, s2, -1, v32, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v42, s2, v33, -4
	v_add_co_ci_u32_e64 v43, s2, -1, v34, s2
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_co_u32 v35, null, v27, s8
	s_mov_b32 s15, 0
	s_mov_b32 s3, s13
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26
                                        ; implicit-def: $sgpr10_sgpr11
                                        ; implicit-def: $vgpr36_vgpr37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s4, 1, v35
	v_cmp_lt_i32_e64 s2, 0, v35
	s_and_saveexec_b32 s27, s2
	s_cbranch_execz .LBB0_7
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_cmp_lt_i32_e64 s3, s24, v35
	s_mov_b32 s29, -1
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26
                                        ; implicit-def: $sgpr10_sgpr11
                                        ; implicit-def: $vgpr36_vgpr37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, s13
	s_or_b32 s3, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, -1
	s_and_saveexec_b32 s28, s3
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	v_ashrrev_i32_e32 v36, 31, v35
	s_add_u32 s10, s6, s8
	s_mov_b32 s15, exec_lo
	s_mov_b32 m0, s10
	s_addc_u32 s11, s7, s9
	v_lshlrev_b64 v[36:37], 2, v[35:36]
	s_xor_b32 s29, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s3, v40, v36
	v_add_co_ci_u32_e64 v19, s3, v41, v37, s3
	v_add_co_u32 v36, s3, v42, v36
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v37, s3, v43, v37, s3
	global_load_b32 v29, v[18:19], off
	v_dual_mov_b32 v26, v17 :: v_dual_mov_b32 v25, v16
	v_mov_b32_e32 v18, v9
	v_dual_mov_b32 v24, v15 :: v_dual_mov_b32 v23, v14
	v_dual_mov_b32 v22, v13 :: v_dual_mov_b32 v21, v12
	v_dual_mov_b32 v20, v11 :: v_dual_mov_b32 v19, v10
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v18, v29
.LBB0_6:                                ; %Flow259
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s28, s29, exec_lo
	s_or_b32 s3, s13, exec_lo
	s_and_b32 s15, s15, exec_lo
	s_or_b32 s4, s4, s28
.LBB0_7:                                ; %Flow258
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	v_dual_mov_b32 v39, s11 :: v_dual_mov_b32 v38, s10
	s_and_saveexec_b32 s10, s4
	s_cbranch_execz .LBB0_15
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 s3, s3, vcc_lo
	s_add_i32 s4, s8, s14
	s_xor_b32 s3, s3, -1
	s_mov_b32 s11, s15
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26
	s_and_saveexec_b32 s27, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s27
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v18, v[31:32], off
	s_add_i32 s11, s6, s8
                                        ; implicit-def: $vgpr35
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s11
	s_or_b32 s11, s15, exec_lo
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v9, v18
	v_dual_mov_b32 v26, v17 :: v_dual_mov_b32 v25, v16
	v_dual_mov_b32 v24, v15 :: v_dual_mov_b32 v23, v14
	v_dual_mov_b32 v22, v13 :: v_dual_mov_b32 v21, v12
	v_dual_mov_b32 v20, v11 :: v_dual_mov_b32 v19, v10
	v_mov_b32_e32 v18, v9
                                        ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17
.LBB0_10:                               ; %Flow261
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_saveexec_b32 s27, s3
	v_dual_mov_b32 v39, s5 :: v_dual_mov_b32 v38, s4
	v_dual_mov_b32 v37, v34 :: v_dual_mov_b32 v36, v33
	s_xor_b32 exec_lo, exec_lo, s27
	s_cbranch_execz .LBB0_14
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=2
	v_cmp_ge_i32_e64 s3, s24, v35
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26
                                        ; implicit-def: $vgpr36_vgpr37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_b32 s28, s2, s13
	s_mov_b32 s2, s11
	s_and_saveexec_b32 s3, s28
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_3 Depth=2
	v_add_nc_u32_e32 v29, -1, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[36:37], 2, v[29:30]
	v_add_co_u32 v18, s2, s16, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v19, s2, s17, v37, s2
	s_add_i32 s2, s6, s8
	s_mov_b32 m0, s2
	global_load_b32 v18, v[18:19], off
	v_add_co_u32 v36, s2, s18, v36
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v37, s2, s19, v37, s2
	s_or_b32 s2, s11, exec_lo
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v9, v18
	v_dual_mov_b32 v26, v17 :: v_dual_mov_b32 v25, v16
	v_dual_mov_b32 v24, v15 :: v_dual_mov_b32 v23, v14
	v_dual_mov_b32 v22, v13 :: v_dual_mov_b32 v21, v12
	v_dual_mov_b32 v20, v11 :: v_dual_mov_b32 v19, v10
	v_mov_b32_e32 v18, v9
                                        ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17
.LBB0_13:                               ; %Flow263
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v39, s5 :: v_dual_mov_b32 v38, s4
	s_and_not1_b32 s3, s11, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s3, s2
.LBB0_14:                               ; %Flow262
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s15, exec_lo
	s_and_b32 s3, s11, exec_lo
	s_or_b32 s15, s2, s3
.LBB0_15:                               ; %Flow260
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s3, s15
	s_cbranch_execz .LBB0_17
; %bb.16:                               ; %.critedge.sink.split
                                        ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v29, v[36:37], off
	v_cmp_eq_u32_e64 s2, 8, v38
	v_dual_mov_b32 v9, v18 :: v_dual_mov_b32 v10, v19
	v_dual_mov_b32 v11, v20 :: v_dual_mov_b32 v12, v21
	v_dual_mov_b32 v13, v22 :: v_dual_mov_b32 v14, v23
	v_dual_mov_b32 v15, v24 :: v_dual_mov_b32 v16, v25
	v_mov_b32_e32 v17, v26
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v8, v8, v29, s2
	v_cmp_eq_u32_e64 s2, 7, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v29, s2
	v_cmp_eq_u32_e64 s2, 6, v38
	v_cndmask_b32_e64 v6, v6, v29, s2
	v_cmp_eq_u32_e64 s2, 5, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v29, s2
	v_cmp_eq_u32_e64 s2, 4, v38
	v_cndmask_b32_e64 v4, v4, v29, s2
	v_cmp_eq_u32_e64 s2, 3, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v29, s2
	v_cmp_eq_u32_e64 s2, 2, v38
	v_cndmask_b32_e64 v2, v2, v29, s2
	v_cmp_eq_u32_e64 s2, 1, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v29, s2
	v_cmp_eq_u32_e64 s2, 0, v38
	v_cndmask_b32_e64 v0, v0, v29, s2
.LBB0_17:                               ; %.critedge
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s8, 3
	s_cbranch_scc0 .LBB0_3
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s12, s12, 1
	s_add_u32 s6, s6, 3
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s12, 3
	s_cbranch_scc1 .LBB0_2
; %bb.19:                               ; %.preheader.preheader
	s_mov_b32 s6, 0
	s_mov_b64 s[2:3], 1
.LBB0_20:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_22 Depth 2
	s_cmp_gt_u32 s6, 7
	s_cbranch_scc1 .LBB0_23
; %bb.21:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b64 s[4:5], s[2:3]
.LBB0_22:                               ;   Parent Loop BB0_20 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 m0, s6
	v_dual_mov_b32 v26, v17 :: v_dual_mov_b32 v25, v16
	v_movrels_b32_e32 v38, v9
	s_mov_b32 m0, s4
	v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v37, v8
	v_movrels_b32_e32 v39, v9
	s_mov_b32 m0, s6
	v_dual_mov_b32 v24, v15 :: v_dual_mov_b32 v23, v14
	v_dual_mov_b32 v22, v13 :: v_dual_mov_b32 v21, v12
	v_dual_mov_b32 v20, v11 :: v_dual_mov_b32 v19, v10
	v_movreld_b32_e32 v18, v39
	s_mov_b32 m0, s4
	v_cmp_gt_f32_e32 vcc_lo, v38, v39
	v_movreld_b32_e32 v18, v38
	s_mov_b32 m0, s6
	v_dual_mov_b32 v30, v1 :: v_dual_mov_b32 v29, v0
	v_movrels_b32_e32 v38, v0
	s_mov_b32 m0, s4
	v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v6
	v_movrels_b32_e32 v39, v0
	s_mov_b32 m0, s6
	v_dual_mov_b32 v34, v5 :: v_dual_mov_b32 v33, v4
	v_dual_mov_b32 v32, v3 :: v_dual_mov_b32 v31, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_movreld_b32_e32 v29, v39
	s_mov_b32 m0, s4
	v_dual_cndmask_b32 v17, v17, v26 :: v_dual_cndmask_b32 v16, v16, v25
	v_dual_cndmask_b32 v15, v15, v24 :: v_dual_cndmask_b32 v14, v14, v23
	v_dual_cndmask_b32 v13, v13, v22 :: v_dual_cndmask_b32 v12, v12, v21
	v_dual_cndmask_b32 v11, v11, v20 :: v_dual_cndmask_b32 v10, v10, v19
	v_movreld_b32_e32 v29, v38
	v_cndmask_b32_e32 v9, v9, v18, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v38, v39
	s_add_u32 s8, s4, 1
	s_addc_u32 s9, s5, 0
	s_cmp_gt_u32 s4, 7
	s_mov_b64 s[4:5], s[8:9]
	v_dual_cndmask_b32 v8, v8, v37 :: v_dual_cndmask_b32 v7, v7, v36
	v_dual_cndmask_b32 v6, v6, v35 :: v_dual_cndmask_b32 v5, v5, v34
	v_dual_cndmask_b32 v4, v4, v33 :: v_dual_cndmask_b32 v3, v3, v32
	v_dual_cndmask_b32 v2, v2, v31 :: v_dual_cndmask_b32 v1, v1, v30
	v_cndmask_b32_e32 v0, v0, v29, vcc_lo
	s_cbranch_scc0 .LBB0_22
.LBB0_23:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_add_i32 s6, s6, 1
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s6, 9
	s_cbranch_scc1 .LBB0_20
; %bb.24:
	v_mad_u64_u32 v[0:1], null, v28, s26, v[27:28]
	s_load_b256 s[0:7], s[0:1], 0x30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v1, vcc_lo
	global_store_b32 v[5:6], v13, off
	global_store_b32 v[7:8], v4, off
	global_load_b32 v5, v[2:3], off
	global_load_b32 v6, v[9:10], off
	v_add_co_u32 v2, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v5, v6
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v9, v7, v13
	v_add_co_u32 v7, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v1, vcc_lo
	global_store_b32 v[5:6], v9, off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[7:8], off
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v4
	global_store_b32 v[0:1], v2, off
.LBB0_25:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 44
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_, .Lfunc_end0-_Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1752
; NumSgprs: 32
; NumVgprs: 44
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 44
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z30SolveSmoothMedianGlobalKernel3PfS_S_S_iiiS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     44
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
