/**
 File name: bfs_gpu_status_array_flag.cu
 Author: Yuede Ji
 Last update: 13:30 10-10-2015
 Description: Using status array to implent GPU version of bfs.
    Calculate the shortest distance from 0 to others
**/

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

//Using arrays to implement queue
char filein[] = "/home/yuede/dataset/kron_16_16.dat";// no need
char fileout[] = "/home/yuede/dataset/kron_16_16.gpu.as.flag.result";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
/**
char filein[] = "/home/yuede/dataset/kron_10_4.dat";// no need
char fileout[] = "/home/yuede/dataset/kron_10_4.gpu.as.result";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
**/

const int v_num = 65535;
const int e_num = 2097152;
const int INF = 0x7FFFFFFF;
const int threads_num = 256;

int beg_pos[v_num+1];
int csr[e_num];
int sa[v_num];
//load from .dat files, and store in array csr[N*N], beg_pos[N]

int csr_begin(int v, int e);
void bfs_sa(int root, int v, int e);
__global__ void traverse_one(int level, int * dev_sa, int * dev_beg_pos, int * dev_csr)
{
    int id = threadIdx.x + blockIdx.x * blockDim.x;
    if(dev_sa[id] == level)///node i belongs to current level
    {
        //int j = dev_beg_pos[id];
        for(int j=dev_beg_pos[id]; j<dev_beg_pos[id+1]; ++j)
        {
            if(dev_sa[dev_csr[j]] > level + 1)
            { 
                dev_sa[dev_csr[j]] = level + 1;
                printf("%d\n", dev_csr[j]);
            }
        }                    
    }
}

int main()
{
    csr_begin(v_num, e_num);

    bfs_sa(0, v_num, e_num);

    FILE * fp_out = fopen(fileout, "w");

    for(int i=0; i<v_num; ++i)
        fprintf(fp_out, "%d\n", sa[i]);
    fclose(fp_out);
    
    return 0;
}
void bfs_sa(int root, int v, int e)
{
    for(int i=0; i<v; ++i)
        sa[i] = INF;
    int level = 0;
    sa[0] = 0;
    bool flag = true; //flag whether current level has nodes
    
    int *dev_sa;
    int *dev_beg_pos;
    int *dev_csr;

    cudaMalloc( (void **) &dev_sa, v*sizeof(int));
    cudaMalloc( (void **) &dev_beg_pos, (v+1)*sizeof(int));
    cudaMalloc( (void **) &dev_csr, e*sizeof(int));

    cudaMemcpy(dev_sa, sa, v*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(dev_beg_pos, beg_pos, (v+1)*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(dev_csr, csr, e*sizeof(int), cudaMemcpyHostToDevice);
    
    while(flag)
    {
        flag = false;
        traverse_one<<<threads_num, threads_num>>>(level, dev_sa, dev_beg_pos, dev_csr);
        ++level;
        cudaMemcpy(sa, dev_sa, v*sizeof(int), cudaMemcpyDeviceToHost);
        for(int i=0; i<v; ++i)
            if(sa[i] == level)
            {
                flag = true;
                break;
            }
    }
    cudaMemcpy(sa, dev_sa, v*sizeof(int), cudaMemcpyDeviceToHost);

    cudaFree(dev_sa);
    cudaFree(dev_beg_pos);
    cudaFree(dev_csr);

}

int csr_begin(int v, int e)
{
    FILE * fp_beg = fopen(file_beg_pos, "r");
    int i = 0;
    int p;
    while(fscanf(fp_beg, "%d", &p) != EOF)
    {
        beg_pos[i] = p;
        ++i;
    }
    fclose(fp_beg);

    i = 0;
    FILE * fp_csr = fopen(file_csr, "r");
    while(fscanf(fp_csr, "%d", &p) != EOF)
    {
        csr[i] = p;
        ++i;
    }
    fclose(fp_csr);
    return v;
}

	.file	"tmpxft_00329102_00000000-6_bfs_gpu_status_array_flag.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"%d"
	.text
	.globl	_Z9csr_beginii
	.type	_Z9csr_beginii, @function
_Z9csr_beginii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r15, %rsi
	leaq	beg_pos(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC1(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	leaq	file_beg_pos(%rip), %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	movq	%rax, %rbx
.L3:
	leaq	4(%rsp), %r13
	xorl	%eax, %eax
	movq	%r12, %rsi
	movq	%rbx, %rdi
	movq	%r13, %rdx
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L10
	movl	4(%rsp), %eax
	addq	$4, %r14
	movl	%eax, -4(%r14)
	jmp	.L3
.L10:
	movq	%rbx, %rdi
	leaq	csr(%rip), %r14
	call	fclose@PLT
	movq	%r15, %rsi
	leaq	file_csr(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %rbx
.L5:
	xorl	%eax, %eax
	movq	%r13, %rdx
	movq	%r12, %rsi
	movq	%rbx, %rdi
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L11
	movl	4(%rsp), %eax
	addq	$4, %r14
	movl	%eax, -4(%r14)
	jmp	.L5
.L11:
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L7
	call	__stack_chk_fail@PLT
.L7:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	movl	%ebp, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z9csr_beginii, .-_Z9csr_beginii
	.globl	_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_
	.type	_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_, @function
_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12traverse_oneiPiS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_, .-_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_
	.globl	_Z12traverse_oneiPiS_S_
	.type	_Z12traverse_oneiPiS_S_, @function
_Z12traverse_oneiPiS_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_
	.cfi_endproc
.LFE2055:
	.size	_Z12traverse_oneiPiS_S_, .-_Z12traverse_oneiPiS_S_
	.globl	_Z6bfs_saiii
	.type	_Z6bfs_saiii, @function
_Z6bfs_saiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	leaq	sa(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movslq	%edx, %rbx
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
.L18:
	cmpl	%eax, %r12d
	jle	.L27
	movl	$2147483647, 0(%r13,%rax,4)
	incq	%rax
	jmp	.L18
.L27:
	movslq	%r12d, %rbp
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	salq	$2, %rbx
	salq	$2, %rbp
	movl	%eax, sa(%rip)
	leaq	4(%rbp), %r14
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	%r14, %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%r14, %rdx
	movl	$1, %ecx
	leaq	beg_pos(%rip), %rsi
	movabsq	$4294967552, %r14
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	leaq	csr(%rip), %rsi
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
.L22:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, %rdx
	movl	$1, %ecx
	movq	%r14, %rdi
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	%ebx, %edi
	movq	8(%rsp), %rsi
	call	_Z37__device_stub__Z12traverse_oneiPiS_S_iPiS_S_
.L20:
	movq	8(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$2, %ecx
	movq	%r13, %rdi
	incl	%ebx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	leaq	-4+sa(%rip), %rdx
.L21:
	cmpl	%eax, %r12d
	jle	.L28
	incq	%rax
	cmpl	%ebx, (%rdx,%rax,4)
	jne	.L21
	jmp	.L22
.L28:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z6bfs_saiii, .-_Z6bfs_saiii
	.section	.rodata.str1.1
.LC2:
	.string	"w"
.LC3:
	.string	"%d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$2097152, %esi
	movl	$65535, %edi
	leaq	.LC3(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	leaq	sa(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	262140(%rbp), %r12
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	_Z9csr_beginii
	movl	$2097152, %edx
	movl	$65535, %esi
	xorl	%edi, %edi
	call	_Z6bfs_saiii
	leaq	.LC2(%rip), %rsi
	leaq	fileout(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %rbx
.L30:
	movl	0(%rbp), %ecx
	movq	%r13, %rdx
	movl	$2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	addq	$4, %rbp
	call	__fprintf_chk@PLT
	cmpq	%r12, %rbp
	jne	.L30
	movq	%rbx, %rdi
	call	fclose@PLT
	popq	%rdx
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z12traverse_oneiPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12traverse_oneiPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	sa
	.bss
	.align 32
	.type	sa, @object
	.size	sa, 262140
sa:
	.zero	262140
	.globl	csr
	.align 32
	.type	csr, @object
	.size	csr, 8388608
csr:
	.zero	8388608
	.globl	beg_pos
	.align 32
	.type	beg_pos, @object
	.size	beg_pos, 262144
beg_pos:
	.zero	262144
	.globl	file_csr
	.data
	.align 32
	.type	file_csr, @object
	.size	file_csr, 35
file_csr:
	.string	"/home/yuede/dataset/kron_16_16.csr"
	.globl	file_beg_pos
	.align 32
	.type	file_beg_pos, @object
	.size	file_beg_pos, 39
file_beg_pos:
	.string	"/home/yuede/dataset/kron_16_16.beg.pos"
	.globl	file_v_e
	.align 32
	.type	file_v_e, @object
	.size	file_v_e, 35
file_v_e:
	.string	"/home/yuede/dataset/kron_16_16.v_e"
	.globl	fileout
	.align 32
	.type	fileout, @object
	.size	fileout, 50
fileout:
	.string	"/home/yuede/dataset/kron_16_16.gpu.as.flag.result"
	.globl	filein
	.align 32
	.type	filein, @object
	.size	filein, 35
filein:
	.string	"/home/yuede/dataset/kron_16_16.dat"
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 File name: bfs_gpu_status_array_flag.cu
 Author: Yuede Ji
 Last update: 13:30 10-10-2015
 Description: Using status array to implent GPU version of bfs.
    Calculate the shortest distance from 0 to others
**/


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

//Using arrays to implement queue
char filein[] = "/home/yuede/dataset/kron_16_16.dat";// no need
char fileout[] = "/home/yuede/dataset/kron_16_16.gpu.as.flag.result";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
/**
char filein[] = "/home/yuede/dataset/kron_10_4.dat";// no need
char fileout[] = "/home/yuede/dataset/kron_10_4.gpu.as.result";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
**/

const int v_num = 65535;
const int e_num = 2097152;
const int INF = 0x7FFFFFFF;
const int threads_num = 256;

int beg_pos[v_num+1];
int csr[e_num];
int sa[v_num];
//load from .dat files, and store in array csr[N*N], beg_pos[N]

int csr_begin(int v, int e);
void bfs_sa(int root, int v, int e);
__global__ void traverse_one(int level, int * dev_sa, int * dev_beg_pos, int * dev_csr)
{
    int id = threadIdx.x + blockIdx.x * blockDim.x;
    if(dev_sa[id] == level)///node i belongs to current level
    {
        //int j = dev_beg_pos[id];
        for(int j=dev_beg_pos[id]; j<dev_beg_pos[id+1]; ++j)
        {
            if(dev_sa[dev_csr[j]] > level + 1)
            { 
                dev_sa[dev_csr[j]] = level + 1;
                printf("%d\n", dev_csr[j]);
            }
        }                    
    }
}

int main()
{
    csr_begin(v_num, e_num);

    bfs_sa(0, v_num, e_num);

    FILE * fp_out = fopen(fileout, "w");

    for(int i=0; i<v_num; ++i)
        fprintf(fp_out, "%d\n", sa[i]);
    fclose(fp_out);
    
    return 0;
}
void bfs_sa(int root, int v, int e)
{
    for(int i=0; i<v; ++i)
        sa[i] = INF;
    int level = 0;
    sa[0] = 0;
    bool flag = true; //flag whether current level has nodes
    
    int *dev_sa;
    int *dev_beg_pos;
    int *dev_csr;

    hipMalloc( (void **) &dev_sa, v*sizeof(int));
    hipMalloc( (void **) &dev_beg_pos, (v+1)*sizeof(int));
    hipMalloc( (void **) &dev_csr, e*sizeof(int));

    hipMemcpy(dev_sa, sa, v*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(dev_beg_pos, beg_pos, (v+1)*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(dev_csr, csr, e*sizeof(int), hipMemcpyHostToDevice);
    
    while(flag)
    {
        flag = false;
        traverse_one<<<threads_num, threads_num>>>(level, dev_sa, dev_beg_pos, dev_csr);
        ++level;
        hipMemcpy(sa, dev_sa, v*sizeof(int), hipMemcpyDeviceToHost);
        for(int i=0; i<v; ++i)
            if(sa[i] == level)
            {
                flag = true;
                break;
            }
    }
    hipMemcpy(sa, dev_sa, v*sizeof(int), hipMemcpyDeviceToHost);

    hipFree(dev_sa);
    hipFree(dev_beg_pos);
    hipFree(dev_csr);

}

int csr_begin(int v, int e)
{
    FILE * fp_beg = fopen(file_beg_pos, "r");
    int i = 0;
    int p;
    while(fscanf(fp_beg, "%d", &p) != EOF)
    {
        beg_pos[i] = p;
        ++i;
    }
    fclose(fp_beg);

    i = 0;
    FILE * fp_csr = fopen(file_csr, "r");
    while(fscanf(fp_csr, "%d", &p) != EOF)
    {
        csr[i] = p;
        ++i;
    }
    fclose(fp_csr);
    return v;
}

	.text
	.file	"bfs_gpu_status_array_flag.hip"
	.globl	_Z27__device_stub__traverse_oneiPiS_S_ # -- Begin function _Z27__device_stub__traverse_oneiPiS_S_
	.type	_Z27__device_stub__traverse_oneiPiS_S_,@function
_Z27__device_stub__traverse_oneiPiS_S_: # @_Z27__device_stub__traverse_oneiPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12traverse_oneiPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__traverse_oneiPiS_S_, .Lfunc_end0-_Z27__device_stub__traverse_oneiPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$65535, %edi                    # imm = 0xFFFF
	callq	_Z9csr_beginii
	movl	$65535, %esi                    # imm = 0xFFFF
	movl	$2097152, %edx                  # imm = 0x200000
	callq	_Z6bfs_saiii
	movl	$fileout, %edi
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %rbx
	movq	$-262140, %r14                  # imm = 0xFFFC0004
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	sa+262140(%r14), %edx
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	fprintf
	addq	$4, %r14
	jne	.LBB1_1
# %bb.2:
	movq	%rbx, %rdi
	callq	fclose
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z9csr_beginii                  # -- Begin function _Z9csr_beginii
	.type	_Z9csr_beginii,@function
_Z9csr_beginii:                         # @_Z9csr_beginii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edi, %ebx
	movl	$file_beg_pos, %edi
	movl	$.L.str.2, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	4(%rsp), %rdx
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	je	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	movl	$beg_pos, %r12d
	leaq	4(%rsp), %r15
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	4(%rsp), %eax
	movl	%eax, (%r12)
	movl	$.L.str.3, %esi
	movq	%r14, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r12
	cmpl	$-1, %eax
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	movq	%r14, %rdi
	callq	fclose
	movl	$file_csr, %edi
	movl	$.L.str.2, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	4(%rsp), %rdx
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	je	.LBB2_6
# %bb.4:                                # %.lr.ph14.preheader
	movl	$csr, %r12d
	leaq	4(%rsp), %r15
.LBB2_5:                                # %.lr.ph14
                                        # =>This Inner Loop Header: Depth=1
	movl	4(%rsp), %eax
	movl	%eax, (%r12)
	movl	$.L.str.3, %esi
	movq	%r14, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r12
	cmpl	$-1, %eax
	jne	.LBB2_5
.LBB2_6:                                # %._crit_edge15
	movq	%r14, %rdi
	callq	fclose
	movl	%ebx, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9csr_beginii, .Lfunc_end2-_Z9csr_beginii
	.cfi_endproc
                                        # -- End function
	.globl	_Z6bfs_saiii                    # -- Begin function _Z6bfs_saiii
	.type	_Z6bfs_saiii,@function
_Z6bfs_saiii:                           # @_Z6bfs_saiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r12d
	movl	%esi, %ebx
	movl	%esi, %ebp
	testl	%esi, %esi
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph.preheader
	leaq	(,%rbp,4), %rax
	xorl	%ecx, %ecx
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$2147483647, sa(%rcx)           # imm = 0x7FFFFFFF
	addq	$4, %rcx
	cmpq	%rcx, %rax
	jne	.LBB3_2
.LBB3_3:                                # %._crit_edge
	movabsq	$4294967552, %r15               # imm = 0x100000100
	movl	$0, sa(%rip)
	movslq	%ebx, %r13
	leaq	(,%r13,4), %r14
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	4(,%r13,4), %rsi
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movslq	%r12d, %r12
	shlq	$2, %r12
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$sa, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$beg_pos, %esi
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movl	$csr, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
.LBB3_4:                                # %.critedge
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_9 Depth 2
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=1
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movl	%r12d, %edi
	callq	_Z27__device_stub__traverse_oneiPiS_S_
.LBB3_6:                                #   in Loop: Header=BB3_4 Depth=1
	movq	8(%rsp), %rsi
	movl	$sa, %edi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%ebx, %ebx
	jle	.LBB3_12
# %bb.7:                                # %.lr.ph32.preheader
                                        #   in Loop: Header=BB3_4 Depth=1
	incl	%r12d
	cmpl	%r12d, sa(%rip)
	je	.LBB3_4
# %bb.8:                                # %.lr.ph44.preheader
                                        #   in Loop: Header=BB3_4 Depth=1
	movl	$1, %ecx
.LBB3_9:                                # %.lr.ph44
                                        #   Parent Loop BB3_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%rcx, %rax
	cmpq	%rcx, %rbp
	je	.LBB3_11
# %bb.10:                               # %.lr.ph32
                                        #   in Loop: Header=BB3_9 Depth=2
	leaq	1(%rax), %rcx
	cmpl	%r12d, sa(,%rax,4)
	jne	.LBB3_9
.LBB3_11:                               # %._crit_edge33
                                        #   in Loop: Header=BB3_4 Depth=1
	cmpq	%r13, %rax
	jl	.LBB3_4
.LBB3_12:                               # %._crit_edge33.thread
	movq	8(%rsp), %rsi
	movl	$sa, %edi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z6bfs_saiii, .Lfunc_end3-_Z6bfs_saiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12traverse_oneiPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	filein,@object                  # @filein
	.data
	.globl	filein
	.p2align	4, 0x0
filein:
	.asciz	"/home/yuede/dataset/kron_16_16.dat"
	.size	filein, 35

	.type	fileout,@object                 # @fileout
	.globl	fileout
	.p2align	4, 0x0
fileout:
	.asciz	"/home/yuede/dataset/kron_16_16.gpu.as.flag.result"
	.size	fileout, 50

	.type	file_v_e,@object                # @file_v_e
	.globl	file_v_e
	.p2align	4, 0x0
file_v_e:
	.asciz	"/home/yuede/dataset/kron_16_16.v_e"
	.size	file_v_e, 35

	.type	file_beg_pos,@object            # @file_beg_pos
	.globl	file_beg_pos
	.p2align	4, 0x0
file_beg_pos:
	.asciz	"/home/yuede/dataset/kron_16_16.beg.pos"
	.size	file_beg_pos, 39

	.type	file_csr,@object                # @file_csr
	.globl	file_csr
	.p2align	4, 0x0
file_csr:
	.asciz	"/home/yuede/dataset/kron_16_16.csr"
	.size	file_csr, 35

	.type	beg_pos,@object                 # @beg_pos
	.bss
	.globl	beg_pos
	.p2align	4, 0x0
beg_pos:
	.zero	262144
	.size	beg_pos, 262144

	.type	csr,@object                     # @csr
	.globl	csr
	.p2align	4, 0x0
csr:
	.zero	8388608
	.size	csr, 8388608

	.type	sa,@object                      # @sa
	.globl	sa
	.p2align	4, 0x0
sa:
	.zero	262140
	.size	sa, 262140

	.type	_Z12traverse_oneiPiS_S_,@object # @_Z12traverse_oneiPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z12traverse_oneiPiS_S_
	.p2align	3, 0x0
_Z12traverse_oneiPiS_S_:
	.quad	_Z27__device_stub__traverse_oneiPiS_S_
	.size	_Z12traverse_oneiPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"w"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d\n"
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"r"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d"
	.size	.L.str.3, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12traverse_oneiPiS_S_"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__traverse_oneiPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym fileout
	.addrsig_sym file_beg_pos
	.addrsig_sym file_csr
	.addrsig_sym beg_pos
	.addrsig_sym csr
	.addrsig_sym sa
	.addrsig_sym _Z12traverse_oneiPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12traverse_oneiPiS_S_ ; -- Begin function _Z12traverse_oneiPiS_S_
	.globl	_Z12traverse_oneiPiS_S_
	.p2align	8
	.type	_Z12traverse_oneiPiS_S_,@function
_Z12traverse_oneiPiS_S_:                ; @_Z12traverse_oneiPiS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_load_b32 s22, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_mov_b32 s8, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 s22, v2
	s_cbranch_execz .LBB0_176
; %bb.1:
	v_add_co_u32 v29, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v30, vcc_lo, s7, v1, vcc_lo
	s_load_b64 s[6:7], s[0:1], 0x18
	global_load_b64 v[31:32], v[29:30], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v31, v32
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_176
; %bb.2:                                ; %.lr.ph
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 2
	v_mov_b32_e32 v6, 1
	v_mov_b32_e32 v0, 33
	s_add_i32 s22, s22, 1
	s_mov_b32 s8, 0
	s_mov_b32 s23, 0
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_15 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_30 Depth 2
                                        ;     Child Loop BB0_33 Depth 2
                                        ;       Child Loop BB0_36 Depth 3
                                        ;       Child Loop BB0_44 Depth 3
                                        ;       Child Loop BB0_52 Depth 3
                                        ;       Child Loop BB0_60 Depth 3
                                        ;       Child Loop BB0_68 Depth 3
                                        ;       Child Loop BB0_76 Depth 3
                                        ;       Child Loop BB0_84 Depth 3
                                        ;       Child Loop BB0_92 Depth 3
                                        ;       Child Loop BB0_100 Depth 3
                                        ;       Child Loop BB0_106 Depth 3
                                        ;       Child Loop BB0_115 Depth 3
                                        ;     Child Loop BB0_123 Depth 2
                                        ;     Child Loop BB0_131 Depth 2
                                        ;     Child Loop BB0_137 Depth 2
                                        ;     Child Loop BB0_146 Depth 2
                                        ;     Child Loop BB0_151 Depth 2
                                        ;     Child Loop BB0_159 Depth 2
                                        ;     Child Loop BB0_165 Depth 2
                                        ;     Child Loop BB0_174 Depth 2
	v_ashrrev_i32_e32 v32, 31, v31
	s_mov_b32 s24, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[31:32]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v7, v[3:4], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 s22, v1
	s_cbranch_execz .LBB0_175
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v1, s22
	global_store_b32 v[7:8], v1, off
	global_load_b32 v32, v[3:4], off
	s_load_b64 s[12:13], s[2:3], 0x50
	v_mov_b32_e32 v1, v33
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v1
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_10
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[7:8], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB0_9
; %bb.6:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s10, 0
.LBB0_7:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ; %Flow351
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_9:                                ; %Flow353
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_10:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[12:13] offset:40
	global_load_b128 v[7:10], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v11
	v_readfirstlane_b32 s11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v7, s17
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
	global_store_b128 v[11:12], v[3:6], off offset:8
.LBB0_12:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v14, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v12, s11
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v10, s9
	v_mov_b32_e32 v11, s10
	v_mov_b32_e32 v9, s8
	s_clause 0x3
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[9:12], off offset:16
	global_store_b128 v[13:14], v[9:12], off offset:32
	global_store_b128 v[13:14], v[9:12], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_20
; %bb.13:                               ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[12:13] offset:32 glc
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	v_mov_b32_e32 v15, s14
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v16, s15 :: v_dual_and_b32 v1, s15, v4
	v_and_b32_e32 v3, s14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v1, vcc_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_16
; %bb.14:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s11, 0
.LBB0_15:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s15
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_15
.LBB0_16:                               ; %Flow349
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_18:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_20:                               ; %Flow350
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v7, s17
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_21:                               ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_23:                               ;   in Loop: Header=BB0_21 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_21 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_26
.LBB0_25:                               ;   in Loop: Header=BB0_21 Depth=2
	s_mov_b32 s1, -1
.LBB0_26:                               ; %Flow344
                                        ;   in Loop: Header=BB0_21 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_21
; %bb.27:                               ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[7:8], v[13:14], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_31
; %bb.28:                               ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[13:14], v2, s[12:13] offset:24 glc
	global_load_b64 v[11:12], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_31
; %bb.29:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_30:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_30
.LBB0_31:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB0_118
; %bb.32:                               ;   in Loop: Header=BB0_3 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v34, 2, v7
	v_dual_mov_b32 v10, v8 :: v_dual_and_b32 v9, -3, v7
	s_mov_b64 s[14:15], 4
.LBB0_33:                               ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_36 Depth 3
                                        ;       Child Loop BB0_44 Depth 3
                                        ;       Child Loop BB0_52 Depth 3
                                        ;       Child Loop BB0_60 Depth 3
                                        ;       Child Loop BB0_68 Depth 3
                                        ;       Child Loop BB0_76 Depth 3
                                        ;       Child Loop BB0_84 Depth 3
                                        ;       Child Loop BB0_92 Depth 3
                                        ;       Child Loop BB0_100 Depth 3
                                        ;       Child Loop BB0_106 Depth 3
                                        ;       Child Loop BB0_115 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[14:15], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s16, s14, 56
	s_cselect_b32 s17, s15, 0
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB0_38
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB0_37
; %bb.35:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_lshl_b64 s[0:1], s[16:17], 3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], s[10:11]
.LBB0_36:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[20:21]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s0, s18
	v_or_b32_e32 v11, v3, v11
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB0_36
.LBB0_37:                               ; %Flow320
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_39
.LBB0_38:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr9
.LBB0_39:                               ; %Flow322
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[11:12], v2, s[10:11]
	s_add_i32 s9, s16, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB0_41:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_46
; %bb.42:                               ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_45
; %bb.43:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_44:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s20
	s_addc_u32 s27, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[26:27]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s9, s20
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB0_44
.LBB0_45:                               ; %Flow315
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s25, 0
	s_branch .LBB0_47
.LBB0_46:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr25
.LBB0_47:                               ; %Flow317
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_49
; %bb.48:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[13:14], v2, s[0:1]
	s_add_i32 s25, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_49:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_cmp_gt_u32 s25, 7
	s_cbranch_scc1 .LBB0_54
; %bb.50:                               ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s25, 0
	s_cbranch_scc1 .LBB0_53
; %bb.51:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_52:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s20
	s_addc_u32 s27, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[26:27]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s25, s20
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB0_52
.LBB0_53:                               ; %Flow310
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_55
.LBB0_54:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr9
.LBB0_55:                               ; %Flow312
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_57
; %bb.56:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[15:16], v2, s[0:1]
	s_add_i32 s9, s25, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_57:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_62
; %bb.58:                               ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_61
; %bb.59:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_60:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s20
	s_addc_u32 s27, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[26:27]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s9, s20
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB0_60
.LBB0_61:                               ; %Flow305
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s25, 0
	s_branch .LBB0_63
.LBB0_62:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr25
.LBB0_63:                               ; %Flow307
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_65
; %bb.64:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[17:18], v2, s[0:1]
	s_add_i32 s25, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_65:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_cmp_gt_u32 s25, 7
	s_cbranch_scc1 .LBB0_70
; %bb.66:                               ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s25, 0
	s_cbranch_scc1 .LBB0_69
; %bb.67:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_68:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s20
	s_addc_u32 s27, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[26:27]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s25, s20
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB0_68
.LBB0_69:                               ; %Flow300
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_71
.LBB0_70:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr9
.LBB0_71:                               ; %Flow302
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_73
; %bb.72:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[19:20], v2, s[0:1]
	s_add_i32 s9, s25, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_73:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_78
; %bb.74:                               ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_77
; %bb.75:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_76:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s20
	s_addc_u32 s27, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[26:27]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s9, s20
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB0_76
.LBB0_77:                               ; %Flow295
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s25, 0
	s_branch .LBB0_79
.LBB0_78:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr25
.LBB0_79:                               ; %Flow297
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_81
; %bb.80:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[21:22], v2, s[0:1]
	s_add_i32 s25, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_81:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_cmp_gt_u32 s25, 7
	s_cbranch_scc1 .LBB0_86
; %bb.82:                               ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s25, 0
	s_cbranch_scc1 .LBB0_85
; %bb.83:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], s[0:1]
.LBB0_84:                               ; %.preheader.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[20:21]
	s_add_i32 s25, s25, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s25, 0
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB0_84
.LBB0_85:                               ; %Flow290
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s9, 0
	s_branch .LBB0_87
.LBB0_86:                               ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s9, -1
.LBB0_87:                               ; %Flow292
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_89
; %bb.88:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[23:24], v2, s[0:1]
.LBB0_89:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	v_mov_b32_e32 v1, v33
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_95
; %bb.90:                               ;   in Loop: Header=BB0_33 Depth=2
	global_load_b64 v[27:28], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[25:26], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v35, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v35, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB0_94
; %bb.91:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s18, 0
.LBB0_92:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[12:13] offset:40
	global_load_b64 v[35:36], v2, s[12:13]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v25, 24, v[35:36]
	v_and_b32_e32 v35, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v35, 24, v[4:5]
	v_mov_b32_e32 v4, v25
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_92
; %bb.93:                               ; %Flow285
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_94:                               ; %Flow287
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_95:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[35:36], v2, s[12:13] offset:40
	global_load_b128 v[25:28], v2, s[12:13]
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_mov_b32 s26, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s20, v35
	v_readfirstlane_b32 s21, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[18:19], s[20:21]
	s_mul_i32 s1, s21, 24
	s_mul_hi_u32 s9, s20, 24
	s_mul_i32 s25, s20, 24
	s_and_saveexec_b32 s27, s0
	s_cbranch_execz .LBB0_97
; %bb.96:                               ;   in Loop: Header=BB0_33 Depth=2
	v_dual_mov_b32 v3, s26 :: v_dual_mov_b32 v4, v2
	s_add_i32 s26, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v35, vcc_lo, v25, s25
	v_add_co_ci_u32_e32 v36, vcc_lo, s26, v26, vcc_lo
	global_store_b128 v[35:36], v[3:6], off offset:8
.LBB0_97:                               ;   in Loop: Header=BB0_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	v_cmp_gt_u64_e64 vcc_lo, s[14:15], 56
	v_or_b32_e32 v3, 0, v10
	v_or_b32_e32 v4, v9, v34
	s_lshl_b64 s[20:21], s[20:21], 12
	s_lshl_b32 s26, s16, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s26, s26, 28
	v_dual_cndmask_b32 v10, v3, v10 :: v_dual_cndmask_b32 v9, v4, v9
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s20
	v_add_co_ci_u32_e32 v27, vcc_lo, s21, v28, vcc_lo
	s_and_b32 s26, s26, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v9, 0xffffff1f, v9, s26
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[21:24], off offset:48
	s_and_saveexec_b32 s20, s0
	s_cbranch_execz .LBB0_105
; %bb.98:                               ;   in Loop: Header=BB0_33 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[12:13] offset:32 glc
	global_load_b64 v[9:10], v2, s[12:13] offset:40
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s26, v9
	v_readfirstlane_b32 s27, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[26:27], s[26:27], s[18:19]
	s_mul_i32 s21, s27, 24
	s_mul_hi_u32 s27, s26, 24
	s_mul_i32 s26, s26, 24
	s_add_i32 s27, s27, s21
	v_add_co_u32 v13, vcc_lo, v25, s26
	v_add_co_ci_u32_e32 v14, vcc_lo, s27, v26, vcc_lo
	s_mov_b32 s21, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_101
; %bb.99:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s26, 0
.LBB0_100:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
	s_sleep 1
	global_store_b64 v[13:14], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_100
.LBB0_101:                              ; %Flow283
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	global_load_b64 v[9:10], v2, s[12:13] offset:16
	s_mov_b32 s26, exec_lo
	s_mov_b32 s21, exec_lo
	v_mbcnt_lo_u32_b32 v1, s26, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_33 Depth=2
	s_bcnt1_i32_b32 s26, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s26
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[1:2], off offset:8
.LBB0_103:                              ;   in Loop: Header=BB0_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_33 Depth=2
	global_load_b32 v1, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s21, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s21, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_105:                              ; %Flow284
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s9, s9, s1
	v_add_co_u32 v1, vcc_lo, v25, s25
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_106:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_106 Depth=3
	global_load_b32 v1, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_108:                              ;   in Loop: Header=BB0_106 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_110
; %bb.109:                              ;   in Loop: Header=BB0_106 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_111
.LBB0_110:                              ;   in Loop: Header=BB0_106 Depth=3
	s_mov_b32 s1, -1
.LBB0_111:                              ; %Flow278
                                        ;   in Loop: Header=BB0_106 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_106
; %bb.112:                              ;   in Loop: Header=BB0_33 Depth=2
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_116
; %bb.113:                              ;   in Loop: Header=BB0_33 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[15:16], v2, s[12:13] offset:24 glc
	global_load_b64 v[13:14], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v1, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_116
; %bb.114:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_mov_b32 s0, 0
.LBB0_115:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_33 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_115
.LBB0_116:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s14, s14, s16
	s_subb_u32 s15, s15, s17
	s_add_u32 s10, s10, s16
	s_addc_u32 s11, s11, s17
	s_cmp_lg_u64 s[14:15], 0
	s_cbranch_scc1 .LBB0_33
; %bb.117:                              ; %Flow323
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_119
.LBB0_118:                              ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_119:                              ; %Flow338
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_148
; %bb.120:                              ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v1, v33
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_126
; %bb.121:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[11:12], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[9:10], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB0_125
; %bb.122:                              ; %.preheader3.i.i.i28.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s10, 0
.LBB0_123:                              ; %.preheader3.i.i.i28
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[12:13] offset:40
	global_load_b64 v[13:14], v2, s[12:13]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_123
; %bb.124:                              ; %Flow335
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_125:                              ; %Flow337
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_126:                              ; %.loopexit4.i.i.i23
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[12:13] offset:40
	global_load_b128 v[11:14], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v9
	v_readfirstlane_b32 s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_128
; %bb.127:                              ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB0_128:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v7, 0xffffff1f, v7, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v16, s11
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v15, s10
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_136
; %bb.129:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[12:13] offset:32 glc
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	v_dual_mov_b32 v15, s14 :: v_dual_mov_b32 v16, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v13, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s18, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB0_132
; %bb.130:                              ; %.preheader1.i.i.i26.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s11, 0
.LBB0_131:                              ; %.preheader1.i.i.i26
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
	s_sleep 1
	global_store_b64 v[13:14], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_131
.LBB0_132:                              ; %Flow333
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB0_134:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_136:                              ; %Flow334
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_137:                              ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_139
; %bb.138:                              ;   in Loop: Header=BB0_137 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_139:                              ;   in Loop: Header=BB0_137 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_141
; %bb.140:                              ;   in Loop: Header=BB0_137 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_142
.LBB0_141:                              ;   in Loop: Header=BB0_137 Depth=2
	s_mov_b32 s1, -1
.LBB0_142:                              ; %Flow328
                                        ;   in Loop: Header=BB0_137 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_137
; %bb.143:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_147
; %bb.144:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[7:8], v2, s[12:13] offset:24 glc
	global_load_b64 v[13:14], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v12, vcc_lo, s15, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_147
; %bb.145:                              ; %.preheader.i.i.i25.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_146:                              ; %.preheader.i.i.i25
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_146
.LBB0_147:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_148:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v1, v33
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_154
; %bb.149:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[13:14], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[7:8], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[13:14]
	s_cbranch_execz .LBB0_153
; %bb.150:                              ; %.preheader3.i.i.i35.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s10, 0
.LBB0_151:                              ; %.preheader3.i.i.i35
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13]
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[13:14]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_151
; %bb.152:                              ; %Flow271
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_153:                              ; %Flow273
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_154:                              ; %.loopexit4.i.i.i29
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	global_load_b128 v[13:16], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_156
; %bb.155:                              ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v13, s17
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v14, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB0_156:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v9, 0xffffff1d, v9, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v11, v32 :: v_dual_mov_b32 v12, v2
	v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v17, s10
	v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v15, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[15:18], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[15:18], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_164
; %bb.157:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[12:13] offset:32 glc
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v3, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s18, v14, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[11:12]
	s_cbranch_execz .LBB0_160
; %bb.158:                              ; %.preheader1.i.i.i33.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s11, 0
.LBB0_159:                              ; %.preheader1.i.i.i33
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_159
.LBB0_160:                              ; %Flow269
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_162:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_164:                              ; %Flow270
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v13, s17
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_165:                              ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_167
; %bb.166:                              ;   in Loop: Header=BB0_165 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_167:                              ;   in Loop: Header=BB0_165 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_169
; %bb.168:                              ;   in Loop: Header=BB0_165 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_170
.LBB0_169:                              ;   in Loop: Header=BB0_165 Depth=2
	s_mov_b32 s1, -1
.LBB0_170:                              ; %Flow264
                                        ;   in Loop: Header=BB0_165 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_165
; %bb.171:                              ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_175
; %bb.172:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13] offset:24 glc
	global_load_b64 v[9:10], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_175
; %bb.173:                              ; %.preheader.i.i.i32.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_174:                              ; %.preheader.i.i.i32
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_174
.LBB0_175:                              ; %Flow354
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	global_load_b32 v1, v[29:30], off offset:4
	v_add_nc_u32_e32 v31, 1, v31
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v31, v1
	s_or_b32 s23, vcc_lo, s23
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_3
.LBB0_176:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12traverse_oneiPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12traverse_oneiPiS_S_, .Lfunc_end0-_Z12traverse_oneiPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6916
; NumSgprs: 30
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d\n"
	.size	.str, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12traverse_oneiPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z12traverse_oneiPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
