// past distance driven
#include <math.h>
#define ABS(x) ((x) > 0 ? (x) : - (x))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define PI 3.141592653589793

__global__ void kernel_backprojection(float *img, float *proj, float angle, float SO, float SD, float da, int na, float ai, float db, int nb, float bi, int nx, int ny, int nz){
    int ix = 16 * blockIdx.x + threadIdx.x;
    int iy = 16 * blockIdx.y + threadIdx.y;
    int iz = 4 * blockIdx.z + threadIdx.z;
    if (ix >= nx || iy >= ny || iz >= nz)
        return;
    int id = ix + iy * nx + iz * nx * ny;
    img[id] = 0.0f;
    float cphi, sphi;
    angle += PI;
    cphi = (float)cosf(angle);
    sphi = (float)sinf(angle);
    float xa, ya, za;
    xa = ix - nx / 2 + 0.5f;
    ya = iy - ny / 2 + 0.5f;
    za = iz - nz / 2 + 0.5f;
    // xa = xa0 * cphi - ya0 * sphi;
    // ya = xa0 * sphi + ya0 * cphi;
    float xl, yl, zl, xr, yr, zr, xt, yt, zt, xb, yb, zb;
    xl = (xa - 0.5f) * cphi + (ya - 0.5f) * sphi;
    yl = -(xa - 0.5f) * sphi + (ya - 0.5f) * cphi;
    xr = (xa + 0.5f) * cphi + (ya + 0.5f) * sphi;
    yr = -(xa + 0.5f) * sphi + (ya + 0.5f) * cphi;
    zl = za; zr = za;
    xt = xa * cphi + ya * sphi;
    yt = -xa * sphi + ya * cphi;
    zt = za + 0.5f;
    xb = xa * cphi + ya * sphi;
    yb = -xa * sphi + ya * cphi;
    zb = za - 0.5f;
    float bl, br, bt, bb, temp, wlr, wbt;
    bl = yl * SD / (SO + xl) / da + na / 2;
    br = yr * SD / (SO + xr) / da + na / 2;
    if (bl > br) {temp = bl; bl = br; br = temp;}
    bt = zt * SD / (SO * xt) / db + nb / 2;
    bb = zb * SD / (SO * xb) / db + nb / 2;
    wlr = br - bl;
    wbt = bt - bb;

    int ibl, ibr, ibt, ibb;
    ibl = (int)floor(bl);
    ibr = (int)floor(br);
    ibt = (int)floor(bt);
    ibb = (int)floor(bb);
    float w1, w2;
    for (int ia = ibl; ia <= ibr; ia ++){
        if (ia < 0 || ia >= na)
            continue;
        for (int ib = ibb; ib <= ibt; ib++){
            if (ib < 0 || ib >= nb)
                continue;
            w1 = MIN(br, ia + 1) - MAX(bl, ia);
            w2 = MIN(bt, ib + 1) - MAX(bb, ib);
            img[id] += proj[ia + ib * na] * w1 * w2 / wlr / wbt;
        }   
    }
}
	.file	"tmpxft_00280f43_00000000-6_kernel_backprojection1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z55__device_stub__Z21kernel_backprojectionPfS_ffffiffifiiiPfS_ffffiffifiii
	.type	_Z55__device_stub__Z21kernel_backprojectionPfS_ffffiffifiiiPfS_ffffiffifiii, @function
_Z55__device_stub__Z21kernel_backprojectionPfS_ffffiffifiiiPfS_ffffiffifiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 36(%rsp)
	movss	%xmm3, 32(%rsp)
	movss	%xmm4, 24(%rsp)
	movss	%xmm5, 20(%rsp)
	movss	%xmm6, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z21kernel_backprojectionPfS_ffffiffifiii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 288
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z55__device_stub__Z21kernel_backprojectionPfS_ffffiffifiiiPfS_ffffiffifiii, .-_Z55__device_stub__Z21kernel_backprojectionPfS_ffffiffifiiiPfS_ffffiffifiii
	.globl	_Z21kernel_backprojectionPfS_ffffiffifiii
	.type	_Z21kernel_backprojectionPfS_ffffiffifiii, @function
_Z21kernel_backprojectionPfS_ffffiffifiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z21kernel_backprojectionPfS_ffffiffifiiiPfS_ffffiffifiii
	.cfi_endproc
.LFE2033:
	.size	_Z21kernel_backprojectionPfS_ffffiffifiii, .-_Z21kernel_backprojectionPfS_ffffiffifiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21kernel_backprojectionPfS_ffffiffifiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21kernel_backprojectionPfS_ffffiffifiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// past distance driven

#include <hip/hip_runtime.h>
#include <math.h>
#define ABS(x) ((x) > 0 ? (x) : - (x))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define PI 3.141592653589793

__global__ void kernel_backprojection(float *img, float *proj, float angle, float SO, float SD, float da, int na, float ai, float db, int nb, float bi, int nx, int ny, int nz){
    int ix = 16 * blockIdx.x + threadIdx.x;
    int iy = 16 * blockIdx.y + threadIdx.y;
    int iz = 4 * blockIdx.z + threadIdx.z;
    if (ix >= nx || iy >= ny || iz >= nz)
        return;
    int id = ix + iy * nx + iz * nx * ny;
    img[id] = 0.0f;
    float cphi, sphi;
    angle += PI;
    cphi = (float)cosf(angle);
    sphi = (float)sinf(angle);
    float xa, ya, za;
    xa = ix - nx / 2 + 0.5f;
    ya = iy - ny / 2 + 0.5f;
    za = iz - nz / 2 + 0.5f;
    // xa = xa0 * cphi - ya0 * sphi;
    // ya = xa0 * sphi + ya0 * cphi;
    float xl, yl, zl, xr, yr, zr, xt, yt, zt, xb, yb, zb;
    xl = (xa - 0.5f) * cphi + (ya - 0.5f) * sphi;
    yl = -(xa - 0.5f) * sphi + (ya - 0.5f) * cphi;
    xr = (xa + 0.5f) * cphi + (ya + 0.5f) * sphi;
    yr = -(xa + 0.5f) * sphi + (ya + 0.5f) * cphi;
    zl = za; zr = za;
    xt = xa * cphi + ya * sphi;
    yt = -xa * sphi + ya * cphi;
    zt = za + 0.5f;
    xb = xa * cphi + ya * sphi;
    yb = -xa * sphi + ya * cphi;
    zb = za - 0.5f;
    float bl, br, bt, bb, temp, wlr, wbt;
    bl = yl * SD / (SO + xl) / da + na / 2;
    br = yr * SD / (SO + xr) / da + na / 2;
    if (bl > br) {temp = bl; bl = br; br = temp;}
    bt = zt * SD / (SO * xt) / db + nb / 2;
    bb = zb * SD / (SO * xb) / db + nb / 2;
    wlr = br - bl;
    wbt = bt - bb;

    int ibl, ibr, ibt, ibb;
    ibl = (int)floor(bl);
    ibr = (int)floor(br);
    ibt = (int)floor(bt);
    ibb = (int)floor(bb);
    float w1, w2;
    for (int ia = ibl; ia <= ibr; ia ++){
        if (ia < 0 || ia >= na)
            continue;
        for (int ib = ibb; ib <= ibt; ib++){
            if (ib < 0 || ib >= nb)
                continue;
            w1 = MIN(br, ia + 1) - MAX(bl, ia);
            w2 = MIN(bt, ib + 1) - MAX(bb, ib);
            img[id] += proj[ia + ib * na] * w1 * w2 / wlr / wbt;
        }   
    }
}
	.text
	.file	"kernel_backprojection1.hip"
	.globl	_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii # -- Begin function _Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii
	.type	_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii,@function
_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii: # @_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	44(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	40(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	36(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	32(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	28(%rsp), %r15
	movl	%edx, (%r15)
	leaq	24(%rsp), %rdx
	movss	%xmm4, (%rdx)
	leaq	20(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	16(%rsp), %r13
	movl	%ecx, (%r13)
	leaq	12(%rsp), %rcx
	movss	%xmm6, (%rcx)
	leaq	8(%rsp), %rbp
	movl	%r8d, (%rbp)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%r15, 48(%rbx)
	movq	%rdx, 56(%rbx)
	movq	%r12, 64(%rbx)
	movq	%r13, 72(%rbx)
	movq	%rcx, 80(%rbx)
	movq	%rbp, 88(%rbx)
	movq	%r8, 96(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21kernel_backprojectionPfS_ffffiffifiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$248, %rsp
	.cfi_adjust_cfa_offset -248
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii, .Lfunc_end0-_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21kernel_backprojectionPfS_ffffiffifiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21kernel_backprojectionPfS_ffffiffifiii,@object # @_Z21kernel_backprojectionPfS_ffffiffifiii
	.section	.rodata,"a",@progbits
	.globl	_Z21kernel_backprojectionPfS_ffffiffifiii
	.p2align	3, 0x0
_Z21kernel_backprojectionPfS_ffffiffifiii:
	.quad	_Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii
	.size	_Z21kernel_backprojectionPfS_ffffiffifiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21kernel_backprojectionPfS_ffffiffifiii"
	.size	.L__unnamed_1, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__kernel_backprojectionPfS_ffffiffifiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21kernel_backprojectionPfS_ffffiffifiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21kernel_backprojectionPfS_ffffiffifiii ; -- Begin function _Z21kernel_backprojectionPfS_ffffiffifiii
	.globl	_Z21kernel_backprojectionPfS_ffffiffifiii
	.p2align	8
	.type	_Z21kernel_backprojectionPfS_ffffiffifiii,@function
_Z21kernel_backprojectionPfS_ffffiffifiii: ; @_Z21kernel_backprojectionPfS_ffffiffifiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[16:17], s[0:1], 0x34
	s_load_b32 s12, s[0:1], 0x3c
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v2, s13, 4, v1
	v_lshl_add_u32 v3, s14, 4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v4, s15, 2, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s17, v3
	v_cmp_gt_i32_e64 s3, s12, v4
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_19
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x400921fb
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[0:1], s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], s[2:3]
	v_cvt_f32_f64_e32 v5, v[0:1]
	v_mad_u64_u32 v[0:1], null, v4, s17, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v0, s16, v[2:3]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	v_mov_b32_e32 v6, 0
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
	v_cmp_ngt_f32_e64 s3, 0x48000000, |v5|
	v_readfirstlane_b32 s2, v5
	s_and_b32 vcc_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	s_bitset0_b32 s2, 31
	s_cbranch_vccz .LBB0_3
; %bb.2:
	s_and_b32 s4, s2, 0x7fffff
	s_lshr_b32 s5, s2, 23
	s_bitset1_b32 s4, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s8, s4, 0xfe5163ab
	s_mul_i32 s13, s4, 0x3c439041
	s_mul_hi_u32 s14, s4, 0x3c439041
	s_add_u32 s8, s8, s13
	s_addc_u32 s13, 0, s14
	s_mul_i32 s14, s4, 0xdb629599
	s_mul_hi_u32 s15, s4, 0xdb629599
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s15
	s_mul_i32 s15, s4, 0xf534ddc0
	s_mul_hi_u32 s18, s4, 0xf534ddc0
	s_add_u32 s14, s14, s15
	s_addc_u32 s15, 0, s18
	s_mul_i32 s18, s4, 0xfc2757d1
	s_mul_hi_u32 s19, s4, 0xfc2757d1
	s_add_u32 s15, s15, s18
	s_addc_u32 s18, 0, s19
	s_mul_i32 s19, s4, 0x4e441529
	s_mul_hi_u32 s20, s4, 0x4e441529
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s20, s4, 0xfe5163ab
	s_mul_hi_u32 s21, s4, 0xa2f9836e
	s_mul_i32 s4, s4, 0xa2f9836e
	s_cselect_b32 s22, s13, s15
	s_cselect_b32 s8, s8, s14
	s_cselect_b32 s13, s20, s13
	s_add_u32 s4, s19, s4
	s_addc_u32 s19, 0, s21
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s20, 0xffffffc0, 0
	s_cselect_b32 s14, s14, s18
	s_cselect_b32 s4, s15, s4
	s_cselect_b32 s15, s18, s19
	s_add_i32 s20, s20, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s20, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s18, s14, s4
	s_cselect_b32 s4, s4, s15
	s_cselect_b32 s14, s22, s14
	s_cselect_b32 s15, s8, s22
	s_cselect_b32 s8, s13, s8
	s_add_i32 s5, s5, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s13, 0xffffffe0, 0
	s_cselect_b32 s4, s18, s4
	s_cselect_b32 s18, s14, s18
	s_cselect_b32 s14, s15, s14
	s_cselect_b32 s8, s8, s15
	s_add_i32 s13, s13, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s13
	s_cmp_eq_u32 s13, 0
	v_mov_b32_e32 v6, s5
	s_cselect_b32 s13, -1, 0
	v_alignbit_b32 v7, s4, s18, v6
	v_alignbit_b32 v8, s18, s14, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s5, v7
	v_cndmask_b32_e64 v7, v8, s18, s13
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s4, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v8, s4, v7, 30
	s_bfe_u32 s5, s4, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s15, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v8, s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v8
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 23, v9
	v_alignbit_b32 v6, s14, s8, v6
	v_sub_nc_u32_e32 v10, 31, v9
	v_cndmask_b32_e64 v6, v6, s14, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v7, v7, v6, 30
	v_alignbit_b32 v6, v6, s8, 30
	s_lshr_b32 s8, s4, 29
	s_lshl_b32 s8, s8, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v7, s15, v7
	v_xor_b32_e32 v6, s15, v6
	s_or_b32 s13, s8, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, s13, v11
	v_alignbit_b32 v8, v8, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v6, v7, v6, v10
	v_alignbit_b32 v7, v8, v6, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v10, v7
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, 31, v10
	v_alignbit_b32 v6, v7, v6, v12
	v_lshrrev_b32_e32 v7, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v6, 9, v6
	v_or_b32_e32 v7, v7, v11
	v_add_nc_u32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v8, 23, v9
	v_sub_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, 0x3fc90fda, v7
	v_add_nc_u32_e32 v6, 0x33000000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3fc90fda, v7, -v8
	v_or_b32_e32 v6, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v7, v7, 0x33a22168, v9
	s_lshr_b32 s8, s4, 30
	s_mov_b32 s4, 0
	s_add_i32 s5, s5, s8
	v_fmac_f32_e32 v7, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v8, v7
	s_branch .LBB0_4
.LBB0_3:
	s_mov_b32 s4, -1
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $vgpr6
.LBB0_4:                                ; %Flow227
	v_mov_b32_e32 v7, s5
	v_mul_f32_e64 v8, 0x3f22f983, |v5|
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_6
; %bb.5:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v8
	v_fma_f32 v6, 0xbfc90fda, v7, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
.LBB0_6:                                ; %_ZL4cosff.exit
	s_load_b32 s4, s[0:1], 0x20
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_8
; %bb.7:
	s_and_b32 s3, s2, 0x7fffff
	s_lshr_b32 s5, s2, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s8, s3, 0xfe5163ab
	s_mul_i32 s13, s3, 0x3c439041
	s_mul_hi_u32 s14, s3, 0x3c439041
	s_add_u32 s8, s8, s13
	s_addc_u32 s13, 0, s14
	s_mul_i32 s14, s3, 0xdb629599
	s_mul_hi_u32 s15, s3, 0xdb629599
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s15
	s_mul_i32 s15, s3, 0xf534ddc0
	s_mul_hi_u32 s18, s3, 0xf534ddc0
	s_add_u32 s14, s14, s15
	s_addc_u32 s15, 0, s18
	s_mul_i32 s18, s3, 0xfc2757d1
	s_mul_hi_u32 s19, s3, 0xfc2757d1
	s_add_u32 s15, s15, s18
	s_addc_u32 s18, 0, s19
	s_mul_i32 s19, s3, 0x4e441529
	s_mul_hi_u32 s20, s3, 0x4e441529
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s20, s3, 0xfe5163ab
	s_mul_hi_u32 s21, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s22, s13, s15
	s_cselect_b32 s8, s8, s14
	s_cselect_b32 s13, s20, s13
	s_add_u32 s3, s19, s3
	s_addc_u32 s19, 0, s21
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s20, 0xffffffc0, 0
	s_cselect_b32 s14, s14, s18
	s_cselect_b32 s3, s15, s3
	s_cselect_b32 s15, s18, s19
	s_add_i32 s20, s20, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s20, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s18, s14, s3
	s_cselect_b32 s3, s3, s15
	s_cselect_b32 s14, s22, s14
	s_cselect_b32 s15, s8, s22
	s_cselect_b32 s8, s13, s8
	s_add_i32 s5, s5, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s13, 0xffffffe0, 0
	s_cselect_b32 s3, s18, s3
	s_cselect_b32 s18, s14, s18
	s_cselect_b32 s14, s15, s14
	s_cselect_b32 s8, s8, s15
	s_add_i32 s13, s13, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s13
	s_cmp_eq_u32 s13, 0
	v_mov_b32_e32 v9, s5
	s_cselect_b32 s13, -1, 0
	v_alignbit_b32 v10, s3, s18, v9
	v_alignbit_b32 v11, s18, s14, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s5, v10
	v_cndmask_b32_e64 v10, v11, s18, s13
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v11, s3, v10, 30
	s_bfe_u32 s5, s3, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s15, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v11, s15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v11
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v14, 23, v12
	v_alignbit_b32 v9, s14, s8, v9
	v_sub_nc_u32_e32 v13, 31, v12
	v_cndmask_b32_e64 v9, v9, s14, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v10, v10, v9, 30
	v_alignbit_b32 v9, v9, s8, 30
	s_lshr_b32 s8, s3, 29
	s_lshl_b32 s8, s8, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, s15, v10
	v_xor_b32_e32 v9, s15, v9
	s_or_b32 s13, s8, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, s13, v14
	v_alignbit_b32 v11, v11, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v9, v10, v9, v13
	v_alignbit_b32 v10, v11, v9, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v13, v10
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, 31, v13
	v_alignbit_b32 v9, v10, v9, v15
	v_lshrrev_b32_e32 v10, 9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v9, 9, v9
	v_or_b32_e32 v10, v10, v14
	v_add_nc_u32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v11, 23, v12
	v_sub_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v10
	v_add_nc_u32_e32 v9, 0x33000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v10, -v11
	v_or_b32_e32 v9, s8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v10, v10, 0x33a22168, v12
	s_lshr_b32 s8, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s5, s5, s8
	v_fmac_f32_e32 v10, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v9, v11, v10
	s_branch .LBB0_9
.LBB0_8:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $vgpr9
.LBB0_9:                                ; %Flow226
	v_mov_b32_e32 v10, s5
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_11
; %bb.10:
	v_rndne_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v8, |v5|
	v_cvt_i32_f32_e32 v10, v8
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v9, v8, 0xa7c234c4, v9
.LBB0_11:                               ; %_ZL4sinff.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v8, v6, v6 :: v_dual_mul_f32 v11, v9, v9
	s_mov_b32 s3, 0xb94c1982
	s_mov_b32 s5, 0x37d75334
	v_and_b32_e32 v14, 1, v7
	v_dual_fmaak_f32 v12, s3, v8, 0x3c0881c4 :: v_dual_fmaak_f32 v15, s3, v11, 0x3c0881c4
	v_dual_fmaak_f32 v13, s5, v8, 0xbab64f3b :: v_dual_fmaak_f32 v16, s5, v11, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v12, v8, v12, 0xbe2aaa9d :: v_dual_lshlrev_b32 v17, 30, v10
	v_lshlrev_b32_e32 v7, 30, v7
	v_dual_fmaak_f32 v13, v8, v13, 0x3d2aabf7 :: v_dual_fmaak_f32 v16, v11, v16, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v15, v11, v15, 0xbe2aaa9d :: v_dual_mul_f32 v12, v8, v12
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_dual_fmaak_f32 v13, v8, v13, 0xbf000004 :: v_dual_fmaak_f32 v16, v11, v16, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v15, v11, v15 :: v_dual_fmac_f32 v6, v6, v12
	v_xor_b32_e32 v12, s2, v5
	s_lshr_b32 s2, s16, 31
	v_fma_f32 v8, v8, v13, 1.0
	s_add_i32 s2, s16, s2
	s_lshr_b32 s3, s17, 31
	s_ashr_i32 s2, s2, 1
	v_fmac_f32_e32 v9, v9, v15
	v_cndmask_b32_e64 v6, -v6, v8, vcc_lo
	v_and_b32_e32 v8, 1, v10
	v_subrev_nc_u32_e32 v2, s2, v2
	s_add_i32 s3, s17, s3
	v_fma_f32 v11, v11, v16, 1.0
	s_ashr_i32 s3, s3, 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_subrev_nc_u32_e32 v3, s3, v3
	v_cvt_f32_i32_e32 v2, v2
	v_and_b32_e32 v10, 0x80000000, v17
	v_dual_cndmask_b32 v8, v11, v9 :: v_dual_and_b32 v7, 0x80000000, v7
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	s_mov_b32 s5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v12, v10
	v_cvt_f32_i32_e32 v10, v3
	v_xor_b32_e32 v6, v7, v6
	v_add_f32_e32 v3, 0.5, v2
	v_xor_b32_e32 v7, v9, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, 0.5, v10
	v_dual_cndmask_b32 v5, 0x7fc00000, v6 :: v_dual_add_f32 v2, -0.5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, 0x7fc00000, v7, vcc_lo
	v_add_f32_e32 v6, -0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, 0.5, v9 :: v_dual_mul_f32 v7, v2, v10
	v_mul_f32_e32 v8, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v14, v10
	v_fma_f32 v6, v6, v5, -v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v2, v5
	v_mul_f32_e32 v2, s10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, s9, v8
	v_div_scale_f32 v7, null, v6, v6, v2
	v_div_scale_f32 v12, vcc_lo, v2, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v12, v8
	v_fma_f32 v13, -v7, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v13, v8
	v_add_f32_e32 v13, 0.5, v3
	v_fma_f32 v7, -v7, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, v13, v10
	v_fmac_f32_e32 v15, v13, v5
	v_div_fmas_f32 v7, v7, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v14, v5, -v12
	v_div_fixup_f32 v2, v7, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v6, s10, v8 :: v_dual_add_f32 v7, s9, v15
	v_div_scale_f32 v8, null, s11, s11, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v11, null, v7, v7, v6
	v_div_scale_f32 v16, vcc_lo, v2, s11, v2
	v_rcp_f32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v8, v12, 1.0
	v_fma_f32 v15, -v11, v13, 1.0
	v_dual_fmac_f32 v13, v15, v13 :: v_dual_fmac_f32 v12, v14, v12
	v_div_scale_f32 v14, s2, v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v14, v13
	v_fma_f32 v19, -v11, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v19, v13
	v_mul_f32_e32 v15, v16, v12
	v_fma_f32 v11, -v11, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v8, v15, v16
	v_fmac_f32_e32 v15, v18, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v15, v16
	v_div_fmas_f32 v8, v8, v12, v15
	s_mov_b32 vcc_lo, s2
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s4, 31
	v_div_fmas_f32 v11, v11, v13, v17
	s_add_i32 s2, s4, s2
	v_div_fixup_f32 v2, v8, s11, v2
	s_ashr_i32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v6, v11, v7, v6
	v_div_scale_f32 v7, null, s11, s11, v6
	v_div_scale_f32 v13, vcc_lo, v6, s11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v7, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v7, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v7, -v7, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v7, v7, v11, v12
	v_cvt_f32_i32_e32 v11, s2
	v_div_fixup_f32 v6, v7, s11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v2, v11
	v_add_f32_e32 v7, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, v2, v7
	v_dual_cndmask_b32 v6, v7, v2 :: v_dual_cndmask_b32 v7, v2, v7
	v_floor_f32_e32 v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v2, v7
	v_cvt_i32_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v2, v2
	v_cmp_le_i32_e32 vcc_lo, v2, v8
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_19
; %bb.12:                               ; %.lr.ph176
	s_lshr_b32 s2, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s12, s2
	s_ashr_i32 s2, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v4, s2, v4
	s_load_b64 s[2:3], s[0:1], 0x28
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v10 :: v_dual_add_f32 v4, 0.5, v4
	v_fmac_f32_e32 v9, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, 0.5, v4
	v_dual_add_f32 v4, -0.5, v4 :: v_dual_mul_f32 v5, s9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v3, s10, v3 :: v_dual_mul_f32 v4, s10, v4
	v_div_scale_f32 v9, null, v5, v5, v3
	v_div_scale_f32 v12, vcc_lo, v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v12, v10
	v_fma_f32 v13, -v9, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v13, v10
	v_fma_f32 v9, -v9, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v10, v11
	v_div_scale_f32 v10, null, v5, v5, v4
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v10, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v12
	v_div_fixup_f32 v3, v9, v5, v3
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v9, null, s2, s2, v3
	v_div_scale_f32 v15, vcc_lo, v3, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v9, v11, 1.0
	v_fmac_f32_e32 v11, v13, v11
	v_div_scale_f32 v13, s0, v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v15, v11
	v_mul_f32_e32 v16, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v9, v14, v15
	v_fma_f32 v18, -v10, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v17, v11
	v_fmac_f32_e32 v16, v18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v9, v14, v15
	v_fma_f32 v10, -v10, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v9, v9, v11, v14
	s_mov_b32 vcc_lo, s0
	s_lshr_b32 s0, s3, 31
	v_div_fmas_f32 v10, v10, v12, v16
	s_add_i32 s0, s3, s0
	v_div_fixup_f32 v3, v9, s2, v3
	s_ashr_i32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v4, v10, v5, v4
	v_div_scale_f32 v5, null, s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v5, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, v4, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v5, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v13, v10 :: v_dual_sub_f32 v13, v6, v7
	v_fma_f32 v5, -v5, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v5, v10, v12
	v_cvt_f32_i32_e32 v10, s0
	v_div_fixup_f32 v4, v5, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v4, v10
	v_add_f32_e32 v10, v3, v10
	v_floor_f32_e32 v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v4, v10
	v_sub_f32_e32 v14, v10, v9
	v_cvt_i32_f32_e32 v11, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v12, v4
	v_mad_u64_u32 v[3:4], null, v11, s4, v[2:3]
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, v11, v12
.LBB0_13:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0, v2
	v_cmp_le_i32_e64 s1, s4, v2
	v_add_nc_u32_e32 v15, 1, v2
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s0
	s_xor_b32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_18
; %bb.14:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_cvt_f32_i32_e32 v4, v15
	v_cvt_f32_i32_e32 v5, v2
	s_mov_b32 s8, 0
	v_mov_b32_e32 v17, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, v6, v4
	v_cndmask_b32_e32 v16, v4, v6, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v7, v5
	v_dual_mov_b32 v4, v3 :: v_dual_cndmask_b32 v5, v5, v7
	v_sub_f32_e32 v16, v16, v5
.LBB0_15:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, -1, v17
	v_cmp_gt_i32_e64 s1, s3, v17
	v_add_nc_u32_e32 v18, 1, v17
	s_and_b32 s9, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s9
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=2
	v_ashrrev_i32_e32 v5, 31, v4
	v_cvt_f32_i32_e32 v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 2, v[4:5]
	v_add_co_u32 v19, vcc_lo, s6, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
	global_load_b32 v5, v[19:20], off
	global_load_b32 v19, v[0:1], off
	v_cvt_f32_i32_e32 v20, v18
	v_cmp_lt_f32_e32 vcc_lo, v10, v20
	v_cndmask_b32_e32 v20, v20, v10, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v9, v21
	v_cndmask_b32_e32 v21, v21, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v20, v21
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v5, v16, v5
	v_mul_f32_e32 v5, v20, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v20, null, v13, v13, v5
	v_div_scale_f32 v23, vcc_lo, v5, v13, v5
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v22, v21
	v_mul_f32_e32 v22, v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v20, v22, v23
	v_fmac_f32_e32 v22, v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v20, v22, v23
	v_div_fmas_f32 v20, v20, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v20, v13, v5
	v_div_scale_f32 v20, null, v14, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v21, 1.0
	v_fmac_f32_e32 v21, v22, v21
	v_div_scale_f32 v22, vcc_lo, v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v22, v21
	v_fma_f32 v24, -v20, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v21
	v_fma_f32 v20, -v20, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v20, v20, v21, v23
	v_div_fixup_f32 v5, v20, v14, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, v19, v5
	global_store_b32 v[0:1], v5, off
.LBB0_17:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_ge_i32_e32 vcc_lo, v17, v12
	v_dual_mov_b32 v17, v18 :: v_dual_add_nc_u32 v4, s4, v4
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_15
.LBB0_18:                               ; %Flow223
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_ge_i32_e32 vcc_lo, v2, v8
	v_dual_mov_b32 v2, v15 :: v_dual_add_nc_u32 v3, 1, v3
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_13
.LBB0_19:                               ; %.loopexit170
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21kernel_backprojectionPfS_ffffiffifiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21kernel_backprojectionPfS_ffffiffifiii, .Lfunc_end0-_Z21kernel_backprojectionPfS_ffffiffifiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3624
; NumSgprs: 25
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 64
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21kernel_backprojectionPfS_ffffiffifiii
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z21kernel_backprojectionPfS_ffffiffifiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
