__global__ void delta_stepping(int* V, int* E, int* W, int* n, int* s, int* delta, int* dist, int* predist, int* nowIsNull, int* quickBreak){
	
	const int u0 = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;  
	const int offset = blockDim.x * blockDim.y * blockDim.z; 
	const int localSize = 100; // malloc how many bucket

	int B[localSize]; 
	bool hadin[localSize]; 
	bool vis[localSize]; 
	int id = 0; // the bucket id
	int u = -1; 
	int pos = -1; // which point of the points each thread represents

	// init
	for(int i = 0; i < localSize; i++){
		B[i] = -1;
		hadin[i] = 0;
		vis[i] = 0;
	}

	if(u0 == (*s) % offset){
		pos = (*s) / offset;
		B[pos] = 0; // put source vertex into bucket 0
		vis[pos] = 1;
		hadin[pos] = 1;
	}

	__syncthreads();

	while(1){

		u = u0;
		while(u < (*n) && (*quickBreak) == 0){
			if(B[u / offset] != -1){ // at least one vertex is in bucket.
				atomicExch(quickBreak, 1);
				break;
			}
			u += offset;
		}

		__syncthreads();
		
		if(*quickBreak == 0){ 
			break;
		}
		
		
		while((*nowIsNull)){

			u = u0;
			while(u < *n){
				
				pos = u / offset;

				if(B[pos] == id){ 
					B[pos] = -1; 
					hadin[pos] = 1; 
					
					if(vis[pos]){ // tell the dist of the vertex is changed or not 
						vis[pos] = 0; 
						
						for(int j = V[u]; j < V[u + 1]; j++){ 
							if(W[j] <= (*delta)){ // light edge
								atomicMin(&predist[E[j]], dist[u] + W[j]);
							}
						}
					}
				} 
				u += offset;
			}

			*nowIsNull = 0; // set current bucket is empty
			__syncthreads();

			u = u0;
			while(u < (*n)){
				if(predist[u] < dist[u]){ 
					
					pos = u / offset; 

					dist[u] = predist[u]; // update dist
					B[pos] = dist[u] / (*delta); // calc after updating, it should be put into which bucket
					vis[pos] = 1; 

					if(B[pos] == id){ 
						// current bucket is not empty
						*nowIsNull = 1;
					}
				}
				u += offset;
			}
			__syncthreads();
		}

		// heavy edge
		u = u0;
		while(u < (*n)){
			pos = u / offset;
			if(hadin[pos]){ 
				hadin[pos] = 0; 
				
				for(int j = V[u]; j < V[u + 1]; j++){
					if(W[j] > (*delta)){ // heavy edge
						atomicMin(&predist[E[j]], dist[u] + W[j]);
					}
				}
			}
			u += offset;
		}
		__syncthreads();

		u = u0;
		while(u < (*n)){
			if(predist[u] < dist[u]){ 
				
				pos = u / offset; // calc offset

				dist[u] = predist[u]; // update dist
				B[pos] = dist[u] / (*delta); // calc it should belong to which buket after updating.
				vis[pos] = 1; // record it's updated
				
			}
			u += offset;
		}

		id += 1; // enter to next bucket
		*nowIsNull = 1; // assume the next bucket has vertex
		*quickBreak = 0; 
		__syncthreads();
	}	
}
	.file	"tmpxft_002c9872_00000000-6_delta.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z14delta_steppingPiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_
	.type	_Z52__device_stub__Z14delta_steppingPiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_, @function
_Z52__device_stub__Z14delta_steppingPiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z52__device_stub__Z14delta_steppingPiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_, .-_Z52__device_stub__Z14delta_steppingPiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_
	.globl	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.type	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_, @function
_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z14delta_steppingPiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_, .-_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void delta_stepping(int* V, int* E, int* W, int* n, int* s, int* delta, int* dist, int* predist, int* nowIsNull, int* quickBreak){
	
	const int u0 = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;  
	const int offset = blockDim.x * blockDim.y * blockDim.z; 
	const int localSize = 100; // malloc how many bucket

	int B[localSize]; 
	bool hadin[localSize]; 
	bool vis[localSize]; 
	int id = 0; // the bucket id
	int u = -1; 
	int pos = -1; // which point of the points each thread represents

	// init
	for(int i = 0; i < localSize; i++){
		B[i] = -1;
		hadin[i] = 0;
		vis[i] = 0;
	}

	if(u0 == (*s) % offset){
		pos = (*s) / offset;
		B[pos] = 0; // put source vertex into bucket 0
		vis[pos] = 1;
		hadin[pos] = 1;
	}

	__syncthreads();

	while(1){

		u = u0;
		while(u < (*n) && (*quickBreak) == 0){
			if(B[u / offset] != -1){ // at least one vertex is in bucket.
				atomicExch(quickBreak, 1);
				break;
			}
			u += offset;
		}

		__syncthreads();
		
		if(*quickBreak == 0){ 
			break;
		}
		
		
		while((*nowIsNull)){

			u = u0;
			while(u < *n){
				
				pos = u / offset;

				if(B[pos] == id){ 
					B[pos] = -1; 
					hadin[pos] = 1; 
					
					if(vis[pos]){ // tell the dist of the vertex is changed or not 
						vis[pos] = 0; 
						
						for(int j = V[u]; j < V[u + 1]; j++){ 
							if(W[j] <= (*delta)){ // light edge
								atomicMin(&predist[E[j]], dist[u] + W[j]);
							}
						}
					}
				} 
				u += offset;
			}

			*nowIsNull = 0; // set current bucket is empty
			__syncthreads();

			u = u0;
			while(u < (*n)){
				if(predist[u] < dist[u]){ 
					
					pos = u / offset; 

					dist[u] = predist[u]; // update dist
					B[pos] = dist[u] / (*delta); // calc after updating, it should be put into which bucket
					vis[pos] = 1; 

					if(B[pos] == id){ 
						// current bucket is not empty
						*nowIsNull = 1;
					}
				}
				u += offset;
			}
			__syncthreads();
		}

		// heavy edge
		u = u0;
		while(u < (*n)){
			pos = u / offset;
			if(hadin[pos]){ 
				hadin[pos] = 0; 
				
				for(int j = V[u]; j < V[u + 1]; j++){
					if(W[j] > (*delta)){ // heavy edge
						atomicMin(&predist[E[j]], dist[u] + W[j]);
					}
				}
			}
			u += offset;
		}
		__syncthreads();

		u = u0;
		while(u < (*n)){
			if(predist[u] < dist[u]){ 
				
				pos = u / offset; // calc offset

				dist[u] = predist[u]; // update dist
				B[pos] = dist[u] / (*delta); // calc it should belong to which buket after updating.
				vis[pos] = 1; // record it's updated
				
			}
			u += offset;
		}

		id += 1; // enter to next bucket
		*nowIsNull = 1; // assume the next bucket has vertex
		*quickBreak = 0; 
		__syncthreads();
	}	
}
	.text
	.file	"delta.hip"
	.globl	_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_ # -- Begin function _Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_
	.type	_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_,@function
_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_: # @_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_,@object # @_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_:
	.quad	_Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_
	.size	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__delta_steppingPiS_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_ ; -- Begin function _Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.globl	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_,@function
_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_: ; @_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x5c
	v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, -1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	scratch_store_b32 v1, v2, off
	v_add_nc_u32_e32 v1, 4, v1
	s_add_i32 s5, s4, 0x1a0
	s_add_i32 s6, s4, 0x210
	s_add_i32 s4, s4, 1
	scratch_store_b8 off, v3, s5
	scratch_store_b8 off, v3, s6
	s_cmpk_eq_i32 s4, 0x64
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_lshr_b32 s20, s2, 16
	s_and_b32 s21, s2, 0xffff
	s_load_b512 s[4:19], s[0:1], 0x0
	s_and_b32 s2, s3, 0xffff
	s_mul_i32 s3, s20, s21
	v_bfe_u32 v4, v0, 20, 10
	s_mul_i32 s2, s3, s2
	v_and_b32_e32 v2, 0x3ff, v0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s2, s3
	s_xor_b32 s24, s22, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s24
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s22, s[12:13], 0x0
	s_sub_i32 s12, 0, s24
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v1
	v_bfe_u32 v1, v0, 10, 10
	v_readfirstlane_b32 s13, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u32_u24 v4, v4, s20, v1
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s23, s22, 31
	s_mul_i32 s25, s12, s13
	s_add_i32 s26, s22, s23
	s_mul_hi_u32 s25, s13, s25
	s_xor_b32 s26, s26, s23
	s_add_i32 s13, s13, s25
	s_xor_b32 s23, s23, s3
	s_mul_hi_u32 s13, s26, s13
	v_mad_u64_u32 v[0:1], null, v4, s21, v[2:3]
	s_mul_i32 s25, s13, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s25, s26, s25
	s_add_i32 s26, s13, 1
	s_sub_i32 s27, s25, s24
	s_cmp_ge_u32 s25, s24
	s_cselect_b32 s13, s26, s13
	s_cselect_b32 s20, s27, s25
	s_add_i32 s25, s13, 1
	s_cmp_ge_u32 s20, s24
	s_cselect_b32 s13, s25, s13
	s_mov_b32 s25, 0
	s_xor_b32 s13, s13, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s13, s13, s23
	s_mul_i32 s20, s13, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s20, s22, s20
	v_cmp_eq_u32_e32 vcc_lo, s20, v0
	s_and_saveexec_b32 s20, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1
	s_lshl_b32 s21, s13, 2
	s_add_i32 s22, s13, 0x210
	s_add_i32 s21, s21, 16
	s_addk_i32 s13, 0x1a0
	scratch_store_b32 off, v1, s21
	scratch_store_b8 off, v2, s22
	scratch_store_b8 off, v2, s13
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s20
	v_mul_lo_u32 v1, s12, v3
	s_load_b128 s[20:23], s[0:1], 0x40
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v15, 1
	s_lshl_b64 s[12:13], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	v_mov_b32_e32 v17, -1
	v_mul_hi_u32 v4, v3, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_nc_u32_e32 v16, v3, v4
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;     Child Loop BB0_14 Depth 2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;         Child Loop BB0_21 Depth 4
                                        ;       Child Loop BB0_30 Depth 3
                                        ;     Child Loop BB0_37 Depth 2
                                        ;       Child Loop BB0_40 Depth 3
                                        ;     Child Loop BB0_48 Depth 2
	buffer_gl0_inv
	global_load_b32 v3, v14, s[10:11]
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v3
	s_cbranch_execz .LBB0_13
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=1
	global_load_b32 v4, v14, s[22:23]
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB0_13
; %bb.7:                                ; %.lr.ph.split.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v4, v0
	s_mov_b32 s1, 0
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $sgpr27
.LBB0_8:                                ; %.lr.ph.split
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_or_b32 s27, s27, exec_lo
	s_or_b32 s28, s28, exec_lo
	s_mov_b32 s29, exec_lo
	v_add_nc_u32_e32 v6, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v5
	v_xor_b32_e32 v5, s3, v5
	v_mul_hi_u32 v7, v6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v7, s24
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_nc_u32_e32 v8, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v9, s24, v6
	v_cmp_le_u32_e32 vcc_lo, s24, v6
	v_dual_cndmask_b32 v7, v7, v8 :: v_dual_cndmask_b32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s24, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v6, v5
	v_lshl_add_u32 v5, v5, 2, 16
	scratch_load_b32 v5, v5, off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 -1, v5
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=2
	v_add_nc_u32_e32 v4, s2, v4
	s_and_not1_b32 s28, s28, exec_lo
	s_and_not1_b32 s27, s27, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v4, v3
	s_and_b32 s30, vcc_lo, exec_lo
	s_or_b32 s28, s28, s30
; %bb.10:                               ; %Flow249
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s29, exec_lo, s28
	s_or_b32 s1, s29, s1
	s_and_not1_b32 s26, s26, exec_lo
	s_and_b32 s29, s27, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s26, s26, s29
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_8
; %bb.11:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_5 Depth=1
	global_atomic_swap_b32 v14, v15, s[22:23]
.LBB0_13:                               ; %.critedge
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v3, v14, s[22:23]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_cbranch_vccnz .LBB0_52
.LBB0_14:                               ; %.preheader153
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;         Child Loop BB0_21 Depth 4
                                        ;       Child Loop BB0_30 Depth 3
	global_load_b32 v3, v14, s[20:21]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_cbranch_vccnz .LBB0_35
; %bb.15:                               ; %.preheader
                                        ;   in Loop: Header=BB0_14 Depth=2
	global_load_b32 v10, v14, s[10:11]
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v10
	s_cbranch_execz .LBB0_28
; %bb.16:                               ; %.lr.ph160.preheader
                                        ;   in Loop: Header=BB0_14 Depth=2
	v_mov_b32_e32 v3, v0
	s_mov_b32 s26, 0
.LBB0_17:                               ; %.lr.ph160
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_21 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_mov_b32 s27, exec_lo
	v_add_nc_u32_e32 v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_mul_hi_u32 v6, v5, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v6, s24
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s24, v5
	v_cmp_le_u32_e32 vcc_lo, s24, v5
	v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
	v_xor_b32_e32 v8, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 1, v6
	v_cmp_le_u32_e32 vcc_lo, s24, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v6, v7, vcc_lo
	v_xor_b32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v5, v8
	v_lshl_add_u32 v5, v6, 2, 16
	scratch_load_b32 v7, v5, off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 s25, v7
	s_cbranch_execz .LBB0_27
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=3
	v_add_nc_u32_e32 v11, 0x210, v6
	v_add_nc_u32_e32 v6, 0x1a0, v6
	s_mov_b32 s28, exec_lo
	scratch_load_u8 v7, v11, off
	scratch_store_b32 v5, v17, off
	scratch_store_b8 v6, v15, off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v7
	s_cbranch_execz .LBB0_26
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=3
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	s_mov_b32 s29, exec_lo
	scratch_store_b8 v11, v14, off
	v_add_co_u32 v4, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v6, v7
	s_cbranch_execz .LBB0_25
; %bb.20:                               ; %.lr.ph158
                                        ;   in Loop: Header=BB0_17 Depth=3
	v_ashrrev_i32_e32 v11, 31, v6
	v_mov_b32_e32 v10, v6
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[10:11]
	s_mov_b32 s30, 0
	v_add_co_u32 v10, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
.LBB0_21:                               ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ;       Parent Loop BB0_17 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v18, v[10:11], off
	global_load_b32 v19, v14, s[14:15]
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_le_i32_e64 v18, v19
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=4
	global_load_b32 v19, v[12:13], off
	global_load_b32 v7, v[8:9], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v20, 31, v19
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_u32 v19, vcc_lo, s18, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v20, vcc_lo
	global_atomic_min_i32 v[19:20], v7, off
	global_load_b32 v7, v[4:5], off offset:4
.LBB0_23:                               ;   in Loop: Header=BB0_21 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v6, v7
	v_add_co_u32 v12, s0, v12, 4
	v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
	s_or_b32 s30, vcc_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB0_21
; %bb.24:                               ; %.loopexit.loopexit
                                        ;   in Loop: Header=BB0_17 Depth=3
	s_or_b32 exec_lo, exec_lo, s30
	global_load_b32 v10, v14, s[10:11]
.LBB0_25:                               ; %Flow242
                                        ;   in Loop: Header=BB0_17 Depth=3
	s_or_b32 exec_lo, exec_lo, s29
.LBB0_26:                               ; %Flow243
                                        ;   in Loop: Header=BB0_17 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s28
.LBB0_27:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_17 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v3, s2, v3
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v3, v10
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_17
.LBB0_28:                               ; %Flow245
                                        ;   in Loop: Header=BB0_14 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	global_store_b32 v14, v14, s[20:21]
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v3, v14, s[10:11]
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v3
	s_cbranch_execz .LBB0_34
; %bb.29:                               ; %.lr.ph163.preheader
                                        ;   in Loop: Header=BB0_14 Depth=2
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v7, v0
	s_mov_b32 s26, 0
.LBB0_30:                               ; %.lr.ph163
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v4, vcc_lo
	s_mov_b32 s27, exec_lo
	global_load_b32 v8, v[8:9], off
	global_load_b32 v9, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v8, v9
	s_cbranch_execz .LBB0_33
; %bb.31:                               ;   in Loop: Header=BB0_30 Depth=3
	global_store_b32 v[5:6], v8, off
	global_load_b32 v5, v14, s[14:15]
	v_ashrrev_i32_e32 v12, 31, v8
	v_ashrrev_i32_e32 v11, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v12
	v_add_nc_u32_e32 v13, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v12
	v_xor_b32_e32 v13, v13, v11
	v_xor_b32_e32 v11, s3, v11
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v6
	v_xor_b32_e32 v5, v5, v6
	v_xor_b32_e32 v6, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v9, v5
	v_sub_nc_u32_e32 v10, 0, v5
	v_rcp_iflag_f32_e32 v9, v9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, 0x4f7ffffe, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v9, v9
	v_mul_lo_u32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v10, v9, v10
	v_add_nc_u32_e32 v9, v9, v10
	v_mul_hi_u32 v10, v13, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v8, v9
	v_mul_lo_u32 v18, v10, s24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v9, v5
	v_sub_nc_u32_e32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v19
	v_subrev_nc_u32_e32 v19, s24, v13
	v_cmp_le_u32_e32 vcc_lo, s24, v13
	v_add_nc_u32_e32 v18, 1, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e64 s0, v8, v5
	v_dual_cndmask_b32 v13, v13, v19 :: v_dual_cndmask_b32 v10, v10, v18
	v_sub_nc_u32_e32 v18, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s24, v13
	v_add_nc_u32_e32 v19, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v8, v18, s0
	v_cndmask_b32_e32 v10, v10, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e32 vcc_lo, v8, v5
	v_add_nc_u32_e32 v20, 1, v9
	v_xor_b32_e32 v8, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v9, v20, s0
	v_sub_nc_u32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v18, 1, v9
	v_cndmask_b32_e32 v5, v9, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v6
	v_sub_nc_u32_e32 v5, v5, v6
	v_lshl_add_u32 v6, v8, 2, 16
	v_add_nc_u32_e32 v8, 0x210, v8
	scratch_store_b32 v6, v5, off
	scratch_store_b8 v8, v15, off
	v_cmp_eq_u32_e32 vcc_lo, s25, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_30 Depth=3
	global_store_b32 v14, v15, s[20:21]
.LBB0_33:                               ;   in Loop: Header=BB0_30 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	global_load_b32 v5, v14, s[10:11]
	v_add_nc_u32_e32 v7, s2, v7
	v_add_co_u32 v3, s0, v3, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v7, v5
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_30
.LBB0_34:                               ; %Flow241
                                        ;   in Loop: Header=BB0_14 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_branch .LBB0_14
.LBB0_35:                               ; %.preheader152
                                        ;   in Loop: Header=BB0_5 Depth=1
	global_load_b32 v10, v14, s[10:11]
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v10
	s_cbranch_execz .LBB0_46
; %bb.36:                               ; %.lr.ph170.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v3, v0
	s_mov_b32 s26, 0
.LBB0_37:                               ; %.lr.ph170
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_40 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_mov_b32 s27, exec_lo
	v_add_nc_u32_e32 v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_mul_hi_u32 v6, v5, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v6, s24
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s24, v5
	v_cmp_le_u32_e32 vcc_lo, s24, v5
	v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
	v_xor_b32_e32 v8, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 1, v6
	v_cmp_le_u32_e32 vcc_lo, s24, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v6, v7, vcc_lo
	v_xor_b32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v8
	v_add_nc_u32_e32 v11, 0x1a0, v5
	scratch_load_u8 v5, v11, off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v5
	s_cbranch_execz .LBB0_45
; %bb.38:                               ;   in Loop: Header=BB0_37 Depth=2
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	s_mov_b32 s28, exec_lo
	scratch_store_b8 v11, v14, off
	v_add_co_u32 v4, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v6, v7
	s_cbranch_execz .LBB0_44
; %bb.39:                               ; %.lr.ph168
                                        ;   in Loop: Header=BB0_37 Depth=2
	v_ashrrev_i32_e32 v11, 31, v6
	v_mov_b32_e32 v10, v6
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[10:11]
	s_mov_b32 s29, 0
	v_add_co_u32 v10, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
.LBB0_40:                               ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v18, v[10:11], off
	global_load_b32 v19, v14, s[14:15]
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v18, v19
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_40 Depth=3
	global_load_b32 v19, v[12:13], off
	global_load_b32 v7, v[8:9], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v20, 31, v19
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_u32 v19, vcc_lo, s18, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v20, vcc_lo
	global_atomic_min_i32 v[19:20], v7, off
	global_load_b32 v7, v[4:5], off offset:4
.LBB0_42:                               ;   in Loop: Header=BB0_40 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v6, v7
	v_add_co_u32 v12, s0, v12, 4
	v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
	s_or_b32 s29, vcc_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB0_40
; %bb.43:                               ; %.loopexit151.loopexit
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
	global_load_b32 v10, v14, s[10:11]
.LBB0_44:                               ; %Flow236
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
.LBB0_45:                               ; %.loopexit151
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v3, s2, v3
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v3, v10
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_37
.LBB0_46:                               ; %Flow238
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v8, v14, s[10:11]
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v8
	s_cbranch_execz .LBB0_51
; %bb.47:                               ; %.lr.ph174.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v7, v0
	s_mov_b32 s26, 0
.LBB0_48:                               ; %.lr.ph174
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v4, vcc_lo
	s_mov_b32 s27, exec_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v9, v10
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_48 Depth=2
	global_store_b32 v[5:6], v9, off
	s_clause 0x1
	global_load_b32 v5, v14, s[14:15]
	global_load_b32 v8, v14, s[10:11]
	v_ashrrev_i32_e32 v12, 31, v7
	v_ashrrev_i32_e32 v18, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, v7, v12
	v_add_nc_u32_e32 v9, v9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v13, v13, v12
	v_xor_b32_e32 v9, v9, v18
	v_xor_b32_e32 v12, s3, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v19, v13, v16
	v_add_nc_u32_e32 v20, 1, v19
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v6
	v_xor_b32_e32 v5, v5, v6
	v_xor_b32_e32 v6, v18, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v10, v5
	v_sub_nc_u32_e32 v11, 0, v5
	v_rcp_iflag_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v10, v10
	v_mul_lo_u32 v11, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v10, v11
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_lo_u32 v11, v19, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v13, v11
	v_subrev_nc_u32_e32 v21, s24, v11
	v_cmp_le_u32_e32 vcc_lo, s24, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v11, v21, vcc_lo
	v_cndmask_b32_e32 v19, v19, v20, vcc_lo
	v_mul_hi_u32 v10, v9, v10
	v_cmp_le_u32_e64 s0, s24, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v13, v10, v5
	v_sub_nc_u32_e32 v9, v9, v13
	v_add_nc_u32_e32 v13, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v9, v5
	v_cmp_ge_u32_e32 vcc_lo, v9, v5
	v_dual_cndmask_b32 v9, v9, v21 :: v_dual_add_nc_u32 v20, 1, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v10, v13, vcc_lo
	v_cndmask_b32_e64 v11, v19, v20, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e32 vcc_lo, v9, v5
	v_add_nc_u32_e32 v13, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v11, v12
	v_cndmask_b32_e32 v5, v10, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v11, v12
	v_xor_b32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v10, v9, 2, 16
	v_sub_nc_u32_e32 v5, v5, v6
	v_add_nc_u32_e32 v6, 0x210, v9
	scratch_store_b32 v10, v5, off
	scratch_store_b8 v6, v15, off
.LBB0_50:                               ;   in Loop: Header=BB0_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v7, s2, v7
	v_add_co_u32 v3, s0, v3, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v7, v8
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_48
.LBB0_51:                               ; %Flow235
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s25, s25, 1
	s_clause 0x1
	global_store_b32 v14, v15, s[20:21]
	global_store_b32 v14, v14, s[22:23]
	s_waitcnt_vscnt null, 0x0
	s_mov_b32 s0, 0
	s_barrier
	s_branch .LBB0_53
.LBB0_52:                               ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr25
.LBB0_53:                               ; %Flow251
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_5
; %bb.54:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 640
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3128
; NumSgprs: 33
; NumVgprs: 22
; ScratchSize: 640
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14delta_steppingPiS_S_S_S_S_S_S_S_S_
    .private_segment_fixed_size: 640
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         _Z14delta_steppingPiS_S_S_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
