#include "includes.h"
__global__ void normal_eqs_flow_GPU(float *d_CO, const float2 *d_flow_compact, const float *d_Zbuffer_flow_compact, const int *d_ind_flow_Zbuffer, float fx, float fy, float ox, float oy, int n_rows, int n_cols, const int *d_n_values_flow, const int *d_start_ind_flow) {

int n_val_accum = gridDim.x * blockDim.x; // _MAX_N_VAL_ACCUM may not be
// multiple of blocksize

int n_flow = d_n_values_flow[blockIdx.y];
int n_accum = (int)ceilf((float)n_flow / (float)n_val_accum);
int start_ind = d_start_ind_flow[blockIdx.y];

// initialize accumulators

float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f;

for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {

if (in_ind < n_flow) { // is this a valid sample?

// fetch flow and Zbuffer from global memory
float2 u = d_flow_compact[in_ind + start_ind];
float disp = __fdividef(1.0f, d_Zbuffer_flow_compact[in_ind + start_ind]);

// compute coordinates
int pixel_ind = d_ind_flow_Zbuffer[in_ind + start_ind];
bool is_ar_flow = (pixel_ind >= (n_rows * n_cols));
pixel_ind -= (int)is_ar_flow * n_rows * n_cols;

float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;

x = x - ox;
y = y - oy;

/************************/
/* evaluate constraints */
/************************/

// unique values A-matrix
A0 += (disp * disp * fx * fx);
A1 += (-disp * disp * x * fx);
A2 += (-disp * x * y);
A3 += (disp * fx * fx + disp * x * x);
A4 += (-disp * y * fx);
A5 += (-disp * disp * y * fy);
A6 += (-disp * fy * fy - disp * y * y); //!!!!
A7 += (disp * x * fy);
A8 += (disp * disp * x * x + disp * disp * y * y);
A9 += (disp * x * x * y / fx + disp * y * fy + disp * y * y * y / fy);
A10 += (-disp * x * fx - disp * x * x * x / fx - disp * x * y * y / fy);
A11 += (x * x * y * y / (fx * fx) + fy * fy + 2.0f * y * y +
y * y * y * y / (fy * fy));
A12 += (-2.0f * x * y - x * x * x * y / (fx * fx) -
x * y * y * y / (fy * fy));
A13 += (x * y * y / fx - x * fy - x * y * y / fy);
A14 += (fx * fx + 2.0f * x * x + x * x * x * x / (fx * fx) +
x * x * y * y / (fy * fy));
A15 += (-y * fx - x * x * y / fx + x * x * y / fy);
A16 += (x * x + y * y);

// B-vector

A17 += (disp * u.x * fx);
A18 += (disp * u.y * fy);
A19 += (-disp * x * u.x - disp * y * u.y);
A20 += (-x * y * u.x / fx - u.y * fy - u.y * y * y / fy);
A21 += (u.x * fx + x * x * u.x / fx + x * y * u.y / fy);
A22 += (-y * u.x + x * u.y);
}
}

/**************************/
/* write out accumulators */
/**************************/

int out_ind =
23 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;

d_CO[out_ind] = A0;
d_CO[out_ind + n_val_accum] = A1;
d_CO[out_ind + 2 * n_val_accum] = A2;
d_CO[out_ind + 3 * n_val_accum] = A3;
d_CO[out_ind + 4 * n_val_accum] = A4;
d_CO[out_ind + 5 * n_val_accum] = A5;
d_CO[out_ind + 6 * n_val_accum] = A6;
d_CO[out_ind + 7 * n_val_accum] = A7;
d_CO[out_ind + 8 * n_val_accum] = A8;
d_CO[out_ind + 9 * n_val_accum] = A9;
d_CO[out_ind + 10 * n_val_accum] = A10;
d_CO[out_ind + 11 * n_val_accum] = A11;
d_CO[out_ind + 12 * n_val_accum] = A12;
d_CO[out_ind + 13 * n_val_accum] = A13;
d_CO[out_ind + 14 * n_val_accum] = A14;
d_CO[out_ind + 15 * n_val_accum] = A15;
d_CO[out_ind + 16 * n_val_accum] = A16;
d_CO[out_ind + 17 * n_val_accum] = A17;
d_CO[out_ind + 18 * n_val_accum] = A18;
d_CO[out_ind + 19 * n_val_accum] = A19;
d_CO[out_ind + 20 * n_val_accum] = A20;
d_CO[out_ind + 21 * n_val_accum] = A21;
d_CO[out_ind + 22 * n_val_accum] = A22;
}
	.file	"tmpxft_00392751_00000000-6_normal_eqs_flow_GPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z66__device_stub__Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_PfPK6float2PKfPKiffffiiS6_S6_
	.type	_Z66__device_stub__Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_PfPK6float2PKfPKiffffiiS6_S6_, @function
_Z66__device_stub__Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_PfPK6float2PKfPKiffffiiS6_S6_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movl	%r8d, 28(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 36(%rsp)
	movss	%xmm3, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z66__device_stub__Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_PfPK6float2PKfPKiffffiiS6_S6_, .-_Z66__device_stub__Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_PfPK6float2PKfPKiffffiiS6_S6_
	.globl	_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_
	.type	_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_, @function
_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_PfPK6float2PKfPKiffffiiS6_S6_
	.cfi_endproc
.LFE2033:
	.size	_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_, .-_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19normal_eqs_flow_GPUPfPK6float2PKfPKiffffiiS6_S6_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normal_eqs_flow_GPU(float *d_CO, const float2 *d_flow_compact, const float *d_Zbuffer_flow_compact, const int *d_ind_flow_Zbuffer, float fx, float fy, float ox, float oy, int n_rows, int n_cols, const int *d_n_values_flow, const int *d_start_ind_flow) {

int n_val_accum = gridDim.x * blockDim.x; // _MAX_N_VAL_ACCUM may not be
// multiple of blocksize

int n_flow = d_n_values_flow[blockIdx.y];
int n_accum = (int)ceilf((float)n_flow / (float)n_val_accum);
int start_ind = d_start_ind_flow[blockIdx.y];

// initialize accumulators

float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f;

for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {

if (in_ind < n_flow) { // is this a valid sample?

// fetch flow and Zbuffer from global memory
float2 u = d_flow_compact[in_ind + start_ind];
float disp = __fdividef(1.0f, d_Zbuffer_flow_compact[in_ind + start_ind]);

// compute coordinates
int pixel_ind = d_ind_flow_Zbuffer[in_ind + start_ind];
bool is_ar_flow = (pixel_ind >= (n_rows * n_cols));
pixel_ind -= (int)is_ar_flow * n_rows * n_cols;

float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;

x = x - ox;
y = y - oy;

/************************/
/* evaluate constraints */
/************************/

// unique values A-matrix
A0 += (disp * disp * fx * fx);
A1 += (-disp * disp * x * fx);
A2 += (-disp * x * y);
A3 += (disp * fx * fx + disp * x * x);
A4 += (-disp * y * fx);
A5 += (-disp * disp * y * fy);
A6 += (-disp * fy * fy - disp * y * y); //!!!!
A7 += (disp * x * fy);
A8 += (disp * disp * x * x + disp * disp * y * y);
A9 += (disp * x * x * y / fx + disp * y * fy + disp * y * y * y / fy);
A10 += (-disp * x * fx - disp * x * x * x / fx - disp * x * y * y / fy);
A11 += (x * x * y * y / (fx * fx) + fy * fy + 2.0f * y * y +
y * y * y * y / (fy * fy));
A12 += (-2.0f * x * y - x * x * x * y / (fx * fx) -
x * y * y * y / (fy * fy));
A13 += (x * y * y / fx - x * fy - x * y * y / fy);
A14 += (fx * fx + 2.0f * x * x + x * x * x * x / (fx * fx) +
x * x * y * y / (fy * fy));
A15 += (-y * fx - x * x * y / fx + x * x * y / fy);
A16 += (x * x + y * y);

// B-vector

A17 += (disp * u.x * fx);
A18 += (disp * u.y * fy);
A19 += (-disp * x * u.x - disp * y * u.y);
A20 += (-x * y * u.x / fx - u.y * fy - u.y * y * y / fy);
A21 += (u.x * fx + x * x * u.x / fx + x * y * u.y / fy);
A22 += (-y * u.x + x * u.y);
}
}

/**************************/
/* write out accumulators */
/**************************/

int out_ind =
23 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;

d_CO[out_ind] = A0;
d_CO[out_ind + n_val_accum] = A1;
d_CO[out_ind + 2 * n_val_accum] = A2;
d_CO[out_ind + 3 * n_val_accum] = A3;
d_CO[out_ind + 4 * n_val_accum] = A4;
d_CO[out_ind + 5 * n_val_accum] = A5;
d_CO[out_ind + 6 * n_val_accum] = A6;
d_CO[out_ind + 7 * n_val_accum] = A7;
d_CO[out_ind + 8 * n_val_accum] = A8;
d_CO[out_ind + 9 * n_val_accum] = A9;
d_CO[out_ind + 10 * n_val_accum] = A10;
d_CO[out_ind + 11 * n_val_accum] = A11;
d_CO[out_ind + 12 * n_val_accum] = A12;
d_CO[out_ind + 13 * n_val_accum] = A13;
d_CO[out_ind + 14 * n_val_accum] = A14;
d_CO[out_ind + 15 * n_val_accum] = A15;
d_CO[out_ind + 16 * n_val_accum] = A16;
d_CO[out_ind + 17 * n_val_accum] = A17;
d_CO[out_ind + 18 * n_val_accum] = A18;
d_CO[out_ind + 19 * n_val_accum] = A19;
d_CO[out_ind + 20 * n_val_accum] = A20;
d_CO[out_ind + 21 * n_val_accum] = A21;
d_CO[out_ind + 22 * n_val_accum] = A22;
}
	.text
	.file	"normal_eqs_flow_GPU.hip"
	.globl	_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_ # -- Begin function _Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.type	_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_,@function
_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_: # @_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	28(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	24(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	20(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	16(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	12(%rsp), %r15
	movl	%r8d, (%r15)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r14, 56(%rbx)
	movq	%r15, 64(%rbx)
	movq	%r8, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_, .Lfunc_end0-_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_,@object # @_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.section	.rodata,"a",@progbits
	.globl	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.p2align	3, 0x0
_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_:
	.quad	_Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.size	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_"
	.size	.L__unnamed_1, 70

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_ ; -- Begin function _Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.globl	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
	.p2align	8
	.type	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_,@function
_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_: ; @_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x54
	s_load_b128 s[4:7], s[0:1], 0x38
	s_mov_b32 s26, s15
	s_mov_b32 s27, 0
	s_load_b32 s9, s[0:1], 0x48
	s_lshl_b64 s[2:3], s[26:27], 2
	s_load_b256 s[16:23], s[0:1], 0x0
	v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v21, 0
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v16, 0
	v_mov_b32_e32 v17, 0
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, 0
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v18, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s8, 0xffff
	s_add_u32 s4, s4, s2
	s_addc_u32 s5, s5, s3
	s_mul_i32 s25, s14, s11
	s_load_b32 s30, s[4:5], 0x0
	s_mul_i32 s24, s9, s11
	s_add_i32 s4, s25, s11
	v_cvt_f32_i32_e32 v1, s24
	v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v20, 0
	s_mov_b32 s31, exec_lo
	v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v24, 0
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v8, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v2, s30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v1, v1, v2
	v_div_scale_f32 v6, vcc_lo, v2, v1, v2
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v5, v6
	v_mov_b32_e32 v6, 0
	v_div_fmas_f32 v3, v3, v4, v5
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v3, v1, v2
	v_ceil_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s25, v3, v[0:1]
	v_mul_lo_u32 v27, s4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v1, v27
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[28:29], s[0:1], 0x30
	s_load_b128 s[12:15], s[0:1], 0x20
	s_add_u32 s0, s6, s2
	s_addc_u32 s1, s7, s3
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v25, 0
	s_load_b32 s33, s[0:1], 0x0
	v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v21, 0
	v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v17, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v28, s29
	v_mul_f32_e64 v29, s12, s12
	v_mul_f32_e64 v30, s13, s13
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v15, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mul_i32 s34, s29, s28
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s35, exec_lo
	v_cmpx_gt_i32_e64 s30, v1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v2, s33, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[31:32], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v33, vcc_lo, s22, v31
	v_add_co_ci_u32_e32 v34, vcc_lo, s23, v32, vcc_lo
	v_add_co_u32 v31, vcc_lo, s20, v31
	v_add_co_ci_u32_e32 v32, vcc_lo, s21, v32, vcc_lo
	global_load_b32 v33, v[33:34], off
	v_add_co_u32 v2, vcc_lo, s18, v2
	global_load_b32 v31, v[31:32], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(2)
	v_cmp_le_i32_e32 vcc_lo, s34, v33
	v_cndmask_b32_e64 v32, 0, s28, vcc_lo
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v39, vcc_lo, 1.0, v31, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v32, v32, s29
	v_sub_nc_u32_e32 v32, v33, v32
	v_div_scale_f32 v33, null, v31, v31, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v32, v32
	v_rcp_f32_e32 v35, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v34, null, v28, v28, v32
	v_rcp_f32_e32 v36, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v37, -v33, v35, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v37, v35
	v_div_scale_f32 v37, s0, v32, v28, v32
	v_fma_f32 v38, -v34, v36, 1.0
	v_fmac_f32_e32 v36, v38, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v38, v39, v35
	v_fma_f32 v41, -v33, v38, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v41, v35
	v_fma_f32 v33, -v33, v38, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v33, v33, v35, v38
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v33, v33, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, v33, v33
	v_dual_mul_f32 v40, v37, v36 :: v_dual_mul_f32 v43, s12, v33
	v_mul_f32_e32 v39, s12, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v42, -v34, v40, v37
	v_fmac_f32_e32 v40, v42, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v34, v40, v37
	v_mul_f32_e64 v37, -v33, s13
	v_div_fmas_f32 v34, v34, v36, v40
	v_mul_f32_e64 v36, v33, -v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v31, v34, v28, v32
	v_floor_f32_e32 v31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v31, v28, v32
	s_waitcnt vmcnt(0)
	v_dual_subrev_f32 v31, s15, v31 :: v_dual_mul_f32 v34, v2, v33
	v_fmac_f32_e32 v24, s12, v39
	v_dual_mul_f32 v39, v36, v31 :: v_dual_subrev_f32 v32, s14, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, s12, v34
	v_mul_f32_e32 v41, v3, v31
	v_dual_fmac_f32 v23, s13, v39 :: v_dual_mul_f32 v38, v3, v33
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v45, v33, v32
	v_mul_f32_e32 v34, v33, v31
	v_mul_f32_e32 v36, v36, v32
	v_mul_f32_e32 v40, v31, v31
	v_fmac_f32_e32 v8, s13, v38
	v_mul_f32_e64 v38, v32, -v33
	v_mul_f32_e32 v33, v31, v41
	v_dual_mul_f32 v44, v35, v31 :: v_dual_fmac_f32 v25, s12, v36
	v_mul_f32_e32 v35, v35, v32
	v_dual_mul_f32 v39, v31, v34 :: v_dual_mul_f32 v46, v32, v32
	v_dual_mul_f32 v47, v31, v32 :: v_dual_mul_f32 v52, v32, v45
	v_fmac_f32_e32 v17, s13, v45
	v_mul_f32_e32 v45, v31, v45
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v42, v31, v39
	v_dual_mul_f32 v40, v31, v40 :: v_dual_mul_f32 v53, v32, v35
	v_fma_f32 v50, v37, s13, -v39
	v_mul_f32_e32 v39, v31, v47
	v_div_scale_f32 v51, null, s13, s13, v33
	v_mul_f32_e32 v37, v2, v46
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v16, v16, v50
	v_div_scale_f32 v68, null, s13, s13, v42
	v_mul_f32_e64 v49, v31, -v32
	v_mul_f32_e32 v35, v31, v46
	v_dual_mul_f32 v41, v31, v40 :: v_dual_mul_f32 v54, v32, v46
	v_fma_f32 v58, s12, v43, v52
	v_fmac_f32_e32 v53, v31, v44
	v_div_scale_f32 v61, null, s12, s12, v39
	v_rcp_f32_e32 v44, v51
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v22, v22, v58
	v_rcp_f32_e32 v73, v68
	v_mul_f32_e32 v48, v3, v34
	v_fma_f32 v56, v31, v31, v46
	v_dual_mul_f32 v36, v2, v49 :: v_dual_mul_f32 v49, v32, v52
	v_mul_f32_e32 v40, v3, v47
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mul_f32 v43, v31, v35 :: v_dual_add_f32 v10, v10, v56
	v_dual_mul_f32 v47, v31, v54 :: v_dual_add_f32 v20, v20, v53
	v_div_scale_f32 v63, null, s13, s13, v39
	v_div_scale_f32 v59, null, s12, s12, v37
	v_rcp_f32_e32 v53, v61
	v_fma_f32 v57, v2, v38, -v48
	v_div_scale_f32 v76, null, v29, v29, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v64, v59
	v_fma_f32 v84, -v51, v44, 1.0
	v_fma_f32 v89, -v68, v73, 1.0
	v_mul_f32_e32 v50, v31, v52
	v_rcp_f32_e32 v52, v63
	v_dual_add_f32 v7, v7, v57 :: v_dual_fmac_f32 v44, v84, v44
	v_rcp_f32_e32 v83, v76
	v_fma_f32 v84, -v61, v53, 1.0
	v_div_scale_f32 v70, null, v30, v30, v41
	v_div_scale_f32 v69, s0, v42, s13, v42
	v_div_scale_f32 v55, null, s13, s13, v35
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v91, -v63, v52, 1.0
	v_fmac_f32_e32 v53, v84, v53
	v_fma_f32 v84, -v59, v64, 1.0
	v_div_scale_f32 v57, null, s12, s12, v36
	v_fmac_f32_e32 v52, v91, v52
	v_rcp_f32_e32 v77, v70
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v73, v89, v73 :: v_dual_fmac_f32 v64, v84, v64
	v_fma_f32 v84, -v76, v83, 1.0
	v_dual_mul_f32 v48, v31, v45 :: v_dual_mul_f32 v45, v32, v54
	v_div_scale_f32 v54, null, s12, s12, v35
	v_fmac_f32_e32 v83, v84, v83
	v_div_scale_f32 v60, null, s13, s13, v40
	v_div_scale_f32 v71, null, s12, s12, v50
	v_div_scale_f32 v74, null, s12, s12, v49
	v_div_scale_f32 v75, null, s13, s13, v48
	v_div_scale_f32 v66, null, v29, v29, v47
	v_rcp_f32_e32 v56, v54
	v_rcp_f32_e32 v62, v55
	v_rcp_f32_e32 v58, v57
	v_rcp_f32_e32 v65, v60
	v_div_scale_f32 v78, null, v29, v29, v45
	v_div_scale_f32 v79, null, v30, v30, v43
	v_rcp_f32_e32 v80, v71
	v_rcp_f32_e32 v81, v74
	v_rcp_f32_e32 v82, v75
	v_rcp_f32_e32 v85, v66
	v_fma_f32 v90, -v70, v77, 1.0
	v_mul_f32_e32 v46, v31, v39
	v_rcp_f32_e32 v87, v78
	v_rcp_f32_e32 v88, v79
	v_fma_f32 v92, -v54, v56, 1.0
	v_fmac_f32_e32 v77, v90, v77
	v_fma_f32 v89, -v55, v62, 1.0
	v_fma_f32 v90, -v57, v58, 1.0
	v_fma_f32 v91, -v60, v65, 1.0
	v_fmac_f32_e32 v56, v92, v56
	v_fma_f32 v92, -v71, v80, 1.0
	v_div_scale_f32 v72, vcc_lo, v50, s12, v50
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v65, v91, v65
	v_fma_f32 v91, -v66, v85, 1.0
	v_fmac_f32_e32 v62, v89, v62
	v_fma_f32 v89, -v74, v81, 1.0
	v_fmac_f32_e32 v58, v90, v58
	v_fma_f32 v90, -v75, v82, 1.0
	v_div_scale_f32 v67, null, v30, v30, v46
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v81, v89, v81
	v_fma_f32 v89, -v78, v87, 1.0
	v_fmac_f32_e32 v80, v92, v80
	v_fmac_f32_e32 v82, v90, v82
	v_fma_f32 v90, -v79, v88, 1.0
	v_fmac_f32_e32 v85, v91, v85
	v_mul_f32_e32 v91, v69, v73
	v_rcp_f32_e32 v86, v67
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v87, v89, v87 :: v_dual_fmac_f32 v88, v90, v88
	v_fma_f32 v21, -v34, s12, v21
	v_fma_f32 v90, -v68, v91, v69
	v_mul_f32_e32 v84, v72, v80
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v26, v31, v38 :: v_dual_fmac_f32 v91, v90, v73
	v_fma_f32 v89, -v71, v84, v72
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v92, -v67, v86, 1.0
	v_div_scale_f32 v90, s3, v49, s12, v49
	v_fma_f32 v68, -v68, v91, v69
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v84, v89, v80
	v_dual_fmac_f32 v86, v92, v86 :: v_dual_mul_f32 v69, v90, v81
	v_div_scale_f32 v89, s2, v41, v30, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v71, -v71, v84, v72
	v_div_scale_f32 v72, s4, v48, s13, v48
	v_div_scale_f32 v92, s1, v33, s13, v33
	v_div_fmas_f32 v71, v71, v80, v84
	v_fma_f32 v84, -v74, v69, v90
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v68, v68, v73, v91
	v_div_scale_f32 v91, s0, v43, v29, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v69, v84, v81
	v_mul_f32_e32 v80, v72, v82
	v_div_scale_f32 v84, s5, v39, s12, v39
	s_mov_b32 vcc_lo, s3
	v_fma_f32 v74, -v74, v69, v90
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v73, -v75, v80, v72
	v_div_scale_f32 v90, s6, v39, s13, v39
	v_div_fixup_f32 v50, v71, s12, v50
	v_div_fmas_f32 v69, v74, v81, v69
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v80, v73, v82 :: v_dual_mul_f32 v73, v91, v83
	s_mov_b32 vcc_lo, s4
	v_div_scale_f32 v81, s3, v35, s12, v35
	v_div_fixup_f32 v42, v68, s13, v42
	v_fma_f32 v74, -v76, v73, v91
	v_fmac_f32_e32 v50, s13, v34
	v_div_fixup_f32 v49, v69, s12, v49
	v_mul_f32_e32 v71, v2, v31
	v_mul_f32_e32 v69, -2.0, v32
	v_fmac_f32_e32 v73, v74, v83
	v_add_f32_e32 v42, v42, v50
	v_fma_f32 v38, v38, s12, -v49
	v_fma_f32 v71, v3, v32, -v71
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f32 v76, -v76, v73, v91
	v_mul_f32_e32 v91, v84, v53
	v_fma_f32 v72, -v75, v80, v72
	v_mul_f32_e32 v75, v89, v77
	v_dual_add_f32 v19, v19, v42 :: v_dual_add_f32 v4, v4, v71
	v_div_fmas_f32 v72, v72, v82, v80
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v80, -v70, v75, v89
	s_mov_b32 vcc_lo, s0
	v_div_scale_f32 v82, s4, v35, s13, v35
	v_mul_f32_e32 v74, v92, v44
	v_fmac_f32_e32 v75, v80, v77
	v_div_fmas_f32 v73, v76, v83, v73
	v_mul_f32_e32 v76, v90, v52
	s_mov_b32 vcc_lo, s2
	v_mul_f32_e32 v83, v81, v56
	v_fma_f32 v70, -v70, v75, v89
	v_mul_f32_e32 v89, v82, v62
	v_fma_f32 v80, -v51, v74, v92
	v_div_fixup_f32 v34, v72, s13, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v70, v70, v77, v75
	v_fma_f32 v75, -v63, v76, v90
	v_fma_f32 v77, -v54, v83, v81
	v_sub_f32_e32 v34, v38, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v41, v70, v30, v41
	v_fmac_f32_e32 v76, v75, v52
	v_fma_f32 v75, -v55, v89, v82
	v_fmac_f32_e32 v74, v80, v44
	v_fma_f32 v80, -v61, v91, v84
	v_dual_fmac_f32 v83, v77, v56 :: v_dual_add_f32 v18, v18, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v89, v75, v62
	v_fma_f32 v51, -v51, v74, v92
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v91, v80, v53
	v_div_scale_f32 v80, s0, v36, s12, v36
	v_fma_f32 v55, -v55, v89, v82
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v77, v80, v58
	v_fma_f32 v63, -v63, v76, v90
	v_fma_f32 v75, -v57, v77, v80
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v77, v75, v58
	v_div_scale_f32 v75, s2, v37, s12, v37
	v_mul_f32_e32 v92, v75, v64
	v_fma_f32 v61, -v61, v91, v84
	v_div_scale_f32 v84, s9, v45, v29, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v93, -v59, v92, v75
	v_mul_f32_e32 v90, v84, v87
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v92, v93, v64
	v_div_scale_f32 v93, s7, v40, s13, v40
	v_fma_f32 v57, -v57, v77, v80
	v_fma_f32 v59, -v59, v92, v75
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v94, v93, v65
	v_fma_f32 v95, -v60, v94, v93
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v94, v95, v65
	v_div_scale_f32 v95, vcc_lo, v47, v29, v47
	v_fma_f32 v60, -v60, v94, v93
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v96, v95, v85
	v_fma_f32 v54, -v54, v83, v81
	v_fma_f32 v97, -v66, v96, v95
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v96, v97, v85
	v_div_scale_f32 v97, s8, v46, v30, v46
	v_fma_f32 v66, -v66, v96, v95
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v98, v97, v86
	v_div_fmas_f32 v48, v66, v85, v96
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v99, -v67, v98, v97
	v_div_fixup_f32 v66, v73, v29, v43
	s_mov_b32 vcc_lo, s8
	v_div_fixup_f32 v47, v48, v29, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v98, v99, v86
	v_fma_f32 v99, -v78, v90, v84
	v_add_f32_e32 v48, v30, v66
	v_fma_f32 v47, v31, v69, -v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v90, v99, v87
	v_div_scale_f32 v99, s10, v43, v30, v43
	v_fma_f32 v75, -v78, v90, v84
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v100, v99, v88
	v_fma_f32 v101, -v79, v100, v99
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v100, v101, v88
	v_fma_f32 v78, -v79, v100, v99
	v_add_f32_e32 v79, v31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v48, v31, v79
	v_add_f32_e32 v41, v41, v48
	v_fma_f32 v67, -v67, v98, v97
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v15, v41
	v_div_fmas_f32 v67, v67, v86, v98
	s_mov_b32 vcc_lo, s5
	v_div_fmas_f32 v49, v61, v53, v91
	s_mov_b32 vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v38, v67, v30, v46
	v_div_fmas_f32 v50, v63, v52, v76
	s_mov_b32 vcc_lo, s9
	v_div_fixup_f32 v46, v49, s12, v39
	v_div_fmas_f32 v42, v75, v87, v90
	s_mov_b32 vcc_lo, s10
	v_sub_f32_e32 v38, v47, v38
	v_div_fmas_f32 v49, v78, v88, v100
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v42, v42, v29, v45
	v_div_fmas_f32 v34, v54, v56, v83
	s_mov_b32 vcc_lo, s4
	v_div_fixup_f32 v39, v50, s13, v39
	v_div_fmas_f32 v45, v55, v62, v89
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v34, v34, s12, v35
	v_add_f32_e32 v14, v14, v38
	v_div_fixup_f32 v43, v49, v30, v43
	v_div_fixup_f32 v35, v45, s13, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v31, s12, -v34
	v_dual_add_f32 v68, v32, v32 :: v_dual_add_f32 v31, v35, v31
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v68, v32, v68, v29
	v_fma_f32 v32, -v32, s13, v46
	v_div_fmas_f32 v46, v57, v58, v77
	s_mov_b32 vcc_lo, s1
	v_add_f32_e32 v11, v11, v31
	v_div_fmas_f32 v44, v51, v44, v74
	s_mov_b32 vcc_lo, s2
	v_sub_f32_e32 v32, v32, v39
	v_div_fmas_f32 v38, v59, v64, v92
	s_mov_b32 vcc_lo, s7
	v_div_fixup_f32 v36, v46, s12, v36
	v_div_fmas_f32 v39, v60, v65, v94
	v_add_f32_e32 v42, v68, v42
	v_div_fixup_f32 v37, v38, s12, v37
	v_div_fixup_f32 v33, v44, s13, v33
	v_fma_f32 v3, -v3, s13, v36
	v_div_fixup_f32 v34, v39, s13, v40
	v_add_f32_e32 v13, v13, v32
	v_fmac_f32_e32 v37, s12, v2
	v_add_f32_e32 v2, v43, v42
	v_sub_f32_e32 v3, v3, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v33, v34, v37 :: v_dual_add_f32 v12, v12, v2
	v_dual_add_f32 v6, v6, v3 :: v_dual_add_f32 v5, v5, v33
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s35
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v1, v27
	s_or_b32 s27, vcc_lo, s27
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s27
.LBB0_6:                                ; %Flow454
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s31
	s_mul_i32 s0, s26, s24
	s_mul_i32 s0, s0, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s0, s25, v0
	s_ashr_i32 s25, s24, 31
	s_lshl_b64 s[0:1], s[24:25], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add3_u32 v2, s24, s24, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v27, s24, v2
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v29, s24, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v31, vcc_lo, v0, s0
	v_add_nc_u32_e32 v33, s24, v29
	v_add_co_ci_u32_e32 v32, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_ashrrev_i32_e32 v34, 31, v33
	s_clause 0x2
	global_store_b32 v[0:1], v24, off
	global_store_b32 v[31:32], v25, off
	global_store_b32 v[2:3], v26, off
	v_lshlrev_b64 v[0:1], 2, v[29:30]
	v_add_co_u32 v2, vcc_lo, s16, v27
	v_lshlrev_b64 v[24:25], 2, v[33:34]
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v28, vcc_lo
	v_add_nc_u32_e32 v26, s24, v33
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v24, vcc_lo, s16, v24
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v28, s24, v26
	v_add_co_ci_u32_e32 v25, vcc_lo, s17, v25, vcc_lo
	v_ashrrev_i32_e32 v27, 31, v26
	global_store_b32 v[2:3], v22, off
	v_ashrrev_i32_e32 v29, 31, v28
	s_clause 0x1
	global_store_b32 v[0:1], v21, off
	global_store_b32 v[24:25], v23, off
	v_add_nc_u32_e32 v21, s24, v28
	v_lshlrev_b64 v[2:3], 2, v[26:27]
	v_lshlrev_b64 v[0:1], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v23, s24, v21
	v_ashrrev_i32_e32 v22, 31, v21
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v25, s24, v23
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_ashrrev_i32_e32 v24, 31, v23
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_ashrrev_i32_e32 v26, 31, v25
	s_clause 0x1
	global_store_b32 v[2:3], v16, off
	global_store_b32 v[0:1], v17, off
	v_lshlrev_b64 v[0:1], 2, v[23:24]
	v_add_co_u32 v2, vcc_lo, s16, v21
	v_lshlrev_b64 v[16:17], 2, v[25:26]
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v22, vcc_lo
	v_add_nc_u32_e32 v21, s24, v25
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v16, vcc_lo, s16, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v23, s24, v21
	v_add_co_ci_u32_e32 v17, vcc_lo, s17, v17, vcc_lo
	v_ashrrev_i32_e32 v22, 31, v21
	global_store_b32 v[2:3], v20, off
	v_ashrrev_i32_e32 v24, 31, v23
	s_clause 0x1
	global_store_b32 v[0:1], v19, off
	global_store_b32 v[16:17], v18, off
	v_add_nc_u32_e32 v16, s24, v23
	v_lshlrev_b64 v[2:3], 2, v[21:22]
	v_lshlrev_b64 v[0:1], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v18, s24, v16
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v20, s24, v18
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_ashrrev_i32_e32 v19, 31, v18
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_ashrrev_i32_e32 v21, 31, v20
	s_clause 0x1
	global_store_b32 v[2:3], v15, off
	global_store_b32 v[0:1], v14, off
	v_lshlrev_b64 v[0:1], 2, v[18:19]
	v_add_co_u32 v2, vcc_lo, s16, v16
	v_add_nc_u32_e32 v16, s24, v20
	v_lshlrev_b64 v[14:15], 2, v[20:21]
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v17, vcc_lo
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v18, s24, v16
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_co_u32 v14, vcc_lo, s16, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s17, v15, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	global_store_b32 v[2:3], v13, off
	v_lshlrev_b64 v[2:3], 2, v[16:17]
	s_clause 0x1
	global_store_b32 v[0:1], v12, off
	global_store_b32 v[14:15], v11, off
	v_add_nc_u32_e32 v11, s24, v18
	v_lshlrev_b64 v[0:1], 2, v[18:19]
	v_add_co_u32 v2, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v13, s24, v11
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v15, s24, v13
	v_ashrrev_i32_e32 v12, 31, v11
	v_ashrrev_i32_e32 v14, 31, v13
	s_clause 0x1
	global_store_b32 v[2:3], v10, off
	global_store_b32 v[0:1], v9, off
	v_add_nc_u32_e32 v9, s24, v15
	v_lshlrev_b64 v[2:3], 2, v[11:12]
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[0:1], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v13, s24, v9
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_lshlrev_b64 v[11:12], 2, v[15:16]
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, s16, v11
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
	v_add_co_u32 v9, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s16, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v14, vcc_lo
	s_clause 0x4
	global_store_b32 v[2:3], v8, off
	global_store_b32 v[0:1], v7, off
	global_store_b32 v[11:12], v6, off
	global_store_b32 v[9:10], v5, off
	global_store_b32 v[13:14], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 102
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_, .Lfunc_end0-_Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3824
; NumSgprs: 38
; NumVgprs: 102
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 102
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z19normal_eqs_flow_GPUPfPK15HIP_vector_typeIfLj2EEPKfPKiffffiiS7_S7_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     102
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
