#include "includes.h"
__global__ void __fillToInds4D(double A, double *B, int ldb, int rdb, int tdb, int *I, int nrows, int *J, int ncols, int *K, int nk, int *L, int nl, int ntk, int nbk, int ntl, int nbl) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int tk = threadIdx.z / ntl;
int tl = threadIdx.z - tk * ntl;
int bk = blockIdx.z / nbl;
int bl = blockIdx.z - bk * nbl;
int kk = tk + ntk * bk;
int ll = tl + ntl * bl;
int i, j, k, l, mapi, mapj, mapk, mapl;
for (l = ll; l < nl; l += ntl * nbl) {
mapl = l;
if (L != NULL) mapl = L[l];
for (k = kk; k < nk; k += ntk * nbk) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * (mapk + tdb * mapl))] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
B[i + ldb * (mapj + rdb * (mapk + tdb * mapl))] = A;
}
}
}
}
}
}
	.file	"tmpxft_0024d5f1_00000000-6___fillToInds4D.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z57__device_stub__Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiiidPdiiiPiiS0_iS0_iS0_iiiii
	.type	_Z57__device_stub__Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiiidPdiiiPiiS0_iS0_iS0_iiiii, @function
_Z57__device_stub__Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiiidPdiiiPiiS0_iS0_iS0_iiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movq	%rdi, 48(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 44(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movl	%edx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	320(%rsp), %rax
	movl	%ecx, 36(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 32(%rsp)
	movq	%rax, (%rsp)
	movsd	%xmm0, 56(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	%rsp, %rax
	movq	%rax, 216(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 304
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z57__device_stub__Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiiidPdiiiPiiS0_iS0_iS0_iiiii, .-_Z57__device_stub__Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiiidPdiiiPiiS0_iS0_iS0_iiiii
	.globl	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.type	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, @function
_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiiidPdiiiPiiS0_iS0_iS0_iiiii
	.cfi_endproc
.LFE2033:
	.size	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, .-_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __fillToInds4D(double A, double *B, int ldb, int rdb, int tdb, int *I, int nrows, int *J, int ncols, int *K, int nk, int *L, int nl, int ntk, int nbk, int ntl, int nbl) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int tk = threadIdx.z / ntl;
int tl = threadIdx.z - tk * ntl;
int bk = blockIdx.z / nbl;
int bl = blockIdx.z - bk * nbl;
int kk = tk + ntk * bk;
int ll = tl + ntl * bl;
int i, j, k, l, mapi, mapj, mapk, mapl;
for (l = ll; l < nl; l += ntl * nbl) {
mapl = l;
if (L != NULL) mapl = L[l];
for (k = kk; k < nk; k += ntk * nbk) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * (mapk + tdb * mapl))] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
B[i + ldb * (mapj + rdb * (mapk + tdb * mapl))] = A;
}
}
}
}
}
}
	.text
	.file	"__fillToInds4D.hip"
	.globl	_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii # -- Begin function _Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.type	_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii,@function
_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii: # @_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	48(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r10, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, .Lfunc_end0-_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii,@object # @_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.section	.rodata,"a",@progbits
	.globl	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.p2align	3, 0x0
_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii:
	.quad	_Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.size	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii"
	.size	.L__unnamed_1, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub____fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii ; -- Begin function _Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.globl	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
	.p2align	8
	.type	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii,@function
_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii: ; @_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x58
	s_load_b32 s3, s[0:1], 0x68
	s_mov_b32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s19
	v_cvt_f32_u32_e32 v3, s3
	s_sub_i32 s2, 0, s19
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v4, v3
	v_bfe_u32 v3, v0, 20, 10
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	v_cvt_u32_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v3, v1
	v_readfirstlane_b32 s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s4, s2
	s_mul_hi_u32 s4, s2, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, v1, s19
	v_add_nc_u32_e32 v4, 1, v1
	s_add_i32 s2, s2, s4
	s_mul_hi_u32 s2, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_mul_i32 s4, s2, s3
	s_add_i32 s5, s2, 1
	v_sub_nc_u32_e32 v2, v3, v2
	s_sub_i32 s4, s15, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_sub_i32 s6, s4, s3
	s_cmp_ge_u32 s4, s3
	v_subrev_nc_u32_e32 v5, s19, v2
	v_cmp_le_u32_e32 vcc_lo, s19, v2
	s_cselect_b32 s2, s5, s2
	s_cselect_b32 s4, s6, s4
	s_add_i32 s5, s2, 1
	s_cmp_ge_u32 s4, s3
	v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v4
	s_cselect_b32 s2, s5, s2
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s19, v2
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v1, v4, vcc_lo
	v_mad_u64_u32 v[1:2], null, s2, s3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, s15, v1
	v_mad_u64_u32 v[1:2], null, v4, s19, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s16, v1
	s_cbranch_execz .LBB0_26
; %bb.1:                                ; %.lr.ph110
	s_clause 0x8
	s_load_b32 s29, s[0:1], 0x7c
	s_load_b64 s[20:21], s[0:1], 0x50
	s_load_b64 s[22:23], s[0:1], 0x40
	s_load_b32 s15, s[0:1], 0x48
	s_load_b64 s[24:25], s[0:1], 0x30
	s_load_b64 s[34:35], s[0:1], 0x70
	s_load_b64 s[26:27], s[0:1], 0x20
	s_load_b32 s28, s[0:1], 0x28
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s11, s[0:1], 0x38
	v_mad_u64_u32 v[3:4], null, s2, s17, v[5:6]
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mul_i32 s17, s18, s17
	s_mul_i32 s18, s3, s19
	s_and_b32 s1, s29, 0xffff
	s_lshr_b32 s33, s29, 16
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, s13, s1, v[2:3]
	v_mad_u64_u32 v[5:6], null, s14, s33, v[0:1]
	s_cmp_lg_u64 s[20:21], 0
	v_cmp_gt_i32_e64 s0, s15, v3
	s_cselect_b32 s13, -1, 0
	s_cmp_lg_u64 s[22:23], 0
	s_mul_i32 s29, s34, s1
	s_cselect_b32 s14, -1, 0
	s_cmp_lg_u64 s[24:25], 0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s1, s11, v5
	v_cmp_gt_i32_e64 s2, s28, v4
	s_cselect_b32 s30, -1, 0
	s_cmp_lg_u64 s[26:27], 0
	s_mul_i32 s33, s35, s33
	s_cselect_b32 s31, -1, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
                                        ;         Child Loop BB0_15 Depth 4
                                        ;         Child Loop BB0_21 Depth 4
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, v1
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_cbranch_vccnz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_co_u32 v6, vcc_lo, s20, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v7, vcc_lo
	global_load_b32 v0, v[6:7], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_25
; %bb.5:                                ; %.lr.ph106
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v0, v0, s10
	v_mov_b32_e32 v6, v3
	s_mov_b32 s34, 0
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
                                        ;         Child Loop BB0_15 Depth 4
                                        ;         Child Loop BB0_21 Depth 4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v6
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=2
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s22, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v8, vcc_lo
	global_load_b32 v2, v[7:8], off
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=2
	s_and_saveexec_b32 s35, s1
	s_cbranch_execz .LBB0_24
; %bb.9:                                ; %.lr.ph103
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v2, v2, v0
	s_mov_b32 s36, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s9
.LBB0_10:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_15 Depth 4
                                        ;         Child Loop BB0_21 Depth 4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v10, v7
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=3
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[7:8]
	v_add_co_u32 v8, vcc_lo, s24, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v9, vcc_lo
	global_load_b32 v10, v[8:9], off
.LBB0_12:                               ;   in Loop: Header=BB0_10 Depth=3
	s_and_not1_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccnz .LBB0_17
; %bb.13:                               ; %.preheader97
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_and_saveexec_b32 s37, s2
	s_cbranch_execz .LBB0_16
; %bb.14:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, v10, v2
	s_mov_b32 s38, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v11, v8, s8
	v_mov_b32_e32 v8, v4
.LBB0_15:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_10 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4
	v_lshlrev_b64 v[12:13], 2, v[8:9]
	v_add_nc_u32_e32 v8, s29, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s26, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s27, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s28, v8
	global_load_b32 v9, v[12:13], off
	s_or_b32 s38, vcc_lo, s38
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v12, v9, v11
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v12, s3, s6, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
	global_store_b64 v[12:13], v[14:15], off
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB0_15
.LBB0_16:                               ; %Flow161
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_or_b32 exec_lo, exec_lo, s37
	s_mov_b32 s3, 0
	s_branch .LBB0_18
.LBB0_17:                               ;   in Loop: Header=BB0_10 Depth=3
	s_mov_b32 s3, -1
.LBB0_18:                               ; %Flow164
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_23
; %bb.19:                               ; %.preheader
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_and_saveexec_b32 s37, s2
	s_cbranch_execz .LBB0_22
; %bb.20:                               ; %.lr.ph101
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v9, v4 :: v_dual_add_nc_u32 v8, v10, v2
	s_mov_b32 s38, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v8, v8, s8
.LBB0_21:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_10 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v13, s5 :: v_dual_add_nc_u32 v10, v8, v9
	v_dual_mov_b32 v12, s4 :: v_dual_add_nc_u32 v9, s29, v9
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e32 vcc_lo, s28, v9
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_or_b32 s38, vcc_lo, s38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s6, v10
	v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
	global_store_b64 v[10:11], v[12:13], off
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB0_21
.LBB0_22:                               ; %Flow163
                                        ;   in Loop: Header=BB0_10 Depth=3
	s_or_b32 exec_lo, exec_lo, s37
.LBB0_23:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_10 Depth=3
	v_add_nc_u32_e32 v7, s33, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s11, v7
	s_or_b32 s36, vcc_lo, s36
	s_and_not1_b32 exec_lo, exec_lo, s36
	s_cbranch_execnz .LBB0_10
.LBB0_24:                               ; %Flow166
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s35
	v_add_nc_u32_e32 v6, s17, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v6
	s_or_b32 s34, vcc_lo, s34
	s_and_not1_b32 exec_lo, exec_lo, s34
	s_cbranch_execnz .LBB0_6
.LBB0_25:                               ; %Flow168
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	v_add_nc_u32_e32 v1, s18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s16, v1
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
.LBB0_26:                               ; %._crit_edge111
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 39
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii, .Lfunc_end0-_Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1168
; NumSgprs: 41
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 41
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         116
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         124
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         126
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         128
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         130
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         132
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         134
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         176
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 368
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     41
    .sgpr_spill_count: 0
    .symbol:         _Z14__fillToInds4DdPdiiiPiiS0_iS0_iS0_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
