/*
 * Copyright 1993-2009 NVIDIA Corporation.  All rights reserved.
 *
 * NOTICE TO USER:
 *
 * This source code is subject to NVIDIA ownership rights under U.S. and
 * international Copyright laws.  Users and possessors of this source code
 * are hereby granted a nonexclusive, royalty-free license to use this code
 * in individual and commercial software.
 *
 * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
 * CODE FOR ANY PURPOSE.  IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
 * IMPLIED WARRANTY OF ANY KIND.  NVIDIA DISCLAIMS ALL WARRANTIES WITH
 * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
 * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
 * OF USE, DATA OR PROFITS,  WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
 * OR OTHER TORTIOUS ACTION,  ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OR PERFORMANCE OF THIS SOURCE CODE.
 *
 * U.S. Government End Users.   This source code is a "commercial item" as
 * that term is defined at  48 C.F.R. 2.101 (OCT 1995), consisting  of
 * "commercial computer  software"  and "commercial computer software
 * documentation" as such terms are  used in 48 C.F.R. 12.212 (SEPT 1995)
 * and is provided to the U.S. Government only as a commercial end item.
 * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
 * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
 * source code with only those rights set forth herein.
 *
 * Any use of this source code in individual and commercial software must
 * include, in the user documentation and internal comments to the code,
 * the above Disclaimer and U.S. Government End Users Notice.
 */


// A simple macro to divide and round-up
#define DIVUP(A,B) ( (A)%(B) == 0 ? (A)/(B) : ((A) / (B) + 1) )

// macro to clamp to min & max value:
#define CLAMP(A,B,C) ( (A) < (B) ? (B) : (A) > (C) ? (C) : (A) )


// Here is the kernel which performs the rotate for every pixel in the output image
__global__ void BrightnessContrastKernel(uchar4 * image, int w, int h, int pitch, float brightness, float contrast)
{
  // compute the x & y coordinates in the image the current pixel must process.  

  // the image data is passed in as a uchar4, so this x coordinate 
  // points 4-pixel groups
  int x = __mul24(blockIdx.x,blockDim.x) + threadIdx.x; 
  int y = __mul24(blockIdx.y,blockDim.y) + threadIdx.y;
   
  if(x < (w>>2) && y < h)    // w/4 because we are processing 4 pixels per thread
  {

    float temp;

    // read in the value to modify
    uchar4 pixel = image[__umul24(y,pitch>>2) + x];

    // Pixel 1 
    temp = ((float)pixel.x + brightness) * contrast;
    pixel.x = CLAMP(temp,0.0f,255.0f);

    // Pixel 2 
    temp = ((float)pixel.y + brightness) * contrast;
    pixel.y = CLAMP(temp,0.0f,255.0f);

    // Pixel 3
    temp = ((float)pixel.z + brightness) * contrast;
    pixel.z = CLAMP(temp,0.0f,255.0f);

    // Pixel 4
    temp = ((float)pixel.w + brightness) * contrast;
    pixel.w = CLAMP(temp,0.0f,255.0f);

    // write the new pixel value back to the image data
    image[__umul24(y,pitch>>2) + x] = pixel;
  }

}

// This function will adjust the brightness and contrast an image
extern "C" cudaError_t AdjustBrightnessContrast(unsigned char * image, int width, int height, 
                          int pitch, float brightness_adjust, float contrast_adjust)
{
  
  // we need to create a 2-d thread block and a 2-d grid
  // of blocks.  Lets just make the blocks 16x14. 
  // Process four pixels / thread
  dim3 BlockSz(16,14,1);
  dim3 GridSz(DIVUP(width,BlockSz.x*4),DIVUP(height,BlockSz.y),1);

  // Now launch the kernel to do the adjustment
  BrightnessContrastKernel<<<GridSz,BlockSz>>>((uchar4*)image,width,height,pitch,brightness_adjust,contrast_adjust);
  
  // just wait here for the kernel to complete
  cudaError_t err = cudaThreadSynchronize();  

  return(err);
}



	.file	"tmpxft_003afc4e_00000000-6_BrightnessContrast.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff
	.type	_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff, @function
_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z24BrightnessContrastKernelP6uchar4iiiff(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff, .-_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff
	.globl	_Z24BrightnessContrastKernelP6uchar4iiiff
	.type	_Z24BrightnessContrastKernelP6uchar4iiiff, @function
_Z24BrightnessContrastKernelP6uchar4iiiff:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff
	.cfi_endproc
.LFE2034:
	.size	_Z24BrightnessContrastKernelP6uchar4iiiff, .-_Z24BrightnessContrastKernelP6uchar4iiiff
	.globl	AdjustBrightnessContrast
	.type	AdjustBrightnessContrast, @function
AdjustBrightnessContrast:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edx, %eax
	movl	%ecx, %r13d
	movl	$14, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edx, %ebp
	xorl	%edx, %edx
	divl	%ecx
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%esi, %ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movl	%esi, %ebx
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	cmpl	$1, %edx
	movl	%esi, %edx
	movl	$1, %esi
	sbbl	$-1, %eax
	andl	$63, %ecx
	shrl	$6, %edx
	cmpl	$1, %ecx
	movl	%eax, 40(%rsp)
	movl	$1, %ecx
	sbbl	$-1, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%edx, 36(%rsp)
	movl	$3758096385, %edx
	movq	36(%rsp), %rdi
	salq	$4, %rdx
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L11
	movl	%r13d, %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	movq	%r12, %rdi
	call	_Z55__device_stub__Z24BrightnessContrastKernelP6uchar4iiiffP6uchar4iiiff
.L11:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
	.cfi_endproc
.LFE2008:
	.size	AdjustBrightnessContrast, .-AdjustBrightnessContrast
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24BrightnessContrastKernelP6uchar4iiiff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24BrightnessContrastKernelP6uchar4iiiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*
 * Copyright 1993-2009 NVIDIA Corporation.  All rights reserved.
 *
 * NOTICE TO USER:
 *
 * This source code is subject to NVIDIA ownership rights under U.S. and
 * international Copyright laws.  Users and possessors of this source code
 * are hereby granted a nonexclusive, royalty-free license to use this code
 * in individual and commercial software.
 *
 * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
 * CODE FOR ANY PURPOSE.  IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
 * IMPLIED WARRANTY OF ANY KIND.  NVIDIA DISCLAIMS ALL WARRANTIES WITH
 * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
 * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
 * OF USE, DATA OR PROFITS,  WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
 * OR OTHER TORTIOUS ACTION,  ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OR PERFORMANCE OF THIS SOURCE CODE.
 *
 * U.S. Government End Users.   This source code is a "commercial item" as
 * that term is defined at  48 C.F.R. 2.101 (OCT 1995), consisting  of
 * "commercial computer  software"  and "commercial computer software
 * documentation" as such terms are  used in 48 C.F.R. 12.212 (SEPT 1995)
 * and is provided to the U.S. Government only as a commercial end item.
 * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
 * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
 * source code with only those rights set forth herein.
 *
 * Any use of this source code in individual and commercial software must
 * include, in the user documentation and internal comments to the code,
 * the above Disclaimer and U.S. Government End Users Notice.
 */


// A simple macro to divide and round-up
#define DIVUP(A,B) ( (A)%(B) == 0 ? (A)/(B) : ((A) / (B) + 1) )

// macro to clamp to min & max value:
#define CLAMP(A,B,C) ( (A) < (B) ? (B) : (A) > (C) ? (C) : (A) )


// Here is the kernel which performs the rotate for every pixel in the output image
__global__ void BrightnessContrastKernel(uchar4 * image, int w, int h, int pitch, float brightness, float contrast)
{
  // compute the x & y coordinates in the image the current pixel must process.  

  // the image data is passed in as a uchar4, so this x coordinate 
  // points 4-pixel groups
  int x = __mul24(blockIdx.x,blockDim.x) + threadIdx.x; 
  int y = __mul24(blockIdx.y,blockDim.y) + threadIdx.y;
   
  if(x < (w>>2) && y < h)    // w/4 because we are processing 4 pixels per thread
  {

    float temp;

    // read in the value to modify
    uchar4 pixel = image[__umul24(y,pitch>>2) + x];

    // Pixel 1 
    temp = ((float)pixel.x + brightness) * contrast;
    pixel.x = CLAMP(temp,0.0f,255.0f);

    // Pixel 2 
    temp = ((float)pixel.y + brightness) * contrast;
    pixel.y = CLAMP(temp,0.0f,255.0f);

    // Pixel 3
    temp = ((float)pixel.z + brightness) * contrast;
    pixel.z = CLAMP(temp,0.0f,255.0f);

    // Pixel 4
    temp = ((float)pixel.w + brightness) * contrast;
    pixel.w = CLAMP(temp,0.0f,255.0f);

    // write the new pixel value back to the image data
    image[__umul24(y,pitch>>2) + x] = pixel;
  }

}

// This function will adjust the brightness and contrast an image
extern "C" hipError_t AdjustBrightnessContrast(unsigned char * image, int width, int height, 
                          int pitch, float brightness_adjust, float contrast_adjust)
{
  
  // we need to create a 2-d thread block and a 2-d grid
  // of blocks.  Lets just make the blocks 16x14. 
  // Process four pixels / thread
  dim3 BlockSz(16,14,1);
  dim3 GridSz(DIVUP(width,BlockSz.x*4),DIVUP(height,BlockSz.y),1);

  // Now launch the kernel to do the adjustment
  BrightnessContrastKernel<<<GridSz,BlockSz>>>((uchar4*)image,width,height,pitch,brightness_adjust,contrast_adjust);
  
  // just wait here for the kernel to complete
  hipError_t err = hipDeviceSynchronize();  

  return(err);
}



	.text
	.file	"BrightnessContrast.hip"
	.globl	_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff # -- Begin function _Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.type	_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff,@function
_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff: # @_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	4(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff, .Lfunc_end0-_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.cfi_endproc
                                        # -- End function
	.globl	AdjustBrightnessContrast        # -- Begin function AdjustBrightnessContrast
	.type	AdjustBrightnessContrast,@function
AdjustBrightnessContrast:               # @AdjustBrightnessContrast
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movl	%esi, %r14d
	movl	%esi, %ecx
	andl	$63, %ecx
	movl	%esi, %eax
	shrl	$6, %eax
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movq	%rdi, %r15
	movl	%edx, %ecx
	shrl	%ecx
	movl	$2454267027, %edx               # imm = 0x92492493
	imulq	%rcx, %rdx
	shrq	$34, %rdx
	movl	%edx, %ecx
	shll	$4, %ecx
	leal	(%rdx,%rdx), %esi
	subl	%ecx, %esi
	xorl	%edi, %edi
	addl	%ebp, %esi
	setne	%dil
	addl	%edx, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$60129542160, %rdx              # imm = 0xE00000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	callq	_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
.LBB1_2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	AdjustBrightnessContrast, .Lfunc_end1-AdjustBrightnessContrast
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff,@object # @_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.section	.rodata,"a",@progbits
	.globl	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.p2align	3, 0x0
_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff:
	.quad	_Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.size	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff"
	.size	.L__unnamed_1, 59

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff ; -- Begin function _Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.globl	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
	.p2align	8
	.type	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff,@function
_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff: ; @_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_bfe_i32 s3, s14, 0x180000
	s_bfe_i32 s8, s15, 0x180000
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s9, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s3, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s8, s9, v[3:4]
	s_ashr_i32 s2, s4, 2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s5, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	s_lshr_b32 s4, s6, 2
	s_load_b32 s0, s[0:1], 0x18
	v_mad_u32_u24 v0, v1, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v3, v2
	v_cvt_f32_ubyte1_e32 v4, v2
	v_cvt_f32_ubyte2_e32 v5, v2
	v_cvt_f32_ubyte3_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v3, s7, v3 :: v_dual_add_f32 v4, s7, v4
	v_dual_add_f32 v5, s7, v5 :: v_dual_add_f32 v2, s7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v3, s0, v3 :: v_dual_mul_f32 v4, s0, v4
	v_dual_mul_f32 v5, s0, v5 :: v_dual_mul_f32 v2, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v3
	v_cndmask_b32_e32 v6, 0x437f0000, v3, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v4
	v_cndmask_b32_e32 v7, 0x437f0000, v4, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v2
	v_cndmask_b32_e32 v8, 0x437f0000, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v5
	v_cndmask_b32_e32 v9, 0x437f0000, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v2, 0, v8, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v5
	v_cvt_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v3, v3
	v_cndmask_b32_e32 v5, 0, v9, vcc_lo
	v_cvt_i32_f32_e32 v2, v2
	v_lshlrev_b16 v4, 8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v5, v5
	v_lshlrev_b16 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, v3, v4
	v_or_b32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, 0xffff, v3
	v_lshlrev_b32_e32 v2, 16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff, .Lfunc_end0-_Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24BrightnessContrastKernelP15HIP_vector_typeIhLj4EEiiiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
