/*!
 * @file 		YuriConvertCuda.cu
 * @author 		Zdenek Travnicek
 * @date 		13.8.2010
 * @date		16.2.2013
 * @copyright	Institute of Intermedia, CTU in Prague, 2010 - 2013
 * 				Distributed under modified BSD Licence, details in file doc/LICENSE
 *
 */


#include <cuda.h>
//include "yuri/video/YuriConvertor.h"

__device__ void _RGB2YUV(char*s, float *Y, float *Cb, float*Cr, float Wb, float Wr, float Wg, float Kb, float Kr)
{
	float r,g,b;
	r = (float)((unsigned char)(s[0]))/255.0f;
	g = (float)((unsigned char)(s[1]))/255.0f;
	b = (float)((unsigned char)(s[2]))/255.0f;
	*Y=r*Wr + g*Wg + b*Wb;
	*Cb=(b-*Y)*Kb;
	*Cr=(r-*Y)*Kr;
}
__device__ unsigned int luma(float Y) {
	return (unsigned int)(64 + Y  * 876);
}
__device__ unsigned int chroma(float Y) {
	return (unsigned int)(512 + Y  * 896);
}
__global__ void RGB2YUV(char *s, char *d, size_t num, float Wb, float Wr, float Wg, float Kb, float Kr)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	//if (2*idx>=num) return;
	int si = 6*idx, di=5*idx;
	float Y1, Cr1, Cb1, Y2, Cb2, Cr2;
	unsigned int Ya, Yb, Cb, Cr;
	for (int i=idx;i<num;i+=4096) {
		si = i * 6;
		di = i * 5;
		_RGB2YUV(s+si+0, &Y1, &Cb1, &Cr1,  Wb, Wr, Wg, Kb, Kr);
		_RGB2YUV(s+si+3, &Y2, &Cb2, &Cr2, Wb, Wr, Wg, Kb, Kr);
		Ya = luma(Y1);
		Yb = luma(Y2);
		Cr= chroma((Cr1+Cr2)/2.0f);
		Cb= chroma((Cb1+Cb2)/2.0f);
		
		d[di]=Ya&0xFF;
		d[di+1]=((Ya>>8)&0x03) | ((Cr<<2)&0xfc); 
		d[di+2]=((Cr>>6)&0x0F) | ((Yb<<4)&0xF0); 
		d[di+3]=((Yb>>4)&0x3F) | ((Cb<<6)&0xC0);
		d[di+4]=((Cb>>2)&0xFF);
	}
}
__device__ unsigned int chr(float v) 
{
	float val = v * 255.0f;
	return (unsigned int)(val>255?255:(val<0?0:val));
}
__global__ void YUV162RGB(char *s, char *d, size_t num, float Wb, float Wr, float Wg, float Kb, float Kr)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if (2*idx>=num) return;
	int si = 6*idx, di=5*idx;
	float Y1, Y2, U, V;	
	for (int i=idx;i<num/2;i+=4096) {
		si = i * 4;
		di = i * 6;
		Y1 = (float)((unsigned char)(s[si+0]))/255.0f;
		Y2 = (float)((unsigned char)(s[si+2]))/255.0f;
		U = (float)((unsigned char)(s[si+1]))/255.0f - 0.5f;
		V = (float)((unsigned char)(s[si+3]))/255.0f - 0.5f;
		d[di+0] = chr(Y1 + 1.403*V);
		d[di+1] = chr(Y1 - 0.344*U - 0.714*V);
		d[di+2] = chr(Y1 + 1.770*U);
		d[di+3] = chr(Y2 + 1.403*V);
		d[di+4] = chr(Y2 - 0.344*U - 0.714*V);
		d[di+5] = chr(Y2 + 1.770*U);
	}
}

void *CudaAlloc(unsigned int size)
{
	void *x;
	cudaMalloc((void **) &x, size*sizeof(char));
	return x;

}
void CudaDealloc(void *mem)
{
	cudaFree(mem);
}

bool YuriConvertRGB24_YUV20(const char *src, char *dest, void *src_cuda, void *dest_cuda,unsigned int num, float Wb, float Wr)
{
	size_t size = num*3, out_size=num*5/2;
	cudaMemcpy(reinterpret_cast<char*>(src_cuda),reinterpret_cast<const char*>(src),
			size,cudaMemcpyHostToDevice);
	float Wg, Kb, Kr;
	Wg=1.0f-Wr-Wb;
	Kb = 0.5f / (1.0f - Wb);
	Kr = 0.5f / (1.0f - Wr);

//	for (int i=0;i<1000;++i) {
		RGB2YUV <<<512, 8 >>> (reinterpret_cast<char*>(src_cuda), 
				reinterpret_cast<char*>(dest_cuda), num, Wb,Wr,Wg,Kb,Kr);
//	}
	cudaMemcpy(reinterpret_cast<char*>(dest),reinterpret_cast<char*>(dest_cuda),
			out_size,cudaMemcpyDeviceToHost);
	return true;
}



bool YuriConvertYUV16_RGB24(const char *src, char *dest, void *src_cuda, void *dest_cuda,unsigned int num, float Wb, float Wr)
{
	size_t size = num*2, out_size=num*3;
	cudaMemcpy(src_cuda,src,size,cudaMemcpyHostToDevice);
	float Wg, Kb, Kr;
	Wg=1.0f-Wr-Wb;
	Kb = 0.5f / (1.0f - Wb);
	Kr = 0.5f / (1.0f - Wr);

	YUV162RGB <<<512, 8 >>> (reinterpret_cast<char*>(src_cuda), 
			reinterpret_cast<char*>(dest_cuda), num, Wb,Wr,Wg,Kb,Kr);
	cudaMemcpy(dest,dest_cuda,out_size,cudaMemcpyDeviceToHost);
	return true;
}


	.file	"tmpxft_002addf6_00000000-6_YuriConvertCuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2018:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2018:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z8_RGB2YUVPcPfS0_S0_fffff
	.type	_Z8_RGB2YUVPcPfS0_S0_fffff, @function
_Z8_RGB2YUVPcPfS0_S0_fffff:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z8_RGB2YUVPcPfS0_S0_fffff, .-_Z8_RGB2YUVPcPfS0_S0_fffff
	.globl	_Z4lumaf
	.type	_Z4lumaf, @function
_Z4lumaf:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z4lumaf, .-_Z4lumaf
	.globl	_Z6chromaf
	.type	_Z6chromaf, @function
_Z6chromaf:
.LFB2162:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4lumaf
	.cfi_endproc
.LFE2162:
	.size	_Z6chromaf, .-_Z6chromaf
	.globl	_Z3chrf
	.type	_Z3chrf, @function
_Z3chrf:
.LFB2164:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4lumaf
	.cfi_endproc
.LFE2164:
	.size	_Z3chrf, .-_Z3chrf
	.globl	_Z9CudaAllocj
	.type	_Z9CudaAllocj, @function
_Z9CudaAllocj:
.LFB2012:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, %esi
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2012:
	.size	_Z9CudaAllocj, .-_Z9CudaAllocj
	.globl	_Z11CudaDeallocPv
	.type	_Z11CudaDeallocPv, @function
_Z11CudaDeallocPv:
.LFB2013:
	.cfi_startproc
	endbr64
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2013:
	.size	_Z11CudaDeallocPv, .-_Z11CudaDeallocPv
	.globl	_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff
	.type	_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff, @function
_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rcx
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movss	%xmm3, 8(%rsp)
	movss	%xmm4, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z7RGB2YUVPcS_mfffff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L15:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff, .-_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff
	.globl	_Z7RGB2YUVPcS_mfffff
	.type	_Z7RGB2YUVPcS_mfffff, @function
_Z7RGB2YUVPcS_mfffff:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff
	.cfi_endproc
.LFE2041:
	.size	_Z7RGB2YUVPcS_mfffff, .-_Z7RGB2YUVPcS_mfffff
	.globl	_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff
	.type	_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff, @function
_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff:
.LFB2014:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %r14
	movq	%rdi, %rsi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	imull	$3, %r8d, %edx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%r13, %rdi
	movq	%rcx, %r12
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	leal	(%r8,%r8,4), %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%r8d, %ebx
	shrl	%ebp
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	call	cudaMemcpy@PLT
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edi
	salq	$3, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$9, %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L21
	movss	.LC0(%rip), %xmm4
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%r13, %rdi
	movss	.LC1(%rip), %xmm3
	movaps	%xmm4, %xmm2
	movaps	%xmm4, %xmm5
	subss	%xmm1, %xmm2
	subss	%xmm0, %xmm5
	movaps	%xmm3, %xmm4
	divss	%xmm2, %xmm4
	subss	%xmm0, %xmm2
	divss	%xmm5, %xmm3
	call	_Z34__device_stub__Z7RGB2YUVPcS_mfffffPcS_mfffff
.L21:
	movq	%rbp, %rdx
	movq	%r12, %rsi
	movq	%r14, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	movb	$1, %al
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2014:
	.size	_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff, .-_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff
	.globl	_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff
	.type	_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff, @function
_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rcx
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movss	%xmm3, 8(%rsp)
	movss	%xmm4, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z9YUV162RGBPcS_mfffff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L23:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff, .-_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff
	.globl	_Z9YUV162RGBPcS_mfffff
	.type	_Z9YUV162RGBPcS_mfffff, @function
_Z9YUV162RGBPcS_mfffff:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff
	.cfi_endproc
.LFE2043:
	.size	_Z9YUV162RGBPcS_mfffff, .-_Z9YUV162RGBPcS_mfffff
	.globl	_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff
	.type	_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff, @function
_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff:
.LFB2015:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	imull	$3, %r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	movq	%rdi, %rsi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdx, %r12
	leal	(%r8,%r8), %edx
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%r12, %rdi
	movq	%rcx, %rbp
	movl	$1, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%r8d, %ebx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	call	cudaMemcpy@PLT
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edi
	salq	$3, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$9, %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L29
	movss	.LC0(%rip), %xmm4
	movl	%ebx, %edx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	movss	.LC1(%rip), %xmm3
	movaps	%xmm4, %xmm2
	movaps	%xmm4, %xmm5
	subss	%xmm1, %xmm2
	subss	%xmm0, %xmm5
	movaps	%xmm3, %xmm4
	divss	%xmm2, %xmm4
	subss	%xmm0, %xmm2
	divss	%xmm5, %xmm3
	call	_Z36__device_stub__Z9YUV162RGBPcS_mfffffPcS_mfffff
.L29:
	movq	%r14, %rdx
	movq	%rbp, %rsi
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	movb	$1, %al
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2015:
	.size	_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff, .-_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z9YUV162RGBPcS_mfffff"
.LC3:
	.string	"_Z7RGB2YUVPcS_mfffff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2045:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9YUV162RGBPcS_mfffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7RGB2YUVPcS_mfffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2045:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1056964608
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*!
 * @file 		YuriConvertCuda.cu
 * @author 		Zdenek Travnicek
 * @date 		13.8.2010
 * @date		16.2.2013
 * @copyright	Institute of Intermedia, CTU in Prague, 2010 - 2013
 * 				Distributed under modified BSD Licence, details in file doc/LICENSE
 *
 */


#include <hip/hip_runtime.h>
//include "yuri/video/YuriConvertor.h"

__device__ void _RGB2YUV(char*s, float *Y, float *Cb, float*Cr, float Wb, float Wr, float Wg, float Kb, float Kr)
{
	float r,g,b;
	r = (float)((unsigned char)(s[0]))/255.0f;
	g = (float)((unsigned char)(s[1]))/255.0f;
	b = (float)((unsigned char)(s[2]))/255.0f;
	*Y=r*Wr + g*Wg + b*Wb;
	*Cb=(b-*Y)*Kb;
	*Cr=(r-*Y)*Kr;
}
__device__ unsigned int luma(float Y) {
	return (unsigned int)(64 + Y  * 876);
}
__device__ unsigned int chroma(float Y) {
	return (unsigned int)(512 + Y  * 896);
}
__global__ void RGB2YUV(char *s, char *d, size_t num, float Wb, float Wr, float Wg, float Kb, float Kr)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	//if (2*idx>=num) return;
	int si = 6*idx, di=5*idx;
	float Y1, Cr1, Cb1, Y2, Cb2, Cr2;
	unsigned int Ya, Yb, Cb, Cr;
	for (int i=idx;i<num;i+=4096) {
		si = i * 6;
		di = i * 5;
		_RGB2YUV(s+si+0, &Y1, &Cb1, &Cr1,  Wb, Wr, Wg, Kb, Kr);
		_RGB2YUV(s+si+3, &Y2, &Cb2, &Cr2, Wb, Wr, Wg, Kb, Kr);
		Ya = luma(Y1);
		Yb = luma(Y2);
		Cr= chroma((Cr1+Cr2)/2.0f);
		Cb= chroma((Cb1+Cb2)/2.0f);
		
		d[di]=Ya&0xFF;
		d[di+1]=((Ya>>8)&0x03) | ((Cr<<2)&0xfc); 
		d[di+2]=((Cr>>6)&0x0F) | ((Yb<<4)&0xF0); 
		d[di+3]=((Yb>>4)&0x3F) | ((Cb<<6)&0xC0);
		d[di+4]=((Cb>>2)&0xFF);
	}
}
__device__ unsigned int chr(float v) 
{
	float val = v * 255.0f;
	return (unsigned int)(val>255?255:(val<0?0:val));
}
__global__ void YUV162RGB(char *s, char *d, size_t num, float Wb, float Wr, float Wg, float Kb, float Kr)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if (2*idx>=num) return;
	int si = 6*idx, di=5*idx;
	float Y1, Y2, U, V;	
	for (int i=idx;i<num/2;i+=4096) {
		si = i * 4;
		di = i * 6;
		Y1 = (float)((unsigned char)(s[si+0]))/255.0f;
		Y2 = (float)((unsigned char)(s[si+2]))/255.0f;
		U = (float)((unsigned char)(s[si+1]))/255.0f - 0.5f;
		V = (float)((unsigned char)(s[si+3]))/255.0f - 0.5f;
		d[di+0] = chr(Y1 + 1.403*V);
		d[di+1] = chr(Y1 - 0.344*U - 0.714*V);
		d[di+2] = chr(Y1 + 1.770*U);
		d[di+3] = chr(Y2 + 1.403*V);
		d[di+4] = chr(Y2 - 0.344*U - 0.714*V);
		d[di+5] = chr(Y2 + 1.770*U);
	}
}

void *CudaAlloc(unsigned int size)
{
	void *x;
	hipMalloc((void **) &x, size*sizeof(char));
	return x;

}
void CudaDealloc(void *mem)
{
	hipFree(mem);
}

bool YuriConvertRGB24_YUV20(const char *src, char *dest, void *src_cuda, void *dest_cuda,unsigned int num, float Wb, float Wr)
{
	size_t size = num*3, out_size=num*5/2;
	hipMemcpy(reinterpret_cast<char*>(src_cuda),reinterpret_cast<const char*>(src),
			size,hipMemcpyHostToDevice);
	float Wg, Kb, Kr;
	Wg=1.0f-Wr-Wb;
	Kb = 0.5f / (1.0f - Wb);
	Kr = 0.5f / (1.0f - Wr);

//	for (int i=0;i<1000;++i) {
		RGB2YUV <<<512, 8 >>> (reinterpret_cast<char*>(src_cuda), 
				reinterpret_cast<char*>(dest_cuda), num, Wb,Wr,Wg,Kb,Kr);
//	}
	hipMemcpy(reinterpret_cast<char*>(dest),reinterpret_cast<char*>(dest_cuda),
			out_size,hipMemcpyDeviceToHost);
	return true;
}



bool YuriConvertYUV16_RGB24(const char *src, char *dest, void *src_cuda, void *dest_cuda,unsigned int num, float Wb, float Wr)
{
	size_t size = num*2, out_size=num*3;
	hipMemcpy(src_cuda,src,size,hipMemcpyHostToDevice);
	float Wg, Kb, Kr;
	Wg=1.0f-Wr-Wb;
	Kb = 0.5f / (1.0f - Wb);
	Kr = 0.5f / (1.0f - Wr);

	YUV162RGB <<<512, 8 >>> (reinterpret_cast<char*>(src_cuda), 
			reinterpret_cast<char*>(dest_cuda), num, Wb,Wr,Wg,Kb,Kr);
	hipMemcpy(dest,dest_cuda,out_size,hipMemcpyDeviceToHost);
	return true;
}


	.text
	.file	"YuriConvertCuda.hip"
	.globl	_Z22__device_stub__RGB2YUVPcS_mfffff # -- Begin function _Z22__device_stub__RGB2YUVPcS_mfffff
	.type	_Z22__device_stub__RGB2YUVPcS_mfffff,@function
_Z22__device_stub__RGB2YUVPcS_mfffff:   # @_Z22__device_stub__RGB2YUVPcS_mfffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	12(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm3, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm4, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rdi, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7RGB2YUVPcS_mfffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__RGB2YUVPcS_mfffff, .Lfunc_end0-_Z22__device_stub__RGB2YUVPcS_mfffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__YUV162RGBPcS_mfffff # -- Begin function _Z24__device_stub__YUV162RGBPcS_mfffff
	.type	_Z24__device_stub__YUV162RGBPcS_mfffff,@function
_Z24__device_stub__YUV162RGBPcS_mfffff: # @_Z24__device_stub__YUV162RGBPcS_mfffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	12(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm3, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm4, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rdi, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9YUV162RGBPcS_mfffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__YUV162RGBPcS_mfffff, .Lfunc_end1-_Z24__device_stub__YUV162RGBPcS_mfffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z9CudaAllocj                   # -- Begin function _Z9CudaAllocj
	.type	_Z9CudaAllocj,@function
_Z9CudaAllocj:                          # @_Z9CudaAllocj
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	%edi, %esi
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9CudaAllocj, .Lfunc_end2-_Z9CudaAllocj
	.cfi_endproc
                                        # -- End function
	.globl	_Z11CudaDeallocPv               # -- Begin function _Z11CudaDeallocPv
	.type	_Z11CudaDeallocPv,@function
_Z11CudaDeallocPv:                      # @_Z11CudaDeallocPv
	.cfi_startproc
# %bb.0:
	jmp	hipFree                         # TAILCALL
.Lfunc_end3:
	.size	_Z11CudaDeallocPv, .Lfunc_end3-_Z11CudaDeallocPv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff
.LCPI4_0:
	.long	0x3f800000                      # float 1
.LCPI4_1:
	.long	0x3f000000                      # float 0.5
	.text
	.globl	_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff
	.type	_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff,@function
_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff: # @_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movl	%r8d, %r15d
	movq	%rcx, %rbx
	movq	%rdx, %r12
	movq	%rsi, %r14
	movq	%rdi, %rsi
	leal	(%r15,%r15,2), %edx
	movq	%r12, %rdi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967304, %rdx               # imm = 0x100000008
	leaq	504(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movss	.LCPI4_0(%rip), %xmm5           # xmm5 = mem[0],zero,zero,zero
	movaps	%xmm5, %xmm2
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	subss	%xmm1, %xmm2
	movss	.LCPI4_1(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm4
	divss	%xmm2, %xmm4
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	subss	%xmm0, %xmm5
	divss	%xmm5, %xmm3
	subss	%xmm0, %xmm2
	movl	%r15d, %edx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_Z22__device_stub__RGB2YUVPcS_mfffff
.LBB4_2:
	leal	(%r15,%r15,4), %edx
	shrl	%edx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movb	$1, %al
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff, .Lfunc_end4-_Z22YuriConvertRGB24_YUV20PKcPcPvS2_jff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff
.LCPI5_0:
	.long	0x3f800000                      # float 1
.LCPI5_1:
	.long	0x3f000000                      # float 0.5
	.text
	.globl	_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff
	.type	_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff,@function
_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff: # @_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movl	%r8d, %r15d
	movq	%rcx, %rbx
	movq	%rdx, %r12
	movq	%rsi, %r14
	movq	%rdi, %rsi
	leal	(%r15,%r15), %edx
	movq	%r12, %rdi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967304, %rdx               # imm = 0x100000008
	leaq	504(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movss	.LCPI5_0(%rip), %xmm5           # xmm5 = mem[0],zero,zero,zero
	movaps	%xmm5, %xmm2
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	subss	%xmm1, %xmm2
	movss	.LCPI5_1(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm4
	divss	%xmm2, %xmm4
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	subss	%xmm0, %xmm5
	divss	%xmm5, %xmm3
	subss	%xmm0, %xmm2
	movl	%r15d, %edx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_Z24__device_stub__YUV162RGBPcS_mfffff
.LBB5_2:
	leal	(%r15,%r15,2), %edx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movb	$1, %al
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff, .Lfunc_end5-_Z22YuriConvertYUV16_RGB24PKcPcPvS2_jff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7RGB2YUVPcS_mfffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9YUV162RGBPcS_mfffff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7RGB2YUVPcS_mfffff,@object    # @_Z7RGB2YUVPcS_mfffff
	.section	.rodata,"a",@progbits
	.globl	_Z7RGB2YUVPcS_mfffff
	.p2align	3, 0x0
_Z7RGB2YUVPcS_mfffff:
	.quad	_Z22__device_stub__RGB2YUVPcS_mfffff
	.size	_Z7RGB2YUVPcS_mfffff, 8

	.type	_Z9YUV162RGBPcS_mfffff,@object  # @_Z9YUV162RGBPcS_mfffff
	.globl	_Z9YUV162RGBPcS_mfffff
	.p2align	3, 0x0
_Z9YUV162RGBPcS_mfffff:
	.quad	_Z24__device_stub__YUV162RGBPcS_mfffff
	.size	_Z9YUV162RGBPcS_mfffff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7RGB2YUVPcS_mfffff"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9YUV162RGBPcS_mfffff"
	.size	.L__unnamed_2, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__RGB2YUVPcS_mfffff
	.addrsig_sym _Z24__device_stub__YUV162RGBPcS_mfffff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7RGB2YUVPcS_mfffff
	.addrsig_sym _Z9YUV162RGBPcS_mfffff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7RGB2YUVPcS_mfffff    ; -- Begin function _Z7RGB2YUVPcS_mfffff
	.globl	_Z7RGB2YUVPcS_mfffff
	.p2align	8
	.type	_Z7RGB2YUVPcS_mfffff,@function
_Z7RGB2YUVPcS_mfffff:                   ; @_Z7RGB2YUVPcS_mfffff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[6:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[6:7], v[1:2]
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x2
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b128 s[12:15], s[0:1], 0x18
	s_load_b32 s5, s[0:1], 0x28
	v_mul_lo_u32 v2, v1, 6
	v_lshl_add_u32 v3, v1, 2, v1
	v_add_nc_u32_e32 v0, 0x1000, v1
	s_mov_b32 s16, 0
	s_mov_b32 s17, 0x445b0000
	s_mov_b32 s18, 0x44600000
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_mov_b32_e32 v6, 0
	v_add_nc_u32_e32 v2, 0x6000, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v1, v[4:5], off
	global_load_d16_b16 v6, v[4:5], off offset:4
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v4, v1
	v_cvt_f32_ubyte1_e32 v5, v1
	v_cvt_f32_ubyte2_e32 v7, v1
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v8, v6
	v_cvt_f32_ubyte1_e32 v6, v6
	v_div_scale_f32 v9, null, 0x437f0000, 0x437f0000, v4
	v_cvt_f32_ubyte3_e32 v1, v1
	v_div_scale_f32 v11, null, 0x437f0000, 0x437f0000, v5
	v_div_scale_f32 v13, null, 0x437f0000, 0x437f0000, v7
	v_div_scale_f32 v19, null, 0x437f0000, 0x437f0000, v6
	v_rcp_f32_e32 v21, v9
	v_div_scale_f32 v15, null, 0x437f0000, 0x437f0000, v1
	v_rcp_f32_e32 v22, v11
	v_div_scale_f32 v17, null, 0x437f0000, 0x437f0000, v8
	v_rcp_f32_e32 v23, v13
	v_rcp_f32_e32 v26, v19
	v_rcp_f32_e32 v24, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_rcp_f32_e32 v25, v17
	v_fma_f32 v27, -v9, v21, 1.0
	v_div_scale_f32 v10, vcc_lo, v4, 0x437f0000, v4
	v_fma_f32 v28, -v11, v22, 1.0
	v_div_scale_f32 v12, s0, v5, 0x437f0000, v5
	v_fmac_f32_e32 v21, v27, v21
	v_fma_f32 v29, -v13, v23, 1.0
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_2)
	v_fma_f32 v32, -v19, v26, 1.0
	v_fma_f32 v30, -v15, v24, 1.0
	v_fmac_f32_e32 v22, v28, v22
	v_fma_f32 v31, -v17, v25, 1.0
	v_fmac_f32_e32 v23, v29, v23
	v_div_scale_f32 v14, s1, v7, 0x437f0000, v7
	v_dual_fmac_f32 v26, v32, v26 :: v_dual_mul_f32 v27, v10, v21
	v_div_scale_f32 v16, s2, v1, 0x437f0000, v1
	v_dual_fmac_f32 v24, v30, v24 :: v_dual_fmac_f32 v25, v31, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v28, v12, v22 :: v_dual_mul_f32 v29, v14, v23
	v_div_scale_f32 v18, s3, v8, 0x437f0000, v8
	v_div_scale_f32 v20, s4, v6, 0x437f0000, v6
	v_fma_f32 v33, -v9, v27, v10
	v_dual_mul_f32 v30, v16, v24 :: v_dual_mul_f32 v31, v18, v25
	v_fma_f32 v34, -v11, v28, v12
	v_fma_f32 v35, -v13, v29, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v32, v20, v26 :: v_dual_fmac_f32 v27, v33, v21
	v_fma_f32 v36, -v15, v30, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v28, v34, v22 :: v_dual_fmac_f32 v29, v35, v23
	v_fma_f32 v37, -v17, v31, v18
	v_fma_f32 v9, -v9, v27, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v30, v36, v24
	v_fma_f32 v10, -v11, v28, v12
	v_fma_f32 v11, -v13, v29, v14
	v_fmac_f32_e32 v31, v37, v25
	v_div_fmas_f32 v9, v9, v21, v27
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v12, -v15, v30, v16
	v_div_fmas_f32 v10, v10, v22, v28
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v38, -v19, v32, v20
	v_fma_f32 v13, -v17, v31, v18
	v_div_fmas_f32 v11, v11, v23, v29
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v4, v9, 0x437f0000, v4
	v_div_fmas_f32 v9, v12, v24, v30
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v5, v10, 0x437f0000, v5
	v_fmac_f32_e32 v32, v38, v26
	v_div_fmas_f32 v10, v13, v25, v31
	s_mov_b32 vcc_lo, s4
	v_div_fixup_f32 v7, v11, 0x437f0000, v7
	v_mul_f32_e32 v5, s14, v5
	v_fma_f32 v14, -v19, v32, v20
	v_div_fixup_f32 v8, v10, 0x437f0000, v8
	v_div_fixup_f32 v1, v9, 0x437f0000, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v11, v14, v26, v32
	v_mul_f32_e32 v8, s14, v8
	v_fmac_f32_e32 v5, s13, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v6, v11, 0x437f0000, v6
	v_dual_fmac_f32 v8, s13, v1 :: v_dual_fmac_f32 v5, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, s12, v6 :: v_dual_sub_f32 v7, v7, v5
	v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v6, v8 :: v_dual_mul_f32 v1, s5, v1
	v_dual_mul_f32 v6, s15, v6 :: v_dual_fmac_f32 v1, s5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, s15, v7
	v_dual_fmaak_f32 v4, s17, v5, 0x42800000 :: v_dual_fmaak_f32 v5, s17, v8, 0x42800000
	v_dual_mul_f32 v1, 0.5, v1 :: v_dual_mul_f32 v6, 0.5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v4, v4
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v1, s18, v1, 0x44000000 :: v_dual_fmaak_f32 v6, s18, v6, 0x44000000
	v_bfe_u32 v7, v4, 8, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v8, 4, v5
	v_bfe_u32 v5, v5, 4, 6
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v6, v6
	v_and_b32_e32 v4, 0xff, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v9, 6, v1
	v_lshl_or_b32 v5, v6, 6, v5
	v_lshl_or_b32 v1, v1, 2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_or_b32 v7, v9, 15, v8
	v_lshlrev_b16 v5, 8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b16 v8, 8, v1
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v9, 31, v3
	v_and_b32_e32 v7, 0xff, v7
	v_or_b32_e32 v8, v4, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_le_u64_e64 s0, s[6:7], v[0:1]
	v_add_co_u32 v4, vcc_lo, s10, v3
	v_or_b32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_and_b32_e32 v7, 0xffff, v8
	v_add_nc_u32_e32 v3, 0x5000, v3
	v_lshrrev_b32_e32 v1, 2, v6
	v_add_nc_u32_e32 v0, 0x1000, v0
	v_lshlrev_b32_e32 v8, 16, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v9, vcc_lo
	s_or_b32 s16, s0, s16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v7, v8
	s_clause 0x1
	global_store_b8 v[4:5], v1, off offset:4
	global_store_b32 v[4:5], v6, off
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow76
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7RGB2YUVPcS_mfffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7RGB2YUVPcS_mfffff, .Lfunc_end0-_Z7RGB2YUVPcS_mfffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1132
; NumSgprs: 21
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9YUV162RGBPcS_mfffff  ; -- Begin function _Z9YUV162RGBPcS_mfffff
	.globl	_Z9YUV162RGBPcS_mfffff
	.p2align	8
	.type	_Z9YUV162RGBPcS_mfffff,@function
_Z9YUV162RGBPcS_mfffff:                 ; @_Z9YUV162RGBPcS_mfffff
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_lshlrev_b32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_cmpx_gt_u64_e64 s[2:3], v[2:3]
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.preheader
	v_ashrrev_i32_e32 v2, 31, v1
	s_lshr_b64 s[8:9], s[2:3], 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v2, v1, 6
	v_add_nc_u32_e32 v0, 0x1000, v1
	v_lshlrev_b32_e32 v3, 2, v1
	s_mov_b32 s10, 0x20c49ba6
	s_mov_b32 s12, 0x9374bc6a
	s_mov_b32 s14, 0x872b020c
	s_mov_b32 s16, 0x851eb852
	s_mov_b32 s11, 0x3ff672b0
	s_mov_b32 s13, 0xbfd60418
	s_mov_b32 s15, 0xbfe6d916
	s_mov_b32 s17, 0x3ffc51eb
	s_mov_b32 s18, 0
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v3
	v_add_nc_u32_e32 v3, 0x4000, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v4, v1
	v_cvt_f32_ubyte2_e32 v5, v1
	v_cvt_f32_ubyte1_e32 v6, v1
	v_cvt_f32_ubyte3_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v7, null, 0x437f0000, 0x437f0000, v4
	v_div_scale_f32 v9, null, 0x437f0000, 0x437f0000, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v11, null, 0x437f0000, 0x437f0000, v6
	v_rcp_f32_e32 v15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v16, v9
	v_div_scale_f32 v13, null, 0x437f0000, 0x437f0000, v1
	v_rcp_f32_e32 v17, v11
	v_div_scale_f32 v8, vcc_lo, v4, 0x437f0000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v18, v13
	v_div_scale_f32 v10, s0, v5, 0x437f0000, v5
	v_fma_f32 v19, -v7, v15, 1.0
	v_fma_f32 v20, -v9, v16, 1.0
	v_div_scale_f32 v12, s1, v6, 0x437f0000, v6
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v21, -v11, v17, 1.0
	v_dual_fmac_f32 v15, v19, v15 :: v_dual_fmac_f32 v16, v20, v16
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v22, -v13, v18, 1.0
	v_div_scale_f32 v14, s2, v1, 0x437f0000, v1
	v_fmac_f32_e32 v17, v21, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v19, v8, v15 :: v_dual_mul_f32 v20, v10, v16
	v_dual_fmac_f32 v18, v22, v18 :: v_dual_mul_f32 v21, v12, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v23, -v7, v19, v8
	v_fma_f32 v24, -v9, v20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v22, v14, v18
	v_fma_f32 v25, -v11, v21, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, v23, v15 :: v_dual_fmac_f32 v20, v24, v16
	v_fma_f32 v26, -v13, v22, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, v25, v17
	v_fma_f32 v7, -v7, v19, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v8, -v9, v20, v10
	v_fmac_f32_e32 v22, v26, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v9, -v11, v21, v12
	v_div_fmas_f32 v7, v7, v15, v19
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v10, -v13, v22, v14
	v_div_fmas_f32 v8, v8, v16, v20
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v4, v7, 0x437f0000, v4
	v_div_fmas_f32 v9, v9, v17, v21
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v8, v8, 0x437f0000, v5
	v_div_fmas_f32 v10, v10, v18, v22
	v_cvt_f64_f32_e32 v[4:5], v4
	v_div_fixup_f32 v6, v9, 0x437f0000, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_f32_e32 v[8:9], v8
	v_div_fixup_f32 v1, v10, 0x437f0000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, -0.5, v6 :: v_dual_add_f32 v1, -0.5, v1
	v_cvt_f64_f32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[10:11], v1
	v_ashrrev_i32_e32 v1, 31, v0
	v_fma_f64 v[12:13], v[6:7], s[12:13], v[4:5]
	v_fma_f64 v[14:15], v[6:7], s[12:13], v[8:9]
	v_fma_f64 v[16:17], v[6:7], s[16:17], v[4:5]
	v_fma_f64 v[4:5], v[10:11], s[10:11], v[4:5]
	v_fma_f64 v[18:19], v[10:11], s[10:11], v[8:9]
	v_fma_f64 v[6:7], v[6:7], s[16:17], v[8:9]
	v_fma_f64 v[12:13], v[10:11], s[14:15], v[12:13]
	v_fma_f64 v[8:9], v[10:11], s[14:15], v[14:15]
	v_cvt_f32_f64_e32 v10, v[16:17]
	v_cvt_f32_f64_e32 v5, v[4:5]
	v_cvt_f32_f64_e32 v11, v[18:19]
	v_cvt_f32_f64_e32 v6, v[6:7]
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_cvt_f32_f64_e32 v12, v[12:13]
	v_cvt_f32_f64_e32 v7, v[8:9]
	v_mul_f32_e32 v9, 0x437f0000, v10
	v_dual_mul_f32 v5, 0x437f0000, v5 :: v_dual_mul_f32 v10, 0x437f0000, v11
	v_mul_f32_e32 v6, 0x437f0000, v6
	v_ashrrev_i32_e32 v8, 31, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ngt_f32_e64 s0, 0, v9
	v_cmp_ngt_f32_e64 s2, 0, v5
	v_cmp_ngt_f32_e64 s3, 0, v10
	v_cmp_ngt_f32_e64 s1, 0, v6
	v_add_nc_u32_e32 v2, 0x6000, v2
	v_cndmask_b32_e64 v11, 0, v9, s0
	v_cmp_nlt_f32_e64 s0, 0x437f0000, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 0, v6, s1
	v_cmp_nlt_f32_e64 s1, 0x437f0000, v6
	v_cndmask_b32_e64 v6, 0, v5, s2
	v_cmp_nlt_f32_e64 s2, 0x437f0000, v5
	v_cndmask_b32_e64 v5, 0, v10, s3
	v_cmp_nlt_f32_e64 s3, 0x437f0000, v10
	v_cndmask_b32_e64 v10, 0x437f0000, v11, s0
	v_cndmask_b32_e64 v9, 0x437f0000, v9, s1
	v_cndmask_b32_e64 v6, 0x437f0000, v6, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, 0x437f0000, v5, s3
	v_cvt_u32_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v9, v9
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v5, v5
	v_and_b32_e32 v10, 0xff, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b16 v9, 8, v9
	v_and_b32_e32 v6, 0xff, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b16 v5, 8, v5
	v_mul_f32_e32 v7, 0x437f0000, v7
	v_or_b32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, 0x437f0000, v12 :: v_dual_lshlrev_b32 v10, 16, v5
	v_cmp_ngt_f32_e64 s0, 0, v11
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, 0, v11, s0
	v_cmp_nlt_f32_e64 s0, 0x437f0000, v11
	v_cndmask_b32_e64 v11, 0x437f0000, v12, s0
	v_cmp_ngt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v11, v11
	v_cndmask_b32_e64 v12, 0, v7, s0
	v_cmp_nlt_f32_e64 s0, 0x437f0000, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b16 v11, 8, v11
	v_cndmask_b32_e64 v7, 0x437f0000, v12, s0
	v_cmp_le_u64_e64 s0, s[8:9], v[0:1]
	v_add_nc_u32_e32 v0, 0x1000, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_or_b32_e32 v6, v6, v11
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 s18, s0, s18
	v_and_b32_e32 v6, 0xffff, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v7, 0xff, v7
	v_or_b32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v1, v7, v9
	s_clause 0x1
	global_store_b16 v[4:5], v1, off offset:4
	global_store_b32 v[4:5], v6, off
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB1_3
.LBB1_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9YUV162RGBPcS_mfffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9YUV162RGBPcS_mfffff, .Lfunc_end1-_Z9YUV162RGBPcS_mfffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1312
; NumSgprs: 21
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7RGB2YUVPcS_mfffff
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z7RGB2YUVPcS_mfffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9YUV162RGBPcS_mfffff
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z9YUV162RGBPcS_mfffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
