#include <cuda.h>
#include <cufft.h>
#include <cuda_profiler_api.h>
#include <stdio.h>

template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
	return __ldg(ptr);
#else
	return *ptr;
#endif
}

#ifndef PI_8
#define PI_8 0.39269908169
#endif

extern "C"
__global__
void Thin(
int nz
, int ny
, int nx
, float threshold
, float * theta // theta (in)
, float * like // like (in)
, float * thin // thin (out)
)
{
	int kz = blockIdx.x*blockDim.x + threadIdx.x;
	int ky = blockIdx.y*blockDim.y + threadIdx.y;
	if (kz < nz && ky+1 < ny && ky >= 1)
	{
		float val;
		int ind;
		for (int kx = 1; kx+1 < nx; kx++)
		{
			ind = (kz*ny + ky)*nx + kx;
      float central = like[ind];
      if(central>threshold)
      {
        float orientation = theta[ind];
        if(orientation<PI_8||orientation>7*PI_8)
        {
          // x oriented
          // compare (x,y,z) to (x+1,y,z) and (x-1,y,z)
          if(central>like[ind+1] && central>like[ind-1])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
        else if(orientation<3*PI_8)
        {
          // xy diagonal
          // compare (x,y,z) to (x+1,y+1,z) and (x-1,y-1,z)
          if(central>like[ind+nx+1] && central>like[ind-nx-1])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
        else if(orientation<5*PI_8)
        {
          // y oriented
          // compare (x,y,z) to (x,y+1,z) and (x,y-1,z)
          if(central>like[ind+nx] && central>like[ind-nx])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
        else 
        {
          // -xy diagonal
          // compare (x,y,z) to (x-1,y+1,z) and (x+1,y-1,z)
          if(central>like[ind+nx-1] && central>like[ind-nx+1])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
      }
      else
      {
        thin[ind] = 0;
      }
		}
	}
}


	.file	"tmpxft_003158d4_00000000-6_cu_thin.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2053:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z4ThiniiifPfS_S_iiifPfS_S_
	.type	_Z31__device_stub__Z4ThiniiifPfS_S_iiifPfS_S_, @function
_Z31__device_stub__Z4ThiniiifPfS_S_iiifPfS_S_:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	Thin(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z31__device_stub__Z4ThiniiifPfS_S_iiifPfS_S_, .-_Z31__device_stub__Z4ThiniiifPfS_S_iiifPfS_S_
	.globl	Thin
	.type	Thin, @function
Thin:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z4ThiniiifPfS_S_iiifPfS_S_
	.cfi_endproc
.LFE2076:
	.size	Thin, .-Thin
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Thin"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2078:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	Thin(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2078:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>

template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
	return __ldg(ptr);
#else
	return *ptr;
#endif
}

#ifndef PI_8
#define PI_8 0.39269908169
#endif

extern "C"
__global__
void Thin(
int nz
, int ny
, int nx
, float threshold
, float * theta // theta (in)
, float * like // like (in)
, float * thin // thin (out)
)
{
	int kz = blockIdx.x*blockDim.x + threadIdx.x;
	int ky = blockIdx.y*blockDim.y + threadIdx.y;
	if (kz < nz && ky+1 < ny && ky >= 1)
	{
		float val;
		int ind;
		for (int kx = 1; kx+1 < nx; kx++)
		{
			ind = (kz*ny + ky)*nx + kx;
      float central = like[ind];
      if(central>threshold)
      {
        float orientation = theta[ind];
        if(orientation<PI_8||orientation>7*PI_8)
        {
          // x oriented
          // compare (x,y,z) to (x+1,y,z) and (x-1,y,z)
          if(central>like[ind+1] && central>like[ind-1])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
        else if(orientation<3*PI_8)
        {
          // xy diagonal
          // compare (x,y,z) to (x+1,y+1,z) and (x-1,y-1,z)
          if(central>like[ind+nx+1] && central>like[ind-nx-1])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
        else if(orientation<5*PI_8)
        {
          // y oriented
          // compare (x,y,z) to (x,y+1,z) and (x,y-1,z)
          if(central>like[ind+nx] && central>like[ind-nx])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
        else 
        {
          // -xy diagonal
          // compare (x,y,z) to (x-1,y+1,z) and (x+1,y-1,z)
          if(central>like[ind+nx-1] && central>like[ind-nx+1])
          {
            thin[ind] = like[ind];
          }
          else
          {
            thin[ind] = 0;
          }
        }
      }
      else
      {
        thin[ind] = 0;
      }
		}
	}
}


	.text
	.file	"cu_thin.hip"
	.globl	__device_stub__Thin             # -- Begin function __device_stub__Thin
	.type	__device_stub__Thin,@function
__device_stub__Thin:                    # @__device_stub__Thin
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	56(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$Thin, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__Thin, .Lfunc_end0-__device_stub__Thin
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$Thin, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	Thin,@object                    # @Thin
	.section	.rodata,"a",@progbits
	.globl	Thin
	.p2align	3, 0x0
Thin:
	.quad	__device_stub__Thin
	.size	Thin, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"Thin"
	.size	.L__unnamed_1, 5

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__Thin
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym Thin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	Thin                    ; -- Begin function Thin
	.globl	Thin
	.p2align	8
	.type	Thin,@function
Thin:                                   ; @Thin
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_35
; %bb.1:
	v_bfe_u32 v0, v0, 10, 10
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v2
	v_cmp_lt_i32_e64 s2, 0, v2
	v_cmp_gt_i32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_35
; %bb.2:                                ; %.preheader
	s_cmp_lt_i32 s6, 3
	s_cbranch_scc1 .LBB0_35
; %bb.3:                                ; %.lr.ph
	v_mul_lo_u32 v1, v1, s5
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x20
	s_ashr_i32 s17, s6, 31
	s_mov_b32 s16, s6
	s_mov_b32 s4, 0x5441c730
	s_mov_b32 s12, 0xe9b98e4a
	s_mov_b32 s5, 0x3fd921fb
	s_mov_b32 s13, 0x4005fdbb
	v_add_nc_u32_e32 v3, v1, v2
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, v3, s6, 1
	v_add3_u32 v0, v0, s15, -1
	s_mov_b32 s14, 0x7f315564
	s_mov_b32 s15, 0x3ff2d97c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, s6, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s1, s10, 4
	s_addc_u32 s18, s11, 0
	s_lshl_b64 s[22:23], s[16:17], 2
	s_add_i32 s6, s6, -2
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_sub_u32 s19, s10, s22
	s_subb_u32 s20, s11, s23
	s_mov_b32 s16, 0x295238fc
	s_add_u32 s21, s1, s22
	s_mov_b32 s17, 0x3fff6a7a
	s_addc_u32 s22, s18, s23
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v4, vcc_lo, s1, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s18, v3, vcc_lo
	v_mov_b32_e32 v1, 0
	s_mov_b32 s23, exec_lo
	global_load_b32 v8, v[4:5], off offset:-4
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 s7, v8
	s_cbranch_execz .LBB0_34
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v6, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[6:7], v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, s[4:5], v[6:7]
	v_cmp_nlt_f64_e64 s0, s[12:13], v[6:7]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s24, s0
	s_xor_b32 s0, exec_lo, s24
	s_cbranch_execz .LBB0_27
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s24, exec_lo
	v_cmpx_ngt_f64_e32 s[14:15], v[6:7]
	s_xor_b32 s24, exec_lo, s24
	s_cbranch_execz .LBB0_20
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s25, exec_lo
	v_cmpx_ngt_f64_e32 s[16:17], v[6:7]
	s_xor_b32 s25, exec_lo, s25
	s_cbranch_execz .LBB0_13
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v4, vcc_lo, s21, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s22, v3, vcc_lo
	s_mov_b32 s27, exec_lo
	global_load_b32 v1, v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s26, v8, v1
	v_cmpx_gt_f32_e32 v8, v1
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v4, vcc_lo, s19, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s20, v3, vcc_lo
	s_and_not1_b32 s26, s26, exec_lo
	global_load_b32 v1, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v8, v1
	s_and_b32 s28, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s26, s26, s28
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s27, s26
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v8, 0
; %bb.12:                               ; %Flow148
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
.LBB0_13:                               ; %Flow152
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s25, s25
	s_cbranch_execz .LBB0_19
; %bb.14:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v4, vcc_lo, s21, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s22, v3, vcc_lo
	s_mov_b32 s27, exec_lo
	global_load_b32 v1, v[4:5], off offset:-4
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s26, v8, v1
	v_cmpx_gt_f32_e32 v8, v1
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v4, vcc_lo, s19, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s20, v3, vcc_lo
	s_and_not1_b32 s26, s26, exec_lo
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v8, v1
	s_and_b32 s28, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s26, s26, s28
.LBB0_16:                               ; %Flow150
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s27, s26
; %bb.17:                               ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v8, 0
; %bb.18:                               ; %Flow151
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
.LBB0_19:                               ; %Flow153
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s25
.LBB0_20:                               ; %Flow157
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s24, s24
	s_cbranch_execz .LBB0_26
; %bb.21:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v4, vcc_lo, s21, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s22, v3, vcc_lo
	s_mov_b32 s26, exec_lo
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s25, v8, v1
	v_cmpx_gt_f32_e32 v8, v1
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s25, s25, exec_lo
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v8, v1
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB0_23:                               ; %Flow155
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s26, s25
; %bb.24:                               ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v8, 0
; %bb.25:                               ; %Flow156
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
.LBB0_26:                               ; %Flow158
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s24
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_27:                               ; %Flow162
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_33
; %bb.28:                               ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v1, v[4:5], off
	s_mov_b32 s25, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s24, v8, v1
	v_cmpx_gt_f32_e32 v8, v1
	s_cbranch_execz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v1, v[4:5], off offset:-8
	s_and_not1_b32 s24, s24, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v8, v1
	s_and_b32 s26, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s24, s24, s26
.LBB0_30:                               ; %Flow160
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s25, s24
; %bb.31:                               ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v8, 0
; %bb.32:                               ; %Flow161
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
.LBB0_33:                               ; %Flow163
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v1, v8
.LBB0_34:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_add_co_u32 v4, vcc_lo, s2, v2
	s_add_i32 s6, s6, -1
	s_add_u32 s2, s2, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_addc_u32 s3, s3, 0
	s_add_u32 s19, s19, 4
	s_addc_u32 s20, s20, 0
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_add_u32 s21, s21, 4
	v_add_nc_u32_e32 v0, 1, v0
	s_addc_u32 s22, s22, 0
	s_add_u32 s1, s1, 4
	s_addc_u32 s18, s18, 0
	s_cmp_lg_u32 s6, 0
	global_store_b32 v[4:5], v1, off
	s_cbranch_scc1 .LBB0_4
.LBB0_35:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel Thin
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 29
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	Thin, .Lfunc_end0-Thin
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1040
; NumSgprs: 31
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 31
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           Thin
    .private_segment_fixed_size: 0
    .sgpr_count:     31
    .sgpr_spill_count: 0
    .symbol:         Thin.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
