/*
 *  file name: convolution2D.cu
 *
 *  CPE810A: Homework 3: Convolution
 *  
 *  Yupeng Cao, 10454637
 *  
 */

#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>

// Define constant memory for kernel storage on Device
#define KERNEL_RADIUS 3
#define KERNEL_W (2 * KERNEL_RADIUS + 1)
__device__ __constant__ float d_Kernel[KERNEL_W];


#define TILE_W 16		// active cell width
#define TILE_H 16		// active cell height
#define TILE_SIZE (TILE_W + KERNEL_RADIUS * 2) * (TILE_W + KERNEL_RADIUS * 2)

#define IMUL(a,b) __mul24(a,b)
#define UNROLL_INNER


__global__ void convolutionRowGPU(
    float *d_Result,
    float *d_Data,
    int dataW,
    int dataH
)
{
    // Data cache: threadIdx.x , threadIdx.y
    __shared__ float data[ TILE_H * (TILE_W + KERNEL_RADIUS * 2) ];
	
	// global mem address of this thread
	const int gLoc = threadIdx.x + 
					 IMUL(blockIdx.x, blockDim.x) +
    				 IMUL(threadIdx.y, dataW) +
    				 IMUL(blockIdx.y, blockDim.y) * dataW;
    				     
    // load cache (32x16 shared memory, 16x16 threads blocks)
    // each threads loads two values from global memory into shared mem
    // if in image area, get value in global mem, else 0
	int x;		// image based coordinate

	// original image based coordinate
	const int x0 = threadIdx.x + IMUL(blockIdx.x, blockDim.x);
	const int shift = threadIdx.y * (TILE_W + KERNEL_RADIUS * 2);

	// right
	x = x0 + KERNEL_RADIUS;
	if ( x > dataW-1 )
		data[threadIdx.x + blockDim.x + shift] = 0;
	else	
		data[threadIdx.x + blockDim.x + shift] = d_Data[gLoc + KERNEL_RADIUS];
    
    __syncthreads();

	// convolution
	float sum = 0;
	x = KERNEL_RADIUS + threadIdx.x;
	for (int i = -KERNEL_RADIUS; i <= KERNEL_RADIUS; i++)
		sum += data[x + i + shift] * d_Kernel[KERNEL_RADIUS + i];

    d_Result[gLoc] = sum;

}

__global__ void convolutionColGPU(
    float *d_Result,
    float *d_Data,
    int dataW,
    int dataH
)
{
    // Data cache: threadIdx.x , threadIdx.y
    __shared__ float data[TILE_W * (TILE_H + KERNEL_RADIUS * 2)];
	
	// global mem address of this thread
	const int gLoc = threadIdx.x + 
					 IMUL(blockIdx.x, blockDim.x) +
    				 IMUL(threadIdx.y, dataW) +
    				 IMUL(blockIdx.y, blockDim.y) * dataW;
    				     
    // load cache (32x16 shared memory, 16x16 threads blocks)
    // each threads loads two values from global memory into shared mem
    // if in image area, get value in global mem, else 0
	int y;		// image based coordinate

	// original image based coordinate
	const int y0 = threadIdx.y + IMUL(blockIdx.y, blockDim.y);
	const int shift = threadIdx.y * (TILE_W);
	
	// case2: lower
	y = y0 + KERNEL_RADIUS;
	const int shift1 = shift + IMUL(blockDim.y, TILE_W);
	if ( y > dataH-1 )
		data[threadIdx.x + shift1] = 0;
	else	
		data[threadIdx.x + shift1] = d_Data[gLoc + IMUL(dataW, KERNEL_RADIUS)];
    
    __syncthreads();

	// convolution
	float sum = 0;
	for (int i = 0; i <= KERNEL_RADIUS*2; i++)
		sum += data[threadIdx.x + (threadIdx.y + i) * TILE_W] * d_Kernel[i];

    d_Result[gLoc] = sum;

}
/*
*********************************************************************
Main Function
*********************************************************************
*/
int main(int argc, char *argv[])
{   

    // Check input parameter
    if (argc == 4){
        printf("Input Data\n");
    }else{
        printf("Error input Parameter \n");
        printf("Please Follow Format to Run Program: ./execute_file <dimX> <dimY> <dimK>\n");
        printf("Please input <dimX>, <dimY>, <dimK> \n");
        printf("dimX and dimY are width and heights for input image and dimK is size for mask \n");
        return 0;
    }
    
    int dimX = atoi(argv[1]);
    int dimY = atoi(argv[2]);
    int dimK = atoi(argv[3]);

    if (dimK != KERNEL_RADIUS){
        printf("Please change KERNEKL_RADIUS values \n");   
        printf("Keep dimK = KERNEKL_RADIUS \n");  
        return -1;
    }
    
    
    // Initialize image size and kernel size
    unsigned int img_size = dimX * dimY;
    const int kernel_length = dimK;

    // Allocate space on host
    float *h_Kernel, *h_Input, *h_OutputCPU, *h_OutputGPU;
    h_Kernel    = (float *)malloc(kernel_length * sizeof(float));
    h_Input     = (float *)malloc(img_size * sizeof(float));
    h_OutputCPU = (float *)malloc(img_size * sizeof(float));
    h_OutputGPU = (float *)malloc(img_size * sizeof(float));

    // Initialize Mask and Image. 
    srand(200);
    for (unsigned int i = 0; i < kernel_length; i++)
    {
        h_Kernel[i] = (float)(rand() % 16);
    }

    for (unsigned i = 0; i < img_size; i++)
    {
        h_Input[i] = (float)(rand() % 16);
    }

    float *d_Input, *d_Temporary_Output, *d_Output;
    cudaMalloc((void **)&d_Input,   img_size * sizeof(float));
    cudaMalloc((void **)&d_Temporary_Output,  img_size * sizeof(float));
    cudaMalloc((void **)&d_Output,  img_size * sizeof(float));

    cudaMemcpy(d_Input, h_Input, img_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpyToSymbol(d_Kernel, h_Kernel, kernel_length);

    dim3 blocks(TILE_W, TILE_H);
	dim3 grids(dimX/TILE_W, dimY/TILE_H);

    convolutionRowGPU<<<grids, blocks>>>(d_Temporary_Output, d_Input, dimX, dimY);
    cudaDeviceSynchronize();
    convolutionColGPU<<<grids, blocks>>>(d_Output, d_Temporary_Output, dimX, dimY);
    cudaDeviceSynchronize();

    return 0;

}

	.file	"tmpxft_0021b76b_00000000-6_convolution.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii
	.type	_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii, @function
_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17convolutionRowGPUPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii, .-_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii
	.globl	_Z17convolutionRowGPUPfS_ii
	.type	_Z17convolutionRowGPUPfS_ii, @function
_Z17convolutionRowGPUPfS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z17convolutionRowGPUPfS_ii, .-_Z17convolutionRowGPUPfS_ii
	.globl	_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii
	.type	_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii, @function
_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17convolutionColGPUPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii, .-_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii
	.globl	_Z17convolutionColGPUPfS_ii
	.type	_Z17convolutionColGPUPfS_ii, @function
_Z17convolutionColGPUPfS_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii
	.cfi_endproc
.LFE2055:
	.size	_Z17convolutionColGPUPfS_ii, .-_Z17convolutionColGPUPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Input Data\n"
.LC1:
	.string	"Error input Parameter \n"
.LC2:
	.string	"Please Follow Format to Run Program: ./execute_file <dimX> <dimY> <dimK>\n"
.LC3:
	.string	"Please input <dimX>, <dimY>, <dimK> \n"
.LC4:
	.string	"dimX and dimY are width and heights for input image and dimK is size for mask \n"
.LC5:
	.string	"Please change KERNEKL_RADIUS values \n"
.LC6:
	.string	"Keep dimK = KERNEKL_RADIUS \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	cmpl	$4, %edi
	jne	.L14
	movq	%rsi, %rbx
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	call	__printf_chk@PLT
	movq	8(%rbx), %rdi
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	cmpl	$3, %eax
	je	.L26
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L13
.L14:
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L17
.L26:
	movl	%ebp, %ebx
	movl	$12, %edi
	movl	$16, %r15d
	call	malloc@PLT
	imull	%r12d, %ebx
	movq	%rax, %r14
	leaq	0(,%rbx,4), %rax
	xorl	%ebx, %ebx
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movl	$200, %edi
	movq	%rax, %r13
	call	srand@PLT
.L19:
	call	rand@PLT
	cltd
	idivl	%r15d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r14,%rbx,4)
	incq	%rbx
	cmpq	$3, %rbx
	jne	.L19
	movq	8(%rsp), %rax
	movq	%r13, %rbx
	leaq	(%rax,%r13), %r15
.L20:
	cmpq	%r15, %rbx
	je	.L28
	call	rand@PLT
	movl	$16, %ecx
	addq	$4, %rbx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, -4(%rbx)
	jmp	.L20
.L28:
	movq	8(%rsp), %rsi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%r14, %rsi
	movl	$3, %edx
	leaq	_ZL8d_Kernel(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	%ebp, %eax
	movl	$16, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rsi
	movl	$1, 56(%rsp)
	idivl	%ecx
	movq	%rsi, 48(%rsp)
	movl	$1, 68(%rsp)
	movl	%eax, 60(%rsp)
	movl	%r12d, %eax
	cltd
	idivl	%ecx
	movq	%rsi, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movl	%eax, 64(%rsp)
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z41__device_stub__Z17convolutionRowGPUPfS_iiPfS_ii
.L22:
	call	cudaDeviceSynchronize@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z41__device_stub__Z17convolutionColGPUPfS_iiPfS_ii
.L23:
	call	cudaDeviceSynchronize@PLT
.L17:
	xorl	%eax, %eax
.L13:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z17convolutionColGPUPfS_ii"
.LC8:
	.string	"_Z17convolutionRowGPUPfS_ii"
.LC9:
	.string	"d_Kernel"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17convolutionColGPUPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17convolutionRowGPUPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movl	$28, %r9d
	leaq	_ZL8d_Kernel(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL8d_Kernel
	.comm	_ZL8d_Kernel,28,16
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 *  file name: convolution2D.cu
 *
 *  CPE810A: Homework 3: Convolution
 *  
 *  Yupeng Cao, 10454637
 *  
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>

// Define constant memory for kernel storage on Device
#define KERNEL_RADIUS 3
#define KERNEL_W (2 * KERNEL_RADIUS + 1)
__device__ __constant__ float d_Kernel[KERNEL_W];


#define TILE_W 16		// active cell width
#define TILE_H 16		// active cell height
#define TILE_SIZE (TILE_W + KERNEL_RADIUS * 2) * (TILE_W + KERNEL_RADIUS * 2)

#define IMUL(a,b) __mul24(a,b)
#define UNROLL_INNER


__global__ void convolutionRowGPU(
    float *d_Result,
    float *d_Data,
    int dataW,
    int dataH
)
{
    // Data cache: threadIdx.x , threadIdx.y
    __shared__ float data[ TILE_H * (TILE_W + KERNEL_RADIUS * 2) ];
	
	// global mem address of this thread
	const int gLoc = threadIdx.x + 
					 IMUL(blockIdx.x, blockDim.x) +
    				 IMUL(threadIdx.y, dataW) +
    				 IMUL(blockIdx.y, blockDim.y) * dataW;
    				     
    // load cache (32x16 shared memory, 16x16 threads blocks)
    // each threads loads two values from global memory into shared mem
    // if in image area, get value in global mem, else 0
	int x;		// image based coordinate

	// original image based coordinate
	const int x0 = threadIdx.x + IMUL(blockIdx.x, blockDim.x);
	const int shift = threadIdx.y * (TILE_W + KERNEL_RADIUS * 2);

	// right
	x = x0 + KERNEL_RADIUS;
	if ( x > dataW-1 )
		data[threadIdx.x + blockDim.x + shift] = 0;
	else	
		data[threadIdx.x + blockDim.x + shift] = d_Data[gLoc + KERNEL_RADIUS];
    
    __syncthreads();

	// convolution
	float sum = 0;
	x = KERNEL_RADIUS + threadIdx.x;
	for (int i = -KERNEL_RADIUS; i <= KERNEL_RADIUS; i++)
		sum += data[x + i + shift] * d_Kernel[KERNEL_RADIUS + i];

    d_Result[gLoc] = sum;

}

__global__ void convolutionColGPU(
    float *d_Result,
    float *d_Data,
    int dataW,
    int dataH
)
{
    // Data cache: threadIdx.x , threadIdx.y
    __shared__ float data[TILE_W * (TILE_H + KERNEL_RADIUS * 2)];
	
	// global mem address of this thread
	const int gLoc = threadIdx.x + 
					 IMUL(blockIdx.x, blockDim.x) +
    				 IMUL(threadIdx.y, dataW) +
    				 IMUL(blockIdx.y, blockDim.y) * dataW;
    				     
    // load cache (32x16 shared memory, 16x16 threads blocks)
    // each threads loads two values from global memory into shared mem
    // if in image area, get value in global mem, else 0
	int y;		// image based coordinate

	// original image based coordinate
	const int y0 = threadIdx.y + IMUL(blockIdx.y, blockDim.y);
	const int shift = threadIdx.y * (TILE_W);
	
	// case2: lower
	y = y0 + KERNEL_RADIUS;
	const int shift1 = shift + IMUL(blockDim.y, TILE_W);
	if ( y > dataH-1 )
		data[threadIdx.x + shift1] = 0;
	else	
		data[threadIdx.x + shift1] = d_Data[gLoc + IMUL(dataW, KERNEL_RADIUS)];
    
    __syncthreads();

	// convolution
	float sum = 0;
	for (int i = 0; i <= KERNEL_RADIUS*2; i++)
		sum += data[threadIdx.x + (threadIdx.y + i) * TILE_W] * d_Kernel[i];

    d_Result[gLoc] = sum;

}
/*
*********************************************************************
Main Function
*********************************************************************
*/
int main(int argc, char *argv[])
{   

    // Check input parameter
    if (argc == 4){
        printf("Input Data\n");
    }else{
        printf("Error input Parameter \n");
        printf("Please Follow Format to Run Program: ./execute_file <dimX> <dimY> <dimK>\n");
        printf("Please input <dimX>, <dimY>, <dimK> \n");
        printf("dimX and dimY are width and heights for input image and dimK is size for mask \n");
        return 0;
    }
    
    int dimX = atoi(argv[1]);
    int dimY = atoi(argv[2]);
    int dimK = atoi(argv[3]);

    if (dimK != KERNEL_RADIUS){
        printf("Please change KERNEKL_RADIUS values \n");   
        printf("Keep dimK = KERNEKL_RADIUS \n");  
        return -1;
    }
    
    
    // Initialize image size and kernel size
    unsigned int img_size = dimX * dimY;
    const int kernel_length = dimK;

    // Allocate space on host
    float *h_Kernel, *h_Input, *h_OutputCPU, *h_OutputGPU;
    h_Kernel    = (float *)malloc(kernel_length * sizeof(float));
    h_Input     = (float *)malloc(img_size * sizeof(float));
    h_OutputCPU = (float *)malloc(img_size * sizeof(float));
    h_OutputGPU = (float *)malloc(img_size * sizeof(float));

    // Initialize Mask and Image. 
    srand(200);
    for (unsigned int i = 0; i < kernel_length; i++)
    {
        h_Kernel[i] = (float)(rand() % 16);
    }

    for (unsigned i = 0; i < img_size; i++)
    {
        h_Input[i] = (float)(rand() % 16);
    }

    float *d_Input, *d_Temporary_Output, *d_Output;
    hipMalloc((void **)&d_Input,   img_size * sizeof(float));
    hipMalloc((void **)&d_Temporary_Output,  img_size * sizeof(float));
    hipMalloc((void **)&d_Output,  img_size * sizeof(float));

    hipMemcpy(d_Input, h_Input, img_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpyToSymbol(HIP_SYMBOL(d_Kernel), h_Kernel, kernel_length);

    dim3 blocks(TILE_W, TILE_H);
	dim3 grids(dimX/TILE_W, dimY/TILE_H);

    convolutionRowGPU<<<grids, blocks>>>(d_Temporary_Output, d_Input, dimX, dimY);
    hipDeviceSynchronize();
    convolutionColGPU<<<grids, blocks>>>(d_Output, d_Temporary_Output, dimX, dimY);
    hipDeviceSynchronize();

    return 0;

}

	.text
	.file	"convolution.hip"
	.globl	_Z32__device_stub__convolutionRowGPUPfS_ii # -- Begin function _Z32__device_stub__convolutionRowGPUPfS_ii
	.type	_Z32__device_stub__convolutionRowGPUPfS_ii,@function
_Z32__device_stub__convolutionRowGPUPfS_ii: # @_Z32__device_stub__convolutionRowGPUPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17convolutionRowGPUPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__convolutionRowGPUPfS_ii, .Lfunc_end0-_Z32__device_stub__convolutionRowGPUPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__convolutionColGPUPfS_ii # -- Begin function _Z32__device_stub__convolutionColGPUPfS_ii
	.type	_Z32__device_stub__convolutionColGPUPfS_ii,@function
_Z32__device_stub__convolutionColGPUPfS_ii: # @_Z32__device_stub__convolutionColGPUPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17convolutionColGPUPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__convolutionColGPUPfS_ii, .Lfunc_end1-_Z32__device_stub__convolutionColGPUPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$4, %edi
	jne	.LBB2_13
# %bb.1:
	movq	%rsi, %r15
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movq	8(%r15), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	16(%r15), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	24(%r15), %rdi
	callq	atoi
	cmpl	$3, %eax
	jne	.LBB2_2
# %bb.11:
	movl	%r14d, %r13d
	movq	%rbx, 16(%rsp)                  # 8-byte Spill
	imull	%ebx, %r13d
	movl	$12, %edi
	callq	malloc
	movq	%rax, %r15
	leaq	(,%r13,4), %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbp
	movl	$200, %edi
	callq	srand
	xorl	%ebx, %ebx
.LBB2_12:                               # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	15(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-16, %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r15,%rbx,4)
	incq	%rbx
	cmpq	$3, %rbx
	jne	.LBB2_12
# %bb.3:                                # %.preheader
	testq	%r13, %r13
	je	.LBB2_6
# %bb.4:                                # %.lr.ph.preheader
	xorl	%ebx, %ebx
.LBB2_5:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	15(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-16, %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbp,%rbx,4)
	incq	%rbx
	cmpq	%rbx, %r13
	jne	.LBB2_5
.LBB2_6:                                # %._crit_edge
	movabsq	$68719476752, %rbx              # imm = 0x1000000010
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%rbx, %r13
	movq	%rbp, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$d_Kernel, %edi
	movl	$3, %edx
	movq	%r15, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movq	16(%rsp), %rbx                  # 8-byte Reload
	leal	15(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	sarl	$4, %eax
	leal	15(%r14), %r15d
	testl	%r14d, %r14d
	cmovnsl	%r14d, %r15d
	sarl	$4, %r15d
	shlq	$32, %r15
	orq	%rax, %r15
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	8(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	%ebx, %edx
	movl	%r14d, %ecx
	callq	_Z32__device_stub__convolutionRowGPUPfS_ii
.LBB2_8:
	callq	hipDeviceSynchronize
	xorl	%r12d, %r12d
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%ebx, %edx
	movl	%r14d, %ecx
	callq	_Z32__device_stub__convolutionColGPUPfS_ii
.LBB2_10:
	callq	hipDeviceSynchronize
	jmp	.LBB2_14
.LBB2_13:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	xorl	%r12d, %r12d
	jmp	.LBB2_14
.LBB2_2:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movl	$-1, %r12d
.LBB2_14:
	movl	%r12d, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17convolutionRowGPUPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17convolutionColGPUPfS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$d_Kernel, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$28, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_Kernel,@object                # @d_Kernel
	.local	d_Kernel
	.comm	d_Kernel,28,16
	.type	_Z17convolutionRowGPUPfS_ii,@object # @_Z17convolutionRowGPUPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z17convolutionRowGPUPfS_ii
	.p2align	3, 0x0
_Z17convolutionRowGPUPfS_ii:
	.quad	_Z32__device_stub__convolutionRowGPUPfS_ii
	.size	_Z17convolutionRowGPUPfS_ii, 8

	.type	_Z17convolutionColGPUPfS_ii,@object # @_Z17convolutionColGPUPfS_ii
	.globl	_Z17convolutionColGPUPfS_ii
	.p2align	3, 0x0
_Z17convolutionColGPUPfS_ii:
	.quad	_Z32__device_stub__convolutionColGPUPfS_ii
	.size	_Z17convolutionColGPUPfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17convolutionRowGPUPfS_ii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17convolutionColGPUPfS_ii"
	.size	.L__unnamed_2, 28

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"d_Kernel"
	.size	.L__unnamed_3, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Error input Parameter "
	.size	.Lstr, 23

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Please Follow Format to Run Program: ./execute_file <dimX> <dimY> <dimK>"
	.size	.Lstr.1, 73

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Please input <dimX>, <dimY>, <dimK> "
	.size	.Lstr.2, 37

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"dimX and dimY are width and heights for input image and dimK is size for mask "
	.size	.Lstr.3, 79

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"Input Data"
	.size	.Lstr.4, 11

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"Please change KERNEKL_RADIUS values "
	.size	.Lstr.5, 37

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Keep dimK = KERNEKL_RADIUS "
	.size	.Lstr.6, 28

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__convolutionRowGPUPfS_ii
	.addrsig_sym _Z32__device_stub__convolutionColGPUPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_Kernel
	.addrsig_sym _Z17convolutionRowGPUPfS_ii
	.addrsig_sym _Z17convolutionColGPUPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17convolutionRowGPUPfS_ii ; -- Begin function _Z17convolutionRowGPUPfS_ii
	.globl	_Z17convolutionRowGPUPfS_ii
	.p2align	8
	.type	_Z17convolutionRowGPUPfS_ii,@function
_Z17convolutionRowGPUPfS_ii:            ; @_Z17convolutionRowGPUPfS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	s_bfe_i32 s7, s14, 0x180000
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s5, 0xffff
	s_lshr_b32 s5, s5, 16
	v_mad_u64_u32 v[0:1], null, s7, s4, v[2:3]
	v_mov_b32_e32 v3, 0
	s_bfe_i32 s7, s15, 0x180000
	v_mul_i32_i24_e32 v1, s6, v4
	s_mul_i32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_mul_i32 s7, s7, s5
	v_add_nc_u32_e32 v5, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v0, v1, s7
	v_cmp_gt_i32_e32 vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v5, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_co_u32 v5, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	global_load_b32 v5, v[5:6], off offset:12
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_mad_u32_u24 v2, v4, 22, v2
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_Kernel@rel32@lo+4
	s_addc_u32 s3, s3, d_Kernel@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v4, v2, s4, 2
	v_lshlrev_b32_e32 v2, 2, v2
	s_movk_i32 s4, 0xffe4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v4, s4, v2
	s_load_b32 s5, s[2:3], 0x0
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_add_i32 s4, s4, 4
	ds_load_b32 v4, v4 offset:28
	s_cmp_eq_u32 s4, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, s5, v4
	s_cbranch_scc0 .LBB0_3
; %bb.4:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17convolutionRowGPUPfS_ii
		.amdhsa_group_segment_fixed_size 1408
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17convolutionRowGPUPfS_ii, .Lfunc_end0-_Z17convolutionRowGPUPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1408 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z17convolutionColGPUPfS_ii ; -- Begin function _Z17convolutionColGPUPfS_ii
	.globl	_Z17convolutionColGPUPfS_ii
	.p2align	8
	.type	_Z17convolutionColGPUPfS_ii,@function
_Z17convolutionColGPUPfS_ii:            ; @_Z17convolutionColGPUPfS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s7, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	s_bfe_i32 s9, s15, 0x180000
	s_bfe_i32 s8, s14, 0x180000
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s6, s7, 16
	v_mad_i32_i24 v0, s4, v1, v3
	s_mul_i32 s9, s9, s6
	s_and_b32 s7, s7, 0xffff
	v_add3_u32 v4, v1, s9, 3
	s_mul_i32 s8, s8, s7
	s_mul_i32 s9, s9, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v0, s9, s8, v0
	v_cmp_gt_i32_e32 vcc_lo, s5, v4
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_bfe_i32 s4, s4, 0x180000
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s4, 3, v[0:1]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_lshl_u32 v5, v1, s6, 4
	v_lshlrev_b32_e32 v6, 2, v3
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_lshl_u32 v3, v5, v3, 2
	v_lshl_add_u32 v1, v1, 6, v6
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_Kernel@rel32@lo+4
	s_addc_u32 s5, s5, d_Kernel@rel32@hi+12
	s_add_u32 s4, s2, s4
	s_addc_u32 s5, s3, s5
	ds_load_b32 v3, v1
	s_load_b32 s4, s[4:5], 0x0
	v_add_nc_u32_e32 v1, 64, v1
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 28
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, s4, v3
	s_cbranch_scc0 .LBB1_3
; %bb.4:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17convolutionColGPUPfS_ii
		.amdhsa_group_segment_fixed_size 1408
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17convolutionColGPUPfS_ii, .Lfunc_end1-_Z17convolutionColGPUPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1408 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_Kernel                ; @d_Kernel
	.type	d_Kernel,@object
	.section	.bss,"aw",@nobits
	.globl	d_Kernel
	.p2align	4, 0x0
d_Kernel:
	.zero	28
	.size	d_Kernel, 28

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_Kernel
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1408
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17convolutionRowGPUPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17convolutionRowGPUPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1408
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17convolutionColGPUPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17convolutionColGPUPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
