// #include "LinearSolver.hh"
// #include "table.hh"

#include <vector>
#include <iostream>
#include <cmath> 

using namespace std; 

#define THREADS_PER_BLOCK 1024

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

__global__ void gpu(int * a, int * b, int * dot) {

	__shared__ int product[THREADS_PER_BLOCK]; 

	int tid = blockIdx.x * blockDim.x + threadIdx.x; 

	product[threadIdx.x] = a[tid] * b[tid]; 

	__syncthreads(); 

	if (threadIdx.x == 0) {

		int sum = 0; 

		for (int i=0; i<THREADS_PER_BLOCK; i++) {

			sum += product[i]; 

		}

		atomicAdd(dot, sum); 

	}

}

int main(int argc, char * argv[]) {

	int N = atoi(argv[1]); 

	// int threadsPerBlock = pow(2, 2); 
	// threadsPerBlock = min(N, threadsPerBlock); 
	// int nBlock = max(1, (N + threadsPerBlock - 1)/threadsPerBlock);  

	// cout << "threads/block = " << threadsPerBlock << " number of blocks = " << nBlock << endl; 

	int *a, *b; 
	int *d_a, *d_b; 
	int dot, *d_dot; 

	size_t size = N*sizeof(int); 

	cudaMalloc(&d_a, size); 
	cudaMalloc(&d_b, size); 
	cudaMalloc(&d_dot, sizeof(int)); 

	a = new int[N]; 
	b = new int[N]; 

	dot = 0; 

	for (int i=0; i<N; i++) {

		a[i] = 1; 
		b[i] = 1; 

	}

	cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice); 
	cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
	cudaMemcpy(d_dot, &dot, sizeof(int), cudaMemcpyHostToDevice); 

	gpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_dot);

	cudaMemcpy(&dot, d_dot, sizeof(int), cudaMemcpyDeviceToHost);  

	cudaFree(d_a); cudaFree(d_b); cudaFree(d_dot);
	delete a, b;  

}

// int main() {

// 	int tend = 1; 
// 	int Nt = 10; 
// 	int y0 = 1; 

// 	int dt = tend/Nt; 

// 	auto f = [] (int y) {return -1*pow(y, 3); }; 

// 	vector<int> t = linspace(0, tend, Nt+1); 

// 	vector<int> y(Nt+1); 
// 	y[0] = y0; 

// 	vector<int> y_ex(Nt+1); 
// 	y_ex[0] = y0; 

// 	int tol = 1e-6; 
// 	int maxiter = 100; 

// 	for (int i=1; i<=Nt; i++) {

// 		int yi = y[i-1];
// 		int ylag = yi; 

// 		for (int j=0; j<maxiter; j++) {

// 			y[i] = yi + dt * f(.5*(ylag + yi)); 

// 			if (abs(ylag - y[i]) < tol) break; 

// 			if (j == maxiter - 1) cout << "max iterations reached" << endl; 

// 			ylag = y[i]; 

// 		} 

// 		y_ex[i] = y0*pow(1/(1 + 2*pow(y0,2)*t[i]), .5); 

// 	}

// 	Table table("out"); 

// 	table.addColumn(t); 
// 	table.addColumn(y); 
// 	table.addColumn(y_ex); 

// 	table.write(); 

// }
	.file	"tmpxft_003155a4_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4002:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4002:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z3gpuPiS_S_PiS_S_
	.type	_Z26__device_stub__Z3gpuPiS_S_PiS_S_, @function
_Z26__device_stub__Z3gpuPiS_S_PiS_S_:
.LFB4024:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z3gpuPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4024:
	.size	_Z26__device_stub__Z3gpuPiS_S_PiS_S_, .-_Z26__device_stub__Z3gpuPiS_S_PiS_S_
	.globl	_Z3gpuPiS_S_
	.type	_Z3gpuPiS_S_, @function
_Z3gpuPiS_S_:
.LFB4025:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z3gpuPiS_S_PiS_S_
	.cfi_endproc
.LFE4025:
	.size	_Z3gpuPiS_S_, .-_Z3gpuPiS_S_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3999:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	leaq	8(%rsp), %rdi
	movslq	%eax, %r12
	leaq	0(,%r12,4), %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movabsq	$2305843009213693950, %rax
	cmpq	%r12, %rax
	jb	.L9
	movq	%rbp, %rdi
	movq	%r12, %rbx
	call	_Znam@PLT
	movq	%rbp, %rdi
	movq	%rax, %r12
	call	_Znam@PLT
	xorl	%edx, %edx
	movq	%rax, %r13
	xorl	%eax, %eax
	movl	%eax, 4(%rsp)
	jmp	.L10
.L9:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L16
	call	__cxa_throw_bad_array_new_length@PLT
.L10:
	cmpl	%edx, %ebx
	jle	.L17
	movl	$1, (%r12,%rdx,4)
	movl	$1, 0(%r13,%rdx,4)
	incq	%rdx
	jmp	.L10
.L17:
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%r12, %rsi
	sarl	$10, %ebx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	leaq	4(%rsp), %rbp
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	%ebx, 32(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$4194305, %edx
	movl	$1, %ecx
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	salq	$10, %rdx
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z26__device_stub__Z3gpuPiS_S_PiS_S_
.L13:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	$4, %esi
	movq	%r12, %rdi
	call	_ZdlPvm@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
.L16:
	call	__stack_chk_fail@PLT
.L14:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3999:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z3gpuPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3gpuPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4027:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// #include "LinearSolver.hh"
// #include "table.hh"


#include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <cmath> 

using namespace std; 

#define THREADS_PER_BLOCK 1024

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

__global__ void gpu(int * a, int * b, int * dot) {

	__shared__ int product[THREADS_PER_BLOCK]; 

	int tid = blockIdx.x * blockDim.x + threadIdx.x; 

	product[threadIdx.x] = a[tid] * b[tid]; 

	__syncthreads(); 

	if (threadIdx.x == 0) {

		int sum = 0; 

		for (int i=0; i<THREADS_PER_BLOCK; i++) {

			sum += product[i]; 

		}

		atomicAdd(dot, sum); 

	}

}

int main(int argc, char * argv[]) {

	int N = atoi(argv[1]); 

	// int threadsPerBlock = pow(2, 2); 
	// threadsPerBlock = min(N, threadsPerBlock); 
	// int nBlock = max(1, (N + threadsPerBlock - 1)/threadsPerBlock);  

	// cout << "threads/block = " << threadsPerBlock << " number of blocks = " << nBlock << endl; 

	int *a, *b; 
	int *d_a, *d_b; 
	int dot, *d_dot; 

	size_t size = N*sizeof(int); 

	hipMalloc(&d_a, size); 
	hipMalloc(&d_b, size); 
	hipMalloc(&d_dot, sizeof(int)); 

	a = new int[N]; 
	b = new int[N]; 

	dot = 0; 

	for (int i=0; i<N; i++) {

		a[i] = 1; 
		b[i] = 1; 

	}

	hipMemcpy(d_a, a, size, hipMemcpyHostToDevice); 
	hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
	hipMemcpy(d_dot, &dot, sizeof(int), hipMemcpyHostToDevice); 

	gpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_dot);

	hipMemcpy(&dot, d_dot, sizeof(int), hipMemcpyDeviceToHost);  

	hipFree(d_a); hipFree(d_b); hipFree(d_dot);
	delete a, b;  

}

// int main() {

// 	int tend = 1; 
// 	int Nt = 10; 
// 	int y0 = 1; 

// 	int dt = tend/Nt; 

// 	auto f = [] (int y) {return -1*pow(y, 3); }; 

// 	vector<int> t = linspace(0, tend, Nt+1); 

// 	vector<int> y(Nt+1); 
// 	y[0] = y0; 

// 	vector<int> y_ex(Nt+1); 
// 	y_ex[0] = y0; 

// 	int tol = 1e-6; 
// 	int maxiter = 100; 

// 	for (int i=1; i<=Nt; i++) {

// 		int yi = y[i-1];
// 		int ylag = yi; 

// 		for (int j=0; j<maxiter; j++) {

// 			y[i] = yi + dt * f(.5*(ylag + yi)); 

// 			if (abs(ylag - y[i]) < tol) break; 

// 			if (j == maxiter - 1) cout << "max iterations reached" << endl; 

// 			ylag = y[i]; 

// 		} 

// 		y_ex[i] = y0*pow(1/(1 + 2*pow(y0,2)*t[i]), .5); 

// 	}

// 	Table table("out"); 

// 	table.addColumn(t); 
// 	table.addColumn(y); 
// 	table.addColumn(y_ex); 

// 	table.write(); 

// }
	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__gpuPiS_S_    # -- Begin function _Z18__device_stub__gpuPiS_S_
	.type	_Z18__device_stub__gpuPiS_S_,@function
_Z18__device_stub__gpuPiS_S_:           # @_Z18__device_stub__gpuPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3gpuPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__gpuPiS_S_, .Lfunc_end0-_Z18__device_stub__gpuPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r14d
	movslq	%eax, %r13
	leaq	(,%r13,4), %r15
	leaq	24(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%r13d, %r13d
	movq	$-1, %r12
	cmovnsq	%r15, %r12
	movq	%r12, %rdi
	callq	_Znam
	movq	%rax, %rbx
	movq	%r12, %rdi
	callq	_Znam
	movq	%rax, %r12
	movl	$0, 4(%rsp)
	testl	%r13d, %r13d
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%r14d, %eax
	xorl	%ecx, %ecx
	movl	$1, %edx
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%edx, (%rbx,%rcx,4)
	movl	%edx, (%r12,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movq	24(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	leaq	4(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	1023(%r14), %edi
	testl	%r14d, %r14d
	cmovnsl	%r14d, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z18__device_stub__gpuPiS_S_
.LBB1_5:
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3gpuPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3gpuPiS_S_,@object            # @_Z3gpuPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z3gpuPiS_S_
	.p2align	3, 0x0
_Z3gpuPiS_S_:
	.quad	_Z18__device_stub__gpuPiS_S_
	.size	_Z3gpuPiS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z3gpuPiS_S_"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__gpuPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3gpuPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3gpuPiS_S_            ; -- Begin function _Z3gpuPiS_S_
	.globl	_Z3gpuPiS_S_
	.p2align	8
	.type	_Z3gpuPiS_S_,@function
_Z3gpuPiS_S_:                           ; @_Z3gpuPiS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	v_lshlrev_b32_e32 v2, 2, v0
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v1, v1, v3
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.preheader.preheader
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
.LBB0_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s2
	s_add_i32 s2, s2, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s2, 0x1000
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v1, s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_bcnt1_i32_b32 s2, s2
	v_mov_b32_e32 v1, 0
	v_mul_lo_u32 v0, v0, s2
	global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3gpuPiS_S_
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3gpuPiS_S_, .Lfunc_end0-_Z3gpuPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3gpuPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3gpuPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
