#include <vector>

using Float = float;

__global__ void gpu_mul(Float * val, Float * wag, Float * inn, size_t N, size_t M)
{
	auto val_ind = blockIdx.x + blockIdx.y * N;
	auto wag_ind = blockIdx.x;
	auto inn_ind = blockIdx.y;
	
	if (val_ind < N*N and wag_ind < N and inn_ind < N) 
	{
		val[blockIdx.x + blockIdx.y * N] = wag[blockIdx.x] * inn[blockIdx.y];
	}
}


void cpu_mul(Float * val, Float * wag, Float * inn, size_t N, size_t M)
{
	Float * row_wag = wag;
	Float * row_val = val;
	for (size_t j = 0; j < M; ++j)
	{				
		for (size_t i = 0; i < N; i += 4)
		{
			row_val[i] = row_wag[i] * inn[i];	
			row_val[i+1] = row_wag[i+1] * inn[i+1];	
			row_val[i+2] = row_wag[i+2] * inn[i+2];	
			row_val[i+3] = row_wag[i+3] * inn[i+3];					
		}
		row_wag += N;
		row_val += N;
	}
}		
	

int main() 
{
	size_t N = 10000;
	size_t M = 10000;
	
	
	std::vector<Float> v;
	v.resize(N + N*M + N*M);
	Float * p = &v[0];

	Float * inn = p;
	Float * wag = p + N;
	Float * val = p+N+M*N;
		
	for (size_t i = 0; i < v.size(); ++i)
	{
		//v[i] = (int8_t)randm::uniform_f(-1, +1);
	}	

	// cpu
	if (0) {
		cpu_mul(val, wag, inn, N, M);			
	}

	// gpu
	if (1) {
	
		Float * gp;
		cudaMalloc(&gp, N + N*M + N*M);
		
		Float * gpu_inn = gp;
		Float * gpu_wag = gp + N;
		Float * gpu_val = gp+N+M*N;
		
		cudaMemcpy(gp, p, v.size(), cudaMemcpyHostToDevice);
		
		dim3 threadsPerBlock(N,M,1);
		gpu_mul<<<1, threadsPerBlock>>>(gpu_val, gpu_wag, gpu_inn, N, M);
	
		
		
		cudaMemcpy(p, gp, v.size(), cudaMemcpyDeviceToHost);

		cudaFree(gp);
		
	}
	
	

	return 0;
}

	.file	"tmpxft_002b18fe_00000000-6_gmain.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2892:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2892:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7cpu_mulPfS_S_mm
	.type	_Z7cpu_mulPfS_S_mm, @function
_Z7cpu_mulPfS_S_mm:
.LFB2877:
	.cfi_startproc
	endbr64
	leaq	0(,%rcx,4), %r10
	xorl	%r9d, %r9d
.L3:
	cmpq	%r8, %r9
	je	.L8
	xorl	%eax, %eax
.L5:
	cmpq	%rcx, %rax
	jnb	.L9
	movss	(%rsi,%rax,4), %xmm0
	mulss	(%rdx,%rax,4), %xmm0
	movss	%xmm0, (%rdi,%rax,4)
	movss	4(%rsi,%rax,4), %xmm0
	mulss	4(%rdx,%rax,4), %xmm0
	movss	%xmm0, 4(%rdi,%rax,4)
	movss	8(%rsi,%rax,4), %xmm0
	mulss	8(%rdx,%rax,4), %xmm0
	movss	%xmm0, 8(%rdi,%rax,4)
	movss	12(%rsi,%rax,4), %xmm0
	mulss	12(%rdx,%rax,4), %xmm0
	movss	%xmm0, 12(%rdi,%rax,4)
	addq	$4, %rax
	jmp	.L5
.L9:
	addq	%r10, %rsi
	addq	%r10, %rdi
	incq	%r9
	jmp	.L3
.L8:
	ret
	.cfi_endproc
.LFE2877:
	.size	_Z7cpu_mulPfS_S_mm, .-_Z7cpu_mulPfS_S_mm
	.globl	_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm
	.type	_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm, @function
_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm:
.LFB2914:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7gpu_mulPfS_S_mm(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L10:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2914:
	.size	_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm, .-_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm
	.globl	_Z7gpu_mulPfS_S_mm
	.type	_Z7gpu_mulPfS_S_mm, @function
_Z7gpu_mulPfS_S_mm:
.LFB2915:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm
	.cfi_endproc
.LFE2915:
	.size	_Z7gpu_mulPfS_S_mm, .-_Z7gpu_mulPfS_S_mm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7gpu_mulPfS_S_mm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2917:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7gpu_mulPfS_S_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2917:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZNSt12_Vector_baseIfSaIfEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIfSaIfEED5Ev,comdat
	.align 2
	.weak	_ZNSt12_Vector_baseIfSaIfEED2Ev
	.type	_ZNSt12_Vector_baseIfSaIfEED2Ev, @function
_ZNSt12_Vector_baseIfSaIfEED2Ev:
.LFB2972:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L17
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L17:
	ret
	.cfi_endproc
.LFE2972:
	.size	_ZNSt12_Vector_baseIfSaIfEED2Ev, .-_ZNSt12_Vector_baseIfSaIfEED2Ev
	.weak	_ZNSt12_Vector_baseIfSaIfEED1Ev
	.set	_ZNSt12_Vector_baseIfSaIfEED1Ev,_ZNSt12_Vector_baseIfSaIfEED2Ev
	.section	.text._ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_,"axG",@progbits,_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_,comdat
	.weak	_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_
	.type	_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_, @function
_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_:
.LFB3089:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	testq	%rsi, %rsi
	je	.L19
	movl	$0x00000000, (%rdi)
	leaq	4(%rdi), %rax
	decq	%rsi
	je	.L19
	leaq	(%rax,%rsi,4), %rdx
	movq	%rax, %rcx
.L21:
	cmpq	%rcx, %rdx
	je	.L28
	movl	$0x00000000, (%rcx)
	addq	$4, %rcx
	jmp	.L21
.L28:
	subq	%rdi, %rdx
	leaq	-4(%rax,%rdx), %rax
.L19:
	ret
	.cfi_endproc
.LFE3089:
	.size	_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_, .-_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB2878:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA2878
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$800040000, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	leaq	32(%rsp), %r12
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
	movq	%rax, 48(%rsp)
.LEHB0:
	call	_Znwm@PLT
	movq	%rax, %rbx
	movl	$200010000, %esi
	movq	%rax, %rdi
	call	_ZNSt27__uninitialized_default_n_1ILb1EE18__uninit_default_nIPfmEET_S3_T0_
	leaq	800040000(%rbx), %rax
	movq	%rsp, %rdi
	movl	$200010000, %esi
	movq	%rbx, 32(%rsp)
	movq	%rax, 40(%rsp)
	movq	%rax, 48(%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rbp
	movl	$1, %ecx
	movl	$200010000, %edx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$42949672970000, %rdx
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L30
.L32:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$200010000, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	jmp	.L40
.L30:
	leaq	40000(%rbp), %rsi
	leaq	400040000(%rbp), %rdi
	movl	$10000, %ecx
	movq	%rbp, %rdx
	movl	$10000, %r8d
	call	_Z32__device_stub__Z7gpu_mulPfS_S_mmPfS_S_mm
	jmp	.L32
.L40:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
.LEHE0:
	movq	%r12, %rdi
	call	_ZNSt12_Vector_baseIfSaIfEED2Ev
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	jmp	.L38
.L36:
	endbr64
	movq	%rax, %rbx
.L33:
	movq	%r12, %rdi
	call	_ZNSt12_Vector_baseIfSaIfEED2Ev
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L38
	movq	%rbx, %rdi
.LEHB1:
	call	_Unwind_Resume@PLT
.LEHE1:
.L38:
	call	__stack_chk_fail@PLT
.L35:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2878:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA2878:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE2878-.LLSDACSB2878
.LLSDACSB2878:
	.uleb128 .LEHB0-.LFB2878
	.uleb128 .LEHE0-.LEHB0
	.uleb128 .L36-.LFB2878
	.uleb128 0
	.uleb128 .LEHB1-.LFB2878
	.uleb128 .LEHE1-.LEHB1
	.uleb128 0
	.uleb128 0
.LLSDACSE2878:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <vector>

using Float = float;

__global__ void gpu_mul(Float * val, Float * wag, Float * inn, size_t N, size_t M)
{
	auto val_ind = blockIdx.x + blockIdx.y * N;
	auto wag_ind = blockIdx.x;
	auto inn_ind = blockIdx.y;
	
	if (val_ind < N*N and wag_ind < N and inn_ind < N) 
	{
		val[blockIdx.x + blockIdx.y * N] = wag[blockIdx.x] * inn[blockIdx.y];
	}
}


void cpu_mul(Float * val, Float * wag, Float * inn, size_t N, size_t M)
{
	Float * row_wag = wag;
	Float * row_val = val;
	for (size_t j = 0; j < M; ++j)
	{				
		for (size_t i = 0; i < N; i += 4)
		{
			row_val[i] = row_wag[i] * inn[i];	
			row_val[i+1] = row_wag[i+1] * inn[i+1];	
			row_val[i+2] = row_wag[i+2] * inn[i+2];	
			row_val[i+3] = row_wag[i+3] * inn[i+3];					
		}
		row_wag += N;
		row_val += N;
	}
}		
	

int main() 
{
	size_t N = 10000;
	size_t M = 10000;
	
	
	std::vector<Float> v;
	v.resize(N + N*M + N*M);
	Float * p = &v[0];

	Float * inn = p;
	Float * wag = p + N;
	Float * val = p+N+M*N;
		
	for (size_t i = 0; i < v.size(); ++i)
	{
		//v[i] = (int8_t)randm::uniform_f(-1, +1);
	}	

	// cpu
	if (0) {
		cpu_mul(val, wag, inn, N, M);			
	}

	// gpu
	if (1) {
	
		Float * gp;
		hipMalloc(&gp, N + N*M + N*M);
		
		Float * gpu_inn = gp;
		Float * gpu_wag = gp + N;
		Float * gpu_val = gp+N+M*N;
		
		hipMemcpy(gp, p, v.size(), hipMemcpyHostToDevice);
		
		dim3 threadsPerBlock(N,M,1);
		gpu_mul<<<1, threadsPerBlock>>>(gpu_val, gpu_wag, gpu_inn, N, M);
	
		
		
		hipMemcpy(p, gp, v.size(), hipMemcpyDeviceToHost);

		hipFree(gp);
		
	}
	
	

	return 0;
}

	.text
	.file	"gmain.hip"
	.globl	_Z22__device_stub__gpu_mulPfS_S_mm # -- Begin function _Z22__device_stub__gpu_mulPfS_S_mm
	.type	_Z22__device_stub__gpu_mulPfS_S_mm,@function
_Z22__device_stub__gpu_mulPfS_S_mm:     # @_Z22__device_stub__gpu_mulPfS_S_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7gpu_mulPfS_S_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__gpu_mulPfS_S_mm, .Lfunc_end0-_Z22__device_stub__gpu_mulPfS_S_mm
	.cfi_endproc
                                        # -- End function
	.globl	_Z7cpu_mulPfS_S_mm              # -- Begin function _Z7cpu_mulPfS_S_mm
	.type	_Z7cpu_mulPfS_S_mm,@function
_Z7cpu_mulPfS_S_mm:                     # @_Z7cpu_mulPfS_S_mm
	.cfi_startproc
# %bb.0:
	testq	%r8, %r8
	je	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	leaq	(,%rcx,4), %rax
	xorl	%r9d, %r9d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testq	%rcx, %rcx
	je	.LBB1_5
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_2 Depth=1
	xorl	%r10d, %r10d
.LBB1_4:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rsi,%r10,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	mulss	(%rdx,%r10,4), %xmm0
	movss	%xmm0, (%rdi,%r10,4)
	movss	4(%rsi,%r10,4), %xmm0           # xmm0 = mem[0],zero,zero,zero
	mulss	4(%rdx,%r10,4), %xmm0
	movss	%xmm0, 4(%rdi,%r10,4)
	movss	8(%rsi,%r10,4), %xmm0           # xmm0 = mem[0],zero,zero,zero
	mulss	8(%rdx,%r10,4), %xmm0
	movss	%xmm0, 8(%rdi,%r10,4)
	movss	12(%rsi,%r10,4), %xmm0          # xmm0 = mem[0],zero,zero,zero
	mulss	12(%rdx,%r10,4), %xmm0
	movss	%xmm0, 12(%rdi,%r10,4)
	addq	$4, %r10
	cmpq	%rcx, %r10
	jb	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r9
	addq	%rax, %rdi
	addq	%rax, %rsi
	cmpq	%r8, %r9
	jne	.LBB1_2
.LBB1_6:                                # %._crit_edge43
	retq
.Lfunc_end1:
	.size	_Z7cpu_mulPfS_S_mm, .Lfunc_end1-_Z7cpu_mulPfS_S_mm
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	xorps	%xmm0, %xmm0
	leaq	16(%rsp), %rdi
	movaps	%xmm0, (%rdi)
	movq	$0, 16(%rdi)
.Ltmp0:
	movl	$200010000, %esi                # imm = 0xBEBE910
	callq	_ZNSt6vectorIfSaIfEE6resizeEm
.Ltmp1:
# %bb.1:
	movq	16(%rsp), %rbx
.Ltmp3:
	leaq	8(%rsp), %rdi
	movl	$200010000, %esi                # imm = 0xBEBE910
	callq	hipMalloc
.Ltmp4:
# %bb.2:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
	movq	8(%rsp), %r14
	movq	24(%rsp), %rdx
	subq	16(%rsp), %rdx
	sarq	$2, %rdx
.Ltmp6:
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp7:
# %bb.3:
.Ltmp9:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$42949672970000, %rdx           # imm = 0x271000002710
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp10:
# %bb.4:
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
.Ltmp11:
	leaq	40000(%r14), %rsi
	leaq	400040000(%r14), %rdi
	movl	$10000, %ecx                    # imm = 0x2710
	movl	$10000, %r8d                    # imm = 0x2710
	movq	%r14, %rdx
	callq	_Z22__device_stub__gpu_mulPfS_S_mm
.Ltmp12:
.LBB2_6:
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	subq	16(%rsp), %rdx
	sarq	$2, %rdx
.Ltmp13:
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp14:
# %bb.7:
	movq	8(%rsp), %rdi
.Ltmp15:
	callq	hipFree
.Ltmp16:
# %bb.8:
	movq	16(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB2_10
# %bb.9:
	callq	_ZdlPv
.LBB2_10:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB2_11:
	.cfi_def_cfa_offset 64
.Ltmp8:
	jmp	.LBB2_14
.LBB2_13:
.Ltmp5:
	jmp	.LBB2_14
.LBB2_17:
.Ltmp2:
	jmp	.LBB2_14
.LBB2_12:
.Ltmp17:
.LBB2_14:
	movq	%rax, %rbx
	movq	16(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB2_16
# %bb.15:
	callq	_ZdlPv
.LBB2_16:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit46
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table2:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 1 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp16-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp16
	.uleb128 .Ltmp17-.Lfunc_begin0          #     jumps to .Ltmp17
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp16-.Lfunc_begin0          # >> Call Site 5 <<
	.uleb128 .Lfunc_end2-.Ltmp16            #   Call between .Ltmp16 and .Lfunc_end2
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.section	.text._ZNSt6vectorIfSaIfEE6resizeEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE6resizeEm,comdat
	.weak	_ZNSt6vectorIfSaIfEE6resizeEm   # -- Begin function _ZNSt6vectorIfSaIfEE6resizeEm
	.p2align	1, 0x90
	.type	_ZNSt6vectorIfSaIfEE6resizeEm,@function
_ZNSt6vectorIfSaIfEE6resizeEm:          # @_ZNSt6vectorIfSaIfEE6resizeEm
	.cfi_startproc
# %bb.0:
	movq	(%rdi), %rdx
	movq	8(%rdi), %rcx
	movq	%rcx, %r8
	subq	%rdx, %r8
	sarq	$2, %r8
	movq	%rsi, %rax
	subq	%r8, %rax
	jbe	.LBB3_1
# %bb.5:
	movq	%rax, %rsi
	jmp	_ZNSt6vectorIfSaIfEE17_M_default_appendEm # TAILCALL
.LBB3_1:
	jae	.LBB3_4
# %bb.2:
	leaq	(%rdx,%rsi,4), %rax
	cmpq	%rax, %rcx
	je	.LBB3_4
# %bb.3:
	movq	%rax, 8(%rdi)
.LBB3_4:                                # %_ZNSt6vectorIfSaIfEE15_M_erase_at_endEPf.exit
	retq
.Lfunc_end3:
	.size	_ZNSt6vectorIfSaIfEE6resizeEm, .Lfunc_end3-_ZNSt6vectorIfSaIfEE6resizeEm
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt6vectorIfSaIfEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_default_appendEm,comdat
	.weak	_ZNSt6vectorIfSaIfEE17_M_default_appendEm # -- Begin function _ZNSt6vectorIfSaIfEE17_M_default_appendEm
	.p2align	1, 0x90
	.type	_ZNSt6vectorIfSaIfEE17_M_default_appendEm,@function
_ZNSt6vectorIfSaIfEE17_M_default_appendEm: # @_ZNSt6vectorIfSaIfEE17_M_default_appendEm
	.cfi_startproc
# %bb.0:
	testq	%rsi, %rsi
	je	.LBB4_16
# %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	8(%rdi), %r15
	movq	16(%rdi), %rax
	subq	%r15, %rax
	sarq	$2, %rax
	cmpq	%rsi, %rax
	jae	.LBB4_2
# %bb.5:
	movq	(%rbx), %r12
	subq	%r12, %r15
	movq	%r15, %r13
	sarq	$2, %r13
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc
	testq	%rax, %rax
	movq	%rax, (%rsp)                    # 8-byte Spill
	je	.LBB4_6
# %bb.7:
	movq	%rbx, %rdi
	movq	%rax, %rsi
	xorl	%edx, %edx
	callq	_ZNSt15__new_allocatorIfE8allocateEmPKv
	movq	%rax, %rbp
	jmp	.LBB4_8
.LBB4_2:
	movl	$0, (%r15)
	leaq	4(%r15), %rdi
	cmpq	$1, %r14
	je	.LBB4_4
# %bb.3:                                # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i
	leaq	-4(,%r14,4), %rdx
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	(%r15,%r14,4), %rdi
.LBB4_4:                                # %_ZSt27__uninitialized_default_n_aIPfmfET_S1_T0_RSaIT1_E.exit
	movq	%rdi, 8(%rbx)
	jmp	.LBB4_15
.LBB4_6:
	xorl	%ebp, %ebp
.LBB4_8:
	leaq	(,%r13,4), %r13
	addq	%rbp, %r13
	movl	$0, (%r13)
	cmpq	$1, %r14
	je	.LBB4_10
# %bb.9:                                # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i30
	leaq	4(%r13), %rdi
	leaq	-4(,%r14,4), %rdx
	xorl	%esi, %esi
	callq	memset@PLT
.LBB4_10:                               # %_ZSt27__uninitialized_default_n_aIPfmfET_S1_T0_RSaIT1_E.exit32
	testq	%r15, %r15
	jle	.LBB4_12
# %bb.11:
	movq	%rbp, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	memmove@PLT
.LBB4_12:                               # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit
	testq	%r12, %r12
	je	.LBB4_14
# %bb.13:
	movq	%r12, %rdi
	callq	_ZdlPv
.LBB4_14:                               # %_ZNSt12_Vector_baseIfSaIfEE13_M_deallocateEPfm.exit35
	movq	%rbp, (%rbx)
	leaq	(,%r14,4), %rax
	addq	%r13, %rax
	movq	%rax, 8(%rbx)
	movq	(%rsp), %rax                    # 8-byte Reload
	leaq	(,%rax,4), %rax
	addq	%rbp, %rax
	movq	%rax, 16(%rbx)
.LBB4_15:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB4_16:
	retq
.Lfunc_end4:
	.size	_ZNSt6vectorIfSaIfEE17_M_default_appendEm, .Lfunc_end4-_ZNSt6vectorIfSaIfEE17_M_default_appendEm
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc,"axG",@progbits,_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc,comdat
	.weak	_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc # -- Begin function _ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc
	.p2align	1, 0x90
	.type	_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc,@function
_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc: # @_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc
	.cfi_startproc
# %bb.0:
	movabsq	$2305843009213693951, %rcx      # imm = 0x1FFFFFFFFFFFFFFF
	movq	8(%rdi), %r8
	subq	(%rdi), %r8
	sarq	$2, %r8
	movq	%rcx, %rax
	subq	%r8, %rax
	cmpq	%rsi, %rax
	jb	.LBB5_2
# %bb.1:
	cmpq	%rsi, %r8
	cmovaq	%r8, %rsi
	leaq	(%rsi,%r8), %rax
	cmpq	%rcx, %rax
	cmovaeq	%rcx, %rax
	addq	%r8, %rsi
	cmovbq	%rcx, %rax
	retq
.LBB5_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdx, %rdi
	callq	_ZSt20__throw_length_errorPKc
.Lfunc_end5:
	.size	_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc, .Lfunc_end5-_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt15__new_allocatorIfE8allocateEmPKv,"axG",@progbits,_ZNSt15__new_allocatorIfE8allocateEmPKv,comdat
	.weak	_ZNSt15__new_allocatorIfE8allocateEmPKv # -- Begin function _ZNSt15__new_allocatorIfE8allocateEmPKv
	.p2align	1, 0x90
	.type	_ZNSt15__new_allocatorIfE8allocateEmPKv,@function
_ZNSt15__new_allocatorIfE8allocateEmPKv: # @_ZNSt15__new_allocatorIfE8allocateEmPKv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rsi, %rax
	shrq	$61, %rax
	jne	.LBB6_1
# %bb.3:
	shlq	$2, %rsi
	movq	%rsi, %rdi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	_Znwm                           # TAILCALL
.LBB6_1:
	.cfi_def_cfa_offset 16
	shrq	$62, %rsi
	je	.LBB6_2
# %bb.4:
	callq	_ZSt28__throw_bad_array_new_lengthv
.LBB6_2:
	callq	_ZSt17__throw_bad_allocv
.Lfunc_end6:
	.size	_ZNSt15__new_allocatorIfE8allocateEmPKv, .Lfunc_end6-_ZNSt15__new_allocatorIfE8allocateEmPKv
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7gpu_mulPfS_S_mm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7gpu_mulPfS_S_mm,@object      # @_Z7gpu_mulPfS_S_mm
	.section	.rodata,"a",@progbits
	.globl	_Z7gpu_mulPfS_S_mm
	.p2align	3, 0x0
_Z7gpu_mulPfS_S_mm:
	.quad	_Z22__device_stub__gpu_mulPfS_S_mm
	.size	_Z7gpu_mulPfS_S_mm, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"vector::_M_default_append"
	.size	.L.str, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7gpu_mulPfS_S_mm"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__gpu_mulPfS_S_mm
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z7gpu_mulPfS_S_mm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7gpu_mulPfS_S_mm      ; -- Begin function _Z7gpu_mulPfS_S_mm
	.globl	_Z7gpu_mulPfS_S_mm
	.p2align	8
	.type	_Z7gpu_mulPfS_S_mm,@function
_Z7gpu_mulPfS_S_mm:                     ; @_Z7gpu_mulPfS_S_mm
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	s_mov_b32 s8, s15
	s_mov_b32 s15, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s9, s8, s7
	s_mul_hi_u32 s11, s8, s6
	s_mul_i32 s10, s8, s6
	s_mul_i32 s17, s6, s7
	s_mul_hi_u32 s16, s6, s6
	s_add_i32 s11, s11, s9
	s_add_u32 s12, s10, s14
	s_addc_u32 s13, s11, 0
	s_add_i32 s9, s16, s17
	s_mul_i32 s16, s6, s6
	s_add_i32 s17, s9, s17
	s_mov_b32 s9, s15
	v_cmp_ge_u64_e64 s12, s[12:13], s[16:17]
	v_cmp_ge_u64_e64 s13, s[14:15], s[6:7]
	v_cmp_ge_u64_e64 s6, s[8:9], s[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s7, s13, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s6, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_2
; %bb.1:
	s_lshl_b64 s[6:7], s[10:11], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s6, s0, s6
	s_addc_u32 s7, s1, s7
	s_lshl_b64 s[0:1], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s6, s6, s0
	s_addc_u32 s7, s7, s1
	s_lshl_b64 s[8:9], s[8:9], 2
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_load_b32 s0, s[0:1], 0x0
	s_load_b32 s1, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v1, s0, s1
	global_store_b32 v0, v1, s[6:7]
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7gpu_mulPfS_S_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7gpu_mulPfS_S_mm, .Lfunc_end0-_Z7gpu_mulPfS_S_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 220
; NumSgprs: 20
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7gpu_mulPfS_S_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z7gpu_mulPfS_S_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
