#include <stdio.h> 

///
/// MM2chainkernel00.cu
/// By Luke Burford 
/// Created: 1 Nov 2018

#define B 32 // threads per block 
#define C 60 // matracies proccessed per block

__global__ void multiply(const float* A, float* tempoMult){ 
    int i; 
    
    float MxM00 = 0; 
    float MxM01 = 0; 
    float MxM10 = 0; 
    float MxM11 = 0; 
    float TH00 = 0; 
    float TH01 = 0; 
    float TH10 = 0; 
    float TH11 = 0; 
    
    __shared__ float SharedAMat[(B*C*4)]; 
    
    #pragma unroll 
    for( i = 0; i<C*4; ++i){ 
        SharedAMat[threadIdx.x * C * 4 + i] = A[threadIdx.x * C * 4 + (blockIdx.x * 4 * C * B)+  i]; 
    } 
    
    __syncthreads(); 
    
    
    TH00 = SharedAMat[threadIdx.x*4*C+0]; 
    TH01 = SharedAMat[threadIdx.x*4*C+1]; 
    TH10 = SharedAMat[threadIdx.x*4*C+2]; 
    TH11 = SharedAMat[threadIdx.x*4*C+3]; 
    
    #pragma unroll 
    for (i = 4 + (threadIdx.x * 4 * C) ; i < C * 4 +  (threadIdx.x * 4 * C); i+=4){ 
        MxM00 = (TH00 * SharedAMat[i])   + (TH01 * SharedAMat[i+2]); 
        MxM01 = (TH00 * SharedAMat[i+1]) + (TH01 * SharedAMat[i+3]); 
        MxM10 = (TH10 * SharedAMat[i])   + (TH11 * SharedAMat[i+2]); 
        MxM11 = (TH10 * SharedAMat[i+1]) + (TH11 * SharedAMat[i+3]); 
        TH00 = MxM00; 
        TH01 = MxM01; 
        TH10 = MxM10; 
        TH11 = MxM11; 
    } 
    
    SharedAMat[threadIdx.x * 4 * C  + 0] = TH00; 
    SharedAMat[threadIdx.x * 4 * C  + 1] = TH01; 
    SharedAMat[threadIdx.x * 4 * C  + 2] = TH10; 
    SharedAMat[threadIdx.x * 4 * C  + 3] = TH11; 
    
    __syncthreads(); 
    
    if (threadIdx.x == 0){ 
        #pragma unroll 
        for (i = C *  4; i < B * 4 * C; i+=C * 4){ 
            MxM00 = (TH00 * SharedAMat[i])   + (TH01 * SharedAMat[i+2]); 
            MxM01 = (TH00 * SharedAMat[i+1]) + (TH01 * SharedAMat[i+3]); 
            MxM10 = (TH10 * SharedAMat[i])   + (TH11 * SharedAMat[i+2]); 
            MxM11 = (TH10 * SharedAMat[i+1]) + (TH11 * SharedAMat[i+3]); 
            TH00 = MxM00; 
            TH01 = MxM01; 
            TH10 = MxM10; 
            TH11 = MxM11; 
        } 
        tempoMult[0 + blockIdx.x * 4] = TH00; 
        tempoMult[1 + blockIdx.x * 4] = TH01; 
        tempoMult[2 + blockIdx.x * 4] = TH10; 
        tempoMult[3 + blockIdx.x * 4] = TH11; 
    } 
}

	.file	"tmpxft_0037f02c_00000000-6_MM2chainKernel00.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z8multiplyPKfPfPKfPf
	.type	_Z30__device_stub__Z8multiplyPKfPfPKfPf, @function
_Z30__device_stub__Z8multiplyPKfPfPKfPf:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8multiplyPKfPf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z30__device_stub__Z8multiplyPKfPfPKfPf, .-_Z30__device_stub__Z8multiplyPKfPfPKfPf
	.globl	_Z8multiplyPKfPf
	.type	_Z8multiplyPKfPf, @function
_Z8multiplyPKfPf:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8multiplyPKfPfPKfPf
	.cfi_endproc
.LFE2052:
	.size	_Z8multiplyPKfPf, .-_Z8multiplyPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8multiplyPKfPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8multiplyPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h> 

///
/// MM2chainkernel00.cu
/// By Luke Burford 
/// Created: 1 Nov 2018

#define B 32 // threads per block 
#define C 60 // matracies proccessed per block

__global__ void multiply(const float* A, float* tempoMult){ 
    int i; 
    
    float MxM00 = 0; 
    float MxM01 = 0; 
    float MxM10 = 0; 
    float MxM11 = 0; 
    float TH00 = 0; 
    float TH01 = 0; 
    float TH10 = 0; 
    float TH11 = 0; 
    
    __shared__ float SharedAMat[(B*C*4)]; 
    
    #pragma unroll 
    for( i = 0; i<C*4; ++i){ 
        SharedAMat[threadIdx.x * C * 4 + i] = A[threadIdx.x * C * 4 + (blockIdx.x * 4 * C * B)+  i]; 
    } 
    
    __syncthreads(); 
    
    
    TH00 = SharedAMat[threadIdx.x*4*C+0]; 
    TH01 = SharedAMat[threadIdx.x*4*C+1]; 
    TH10 = SharedAMat[threadIdx.x*4*C+2]; 
    TH11 = SharedAMat[threadIdx.x*4*C+3]; 
    
    #pragma unroll 
    for (i = 4 + (threadIdx.x * 4 * C) ; i < C * 4 +  (threadIdx.x * 4 * C); i+=4){ 
        MxM00 = (TH00 * SharedAMat[i])   + (TH01 * SharedAMat[i+2]); 
        MxM01 = (TH00 * SharedAMat[i+1]) + (TH01 * SharedAMat[i+3]); 
        MxM10 = (TH10 * SharedAMat[i])   + (TH11 * SharedAMat[i+2]); 
        MxM11 = (TH10 * SharedAMat[i+1]) + (TH11 * SharedAMat[i+3]); 
        TH00 = MxM00; 
        TH01 = MxM01; 
        TH10 = MxM10; 
        TH11 = MxM11; 
    } 
    
    SharedAMat[threadIdx.x * 4 * C  + 0] = TH00; 
    SharedAMat[threadIdx.x * 4 * C  + 1] = TH01; 
    SharedAMat[threadIdx.x * 4 * C  + 2] = TH10; 
    SharedAMat[threadIdx.x * 4 * C  + 3] = TH11; 
    
    __syncthreads(); 
    
    if (threadIdx.x == 0){ 
        #pragma unroll 
        for (i = C *  4; i < B * 4 * C; i+=C * 4){ 
            MxM00 = (TH00 * SharedAMat[i])   + (TH01 * SharedAMat[i+2]); 
            MxM01 = (TH00 * SharedAMat[i+1]) + (TH01 * SharedAMat[i+3]); 
            MxM10 = (TH10 * SharedAMat[i])   + (TH11 * SharedAMat[i+2]); 
            MxM11 = (TH10 * SharedAMat[i+1]) + (TH11 * SharedAMat[i+3]); 
            TH00 = MxM00; 
            TH01 = MxM01; 
            TH10 = MxM10; 
            TH11 = MxM11; 
        } 
        tempoMult[0 + blockIdx.x * 4] = TH00; 
        tempoMult[1 + blockIdx.x * 4] = TH01; 
        tempoMult[2 + blockIdx.x * 4] = TH10; 
        tempoMult[3 + blockIdx.x * 4] = TH11; 
    } 
}

	.text
	.file	"MM2chainKernel00.hip"
	.globl	_Z23__device_stub__multiplyPKfPf # -- Begin function _Z23__device_stub__multiplyPKfPf
	.type	_Z23__device_stub__multiplyPKfPf,@function
_Z23__device_stub__multiplyPKfPf:       # @_Z23__device_stub__multiplyPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8multiplyPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__multiplyPKfPf, .Lfunc_end0-_Z23__device_stub__multiplyPKfPf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8multiplyPKfPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8multiplyPKfPf,@object        # @_Z8multiplyPKfPf
	.section	.rodata,"a",@progbits
	.globl	_Z8multiplyPKfPf
	.p2align	3, 0x0
_Z8multiplyPKfPf:
	.quad	_Z23__device_stub__multiplyPKfPf
	.size	_Z8multiplyPKfPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8multiplyPKfPf"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__multiplyPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8multiplyPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8multiplyPKfPf        ; -- Begin function _Z8multiplyPKfPf
	.globl	_Z8multiplyPKfPf
	.p2align	8
	.type	_Z8multiplyPKfPf,@function
_Z8multiplyPKfPf:                       ; @_Z8multiplyPKfPf
; %bb.0:                                ; %.lr.ph.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mul_i32 s4, s15, 0x1e00
	v_mul_u32_u24_e32 v3, 0xf0, v0
	v_mad_u32_u24 v4, 0xf0, v0, s4
	v_mov_b32_e32 v5, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v6, 2, v3
	v_lshlrev_b64 v[1:2], 2, v[4:5]
	v_mov_b32_e32 v3, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x3
	global_load_b128 v[7:10], v[1:2], off offset:48
	global_load_b128 v[11:14], v[1:2], off offset:32
	global_load_b128 v[15:18], v[1:2], off offset:16
	global_load_b128 v[19:22], v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 16, v4
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[19:22]
	ds_store_b128 v6, v[15:18] offset:16
	ds_store_b128 v6, v[11:14] offset:32
	ds_store_b128 v6, v[7:10] offset:48
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 17, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 18, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 19, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 20, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:64
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 21, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 22, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 23, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 24, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:80
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 25, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 26, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 27, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 28, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:96
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 29, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 30, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 32, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:112
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 33, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 34, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 35, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 36, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:128
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 37, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 38, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 39, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 40, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:144
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 41, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 42, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 43, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 44, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:160
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 45, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 46, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 47, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 48, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:176
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 49, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 50, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 51, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 52, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:192
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 53, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 54, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 55, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 56, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:208
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 57, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 58, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 59, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 60, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:224
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 61, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 62, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 63, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 64, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:240
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x41, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x42, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x43, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x44, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:256
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x45, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x46, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x47, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x48, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:272
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x49, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x4a, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x4b, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x4c, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:288
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x4d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x4e, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x4f, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x50, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:304
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x51, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x52, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x53, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x54, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:320
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x55, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x56, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x57, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x58, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:336
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x59, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x5a, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x5b, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x5c, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:352
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x5d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x5e, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x5f, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x60, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:368
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x61, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x62, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x63, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x64, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:384
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x65, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x66, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x67, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x68, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:400
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x69, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x6a, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x6b, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x6c, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:416
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x6d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x6e, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x6f, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x70, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:432
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x71, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x72, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x73, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x74, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:448
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x75, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x76, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x77, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x78, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:464
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x79, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x7a, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x7b, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x7c, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:480
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x7d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x7e, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x7f, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x80, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:496
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x81, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x82, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x83, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x84, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:512
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x85, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x86, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x87, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x88, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:528
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x89, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x8a, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x8b, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x8c, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:544
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x8d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x8e, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x8f, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x90, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:560
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x91, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x92, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x93, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x94, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:576
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x95, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x96, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x97, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x98, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:592
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x99, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x9a, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x9b, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x9c, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:608
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x9d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x9e, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0x9f, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa0, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:624
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa2, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa4, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:640
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa6, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa8, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:656
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xa9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xaa, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xab, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xac, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:672
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xad, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xae, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xaf, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb0, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:688
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb2, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb4, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:704
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb6, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb8, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:720
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xb9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xba, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xbb, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xbc, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:736
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xbd, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xbe, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xbf, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc0, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:752
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc2, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc4, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:768
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc6, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc8, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:784
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xc9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xca, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xcb, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xcc, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:800
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xcd, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xce, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xcf, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd0, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:816
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd2, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd4, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:832
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd6, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd8, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:848
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xd9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xda, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xdb, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xdc, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:864
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xdd, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xde, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xdf, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe0, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:880
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe2, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe4, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:896
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe6, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe8, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[7:10] offset:912
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xe9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xea, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v9, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xeb, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v10, v[1:2], off
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 0xec, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_add_nc_u32_e32 v2, 0xed, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(2)
	ds_store_b128 v6, v[7:10] offset:928
	v_dual_mov_b32 v8, v5 :: v_dual_add_nc_u32 v7, 0xee, v4
	v_add_nc_u32_e32 v4, 0xef, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_load_b32 v3, v[7:8], off
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b32 v4, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b128 v6, v[1:4] offset:944
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b128 v[1:4], v6
	ds_load_b128 v[7:10], v6 offset:16
	ds_load_b128 v[11:14], v6 offset:32
	ds_load_b128 v[15:18], v6 offset:48
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v19, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v2, v2, v10 :: v_dual_fmac_f32 v19, v1, v7
	v_dual_fmac_f32 v2, v1, v8 :: v_dual_mul_f32 v1, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v4, v10 :: v_dual_fmac_f32 v1, v3, v7
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v4, v3, v8 :: v_dual_mul_f32 v3, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v2, v2, v14 :: v_dual_mul_f32 v7, v4, v13
	v_fmac_f32_e32 v3, v19, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v2, v19, v12
	v_dual_mul_f32 v4, v4, v14 :: v_dual_fmac_f32 v7, v1, v11
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v2, v18 :: v_dual_fmac_f32 v4, v1, v12
	v_dual_mul_f32 v8, v2, v17 :: v_dual_fmac_f32 v9, v3, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v11, v4, v18 :: v_dual_fmac_f32 v8, v3, v15
	v_mul_f32_e32 v10, v4, v17
	ds_load_b128 v[1:4], v6 offset:64
	v_fmac_f32_e32 v11, v7, v16
	v_fmac_f32_e32 v10, v7, v15
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:80
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v7, v1 :: v_dual_mul_f32 v9, v9, v4
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v8, v2
	v_fmac_f32_e32 v7, v8, v1
	ds_load_b128 v[1:4], v6 offset:96
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v7, v1
	v_mul_f32_e32 v11, v11, v4
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:112
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:128
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:144
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:160
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:176
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:192
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:208
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:224
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:240
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:256
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:272
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:288
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:304
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:320
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:336
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:352
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:368
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:384
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:400
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:416
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:432
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:448
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:464
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:480
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:496
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:528
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:544
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:560
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:576
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:592
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:608
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:624
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:640
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:656
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:672
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:688
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:704
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:720
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:736
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:752
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:768
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:784
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:800
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:816
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:832
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:848
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:864
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:880
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v7, v9, v3
	v_mul_f32_e32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_dual_fmac_f32 v9, v8, v2 :: v_dual_mul_f32 v8, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v11, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_fmac_f32_e32 v11, v10, v2
	ds_load_b128 v[1:4], v6 offset:896
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v10, v7, v1
	v_fmac_f32_e32 v9, v7, v2
	v_mul_f32_e32 v7, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v1
	v_fmac_f32_e32 v11, v8, v2
	ds_load_b128 v[1:4], v6 offset:912
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v9, v4 :: v_dual_fmac_f32 v8, v10, v1
	v_dual_fmac_f32 v9, v10, v2 :: v_dual_mul_f32 v10, v11, v3
	v_mul_f32_e32 v11, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v7, v1
	v_fmac_f32_e32 v11, v7, v2
	ds_load_b128 v[1:4], v6 offset:928
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v12, v9, v3
	v_mul_f32_e32 v13, v9, v4
	v_mul_f32_e32 v4, v11, v4
	v_mul_f32_e32 v14, v11, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v12, v8, v1
	v_fmac_f32_e32 v13, v8, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v10, v2
	v_fmac_f32_e32 v14, v10, v1
	ds_load_b128 v[7:10], v6 offset:944
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v1, v13, v9
	v_dual_mul_f32 v2, v13, v10 :: v_dual_mul_f32 v3, v4, v9
	v_mul_f32_e32 v4, v4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v1, v12, v7
	v_dual_fmac_f32 v2, v12, v8 :: v_dual_fmac_f32 v3, v14, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v4, v14, v8
	ds_store_b128 v6, v[1:4]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %.preheader.preheader
	ds_load_b128 v[6:9], v5 offset:960
	ds_load_b128 v[10:13], v5 offset:1920
	ds_load_b128 v[14:17], v5 offset:2880
	ds_load_b128 v[18:21], v5 offset:3840
	s_lshl_b32 s4, s15, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(3)
	v_mul_f32_e32 v0, v2, v9
	v_dual_mul_f32 v2, v2, v8 :: v_dual_mul_f32 v9, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, v3, v7
	v_fmac_f32_e32 v0, v1, v7
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v1, v6 :: v_dual_mul_f32 v7, v0, v13
	v_mul_f32_e32 v4, v4, v8
	v_dual_mul_f32 v8, v9, v13 :: v_dual_fmac_f32 v7, v2, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v3, v6
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v8, v4, v11 :: v_dual_mul_f32 v11, v7, v17
	v_mul_f32_e32 v6, v0, v12
	v_mul_f32_e32 v12, v9, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v6, v2, v10
	ds_load_b128 v[0:3], v5 offset:4800
	v_dual_fmac_f32 v11, v6, v15 :: v_dual_fmac_f32 v12, v4, v10
	v_mul_f32_e32 v10, v8, v17
	v_mul_f32_e32 v4, v7, v16
	v_mul_f32_e32 v16, v8, v16
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v12, v15 :: v_dual_mul_f32 v15, v11, v21
	v_dual_fmac_f32 v16, v12, v14 :: v_dual_mul_f32 v17, v10, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v17, v16, v19 :: v_dual_fmac_f32 v4, v6, v14
	ds_load_b128 v[6:9], v5 offset:5760
	v_mul_f32_e32 v14, v11, v20
	v_mul_f32_e32 v20, v10, v20
	ds_load_b128 v[10:13], v5 offset:6720
	v_fmac_f32_e32 v15, v4, v19
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v4, v18 :: v_dual_mul_f32 v19, v15, v3
	v_mul_f32_e32 v15, v15, v2
	v_fmac_f32_e32 v19, v14, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v14, v0
	s_waitcnt lgkmcnt(1)
	v_mul_f32_e32 v21, v19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v21, v15, v7 :: v_dual_fmac_f32 v20, v16, v18
	v_mul_f32_e32 v16, v17, v3
	v_fmac_f32_e32 v16, v20, v1
	v_mul_f32_e32 v18, v17, v2
	ds_load_b128 v[1:4], v5 offset:7680
	v_mul_f32_e32 v9, v16, v9
	v_fmac_f32_e32 v18, v20, v0
	v_mul_f32_e32 v0, v19, v8
	v_mul_f32_e32 v19, v16, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_fmac_f32 v9, v18, v7 :: v_dual_fmac_f32 v0, v15, v6
	ds_load_b128 v[14:17], v5 offset:8640
	s_waitcnt lgkmcnt(2)
	v_dual_mul_f32 v20, v21, v13 :: v_dual_fmac_f32 v19, v18, v6
	v_mul_f32_e32 v18, v21, v12
	v_mul_f32_e32 v13, v9, v13
	v_mul_f32_e32 v21, v9, v12
	ds_load_b128 v[6:9], v5 offset:9600
	v_fmac_f32_e32 v20, v0, v11
	v_dual_fmac_f32 v18, v0, v10 :: v_dual_fmac_f32 v13, v19, v11
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, v19, v10 :: v_dual_mul_f32 v0, v20, v4
	v_mul_f32_e32 v19, v20, v3
	v_mul_f32_e32 v20, v13, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v0, v18, v2
	v_fmac_f32_e32 v19, v18, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v20, v21, v1
	v_mul_f32_e32 v4, v13, v4
	ds_load_b128 v[10:13], v5 offset:10560
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v18, v0, v17
	v_dual_fmac_f32 v4, v21, v2 :: v_dual_mul_f32 v21, v0, v16
	ds_load_b128 v[0:3], v5 offset:11520
	v_fmac_f32_e32 v18, v19, v15
	v_fmac_f32_e32 v21, v19, v14
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v9
	v_dual_mul_f32 v18, v18, v8 :: v_dual_fmac_f32 v19, v21, v7
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v18, v21, v6 :: v_dual_mul_f32 v21, v19, v13
	v_fmac_f32_e32 v21, v18, v11
	v_mul_f32_e32 v17, v4, v17
	v_mul_f32_e32 v4, v4, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v20, v15
	v_dual_fmac_f32 v4, v20, v14 :: v_dual_mul_f32 v9, v17, v9
	v_mul_f32_e32 v20, v17, v8
	ds_load_b128 v[14:17], v5 offset:12480
	v_fmac_f32_e32 v9, v4, v7
	v_fmac_f32_e32 v20, v4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mul_f32 v4, v19, v12 :: v_dual_mul_f32 v13, v9, v13
	v_mul_f32_e32 v12, v9, v12
	ds_load_b128 v[6:9], v5 offset:13440
	v_dual_fmac_f32 v4, v18, v10 :: v_dual_fmac_f32 v13, v20, v11
	s_waitcnt lgkmcnt(2)
	v_dual_mul_f32 v11, v21, v3 :: v_dual_fmac_f32 v12, v20, v10
	v_mul_f32_e32 v10, v21, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v18, v13, v3 :: v_dual_fmac_f32 v11, v4, v1
	v_dual_mul_f32 v19, v13, v2 :: v_dual_fmac_f32 v10, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v12, v1
	s_waitcnt lgkmcnt(1)
	v_mul_f32_e32 v20, v11, v17
	ds_load_b128 v[1:4], v5 offset:14400
	v_fmac_f32_e32 v19, v12, v0
	v_dual_mul_f32 v0, v11, v16 :: v_dual_mul_f32 v17, v18, v17
	v_fmac_f32_e32 v20, v10, v15
	v_mul_f32_e32 v18, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v0, v10, v14 :: v_dual_fmac_f32 v17, v19, v15
	s_waitcnt lgkmcnt(1)
	v_mul_f32_e32 v21, v20, v9
	ds_load_b128 v[10:13], v5 offset:15360
	v_dual_fmac_f32 v18, v19, v14 :: v_dual_mul_f32 v19, v20, v8
	v_mul_f32_e32 v9, v17, v9
	v_dual_fmac_f32 v21, v0, v7 :: v_dual_mul_f32 v20, v17, v8
	ds_load_b128 v[14:17], v5 offset:16320
	v_fmac_f32_e32 v19, v0, v6
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v9, v18, v7 :: v_dual_mul_f32 v0, v21, v4
	v_fmac_f32_e32 v20, v18, v6
	v_mul_f32_e32 v18, v21, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v4, v9, v4
	v_mul_f32_e32 v21, v9, v3
	ds_load_b128 v[6:9], v5 offset:17280
	v_fmac_f32_e32 v0, v19, v2
	v_fmac_f32_e32 v18, v19, v1
	v_fmac_f32_e32 v4, v20, v2
	v_fmac_f32_e32 v21, v20, v1
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v19, v0, v13
	v_mul_f32_e32 v20, v0, v12
	v_mul_f32_e32 v13, v4, v13
	v_mul_f32_e32 v4, v4, v12
	ds_load_b128 v[0:3], v5 offset:18240
	v_fmac_f32_e32 v19, v18, v11
	v_dual_fmac_f32 v20, v18, v10 :: v_dual_fmac_f32 v13, v21, v11
	v_fmac_f32_e32 v4, v21, v10
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v18, v19, v17
	v_mul_f32_e32 v19, v19, v16
	v_mul_f32_e32 v17, v13, v17
	v_mul_f32_e32 v21, v13, v16
	ds_load_b128 v[10:13], v5 offset:19200
	v_fmac_f32_e32 v18, v20, v15
	v_fmac_f32_e32 v19, v20, v14
	v_fmac_f32_e32 v17, v4, v15
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, v4, v14 :: v_dual_mul_f32 v20, v18, v9
	v_dual_mul_f32 v4, v18, v8 :: v_dual_mul_f32 v9, v17, v9
	v_mul_f32_e32 v8, v17, v8
	ds_load_b128 v[14:17], v5 offset:20160
	v_fmac_f32_e32 v20, v19, v7
	v_dual_fmac_f32 v4, v19, v6 :: v_dual_fmac_f32 v9, v21, v7
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v8, v21, v6 :: v_dual_mul_f32 v7, v20, v3
	v_mul_f32_e32 v6, v20, v2
	v_mul_f32_e32 v18, v9, v3
	v_mul_f32_e32 v19, v9, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v7, v4, v1
	v_fmac_f32_e32 v6, v4, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v18, v8, v1
	ds_load_b128 v[1:4], v5 offset:21120
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v19, v8, v0 :: v_dual_mul_f32 v20, v7, v13
	v_dual_mul_f32 v0, v7, v12 :: v_dual_mul_f32 v13, v18, v13
	v_mul_f32_e32 v18, v18, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v6, v11
	v_dual_fmac_f32 v0, v6, v10 :: v_dual_fmac_f32 v13, v19, v11
	ds_load_b128 v[6:9], v5 offset:22080
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v18, v19, v10 :: v_dual_mul_f32 v21, v20, v17
	v_mul_f32_e32 v19, v20, v16
	v_mul_f32_e32 v17, v13, v17
	v_mul_f32_e32 v20, v13, v16
	ds_load_b128 v[10:13], v5 offset:23040
	v_fmac_f32_e32 v21, v0, v15
	v_fmac_f32_e32 v19, v0, v14
	v_fmac_f32_e32 v17, v18, v15
	v_fmac_f32_e32 v20, v18, v14
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v0, v21, v4
	v_mul_f32_e32 v18, v21, v3
	v_mul_f32_e32 v4, v17, v4
	v_mul_f32_e32 v21, v17, v3
	ds_load_b128 v[14:17], v5 offset:24000
	v_fmac_f32_e32 v0, v19, v2
	v_fmac_f32_e32 v18, v19, v1
	v_fmac_f32_e32 v4, v20, v2
	v_fmac_f32_e32 v21, v20, v1
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v19, v0, v9
	v_mul_f32_e32 v20, v0, v8
	v_mul_f32_e32 v9, v4, v9
	v_mul_f32_e32 v4, v4, v8
	ds_load_b128 v[0:3], v5 offset:24960
	v_fmac_f32_e32 v19, v18, v7
	v_dual_fmac_f32 v20, v18, v6 :: v_dual_fmac_f32 v9, v21, v7
	v_fmac_f32_e32 v4, v21, v6
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v18, v19, v13
	v_mul_f32_e32 v19, v19, v12
	v_mul_f32_e32 v13, v9, v13
	v_mul_f32_e32 v21, v9, v12
	ds_load_b128 v[6:9], v5 offset:25920
	v_fmac_f32_e32 v18, v20, v11
	v_fmac_f32_e32 v19, v20, v10
	v_fmac_f32_e32 v13, v4, v11
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, v4, v10 :: v_dual_mul_f32 v20, v18, v17
	v_dual_mul_f32 v4, v13, v17 :: v_dual_mul_f32 v17, v18, v16
	v_mul_f32_e32 v16, v13, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v20, v19, v15
	ds_load_b128 v[10:13], v5 offset:26880
	v_dual_fmac_f32 v4, v21, v15 :: v_dual_fmac_f32 v17, v19, v14
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v16, v21, v14 :: v_dual_mul_f32 v15, v20, v3
	v_mul_f32_e32 v18, v20, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v14, v4, v3
	v_mul_f32_e32 v19, v4, v2
	v_fmac_f32_e32 v15, v17, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v18, v17, v0
	v_fmac_f32_e32 v14, v16, v1
	ds_load_b128 v[1:4], v5 offset:27840
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v19, v16, v0 :: v_dual_mul_f32 v20, v15, v9
	v_dual_mul_f32 v21, v15, v8 :: v_dual_mul_f32 v0, v14, v9
	v_mul_f32_e32 v22, v14, v8
	ds_load_b128 v[14:17], v5 offset:28800
	v_fmac_f32_e32 v20, v18, v7
	v_dual_fmac_f32 v21, v18, v6 :: v_dual_fmac_f32 v0, v19, v7
	v_fmac_f32_e32 v22, v19, v6
	ds_load_b128 v[6:9], v5 offset:29760
	s_waitcnt lgkmcnt(3)
	v_mul_f32_e32 v18, v20, v13
	v_mul_f32_e32 v19, v20, v12
	v_mul_f32_e32 v13, v0, v13
	v_mul_f32_e32 v0, v0, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v18, v21, v11
	v_fmac_f32_e32 v19, v21, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v13, v22, v11
	v_fmac_f32_e32 v0, v22, v10
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v11, v18, v4
	v_mul_f32_e32 v10, v18, v3
	v_mul_f32_e32 v4, v13, v4
	v_mul_f32_e32 v3, v13, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v11, v19, v2
	v_fmac_f32_e32 v10, v19, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v0, v2
	v_fmac_f32_e32 v3, v0, v1
	s_waitcnt lgkmcnt(1)
	v_mul_f32_e32 v2, v11, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v11, v11, v16 :: v_dual_mul_f32 v12, v4, v17
	v_mul_f32_e32 v4, v4, v16
	v_fmac_f32_e32 v2, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v11, v10, v14 :: v_dual_fmac_f32 v12, v3, v15
	v_fmac_f32_e32 v4, v3, v14
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v0, v2, v8
	v_dual_mul_f32 v1, v2, v9 :: v_dual_mul_f32 v2, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v3, v12, v9 :: v_dual_fmac_f32 v0, v11, v6
	v_dual_fmac_f32 v1, v11, v7 :: v_dual_fmac_f32 v2, v4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v3, v4, v7
	global_store_b128 v5, v[0:3], s[0:1]
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8multiplyPKfPf
		.amdhsa_group_segment_fixed_size 30720
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8multiplyPKfPf, .Lfunc_end0-_Z8multiplyPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 15624
; NumSgprs: 18
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 30720 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 30720
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8multiplyPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8multiplyPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
