#include<stdio.h>
#include<stdlib.h>

__device__ int gpuHistogram[10];

__global__ void computeGpuHistogram(int *arr, int noOfElements)
{
    //clear the global gpu Histogram array
	if(blockIdx.x == 0 && threadIdx.x < 10)
		gpuHistogram[threadIdx.x] = 0;

	//force all threads to wait for the first 10 threads 
	__syncthreads();

	//initialize the counter variables. 
	//NOTE: These variables will be allocated to registers.
	int count0 = 0, 
	    count1 = 0,
		count2 = 0,
		count3 = 0,
		count4 = 0,
		count5 = 0,
		count6 = 0,
		count7 = 0,
		count8 = 0,
		count9 = 0;

	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int noOfThreads = blockDim.x * gridDim.x;

    while(tid < noOfElements)
	{
		if(arr[tid] == 0)
			++count0;
		else if(arr[tid] == 1)
			++count1;
        else if(arr[tid] == 2)
			++count2;
		else if(arr[tid] == 3)
			++count3;
		else if(arr[tid] == 4)
			++count4;
		else if(arr[tid] == 5)
			++count5;
		else if(arr[tid] == 6)
			++count6;
		else if(arr[tid] == 7)
			++count7;
		else if(arr[tid] == 8)
			++count8;
		else
			++count9;

		tid += noOfThreads;
	}

    //wait for all threads to complete writing into the shared mem.
	__syncthreads();

	//compute the final histogram.
	atomicAdd(&gpuHistogram[0], count0);
	atomicAdd(&gpuHistogram[1], count1);
	atomicAdd(&gpuHistogram[2], count2);
	atomicAdd(&gpuHistogram[3], count3);
	atomicAdd(&gpuHistogram[4], count4);
	atomicAdd(&gpuHistogram[5], count5);
	atomicAdd(&gpuHistogram[6], count6);
	atomicAdd(&gpuHistogram[7], count7);
	atomicAdd(&gpuHistogram[8], count8);
	atomicAdd(&gpuHistogram[9], count9);

}


void checkError(cudaError_t error, char * function)
{
	if(error != cudaSuccess)
	{
	    printf("\"%s\" has a problem with error code %d and desc: %s\n", function, error, cudaGetErrorString(error));
	    exit(-1);
    }
} 

void readValue(int *value, char * msg, int lowerBound, int upperBound)
{
	while(1)
	{
		printf("%s(%d-%d): ", msg, lowerBound, upperBound);
		scanf("%d", value);
		
		if(*value <= upperBound && *value >= lowerBound)
		    return;	

		printf("Incorrect values. Enter again.\n");
	}
}

void fillArrayWithRandNos(int * arr, int noOfElements)
{
	int i;
	srand(5);												//for consistent numbers on every run.
	if(noOfElements < 20)
	{
		for(i = 0 ; i < noOfElements; ++i)
		{
            arr[i] = rand()%10;
			printf("%d   ", arr[i]);
		}
        printf("\n");
		return;
	}

	for(i = 0 ; i < noOfElements; ++i)
		arr[i] = rand()%10;
}

void computeHistogram(int *arr, int *histogram, int noOfElements)
{
	int i;
	for(i = 0 ; i < noOfElements ; ++i)
		++histogram[arr[i]];
}

bool cpuGpuResultsCompare(int *cpuResultsArray, int * histogramFromGPU)
{
	for(int i = 0 ; i < 10 ; i ++)
    	if(cpuResultsArray[i] != histogramFromGPU[i])
			return false;

	return true;
}

int main()
{
	int noOfElements = -1, i;
	int *arr, *gpuArray;
    size_t size; 
	
	//have variables for threads per block, number of blocks.
    int threadsPerBlock = 0, blocksInGrid = 0;

    //create cuda event variables
    cudaEvent_t hostStart, hostStop, deviceStart, deviceStop;
    float timeDifferenceOnHost, timeDifferenceOnDevice;
    
    //create cuda events.
    cudaEventCreate(&hostStart);
	cudaEventCreate(&hostStop);
	cudaEventCreate(&deviceStart);
	cudaEventCreate(&deviceStop);
    while(1)
	{
		int histogram[10] = {0,0,0,0,0,0,0,0,0,0}, histogramFromGPU[10];
		
		printf("Enter the no. of elements to run test on: ");
		scanf("%d", &noOfElements);

    	arr = (int *)malloc(noOfElements * sizeof(int));

		printf("Filling array with random numbers...\n");
		fillArrayWithRandNos(arr, noOfElements);

	    printf("Computing histogram on CPU...\n");
		cudaEventRecord(hostStart, 0);
	    computeHistogram(arr, histogram, noOfElements);
		cudaEventRecord(hostStop, 0);
	    cudaEventElapsedTime(&timeDifferenceOnHost, hostStart, hostStop);

		//printf("Computation over. Results of CPU computation:\n");
		//for(i = 0 ; i < 10 ; ++i)
	        //printf("No of %d: %d\n", i, histogram[i]);
	
	
		size = noOfElements * sizeof(int);
	    checkError(cudaMalloc((void**)&gpuArray, size), "Mallocing array on GPU");
	
		checkError(cudaMemcpy(gpuArray, arr, size, cudaMemcpyHostToDevice), "Input array copy");
	   
		//create a proper grid block using dim3
	    readValue(&threadsPerBlock, "Enter no. of threads per block(input of 'P' will construct a P threaded linear block)", 4,1024);
		readValue(&blocksInGrid, "Enter no. of blocks in grid(input of 'P' will construct linear grid with P blocks)", 0, 65535/threadsPerBlock+1);
	
		cudaEventRecord(deviceStart, 0);
	 	computeGpuHistogram<<<blocksInGrid, threadsPerBlock>>>(gpuArray, noOfElements);   
	    cudaThreadSynchronize();
	    cudaEventRecord(deviceStop, 0);
		cudaEventElapsedTime(&timeDifferenceOnDevice, deviceStart, deviceStop);
	
		cudaMemcpyFromSymbol(&histogramFromGPU,"gpuHistogram", sizeof(histogramFromGPU), 0, cudaMemcpyDeviceToHost);
	
	  	if(cpuGpuResultsCompare(histogram, histogramFromGPU))
			printf("GPU and CPU results match\n");
		else
			printf("GPU and CPU results don't match\n");

		printf("CPU & GPU stats: \n");
		for(i = 0 ; i < 10 ; ++i)
	        printf("No of %ds: %d %d\n", i, histogram[i], histogramFromGPU[i]);
			
		printf("Time on CPU : %5.5f, Time on GPU: %5.5f\n", timeDifferenceOnHost, timeDifferenceOnDevice);
	
		printf("-----------------------------------------------\n");
		printf("Speedup: %5.5f\n", timeDifferenceOnHost/timeDifferenceOnDevice);
	
    	free(arr);
		cudaFree(gpuArray);

		char c = 'n';
	 	printf("Again?(y/n): ");
		while(true)
		{
		   c = getchar();
	       if(c == 'y' || c == 'n')
	   	  	  break;
	    }
	   
	    if(c == 'n')
	       break;
	}	 
	printf("\n");

	cudaEventDestroy(deviceStop);
	cudaEventDestroy(deviceStart);
	cudaEventDestroy(hostStart);
	cudaEventDestroy(hostStop);

    return 0;
}

	.file	"tmpxft_00224aa7_00000000-6_GPUHistogram.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\"%s\" has a problem with error code %d and desc: %s\n"
	.text
	.globl	_Z10checkError9cudaErrorPc
	.type	_Z10checkError9cudaErrorPc, @function
_Z10checkError9cudaErrorPc:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movl	%ebx, %ecx
	movq	%rbp, %rdx
	movq	%rax, %r8
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z10checkError9cudaErrorPc, .-_Z10checkError9cudaErrorPc
	.section	.rodata.str1.1
.LC1:
	.string	"%s(%d-%d): "
.LC2:
	.string	"%d"
.LC3:
	.string	"Incorrect values. Enter again.\n"
	.text
	.globl	_Z9readValuePiPcii
	.type	_Z9readValuePiPcii, @function
_Z9readValuePiPcii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	leaq	.LC1(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rdi, %rbx
.L10:
	movl	%r12d, %r8d
	movl	%ebp, %ecx
	movq	%r13, %rdx
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rsi
	leaq	.LC2(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	(%rbx), %eax
	cmpl	%ebp, %eax
	jl	.L9
	cmpl	%r12d, %eax
	jle	.L17
.L9:
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L10
.L17:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9readValuePiPcii, .-_Z9readValuePiPcii
	.section	.rodata.str1.1
.LC4:
	.string	"%d   "
.LC5:
	.string	"\n"
	.text
	.globl	_Z20fillArrayWithRandNosPii
	.type	_Z20fillArrayWithRandNosPii, @function
_Z20fillArrayWithRandNosPii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movslq	%esi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	movl	$5, %edi
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	srand@PLT
	cmpl	$19, %ebp
	jg	.L26
	xorl	%r12d, %r12d
	leaq	.LC4(%rip), %r13
.L20:
	cmpl	%r12d, %ebp
	jle	.L28
	call	rand@PLT
	movl	$10, %ecx
	movq	%r13, %rsi
	movl	$2, %edi
	cltd
	idivl	%ecx
	xorl	%eax, %eax
	movl	%edx, (%rbx,%r12,4)
	incq	%r12
	call	__printf_chk@PLT
	jmp	.L20
.L28:
	popq	%rdx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	leaq	.LC5(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L26:
	.cfi_restore_state
	leaq	(%rbx,%rbp,4), %r12
	movl	$10, %ebp
.L23:
	call	rand@PLT
	addq	$4, %rbx
	cltd
	idivl	%ebp
	movl	%edx, -4(%rbx)
	cmpq	%r12, %rbx
	jne	.L23
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z20fillArrayWithRandNosPii, .-_Z20fillArrayWithRandNosPii
	.globl	_Z16computeHistogramPiS_i
	.type	_Z16computeHistogramPiS_i, @function
_Z16computeHistogramPiS_i:
.LFB2030:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L30:
	cmpl	%eax, %edx
	jle	.L32
	movslq	(%rdi,%rax,4), %rcx
	incq	%rax
	incl	(%rsi,%rcx,4)
	jmp	.L30
.L32:
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z16computeHistogramPiS_i, .-_Z16computeHistogramPiS_i
	.globl	_Z20cpuGpuResultsComparePiS_
	.type	_Z20cpuGpuResultsComparePiS_, @function
_Z20cpuGpuResultsComparePiS_:
.LFB2031:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L35:
	movl	(%rsi,%rax), %edx
	cmpl	%edx, (%rdi,%rax)
	jne	.L36
	addq	$4, %rax
	cmpq	$40, %rax
	jne	.L35
	movb	$1, %al
	ret
.L36:
	xorl	%eax, %eax
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z20cpuGpuResultsComparePiS_, .-_Z20cpuGpuResultsComparePiS_
	.globl	_Z40__device_stub__Z19computeGpuHistogramPiiPii
	.type	_Z40__device_stub__Z19computeGpuHistogramPiiPii, @function
_Z40__device_stub__Z19computeGpuHistogramPiiPii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z19computeGpuHistogramPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L38:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z40__device_stub__Z19computeGpuHistogramPiiPii, .-_Z40__device_stub__Z19computeGpuHistogramPiiPii
	.globl	_Z19computeGpuHistogramPii
	.type	_Z19computeGpuHistogramPii, @function
_Z19computeGpuHistogramPii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z19computeGpuHistogramPiiPii
	.cfi_endproc
.LFE2058:
	.size	_Z19computeGpuHistogramPii, .-_Z19computeGpuHistogramPii
	.section	.rodata.str1.1
.LC6:
	.string	"Enter the no. of elements to run test on: "
.LC7:
	.string	"Filling array with random numbers...\n"
.LC8:
	.string	"Computing histogram on CPU...\n"
.LC9:
	.string	"Mallocing array on GPU"
.LC10:
	.string	"Input array copy"
.LC11:
	.string	"Enter no. of threads per block(input of 'P' will construct a P threaded linear block)"
.LC12:
	.string	"Enter no. of blocks in grid(input of 'P' will construct linear grid with P blocks)"
.LC13:
	.string	"gpuHistogram"
.LC14:
	.string	"GPU and CPU results match\n"
.LC15:
	.string	"GPU and CPU results don't match\n"
.LC16:
	.string	"CPU & GPU stats: \n"
.LC17:
	.string	"No of %ds: %d %d\n"
.LC18:
	.string	"Time on CPU : %5.5f, Time on GPU: %5.5f\n"
.LC19:
	.string	"-----------------------------------------------\n"
.LC20:
	.string	"Speedup: %5.5f\n"
.LC21:
	.string	"Again?(y/n): "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rdi
	xorl	%eax, %eax
	movl	$-1, 4(%rsp)
	movl	%eax, 8(%rsp)
	movl	%eax, 12(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
.L51:
	movl	%r13d, %eax
	leaq	88(%rsp), %rdi
	movl	$10, %ecx
	rep stosl
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	4(%rsp), %rsi
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rdi
	call	__isoc23_scanf@PLT
	movslq	4(%rsp), %rdi
	leaq	88(%rsp), %r12
	salq	$2, %rdi
	call	malloc@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	4(%rsp), %esi
	movq	%rbx, %rdi
	call	_Z20fillArrayWithRandNosPii
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	4(%rsp), %edx
	movq	%r12, %rsi
	movq	%rbx, %rdi
	call	_Z16computeHistogramPiS_i
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movslq	4(%rsp), %rbp
	leaq	24(%rsp), %rdi
	salq	$2, %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	.LC9(%rip), %rsi
	movl	%eax, %edi
	call	_Z10checkError9cudaErrorPc
	movq	24(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z10checkError9cudaErrorPc
	leaq	8(%rsp), %rdi
	movl	$1024, %ecx
	movl	$4, %edx
	leaq	.LC11(%rip), %rsi
	call	_Z9readValuePiPcii
	movl	$65535, %eax
	leaq	12(%rsp), %rdi
	leaq	.LC12(%rip), %rsi
	cltd
	idivl	8(%rsp)
	xorl	%edx, %edx
	leal	1(%rax), %ecx
	call	_Z9readValuePiPcii
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	8(%rsp), %eax
	movl	12(%rsp), %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 76(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movl	84(%rsp), %ecx
	movl	%edx, 64(%rsp)
	movq	76(%rsp), %rdx
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movl	4(%rsp), %esi
	movq	24(%rsp), %rdi
	call	_Z40__device_stub__Z19computeGpuHistogramPiiPii
.L44:
	call	cudaThreadSynchronize@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	leaq	128(%rsp), %r14
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	$40, %edx
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	leaq	.LC13(%rip), %rsi
	movl	$2, %r8d
	call	cudaMemcpyFromSymbol@PLT
	movq	%r14, %rsi
	movq	%r12, %rdi
	call	_Z20cpuGpuResultsComparePiS_
	leaq	.LC14(%rip), %rsi
	testb	%al, %al
	jne	.L58
	leaq	.LC15(%rip), %rsi
.L58:
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC17(%rip), %r15
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L47:
	movl	(%r12,%rbp,4), %ecx
	movl	(%r14,%rbp,4), %r8d
	movl	%ebp, %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$10, %rbp
	jne	.L47
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	20(%rsp), %xmm1
	cvtss2sd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC19(%rip), %rsi
	call	__printf_chk@PLT
	leaq	.LC20(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	16(%rsp), %xmm0
	divss	20(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC21(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L48:
	call	getchar@PLT
	cmpb	$121, %al
	je	.L53
	cmpb	$110, %al
	jne	.L48
	jmp	.L50
.L53:
	cmpb	$110, %al
	jne	.L51
.L50:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z19computeGpuHistogramPii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19computeGpuHistogramPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movl	$40, %r9d
	leaq	_ZL12gpuHistogram(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL12gpuHistogram
	.comm	_ZL12gpuHistogram,40,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>

__device__ int gpuHistogram[10];

__global__ void computeGpuHistogram(int *arr, int noOfElements)
{
    //clear the global gpu Histogram array
	if(blockIdx.x == 0 && threadIdx.x < 10)
		gpuHistogram[threadIdx.x] = 0;

	//force all threads to wait for the first 10 threads 
	__syncthreads();

	//initialize the counter variables. 
	//NOTE: These variables will be allocated to registers.
	int count0 = 0, 
	    count1 = 0,
		count2 = 0,
		count3 = 0,
		count4 = 0,
		count5 = 0,
		count6 = 0,
		count7 = 0,
		count8 = 0,
		count9 = 0;

	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int noOfThreads = blockDim.x * gridDim.x;

    while(tid < noOfElements)
	{
		if(arr[tid] == 0)
			++count0;
		else if(arr[tid] == 1)
			++count1;
        else if(arr[tid] == 2)
			++count2;
		else if(arr[tid] == 3)
			++count3;
		else if(arr[tid] == 4)
			++count4;
		else if(arr[tid] == 5)
			++count5;
		else if(arr[tid] == 6)
			++count6;
		else if(arr[tid] == 7)
			++count7;
		else if(arr[tid] == 8)
			++count8;
		else
			++count9;

		tid += noOfThreads;
	}

    //wait for all threads to complete writing into the shared mem.
	__syncthreads();

	//compute the final histogram.
	atomicAdd(&gpuHistogram[0], count0);
	atomicAdd(&gpuHistogram[1], count1);
	atomicAdd(&gpuHistogram[2], count2);
	atomicAdd(&gpuHistogram[3], count3);
	atomicAdd(&gpuHistogram[4], count4);
	atomicAdd(&gpuHistogram[5], count5);
	atomicAdd(&gpuHistogram[6], count6);
	atomicAdd(&gpuHistogram[7], count7);
	atomicAdd(&gpuHistogram[8], count8);
	atomicAdd(&gpuHistogram[9], count9);

}


void checkError(hipError_t error, char * function)
{
	if(error != hipSuccess)
	{
	    printf("\"%s\" has a problem with error code %d and desc: %s\n", function, error, hipGetErrorString(error));
	    exit(-1);
    }
} 

void readValue(int *value, char * msg, int lowerBound, int upperBound)
{
	while(1)
	{
		printf("%s(%d-%d): ", msg, lowerBound, upperBound);
		scanf("%d", value);
		
		if(*value <= upperBound && *value >= lowerBound)
		    return;	

		printf("Incorrect values. Enter again.\n");
	}
}

void fillArrayWithRandNos(int * arr, int noOfElements)
{
	int i;
	srand(5);												//for consistent numbers on every run.
	if(noOfElements < 20)
	{
		for(i = 0 ; i < noOfElements; ++i)
		{
            arr[i] = rand()%10;
			printf("%d   ", arr[i]);
		}
        printf("\n");
		return;
	}

	for(i = 0 ; i < noOfElements; ++i)
		arr[i] = rand()%10;
}

void computeHistogram(int *arr, int *histogram, int noOfElements)
{
	int i;
	for(i = 0 ; i < noOfElements ; ++i)
		++histogram[arr[i]];
}

bool cpuGpuResultsCompare(int *cpuResultsArray, int * histogramFromGPU)
{
	for(int i = 0 ; i < 10 ; i ++)
    	if(cpuResultsArray[i] != histogramFromGPU[i])
			return false;

	return true;
}

int main()
{
	int noOfElements = -1, i;
	int *arr, *gpuArray;
    size_t size; 
	
	//have variables for threads per block, number of blocks.
    int threadsPerBlock = 0, blocksInGrid = 0;

    //create cuda event variables
    hipEvent_t hostStart, hostStop, deviceStart, deviceStop;
    float timeDifferenceOnHost, timeDifferenceOnDevice;
    
    //create cuda events.
    hipEventCreate(&hostStart);
	hipEventCreate(&hostStop);
	hipEventCreate(&deviceStart);
	hipEventCreate(&deviceStop);
    while(1)
	{
		int histogram[10] = {0,0,0,0,0,0,0,0,0,0}, histogramFromGPU[10];
		
		printf("Enter the no. of elements to run test on: ");
		scanf("%d", &noOfElements);

    	arr = (int *)malloc(noOfElements * sizeof(int));

		printf("Filling array with random numbers...\n");
		fillArrayWithRandNos(arr, noOfElements);

	    printf("Computing histogram on CPU...\n");
		hipEventRecord(hostStart, 0);
	    computeHistogram(arr, histogram, noOfElements);
		hipEventRecord(hostStop, 0);
	    hipEventElapsedTime(&timeDifferenceOnHost, hostStart, hostStop);

		//printf("Computation over. Results of CPU computation:\n");
		//for(i = 0 ; i < 10 ; ++i)
	        //printf("No of %d: %d\n", i, histogram[i]);
	
	
		size = noOfElements * sizeof(int);
	    checkError(hipMalloc((void**)&gpuArray, size), "Mallocing array on GPU");
	
		checkError(hipMemcpy(gpuArray, arr, size, hipMemcpyHostToDevice), "Input array copy");
	   
		//create a proper grid block using dim3
	    readValue(&threadsPerBlock, "Enter no. of threads per block(input of 'P' will construct a P threaded linear block)", 4,1024);
		readValue(&blocksInGrid, "Enter no. of blocks in grid(input of 'P' will construct linear grid with P blocks)", 0, 65535/threadsPerBlock+1);
	
		hipEventRecord(deviceStart, 0);
	 	computeGpuHistogram<<<blocksInGrid, threadsPerBlock>>>(gpuArray, noOfElements);   
	    hipDeviceSynchronize();
	    hipEventRecord(deviceStop, 0);
		hipEventElapsedTime(&timeDifferenceOnDevice, deviceStart, deviceStop);
	
		hipMemcpyFromSymbol(&histogramFromGPU,HIP_SYMBOL("gpuHistogram"), sizeof(histogramFromGPU), 0, hipMemcpyDeviceToHost);
	
	  	if(cpuGpuResultsCompare(histogram, histogramFromGPU))
			printf("GPU and CPU results match\n");
		else
			printf("GPU and CPU results don't match\n");

		printf("CPU & GPU stats: \n");
		for(i = 0 ; i < 10 ; ++i)
	        printf("No of %ds: %d %d\n", i, histogram[i], histogramFromGPU[i]);
			
		printf("Time on CPU : %5.5f, Time on GPU: %5.5f\n", timeDifferenceOnHost, timeDifferenceOnDevice);
	
		printf("-----------------------------------------------\n");
		printf("Speedup: %5.5f\n", timeDifferenceOnHost/timeDifferenceOnDevice);
	
    	free(arr);
		hipFree(gpuArray);

		char c = 'n';
	 	printf("Again?(y/n): ");
		while(true)
		{
		   c = getchar();
	       if(c == 'y' || c == 'n')
	   	  	  break;
	    }
	   
	    if(c == 'n')
	       break;
	}	 
	printf("\n");

	hipEventDestroy(deviceStop);
	hipEventDestroy(deviceStart);
	hipEventDestroy(hostStart);
	hipEventDestroy(hostStop);

    return 0;
}

	.text
	.file	"GPUHistogram.hip"
	.globl	_Z34__device_stub__computeGpuHistogramPii # -- Begin function _Z34__device_stub__computeGpuHistogramPii
	.type	_Z34__device_stub__computeGpuHistogramPii,@function
_Z34__device_stub__computeGpuHistogramPii: # @_Z34__device_stub__computeGpuHistogramPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19computeGpuHistogramPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__computeGpuHistogramPii, .Lfunc_end0-_Z34__device_stub__computeGpuHistogramPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10checkError10hipError_tPc    # -- Begin function _Z10checkError10hipError_tPc
	.type	_Z10checkError10hipError_tPc,@function
_Z10checkError10hipError_tPc:           # @_Z10checkError10hipError_tPc
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB1_2
# %bb.1:
	retq
.LBB1_2:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z10checkError10hipError_tPc, .Lfunc_end1-_Z10checkError10hipError_tPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z9readValuePiPcii              # -- Begin function _Z9readValuePiPcii
	.type	_Z9readValuePiPcii,@function
_Z9readValuePiPcii:                     # @_Z9readValuePiPcii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	$.L.str.1, %edi
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%r15), %eax
	cmpl	%ebx, %eax
	jg	.LBB2_3
# %bb.2:                                #   in Loop: Header=BB2_1 Depth=1
	cmpl	%ebp, %eax
	jge	.LBB2_4
.LBB2_3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_1 Depth=1
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	jmp	.LBB2_1
.LBB2_4:                                # %._crit_edge
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9readValuePiPcii, .Lfunc_end2-_Z9readValuePiPcii
	.cfi_endproc
                                        # -- End function
	.globl	_Z20fillArrayWithRandNosPii     # -- Begin function _Z20fillArrayWithRandNosPii
	.type	_Z20fillArrayWithRandNosPii,@function
_Z20fillArrayWithRandNosPii:            # @_Z20fillArrayWithRandNosPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	$5, %edi
	callq	srand
	cmpl	$20, %ebp
	jge	.LBB3_1
# %bb.4:                                # %.preheader
	testl	%ebp, %ebp
	jle	.LBB3_7
# %bb.5:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB3_6:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movslq	%eax, %rsi
	imulq	$1717986919, %rsi, %rax         # imm = 0x66666667
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$34, %rax
	addl	%ecx, %eax
	addl	%eax, %eax
	leal	(%rax,%rax,4), %eax
	subl	%eax, %esi
	movl	%esi, (%rbx,%r15,4)
	movl	$.L.str.4, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB3_6
.LBB3_7:                                # %._crit_edge
	movl	$10, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	putchar@PLT                     # TAILCALL
.LBB3_1:                                # %.preheader14.preheader
	.cfi_def_cfa_offset 48
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB3_2:                                # %.preheader14
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB3_2
# %bb.3:                                # %.loopexit
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z20fillArrayWithRandNosPii, .Lfunc_end3-_Z20fillArrayWithRandNosPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z16computeHistogramPiS_i       # -- Begin function _Z16computeHistogramPiS_i
	.type	_Z16computeHistogramPiS_i,@function
_Z16computeHistogramPiS_i:              # @_Z16computeHistogramPiS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB4_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorl	%ecx, %ecx
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%rdi,%rcx,4), %rdx
	incl	(%rsi,%rdx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_2
.LBB4_3:                                # %._crit_edge
	retq
.Lfunc_end4:
	.size	_Z16computeHistogramPiS_i, .Lfunc_end4-_Z16computeHistogramPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20cpuGpuResultsComparePiS_    # -- Begin function _Z20cpuGpuResultsComparePiS_
	.type	_Z20cpuGpuResultsComparePiS_,@function
_Z20cpuGpuResultsComparePiS_:           # @_Z20cpuGpuResultsComparePiS_
	.cfi_startproc
# %bb.0:
	movl	(%rdi), %eax
	cmpl	(%rsi), %eax
	jne	.LBB5_5
# %bb.1:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
.LBB5_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rcx, %rax
	cmpq	$9, %rcx
	je	.LBB5_4
# %bb.3:                                #   in Loop: Header=BB5_2 Depth=1
	movl	4(%rdi,%rax,4), %edx
	leaq	1(%rax), %rcx
	cmpl	4(%rsi,%rax,4), %edx
	je	.LBB5_2
.LBB5_4:                                # %._crit_edge.loopexit
	cmpq	$9, %rax
	setae	%al
                                        # kill: def $al killed $al killed $eax
	retq
.LBB5_5:
	xorl	%eax, %eax
                                        # kill: def $al killed $al killed $eax
	retq
.Lfunc_end5:
	.size	_Z20cpuGpuResultsComparePiS_, .Lfunc_end5-_Z20cpuGpuResultsComparePiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967296, %r12               # imm = 0x100000000
	movq	%rsp, %rbx
	movl	$-1, (%rbx)
	xorl	%eax, %eax
	leaq	12(%rsp), %r14
	movl	%eax, (%r14)
	leaq	60(%rsp), %r15
	movl	%eax, (%r15)
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
.LBB6_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_3 Depth 2
                                        #     Child Loop BB6_8 Depth 2
                                        #     Child Loop BB6_13 Depth 2
                                        #     Child Loop BB6_15 Depth 2
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 80(%rsp)
	movaps	%xmm0, 64(%rsp)
	movq	$0, 96(%rsp)
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%rsp), %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %r13
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	(%rsp), %esi
	movq	%r13, %rdi
	callq	_Z20fillArrayWithRandNosPii
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB6_4
# %bb.2:                                # %.lr.ph.preheader.i
                                        #   in Loop: Header=BB6_1 Depth=1
	xorl	%ecx, %ecx
.LBB6_3:                                # %.lr.ph.i
                                        #   Parent Loop BB6_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	(%r13,%rcx,4), %rdx
	incl	64(%rsp,%rdx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB6_3
.LBB6_4:                                # %_Z16computeHistogramPiS_i.exit
                                        #   in Loop: Header=BB6_1 Depth=1
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	8(%rsp), %rdi
	callq	hipEventElapsedTime
	movslq	(%rsp), %rbp
	shlq	$2, %rbp
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.9, %esi
	movl	%eax, %edi
	callq	_Z10checkError10hipError_tPc
	movq	48(%rsp), %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.10, %esi
	movl	%eax, %edi
	callq	_Z10checkError10hipError_tPc
	movl	$.L.str.11, %esi
	movq	%r14, %rdi
	movl	$4, %edx
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z9readValuePiPcii
	movl	$65535, %eax                    # imm = 0xFFFF
	xorl	%edx, %edx
	idivl	12(%rsp)
                                        # kill: def $eax killed $eax def $rax
	leal	1(%rax), %ecx
	movl	$.L.str.12, %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_Z9readValuePiPcii
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	60(%rsp), %edi
	movl	12(%rsp), %edx
	orq	%r12, %rdi
	orq	%r12, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_6
# %bb.5:                                #   in Loop: Header=BB6_1 Depth=1
	movq	48(%rsp), %rdi
	movl	(%rsp), %esi
	callq	_Z34__device_stub__computeGpuHistogramPii
.LBB6_6:                                #   in Loop: Header=BB6_1 Depth=1
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	4(%rsp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.13, %esi
	movl	$40, %edx
	leaq	112(%rsp), %rdi
	xorl	%ecx, %ecx
	movl	$2, %r8d
	callq	hipMemcpyFromSymbol
	movl	64(%rsp), %eax
	cmpl	112(%rsp), %eax
	jne	.LBB6_11
# %bb.7:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB6_1 Depth=1
	movq	$-1, %rax
.LBB6_8:                                # %.lr.ph
                                        #   Parent Loop BB6_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.Lstr.4, %edi
	cmpq	$8, %rax
	je	.LBB6_12
# %bb.9:                                #   in Loop: Header=BB6_8 Depth=2
	movl	72(%rsp,%rax,4), %edx
	leaq	1(%rax), %rcx
	cmpl	120(%rsp,%rax,4), %edx
	movq	%rcx, %rax
	je	.LBB6_8
# %bb.10:                               # %_Z20cpuGpuResultsComparePiS_.exit
                                        #   in Loop: Header=BB6_1 Depth=1
	cmpq	$8, %rcx
	ja	.LBB6_12
.LBB6_11:                               # %.critedge
                                        #   in Loop: Header=BB6_1 Depth=1
	movl	$.Lstr.3, %edi
.LBB6_12:                               # %_Z20cpuGpuResultsComparePiS_.exit.thread
                                        #   in Loop: Header=BB6_1 Depth=1
	callq	puts@PLT
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	xorl	%ebp, %ebp
.LBB6_13:                               #   Parent Loop BB6_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	64(%rsp,%rbp,4), %edx
	movl	112(%rsp,%rbp,4), %ecx
	movl	$.L.str.17, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%rbp
	cmpq	$10, %rbp
	jne	.LBB6_13
# %bb.14:                               #   in Loop: Header=BB6_1 Depth=1
	cvtss2sd	8(%rsp), %xmm0
	cvtss2sd	4(%rsp), %xmm1
	movl	$.L.str.18, %edi
	movb	$2, %al
	callq	printf
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movss	8(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	divss	4(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.20, %edi
	movb	$1, %al
	callq	printf
	movq	%r13, %rdi
	callq	free
	movq	48(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.21, %edi
	xorl	%eax, %eax
	callq	printf
.LBB6_15:                               #   Parent Loop BB6_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	getchar
	cmpb	$110, %al
	je	.LBB6_17
# %bb.16:                               #   in Loop: Header=BB6_15 Depth=2
	movzbl	%al, %eax
	cmpl	$121, %eax
	jne	.LBB6_15
	jmp	.LBB6_1
.LBB6_17:
	movl	$10, %edi
	callq	putchar@PLT
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	xorl	%eax, %eax
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19computeGpuHistogramPii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$gpuHistogram, %esi
	movl	$.L.str.13, %edx
	movl	$.L.str.13, %ecx
	movl	$40, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	gpuHistogram,@object            # @gpuHistogram
	.local	gpuHistogram
	.comm	gpuHistogram,40,16
	.type	_Z19computeGpuHistogramPii,@object # @_Z19computeGpuHistogramPii
	.section	.rodata,"a",@progbits
	.globl	_Z19computeGpuHistogramPii
	.p2align	3, 0x0
_Z19computeGpuHistogramPii:
	.quad	_Z34__device_stub__computeGpuHistogramPii
	.size	_Z19computeGpuHistogramPii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\"%s\" has a problem with error code %d and desc: %s\n"
	.size	.L.str, 52

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%s(%d-%d): "
	.size	.L.str.1, 12

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d"
	.size	.L.str.2, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d   "
	.size	.L.str.4, 6

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Enter the no. of elements to run test on: "
	.size	.L.str.6, 43

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Mallocing array on GPU"
	.size	.L.str.9, 23

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Input array copy"
	.size	.L.str.10, 17

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Enter no. of threads per block(input of 'P' will construct a P threaded linear block)"
	.size	.L.str.11, 86

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Enter no. of blocks in grid(input of 'P' will construct linear grid with P blocks)"
	.size	.L.str.12, 83

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"gpuHistogram"
	.size	.L.str.13, 13

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"No of %ds: %d %d\n"
	.size	.L.str.17, 18

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Time on CPU : %5.5f, Time on GPU: %5.5f\n"
	.size	.L.str.18, 41

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"Speedup: %5.5f\n"
	.size	.L.str.20, 16

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"Again?(y/n): "
	.size	.L.str.21, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19computeGpuHistogramPii"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Incorrect values. Enter again."
	.size	.Lstr, 31

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Filling array with random numbers..."
	.size	.Lstr.1, 37

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Computing histogram on CPU..."
	.size	.Lstr.2, 30

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"GPU and CPU results don't match"
	.size	.Lstr.3, 32

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"GPU and CPU results match"
	.size	.Lstr.4, 26

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"CPU & GPU stats: "
	.size	.Lstr.5, 18

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"-----------------------------------------------"
	.size	.Lstr.6, 48

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__computeGpuHistogramPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym gpuHistogram
	.addrsig_sym _Z19computeGpuHistogramPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19computeGpuHistogramPii ; -- Begin function _Z19computeGpuHistogramPii
	.globl	_Z19computeGpuHistogramPii
	.p2align	8
	.type	_Z19computeGpuHistogramPii,@function
_Z19computeGpuHistogramPii:             ; @_Z19computeGpuHistogramPii
; %bb.0:
	v_cmp_gt_u32_e32 vcc_lo, 10, v0
	s_cmp_eq_u32 s15, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, vcc_lo
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+4
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+12
	global_store_b32 v1, v2, s[4:5]
.LBB0_2:                                ; %._crit_edge82
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s6, s[0:1], 0x8
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 0
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v21, 0
	s_mov_b32 s8, 0
	s_mov_b32 s7, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_mov_b32_e32 v15, 0
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_mov_b32_e32 v0, 0
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB0_44
; %bb.3:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v15, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 0
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v21, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s4
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[2:3], 2
.LBB0_4:                                ; %NodeBlock146
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v22, v[2:3], off
	v_dual_mov_b32 v14, v21 :: v_dual_mov_b32 v13, v20
	v_dual_mov_b32 v12, v19 :: v_dual_mov_b32 v11, v18
	v_dual_mov_b32 v10, v16 :: v_dual_mov_b32 v9, v17
	v_dual_mov_b32 v8, v15 :: v_dual_mov_b32 v7, v0
	v_mov_b32_e32 v6, v5
	s_mov_b32 s0, 0
	s_mov_b32 s3, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 3, v22
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_24
; %bb.5:                                ; %NodeBlock144
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s9, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
	v_cmpx_lt_i32_e32 5, v22
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_17
; %bb.6:                                ; %NodeBlock142
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
	v_cmpx_lt_i32_e32 6, v22
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB0_14
; %bb.7:                                ; %NodeBlock140
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
	v_cmpx_lt_i32_e32 7, v22
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %LeafBlock138
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, -1
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr0
	v_cmpx_eq_u32_e32 8, v22
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v0, 1, v7
	s_xor_b32 s10, exec_lo, -1
; %bb.10:                               ; %Flow155
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v18, v11
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v16, v10
	v_mov_b32_e32 v17, v9
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v20, v13
	v_mov_b32_e32 v21, v14
	s_and_b32 s10, s10, exec_lo
.LBB0_11:                               ; %Flow154
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s11, s11
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v0, v7 :: v_dual_add_nc_u32 v15, 1, v8
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v18, v11
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v20, v13
	v_mov_b32_e32 v21, v14
; %bb.13:                               ; %Flow156
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s10, s10, exec_lo
.LBB0_14:                               ; %Flow153
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s9, s9
; %bb.15:                               ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v0, v7 :: v_dual_add_nc_u32 v17, 1, v9
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v18, v11
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v20, v13
	v_mov_b32_e32 v21, v14
; %bb.16:                               ; %Flow157
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s9, s10, exec_lo
                                        ; implicit-def: $vgpr22
.LBB0_17:                               ; %Flow152
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_23
; %bb.18:                               ; %NodeBlock136
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $vgpr16
	v_cmpx_lt_i32_e32 4, v22
	s_xor_b32 s10, exec_lo, s10
; %bb.19:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v16, 1, v10
; %bb.20:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_saveexec_b32 s10, s10
	v_mov_b32_e32 v18, v11
	s_xor_b32 exec_lo, exec_lo, s10
; %bb.21:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v18, 1, v11
	v_mov_b32_e32 v16, v10
; %bb.22:                               ; %Flow148
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v0, v7
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v20, v13
	v_mov_b32_e32 v17, v9
	v_mov_b32_e32 v19, v12
	v_mov_b32_e32 v21, v14
.LBB0_23:                               ; %Flow158
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s9, exec_lo
                                        ; implicit-def: $vgpr22
.LBB0_24:                               ; %Flow151
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_38
; %bb.25:                               ; %NodeBlock134
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
	v_cmpx_lt_i32_e32 1, v22
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_31
; %bb.26:                               ; %NodeBlock132
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr19
	v_cmpx_lt_i32_e32 2, v22
	s_xor_b32 s9, exec_lo, s9
; %bb.27:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v19, 1, v12
; %bb.28:                               ; %Flow149
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_saveexec_b32 s9, s9
	v_mov_b32_e32 v20, v13
	s_xor_b32 exec_lo, exec_lo, s9
; %bb.29:                               ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v19, v12 :: v_dual_add_nc_u32 v20, 1, v13
; %bb.30:                               ; %Flow150
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v0, v7
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v11
	v_mov_b32_e32 v21, v14
                                        ; implicit-def: $vgpr22
.LBB0_31:                               ; %Flow160
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_saveexec_b32 s0, s0
	s_mov_b32 s9, 0
	s_mov_b32 s10, s3
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_37
; %bb.32:                               ; %NodeBlock
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr21
	v_cmpx_lt_i32_e32 0, v22
	s_xor_b32 s9, exec_lo, s9
; %bb.33:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v21, 1, v14
                                        ; implicit-def: $vgpr22
; %bb.34:                               ; %Flow162
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_saveexec_b32 s10, s9
	s_mov_b32 s9, 0
	s_mov_b32 s11, s3
	s_xor_b32 exec_lo, exec_lo, s10
; %bb.35:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 0, v22
	s_and_not1_b32 s11, s3, exec_lo
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr21
	s_and_b32 s12, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s11, s12
; %bb.36:                               ; %Flow163
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v0, v7
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v11
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v20, v13
	s_and_not1_b32 s10, s3, exec_lo
	s_and_b32 s11, s11, exec_lo
	s_and_b32 s9, s9, exec_lo
	s_or_b32 s10, s10, s11
.LBB0_37:                               ; %Flow161
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_and_b32 s0, s9, exec_lo
	s_or_b32 s3, s3, s10
.LBB0_38:                               ; %Flow159
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s3
; %bb.39:                               ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v0, v7 :: v_dual_add_nc_u32 v5, 1, v6
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v11
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v20, v13
	v_mov_b32_e32 v21, v14
	s_and_not1_b32 s0, s0, exec_lo
; %bb.40:                               ; %Flow164
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
; %bb.41:                               ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v21, v14 :: v_dual_add_nc_u32 v4, 1, v4
	v_dual_mov_b32 v20, v13 :: v_dual_mov_b32 v19, v12
	v_dual_mov_b32 v18, v11 :: v_dual_mov_b32 v17, v9
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v8
	v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v5, v6
; %bb.42:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_u32 v2, s0, v2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	v_cmp_le_i32_e32 vcc_lo, s6, v1
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_4
; %bb.43:                               ; %Flow165
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_44:                               ; %Flow166
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s0, exec_lo
	s_mov_b32 s1, 0
	s_barrier
	buffer_gl0_inv
.LBB0_45:                               ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s3, v4, s2
	s_lshl_b32 s2, 1, s2
	s_and_not1_b32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s1, s1, s3
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_45
; %bb.46:                               ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s0, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_48
; %bb.47:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+4
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+12
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_48:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_49:                               ; %ComputeLoop83
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s1
	v_readlane_b32 s3, v21, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s1, s1, s2
	s_add_i32 s0, s0, s3
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB0_49
; %bb.50:                               ; %ComputeEnd84
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_52
; %bb.51:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+8
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+16
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_52:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
.LBB0_53:                               ; %ComputeLoop87
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s0
	v_readlane_b32 s3, v20, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s0, s0, s2
	s_add_i32 s1, s1, s3
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_53
; %bb.54:                               ; %ComputeEnd88
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s0, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_56
; %bb.55:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+12
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+20
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_56:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_57:                               ; %ComputeLoop91
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s1
	v_readlane_b32 s3, v19, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s1, s1, s2
	s_add_i32 s0, s0, s3
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB0_57
; %bb.58:                               ; %ComputeEnd92
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_60
; %bb.59:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+16
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+24
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_60:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
.LBB0_61:                               ; %ComputeLoop95
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s0
	v_readlane_b32 s3, v18, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s0, s0, s2
	s_add_i32 s1, s1, s3
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_61
; %bb.62:                               ; %ComputeEnd96
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s0, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_64
; %bb.63:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+20
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+28
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_64:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_65:                               ; %ComputeLoop99
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s1
	v_readlane_b32 s3, v16, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s1, s1, s2
	s_add_i32 s0, s0, s3
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB0_65
; %bb.66:                               ; %ComputeEnd100
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_68
; %bb.67:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+24
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+32
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_68:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
.LBB0_69:                               ; %ComputeLoop103
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s0
	v_readlane_b32 s3, v17, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s0, s0, s2
	s_add_i32 s1, s1, s3
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_69
; %bb.70:                               ; %ComputeEnd104
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s0, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_72
; %bb.71:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+28
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+36
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_72:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_73:                               ; %ComputeLoop107
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s1
	v_readlane_b32 s3, v15, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s1, s1, s2
	s_add_i32 s0, s0, s3
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB0_73
; %bb.74:                               ; %ComputeEnd108
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_76
; %bb.75:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+32
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+40
	global_atomic_add_u32 v1, v2, s[4:5]
.LBB0_76:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
.LBB0_77:                               ; %ComputeLoop111
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s0
	v_readlane_b32 s3, v0, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s0, s0, s2
	s_add_i32 s1, s1, s3
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_77
; %bb.78:                               ; %ComputeEnd112
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s0, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_80
; %bb.79:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpuHistogram@rel32@lo+36
	s_addc_u32 s5, s5, gpuHistogram@rel32@hi+44
	global_atomic_add_u32 v0, v1, s[4:5]
.LBB0_80:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_81:                               ; %ComputeLoop115
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ctz_i32_b32 s2, s1
	v_readlane_b32 s3, v5, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s1, s1, s2
	s_add_i32 s0, s0, s3
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB0_81
; %bb.82:                               ; %ComputeEnd116
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_84
; %bb.83:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gpuHistogram@rel32@lo+40
	s_addc_u32 s3, s3, gpuHistogram@rel32@hi+48
	global_atomic_add_u32 v0, v1, s[2:3]
.LBB0_84:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19computeGpuHistogramPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19computeGpuHistogramPii, .Lfunc_end0-_Z19computeGpuHistogramPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2296
; NumSgprs: 18
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	gpuHistogram            ; @gpuHistogram
	.type	gpuHistogram,@object
	.section	.bss,"aw",@nobits
	.globl	gpuHistogram
	.p2align	4, 0x0
gpuHistogram:
	.zero	40
	.size	gpuHistogram, 40

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym gpuHistogram
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19computeGpuHistogramPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19computeGpuHistogramPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
