#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <ctime>

#define ITERATIONS 100
#define ARR_SIZE 1000000

#define ARR_SIZE_PRINT_LIMIT 100

//CUDA values
#define NUM_BLOCKS 4096
#define NUM_THREADS 1

//Random values range
const int MIN_RAND_NUM = -100;
const int MAX_RAND_NUM = 100;

void print_array(int *arr, int size){
    if(size > ARR_SIZE_PRINT_LIMIT){
        return;
    }
    for(int i = 0; i < size; ++i){
        printf("%d ", arr[i]);
    }
    printf("\n");
}

__device__ void sort_2_preordered_segments(const int &start_idx, const int &middle_idx, const int &end_idx, int* from, int* to){
    //Define the starting indexes of the leftmost segment, the rightmost segment and the new segment 
    //that will store the new sorted segment as a combination of the 2 previous ones
    int left_idx  = start_idx;
    int right_idx = middle_idx+1;
    int idx = start_idx;

    //Sort the new segment by sorting the two previously sorted leftmost and rightmost segments
    while(left_idx <= middle_idx || right_idx <= end_idx){

        if(left_idx <= middle_idx && right_idx <= end_idx){

            if(from[left_idx] < from[right_idx]){
                to[idx++] = from[left_idx++];
            } else{
                to[idx++] = from[right_idx++];
            }

        } else if(left_idx <= middle_idx){
            to[idx++] = from[left_idx++];
        } else{
            to[idx++] = from[right_idx++];
        }
    }
}

__global__ void process_layer(int *from, int *to, int layer_size, int num_segments, int segments_per_block){

    int index = blockIdx.x*blockDim.x + threadIdx.x;
    int range_size = index*segments_per_block;

    //End process if blockId surpasses the number of segments to process
    if(range_size >= num_segments){
        return;
    }

    //Iterate over each segment in charge of the current Block in the array [FROM] of size "layer_size" and 
    //sort it as 2 separated ordered lists into the new array [TO]
    for(int range_idx = range_size; 
        range_idx < range_size+segments_per_block && range_idx < num_segments; ++range_idx){
        
        int segment_idx = range_idx*layer_size;

        //Current segment is complete (it has a size of at least "layer_size")
        if( segment_idx+layer_size-1 < ARR_SIZE ){

            //Get start, end and middle indexes of the current segment to sort it as 2 previously ordered segments
            //The first segment from start_idx to middle_idx
            //The second segment from middle_idx+1 to end_idx
            int start_idx   = segment_idx;
            int end_idx     = segment_idx+layer_size-1;
            int middle_idx  = (start_idx+end_idx)>>1;

            //Sort the preordered segments into a new combined ordered segment
            sort_2_preordered_segments(start_idx, middle_idx, end_idx, from, to);

        } else if( ARR_SIZE-segment_idx > (layer_size>>1) ){     //Last segment in layer is not complete but is greater than the previous "layer_size"

            //Get start, end and middle index of the leftmost and rightmost segments
            int start_idx    = segment_idx;
            int end_idx      = ARR_SIZE-1;
            int middle_idx   = segment_idx+(layer_size>>1)-1;

            //Sort the preordered segments into a new combined ordered segment
            sort_2_preordered_segments(start_idx, middle_idx, end_idx, from, to);
        } else{     //Last segment in layer is not complete but is smaller than the previous "layer_size"

            //Copy the last segment directly from [FROM] to [TO]
            for(int i = segment_idx; i < ARR_SIZE; ++i){
                to[i] = from[i];
            }
        }
    }  
}

__global__ void process_last_layer(int *from, int *to, int layer_size){

    //Get start, end and middle index of the leftmost and rightmost segments
    int start_idx    = 0;
    int end_idx      = ARR_SIZE-1;
    int middle_idx   = (layer_size>>1)-1;

    //Sort the preordered segments into a new combined ordered segment
    sort_2_preordered_segments(start_idx, middle_idx, end_idx, from, to);
}

int* iterative_merge_sort(int *arrA, int *arrB){

    //Auxiliar pointers to know to which array; the segments to sort are being passed during each layer
    //Each layer will always try to get the elements to sort from the [FROM] array and put the sorted elements to the [TO] array
    int *from   = arrA;
    int *to     = arrB;

    //The size of the segments in each processed layer
    int layer_size;

    //Iterate over all the segment sizes that are powers of two (2, 4, 8, 16, ...) to sort the array by layers of that sizes
    for(layer_size = 2; layer_size <= ARR_SIZE; layer_size <<= 1){
        
        //Each layer swaps the [FROM] and [TO] pointers so the array that was previously the target to store the newly ordered segments
        //is now the one were the ordered segments are extracted from
        std::swap(from,to);

        //Number of segments of the total array size to be processed in the current layer
        int num_segments        = ARR_SIZE/layer_size+(ARR_SIZE%layer_size != 0);
        //Number of segments to be processed by each block
        int segments_per_block  = num_segments/(NUM_BLOCKS*NUM_THREADS)+
                                (num_segments%(NUM_BLOCKS*NUM_THREADS) != 0); 

        //CUDA Kernel
        process_layer<<<NUM_BLOCKS,NUM_THREADS>>>(from, to, layer_size, num_segments, segments_per_block);
        //cudaDeviceSynchronize();
    }

    //An extra layer has to be processed due to the fact that ARR_SIZE is not a perfect power of 2
    if(layer_size > ARR_SIZE){

        std::swap(from, to);

        //CUDA Kernel
        process_last_layer<<<1,1>>>(from, to, layer_size);
        //cudaDeviceSynchronize();
    }

    //Return pointer to final sorted values of the array
    return to;
}

int main(){

    //Random Seed
    srand(time(NULL));

    //Allocate array's A memory
    int *arrA = (int*)malloc(sizeof(int)*ARR_SIZE);

    //Allocate array's B memory
    int *arrB = (int*)malloc(sizeof(int)*ARR_SIZE);

    //Device arrays reference pointers
    int *deviceA, *deviceB;
    //Allocate space for device copies of array A, B

    cudaMalloc((void**) &deviceA, sizeof(int)*ARR_SIZE);
    cudaMalloc((void**) &deviceB, sizeof(int)*ARR_SIZE);

    for(int iteration = 0; iteration < ITERATIONS; ++iteration){

        //Initialize array A and array B with random values
        for(int i = 0; i < ARR_SIZE; ++i){
            arrA[i] = arrB[i] = (rand()%(MAX_RAND_NUM-MIN_RAND_NUM+1))+MIN_RAND_NUM;
        }

        //Copy initialized arrays to device
        cudaMemcpy(deviceA, arrA, sizeof(int)*ARR_SIZE, cudaMemcpyHostToDevice);
        cudaMemcpy(deviceB, arrB, sizeof(int)*ARR_SIZE, cudaMemcpyHostToDevice);

        //Print array A
        print_array(arrA, ARR_SIZE);

        //Iterative merge sort
        int *sorted_array = iterative_merge_sort(deviceA, deviceB);

        //Copy sorted array from device to host
        cudaMemcpy(arrB, sorted_array, sizeof(int)*ARR_SIZE, cudaMemcpyDeviceToHost);

        //Print any error regarding the GPU
        //printf("%s\n", cudaGetErrorString(cudaGetLastError()));

        //Print whatever array the pointer "to" ended up pointing to (this one stores the final sorted values)
        print_array(arrB, ARR_SIZE);
    }

    //Free allocated memory
    free(arrA);
    free(arrB);

    //Free device allocated memory
    cudaFree(deviceA);
    cudaFree(deviceB);

    return 0;
}
	.file	"tmpxft_002ae58b_00000000-6_iterative_merge_sort_cuda.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
.LC1:
	.string	"\n"
	.text
	.globl	_Z11print_arrayPii
	.type	_Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB3635:
	.cfi_startproc
	endbr64
	cmpl	$100, %esi
	jg	.L2
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
.L4:
	cmpl	%ebx, %ebp
	jle	.L10
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L4
.L10:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC1(%rip), %rsi
	popq	%rbx
	.cfi_restore 3
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_restore 6
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_restore 12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_restore 13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L2:
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z11print_arrayPii, .-_Z11print_arrayPii
	.globl	_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_
	.type	_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_, @function
_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_, .-_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_
	.globl	_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii
	.type	_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii, @function
_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13process_layerPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii, .-_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii
	.globl	_Z13process_layerPiS_iii
	.type	_Z13process_layerPiS_iii, @function
_Z13process_layerPiS_iii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii
	.cfi_endproc
.LFE3665:
	.size	_Z13process_layerPiS_iii, .-_Z13process_layerPiS_iii
	.globl	_Z41__device_stub__Z18process_last_layerPiS_iPiS_i
	.type	_Z41__device_stub__Z18process_last_layerPiS_iPiS_i, @function
_Z41__device_stub__Z18process_last_layerPiS_iPiS_i:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18process_last_layerPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L18:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z41__device_stub__Z18process_last_layerPiS_iPiS_i, .-_Z41__device_stub__Z18process_last_layerPiS_iPiS_i
	.globl	_Z18process_last_layerPiS_i
	.type	_Z18process_last_layerPiS_i, @function
_Z18process_last_layerPiS_i:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18process_last_layerPiS_iPiS_i
	.cfi_endproc
.LFE3667:
	.size	_Z18process_last_layerPiS_i, .-_Z18process_last_layerPiS_i
	.globl	_Z20iterative_merge_sortPiS_
	.type	_Z20iterative_merge_sortPiS_, @function
_Z20iterative_merge_sortPiS_:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movabsq	$4294967297, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	$19, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	$2, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rsi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
.L25:
	movl	$1048577, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, %rdx
	salq	$12, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r14, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movl	$1000000, %eax
	movl	$4096, %esi
	movq	%rbx, %rdi
	cltd
	idivl	%r12d
	cmpl	$1, %edx
	sbbl	$-1, %eax
	xorl	%r8d, %r8d
	testl	$4095, %eax
	movl	%eax, %ecx
	setne	%r8b
	cltd
	idivl	%esi
	movl	%r12d, %edx
	movq	%rbp, %rsi
	addl	%eax, %r8d
	call	_Z38__device_stub__Z13process_layerPiS_iiiPiS_iii
.L24:
	addl	%r12d, %r12d
	decl	%r13d
	je	.L30
	xchgq	%rbx, %rbp
	jmp	.L25
.L30:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 28(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	%r12d, %edx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	call	_Z41__device_stub__Z18process_last_layerPiS_iPiS_i
.L23:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z20iterative_merge_sortPiS_, .-_Z20iterative_merge_sortPiS_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%edi, %edi
	movl	$201, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	$100, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movl	$4000000, %edi
	call	malloc@PLT
	movl	$4000000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4000000, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
.L32:
	xorl	%r12d, %r12d
.L33:
	call	rand@PLT
	cltd
	idivl	%r14d
	subl	$100, %edx
	movl	%edx, (%rbx,%r12)
	movl	%edx, 0(%rbp,%r12)
	addq	$4, %r12
	cmpq	$4000000, %r12
	jne	.L33
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$4000000, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4000000, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z20iterative_merge_sortPiS_
	movl	$2, %ecx
	movl	$4000000, %edx
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	cudaMemcpy@PLT
	decl	%r13d
	jne	.L32
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z18process_last_layerPiS_i"
.LC3:
	.string	"_Z13process_layerPiS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18process_last_layerPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13process_layerPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <ctime>

#define ITERATIONS 100
#define ARR_SIZE 1000000

#define ARR_SIZE_PRINT_LIMIT 100

//CUDA values
#define NUM_BLOCKS 4096
#define NUM_THREADS 1

//Random values range
const int MIN_RAND_NUM = -100;
const int MAX_RAND_NUM = 100;

void print_array(int *arr, int size){
    if(size > ARR_SIZE_PRINT_LIMIT){
        return;
    }
    for(int i = 0; i < size; ++i){
        printf("%d ", arr[i]);
    }
    printf("\n");
}

__device__ void sort_2_preordered_segments(const int &start_idx, const int &middle_idx, const int &end_idx, int* from, int* to){
    //Define the starting indexes of the leftmost segment, the rightmost segment and the new segment 
    //that will store the new sorted segment as a combination of the 2 previous ones
    int left_idx  = start_idx;
    int right_idx = middle_idx+1;
    int idx = start_idx;

    //Sort the new segment by sorting the two previously sorted leftmost and rightmost segments
    while(left_idx <= middle_idx || right_idx <= end_idx){

        if(left_idx <= middle_idx && right_idx <= end_idx){

            if(from[left_idx] < from[right_idx]){
                to[idx++] = from[left_idx++];
            } else{
                to[idx++] = from[right_idx++];
            }

        } else if(left_idx <= middle_idx){
            to[idx++] = from[left_idx++];
        } else{
            to[idx++] = from[right_idx++];
        }
    }
}

__global__ void process_layer(int *from, int *to, int layer_size, int num_segments, int segments_per_block){

    int index = blockIdx.x*blockDim.x + threadIdx.x;
    int range_size = index*segments_per_block;

    //End process if blockId surpasses the number of segments to process
    if(range_size >= num_segments){
        return;
    }

    //Iterate over each segment in charge of the current Block in the array [FROM] of size "layer_size" and 
    //sort it as 2 separated ordered lists into the new array [TO]
    for(int range_idx = range_size; 
        range_idx < range_size+segments_per_block && range_idx < num_segments; ++range_idx){
        
        int segment_idx = range_idx*layer_size;

        //Current segment is complete (it has a size of at least "layer_size")
        if( segment_idx+layer_size-1 < ARR_SIZE ){

            //Get start, end and middle indexes of the current segment to sort it as 2 previously ordered segments
            //The first segment from start_idx to middle_idx
            //The second segment from middle_idx+1 to end_idx
            int start_idx   = segment_idx;
            int end_idx     = segment_idx+layer_size-1;
            int middle_idx  = (start_idx+end_idx)>>1;

            //Sort the preordered segments into a new combined ordered segment
            sort_2_preordered_segments(start_idx, middle_idx, end_idx, from, to);

        } else if( ARR_SIZE-segment_idx > (layer_size>>1) ){     //Last segment in layer is not complete but is greater than the previous "layer_size"

            //Get start, end and middle index of the leftmost and rightmost segments
            int start_idx    = segment_idx;
            int end_idx      = ARR_SIZE-1;
            int middle_idx   = segment_idx+(layer_size>>1)-1;

            //Sort the preordered segments into a new combined ordered segment
            sort_2_preordered_segments(start_idx, middle_idx, end_idx, from, to);
        } else{     //Last segment in layer is not complete but is smaller than the previous "layer_size"

            //Copy the last segment directly from [FROM] to [TO]
            for(int i = segment_idx; i < ARR_SIZE; ++i){
                to[i] = from[i];
            }
        }
    }  
}

__global__ void process_last_layer(int *from, int *to, int layer_size){

    //Get start, end and middle index of the leftmost and rightmost segments
    int start_idx    = 0;
    int end_idx      = ARR_SIZE-1;
    int middle_idx   = (layer_size>>1)-1;

    //Sort the preordered segments into a new combined ordered segment
    sort_2_preordered_segments(start_idx, middle_idx, end_idx, from, to);
}

int* iterative_merge_sort(int *arrA, int *arrB){

    //Auxiliar pointers to know to which array; the segments to sort are being passed during each layer
    //Each layer will always try to get the elements to sort from the [FROM] array and put the sorted elements to the [TO] array
    int *from   = arrA;
    int *to     = arrB;

    //The size of the segments in each processed layer
    int layer_size;

    //Iterate over all the segment sizes that are powers of two (2, 4, 8, 16, ...) to sort the array by layers of that sizes
    for(layer_size = 2; layer_size <= ARR_SIZE; layer_size <<= 1){
        
        //Each layer swaps the [FROM] and [TO] pointers so the array that was previously the target to store the newly ordered segments
        //is now the one were the ordered segments are extracted from
        std::swap(from,to);

        //Number of segments of the total array size to be processed in the current layer
        int num_segments        = ARR_SIZE/layer_size+(ARR_SIZE%layer_size != 0);
        //Number of segments to be processed by each block
        int segments_per_block  = num_segments/(NUM_BLOCKS*NUM_THREADS)+
                                (num_segments%(NUM_BLOCKS*NUM_THREADS) != 0); 

        //CUDA Kernel
        process_layer<<<NUM_BLOCKS,NUM_THREADS>>>(from, to, layer_size, num_segments, segments_per_block);
        //cudaDeviceSynchronize();
    }

    //An extra layer has to be processed due to the fact that ARR_SIZE is not a perfect power of 2
    if(layer_size > ARR_SIZE){

        std::swap(from, to);

        //CUDA Kernel
        process_last_layer<<<1,1>>>(from, to, layer_size);
        //cudaDeviceSynchronize();
    }

    //Return pointer to final sorted values of the array
    return to;
}

int main(){

    //Random Seed
    srand(time(NULL));

    //Allocate array's A memory
    int *arrA = (int*)malloc(sizeof(int)*ARR_SIZE);

    //Allocate array's B memory
    int *arrB = (int*)malloc(sizeof(int)*ARR_SIZE);

    //Device arrays reference pointers
    int *deviceA, *deviceB;
    //Allocate space for device copies of array A, B

    hipMalloc((void**) &deviceA, sizeof(int)*ARR_SIZE);
    hipMalloc((void**) &deviceB, sizeof(int)*ARR_SIZE);

    for(int iteration = 0; iteration < ITERATIONS; ++iteration){

        //Initialize array A and array B with random values
        for(int i = 0; i < ARR_SIZE; ++i){
            arrA[i] = arrB[i] = (rand()%(MAX_RAND_NUM-MIN_RAND_NUM+1))+MIN_RAND_NUM;
        }

        //Copy initialized arrays to device
        hipMemcpy(deviceA, arrA, sizeof(int)*ARR_SIZE, hipMemcpyHostToDevice);
        hipMemcpy(deviceB, arrB, sizeof(int)*ARR_SIZE, hipMemcpyHostToDevice);

        //Print array A
        print_array(arrA, ARR_SIZE);

        //Iterative merge sort
        int *sorted_array = iterative_merge_sort(deviceA, deviceB);

        //Copy sorted array from device to host
        hipMemcpy(arrB, sorted_array, sizeof(int)*ARR_SIZE, hipMemcpyDeviceToHost);

        //Print any error regarding the GPU
        //printf("%s\n", cudaGetErrorString(cudaGetLastError()));

        //Print whatever array the pointer "to" ended up pointing to (this one stores the final sorted values)
        print_array(arrB, ARR_SIZE);
    }

    //Free allocated memory
    free(arrA);
    free(arrB);

    //Free device allocated memory
    hipFree(deviceA);
    hipFree(deviceB);

    return 0;
}
	.text
	.file	"iterative_merge_sort_cuda.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z11print_arrayPii              # -- Begin function _Z11print_arrayPii
	.type	_Z11print_arrayPii,@function
_Z11print_arrayPii:                     # @_Z11print_arrayPii
	.cfi_startproc
# %bb.0:
	cmpl	$100, %esi
	jle	.LBB0_1
# %bb.6:
	retq
.LBB0_1:                                # %.preheader
	testl	%esi, %esi
	jle	.LBB0_5
# %bb.2:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB0_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB0_3
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB0_5:                                # %._crit_edge
	movl	$10, %edi
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end0:
	.size	_Z11print_arrayPii, .Lfunc_end0-_Z11print_arrayPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__process_layerPiS_iii # -- Begin function _Z28__device_stub__process_layerPiS_iii
	.type	_Z28__device_stub__process_layerPiS_iii,@function
_Z28__device_stub__process_layerPiS_iii: # @_Z28__device_stub__process_layerPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13process_layerPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__process_layerPiS_iii, .Lfunc_end1-_Z28__device_stub__process_layerPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__process_last_layerPiS_i # -- Begin function _Z33__device_stub__process_last_layerPiS_i
	.type	_Z33__device_stub__process_last_layerPiS_i,@function
_Z33__device_stub__process_last_layerPiS_i: # @_Z33__device_stub__process_last_layerPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18process_last_layerPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z33__device_stub__process_last_layerPiS_i, .Lfunc_end2-_Z33__device_stub__process_last_layerPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20iterative_merge_sortPiS_    # -- Begin function _Z20iterative_merge_sortPiS_
	.type	_Z20iterative_merge_sortPiS_,@function
_Z20iterative_merge_sortPiS_:           # @_Z20iterative_merge_sortPiS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	$2, %r12d
	movabsq	$4294967297, %r15               # imm = 0x100000001
	leaq	4095(%r15), %r13
	movl	$1000000, %ebp                  # imm = 0xF4240
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %r14
	movq	%rdi, %rbx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_3
# %bb.2:                                #   in Loop: Header=BB3_1 Depth=1
	movl	$1000000, %eax                  # imm = 0xF4240
	xorl	%edx, %edx
	divl	%r12d
	leal	-1(%r12), %ecx
	andl	%ebp, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movl	%eax, %r8d
	shrl	$12, %r8d
	movl	%eax, %ecx
	andl	$4095, %ecx                     # imm = 0xFFF
	cmpl	$1, %ecx
	sbbl	$-1, %r8d
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_Z28__device_stub__process_layerPiS_iii
.LBB3_3:                                #   in Loop: Header=BB3_1 Depth=1
	addl	%r12d, %r12d
	movq	%r14, %rdi
	cmpl	$1000001, %r12d                 # imm = 0xF4241
	jl	.LBB3_1
# %bb.4:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	callq	_Z33__device_stub__process_last_layerPiS_i
.LBB3_6:
	movq	%r14, %rax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z20iterative_merge_sortPiS_, .Lfunc_end3-_Z20iterative_merge_sortPiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%r15d, %r15d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	malloc
	movq	%rax, %rbx
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	malloc
	movq	%rax, %r14
	leaq	16(%rsp), %rdi
	movl	$4000000, %esi                  # imm = 0x3D0900
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4000000, %esi                  # imm = 0x3D0900
	callq	hipMalloc
.LBB4_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_2 Depth 2
	xorl	%r12d, %r12d
.LBB4_2:                                #   Parent Loop BB4_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$42735993, %rax, %rcx           # imm = 0x28C1979
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	imull	$201, %ecx, %ecx
	negl	%ecx
	addl	%ecx, %eax
	addl	$-100, %eax
	movl	%eax, (%r14,%r12,4)
	movl	%eax, (%rbx,%r12,4)
	incq	%r12
	cmpq	$1000000, %r12                  # imm = 0xF4240
	jne	.LBB4_2
# %bb.3:                                #   in Loop: Header=BB4_1 Depth=1
	movq	16(%rsp), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z20iterative_merge_sortPiS_
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%r14, %rdi
	movq	%rax, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	incl	%r15d
	cmpl	$100, %r15d
	jne	.LBB4_1
# %bb.4:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13process_layerPiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18process_last_layerPiS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d "
	.size	.L.str, 4

	.type	_Z13process_layerPiS_iii,@object # @_Z13process_layerPiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z13process_layerPiS_iii
	.p2align	3, 0x0
_Z13process_layerPiS_iii:
	.quad	_Z28__device_stub__process_layerPiS_iii
	.size	_Z13process_layerPiS_iii, 8

	.type	_Z18process_last_layerPiS_i,@object # @_Z18process_last_layerPiS_i
	.globl	_Z18process_last_layerPiS_i
	.p2align	3, 0x0
_Z18process_last_layerPiS_i:
	.quad	_Z33__device_stub__process_last_layerPiS_i
	.size	_Z18process_last_layerPiS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13process_layerPiS_iii"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18process_last_layerPiS_i"
	.size	.L__unnamed_2, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__process_layerPiS_iii
	.addrsig_sym _Z33__device_stub__process_last_layerPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13process_layerPiS_iii
	.addrsig_sym _Z18process_last_layerPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13process_layerPiS_iii ; -- Begin function _Z13process_layerPiS_iii
	.globl	_Z13process_layerPiS_iii
	.p2align	8
	.type	_Z13process_layerPiS_iii,@function
_Z13process_layerPiS_iii:               ; @_Z13process_layerPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_mul_lo_u32 v7, v1, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s5, v7
	s_cbranch_execz .LBB0_45
; %bb.1:                                ; %.preheader69
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_45
; %bb.2:                                ; %.lr.ph72
	s_load_b128 s[8:11], s[0:1], 0x0
	s_mul_i32 s0, s6, s4
	v_add_nc_u32_e32 v2, s6, v7
	v_mul_lo_u32 v0, s0, v1
	s_ashr_i32 s1, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_sub_i32 s2, 0xf4240, s1
	v_min_i32_e32 v8, s5, v2
	s_cmp_lt_i32 s1, 1
	s_mov_b32 s5, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, -1, v0
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
                                        ;     Child Loop BB0_30 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	v_mul_lo_u32 v3, v7, s4
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v10, s4, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_lt_i32_e32 0xf4240, v10
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_27
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_le_i32_e64 s2, v3
	s_xor_b32 s7, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.5:                                ; %.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_i32_e32 0xf4240, v3
	s_cbranch_execz .LBB0_8
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_co_u32 v3, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	s_mov_b32 s13, 0
.LBB0_7:                                ; %.lr.ph
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v6, v[3:4], off
	v_add_nc_u32_e32 v5, 1, v5
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, 0xf423e, v5
	s_or_b32 s13, vcc_lo, s13
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v6, off
	v_add_co_u32 v1, s0, v1, 4
	v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_7
.LBB0_8:                                ; %Flow110
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_9:                                ; %Flow118
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_saveexec_b32 s0, s7
	s_cbranch_execz .LBB0_26
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v10, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s14, 0xf423f, v10
	s_and_b32 s7, s3, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s12, s7, -1
	s_and_saveexec_b32 s7, s12
	s_cbranch_execz .LBB0_25
; %bb.11:                               ; %.critedge.i44.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v5, v10
	s_mov_b32 s12, 0
	s_mov_b32 s13, s3
.LBB0_12:                               ; %.critedge.i44
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s14, s13, s14
	s_xor_b32 s14, s14, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s15, s14
	s_xor_b32 s14, exec_lo, s15
	s_cbranch_execz .LBB0_18
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=2
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_mov_b32 s15, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[11:12], off
	global_load_b32 v6, v[13:14], off
	s_waitcnt vmcnt(0)
	v_cmpx_ge_i32_e64 v4, v6
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_12 Depth=2
	v_add_nc_u32_e32 v5, 1, v5
	global_store_b32 v[1:2], v6, off
                                        ; implicit-def: $vgpr4
.LBB0_15:                               ; %Flow111
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_12 Depth=2
	v_add_nc_u32_e32 v3, 1, v3
	global_store_b32 v[1:2], v4, off
.LBB0_17:                               ; %Flow112
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_18:                               ; %Flow115
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_and_not1_saveexec_b32 s14, s14
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_12 Depth=2
	s_xor_b32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s15, s13
	s_xor_b32 s13, exec_lo, s15
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_12 Depth=2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v3
	v_add_co_u32 v11, vcc_lo, s8, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	global_load_b32 v4, v[11:12], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v4, off
.LBB0_21:                               ; %Flow113
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_and_not1_saveexec_b32 s13, s13
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_12 Depth=2
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	v_add_nc_u32_e32 v5, 1, v5
	v_add_co_u32 v11, vcc_lo, s8, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	global_load_b32 v4, v[11:12], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v4, off
.LBB0_23:                               ; %Flow114
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_24:                               ;   in Loop: Header=BB0_12 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s14
	v_cmp_ge_i32_e64 s13, v3, v10
	v_cmp_lt_i32_e64 s14, 0xf423f, v5
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_and_b32 s15, s13, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s15, exec_lo, s15
	s_or_b32 s12, s15, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_12
.LBB0_25:                               ; %Flow117
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_26:                               ; %Flow119
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_27:                               ; %Flow127
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_44
; %bb.28:                               ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v4, -1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v4, v3
	v_ashrrev_i32_e32 v11, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s12, v3, v11
	v_cmp_ge_i32_e64 s13, v11, v4
	s_and_b32 s6, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s6, -1
	s_and_saveexec_b32 s6, s7
	s_cbranch_execz .LBB0_43
; %bb.29:                               ; %.critedge.preheader.i
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v5, 1, v11
	s_mov_b32 s7, 0
.LBB0_30:                               ; %.critedge.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_or_b32 s13, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s13, s13, -1
	s_and_saveexec_b32 s14, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s14
	s_cbranch_execz .LBB0_36
; %bb.31:                               ;   in Loop: Header=BB0_30 Depth=2
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[12:13], off
	global_load_b32 v6, v[14:15], off
	s_waitcnt vmcnt(0)
	v_cmpx_ge_i32_e64 v4, v6
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_30 Depth=2
	v_add_nc_u32_e32 v5, 1, v5
	global_store_b32 v[1:2], v6, off
                                        ; implicit-def: $vgpr4
.LBB0_33:                               ; %Flow120
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_and_not1_saveexec_b32 s14, s14
	s_cbranch_execz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_30 Depth=2
	v_add_nc_u32_e32 v3, 1, v3
	global_store_b32 v[1:2], v4, off
.LBB0_35:                               ; %Flow121
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_36:                               ; %Flow124
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_and_not1_saveexec_b32 s13, s13
	s_cbranch_execz .LBB0_42
; %bb.37:                               ;   in Loop: Header=BB0_30 Depth=2
	s_xor_b32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s12
	s_xor_b32 s12, exec_lo, s14
	s_cbranch_execz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_30 Depth=2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v3
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_load_b32 v4, v[12:13], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v4, off
.LBB0_39:                               ; %Flow122
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_and_not1_saveexec_b32 s12, s12
	s_cbranch_execz .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_30 Depth=2
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[5:6]
	v_add_nc_u32_e32 v5, 1, v5
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_load_b32 v4, v[12:13], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v4, off
.LBB0_41:                               ; %Flow123
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_42:                               ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s13
	v_cmp_gt_i32_e64 s12, v3, v11
	v_cmp_ge_i32_e64 s13, v5, v10
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_and_b32 s14, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s14, exec_lo, s14
	s_or_b32 s7, s14, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_30
.LBB0_43:                               ; %Flow126
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_44:                               ; %_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v7, 1, v7
	v_add_nc_u32_e32 v9, s4, v9
	v_add_nc_u32_e32 v0, s4, v0
	v_cmp_ge_i32_e32 vcc_lo, v7, v8
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_3
.LBB0_45:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13process_layerPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13process_layerPiS_iii, .Lfunc_end0-_Z13process_layerPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1324
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18process_last_layerPiS_i ; -- Begin function _Z18process_last_layerPiS_i
	.globl	_Z18process_last_layerPiS_i
	.p2align	8
	.type	_Z18process_last_layerPiS_i,@function
_Z18process_last_layerPiS_i:            ; @_Z18process_last_layerPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s4, 1
	s_mov_b32 s4, 0
	s_cmp_lt_i32 s8, 1
	s_mov_b32 s6, s8
	s_cselect_b32 s9, -1, 0
	s_cmp_gt_i32 s8, 0xf423f
	s_cselect_b32 s10, -1, 0
.LBB1_1:                                ; %.critedge.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s9, s10
	s_mov_b32 s10, -1
	s_and_b32 vcc_lo, exec_lo, s5
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr5
	s_cbranch_vccnz .LBB1_7
; %bb.2:                                ;   in Loop: Header=BB1_1 Depth=1
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[4:5], 2
	s_mov_b32 s5, -1
	s_add_u32 s10, s0, s10
	s_addc_u32 s11, s1, s11
	s_ashr_i32 s7, s6, 31
	s_lshl_b64 s[12:13], s[6:7], 2
                                        ; implicit-def: $sgpr7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s0, s12
	s_addc_u32 s13, s1, s13
	s_clause 0x1
	global_load_b32 v1, v0, s[10:11]
	global_load_b32 v2, v0, s[12:13]
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v1, v2
	s_cbranch_vccz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s7, s6, 1
	s_mov_b32 s5, 0
	global_store_b32 v0, v2, s[2:3]
.LBB1_4:                                ; %Flow
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_mov_b32 s5, s4
	s_cbranch_vccnz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s5, s4, 1
	s_mov_b32 s7, s6
	global_store_b32 v0, v1, s[2:3]
.LBB1_6:                                ; %Flow15
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s10, 0
.LBB1_7:                                ; %Flow18
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_13
; %bb.8:                                ;   in Loop: Header=BB1_1 Depth=1
	s_xor_b32 s5, s9, -1
	s_mov_b32 s7, -1
	s_and_not1_b32 vcc_lo, exec_lo, s5
                                        ; implicit-def: $sgpr5
	s_cbranch_vccnz .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_1 Depth=1
	s_ashr_i32 s5, s4, 31
	s_mov_b32 s7, 0
	s_lshl_b64 s[10:11], s[4:5], 2
	s_add_i32 s5, s4, 1
	s_add_u32 s10, s0, s10
	s_addc_u32 s11, s1, s11
	global_load_b32 v1, v0, s[10:11]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v1, s[2:3]
.LBB1_10:                               ; %Flow16
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_1 Depth=1
	s_ashr_i32 s7, s6, 31
	s_add_i32 s5, s6, 1
	s_lshl_b64 s[10:11], s[6:7], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s0, s10
	s_addc_u32 s7, s1, s11
	global_load_b32 v1, v0, s[6:7]
	s_mov_b32 s6, s5
	s_mov_b32 s5, s4
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v1, s[2:3]
.LBB1_12:                               ; %Flow17
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_mov_b32 s7, s6
.LBB1_13:                               ;   in Loop: Header=BB1_1 Depth=1
	s_cmp_ge_i32 s5, s8
	s_mov_b32 s6, s7
	s_cselect_b32 s9, -1, 0
	s_cmp_gt_i32 s7, 0xf423f
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s9, s10
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_mov_b32 s4, s5
	s_cbranch_vccnz .LBB1_1
; %bb.14:                               ; %_Z26sort_2_preordered_segmentsRKiS0_S0_PiS1_.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18process_last_layerPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 14
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18process_last_layerPiS_i, .Lfunc_end1-_Z18process_last_layerPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 16
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13process_layerPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13process_layerPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18process_last_layerPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z18process_last_layerPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
