#include"stdio.h"
#include"time.h"
__global__ void gpu_1(float *da1,float *db1,float *dc1,int n)
{
	for(int i=0;i<n;i++)
	{
		//dc1[i]=db1[i]+da1[i];
		dc1[i]=db1[i]*da1[i];
		
		
	}
	
}
__global__ void gpu_2(float *da1,float *db1,float *dc1,int n)
{
	int tid=threadIdx.x;
	const int t_n=blockDim.x;
	printf("%d\n",t_n);
	while(tid<n)
	{
		//dc1[tid]=db1[tid]+da1[tid];
		dc1[tid]=db1[tid]*da1[tid];
		
		tid+=t_n;
	}
	
}
__global__ void gpu_3(float *da1,float *db1,float *dc1,int n)
{
	const int tidx=threadIdx.x;//当前线程的编号
	const int bidx=blockIdx.x;//当前block的个数
	const int t_n=gridDim.x*blockDim.x;//总block的个数乘总维度
	int tid=bidx*blockDim.x+tidx;	
	//printf("%d\n",t_n);
	while(tid<n)
	{
		//dc1[tid]=db1[tid]+da1[tid];
		dc1[tid]=db1[tid]*da1[tid];
		
		tid+=t_n;
	}
	
}
int main()
{
	const int arrsize=99999;
  	const int ARRAY_BYTES = arrsize * sizeof(float);
	float a[arrsize];
	float b[arrsize];
	float c[arrsize];
	for(int i=0;i<arrsize;i++)
	{
		b[i]=(float)(i+1);
		a[i]=(float)(i+1);
	}
clock_t start,end;
clock_t start_gpu1,end_gpu1;
start=clock();
for(int i=0;i<arrsize;i++)
	{
		//c[i]=b[i]+a[i];
		c[i]=b[i]*a[i];
		
		
	}
end=clock();
double during=(double)(end-start)/CLOCKS_PER_SEC;
printf("耗时%f秒\n",during);
printf("%f\n",c[0]);
/***********************************gpu单block单thread**************************************/
	float *da;
	float *db;
	float *dc;
	float ga1[arrsize];
	float gb1[arrsize];
	float gc1[arrsize];
	for(int i=0;i<arrsize;i++)
	{
		gb1[i]=(float)(i+1);
		ga1[i]=(float)(i+1);
	}
	cudaMalloc((void**) &da,ARRAY_BYTES);
	cudaMalloc((void**) &db,ARRAY_BYTES);
	cudaMalloc((void**) &dc,ARRAY_BYTES);
	cudaMemcpy(da,ga1,ARRAY_BYTES,cudaMemcpyHostToDevice);
	cudaMemcpy(db,gb1,ARRAY_BYTES,cudaMemcpyHostToDevice);
	start_gpu1=clock();
	//gpu_1<<<1,1>>>(da,db,dc,arrsize);
/***********************************gpu单block多thread**************************************/
	gpu_2<<<1,1024>>>(da,db,dc,arrsize);
/***********************************gpu多block多thread**************************************/
	//gpu_3<<<5000,1024>>>(da,db,dc,arrsize);
	end_gpu1=clock();
	cudaMemcpy(gc1,dc,ARRAY_BYTES,cudaMemcpyDeviceToHost);
	
double during1=(double)(end_gpu1-start_gpu1)/CLOCKS_PER_SEC;
printf("耗时%f秒\n",during1);
printf("%f\n",gc1[0]);
	cudaFree(da);
	cudaFree(db);
	cudaFree(dc);


}

	.file	"tmpxft_00219631_00000000-6_vec.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z29__device_stub__Z5gpu_1PfS_S_iPfS_S_i
	.type	_Z29__device_stub__Z5gpu_1PfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5gpu_1PfS_S_iPfS_S_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5gpu_1PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z29__device_stub__Z5gpu_1PfS_S_iPfS_S_i, .-_Z29__device_stub__Z5gpu_1PfS_S_iPfS_S_i
	.globl	_Z5gpu_1PfS_S_i
	.type	_Z5gpu_1PfS_S_i, @function
_Z5gpu_1PfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z5gpu_1PfS_S_iPfS_S_i
	.cfi_endproc
.LFE2053:
	.size	_Z5gpu_1PfS_S_i, .-_Z5gpu_1PfS_S_i
	.globl	_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i
	.type	_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5gpu_2PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i, .-_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i
	.globl	_Z5gpu_2PfS_S_i
	.type	_Z5gpu_2PfS_S_i, @function
_Z5gpu_2PfS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z5gpu_2PfS_S_i, .-_Z5gpu_2PfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\350\200\227\346\227\266%f\347\247\222\n"
.LC2:
	.string	"%f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	-2396160(%rsp), %r11
	.cfi_def_cfa 11, 2396200
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$3880, %rsp
	.cfi_def_cfa_offset 2400080
	movq	%fs:40, %rax
	movq	%rax, 2400024(%rsp)
	movl	$1, %eax
	leaq	400044(%rsp), %r12
	leaq	48(%rsp), %rbp
.L14:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, -4(%r12,%rax,4)
	movss	%xmm0, -4(%rbp,%rax,4)
	incq	%rax
	cmpq	$100000, %rax
	jne	.L14
	call	clock@PLT
	xorl	%edx, %edx
	movq	%rax, %rbx
.L15:
	movss	(%r12,%rdx), %xmm0
	mulss	0(%rbp,%rdx), %xmm0
	movss	%xmm0, 800040(%rsp,%rdx)
	addq	$4, %rdx
	cmpq	$399996, %rdx
	jne	.L15
	call	clock@PLT
	leaq	.LC1(%rip), %r12
	movl	$2, %edi
	leaq	.LC2(%rip), %rbp
	subq	%rbx, %rax
	movq	%r12, %rsi
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC0(%rip), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	800040(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$1, %eax
.L16:
	cvtsi2ssl	%eax, %xmm0
	leaq	1600032(%rsp), %rbx
	leaq	1200036(%rsp), %r13
	movss	%xmm0, 1600028(%rsp,%rax,4)
	movss	%xmm0, 1200032(%rsp,%rax,4)
	incq	%rax
	cmpq	$100000, %rax
	jne	.L16
	movq	%rsp, %rdi
	movl	$399996, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$399996, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$399996, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	movl	$399996, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$399996, %edx
	call	cudaMemcpy@PLT
	call	clock@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movq	%rax, %r13
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$99999, %ecx
	movq	(%rsp), %rdi
	call	_Z29__device_stub__Z5gpu_2PfS_S_iPfS_S_i
.L17:
	call	clock@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$399996, %edx
	movq	%rax, %rbx
	leaq	2000028(%rsp), %rdi
	call	cudaMemcpy@PLT
	subq	%r13, %rbx
	movq	%r12, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%rbx, %xmm0
	divsd	.LC0(%rip), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	2000028(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	2400024(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$2400040, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z29__device_stub__Z5gpu_3PfS_S_iPfS_S_i
	.type	_Z29__device_stub__Z5gpu_3PfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5gpu_3PfS_S_iPfS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5gpu_3PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z29__device_stub__Z5gpu_3PfS_S_iPfS_S_i, .-_Z29__device_stub__Z5gpu_3PfS_S_iPfS_S_i
	.globl	_Z5gpu_3PfS_S_i
	.type	_Z5gpu_3PfS_S_i, @function
_Z5gpu_3PfS_S_i:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z5gpu_3PfS_S_iPfS_S_i
	.cfi_endproc
.LFE2057:
	.size	_Z5gpu_3PfS_S_i, .-_Z5gpu_3PfS_S_i
	.section	.rodata.str1.1
.LC3:
	.string	"_Z5gpu_3PfS_S_i"
.LC4:
	.string	"_Z5gpu_2PfS_S_i"
.LC5:
	.string	"_Z5gpu_1PfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5gpu_3PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5gpu_2PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5gpu_1PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include"stdio.h"
#include"time.h"
__global__ void gpu_1(float *da1,float *db1,float *dc1,int n)
{
	for(int i=0;i<n;i++)
	{
		//dc1[i]=db1[i]+da1[i];
		dc1[i]=db1[i]*da1[i];
		
		
	}
	
}
__global__ void gpu_2(float *da1,float *db1,float *dc1,int n)
{
	int tid=threadIdx.x;
	const int t_n=blockDim.x;
	printf("%d\n",t_n);
	while(tid<n)
	{
		//dc1[tid]=db1[tid]+da1[tid];
		dc1[tid]=db1[tid]*da1[tid];
		
		tid+=t_n;
	}
	
}
__global__ void gpu_3(float *da1,float *db1,float *dc1,int n)
{
	const int tidx=threadIdx.x;//当前线程的编号
	const int bidx=blockIdx.x;//当前block的个数
	const int t_n=gridDim.x*blockDim.x;//总block的个数乘总维度
	int tid=bidx*blockDim.x+tidx;	
	//printf("%d\n",t_n);
	while(tid<n)
	{
		//dc1[tid]=db1[tid]+da1[tid];
		dc1[tid]=db1[tid]*da1[tid];
		
		tid+=t_n;
	}
	
}
int main()
{
	const int arrsize=99999;
  	const int ARRAY_BYTES = arrsize * sizeof(float);
	float a[arrsize];
	float b[arrsize];
	float c[arrsize];
	for(int i=0;i<arrsize;i++)
	{
		b[i]=(float)(i+1);
		a[i]=(float)(i+1);
	}
clock_t start,end;
clock_t start_gpu1,end_gpu1;
start=clock();
for(int i=0;i<arrsize;i++)
	{
		//c[i]=b[i]+a[i];
		c[i]=b[i]*a[i];
		
		
	}
end=clock();
double during=(double)(end-start)/CLOCKS_PER_SEC;
printf("耗时%f秒\n",during);
printf("%f\n",c[0]);
/***********************************gpu单block单thread**************************************/
	float *da;
	float *db;
	float *dc;
	float ga1[arrsize];
	float gb1[arrsize];
	float gc1[arrsize];
	for(int i=0;i<arrsize;i++)
	{
		gb1[i]=(float)(i+1);
		ga1[i]=(float)(i+1);
	}
	hipMalloc((void**) &da,ARRAY_BYTES);
	hipMalloc((void**) &db,ARRAY_BYTES);
	hipMalloc((void**) &dc,ARRAY_BYTES);
	hipMemcpy(da,ga1,ARRAY_BYTES,hipMemcpyHostToDevice);
	hipMemcpy(db,gb1,ARRAY_BYTES,hipMemcpyHostToDevice);
	start_gpu1=clock();
	//gpu_1<<<1,1>>>(da,db,dc,arrsize);
/***********************************gpu单block多thread**************************************/
	gpu_2<<<1,1024>>>(da,db,dc,arrsize);
/***********************************gpu多block多thread**************************************/
	//gpu_3<<<5000,1024>>>(da,db,dc,arrsize);
	end_gpu1=clock();
	hipMemcpy(gc1,dc,ARRAY_BYTES,hipMemcpyDeviceToHost);
	
double during1=(double)(end_gpu1-start_gpu1)/CLOCKS_PER_SEC;
printf("耗时%f秒\n",during1);
printf("%f\n",gc1[0]);
	hipFree(da);
	hipFree(db);
	hipFree(dc);


}

	.text
	.file	"vec.hip"
	.globl	_Z20__device_stub__gpu_1PfS_S_i # -- Begin function _Z20__device_stub__gpu_1PfS_S_i
	.type	_Z20__device_stub__gpu_1PfS_S_i,@function
_Z20__device_stub__gpu_1PfS_S_i:        # @_Z20__device_stub__gpu_1PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5gpu_1PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__gpu_1PfS_S_i, .Lfunc_end0-_Z20__device_stub__gpu_1PfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__gpu_2PfS_S_i # -- Begin function _Z20__device_stub__gpu_2PfS_S_i
	.type	_Z20__device_stub__gpu_2PfS_S_i,@function
_Z20__device_stub__gpu_2PfS_S_i:        # @_Z20__device_stub__gpu_2PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5gpu_2PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__gpu_2PfS_S_i, .Lfunc_end1-_Z20__device_stub__gpu_2PfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__gpu_3PfS_S_i # -- Begin function _Z20__device_stub__gpu_3PfS_S_i
	.type	_Z20__device_stub__gpu_3PfS_S_i,@function
_Z20__device_stub__gpu_3PfS_S_i:        # @_Z20__device_stub__gpu_3PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5gpu_3PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__gpu_3PfS_S_i, .Lfunc_end2-_Z20__device_stub__gpu_3PfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$2400032, %rsp                  # imm = 0x249F20
	.cfi_def_cfa_offset 2400064
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%eax, %eax
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%rax), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, 1200032(%rsp,%rax,4)
	movss	%xmm0, 1600032(%rsp,%rax,4)
	movq	%rcx, %rax
	cmpq	$99999, %rcx                    # imm = 0x1869F
	jne	.LBB3_1
# %bb.2:
	xorl	%r14d, %r14d
	callq	clock
	movq	%rax, %rbx
.LBB3_3:                                # =>This Inner Loop Header: Depth=1
	movss	1200032(%rsp,%r14,4), %xmm0     # xmm0 = mem[0],zero,zero,zero
	mulss	1600032(%rsp,%r14,4), %xmm0
	movss	%xmm0, 800032(%rsp,%r14,4)
	incq	%r14
	cmpq	$99999, %r14                    # imm = 0x1869F
	jne	.LBB3_3
# %bb.4:
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	800032(%rsp), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
.LBB3_5:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%rax), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, 32(%rsp,%rax,4)
	movss	%xmm0, 400032(%rsp,%rax,4)
	movq	%rcx, %rax
	cmpq	$99999, %rcx                    # imm = 0x1869F
	jne	.LBB3_5
# %bb.6:
	leaq	24(%rsp), %rbx
	movl	$399996, %esi                   # imm = 0x61A7C
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r14
	movl	$399996, %esi                   # imm = 0x61A7C
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$399996, %esi                   # imm = 0x61A7C
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	400032(%rsp), %rsi
	movl	$399996, %edx                   # imm = 0x61A7C
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	leaq	32(%rsp), %rsi
	movl	$399996, %edx                   # imm = 0x61A7C
	movl	$1, %ecx
	callq	hipMemcpy
	callq	clock
	movq	%rax, %rbx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1023(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$99999, %ecx                    # imm = 0x1869F
	callq	_Z20__device_stub__gpu_2PfS_S_i
.LBB3_8:
	callq	clock
	movq	%rax, %r14
	movq	8(%rsp), %rsi
	leaq	2000032(%rsp), %r15
	movl	$399996, %edx                   # imm = 0x61A7C
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	subq	%rbx, %r14
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r14, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$2400032, %rsp                  # imm = 0x249F20
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5gpu_1PfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5gpu_2PfS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5gpu_3PfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5gpu_1PfS_S_i,@object         # @_Z5gpu_1PfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z5gpu_1PfS_S_i
	.p2align	3, 0x0
_Z5gpu_1PfS_S_i:
	.quad	_Z20__device_stub__gpu_1PfS_S_i
	.size	_Z5gpu_1PfS_S_i, 8

	.type	_Z5gpu_2PfS_S_i,@object         # @_Z5gpu_2PfS_S_i
	.globl	_Z5gpu_2PfS_S_i
	.p2align	3, 0x0
_Z5gpu_2PfS_S_i:
	.quad	_Z20__device_stub__gpu_2PfS_S_i
	.size	_Z5gpu_2PfS_S_i, 8

	.type	_Z5gpu_3PfS_S_i,@object         # @_Z5gpu_3PfS_S_i
	.globl	_Z5gpu_3PfS_S_i
	.p2align	3, 0x0
_Z5gpu_3PfS_S_i:
	.quad	_Z20__device_stub__gpu_3PfS_S_i
	.size	_Z5gpu_3PfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\350\200\227\346\227\266%f\347\247\222\n"
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%f\n"
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5gpu_1PfS_S_i"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z5gpu_2PfS_S_i"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z5gpu_3PfS_S_i"
	.size	.L__unnamed_3, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__gpu_1PfS_S_i
	.addrsig_sym _Z20__device_stub__gpu_2PfS_S_i
	.addrsig_sym _Z20__device_stub__gpu_3PfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5gpu_1PfS_S_i
	.addrsig_sym _Z5gpu_2PfS_S_i
	.addrsig_sym _Z5gpu_3PfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5gpu_1PfS_S_i         ; -- Begin function _Z5gpu_1PfS_S_i
	.globl	_Z5gpu_1PfS_S_i
	.p2align	8
	.type	_Z5gpu_1PfS_S_i,@function
_Z5gpu_1PfS_S_i:                        ; @_Z5gpu_1PfS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v1, v0, s[6:7]
	global_load_b32 v2, v0, s[4:5]
	s_add_i32 s2, s2, -1
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v1, v1, v2
	global_store_b32 v0, v1, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5gpu_1PfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5gpu_1PfS_S_i, .Lfunc_end0-_Z5gpu_1PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5gpu_2PfS_S_i         ; -- Begin function _Z5gpu_2PfS_S_i
	.globl	_Z5gpu_2PfS_S_i
	.p2align	8
	.type	_Z5gpu_2PfS_S_i,@function
_Z5gpu_2PfS_S_i:                        ; @_Z5gpu_2PfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s16, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x70
	v_mbcnt_lo_u32_b32 v31, -1, 0
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v31
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v5
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_6
; %bb.1:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v1, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[4:5] offset:40
	global_load_b64 v[6:7], v1, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v3, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[7:8], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[9:10]
	s_cbranch_execz .LBB1_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB1_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[4:5] offset:40
	global_load_b64 v[11:12], v1, s[4:5]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v8, v3, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
	v_mov_b32_e32 v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
	v_mov_b32_e32 v7, v3
	global_load_b64 v[7:8], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_3
; %bb.4:                                ; %Flow345
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_5:                                ; %Flow347
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[9:10], v6, s[4:5] offset:40
	global_load_b128 v[1:4], v6, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v9
	v_readfirstlane_b32 s9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, v6
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v1, s11
	v_add_co_ci_u32_e32 v12, vcc_lo, s12, v2, vcc_lo
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, v7
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
	v_dual_mov_b32 v5, 33 :: v_dual_mov_b32 v8, v6
	v_mov_b32_e32 v7, v6
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v14, s15
	v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s14
	s_clause 0x3
	global_store_b128 v[9:10], v[5:8], off
	global_store_b128 v[9:10], v[11:14], off offset:16
	global_store_b128 v[9:10], v[11:14], off offset:32
	global_store_b128 v[9:10], v[11:14], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB1_15
; %bb.9:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s9, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v11, s[4:5] offset:40
	v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s7, v4
	v_and_b32_e32 v3, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v5, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_add_co_u32 v7, vcc_lo, v1, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB1_11
.LBB1_10:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_10
.LBB1_11:                               ; %Flow343
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v6, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v5, s12, 0
	global_load_b64 v[3:4], v6, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB1_13
; %bb.12:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB1_13:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_15
; %bb.14:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_15:                               ; %Flow344
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v1, vcc_lo, v1, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s10, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB1_16:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_16 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB1_18:                               ;   in Loop: Header=BB1_16 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_16 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB1_21
.LBB1_20:                               ;   in Loop: Header=BB1_16 Depth=1
	s_mov_b32 s3, -1
.LBB1_21:                               ; %Flow338
                                        ;   in Loop: Header=BB1_16 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_16
; %bb.22:
	global_load_b64 v[1:2], v[9:10], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_26
; %bb.23:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[4:5] offset:40
	global_load_b64 v[10:11], v9, s[4:5] offset:24 glc
	global_load_b64 v[7:8], v9, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_26
; %bb.24:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s2, 0
.LBB1_25:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_25
.LBB1_26:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB1_112
; %bb.27:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v7, 2 :: v_dual_and_b32 v32, 2, v1
	v_dual_mov_b32 v30, 0 :: v_dual_and_b32 v3, -3, v1
	v_mov_b32_e32 v4, v2
	v_mov_b32_e32 v8, 1
	s_mov_b64 s[8:9], 4
.LBB1_28:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_31 Depth 2
                                        ;     Child Loop BB1_38 Depth 2
                                        ;     Child Loop BB1_46 Depth 2
                                        ;     Child Loop BB1_54 Depth 2
                                        ;     Child Loop BB1_62 Depth 2
                                        ;     Child Loop BB1_70 Depth 2
                                        ;     Child Loop BB1_78 Depth 2
                                        ;     Child Loop BB1_86 Depth 2
                                        ;     Child Loop BB1_94 Depth 2
                                        ;     Child Loop BB1_100 Depth 2
                                        ;     Child Loop BB1_109 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s2, s[8:9], 56
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr18
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_mov_b32 s2, -1
	s_cbranch_scc1 .LBB1_33
; %bb.29:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB1_32
; %bb.30:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_lshl_b64 s[2:3], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[6:7]
.LBB1_31:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v5, v30, s[14:15]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s2, s12
	v_or_b32_e32 v11, v5, v11
	v_or_b32_e32 v12, v6, v12
	s_cbranch_scc1 .LBB1_31
.LBB1_32:                               ; %Flow314
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s18, 0
.LBB1_33:                               ; %Flow316
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b64 s[2:3], s[6:7]
	s_cbranch_vccnz .LBB1_35
; %bb.34:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[11:12], v30, s[6:7]
	s_add_i32 s18, s10, -8
	s_add_u32 s2, s6, 8
	s_addc_u32 s3, s7, 0
.LBB1_35:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB1_40
; %bb.36:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB1_39
; %bb.37:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_38:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s14
	s_addc_u32 s21, s3, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v5, v30, s[20:21]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s18, s14
	v_or_b32_e32 v13, v5, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v6, v14
	s_cbranch_scc1 .LBB1_38
.LBB1_39:                               ; %Flow309
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB1_41
.LBB1_40:                               ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr17
.LBB1_41:                               ; %Flow311
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_43
; %bb.42:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[13:14], v30, s[2:3]
	s_add_i32 s17, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB1_43:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB1_48
; %bb.44:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB1_47
; %bb.45:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_46:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s2, s14
	s_addc_u32 s19, s3, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v5, v30, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v15, v5, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v6, v16
	s_cbranch_scc1 .LBB1_46
.LBB1_47:                               ; %Flow304
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s18, 0
	s_branch .LBB1_49
.LBB1_48:                               ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr18
.LBB1_49:                               ; %Flow306
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_51
; %bb.50:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[15:16], v30, s[2:3]
	s_add_i32 s18, s17, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB1_51:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB1_56
; %bb.52:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB1_55
; %bb.53:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_54:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s14
	s_addc_u32 s21, s3, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v5, v30, s[20:21]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s18, s14
	v_or_b32_e32 v17, v5, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v6, v18
	s_cbranch_scc1 .LBB1_54
.LBB1_55:                               ; %Flow299
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB1_57
.LBB1_56:                               ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr17
.LBB1_57:                               ; %Flow301
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_59
; %bb.58:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[17:18], v30, s[2:3]
	s_add_i32 s17, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB1_59:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB1_64
; %bb.60:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB1_63
; %bb.61:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_62:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s2, s14
	s_addc_u32 s19, s3, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v5, v30, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v19, v5, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v6, v20
	s_cbranch_scc1 .LBB1_62
.LBB1_63:                               ; %Flow294
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s18, 0
	s_branch .LBB1_65
.LBB1_64:                               ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr18
.LBB1_65:                               ; %Flow296
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_67
; %bb.66:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[19:20], v30, s[2:3]
	s_add_i32 s18, s17, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB1_67:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB1_72
; %bb.68:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB1_71
; %bb.69:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_70:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s14
	s_addc_u32 s21, s3, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v5, v30, s[20:21]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s18, s14
	v_or_b32_e32 v21, v5, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v6, v22
	s_cbranch_scc1 .LBB1_70
.LBB1_71:                               ; %Flow289
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB1_73
.LBB1_72:                               ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr17
.LBB1_73:                               ; %Flow291
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_75
; %bb.74:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[21:22], v30, s[2:3]
	s_add_i32 s17, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB1_75:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB1_80
; %bb.76:                               ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB1_79
; %bb.77:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[2:3]
.LBB1_78:                               ; %.preheader.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v5, v30, s[14:15]
	s_add_i32 s17, s17, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s12, v[29:30]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s17, 0
	v_or_b32_e32 v23, v5, v23
	v_or_b32_e32 v24, v6, v24
	s_cbranch_scc1 .LBB1_78
.LBB1_79:                               ; %Flow284
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB1_81
.LBB1_80:                               ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s12, -1
.LBB1_81:                               ; %Flow286
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_83
; %bb.82:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[23:24], v30, s[2:3]
.LBB1_83:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	v_mov_b32_e32 v29, v31
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v29
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_89
; %bb.84:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[27:28], v30, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v30, s[4:5] offset:40
	global_load_b64 v[9:10], v30, s[4:5]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v6, v6, v28
	v_and_b32_e32 v5, v5, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v25, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v25, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[25:26], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v30, v[25:28], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[27:28]
	s_cbranch_execz .LBB1_88
; %bb.85:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s13, 0
.LBB1_86:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[4:5] offset:40
	global_load_b64 v[25:26], v30, s[4:5]
	v_dual_mov_b32 v28, v6 :: v_dual_mov_b32 v27, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[25:26]
	v_and_b32_e32 v25, v10, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[6:7]
	v_mov_b32_e32 v6, v9
	global_load_b64 v[25:26], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v30, v[25:28], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[27:28]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_86
; %bb.87:                               ; %Flow279
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_88:                               ; %Flow281
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB1_89:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[4:5] offset:40
	global_load_b128 v[25:28], v30, s[4:5]
	v_readfirstlane_b32 s12, v5
	v_readfirstlane_b32 s13, v6
	s_mov_b32 s19, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v9
	v_readfirstlane_b32 s15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[12:13], s[14:15]
	s_mul_i32 s3, s15, 24
	s_mul_hi_u32 s17, s14, 24
	s_mul_i32 s18, s14, 24
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB1_91
; %bb.90:                               ;   in Loop: Header=BB1_28 Depth=1
	v_dual_mov_b32 v5, s19 :: v_dual_mov_b32 v6, v30
	s_add_i32 s19, s17, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, s18
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v26, vcc_lo
	global_store_b128 v[9:10], v[5:8], off offset:8
.LBB1_91:                               ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v5, 0, v4
	v_or_b32_e32 v6, v3, v32
	s_lshl_b64 s[14:15], s[14:15], 12
	s_lshl_b32 s19, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s19, s19, 28
	v_dual_cndmask_b32 v10, v5, v4 :: v_dual_cndmask_b32 v5, v6, v3
	v_lshlrev_b64 v[3:4], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v27, s14
	v_add_co_ci_u32_e32 v28, vcc_lo, s15, v28, vcc_lo
	s_and_b32 s19, s19, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v27, vcc_lo, v6, v3
	v_and_or_b32 v9, 0xffffff1f, v5, s19
	v_add_co_ci_u32_e32 v28, vcc_lo, v28, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[27:28], v[9:12], off
	global_store_b128 v[27:28], v[13:16], off offset:16
	global_store_b128 v[27:28], v[17:20], off offset:32
	global_store_b128 v[27:28], v[21:24], off offset:48
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB1_99
; %bb.92:                               ;   in Loop: Header=BB1_28 Depth=1
	s_clause 0x1
	global_load_b64 v[13:14], v30, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v30, s[4:5] offset:40
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[12:13]
	s_mul_i32 s15, s21, 24
	s_mul_hi_u32 s19, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s19, s19, s15
	v_add_co_u32 v9, vcc_lo, v25, s20
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v26, vcc_lo
	s_mov_b32 s15, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v30, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB1_95
; %bb.93:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s19, 0
.LBB1_94:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s12 :: v_dual_mov_b32 v4, s13
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v30, v[3:6], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s19, vcc_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB1_94
.LBB1_95:                               ; %Flow277
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	global_load_b64 v[3:4], v30, s[4:5] offset:16
	s_mov_b32 s19, exec_lo
	s_mov_b32 s15, exec_lo
	v_mbcnt_lo_u32_b32 v5, s19, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB1_97
; %bb.96:                               ;   in Loop: Header=BB1_28 Depth=1
	s_bcnt1_i32_b32 s19, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s19
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[29:30], off offset:8
.LBB1_97:                               ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_99
; %bb.98:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b32 v29, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s15, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[29:30], off
	s_and_b32 m0, s15, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_99:                               ; %Flow278
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s17, s17, s3
	v_add_co_u32 v3, vcc_lo, v25, s18
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_100:                              ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_102
; %bb.101:                              ;   in Loop: Header=BB1_100 Depth=2
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB1_102:                              ;   in Loop: Header=BB1_100 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v5
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_104
; %bb.103:                              ;   in Loop: Header=BB1_100 Depth=2
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB1_105
.LBB1_104:                              ;   in Loop: Header=BB1_100 Depth=2
	s_mov_b32 s3, -1
.LBB1_105:                              ; %Flow272
                                        ;   in Loop: Header=BB1_100 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_100
; %bb.106:                              ;   in Loop: Header=BB1_28 Depth=1
	global_load_b128 v[3:6], v[27:28], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_110
; %bb.107:                              ;   in Loop: Header=BB1_28 Depth=1
	s_clause 0x2
	global_load_b64 v[5:6], v30, s[4:5] offset:40
	global_load_b64 v[13:14], v30, s[4:5] offset:24 glc
	global_load_b64 v[11:12], v30, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v15, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
	v_and_b32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v9, v5
	v_mul_hi_u32 v15, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, vcc_lo, v11, v5
	v_mov_b32_e32 v11, v13
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v6, v15, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[5:6], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v30, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_110
; %bb.108:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s2, 0
.LBB1_109:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[5:6], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v30, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_109
.LBB1_110:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB1_28
; %bb.111:                              ; %Flow317
	s_mov_b32 s2, 0
	s_branch .LBB1_113
.LBB1_112:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr3_vgpr4
.LBB1_113:                              ; %Flow332
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB1_142
; %bb.114:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v3, v31
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v3
	v_cmp_eq_u32_e64 s2, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_120
; %bb.115:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[7:8], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v11, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[7:8]
	s_cbranch_execz .LBB1_119
; %bb.116:                              ; %.preheader3.i.i.i18.preheader
	s_mov_b32 s7, 0
.LBB1_117:                              ; %.preheader3.i.i.i18
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[11:12], v4, s[4:5]
	v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
	global_load_b64 v[5:6], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_117
; %bb.118:                              ; %Flow329
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_119:                              ; %Flow331
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_120:                              ; %.loopexit4.i.i.i13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[4:5] offset:40
	global_load_b128 v[5:8], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v11
	v_readfirstlane_b32 s9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB1_122
; %bb.121:
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, v4
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v5, s11
	v_add_co_ci_u32_e32 v14, vcc_lo, s12, v6, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB1_122:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[9:10], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v9
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v1, 0xffffff1f, v1, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
	v_mov_b32_e32 v3, v4
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v12, s15
	v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
	s_clause 0x3
	global_store_b128 v[7:8], v[1:4], off
	global_store_b128 v[7:8], v[9:12], off offset:16
	global_store_b128 v[7:8], v[9:12], off offset:32
	global_store_b128 v[7:8], v[9:12], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB1_130
; %bb.123:
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s6
	v_mov_b32_e32 v13, s7
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[4:5] offset:32 glc
	global_load_b64 v[1:2], v11, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v1
	v_readfirstlane_b32 s13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v9, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v6, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB1_126
; %bb.124:                              ; %.preheader1.i.i.i16.preheader
	s_mov_b32 s12, 0
.LBB1_125:                              ; %.preheader1.i.i.i16
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7
	s_sleep 1
	global_store_b64 v[9:10], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[1:2], v11, v[1:4], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_125
.LBB1_126:                              ; %Flow327
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v4, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v3, s12, 0
	global_load_b64 v[1:2], v4, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_128
; %bb.127:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB1_128:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB1_130
; %bb.129:
	global_load_b32 v1, v[1:2], off offset:24
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[1:2], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_130:                              ; %Flow328
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v1, vcc_lo, v5, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s10, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB1_131:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_133
; %bb.132:                              ;   in Loop: Header=BB1_131 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB1_133:                              ;   in Loop: Header=BB1_131 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_135
; %bb.134:                              ;   in Loop: Header=BB1_131 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB1_136
.LBB1_135:                              ;   in Loop: Header=BB1_131 Depth=1
	s_mov_b32 s3, -1
.LBB1_136:                              ; %Flow322
                                        ;   in Loop: Header=BB1_131 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_131
; %bb.137:
	global_load_b128 v[3:6], v[7:8], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_141
; %bb.138:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[1:2], v9, s[4:5] offset:40
	global_load_b64 v[10:11], v9, s[4:5] offset:24 glc
	global_load_b64 v[7:8], v9, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v5, v5, v12
	v_and_b32_e32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v5, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v7, v1
	v_mov_b32_e32 v7, v10
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_mov_b32_e32 v8, v11
	global_store_b64 v[1:2], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v9, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[7:8], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_141
; %bb.139:                              ; %.preheader.i.i.i15.preheader
	s_mov_b32 s2, 0
.LBB1_140:                              ; %.preheader.i.i.i15
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[7:8]
	v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_140
.LBB1_141:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_142:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, v31
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v5
	v_cmp_eq_u32_e64 s2, s2, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_148
; %bb.143:
	v_mov_b32_e32 v6, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[9:10], v6, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v6, s[4:5] offset:40
	global_load_b64 v[7:8], v6, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v9
	v_and_b32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v11, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v7, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	global_load_b64 v[7:8], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v6, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[9:10]
	s_cbranch_execz .LBB1_147
; %bb.144:                              ; %.preheader3.i.i.i25.preheader
	s_mov_b32 s7, 0
.LBB1_145:                              ; %.preheader3.i.i.i25
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[4:5] offset:40
	global_load_b64 v[11:12], v6, s[4:5]
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[2:3]
	v_mov_b32_e32 v2, v7
	global_load_b64 v[7:8], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v6, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[9:10]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_145
; %bb.146:                              ; %Flow265
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_147:                              ; %Flow267
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_148:                              ; %.loopexit4.i.i.i19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v6, s[4:5] offset:40
	global_load_b128 v[7:10], v6, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v11
	v_readfirstlane_b32 s9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB1_150
; %bb.149:
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, v6
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v7, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v8, vcc_lo
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[1:2], v[11:14], off offset:8
.LBB1_150:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[1:2], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v10, vcc_lo
	s_mov_b32 s12, 0
	s_and_b32 s8, 0xffff, s16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v3, 0xffffff1d, v3, 34
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	v_mov_b32_e32 v5, s8
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v12, s15
	v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
	s_clause 0x3
	global_store_b128 v[1:2], v[3:6], off
	global_store_b128 v[1:2], v[9:12], off offset:16
	global_store_b128 v[1:2], v[9:12], off offset:32
	global_store_b128 v[1:2], v[9:12], off offset:48
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB1_158
; %bb.151:
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, s6
	v_mov_b32_e32 v11, s7
	s_clause 0x1
	global_load_b64 v[12:13], v9, s[4:5] offset:32 glc
	global_load_b64 v[1:2], v9, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v1
	v_readfirstlane_b32 s13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s13, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s14, s14, s13
	v_add_co_u32 v5, vcc_lo, v7, s12
	v_add_co_ci_u32_e32 v6, vcc_lo, s14, v8, vcc_lo
	s_mov_b32 s12, exec_lo
	global_store_b64 v[5:6], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v9, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB1_154
; %bb.152:                              ; %.preheader1.i.i.i23.preheader
	s_mov_b32 s13, 0
.LBB1_153:                              ; %.preheader1.i.i.i23
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7
	s_sleep 1
	global_store_b64 v[5:6], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[1:2], v9, v[1:4], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_153
.LBB1_154:                              ; %Flow263
	s_or_b32 exec_lo, exec_lo, s12
	v_mov_b32_e32 v4, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s12, exec_lo
	v_mbcnt_lo_u32_b32 v3, s13, 0
	global_load_b64 v[1:2], v4, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_156
; %bb.155:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB1_156:
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB1_158
; %bb.157:
	global_load_b32 v1, v[1:2], off offset:24
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[1:2], off
	s_and_b32 m0, s12, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_158:                              ; %Flow264
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s10, s10, s3
	v_add_co_u32 v1, vcc_lo, v7, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB1_159:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_161
; %bb.160:                              ;   in Loop: Header=BB1_159 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB1_161:                              ;   in Loop: Header=BB1_159 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_163
; %bb.162:                              ;   in Loop: Header=BB1_159 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB1_164
.LBB1_163:                              ;   in Loop: Header=BB1_159 Depth=1
	s_mov_b32 s3, -1
.LBB1_164:                              ; %Flow258
                                        ;   in Loop: Header=BB1_159 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_159
; %bb.165:
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_169
; %bb.166:
	v_mov_b32_e32 v7, 0
	s_clause 0x2
	global_load_b64 v[3:4], v7, s[4:5] offset:40
	global_load_b64 v[8:9], v7, s[4:5] offset:24 glc
	global_load_b64 v[5:6], v7, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, v2, v11 :: v_dual_cndmask_b32 v1, v1, v10
	v_and_b32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v1, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v3
	v_mov_b32_e32 v3, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v4, v9
	global_store_b64 v[5:6], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v7, v[1:4], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_169
; %bb.167:                              ; %.preheader.i.i.i22.preheader
	s_mov_b32 s2, 0
.LBB1_168:                              ; %.preheader.i.i.i22
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[5:6], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[1:4], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[3:4]
	v_dual_mov_b32 v3, v8 :: v_dual_mov_b32 v4, v9
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_168
.LBB1_169:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s9, s[0:1], 0x18
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s9, v0
	s_cbranch_execz .LBB1_172
; %bb.170:                              ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
	s_mov_b32 s1, 0
	s_lshl_b32 s10, s8, 2
.LBB1_171:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v7, v[3:4], off
	global_load_b32 v5, v[5:6], off
	v_add_nc_u32_e32 v0, s8, v0
	v_add_co_u32 v3, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, s10
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v7, v5
	v_cmp_le_i32_e64 s0, s9, v0
	global_store_b32 v[3:4], v5, off
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_171
.LBB1_172:                              ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5gpu_2PfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5gpu_2PfS_S_i, .Lfunc_end1-_Z5gpu_2PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6872
; NumSgprs: 24
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5gpu_3PfS_S_i         ; -- Begin function _Z5gpu_3PfS_S_i
	.globl	_Z5gpu_3PfS_S_i
	.p2align	8
	.type	_Z5gpu_3PfS_S_i,@function
_Z5gpu_3PfS_S_i:                        ; @_Z5gpu_3PfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s12, s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s9, s8
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[8:9], 2
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v0, v[4:5], off
	global_load_b32 v6, v[6:7], off
	v_add_nc_u32_e32 v1, s8, v1
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s10
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v6
	v_cmp_le_i32_e64 s0, s12, v1
	global_store_b32 v[4:5], v0, off
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5gpu_3PfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z5gpu_3PfS_S_i, .Lfunc_end2-_Z5gpu_3PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d\n"
	.size	.str, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5gpu_1PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z5gpu_1PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5gpu_2PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z5gpu_2PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5gpu_3PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5gpu_3PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
