/**
 CUDAで学ぶアルゴリズムとデータ構造
 ステップバイステップでＮ−クイーン問題を最適化
 一般社団法人  共同通信社  情報技術局  鈴木  維一郎(suzuki.iichiro@kyodonews.jp)

 コンパイルと実行
 $ nvcc -O3 CUDA**_N-Queen.cu && ./a.out (-c|-r|-g)
                    -c:cpu 
                    -r cpu再帰 
                    -g GPU 

 ３．バックトラック

 　各列、対角線上にクイーンがあるかどうかのフラグを用意し、途中で制約を満た
 さない事が明らかな場合は、それ以降のパターン生成を行わない。
 　各列、対角線上にクイーンがあるかどうかのフラグを用意することで高速化を図る。
 　これまでは行方向と列方向に重複しない組み合わせを列挙するものですが、王妃
 は斜め方向のコマをとることができるので、どの斜めライン上にも王妃をひとつだ
 けしか配置できない制限を加える事により、深さ優先探索で全ての葉を訪問せず木
 を降りても解がないと判明した時点で木を引き返すということができます。


 実行結果
$ nvcc -O3 CUDA03_N-Queen.cu  && ./a.out -g
３．GPU 非再帰 バックトラック
 N:        Total      Unique      dd:hh:mm:ss.ms
 4:            2               0  00:00:00:00.02
 5:           10               0  00:00:00:00.00
 6:            4               0  00:00:00:00.00
 7:           40               0  00:00:00:00.00
 8:           92               0  00:00:00:00.01
 9:          352               0  00:00:00:00.06
10:          724               0  00:00:00:00.27
11:         2680               0  00:00:00:01.09
12:        14200               0  00:00:00:05.15
*/

#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define THREAD_NUM		96
#define MAX 27
//変数宣言
long Unique=0;      //GPU
int down[2*MAX-1];  //down:flagA 縦 配置フラグ　
int left[2*MAX-1];  //left:flagB 斜め配置フラグ　
int right[2*MAX-1]; //right:flagC 斜め配置フラグ　
long TOTAL=0;       //CPU,CPUR
long UNIQUE=0;      //CPU,CPUR
int aBoard[MAX];
//関数宣言GPU
__global__ void nqueen_cuda(int *d_aBoard,int *d_down,int *d_right,int *d_left,long *d_results,long TOTAL,int row,int size);
void solve_nqueen_cuda(int si,long results[2],int steps);
bool InitCUDA();
//関数宣言CPU
void TimeFormat(clock_t utime,char *form);
void NQueen(int row,int size);
void NQueenR(int row,int size);
//
//
//hh:mm:ss.ms形式に処理時間を出力
void TimeFormat(clock_t utime,char *form){
  int dd,hh,mm;
  float ftime,ss;
  ftime=(float)utime/CLOCKS_PER_SEC;
  mm=(int)ftime/60;
  ss=ftime-(int)(mm*60);
  dd=mm/(24*60);
  mm=mm%(24*60);
  hh=mm/60;
  mm=mm%60;
  if(dd)
    sprintf(form,"%4d %02d:%02d:%05.2f",dd,hh,mm,ss);
  else if(hh)
    sprintf(form,"     %2d:%02d:%05.2f",hh,mm,ss);
  else if(mm)
    sprintf(form,"        %2d:%05.2f",mm,ss);
  else
    sprintf(form,"           %5.2f",ss);
}
//GPUカーネル
__global__
void nqueen_cuda(int *d_aBoard,int *d_down,int *d_right,int *d_left,long *d_results,long TOTAL,int row,int size){
  int sizeE=size-1;
  bool matched;
  while(row>=0){
    matched=false;
    // １回目はaBoard[row]が-1なのでcolを0で初期化
    // ２回目以降はcolを<sizeまで右へシフト
    for(int col=d_aBoard[row]+1;col<size;col++){
      if(d_down[col]==0 && d_right[col-row+sizeE]==0 &&d_left[col+row]==0){ 	//まだ効き筋がない
        if(d_aBoard[row]!=-1){		//Qを配置済み
          //colがaBoard[row]におきかわる
          d_down[d_aBoard[row]] =d_right[d_aBoard[row]-row+sizeE] =d_left[d_aBoard[row]+row]=0;
        }
        d_aBoard[row]=col;				//Qを配置
        d_down[col] =d_right[col-row+sizeE] =d_left[col+row]=1;			//効き筋とする
        matched=true;						//配置した
        break;
      }
    }
    if(matched){								//配置済みなら
      row++;										//次のrowへ
      if(row==size){
        //print(size); //print()でTOTALを++しない
        TOTAL++;
        row--;
      }
    }else{
      if(d_aBoard[row]!=-1){
        int col=d_aBoard[row]; /** col の代用 */
        d_aBoard[row]=-1;
        d_down[col] =d_right[col-row+sizeE] =d_left[col+row]=0;
      }
      row--;										//バックトラック
    }
  }
  d_results[0]=TOTAL;
}
//CUDA実行関数
void solve_nqueen_cuda(int si,long results[2],int steps){
    //メモリ登録
    int *h_aBoard;
    int *h_down;
    int *h_right;
    int *h_left;
    long *h_results;
    cudaMallocHost((void**)&h_aBoard,sizeof(int)*MAX);
    cudaMallocHost((void**)&h_down,sizeof(int)*2*MAX-1);
    cudaMallocHost((void**)&h_right,sizeof(int)*2*MAX-1);
    cudaMallocHost((void**)&h_left,sizeof(int)*2*MAX-1);
    cudaMallocHost((void**)&h_results,sizeof(long)*steps);
    int *d_aBoard;
    int *d_down;
    int *d_right;
    int *d_left;
    long *d_results;
    cudaMalloc((void**)&d_aBoard,sizeof(int)*MAX);
    cudaMalloc((void**)&d_down,sizeof(int)*2*MAX-1);
    cudaMalloc((void**)&d_right,sizeof(int)*2*MAX-1);
    cudaMalloc((void**)&d_left,sizeof(int)*2*MAX-1);
    cudaMalloc((void**)&d_results,sizeof(long)*steps);
    //初期化
    for(int i=0;i<si;i++){
        h_aBoard[i]=-1;
    }
    //host to device
    cudaMemcpy(d_aBoard,h_aBoard,
      sizeof(int)*MAX,cudaMemcpyHostToDevice);
    cudaMemcpy(d_down,h_down,
      sizeof(int)*2*MAX-1,cudaMemcpyHostToDevice);
    cudaMemcpy(d_right,h_right,
      sizeof(int)*2*MAX-1,cudaMemcpyHostToDevice);
    cudaMemcpy(d_left,h_left,
      sizeof(int)*2*MAX-1,cudaMemcpyHostToDevice);
    cudaMemcpy(d_results,h_results,
      sizeof(long)*steps,cudaMemcpyHostToDevice);
    //実行
    nqueen_cuda<<<1,1>>>(d_aBoard,d_down,d_right,d_left,d_results,0,0,si);
    //device to host
    cudaMemcpy(h_results,d_results,
      sizeof(long)*steps,cudaMemcpyDeviceToHost);
    //return用
    results[0]=h_results[0];
    //開放
    cudaFreeHost(h_aBoard);
    cudaFreeHost(h_down);
    cudaFreeHost(h_right);
    cudaFreeHost(h_left);
    cudaFreeHost(h_results);
    cudaFree(d_aBoard);
    cudaFree(d_down);
    cudaFree(d_left);
    cudaFree(d_right);
    cudaFree(d_results);
}
/** CUDA 初期化 **/
bool InitCUDA(){
  int count;
  cudaGetDeviceCount(&count);
  if(count==0){fprintf(stderr,"There is no device.\n");return false;}
  int i;
  for(i=0;i<count;i++){
    cudaDeviceProp prop;
    if(cudaGetDeviceProperties(&prop,i)==cudaSuccess){if(prop.major>=1){break;} }
  }
  if(i==count){
    fprintf(stderr,"There is no device supporting CUDA 1.x.\n");return false;}
  cudaSetDevice(i);
  return true;
}
// CPU 非再帰版 ロジックメソッド
void NQueen(int row,int size){
  int sizeE=size-1;
  bool matched;
  while(row>=0){
    matched=false;
    // １回目はaBoard[row]が-1なのでcolを0で初期化
    // ２回目以降はcolを<sizeまで右へシフト
    for(int col=aBoard[row]+1;col<size;col++){
      if(down[col]==0 && right[col-row+sizeE]==0 &&left[col+row]==0){ 	//まだ効き筋がない
        if(aBoard[row]!=-1){		//Qを配置済み
          //colがaBoard[row]におきかわる
          down[aBoard[row]] =right[aBoard[row]-row+sizeE] =left[aBoard[row]+row]=0;
        }
        aBoard[row]=col;				//Qを配置
        down[col] =right[col-row+sizeE] =left[col+row]=1;			//効き筋とする
        matched=true;						//配置した
        break;
      }
    }
    if(matched){								//配置済みなら
      row++;										//次のrowへ
      if(row==size){
        //print(size); //print()でTOTALを++しない
        TOTAL++;
        row--;
      }
    }else{
      if(aBoard[row]!=-1){
        int col=aBoard[row]; /** col の代用 */
        aBoard[row]=-1;
        down[col] =right[col-row+sizeE] =left[col+row]=0;
      }
      row--;										//バックトラック
    }
  }
}
// CPUR 再帰版 ロジックメソッド
void NQueenR(int row,int size){
  int sizeE=size-1;
  if(row==size){
    TOTAL++;
  }else{
    for(int col=0;col<size;col++){
      aBoard[row]=col;
      if(down[col]==0
          && right[row-col+sizeE]==0
          && left[row+col]==0){
        down[col]
          =right[row-col+sizeE]
          =left[row+col]=1;
        NQueenR(row+1,size);
        down[col]
          =right[row-col+sizeE]
          =left[row+col]=0;
      }
    }
  }
}
//メインメソッド
int main(int argc,char** argv) {
  bool cpu=false,cpur=false,gpu=false,sgpu=false;
  int argstart=1,steps=24576;
  /** パラメータの処理 */
  if(argc>=2&&argv[1][0]=='-'){
    if(argv[1][1]=='c'||argv[1][1]=='C'){cpu=true;}
    else if(argv[1][1]=='r'||argv[1][1]=='R'){cpur=true;}
    else if(argv[1][1]=='g'||argv[1][1]=='G'){gpu=true;}
    else if(argv[1][1]=='s'||argv[1][1]=='S'){sgpu=true;}
    else
      cpur=true;
    argstart=2;
  }
  if(argc<argstart){
    printf("Usage: %s [-c|-g|-r|-s]\n",argv[0]);
    printf("  -c: CPU only\n");
    printf("  -r: CPUR only\n");
    printf("  -g: GPU only\n");
    printf("  -s: SGPU only\n");
    printf("Default CPUR to 8 queen\n");
  }
  /** 出力と実行 */
  if(cpu){
    printf("\n\n３．CPU 非再帰 バックトラック\n");
  }else if(cpur){
    printf("\n\n３．CPUR 再帰 バックトラック\n");
  }else if(gpu){
    printf("\n\n３．GPU 非再帰 バックトラック\n");
  }else if(sgpu){
    printf("\n\n３．SGPU 非再帰 バックトラック\n");
  }
  if(cpu||cpur){
    printf("%s\n"," N:        Total       Unique        hh:mm:ss.ms");
    clock_t st;           //速度計測用
    char t[20];           //hh:mm:ss.msを格納
    int min=4; 
    int targetN=17;
    //aBaord配列を-1で初期化
    for(int i=min;i<=targetN;i++){
      TOTAL=0; UNIQUE=0;
      for(int j=0;j<=targetN;j++){ aBoard[j]=-1; }
      st=clock();
      if(cpu){ NQueen(0,i); }
      if(cpur){ NQueenR(0,i); }
      TimeFormat(clock()-st,t); 
      printf("%2d:%13ld%16ld%s\n",i,TOTAL,UNIQUE,t);
    }
  }
  /** GPU */
  if(gpu||sgpu){
    if(!InitCUDA()){return 0;}
    int min=4;int targetN=18;
    struct timeval t0;struct timeval t1;
    int ss;int ms;int dd;
    long TOTAL;
    long results[2];//結果格納用
    printf("%s\n"," N:        Total      Unique      dd:hh:mm:ss.ms");
    for(int i=min;i<=targetN;i++){
      gettimeofday(&t0,NULL);   // 計測開始
      if(gpu){
        solve_nqueen_cuda(i,results,steps);
        TOTAL=results[0];
        UNIQUE=results[1];
      }
      gettimeofday(&t1,NULL);   // 計測終了
      if (t1.tv_usec<t0.tv_usec) {
        dd=(int)(t1.tv_sec-t0.tv_sec-1)/86400;
        ss=(t1.tv_sec-t0.tv_sec-1)%86400;
        ms=(1000000+t1.tv_usec-t0.tv_usec+500)/10000;
      } else {
        dd=(int)(t1.tv_sec-t0.tv_sec)/86400;
        ss=(t1.tv_sec-t0.tv_sec)%86400;
        ms=(t1.tv_usec-t0.tv_usec+500)/10000;
      }
      int hh=ss/3600;
      int mm=(ss-hh*3600)/60;
      ss%=60;
      printf("%2d:%13ld%16ld%4.2d:%02d:%02d:%02d.%02d\n", i,TOTAL,Unique,dd,hh,mm,ss,ms);
    }
  }
  return 0;
}

	.file	"tmpxft_002525d1_00000000-6_CUDA03_N-Queen.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"%4d %02d:%02d:%05.2f"
.LC2:
	.string	"     %2d:%02d:%05.2f"
.LC3:
	.string	"        %2d:%05.2f"
.LC4:
	.string	"           %5.2f"
	.text
	.globl	_Z10TimeFormatlPc
	.type	_Z10TimeFormatlPc, @function
_Z10TimeFormatlPc:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	movq	%rsi, %rdi
	movl	$60, %esi
	movl	$1440, %r8d
	cvtsi2ssq	%rax, %xmm0
	divss	.LC0(%rip), %xmm0
	cvttss2sil	%xmm0, %eax
	cltd
	idivl	%esi
	cltd
	movl	%eax, %ecx
	idivl	%r8d
	imull	$60, %ecx, %ecx
	cvtsi2ssl	%ecx, %xmm1
	subss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	%eax, %r8d
	movl	%edx, %eax
	cltd
	idivl	%esi
	movl	%edx, %r9d
	testl	%r8d, %r8d
	je	.L3
	subq	$16, %rsp
	.cfi_def_cfa_offset 24
	movl	%eax, %r9d
	movl	$2, %esi
	movb	$1, %al
	pushq	%rdx
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rcx
	orq	$-1, %rdx
	call	__sprintf_chk@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
.L3:
	testl	%eax, %eax
	je	.L5
	movl	%eax, %r8d
	orq	$-1, %rdx
	movl	$2, %esi
	movb	$1, %al
	leaq	.LC2(%rip), %rcx
	jmp	__sprintf_chk@PLT
.L5:
	testl	%edx, %edx
	je	.L6
	movl	%edx, %r8d
	leaq	.LC3(%rip), %rcx
	orq	$-1, %rdx
	movb	$1, %al
	movl	$2, %esi
	jmp	__sprintf_chk@PLT
.L6:
	leaq	.LC4(%rip), %rcx
	orq	$-1, %rdx
	movl	$2, %esi
	movb	$1, %al
	jmp	__sprintf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10TimeFormatlPc, .-_Z10TimeFormatlPc
	.section	.rodata.str1.1
.LC5:
	.string	"There is no device.\n"
.LC6:
	.string	"There is no device supporting CUDA 1.x.\n"
	.text
	.globl	_Z8InitCUDAv
	.type	_Z8InitCUDAv, @function
_Z8InitCUDAv:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$1064, %rsp
	.cfi_def_cfa_offset 1088
	movq	%fs:40, %rax
	movq	%rax, 1048(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
	cmpl	$0, 12(%rsp)
	leaq	.LC5(%rip), %rdx
	je	.L26
	xorl	%ebx, %ebx
	leaq	16(%rsp), %rbp
.L13:
	cmpl	%ebx, 12(%rsp)
	jle	.L17
	movl	%ebx, %esi
	movq	%rbp, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	testl	%eax, %eax
	jne	.L15
	cmpl	$0, 376(%rsp)
	jg	.L17
.L15:
	incl	%ebx
	jmp	.L13
.L17:
	cmpl	%ebx, 12(%rsp)
	jne	.L19
	leaq	.LC6(%rip), %rdx
.L26:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	xorl	%eax, %eax
	jmp	.L12
.L19:
	movl	%ebx, %edi
	call	cudaSetDevice@PLT
	movb	$1, %al
.L12:
	movq	1048(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$1064, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z8InitCUDAv, .-_Z8InitCUDAv
	.globl	_Z6NQueenii
	.type	_Z6NQueenii, @function
_Z6NQueenii:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edi, %eax
	leal	-1(%rsi), %r11d
	leaq	down(%rip), %r8
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	right(%rip), %r9
	leaq	left(%rip), %r10
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	aBoard(%rip), %rbx
.L28:
	testl	%eax, %eax
	js	.L42
	movslq	%eax, %r13
.L37:
	movslq	(%rbx,%r13,4), %rdx
	movl	%r11d, %edi
	subl	%eax, %edi
	leal	1(%rdx), %ecx
	movslq	%ecx, %rcx
.L29:
	cmpl	%ecx, %esi
	jle	.L44
	cmpl	$0, (%r8,%rcx,4)
	jne	.L30
	leal	(%rdi,%rcx), %ebp
	movslq	%ebp, %rbp
	cmpl	$0, (%r9,%rbp,4)
	jne	.L30
	leal	(%rax,%rcx), %r12d
	movslq	%r12d, %r12
	cmpl	$0, (%r10,%r12,4)
	jne	.L30
	cmpl	$-1, %edx
	je	.L31
	leal	(%rdx,%rax), %edi
	movslq	%edi, %rdi
	movl	$0, (%r10,%rdi,4)
	movl	%edx, %edi
	subl	%eax, %edi
	addl	%r11d, %edi
	movslq	%edi, %rdi
	movl	$0, (%r9,%rdi,4)
	xorl	%edi, %edi
	movl	%edi, (%r8,%rdx,4)
.L31:
	movl	%ecx, (%rbx,%r13,4)
	leal	1(%rax), %edx
	movslq	%ecx, %rcx
	movl	$1, (%r10,%r12,4)
	movl	$1, (%r9,%rbp,4)
	movl	$1, (%r8,%rcx,4)
	cmpl	%edx, %esi
	jne	.L33
	incq	TOTAL(%rip)
	jmp	.L37
.L30:
	incq	%rcx
	jmp	.L29
.L44:
	cmpl	$-1, %edx
	je	.L36
	leal	(%rdx,%rax), %ecx
	xorl	%edi, %edi
	xorl	%ebp, %ebp
	movl	$-1, (%rbx,%r13,4)
	movslq	%ecx, %rcx
	movl	%ebp, (%r8,%rdx,4)
	movl	%edi, (%r10,%rcx,4)
	movl	%edx, %ecx
	subl	%eax, %ecx
	addl	%r11d, %ecx
	movslq	%ecx, %rcx
	movl	%ebp, (%r9,%rcx,4)
.L36:
	leal	-1(%rax), %edx
.L33:
	movl	%edx, %eax
	jmp	.L28
.L42:
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z6NQueenii, .-_Z6NQueenii
	.globl	_Z7NQueenRii
	.type	_Z7NQueenRii, @function
_Z7NQueenRii:
.LFB2031:
	.cfi_startproc
	endbr64
	cmpl	%edi, %esi
	je	.L46
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%edi, %rcx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	down(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	jmp	.L47
.L46:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	.cfi_restore 14
	.cfi_restore 15
	incq	TOTAL(%rip)
	ret
.L50:
	.cfi_def_cfa_offset 80
	.cfi_offset 3, -56
	.cfi_offset 6, -48
	.cfi_offset 12, -40
	.cfi_offset 13, -32
	.cfi_offset 14, -24
	.cfi_offset 15, -16
	leaq	aBoard(%rip), %rax
	cmpl	$0, (%r14)
	movl	%r13d, (%rax,%rcx,4)
	je	.L55
.L49:
	incl	%r13d
	addq	$4, %r14
.L47:
	cmpl	%r12d, %r13d
	jl	.L50
	jmp	.L56
.L55:
	leal	-1(%rbx,%r12), %ebp
	leaq	right(%rip), %rax
	subl	%r13d, %ebp
	movslq	%ebp, %rbp
	cmpl	$0, (%rax,%rbp,4)
	jne	.L49
	leal	(%rbx,%r13), %r15d
	leaq	left(%rip), %rdx
	movslq	%r15d, %r15
	cmpl	$0, (%rdx,%r15,4)
	jne	.L49
	movl	$1, (%r14)
	leal	1(%rbx), %edi
	movl	%r12d, %esi
	movq	%rcx, 8(%rsp)
	movl	$1, (%rdx,%r15,4)
	movl	$1, (%rax,%rbp,4)
	call	_Z7NQueenRii
	leaq	left(%rip), %rdx
	xorl	%eax, %eax
	movq	8(%rsp), %rcx
	movl	%eax, (%rdx,%r15,4)
	xorl	%edx, %edx
	leaq	right(%rip), %rax
	movl	%edx, (%rax,%rbp,4)
	movl	%edx, (%r14)
	jmp	.L49
.L56:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z7NQueenRii, .-_Z7NQueenRii
	.globl	_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii
	.type	_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii, @function
_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11nqueen_cudaPiS_S_S_Pllii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L57:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L59
	call	__stack_chk_fail@PLT
.L59:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii, .-_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii
	.globl	_Z11nqueen_cudaPiS_S_S_Pllii
	.type	_Z11nqueen_cudaPiS_S_S_Pllii, @function
_Z11nqueen_cudaPiS_S_S_Pllii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii
	.cfi_endproc
.LFE2058:
	.size	_Z11nqueen_cudaPiS_S_S_Pllii, .-_Z11nqueen_cudaPiS_S_S_Pllii
	.globl	_Z17solve_nqueen_cudaiPli
	.type	_Z17solve_nqueen_cudaiPli, @function
_Z17solve_nqueen_cudaiPli:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rsi, %r12
	movl	$108, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movslq	%edx, %rbx
	salq	$3, %rbx
	subq	$112, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocHost@PLT
	leaq	8(%rsp), %rdi
	movl	$215, %esi
	call	cudaMallocHost@PLT
	leaq	16(%rsp), %rdi
	movl	$215, %esi
	call	cudaMallocHost@PLT
	leaq	24(%rsp), %rdi
	movl	$215, %esi
	call	cudaMallocHost@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMallocHost@PLT
	leaq	40(%rsp), %rdi
	movl	$108, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$215, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$215, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$215, %esi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	xorl	%eax, %eax
.L63:
	cmpl	%eax, %ebp
	jle	.L68
	movl	$-1, (%rsi,%rax,4)
	incq	%rax
	jmp	.L63
.L68:
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movl	$108, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movl	$215, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movl	$215, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movl	$215, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	72(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 100(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 92(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	pushq	%rbp
	.cfi_def_cfa_offset 152
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 160
	movq	88(%rsp), %r8
	movq	80(%rsp), %rcx
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z42__device_stub__Z11nqueen_cudaPiS_S_S_PlliiPiS_S_S_Pllii
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L65:
	movq	72(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rax
	movq	(%rsp), %rdi
	movq	(%rax), %rax
	movq	%rax, (%r12)
	call	cudaFreeHost@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	16(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$112, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z17solve_nqueen_cudaiPli, .-_Z17solve_nqueen_cudaiPli
	.section	.rodata.str1.1
.LC7:
	.string	"Usage: %s [-c|-g|-r|-s]\n"
.LC8:
	.string	"  -c: CPU only\n"
.LC9:
	.string	"  -r: CPUR only\n"
.LC10:
	.string	"  -g: GPU only\n"
.LC11:
	.string	"  -s: SGPU only\n"
.LC12:
	.string	"Default CPUR to 8 queen\n"
.LC13:
	.string	"\n\n\357\274\223\357\274\216CPU \351\235\236\345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257\n"
.LC14:
	.string	"\n\n\357\274\223\357\274\216GPU \351\235\236\345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257\n"
.LC15:
	.string	"\n\n\357\274\223\357\274\216SGPU \351\235\236\345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257\n"
.LC16:
	.string	" N:        Total       Unique        hh:mm:ss.ms"
.LC17:
	.string	"%s\n"
.LC18:
	.string	"%2d:%13ld%16ld%s\n"
.LC19:
	.string	" N:        Total      Unique      dd:hh:mm:ss.ms"
.LC20:
	.string	"%2d:%13ld%16ld%4.2d:%02d:%02d:%02d.%02d\n"
.LC21:
	.string	"\n\n\357\274\223\357\274\216CPUR \345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jle	.L70
	movq	8(%rsi), %rax
	cmpb	$45, (%rax)
	jne	.L78
	movb	1(%rax), %cl
	subl	$67, %ecx
	cmpb	$48, %cl
	ja	.L72
	movabsq	$4294967297, %rdx
	movl	$1, %eax
	salq	%cl, %rax
	testq	%rdx, %rax
	jne	.L92
	movabsq	$68719476752, %rdx
	testq	%rdx, %rax
	jne	.L93
	movabsq	$281474976776192, %rdx
	testq	%rdx, %rax
	je	.L72
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	jmp	.L76
.L70:
	je	.L78
	movq	(%rsi), %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC7(%rip), %rsi
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L78
.L92:
	leaq	.LC13(%rip), %rsi
	xorl	%eax, %eax
	movb	$1, %r13b
	xorl	%r12d, %r12d
	movl	$2, %edi
	call	__printf_chk@PLT
.L75:
	leaq	.LC16(%rip), %rdx
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4, %ebx
	leaq	aBoard(%rip), %r14
.L81:
	xorl	%eax, %eax
	movl	$72, %ecx
	movq	%r14, %rdi
	movq	%rax, TOTAL(%rip)
	movq	%rax, UNIQUE(%rip)
	movb	$-1, %al
	rep stosb
	call	clock@PLT
	movq	%rax, %rbp
	testb	%r13b, %r13b
	je	.L79
	movl	%ebx, %esi
	xorl	%edi, %edi
	call	_Z6NQueenii
.L79:
	testb	%r12b, %r12b
	je	.L80
	movl	%ebx, %esi
	xorl	%edi, %edi
	call	_Z7NQueenRii
.L80:
	call	clock@PLT
	leaq	68(%rsp), %r9
	subq	%rbp, %rax
	movq	%r9, %rsi
	movq	%r9, 8(%rsp)
	movq	%rax, %rdi
	call	_Z10TimeFormatlPc
	movq	8(%rsp), %r9
	movl	%ebx, %edx
	xorl	%eax, %eax
	movq	UNIQUE(%rip), %r8
	movq	TOTAL(%rip), %rcx
	leaq	.LC18(%rip), %rsi
	incl	%ebx
	movl	$2, %edi
	call	__printf_chk@PLT
	cmpl	$18, %ebx
	jne	.L81
.L78:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L90
	call	__stack_chk_fail@PLT
.L93:
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movb	$1, %bpl
	call	__printf_chk@PLT
.L76:
	call	_Z8InitCUDAv
	testb	%al, %al
	je	.L78
	leaq	.LC19(%rip), %rdx
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4, %ebx
	leaq	.LC20(%rip), %r13
.L86:
	xorl	%esi, %esi
	leaq	16(%rsp), %rdi
	call	gettimeofday@PLT
	testb	%bpl, %bpl
	je	.L83
	leaq	48(%rsp), %rsi
	movl	$24576, %edx
	movl	%ebx, %edi
	call	_Z17solve_nqueen_cudaiPli
	movq	56(%rsp), %rax
	movq	48(%rsp), %r12
	movq	%rax, UNIQUE(%rip)
.L83:
	xorl	%esi, %esi
	leaq	32(%rsp), %rdi
	call	gettimeofday@PLT
	movq	40(%rsp), %rcx
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %r8
	cmpq	%rdi, %rcx
	jge	.L84
	leal	-1(%rsi), %eax
	movl	$86400, %r9d
	subq	%r8, %rsi
	subq	%rdi, %rcx
	subl	%r8d, %eax
	movl	$86400, %r8d
	addq	$1000500, %rcx
	cltd
	idivl	%r9d
	movl	%eax, %r9d
	leaq	-1(%rsi), %rax
	cqto
	idivq	%r8
	movl	%edx, %esi
	jmp	.L115
.L84:
	movl	%esi, %eax
	movl	$86400, %r10d
	subq	%rdi, %rcx
	subl	%r8d, %eax
	addq	$500, %rcx
	cltd
	idivl	%r10d
	movl	%eax, %r9d
	movq	%rsi, %rax
	subq	%r8, %rax
	movl	$86400, %r8d
	cqto
	idivq	%r8
	movl	%edx, %esi
.L115:
	movq	%rcx, %rax
	movl	$10000, %edi
	movq	Unique(%rip), %r8
	cqto
	idivq	%rdi
	movl	$3600, %edi
	movq	%rax, %rcx
	movl	%esi, %eax
	cltd
	pushq	%rcx
	.cfi_def_cfa_offset 152
	movl	$60, %ecx
	idivl	%edi
	movl	%eax, %edi
	movl	%esi, %eax
	cltd
	idivl	%ecx
	imull	$-3600, %edi, %eax
	addl	%esi, %eax
	movq	%r13, %rsi
	pushq	%rdx
	.cfi_def_cfa_offset 160
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	movq	%r12, %rcx
	incl	%ebx
	pushq	%rax
	.cfi_def_cfa_offset 168
	xorl	%eax, %eax
	pushq	%rdi
	.cfi_def_cfa_offset 176
	movl	$2, %edi
	call	__printf_chk@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 144
	cmpl	$19, %ebx
	jne	.L86
	jmp	.L78
.L72:
	leaq	.LC21(%rip), %rsi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	movb	$1, %r12b
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L75
.L90:
	addq	$96, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z11nqueen_cudaPiS_S_S_Pllii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11nqueen_cudaPiS_S_S_Pllii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	aBoard
	.bss
	.align 32
	.type	aBoard, @object
	.size	aBoard, 108
aBoard:
	.zero	108
	.globl	UNIQUE
	.align 8
	.type	UNIQUE, @object
	.size	UNIQUE, 8
UNIQUE:
	.zero	8
	.globl	TOTAL
	.align 8
	.type	TOTAL, @object
	.size	TOTAL, 8
TOTAL:
	.zero	8
	.globl	right
	.align 32
	.type	right, @object
	.size	right, 212
right:
	.zero	212
	.globl	left
	.align 32
	.type	left, @object
	.size	left, 212
left:
	.zero	212
	.globl	down
	.align 32
	.type	down, @object
	.size	down, 212
down:
	.zero	212
	.globl	Unique
	.align 8
	.type	Unique, @object
	.size	Unique, 8
Unique:
	.zero	8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 CUDAで学ぶアルゴリズムとデータ構造
 ステップバイステップでＮ−クイーン問題を最適化
 一般社団法人  共同通信社  情報技術局  鈴木  維一郎(suzuki.iichiro@kyodonews.jp)

 コンパイルと実行
 $ nvcc -O3 CUDA**_N-Queen.cu && ./a.out (-c|-r|-g)
                    -c:cpu 
                    -r cpu再帰 
                    -g GPU 

 ３．バックトラック

 　各列、対角線上にクイーンがあるかどうかのフラグを用意し、途中で制約を満た
 さない事が明らかな場合は、それ以降のパターン生成を行わない。
 　各列、対角線上にクイーンがあるかどうかのフラグを用意することで高速化を図る。
 　これまでは行方向と列方向に重複しない組み合わせを列挙するものですが、王妃
 は斜め方向のコマをとることができるので、どの斜めライン上にも王妃をひとつだ
 けしか配置できない制限を加える事により、深さ優先探索で全ての葉を訪問せず木
 を降りても解がないと判明した時点で木を引き返すということができます。


 実行結果
$ nvcc -O3 CUDA03_N-Queen.cu  && ./a.out -g
３．GPU 非再帰 バックトラック
 N:        Total      Unique      dd:hh:mm:ss.ms
 4:            2               0  00:00:00:00.02
 5:           10               0  00:00:00:00.00
 6:            4               0  00:00:00:00.00
 7:           40               0  00:00:00:00.00
 8:           92               0  00:00:00:00.01
 9:          352               0  00:00:00:00.06
10:          724               0  00:00:00:00.27
11:         2680               0  00:00:00:01.09
12:        14200               0  00:00:00:05.15
*/

#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>


#define THREAD_NUM		96
#define MAX 27
//変数宣言
long Unique=0;      //GPU
int down[2*MAX-1];  //down:flagA 縦 配置フラグ　
int left[2*MAX-1];  //left:flagB 斜め配置フラグ　
int right[2*MAX-1]; //right:flagC 斜め配置フラグ　
long TOTAL=0;       //CPU,CPUR
long UNIQUE=0;      //CPU,CPUR
int aBoard[MAX];
//関数宣言GPU
__global__ void nqueen_cuda(int *d_aBoard,int *d_down,int *d_right,int *d_left,long *d_results,long TOTAL,int row,int size);
void solve_nqueen_cuda(int si,long results[2],int steps);
bool InitCUDA();
//関数宣言CPU
void TimeFormat(clock_t utime,char *form);
void NQueen(int row,int size);
void NQueenR(int row,int size);
//
//
//hh:mm:ss.ms形式に処理時間を出力
void TimeFormat(clock_t utime,char *form){
  int dd,hh,mm;
  float ftime,ss;
  ftime=(float)utime/CLOCKS_PER_SEC;
  mm=(int)ftime/60;
  ss=ftime-(int)(mm*60);
  dd=mm/(24*60);
  mm=mm%(24*60);
  hh=mm/60;
  mm=mm%60;
  if(dd)
    sprintf(form,"%4d %02d:%02d:%05.2f",dd,hh,mm,ss);
  else if(hh)
    sprintf(form,"     %2d:%02d:%05.2f",hh,mm,ss);
  else if(mm)
    sprintf(form,"        %2d:%05.2f",mm,ss);
  else
    sprintf(form,"           %5.2f",ss);
}
//GPUカーネル
__global__
void nqueen_cuda(int *d_aBoard,int *d_down,int *d_right,int *d_left,long *d_results,long TOTAL,int row,int size){
  int sizeE=size-1;
  bool matched;
  while(row>=0){
    matched=false;
    // １回目はaBoard[row]が-1なのでcolを0で初期化
    // ２回目以降はcolを<sizeまで右へシフト
    for(int col=d_aBoard[row]+1;col<size;col++){
      if(d_down[col]==0 && d_right[col-row+sizeE]==0 &&d_left[col+row]==0){ 	//まだ効き筋がない
        if(d_aBoard[row]!=-1){		//Qを配置済み
          //colがaBoard[row]におきかわる
          d_down[d_aBoard[row]] =d_right[d_aBoard[row]-row+sizeE] =d_left[d_aBoard[row]+row]=0;
        }
        d_aBoard[row]=col;				//Qを配置
        d_down[col] =d_right[col-row+sizeE] =d_left[col+row]=1;			//効き筋とする
        matched=true;						//配置した
        break;
      }
    }
    if(matched){								//配置済みなら
      row++;										//次のrowへ
      if(row==size){
        //print(size); //print()でTOTALを++しない
        TOTAL++;
        row--;
      }
    }else{
      if(d_aBoard[row]!=-1){
        int col=d_aBoard[row]; /** col の代用 */
        d_aBoard[row]=-1;
        d_down[col] =d_right[col-row+sizeE] =d_left[col+row]=0;
      }
      row--;										//バックトラック
    }
  }
  d_results[0]=TOTAL;
}
//CUDA実行関数
void solve_nqueen_cuda(int si,long results[2],int steps){
    //メモリ登録
    int *h_aBoard;
    int *h_down;
    int *h_right;
    int *h_left;
    long *h_results;
    hipHostMalloc((void**)&h_aBoard,sizeof(int)*MAX, hipHostMallocDefault);
    hipHostMalloc((void**)&h_down,sizeof(int)*2*MAX-1, hipHostMallocDefault);
    hipHostMalloc((void**)&h_right,sizeof(int)*2*MAX-1, hipHostMallocDefault);
    hipHostMalloc((void**)&h_left,sizeof(int)*2*MAX-1, hipHostMallocDefault);
    hipHostMalloc((void**)&h_results,sizeof(long)*steps, hipHostMallocDefault);
    int *d_aBoard;
    int *d_down;
    int *d_right;
    int *d_left;
    long *d_results;
    hipMalloc((void**)&d_aBoard,sizeof(int)*MAX);
    hipMalloc((void**)&d_down,sizeof(int)*2*MAX-1);
    hipMalloc((void**)&d_right,sizeof(int)*2*MAX-1);
    hipMalloc((void**)&d_left,sizeof(int)*2*MAX-1);
    hipMalloc((void**)&d_results,sizeof(long)*steps);
    //初期化
    for(int i=0;i<si;i++){
        h_aBoard[i]=-1;
    }
    //host to device
    hipMemcpy(d_aBoard,h_aBoard,
      sizeof(int)*MAX,hipMemcpyHostToDevice);
    hipMemcpy(d_down,h_down,
      sizeof(int)*2*MAX-1,hipMemcpyHostToDevice);
    hipMemcpy(d_right,h_right,
      sizeof(int)*2*MAX-1,hipMemcpyHostToDevice);
    hipMemcpy(d_left,h_left,
      sizeof(int)*2*MAX-1,hipMemcpyHostToDevice);
    hipMemcpy(d_results,h_results,
      sizeof(long)*steps,hipMemcpyHostToDevice);
    //実行
    nqueen_cuda<<<1,1>>>(d_aBoard,d_down,d_right,d_left,d_results,0,0,si);
    //device to host
    hipMemcpy(h_results,d_results,
      sizeof(long)*steps,hipMemcpyDeviceToHost);
    //return用
    results[0]=h_results[0];
    //開放
    hipHostFree(h_aBoard);
    hipHostFree(h_down);
    hipHostFree(h_right);
    hipHostFree(h_left);
    hipHostFree(h_results);
    hipFree(d_aBoard);
    hipFree(d_down);
    hipFree(d_left);
    hipFree(d_right);
    hipFree(d_results);
}
/** CUDA 初期化 **/
bool InitCUDA(){
  int count;
  hipGetDeviceCount(&count);
  if(count==0){fprintf(stderr,"There is no device.\n");return false;}
  int i;
  for(i=0;i<count;i++){
    hipDeviceProp_t prop;
    if(hipGetDeviceProperties(&prop,i)==hipSuccess){if(prop.major>=1){break;} }
  }
  if(i==count){
    fprintf(stderr,"There is no device supporting CUDA 1.x.\n");return false;}
  hipSetDevice(i);
  return true;
}
// CPU 非再帰版 ロジックメソッド
void NQueen(int row,int size){
  int sizeE=size-1;
  bool matched;
  while(row>=0){
    matched=false;
    // １回目はaBoard[row]が-1なのでcolを0で初期化
    // ２回目以降はcolを<sizeまで右へシフト
    for(int col=aBoard[row]+1;col<size;col++){
      if(down[col]==0 && right[col-row+sizeE]==0 &&left[col+row]==0){ 	//まだ効き筋がない
        if(aBoard[row]!=-1){		//Qを配置済み
          //colがaBoard[row]におきかわる
          down[aBoard[row]] =right[aBoard[row]-row+sizeE] =left[aBoard[row]+row]=0;
        }
        aBoard[row]=col;				//Qを配置
        down[col] =right[col-row+sizeE] =left[col+row]=1;			//効き筋とする
        matched=true;						//配置した
        break;
      }
    }
    if(matched){								//配置済みなら
      row++;										//次のrowへ
      if(row==size){
        //print(size); //print()でTOTALを++しない
        TOTAL++;
        row--;
      }
    }else{
      if(aBoard[row]!=-1){
        int col=aBoard[row]; /** col の代用 */
        aBoard[row]=-1;
        down[col] =right[col-row+sizeE] =left[col+row]=0;
      }
      row--;										//バックトラック
    }
  }
}
// CPUR 再帰版 ロジックメソッド
void NQueenR(int row,int size){
  int sizeE=size-1;
  if(row==size){
    TOTAL++;
  }else{
    for(int col=0;col<size;col++){
      aBoard[row]=col;
      if(down[col]==0
          && right[row-col+sizeE]==0
          && left[row+col]==0){
        down[col]
          =right[row-col+sizeE]
          =left[row+col]=1;
        NQueenR(row+1,size);
        down[col]
          =right[row-col+sizeE]
          =left[row+col]=0;
      }
    }
  }
}
//メインメソッド
int main(int argc,char** argv) {
  bool cpu=false,cpur=false,gpu=false,sgpu=false;
  int argstart=1,steps=24576;
  /** パラメータの処理 */
  if(argc>=2&&argv[1][0]=='-'){
    if(argv[1][1]=='c'||argv[1][1]=='C'){cpu=true;}
    else if(argv[1][1]=='r'||argv[1][1]=='R'){cpur=true;}
    else if(argv[1][1]=='g'||argv[1][1]=='G'){gpu=true;}
    else if(argv[1][1]=='s'||argv[1][1]=='S'){sgpu=true;}
    else
      cpur=true;
    argstart=2;
  }
  if(argc<argstart){
    printf("Usage: %s [-c|-g|-r|-s]\n",argv[0]);
    printf("  -c: CPU only\n");
    printf("  -r: CPUR only\n");
    printf("  -g: GPU only\n");
    printf("  -s: SGPU only\n");
    printf("Default CPUR to 8 queen\n");
  }
  /** 出力と実行 */
  if(cpu){
    printf("\n\n３．CPU 非再帰 バックトラック\n");
  }else if(cpur){
    printf("\n\n３．CPUR 再帰 バックトラック\n");
  }else if(gpu){
    printf("\n\n３．GPU 非再帰 バックトラック\n");
  }else if(sgpu){
    printf("\n\n３．SGPU 非再帰 バックトラック\n");
  }
  if(cpu||cpur){
    printf("%s\n"," N:        Total       Unique        hh:mm:ss.ms");
    clock_t st;           //速度計測用
    char t[20];           //hh:mm:ss.msを格納
    int min=4; 
    int targetN=17;
    //aBaord配列を-1で初期化
    for(int i=min;i<=targetN;i++){
      TOTAL=0; UNIQUE=0;
      for(int j=0;j<=targetN;j++){ aBoard[j]=-1; }
      st=clock();
      if(cpu){ NQueen(0,i); }
      if(cpur){ NQueenR(0,i); }
      TimeFormat(clock()-st,t); 
      printf("%2d:%13ld%16ld%s\n",i,TOTAL,UNIQUE,t);
    }
  }
  /** GPU */
  if(gpu||sgpu){
    if(!InitCUDA()){return 0;}
    int min=4;int targetN=18;
    struct timeval t0;struct timeval t1;
    int ss;int ms;int dd;
    long TOTAL;
    long results[2];//結果格納用
    printf("%s\n"," N:        Total      Unique      dd:hh:mm:ss.ms");
    for(int i=min;i<=targetN;i++){
      gettimeofday(&t0,NULL);   // 計測開始
      if(gpu){
        solve_nqueen_cuda(i,results,steps);
        TOTAL=results[0];
        UNIQUE=results[1];
      }
      gettimeofday(&t1,NULL);   // 計測終了
      if (t1.tv_usec<t0.tv_usec) {
        dd=(int)(t1.tv_sec-t0.tv_sec-1)/86400;
        ss=(t1.tv_sec-t0.tv_sec-1)%86400;
        ms=(1000000+t1.tv_usec-t0.tv_usec+500)/10000;
      } else {
        dd=(int)(t1.tv_sec-t0.tv_sec)/86400;
        ss=(t1.tv_sec-t0.tv_sec)%86400;
        ms=(t1.tv_usec-t0.tv_usec+500)/10000;
      }
      int hh=ss/3600;
      int mm=(ss-hh*3600)/60;
      ss%=60;
      printf("%2d:%13ld%16ld%4.2d:%02d:%02d:%02d.%02d\n", i,TOTAL,Unique,dd,hh,mm,ss,ms);
    }
  }
  return 0;
}

	.text
	.file	"CUDA03_N-Queen.hip"
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z10TimeFormatlPc
.LCPI0_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z10TimeFormatlPc
	.type	_Z10TimeFormatlPc,@function
_Z10TimeFormatlPc:                      # @_Z10TimeFormatlPc
	.cfi_startproc
# %bb.0:
	movq	%rsi, %rax
	cvtsi2ss	%rdi, %xmm0
	divss	.LCPI0_0(%rip), %xmm0
	cvttss2si	%xmm0, %ecx
	movslq	%ecx, %rdx
	imulq	$-2004318071, %rdx, %rcx        # imm = 0x88888889
	shrq	$32, %rcx
	addl	%edx, %ecx
	movl	%ecx, %esi
	shrl	$31, %esi
	sarl	$5, %ecx
	addl	%esi, %ecx
	imull	$60, %ecx, %esi
	cvtsi2ss	%esi, %xmm1
	subss	%xmm1, %xmm0
	movslq	%ecx, %rsi
	imulq	$-1240768329, %rsi, %rcx        # imm = 0xB60B60B7
	shrq	$32, %rcx
	addl	%esi, %ecx
	movl	%ecx, %edi
	shrl	$31, %edi
	sarl	$10, %ecx
	addl	%edi, %ecx
	imull	$1440, %ecx, %ecx               # imm = 0x5A0
	subl	%ecx, %esi
	movswl	%si, %ecx
	imull	$-30583, %ecx, %ecx             # imm = 0x8889
	shrl	$16, %ecx
	addl	%esi, %ecx
	movzwl	%cx, %ecx
	movswl	%cx, %edi
	shrl	$15, %ecx
	sarl	$5, %edi
	addl	%ecx, %edi
	movswl	%di, %ecx
	imull	$60, %edi, %r8d
	movl	%esi, %edi
	subl	%r8d, %edi
	movswl	%di, %r8d
	leal	86399(%rdx), %r9d
	cmpl	$172799, %r9d                   # imm = 0x2A2FF
	jae	.LBB0_4
# %bb.1:
	addl	$59, %esi
	cvtss2sd	%xmm0, %xmm0
	cmpl	$119, %esi
	jae	.LBB0_5
# %bb.2:
	testw	%di, %di
	je	.LBB0_3
# %bb.6:
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	movl	%r8d, %edx
	movb	$1, %al
	jmp	sprintf                         # TAILCALL
.LBB0_4:
	imulq	$-1037155065, %rdx, %rsi        # imm = 0xC22E4507
	shrq	$32, %rsi
	addl	%esi, %edx
	movl	%edx, %esi
	shrl	$31, %esi
	sarl	$16, %edx
	addl	%esi, %edx
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %esi
	movq	%rax, %rdi
                                        # kill: def $edx killed $edx killed $rdx
	movb	$1, %al
	jmp	sprintf                         # TAILCALL
.LBB0_5:
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	movl	%ecx, %edx
	movl	%r8d, %ecx
	movb	$1, %al
	jmp	sprintf                         # TAILCALL
.LBB0_3:
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	movb	$1, %al
	jmp	sprintf                         # TAILCALL
.Lfunc_end0:
	.size	_Z10TimeFormatlPc, .Lfunc_end0-_Z10TimeFormatlPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii # -- Begin function _Z26__device_stub__nqueen_cudaPiS_S_S_Pllii
	.type	_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii,@function
_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii: # @_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11nqueen_cudaPiS_S_S_Pllii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii, .Lfunc_end1-_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii
	.cfi_endproc
                                        # -- End function
	.globl	_Z17solve_nqueen_cudaiPli       # -- Begin function _Z17solve_nqueen_cudaiPli
	.type	_Z17solve_nqueen_cudaiPli,@function
_Z17solve_nqueen_cudaiPli:              # @_Z17solve_nqueen_cudaiPli
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movl	%edi, %r14d
	leaq	72(%rsp), %r12
	movl	$108, %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	64(%rsp), %rdi
	movl	$215, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	56(%rsp), %rdi
	movl	$215, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	48(%rsp), %rdi
	movl	$215, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	%ebp, %r15
	shlq	$3, %r15
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	40(%rsp), %rdi
	movl	$108, %esi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$215, %esi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$215, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$215, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r12), %r12
	testl	%r14d, %r14d
	jle	.LBB2_2
# %bb.1:                                # %.lr.ph
	movl	%r14d, %edx
	shlq	$2, %rdx
	movq	%r12, %rdi
	movl	$255, %esi
	callq	memset@PLT
.LBB2_2:                                # %._crit_edge
	movq	40(%rsp), %rdi
	movl	$108, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movq	64(%rsp), %rsi
	movl	$215, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movl	$215, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi
	movl	$215, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB2_4:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rax
	movq	(%rax), %rax
	movq	%rax, (%rbx)
	movq	72(%rsp), %rdi
	callq	hipHostFree
	movq	64(%rsp), %rdi
	callq	hipHostFree
	movq	56(%rsp), %rdi
	callq	hipHostFree
	movq	48(%rsp), %rdi
	callq	hipHostFree
	movq	8(%rsp), %rdi
	callq	hipHostFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z17solve_nqueen_cudaiPli, .Lfunc_end2-_Z17solve_nqueen_cudaiPli
	.cfi_endproc
                                        # -- End function
	.globl	_Z8InitCUDAv                    # -- Begin function _Z8InitCUDAv
	.type	_Z8InitCUDAv,@function
_Z8InitCUDAv:                           # @_Z8InitCUDAv
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$1480, %rsp                     # imm = 0x5C8
	.cfi_def_cfa_offset 1504
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	4(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	movl	(%rbx), %ecx
	testl	%ecx, %ecx
	je	.LBB3_3
# %bb.1:                                # %.preheader
	jle	.LBB3_2
# %bb.5:                                # %.lr.ph
	xorl	%ebx, %ebx
	leaq	8(%rsp), %r14
.LBB3_6:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	hipGetDevicePropertiesR0600
	movl	4(%rsp), %ecx
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_6 Depth=1
	cmpl	$0, 368(%rsp)
	jg	.LBB3_9
.LBB3_8:                                #   in Loop: Header=BB3_6 Depth=1
	incl	%ebx
	cmpl	%ecx, %ebx
	jl	.LBB3_6
	jmp	.LBB3_9
.LBB3_2:
	xorl	%ebx, %ebx
.LBB3_9:                                # %._crit_edge
	cmpl	%ecx, %ebx
	je	.LBB3_10
# %bb.11:
	movl	%ebx, %edi
	callq	hipSetDevice
	movb	$1, %al
.LBB3_12:
                                        # kill: def $al killed $al killed $eax
	addq	$1480, %rsp                     # imm = 0x5C8
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB3_3:
	.cfi_def_cfa_offset 1504
	movq	stderr(%rip), %rcx
	movl	$.L.str.4, %edi
	movl	$20, %esi
	jmp	.LBB3_4
.LBB3_10:
	movq	stderr(%rip), %rcx
	movl	$.L.str.5, %edi
	movl	$40, %esi
.LBB3_4:
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%eax, %eax
	jmp	.LBB3_12
.Lfunc_end3:
	.size	_Z8InitCUDAv, .Lfunc_end3-_Z8InitCUDAv
	.cfi_endproc
                                        # -- End function
	.globl	_Z6NQueenii                     # -- Begin function _Z6NQueenii
	.type	_Z6NQueenii,@function
_Z6NQueenii:                            # @_Z6NQueenii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	testl	%edi, %edi
	js	.LBB4_18
# %bb.1:                                # %.lr.ph59.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leal	-1(%rsi), %eax
	movq	TOTAL(%rip), %rcx
	movq	%rcx, -16(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	subl	%esi, %ecx
	movq	%rcx, -8(%rsp)                  # 8-byte Spill
	xorl	%r9d, %r9d
.LBB4_2:                                # %.lr.ph59
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_4 Depth 2
	movl	%edi, %ebx
	movl	aBoard(,%rbx,4), %r11d
	movslq	%r11d, %r10
	leal	1(%r10), %ecx
	cmpl	%esi, %ecx
	jge	.LBB4_13
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB4_2 Depth=1
	movl	%eax, %ebp
	subl	%edi, %ebp
	leaq	(%r10,%rbx), %r14
	leal	(%rsi,%r10), %r12d
	subl	%edi, %r12d
	movq	-8(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%r11), %r13
	leaq	(,%r10,4), %rcx
	leaq	(,%r14,4), %r8
	xorl	%r15d, %r15d
.LBB4_4:                                #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	$0, down+4(%rcx,%r15,4)
	jne	.LBB4_12
# %bb.5:                                #   in Loop: Header=BB4_4 Depth=2
	leal	(%r12,%r15), %edx
	movslq	%edx, %rdx
	cmpl	$0, right(,%rdx,4)
	jne	.LBB4_12
# %bb.6:                                #   in Loop: Header=BB4_4 Depth=2
	cmpl	$0, left+4(%r8,%r15,4)
	je	.LBB4_7
.LBB4_12:                               #   in Loop: Header=BB4_4 Depth=2
	incq	%r15
	movl	%r13d, %edx
	addl	%r15d, %edx
	jne	.LBB4_4
.LBB4_13:                               # %.critedge
                                        #   in Loop: Header=BB4_2 Depth=1
	cmpl	$-1, %r11d
	je	.LBB4_15
# %bb.14:                               #   in Loop: Header=BB4_2 Depth=1
	movl	$-1, aBoard(,%rbx,4)
	leal	(%r10,%rdi), %ecx
	movslq	%ecx, %rcx
	movl	%r9d, left(,%rcx,4)
	movl	%eax, %ecx
	subl	%edi, %ecx
	addl	%r11d, %ecx
	movslq	%ecx, %rcx
	movl	%r9d, right(,%rcx,4)
	movl	%r9d, down(,%r10,4)
.LBB4_15:                               #   in Loop: Header=BB4_2 Depth=1
	decl	%edi
.LBB4_16:                               #   in Loop: Header=BB4_2 Depth=1
	testl	%edi, %edi
	jns	.LBB4_2
	jmp	.LBB4_17
.LBB4_7:                                #   in Loop: Header=BB4_2 Depth=1
	cmpl	$-1, %r11d
	je	.LBB4_9
# %bb.8:                                #   in Loop: Header=BB4_2 Depth=1
	leal	(%r11,%rdi), %ecx
	movslq	%ecx, %rcx
	movl	%r9d, left(,%rcx,4)
	addl	%r10d, %ebp
	movslq	%ebp, %rcx
	movl	%r9d, right(,%rcx,4)
	movl	%r9d, down(,%r10,4)
.LBB4_9:                                #   in Loop: Header=BB4_2 Depth=1
	leaq	(%r11,%r15), %rcx
	incq	%rcx
	movl	%ecx, aBoard(,%rbx,4)
	shlq	$2, %r15
	movl	$1, %ecx
	movl	%ecx, left+4(%r15,%r14,4)
	movl	%ecx, right(,%rdx,4)
	movl	%ecx, down+4(%r15,%r10,4)
	leal	1(%rdi), %ecx
	cmpl	%esi, %ecx
	jne	.LBB4_10
# %bb.11:                               #   in Loop: Header=BB4_2 Depth=1
	movq	-16(%rsp), %rcx                 # 8-byte Reload
	incq	%rcx
	movq	%rcx, -16(%rsp)                 # 8-byte Spill
	movq	%rcx, TOTAL(%rip)
	jmp	.LBB4_16
.LBB4_10:                               #   in Loop: Header=BB4_2 Depth=1
	movl	%ecx, %edi
	jmp	.LBB4_16
.LBB4_17:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB4_18:                               # %._crit_edge
	retq
.Lfunc_end4:
	.size	_Z6NQueenii, .Lfunc_end4-_Z6NQueenii
	.cfi_endproc
                                        # -- End function
	.globl	_Z7NQueenRii                    # -- Begin function _Z7NQueenRii
	.type	_Z7NQueenRii,@function
_Z7NQueenRii:                           # @_Z7NQueenRii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
	cmpl	%esi, %edi
	jne	.LBB5_2
# %bb.1:
	incq	TOTAL(%rip)
.LBB5_10:                               # %.loopexit
	retq
.LBB5_2:                                # %.preheader
	testl	%esi, %esi
	jle	.LBB5_10
# %bb.3:                                # %.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	movl	%esi, %r14d
	movslq	%edi, %r15
	leal	(%rbx,%rsi), %ebp
	decl	%ebp
	incl	%ebx
	leaq	(,%r15,4), %rax
	xorl	%r12d, %r12d
	movq	%rax, 8(%rsp)                   # 8-byte Spill
.LBB5_4:                                # =>This Inner Loop Header: Depth=1
	movl	%r12d, aBoard(,%r15,4)
	cmpl	$0, down(,%r12,4)
	jne	.LBB5_8
# %bb.5:                                #   in Loop: Header=BB5_4 Depth=1
	movslq	%ebp, %r13
	cmpl	$0, right(,%r13,4)
	jne	.LBB5_8
# %bb.6:                                #   in Loop: Header=BB5_4 Depth=1
	cmpl	$0, left(%rax,%r12,4)
	jne	.LBB5_8
# %bb.7:                                #   in Loop: Header=BB5_4 Depth=1
	leaq	(,%r12,4), %rdx
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movl	$1, %ecx
	movl	%ecx, left(%rdx,%r15,4)
	movl	%ecx, right(,%r13,4)
	movl	%ecx, down(,%r12,4)
	movl	%ebx, %edi
	movl	%r14d, %esi
	callq	_Z7NQueenRii
	xorl	%eax, %eax
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	%eax, left(%rcx,%r15,4)
	movl	%eax, right(,%r13,4)
	movl	%eax, down(,%r12,4)
	movq	8(%rsp), %rax                   # 8-byte Reload
.LBB5_8:                                #   in Loop: Header=BB5_4 Depth=1
	incq	%r12
	decl	%ebp
	cmpq	%r12, %r14
	jne	.LBB5_4
# %bb.9:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
	retq
.Lfunc_end5:
	.size	_Z7NQueenRii, .Lfunc_end5-_Z7NQueenRii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movb	$1, %bl
	movl	$1, %eax
	cmpl	$2, %edi
	jl	.LBB6_1
# %bb.2:
	movq	8(%rsi), %rcx
	cmpb	$45, (%rcx)
	jne	.LBB6_1
# %bb.3:
	movzbl	1(%rcx), %ecx
	movb	$1, %r12b
	movl	$2, %eax
	cmpl	$98, %ecx
	jg	.LBB6_11
# %bb.4:
	cmpl	$81, %ecx
	jg	.LBB6_8
# %bb.5:
	cmpl	$67, %ecx
	je	.LBB6_13
# %bb.6:
	cmpl	$71, %ecx
	je	.LBB6_7
	jmp	.LBB6_17
.LBB6_1:
	xorl	%r13d, %r13d
	movb	$1, %bpl
	movb	$1, %r12b
	jmp	.LBB6_20
.LBB6_11:
	cmpl	$113, %ecx
	jg	.LBB6_14
# %bb.12:
	cmpl	$99, %ecx
	je	.LBB6_13
# %bb.16:
	cmpl	$103, %ecx
	jne	.LBB6_17
.LBB6_7:
	xorl	%ebp, %ebp
	movb	$1, %bl
	jmp	.LBB6_19
.LBB6_8:
	cmpl	$82, %ecx
	je	.LBB6_17
# %bb.9:
	cmpl	$83, %ecx
	je	.LBB6_10
	jmp	.LBB6_17
.LBB6_14:
	cmpl	$115, %ecx
	je	.LBB6_10
# %bb.15:
	cmpl	$114, %ecx
.LBB6_17:
	xorl	%r12d, %r12d
	movb	$1, %bl
	jmp	.LBB6_18
.LBB6_13:
	movb	$1, %bl
	movb	$1, %bpl
	movb	$1, %r13b
	jmp	.LBB6_20
.LBB6_10:
	xorl	%ebx, %ebx
.LBB6_18:
	movb	$1, %bpl
.LBB6_19:
	xorl	%r13d, %r13d
.LBB6_20:
	cmpl	%edi, %eax
	jle	.LBB6_22
# %bb.21:
	movq	(%rsi), %rsi
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	$.Lstr.4, %edi
	callq	puts@PLT
.LBB6_22:
	movl	%r12d, %eax
	xorb	$1, %al
	orb	%r13b, %al
	je	.LBB6_23
# %bb.25:                               # %.thread
	movl	%ebx, 8(%rsp)                   # 4-byte Spill
	movl	%ebp, 12(%rsp)                  # 4-byte Spill
	movl	$.Lstr.8, %eax
	movl	$.Lstr.7, %edi
	testb	%r13b, %r13b
	cmovneq	%rax, %rdi
	callq	puts@PLT
	movl	$.L.str.17, %edi
	callq	puts@PLT
	movl	$4, %ebx
	xorl	%ebp, %ebp
	leaq	16(%rsp), %r14
.LBB6_26:                               # =>This Inner Loop Header: Depth=1
	movq	%rbp, TOTAL(%rip)
	movq	%rbp, UNIQUE(%rip)
	pcmpeqd	%xmm0, %xmm0
	movdqa	%xmm0, aBoard(%rip)
	movdqa	%xmm0, aBoard+16(%rip)
	movdqa	%xmm0, aBoard+32(%rip)
	movdqa	%xmm0, aBoard+48(%rip)
	movq	$-1, aBoard+64(%rip)
	callq	clock
	movq	%rax, %r15
	testb	%r13b, %r13b
	je	.LBB6_28
# %bb.27:                               #   in Loop: Header=BB6_26 Depth=1
	xorl	%edi, %edi
	movl	%ebx, %esi
	callq	_Z6NQueenii
.LBB6_28:                               #   in Loop: Header=BB6_26 Depth=1
	testb	%r12b, %r12b
	jne	.LBB6_30
# %bb.29:                               #   in Loop: Header=BB6_26 Depth=1
	xorl	%edi, %edi
	movl	%ebx, %esi
	callq	_Z7NQueenRii
.LBB6_30:                               #   in Loop: Header=BB6_26 Depth=1
	callq	clock
	subq	%r15, %rax
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_Z10TimeFormatlPc
	movq	TOTAL(%rip), %rdx
	movq	UNIQUE(%rip), %rcx
	movl	$.L.str.18, %edi
	movl	%ebx, %esi
	movq	%r14, %r8
	xorl	%eax, %eax
	callq	printf
	incl	%ebx
	cmpl	$18, %ebx
	jne	.LBB6_26
# %bb.31:
	movl	12(%rsp), %ebp                  # 4-byte Reload
	movl	8(%rsp), %ebx                   # 4-byte Reload
	jmp	.LBB6_32
.LBB6_23:
	testb	%bl, %bpl
	je	.LBB6_24
.LBB6_32:
	testb	%bpl, %bl
	je	.LBB6_33
	jmp	.LBB6_38
.LBB6_24:                               # %.thread101.sink.split
	movl	$.Lstr.5, %eax
	movl	$.Lstr.6, %edi
	testb	%bpl, %bpl
	cmovneq	%rax, %rdi
	callq	puts@PLT
.LBB6_33:                               # %.thread101
	callq	_Z8InitCUDAv
	testb	%al, %al
	je	.LBB6_38
# %bb.34:
	movl	$.L.str.19, %edi
	callq	puts@PLT
	movl	$4, %ebx
	leaq	72(%rsp), %r15
	movabsq	$1749024623285053783, %r14      # imm = 0x1845C8A0CE512957
                                        # implicit-def: $r13
.LBB6_35:                               # =>This Inner Loop Header: Depth=1
	leaq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	%ebp, %r12d
	testb	%bpl, %bpl
	jne	.LBB6_37
# %bb.36:                               #   in Loop: Header=BB6_35 Depth=1
	movl	%ebx, %edi
	leaq	48(%rsp), %rsi
	movl	$24576, %edx                    # imm = 0x6000
	callq	_Z17solve_nqueen_cudaiPli
	movq	48(%rsp), %r13
	movq	56(%rsp), %rax
	movq	%rax, UNIQUE(%rip)
.LBB6_37:                               #   in Loop: Header=BB6_35 Depth=1
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	80(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	24(%rsp), %rsi
	leaq	1000000(%rdx), %rax
	movq	%rcx, %rdi
	negq	%rdi
	cmpq	%rsi, %rdx
	notq	%rcx
	cmovgeq	%rdi, %rcx
	cmovgeq	%rdx, %rax
	addq	72(%rsp), %rcx
	movslq	%ecx, %r8
	imulq	$-1037155065, %r8, %rdx         # imm = 0xC22E4507
	shrq	$32, %rdx
	addl	%edx, %r8d
	movl	%r8d, %edi
	shrl	$31, %edi
	sarl	$16, %r8d
	subq	%rsi, %rax
	addq	$500, %rax                      # imm = 0x1F4
	movabsq	$3777893186295716171, %rdx      # imm = 0x346DC5D63886594B
	imulq	%rdx
	movq	%rdx, %r10
	addl	%edi, %r8d
	movq	%rdx, %rsi
	shrq	$63, %rsi
	shrq	$11, %r10
	movq	%rcx, %rax
	imulq	%r14
	addl	%esi, %r10d
	movq	%rdx, %rax
	shrq	$63, %rax
	sarq	$13, %rdx
	addq	%rax, %rdx
	imulq	$86400, %rdx, %rax              # imm = 0x15180
	subq	%rax, %rcx
	movslq	%ecx, %r11
	imulq	$-1851608123, %r11, %r9         # imm = 0x91A2B3C5
	shrq	$32, %r9
	addl	%r11d, %r9d
	movl	%r9d, %eax
	shrl	$31, %eax
	sarl	$11, %r9d
	addl	%eax, %r9d
	imull	$-3600, %r9d, %eax              # imm = 0xF1F0
	addl	%r11d, %eax
	movslq	%eax, %rbp
	imulq	$-2004318071, %rbp, %rax        # imm = 0x88888889
	shrq	$32, %rax
	addl	%eax, %ebp
	movl	%ebp, %eax
	shrl	$31, %eax
	sarl	$5, %ebp
	addl	%eax, %ebp
	imulq	$-2004318071, %r11, %rax        # imm = 0x88888889
	shrq	$32, %rax
	addl	%r11d, %eax
	movl	%eax, %ecx
	shrl	$31, %ecx
	sarl	$5, %eax
	addl	%ecx, %eax
	imull	$60, %eax, %eax
	subl	%eax, %r11d
	movq	Unique(%rip), %rcx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$.L.str.20, %edi
	movl	%ebx, %esi
	movq	%r13, %rdx
                                        # kill: def $r8d killed $r8d killed $r8
                                        # kill: def $r9d killed $r9d killed $r9
	xorl	%eax, %eax
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	incl	%ebx
	cmpl	$19, %ebx
	movl	%r12d, %ebp
	jne	.LBB6_35
.LBB6_38:
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11nqueen_cudaPiS_S_S_Pllii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	Unique,@object                  # @Unique
	.bss
	.globl	Unique
	.p2align	3, 0x0
Unique:
	.quad	0                               # 0x0
	.size	Unique, 8

	.type	down,@object                    # @down
	.globl	down
	.p2align	4, 0x0
down:
	.zero	212
	.size	down, 212

	.type	left,@object                    # @left
	.globl	left
	.p2align	4, 0x0
left:
	.zero	212
	.size	left, 212

	.type	right,@object                   # @right
	.globl	right
	.p2align	4, 0x0
right:
	.zero	212
	.size	right, 212

	.type	TOTAL,@object                   # @TOTAL
	.globl	TOTAL
	.p2align	3, 0x0
TOTAL:
	.quad	0                               # 0x0
	.size	TOTAL, 8

	.type	UNIQUE,@object                  # @UNIQUE
	.globl	UNIQUE
	.p2align	3, 0x0
UNIQUE:
	.quad	0                               # 0x0
	.size	UNIQUE, 8

	.type	aBoard,@object                  # @aBoard
	.globl	aBoard
	.p2align	4, 0x0
aBoard:
	.zero	108
	.size	aBoard, 108

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%4d %02d:%02d:%05.2f"
	.size	.L.str, 21

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"     %2d:%02d:%05.2f"
	.size	.L.str.1, 21

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"        %2d:%05.2f"
	.size	.L.str.2, 19

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"           %5.2f"
	.size	.L.str.3, 17

	.type	_Z11nqueen_cudaPiS_S_S_Pllii,@object # @_Z11nqueen_cudaPiS_S_S_Pllii
	.section	.rodata,"a",@progbits
	.globl	_Z11nqueen_cudaPiS_S_S_Pllii
	.p2align	3, 0x0
_Z11nqueen_cudaPiS_S_S_Pllii:
	.quad	_Z26__device_stub__nqueen_cudaPiS_S_S_Pllii
	.size	_Z11nqueen_cudaPiS_S_S_Pllii, 8

	.type	.L.str.4,@object                # @.str.4
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.4:
	.asciz	"There is no device.\n"
	.size	.L.str.4, 21

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"There is no device supporting CUDA 1.x.\n"
	.size	.L.str.5, 41

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Usage: %s [-c|-g|-r|-s]\n"
	.size	.L.str.6, 25

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	" N:        Total       Unique        hh:mm:ss.ms"
	.size	.L.str.17, 49

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"%2d:%13ld%16ld%s\n"
	.size	.L.str.18, 18

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	" N:        Total      Unique      dd:hh:mm:ss.ms"
	.size	.L.str.19, 49

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"%2d:%13ld%16ld%4.2d:%02d:%02d:%02d.%02d\n"
	.size	.L.str.20, 41

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11nqueen_cudaPiS_S_S_Pllii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"  -c: CPU only"
	.size	.Lstr, 15

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"  -r: CPUR only"
	.size	.Lstr.1, 16

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"  -g: GPU only"
	.size	.Lstr.2, 15

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"  -s: SGPU only"
	.size	.Lstr.3, 16

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"Default CPUR to 8 queen"
	.size	.Lstr.4, 24

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"\n\n\357\274\223\357\274\216SGPU \351\235\236\345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257"
	.size	.Lstr.5, 45

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"\n\n\357\274\223\357\274\216GPU \351\235\236\345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257"
	.size	.Lstr.6, 44

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"\n\n\357\274\223\357\274\216CPUR \345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257"
	.size	.Lstr.7, 42

	.type	.Lstr.8,@object                 # @str.8
.Lstr.8:
	.asciz	"\n\n\357\274\223\357\274\216CPU \351\235\236\345\206\215\345\270\260 \343\203\220\343\203\203\343\202\257\343\203\210\343\203\251\343\203\203\343\202\257"
	.size	.Lstr.8, 44

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__nqueen_cudaPiS_S_S_Pllii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11nqueen_cudaPiS_S_S_Pllii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11nqueen_cudaPiS_S_S_Pllii ; -- Begin function _Z11nqueen_cudaPiS_S_S_Pllii
	.globl	_Z11nqueen_cudaPiS_S_S_Pllii
	.p2align	8
	.type	_Z11nqueen_cudaPiS_S_S_Pllii,@function
_Z11nqueen_cudaPiS_S_S_Pllii:           ; @_Z11nqueen_cudaPiS_S_S_Pllii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[12:13], s[0:1], 0x30
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s12, 0
	s_cbranch_scc1 .LBB0_23
; %bb.1:                                ; %.lr.ph89.preheader
	v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, -1
	v_mov_b32_e32 v4, 1
	s_add_i32 s28, s13, -1
	s_add_u32 s29, s2, 4
	s_addc_u32 s30, s3, 0
	s_mov_b32 s10, s12
                                        ; implicit-def: $sgpr18_sgpr19
                                        ; implicit-def: $sgpr16_sgpr17
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr22_sgpr23
.LBB0_2:                                ; %.lr.ph89
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_mov_b32 s11, 0
	s_mov_b32 s21, -1
	s_lshl_b64 s[14:15], s[10:11], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s14, s0, s14
	s_addc_u32 s15, s1, s15
	global_load_b32 v5, v2, s[14:15]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v5
	s_add_i32 s31, s20, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s31, s13
	s_cbranch_scc1 .LBB0_13
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_ashr_i32 s21, s20, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[20:21], 2
	s_add_u32 s24, s29, s16
	s_addc_u32 s25, s30, s17
	s_sub_i32 s11, s13, s10
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v2, s[24:25]
	s_mov_b32 s21, -1
	s_mov_b32 s26, -1
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $sgpr22_sgpr23
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr16_sgpr17
                                        ; implicit-def: $sgpr18_sgpr19
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	s_cbranch_vccnz .LBB0_9
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s12, s11, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s16, s12, -1
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[16:17], 2
	s_add_u32 s16, s4, s16
	s_addc_u32 s17, s5, s17
	global_load_b32 v5, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ne_u32_e64 s26, 0, v5
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $sgpr16_sgpr17
                                        ; implicit-def: $sgpr18_sgpr19
	s_branch .LBB0_8
.LBB0_7:                                ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s18, s10, s31
	s_mov_b32 s33, -1
	s_ashr_i32 s19, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[18:19], s[18:19], 2
	s_add_u32 s18, s6, s18
	s_addc_u32 s19, s7, s19
	global_load_b32 v5, v2, s[18:19]
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s26, 0, v5
.LBB0_8:                                ; %Flow143
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b64 s[22:23], s[24:25]
	s_mov_b32 s12, s31
.LBB0_9:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s26
                                        ; implicit-def: $sgpr34
                                        ; implicit-def: $sgpr26_sgpr27
	s_cbranch_vccz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s34, s31, 1
	s_add_u32 s26, s24, 4
	s_addc_u32 s27, s25, 0
	s_cmp_ge_i32 s34, s13
	s_mov_b32 s33, 0
	s_cselect_b32 s21, -1, 0
	s_mov_b64 s[22:23], s[24:25]
	s_mov_b32 s12, s31
                                        ; implicit-def: $sgpr16_sgpr17
                                        ; implicit-def: $sgpr18_sgpr19
.LBB0_11:                               ; %Flow144
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_b32 vcc_lo, exec_lo, s21
	s_mov_b64 s[24:25], s[26:27]
	s_mov_b32 s31, s34
	s_cbranch_vccnz .LBB0_4
; %bb.12:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_xor_b32 s21, s33, -1
	s_mov_b32 s11, -1
.LBB0_13:                               ; %Flow145
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s21
                                        ; implicit-def: $sgpr21
	s_cbranch_vccz .LBB0_17
; %bb.14:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_cmp_eq_u32 s20, -1
	s_cbranch_scc1 .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s24, s20, s10
	global_store_b32 v2, v3, s[14:15]
	s_ashr_i32 s25, s24, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[24:25], s[24:25], 2
	s_add_u32 s24, s6, s24
	s_addc_u32 s25, s7, s25
	s_sub_i32 s11, s28, s10
	global_store_b32 v2, v2, s[24:25]
	s_add_i32 s26, s11, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s27, s26, 31
	s_lshl_b64 s[26:27], s[26:27], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s26, s4, s26
	s_addc_u32 s27, s5, s27
	s_ashr_i32 s21, s20, 31
	s_lshl_b64 s[34:35], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s2, s34
	s_addc_u32 s25, s3, s35
	s_clause 0x1
	global_store_b32 v2, v2, s[26:27]
	global_store_b32 v2, v2, s[24:25]
.LBB0_16:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s21, s10, -1
	s_mov_b32 s11, 0
.LBB0_17:                               ; %Flow146
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccz .LBB0_21
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	s_cmp_eq_u32 s20, -1
	s_cbranch_scc1 .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s20, s20, s10
	s_sub_i32 s11, s28, s10
	s_ashr_i32 s21, s20, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[20:21], 2
	s_add_u32 s20, s6, s20
	s_addc_u32 s21, s7, s21
	global_store_b32 v2, v2, s[20:21]
	global_load_b32 v5, v2, s[14:15]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s20, s11, s20
	s_ashr_i32 s21, s20, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[20:21], 2
	s_add_u32 s20, s4, s20
	s_addc_u32 s21, s5, s21
	global_store_b32 v2, v2, s[20:21]
	global_load_b32 v5, v2, s[14:15]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	global_store_b32 v[5:6], v2, off
.LBB0_20:                               ; %.critedge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s11, s10, 1
	v_mov_b32_e32 v5, s12
	s_cmp_eq_u32 s11, s13
	s_clause 0x1
	global_store_b32 v2, v5, s[14:15]
	global_store_b32 v2, v4, s[18:19]
	s_cselect_b32 s20, -1, 0
	global_store_b32 v2, v4, s[16:17]
	v_cndmask_b32_e64 v6, 0, 1, s20
	s_and_b32 s14, s20, exec_lo
	s_cselect_b32 s21, s10, s11
	global_store_b32 v2, v4, s[22:23]
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_21:                               ;   in Loop: Header=BB0_2 Depth=1
	s_cmp_gt_i32 s21, -1
	s_cbranch_scc0 .LBB0_24
; %bb.22:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, s21
	s_branch .LBB0_2
.LBB0_23:
	v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
.LBB0_24:                               ; %._crit_edge90
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[0:1], s[8:9]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11nqueen_cudaPiS_S_S_Pllii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11nqueen_cudaPiS_S_S_Pllii, .Lfunc_end0-_Z11nqueen_cudaPiS_S_S_Pllii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 796
; NumSgprs: 38
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11nqueen_cudaPiS_S_S_Pllii
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z11nqueen_cudaPiS_S_S_Pllii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
