/******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel 
*	C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
*	College student.
*       Faculty of Computer Science and Technology.
*       Ho Chi Minh University of Technology, Viet Nam.
*       vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/

#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
	if (code != cudaSuccess)
	{
		fprintf(stderr, "GPUassert: %s %s %d\n", \
			cudaGetErrorString(code), file, line);
		if (abort) 
			exit(code);
	}
}

/* Structure *****************************************************************/
typedef struct {
	int64_t rbeg;
	int32_t qbeg, len;
	int score;
} mem_seed_t; // unaligned memory

typedef struct {
	int n, m, first, rid;
	uint32_t w:29, kept:2, is_alt:1;
	float frac_rep;
	int64_t pos;
	mem_seed_t *seeds;
} mem_chain_t;

typedef struct {
	size_t n, m;
	mem_chain_t *a;
} mem_chain_v;

typedef struct {
	int n, m, first, rid;
	uint32_t w:29, kept:2, is_alt:1;
	float frac_rep;
	int64_t pos;
} flat_mem_chain_t;

typedef struct {
	size_t n, m;
} flat_mem_chain_v;

__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
		flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
	int i, j;
	*d_b = 0;
	for(i = 0; i < n; i++) {
		*d_b += chns[i].n;
		for(j = 0; j < n_a; j++) {
			*d_b += a[j].n;		
		}	
	}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
	// Assumptions
	int b;
	int *d_b;
	gpuErrchk(cudaMalloc(&d_b, sizeof(int)));
	// Begin Assumptions
	int n, i, j, k;
	n = 10;
	
	mem_chain_v *chns;
	chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
	for(i = 0; i < n; i++) {
		chns[i].n = 10;
		chns[i].a = (mem_chain_t*)malloc(\
			chns[i].n * sizeof(mem_chain_t));
		for(j = 0; j < chns[i].n; j++) {
			chns[i].a[j].n = 10;
			chns[i].a[j].seeds = (mem_seed_t*)malloc(\
				chns[i].a[j].n * sizeof(mem_seed_t));		
			for(k = 0; k < chns[i].a[j].n; k++) {
				chns[i].a[j].seeds[k].score = i + j + k;
			}
		}
	}
	// End Assumptions
	int n_a, n_seeds;
	n_a = 0; n_seeds = 0;

	for(i = 0; i < n; i++) {
		n_a += chns[i].n;
		for(j = 0; j < chns[i].n; j++) {
			n_seeds += chns[i].a[j].n;
		}
	}

	flat_mem_chain_v *f_chns, *df_chns;
	flat_mem_chain_t *f_a, *df_a;
	mem_seed_t *seeds, *d_seeds;
	
	// Flattened the nested structure
	f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
	f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
	seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));

	int acc_a, acc_seeds;
	acc_a = 0; acc_seeds = 0;

	for(i = 0; i < n; i++) {
		f_chns[i].n = chns[i].n;
		f_chns[i].m = chns[i].m;
		for(j = 0; j < chns[i].n; j++) {
			// int n, m, first, rid;
			// uint32_t w:29, kept:2, is_alt:1;
			// float frac_rep;
			// int64_t pos;
			mem_chain_t *tmp;
			tmp = &chns[i].a[j];
			f_a[acc_a].n = tmp->n;
			f_a[acc_a].m = tmp->m;
			f_a[acc_a].first = tmp->first;
			f_a[acc_a].rid = tmp->rid;
			f_a[acc_a].w = tmp->w;
			f_a[acc_a].kept = tmp->kept;
			f_a[acc_a].is_alt = tmp->is_alt;
			f_a[acc_a].frac_rep = tmp->frac_rep;
			f_a[acc_a].pos = tmp->pos;
			for(k = 0; k < chns[i].a[j].n; k++) {
				// int64_t rbeg;
				// int32_t qbeg, len;
				// int score;
				mem_seed_t *tmp0;
				tmp0 = &chns[i].a[j].seeds[k];
				seeds[acc_seeds].rbeg = tmp0->rbeg;
				seeds[acc_seeds].qbeg = tmp0->qbeg;
				seeds[acc_seeds].len = tmp0->len;
				seeds[acc_seeds].score = tmp0->score;
			}
			acc_seeds += chns[i].a[j].n;		
		}
		acc_a += chns[i].n;
	}

	// Copy the flattened structure to kernel
	gpuErrchk(cudaMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
	gpuErrchk(cudaMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
	gpuErrchk(cudaMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));

	gpuErrchk(cudaMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
				cudaMemcpyHostToDevice));
	gpuErrchk(cudaMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
				cudaMemcpyHostToDevice));
	gpuErrchk(cudaMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
				cudaMemcpyHostToDevice));	

	printf("n = %d, n_a = %d\n", n, n_a);
	func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);

	gpuErrchk(cudaPeekAtLastError());
	gpuErrchk(cudaDeviceSynchronize());
	gpuErrchk(cudaMemcpy(&b, d_b, sizeof(int), cudaMemcpyDeviceToHost));	
	printf("d_b = %d\n", b);
	
	cudaFree(df_chns);
	cudaFree(df_a);
	cudaFree(d_seeds);
	cudaFree(d_b);
	return 0;
}

	.file	"tmpxft_0026e60e_00000000-6_deepCopy_2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.text
	.globl	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.globl	_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.type	_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, @function
_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L12:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .-_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.globl	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.type	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, @function
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.cfi_endproc
.LFE2054:
	.size	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .-_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.section	.rodata.str1.1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/vuongpd95/cuda-test/master/deepCopy_2/deepCopy_2.cu"
.LC2:
	.string	"n = %d, n_a = %d\n"
.LC3:
	.string	"d_b = %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$84, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	$240, %edi
	call	malloc@PLT
	movq	%rax, %r14
	movq	%rax, %rbx
	movq	%rax, %r13
.L20:
	movq	$10, 0(%r13)
	movl	$400, %edi
	xorl	%r15d, %r15d
	call	malloc@PLT
	movq	%rax, 16(%r13)
	movq	%rax, %rbp
.L19:
	movl	$10, 0(%rbp)
	movl	$240, %edi
	call	malloc@PLT
	leal	(%r15,%r12), %ecx
	xorl	%edx, %edx
	movq	%rax, 32(%rbp)
.L18:
	movl	%ecx, 16(%rax,%rdx)
	addq	$24, %rdx
	incl	%ecx
	cmpq	$240, %rdx
	jne	.L18
	incl	%r15d
	addq	$40, %rbp
	cmpl	$10, %r15d
	jne	.L19
	incl	%r12d
	addq	$24, %r13
	cmpl	$10, %r12d
	jne	.L20
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	xorl	%esi, %esi
.L23:
	movq	(%r14,%rax), %rdx
	leal	(%rsi,%rdx), %ecx
	imulq	$40, %rdx, %rdx
	movl	%ecx, 24(%rsp)
	movl	%ecx, %esi
	xorl	%ecx, %ecx
.L21:
	cmpq	%rdx, %rcx
	je	.L37
	movq	16(%r14,%rax), %rdi
	addl	(%rdi,%rcx), %ebp
	addq	$40, %rcx
	jmp	.L21
.L37:
	addq	$24, %rax
	cmpq	$240, %rax
	jne	.L23
	movl	$160, %edi
	call	malloc@PLT
	movq	%rax, 16(%rsp)
	movslq	24(%rsp), %rax
	salq	$5, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	%rax, %r12
	movslq	%ebp, %rax
	imulq	$24, %rax, %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	xorl	%esi, %esi
	movq	16(%rsp), %rdi
	movq	%rax, %r13
	leaq	240(%r14), %rax
	movl	%esi, 28(%rsp)
	xorl	%r14d, %r14d
	movq	%rax, 40(%rsp)
.L28:
	movq	(%rbx), %r11
	movq	8(%rbx), %rax
	xorl	%r8d, %r8d
	imulq	$40, %r11, %rcx
	movq	%rax, 8(%rdi)
	movslq	28(%rsp), %rax
	movq	%r11, (%rdi)
	salq	$5, %rax
	movq	%rcx, 32(%rsp)
	addq	%r12, %rax
.L24:
	cmpq	%r8, 32(%rsp)
	je	.L38
	movq	16(%rbx), %rcx
	xorl	%r9d, %r9d
	addq	%r8, %rcx
	movq	(%rcx), %rdx
	movq	24(%rcx), %rsi
	movl	(%rcx), %r15d
	movq	%rdx, (%rax)
	movq	8(%rcx), %rdx
	movq	%rsi, 24(%rax)
	movq	%rdx, 8(%rax)
	movq	16(%rcx), %rdx
	movq	%rdx, 16(%rax)
	movslq	%r14d, %rdx
	imulq	$24, %rdx, %rdx
	addq	%r13, %rdx
.L25:
	cmpl	%r9d, %r15d
	jle	.L39
	imulq	$24, %r9, %rsi
	addq	32(%rcx), %rsi
	incq	%r9
	movq	(%rsi), %r10
	movq	%r10, (%rdx)
	movl	8(%rsi), %r10d
	movl	%r10d, 8(%rdx)
	movl	12(%rsi), %r10d
	movl	16(%rsi), %esi
	movl	%r10d, 12(%rdx)
	movl	%esi, 16(%rdx)
	jmp	.L25
.L39:
	addl	%r15d, %r14d
	addq	$40, %r8
	jmp	.L24
.L38:
	movq	40(%rsp), %rax
	addq	$24, %rbx
	addl	%r11d, 28(%rsp)
	addq	$16, %rdi
	cmpq	%rax, %rbx
	jne	.L28
	leaq	56(%rsp), %rdi
	movl	$160, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$163, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$164, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$165, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movl	$160, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$167, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$169, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$171, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	24(%rsp), %ecx
	movl	$10, %edx
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 100(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	%rax
	.cfi_def_cfa_offset 184
	movl	%ebp, %edx
	movl	$10, %edi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	88(%rsp), %r9
	movq	80(%rsp), %r8
	movq	72(%rsp), %rcx
	movl	40(%rsp), %esi
	call	_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	popq	%rdx
	.cfi_def_cfa_offset 184
	popq	%rcx
	.cfi_def_cfa_offset 176
.L29:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$177, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$178, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	48(%rsp), %rsi
	leaq	92(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$179, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	92(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel 
*	C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
*	College student.
*       Faculty of Computer Science and Technology.
*       Ho Chi Minh University of Technology, Viet Nam.
*       vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/

#include "hip/hip_runtime.h"


#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
	if (code != hipSuccess)
	{
		fprintf(stderr, "GPUassert: %s %s %d\n", \
			hipGetErrorString(code), file, line);
		if (abort) 
			exit(code);
	}
}

/* Structure *****************************************************************/
typedef struct {
	int64_t rbeg;
	int32_t qbeg, len;
	int score;
} mem_seed_t; // unaligned memory

typedef struct {
	int n, m, first, rid;
	uint32_t w:29, kept:2, is_alt:1;
	float frac_rep;
	int64_t pos;
	mem_seed_t *seeds;
} mem_chain_t;

typedef struct {
	size_t n, m;
	mem_chain_t *a;
} mem_chain_v;

typedef struct {
	int n, m, first, rid;
	uint32_t w:29, kept:2, is_alt:1;
	float frac_rep;
	int64_t pos;
} flat_mem_chain_t;

typedef struct {
	size_t n, m;
} flat_mem_chain_v;

__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
		flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
	int i, j;
	*d_b = 0;
	for(i = 0; i < n; i++) {
		*d_b += chns[i].n;
		for(j = 0; j < n_a; j++) {
			*d_b += a[j].n;		
		}	
	}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
	// Assumptions
	int b;
	int *d_b;
	gpuErrchk(hipMalloc(&d_b, sizeof(int)));
	// Begin Assumptions
	int n, i, j, k;
	n = 10;
	
	mem_chain_v *chns;
	chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
	for(i = 0; i < n; i++) {
		chns[i].n = 10;
		chns[i].a = (mem_chain_t*)malloc(\
			chns[i].n * sizeof(mem_chain_t));
		for(j = 0; j < chns[i].n; j++) {
			chns[i].a[j].n = 10;
			chns[i].a[j].seeds = (mem_seed_t*)malloc(\
				chns[i].a[j].n * sizeof(mem_seed_t));		
			for(k = 0; k < chns[i].a[j].n; k++) {
				chns[i].a[j].seeds[k].score = i + j + k;
			}
		}
	}
	// End Assumptions
	int n_a, n_seeds;
	n_a = 0; n_seeds = 0;

	for(i = 0; i < n; i++) {
		n_a += chns[i].n;
		for(j = 0; j < chns[i].n; j++) {
			n_seeds += chns[i].a[j].n;
		}
	}

	flat_mem_chain_v *f_chns, *df_chns;
	flat_mem_chain_t *f_a, *df_a;
	mem_seed_t *seeds, *d_seeds;
	
	// Flattened the nested structure
	f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
	f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
	seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));

	int acc_a, acc_seeds;
	acc_a = 0; acc_seeds = 0;

	for(i = 0; i < n; i++) {
		f_chns[i].n = chns[i].n;
		f_chns[i].m = chns[i].m;
		for(j = 0; j < chns[i].n; j++) {
			// int n, m, first, rid;
			// uint32_t w:29, kept:2, is_alt:1;
			// float frac_rep;
			// int64_t pos;
			mem_chain_t *tmp;
			tmp = &chns[i].a[j];
			f_a[acc_a].n = tmp->n;
			f_a[acc_a].m = tmp->m;
			f_a[acc_a].first = tmp->first;
			f_a[acc_a].rid = tmp->rid;
			f_a[acc_a].w = tmp->w;
			f_a[acc_a].kept = tmp->kept;
			f_a[acc_a].is_alt = tmp->is_alt;
			f_a[acc_a].frac_rep = tmp->frac_rep;
			f_a[acc_a].pos = tmp->pos;
			for(k = 0; k < chns[i].a[j].n; k++) {
				// int64_t rbeg;
				// int32_t qbeg, len;
				// int score;
				mem_seed_t *tmp0;
				tmp0 = &chns[i].a[j].seeds[k];
				seeds[acc_seeds].rbeg = tmp0->rbeg;
				seeds[acc_seeds].qbeg = tmp0->qbeg;
				seeds[acc_seeds].len = tmp0->len;
				seeds[acc_seeds].score = tmp0->score;
			}
			acc_seeds += chns[i].a[j].n;		
		}
		acc_a += chns[i].n;
	}

	// Copy the flattened structure to kernel
	gpuErrchk(hipMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
	gpuErrchk(hipMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
	gpuErrchk(hipMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));

	gpuErrchk(hipMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
				hipMemcpyHostToDevice));
	gpuErrchk(hipMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
				hipMemcpyHostToDevice));
	gpuErrchk(hipMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
				hipMemcpyHostToDevice));	

	printf("n = %d, n_a = %d\n", n, n_a);
	func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);

	gpuErrchk(hipPeekAtLastError());
	gpuErrchk(hipDeviceSynchronize());
	gpuErrchk(hipMemcpy(&b, d_b, sizeof(int), hipMemcpyDeviceToHost));	
	printf("d_b = %d\n", b);
	
	hipFree(df_chns);
	hipFree(df_a);
	hipFree(d_seeds);
	hipFree(d_b);
	return 0;
}

	.text
	.file	"deepCopy_2.hip"
	.globl	_Z9gpuAssert10hipError_tPKcib   # -- Begin function _Z9gpuAssert10hipError_tPKcib
	.type	_Z9gpuAssert10hipError_tPKcib,@function
_Z9gpuAssert10hipError_tPKcib:          # @_Z9gpuAssert10hipError_tPKcib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%edi, %edi
	jne	.LBB0_1
.LBB0_2:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_1:
	.cfi_def_cfa_offset 48
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, %r15
	movl	%edi, %ebx
	movq	stderr(%rip), %r12
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%r12, %rdi
	movq	%rax, %rdx
	movq	%r15, %rcx
	movl	%r14d, %r8d
	xorl	%eax, %eax
	callq	fprintf
	testb	%bpl, %bpl
	je	.LBB0_2
# %bb.3:
	movl	%ebx, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z9gpuAssert10hipError_tPKcib, .Lfunc_end0-_Z9gpuAssert10hipError_tPKcib
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi # -- Begin function _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.type	_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@function
_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi: # @_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .Lfunc_end1-_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$84, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movl	$240, %edi
	callq	malloc
	movq	%rax, %r13
	xorl	%r15d, %r15d
.LBB2_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
                                        #       Child Loop BB2_3 Depth 3
	leaq	(%r15,%r15,2), %r14
	movq	$10, (%r13,%r14,8)
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %rbx
	movq	%rax, 16(%r13,%r14,8)
	movl	%r15d, %ebp
	xorl	%r12d, %r12d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_3 Depth 3
	leaq	(%r12,%r12,4), %r14
	movl	$10, (%rbx,%r14,8)
	movl	$240, %edi
	callq	malloc
	movq	%rax, 32(%rbx,%r14,8)
	movl	$16, %ecx
	movl	%ebp, %edx
.LBB2_3:                                #   Parent Loop BB2_1 Depth=1
                                        #     Parent Loop BB2_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%edx, (%rax,%rcx)
	incl	%edx
	addq	$24, %rcx
	cmpq	$256, %rcx                      # imm = 0x100
	jne	.LBB2_3
# %bb.4:                                #   in Loop: Header=BB2_2 Depth=2
	incq	%r12
	incl	%ebp
	cmpq	$10, %r12
	jne	.LBB2_2
# %bb.5:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB2_1
# %bb.6:                                # %.preheader.preheader
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	xorl	%ebp, %ebp
.LBB2_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_9 Depth 2
	leaq	(%rax,%rax,2), %rdx
	movq	(%r13,%rdx,8), %rcx
	testq	%rcx, %rcx
	je	.LBB2_10
# %bb.8:                                # %.lr.ph
                                        #   in Loop: Header=BB2_7 Depth=1
	movq	16(%r13,%rdx,8), %rdx
	movq	%rcx, %rsi
.LBB2_9:                                #   Parent Loop BB2_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	addl	(%rdx), %ebp
	addq	$40, %rdx
	decq	%rsi
	jne	.LBB2_9
.LBB2_10:                               # %._crit_edge
                                        #   in Loop: Header=BB2_7 Depth=1
	addl	%ecx, %ebx
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB2_7
# %bb.11:
	movq	%r13, 88(%rsp)                  # 8-byte Spill
	movl	$160, %edi
	callq	malloc
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	%ebx, 32(%rsp)                  # 4-byte Spill
	movslq	%ebx, %rdi
	shlq	$5, %rdi
	movq	%rdi, 72(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movslq	%ebp, %rax
	shlq	$3, %rax
	leaq	(%rax,%rax,2), %rdi
	movq	%rdi, 80(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, %r13
	xorl	%eax, %eax
	xorl	%r11d, %r11d
	xorl	%esi, %esi
.LBB2_12:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_15 Depth 2
                                        #       Child Loop BB2_17 Depth 3
	leaq	(%rax,%rax,2), %rdi
	movq	88(%rsp), %rcx                  # 8-byte Reload
	movq	(%rcx,%rdi,8), %rdx
	movq	%rax, %r8
	shlq	$4, %r8
	movq	48(%rsp), %r10                  # 8-byte Reload
	movq	%rdx, (%r10,%r8)
	movq	8(%rcx,%rdi,8), %r9
	movq	%r9, 8(%r10,%r8)
	testq	%rdx, %rdx
	movl	%r11d, 36(%rsp)                 # 4-byte Spill
	je	.LBB2_13
# %bb.14:                               # %.lr.ph175
                                        #   in Loop: Header=BB2_12 Depth=1
	movq	16(%rcx,%rdi,8), %rdi
	movslq	%r11d, %r8
	shlq	$5, %r8
	movq	40(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%r8), %r9
	leaq	(%rcx,%r8), %r10
	addq	$4, %r10
	xorl	%r11d, %r11d
.LBB2_15:                               #   Parent Loop BB2_12 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_17 Depth 3
	leaq	(%r11,%r11,4), %r15
	movl	(%rdi,%r15,8), %r8d
	movl	%r8d, (%r9)
	movl	4(%rdi,%r15,8), %ebx
	movl	%ebx, (%r10)
	movl	8(%rdi,%r15,8), %ebx
	movl	%ebx, 4(%r10)
	movl	12(%rdi,%r15,8), %ebx
	movl	%ebx, 8(%r10)
	movl	16(%rdi,%r15,8), %ebx
	movl	%ebx, 12(%r10)
	movss	20(%rdi,%r15,8), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 16(%r10)
	movq	24(%rdi,%r15,8), %rbx
	movq	%rbx, 20(%r10)
	testl	%r8d, %r8d
	jle	.LBB2_18
# %bb.16:                               # %.lr.ph169
                                        #   in Loop: Header=BB2_15 Depth=2
	movq	32(%rdi,%r15,8), %r15
	movslq	%esi, %rbx
	leaq	(%rbx,%rbx,2), %rbx
	leaq	(,%rbx,8), %r12
	addq	%r13, %r12
	leaq	(,%r8,8), %rbx
	leaq	(%rbx,%rbx,2), %rbx
	xorl	%r14d, %r14d
.LBB2_17:                               #   Parent Loop BB2_12 Depth=1
                                        #     Parent Loop BB2_15 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	(%r15,%r14), %rcx
	movq	%rcx, (%r12)
	movl	8(%r15,%r14), %ecx
	movl	%ecx, 8(%r12)
	movl	12(%r15,%r14), %ecx
	movl	%ecx, 12(%r12)
	movl	16(%r15,%r14), %ecx
	movl	%ecx, 16(%r12)
	addq	$24, %r14
	cmpq	%r14, %rbx
	jne	.LBB2_17
.LBB2_18:                               # %._crit_edge170
                                        #   in Loop: Header=BB2_15 Depth=2
	addl	%esi, %r8d
	incq	%r11
	movl	%r8d, %esi
	cmpq	%rdx, %r11
	jne	.LBB2_15
	jmp	.LBB2_19
.LBB2_13:                               #   in Loop: Header=BB2_12 Depth=1
	movl	%esi, %r8d
.LBB2_19:                               # %._crit_edge176
                                        #   in Loop: Header=BB2_12 Depth=1
	movl	36(%rsp), %r11d                 # 4-byte Reload
	addl	%edx, %r11d
	incq	%rax
	movl	%r8d, %esi
	cmpq	$10, %rax
	jne	.LBB2_12
# %bb.20:
	leaq	64(%rsp), %r14
	movl	$160, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$163, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	leaq	16(%rsp), %rdi
	movq	72(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$164, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	movq	80(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$165, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movq	(%r14), %rdi
	movl	$160, %edx
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$168, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$170, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movq	(%r12), %rdi
	movq	%r13, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$172, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movl	$.L.str.2, %edi
	movl	$10, %esi
	movl	32(%rsp), %ebx                  # 4-byte Reload
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	printf
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_22
# %bb.21:
	movq	64(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	56(%rsp), %r9
	movq	24(%rsp), %rax
	movq	%rax, (%rsp)
	movl	$10, %edi
	movl	%ebx, %esi
	movl	%ebp, %edx
	callq	_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.LBB2_22:
	callq	hipPeekAtLastError
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$177, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	callq	hipDeviceSynchronize
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$178, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movq	24(%rsp), %rsi
	leaq	100(%rsp), %rbx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$179, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movl	(%rbx), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str, 21

	.type	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@object # @_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.section	.rodata,"a",@progbits
	.globl	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.p2align	3, 0x0
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
	.quad	_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.size	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/vuongpd95/cuda-test/master/deepCopy_2/deepCopy_2.hip"
	.size	.L.str.1, 115

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"n = %d, n_a = %d\n"
	.size	.L.str.2, 18

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"d_b = %d\n"
	.size	.L.str.3, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi"
	.size	.L__unnamed_1, 64

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi ; -- Begin function _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.globl	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
	.p2align	8
	.type	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@function
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi: ; @_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x28
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	global_store_b32 v0, v0, s[8:9]
	s_cbranch_scc1 .LBB0_6
; %bb.1:                                ; %.lr.ph20
	s_load_b128 s[4:7], s[0:1], 0x10
	s_cmp_gt_i32 s3, 0
	s_mov_b32 s11, 0
	s_cselect_b32 s0, -1, 0
	s_mov_b32 s10, s11
	v_cndmask_b32_e64 v1, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v1
	v_mov_b32_e32 v1, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_lshl_b64 s[12:13], s[10:11], 4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
	s_and_b32 vcc_lo, exec_lo, s0
	s_load_b32 s1, s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, s1, v1
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_vccnz .LBB0_5
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b64 s[12:13], s[6:7]
	s_mov_b32 s1, s3
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v0, s[12:13]
	s_add_i32 s1, s1, -1
	s_add_u32 s12, s12, 32
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v1, v2
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_scc1 .LBB0_4
.LBB0_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, s2
	s_cbranch_scc1 .LBB0_2
.LBB0_6:                                ; %._crit_edge21
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 14
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .Lfunc_end0-_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 220
; NumSgprs: 16
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
