#include <iostream>

#define THREADS_PER_BLOCK 8

__global__ void bitonicSortKernel(int *arr, int j, int k, int n) {
  int i = threadIdx.x + blockIdx.x * blockDim.x;
  int l = i ^ j;
  if (i < l && l < n) {
    int dir = i & k;
    if ((dir == 0 && arr[i] > arr[l]) || (dir != 0 && arr[i] < arr[l])) {
      int temp = arr[i];
      arr[i] = arr[l];
      arr[l] = temp;
    }
  }
}

void bitonicSortPower2(int *array, int n) {
  int threads = n / 2;
  int blocks = (threads + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK;
  for (int k = 2; k <= n; k *= 2)
    for (int j = k / 2; j > 0; j /= 2)
      bitonicSortKernel<<<blocks, THREADS_PER_BLOCK>>>(array, j, k, n);
}

int maxPowerLessThan(int n) {
  int ret = 1;
  n = n / 2;
  while (n) {
    ret *= 2;
    n /= 2;
  }
  return ret;
}

void bitonicSort(int *array, int n) {
  int len = maxPowerLessThan(n);
  bitonicSortPower2(array, len);
  bitonicSortPower2(&array[n - len], len);
  int offset = (n - len) / 2;
  bitonicSortPower2(&array[offset], len);
  bitonicSortPower2(array, len);
  bitonicSortPower2(&array[n - len], len);
  bitonicSortPower2(&array[offset], len);
}

int main() {
  int n = 15;
  int *h_arr;
  h_arr = (int *)malloc(n * sizeof(int));
  for (int i = 0; i < n; i++) {
    h_arr[i] = n - i;
  }
  int *d_arr;
  cudaMalloc((void **)&d_arr, n * sizeof(int));
  cudaMemcpy(d_arr, h_arr, n * sizeof(int), cudaMemcpyHostToDevice);
  bitonicSort(d_arr, n);
  cudaMemcpy(h_arr, d_arr, n * sizeof(int), cudaMemcpyDeviceToHost);
  for (int i = 0; i < n; i++) {
    std::cout << h_arr[i] << " ";
  }
}
	.file	"tmpxft_0034fa07_00000000-6_sort.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z16maxPowerLessThani
	.type	_Z16maxPowerLessThani, @function
_Z16maxPowerLessThani:
.LFB3636:
	.cfi_startproc
	endbr64
	movl	%edi, %eax
	movl	$2, %ecx
	movl	$2, %esi
	cltd
	idivl	%ecx
	movl	$1, %ecx
.L3:
	testl	%eax, %eax
	je	.L6
	cltd
	addl	%ecx, %ecx
	idivl	%esi
	jmp	.L3
.L6:
	movl	%ecx, %eax
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z16maxPowerLessThani, .-_Z16maxPowerLessThani
	.globl	_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii
	.type	_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii, @function
_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17bitonicSortKernelPiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L7:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii, .-_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii
	.globl	_Z17bitonicSortKernelPiiii
	.type	_Z17bitonicSortKernelPiiii, @function
_Z17bitonicSortKernelPiiii:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii
	.cfi_endproc
.LFE3664:
	.size	_Z17bitonicSortKernelPiiii, .-_Z17bitonicSortKernelPiiii
	.globl	_Z17bitonicSortPower2Pii
	.type	_Z17bitonicSortPower2Pii, @function
_Z17bitonicSortPower2Pii:
.LFB3635:
	.cfi_startproc
	endbr64
	movl	%esi, %eax
	movl	$2, %ecx
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movabsq	$4294967304, %r15
	cltd
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	idivl	%ecx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$8, %ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	%esi, %ebx
	movl	$2, %ebp
	addl	$7, %eax
	cltd
	idivl	%ecx
	movl	%eax, %r13d
.L13:
	cmpl	%ebx, %ebp
	jg	.L19
	movl	%ebp, %eax
	movl	$2, %ecx
	cltd
	idivl	%ecx
	movl	%eax, %r12d
.L14:
	testl	%r12d, %r12d
	jle	.L20
	movl	%r13d, 8(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movl	%ebx, %ecx
	movl	%ebp, %edx
	movl	%r12d, %esi
	movq	%r14, %rdi
	call	_Z40__device_stub__Z17bitonicSortKernelPiiiiPiiii
.L15:
	sarl	%r12d
	jmp	.L14
.L20:
	addl	%ebp, %ebp
	jmp	.L13
.L19:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z17bitonicSortPower2Pii, .-_Z17bitonicSortPower2Pii
	.globl	_Z11bitonicSortPii
	.type	_Z11bitonicSortPii, @function
_Z11bitonicSortPii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	movl	%esi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%esi, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 48
	call	_Z16maxPowerLessThani
	movq	%rbp, %rdi
	movl	%eax, %r12d
	movl	%eax, %esi
	call	_Z17bitonicSortPower2Pii
	subl	%r12d, %ebx
	movl	%r12d, %esi
	movslq	%ebx, %rax
	leaq	0(%rbp,%rax,4), %r13
	movq	%r13, %rdi
	call	_Z17bitonicSortPower2Pii
	movl	%ebx, %eax
	movl	$2, %ecx
	movl	%r12d, %esi
	cltd
	idivl	%ecx
	cltq
	leaq	0(%rbp,%rax,4), %rbx
	movq	%rbx, %rdi
	call	_Z17bitonicSortPower2Pii
	movl	%r12d, %esi
	movq	%rbp, %rdi
	call	_Z17bitonicSortPower2Pii
	movl	%r12d, %esi
	movq	%r13, %rdi
	call	_Z17bitonicSortPower2Pii
	popq	%rdx
	.cfi_def_cfa_offset 40
	movl	%r12d, %esi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z17bitonicSortPower2Pii
	.cfi_endproc
.LFE3637:
	.size	_Z11bitonicSortPii, .-_Z11bitonicSortPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$60, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$15, %ecx
	movq	%rax, %rbx
	xorl	%eax, %eax
.L24:
	movl	%ecx, %edx
	subl	%eax, %edx
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	cmpq	$15, %rax
	jne	.L24
	movq	%rsp, %rdi
	movl	$60, %esi
	xorl	%ebp, %ebp
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$60, %edx
	leaq	_ZSt4cout(%rip), %r12
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	movl	$15, %esi
	call	_Z11bitonicSortPii
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$60, %edx
	call	cudaMemcpy@PLT
.L25:
	movl	(%rbx,%rbp,4), %esi
	movq	%r12, %rdi
	incq	%rbp
	call	_ZNSolsEi@PLT
	movl	$1, %edx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$15, %rbp
	jne	.L25
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z17bitonicSortKernelPiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17bitonicSortKernelPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>

#define THREADS_PER_BLOCK 8

__global__ void bitonicSortKernel(int *arr, int j, int k, int n) {
  int i = threadIdx.x + blockIdx.x * blockDim.x;
  int l = i ^ j;
  if (i < l && l < n) {
    int dir = i & k;
    if ((dir == 0 && arr[i] > arr[l]) || (dir != 0 && arr[i] < arr[l])) {
      int temp = arr[i];
      arr[i] = arr[l];
      arr[l] = temp;
    }
  }
}

void bitonicSortPower2(int *array, int n) {
  int threads = n / 2;
  int blocks = (threads + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK;
  for (int k = 2; k <= n; k *= 2)
    for (int j = k / 2; j > 0; j /= 2)
      bitonicSortKernel<<<blocks, THREADS_PER_BLOCK>>>(array, j, k, n);
}

int maxPowerLessThan(int n) {
  int ret = 1;
  n = n / 2;
  while (n) {
    ret *= 2;
    n /= 2;
  }
  return ret;
}

void bitonicSort(int *array, int n) {
  int len = maxPowerLessThan(n);
  bitonicSortPower2(array, len);
  bitonicSortPower2(&array[n - len], len);
  int offset = (n - len) / 2;
  bitonicSortPower2(&array[offset], len);
  bitonicSortPower2(array, len);
  bitonicSortPower2(&array[n - len], len);
  bitonicSortPower2(&array[offset], len);
}

int main() {
  int n = 15;
  int *h_arr;
  h_arr = (int *)malloc(n * sizeof(int));
  for (int i = 0; i < n; i++) {
    h_arr[i] = n - i;
  }
  int *d_arr;
  hipMalloc((void **)&d_arr, n * sizeof(int));
  hipMemcpy(d_arr, h_arr, n * sizeof(int), hipMemcpyHostToDevice);
  bitonicSort(d_arr, n);
  hipMemcpy(h_arr, d_arr, n * sizeof(int), hipMemcpyDeviceToHost);
  for (int i = 0; i < n; i++) {
    std::cout << h_arr[i] << " ";
  }
}
	.text
	.file	"sort.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z32__device_stub__bitonicSortKernelPiiii # -- Begin function _Z32__device_stub__bitonicSortKernelPiiii
	.type	_Z32__device_stub__bitonicSortKernelPiiii,@function
_Z32__device_stub__bitonicSortKernelPiiii: # @_Z32__device_stub__bitonicSortKernelPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17bitonicSortKernelPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__bitonicSortKernelPiiii, .Lfunc_end0-_Z32__device_stub__bitonicSortKernelPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z17bitonicSortPower2Pii        # -- Begin function _Z17bitonicSortPower2Pii
	.type	_Z17bitonicSortPower2Pii,@function
_Z17bitonicSortPower2Pii:               # @_Z17bitonicSortPower2Pii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, (%rsp)                    # 8-byte Spill
	cmpl	$2, %esi
	jl	.LBB1_7
# %bb.1:                                # %.preheader.lr.ph
	movl	%esi, %ebx
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	%esi, %r12d
	shrl	%r12d
	addl	$7, %r12d
	shrl	$3, %r12d
	btsq	$32, %r12
	movl	$2, %ebp
	addq	$8, %r15
.LBB1_2:                                # %.lr.ph.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	movl	%ebp, %r13d
	movl	%ebp, %r14d
.LBB1_3:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	shrl	%r14d
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=2
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	%r14d, %esi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	callq	_Z32__device_stub__bitonicSortKernelPiiii
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=2
	cmpl	$4, %r13d
	movl	%r14d, %r13d
	jae	.LBB1_3
# %bb.6:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	addl	%ebp, %ebp
	cmpl	%ebx, %ebp
	jle	.LBB1_2
.LBB1_7:                                # %._crit_edge26
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z17bitonicSortPower2Pii, .Lfunc_end1-_Z17bitonicSortPower2Pii
	.cfi_endproc
                                        # -- End function
	.globl	_Z16maxPowerLessThani           # -- Begin function _Z16maxPowerLessThani
	.type	_Z16maxPowerLessThani,@function
_Z16maxPowerLessThani:                  # @_Z16maxPowerLessThani
	.cfi_startproc
# %bb.0:
                                        # kill: def $edi killed $edi def $rdi
	leal	1(%rdi), %ecx
	movl	$1, %eax
	cmpl	$3, %ecx
	jb	.LBB2_2
.LBB2_1:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%edi, %ecx
	shrl	$31, %ecx
	addl	%edi, %ecx
	sarl	%ecx
	addl	%eax, %eax
	leal	1(%rcx), %edx
	movl	%ecx, %edi
	cmpl	$2, %edx
	ja	.LBB2_1
.LBB2_2:                                # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z16maxPowerLessThani, .Lfunc_end2-_Z16maxPowerLessThani
	.cfi_endproc
                                        # -- End function
	.globl	_Z11bitonicSortPii              # -- Begin function _Z11bitonicSortPii
	.type	_Z11bitonicSortPii,@function
_Z11bitonicSortPii:                     # @_Z11bitonicSortPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %r15d
	movq	%rdi, %r14
	leal	1(%r15), %eax
	movl	$1, %ebx
	cmpl	$3, %eax
	jb	.LBB3_3
# %bb.1:                                # %.lr.ph.i.preheader
	movl	%r15d, %eax
.LBB3_2:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	sarl	%ecx
	addl	%ebx, %ebx
	leal	1(%rcx), %edx
	movl	%ecx, %eax
	cmpl	$2, %edx
	ja	.LBB3_2
.LBB3_3:                                # %_Z16maxPowerLessThani.exit
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_Z17bitonicSortPower2Pii
	subl	%ebx, %r15d
	movslq	%r15d, %r12
	leaq	(%r14,%r12,4), %r15
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_Z17bitonicSortPower2Pii
	movl	%r12d, %eax
	shrl	$31, %eax
	addl	%r12d, %eax
	sarl	%eax
	cltq
	leaq	(%r14,%rax,4), %r12
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_Z17bitonicSortPower2Pii
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_Z17bitonicSortPower2Pii
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_Z17bitonicSortPower2Pii
	movq	%r12, %rdi
	movl	%ebx, %esi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z17bitonicSortPower2Pii        # TAILCALL
.Lfunc_end3:
	.size	_Z11bitonicSortPii, .Lfunc_end3-_Z11bitonicSortPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$60, %edi
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	xorl	$15, %ecx
	movl	%ecx, (%rbx,%rax,4)
	incq	%rax
	cmpq	$15, %rax
	jne	.LBB4_1
# %bb.2:
	movq	%rsp, %r14
	movl	$60, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$60, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movl	$15, %esi
	callq	_Z11bitonicSortPii
	movq	(%r14), %rsi
	movl	$60, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r14
	cmpq	$15, %r14
	jne	.LBB4_3
# %bb.4:
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17bitonicSortKernelPiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17bitonicSortKernelPiiii,@object # @_Z17bitonicSortKernelPiiii
	.section	.rodata,"a",@progbits
	.globl	_Z17bitonicSortKernelPiiii
	.p2align	3, 0x0
_Z17bitonicSortKernelPiiii:
	.quad	_Z32__device_stub__bitonicSortKernelPiiii
	.size	_Z17bitonicSortKernelPiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" "
	.size	.L.str, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17bitonicSortKernelPiiii"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__bitonicSortKernelPiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17bitonicSortKernelPiiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17bitonicSortKernelPiiii ; -- Begin function _Z17bitonicSortKernelPiiii
	.globl	_Z17bitonicSortKernelPiiii
	.p2align	8
	.type	_Z17bitonicSortKernelPiiii,@function
_Z17bitonicSortKernelPiiii:             ; @_Z17bitonicSortKernelPiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	v_xor_b32_e32 v0, s4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v4, v0
	v_cmp_gt_i32_e64 s2, s6, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_7
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_and_b32_e32 v4, s5, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
	s_mov_b32 s0, 0
	s_clause 0x1
	global_load_b32 v5, v[0:1], off
	global_load_b32 v6, v[2:3], off
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u32_e32 0, v4
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v5, v6
	s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v5, v6
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s2
.LBB0_5:                                ; %Flow39
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b32 v[0:1], v6, off
	global_store_b32 v[2:3], v5, off
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17bitonicSortKernelPiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17bitonicSortKernelPiiii, .Lfunc_end0-_Z17bitonicSortKernelPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17bitonicSortKernelPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17bitonicSortKernelPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
