#include <iostream>
#include "../include/matrixMultiplication.cuh"

namespace blas3{

    namespace cudaBlas {

        __global__ void
        naiveMatrixMultiplication(float *MatA, float *MatB, float *result, size_t m, size_t n, size_t k) {
            unsigned int column_id = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_id = blockIdx.y * blockDim.y + threadIdx.y;

            float sum = 0.0f;

            if (row_id < m && column_id < k) {

                for (size_t i = 0; i < k; i++) {
                    sum += MatA[n * row_id + i] * MatB[i * k + column_id];
                }
                result[row_id * n + column_id] = sum;
            }
        }


        __global__ void
        sharedMatrixMultiplication(float *MatA, float *MatB, float *result, size_t M, size_t K, size_t N) {
            /*
             * Matrix Multiplication with
             * Tiling
             * Coalesced Access
             * No Bank Conflict
             * */
#define BLOCK_SIZE 32

            unsigned int block_x_id = blockIdx.x;
            unsigned int block_y_id = blockIdx.y;

            unsigned int thread_x_id = threadIdx.x;
            unsigned int thread_y_id = threadIdx.y;

            __shared__ float A_shared[BLOCK_SIZE][BLOCK_SIZE];
            __shared__ float B_shared[BLOCK_SIZE][BLOCK_SIZE];

            auto a_start_index = K * BLOCK_SIZE * block_y_id;
            auto a_end = a_start_index + K - 1;
            int a_step = BLOCK_SIZE;

            auto b_start_index = BLOCK_SIZE * block_x_id;
            auto b_step = BLOCK_SIZE * N;

            float sum = 0.0f;

            for (int a = a_start_index, b = b_start_index; a <= a_end; a += a_step, b += b_step) {
                A_shared[thread_y_id][thread_x_id] = MatA[a + K * thread_y_id + thread_x_id];
                B_shared[thread_y_id][thread_x_id] = MatB[b + N * thread_y_id + thread_x_id];

                __syncthreads();


#pragma unroll
                for (int k = 0; k < BLOCK_SIZE; k++) {
                    sum += A_shared[thread_y_id][k] * B_shared[k][thread_x_id];
                }

                __syncthreads();
            }

            auto result_index = N * BLOCK_SIZE * block_y_id + BLOCK_SIZE * block_x_id;
            result[result_index + N * thread_y_id + thread_x_id] = sum;


        }


        __global__ void
        MatrixMultiplication_reducedOps32(float *MatA, float *MatB, float *result, size_t M, size_t N, size_t K) {
            const int TILE_SIZE = 32;
            const int VECTOR_SIZE = 4;

            unsigned int block_x = blockIdx.x;
            unsigned int thread_x = threadIdx.x;
            unsigned int block_y = blockIdx.y;
            unsigned int thread_y = threadIdx.y;

            __shared__ float A_shared[TILE_SIZE * TILE_SIZE];
            float result_vector[TILE_SIZE] = {0};

            auto a_start_index = K * TILE_SIZE * block_y;
            auto a_end = a_start_index + K - 1;
            auto a_step = TILE_SIZE;

            auto b_start_index = TILE_SIZE * VECTOR_SIZE * block_x;
            auto b_step = TILE_SIZE * N;

            for (int a = a_start_index, b = b_start_index; a <= a_end; a += a_step, b += b_step) {

#pragma unroll
                for (int i = 0; i < TILE_SIZE / VECTOR_SIZE; ++i) {

                    A_shared[(i * VECTOR_SIZE + thread_y) + TILE_SIZE * thread_x] =
                            MatA[a + K * (i * VECTOR_SIZE + thread_y) + thread_x];
                }
                __syncthreads();

                float *a_shared_base = A_shared;
                float *b_base = MatB + b + TILE_SIZE * thread_y + thread_x;

#pragma unroll
                for (int i = 0; i < TILE_SIZE; i++) {
                    float b_value = *b_base;

                    result_vector[0] += a_shared_base[0] * b_value;
                    result_vector[1] += a_shared_base[1] * b_value;
                    result_vector[2] += a_shared_base[2] * b_value;
                    result_vector[3] += a_shared_base[3] * b_value;
                    result_vector[4] += a_shared_base[4] * b_value;
                    result_vector[5] += a_shared_base[5] * b_value;
                    result_vector[6] += a_shared_base[6] * b_value;
                    result_vector[7] += a_shared_base[7] * b_value;
                    result_vector[8] += a_shared_base[8] * b_value;
                    result_vector[9] += a_shared_base[9] * b_value;

                    result_vector[10] += a_shared_base[10] * b_value;
                    result_vector[11] += a_shared_base[11] * b_value;
                    result_vector[12] += a_shared_base[12] * b_value;
                    result_vector[13] += a_shared_base[13] * b_value;
                    result_vector[14] += a_shared_base[14] * b_value;
                    result_vector[15] += a_shared_base[15] * b_value;
                    result_vector[16] += a_shared_base[16] * b_value;
                    result_vector[17] += a_shared_base[17] * b_value;
                    result_vector[18] += a_shared_base[18] * b_value;
                    result_vector[19] += a_shared_base[19] * b_value;

                    result_vector[20] += a_shared_base[20] * b_value;
                    result_vector[21] += a_shared_base[21] * b_value;
                    result_vector[22] += a_shared_base[22] * b_value;
                    result_vector[23] += a_shared_base[23] * b_value;
                    result_vector[24] += a_shared_base[24] * b_value;
                    result_vector[25] += a_shared_base[25] * b_value;
                    result_vector[26] += a_shared_base[26] * b_value;
                    result_vector[27] += a_shared_base[27] * b_value;
                    result_vector[28] += a_shared_base[28] * b_value;
                    result_vector[29] += a_shared_base[29] * b_value;

                    result_vector[30] += a_shared_base[30] * b_value;
                    result_vector[31] += a_shared_base[31] * b_value;

                    a_shared_base += TILE_SIZE;
                    b_base += N;
                }
                __syncthreads();
            }

            auto c_ptr = N * TILE_SIZE * block_y + TILE_SIZE * VECTOR_SIZE * block_x;
            c_ptr += TILE_SIZE * thread_y + thread_x;

#pragma unroll
            for (int i = 0; i < TILE_SIZE; ++i) {
                result[c_ptr] = result_vector[i];
                c_ptr += N;
            }
        }


        __global__ void
        MatrixMultiplication_reducedOps16(float *MatA, float *MatB, float *result, size_t M, size_t N, size_t K) {
            const int TILE_SIZE_16 = 16;
            const int VECTOR_SIZE = 4;

            unsigned int block_x = blockIdx.x;
            unsigned int thread_x = threadIdx.x;
            unsigned int block_y = blockIdx.y;
            unsigned int thread_y = threadIdx.y;

            __shared__ float A_shared[TILE_SIZE_16 * TILE_SIZE_16];
            float result_vector[TILE_SIZE_16] = {0};

            auto a_start_index = K * TILE_SIZE_16 * block_y;
            auto a_end = a_start_index + K - 1;
            auto a_step = TILE_SIZE_16;

            auto b_start_index = TILE_SIZE_16 * VECTOR_SIZE * block_x;
            auto b_step = TILE_SIZE_16 * N;

            for (int a = a_start_index, b = b_start_index; a <= a_end; a += a_step, b += b_step) {
#pragma unroll
                for (int i = 0; i < TILE_SIZE_16 / VECTOR_SIZE; ++i) {
                    A_shared[(i * VECTOR_SIZE + thread_y) + TILE_SIZE_16 * thread_x] =
                            MatA[a + K * (i * VECTOR_SIZE + thread_y) + thread_x];
                }
                __syncthreads();

                float *a_shared_base = A_shared;
                float *b_base = MatB + b + TILE_SIZE_16 * thread_y + thread_x;

#pragma unroll
                for (int i = 0; i < TILE_SIZE_16; i++) {
                    float b_value = *b_base;
                    result_vector[0] += a_shared_base[0] * b_value;
                    result_vector[1] += a_shared_base[1] * b_value;
                    result_vector[2] += a_shared_base[2] * b_value;
                    result_vector[3] += a_shared_base[3] * b_value;
                    result_vector[4] += a_shared_base[4] * b_value;
                    result_vector[5] += a_shared_base[5] * b_value;
                    result_vector[6] += a_shared_base[6] * b_value;
                    result_vector[7] += a_shared_base[7] * b_value;
                    result_vector[8] += a_shared_base[8] * b_value;
                    result_vector[9] += a_shared_base[9] * b_value;

                    result_vector[10] += a_shared_base[10] * b_value;
                    result_vector[11] += a_shared_base[11] * b_value;
                    result_vector[12] += a_shared_base[12] * b_value;
                    result_vector[13] += a_shared_base[13] * b_value;
                    result_vector[14] += a_shared_base[14] * b_value;
                    result_vector[15] += a_shared_base[15] * b_value;

                    a_shared_base += TILE_SIZE_16;
                    b_base += N;
                }
                __syncthreads();
            }

            auto c_ptr = N * TILE_SIZE_16 * block_y + TILE_SIZE_16 * VECTOR_SIZE * block_x;
            c_ptr += TILE_SIZE_16 * thread_y + thread_x;

#pragma unroll
            for (int i = 0; i < TILE_SIZE_16; ++i) {
                result[c_ptr] = result_vector[i];
                c_ptr += N;
            }
        }

        __global__ void sharedGEMM(float *MatA, float *MatB, float *Result, size_t M, size_t N, size_t K) {
            const unsigned int TILE_SIZE = 32;

            unsigned int row_id = blockIdx.y * TILE_SIZE + threadIdx.y;
            unsigned int column_id = blockIdx.x * TILE_SIZE + threadIdx.x;

            __shared__ float A_shared[TILE_SIZE][TILE_SIZE];
            __shared__ float B_shared[TILE_SIZE][TILE_SIZE];

            float sum = 0.0f;

            for (size_t m = 0; m < (TILE_SIZE + N - 1) / TILE_SIZE; m++) {
                if (m * TILE_SIZE + threadIdx.x < N and row_id < M)
                    A_shared[threadIdx.y][threadIdx.x] = MatA[row_id * N + m * TILE_SIZE + threadIdx.x];
                else
                    A_shared[threadIdx.y][threadIdx.x] = 0.0f;

                if (m * TILE_SIZE + threadIdx.y < N && column_id < K) {
                    B_shared[threadIdx.y][threadIdx.x] = MatB[(m * TILE_SIZE + threadIdx.y) * K +
                                                              column_id]; //Coalesced ??
                } else
                    B_shared[threadIdx.y][threadIdx.x] = 0.0f;

                __syncthreads();


                for (int n = 0; n < TILE_SIZE; n++) {
                    sum += A_shared[threadIdx.y][n] * B_shared[n][threadIdx.x];
                }
                __syncthreads();
            }
            if (row_id < M and column_id < K) {
                Result[((blockIdx.y * blockDim.y + threadIdx.y) * K) +
                       blockIdx.x * blockDim.x + threadIdx.x] = sum;
            }
        }
    }

}

/*
int main(){
    size_t m = 102;
    size_t n = 604;
    size_t k = 366;

    float* h_a, *h_b, *h_c;
    float* d_a, *d_b, *d_c;

    h_a = (float*) malloc(m * n * sizeof(float ));
    h_b = (float*) malloc(n * k * sizeof(float ));
    h_c = (float*) malloc(m * k * sizeof(float ));

    cudaMalloc(&d_a, m * n * sizeof(float ));
    cudaMalloc(&d_b, n * k * sizeof(float ));
    cudaMalloc(&d_c, m * k * sizeof(float ));


    for(int i = 0; i < m * n;i++){
        h_a[i] = 1.0f;
    }

    for(int i=0; i< n*k; i++){
        h_b[i] = 1.0f;
    }

    cudaMemcpy(d_a, h_a, m * n * sizeof(float ), cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, n * k * sizeof(float ), cudaMemcpyHostToDevice);

    dim3 threads(32, 32);
    dim3 blocksPerGrid((n - 1) / threads.x + 1, (n - 1) / threads.y + 1);

    blas3::sharedGEMM<<<blocksPerGrid, threads>>>(d_a, d_b, d_c, m ,n, k);
    cudaDeviceSynchronize();
    cudaMemcpy(h_c, d_c, m * k * sizeof(float ), cudaMemcpyDeviceToHost);
    for(int i=0; i<500; i++){
        std::cout<<h_c[i]<<"  ";
    }
    std::cout<<std::endl;
}

 */
	.file	"tmpxft_002cc107_00000000-6_matrixMultiplication.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3637:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3637:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z71__device_stub__ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm
	.type	_Z71__device_stub__ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm, @function
_Z71__device_stub__ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm:
.LFB3659:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3659:
	.size	_Z71__device_stub__ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm, .-_Z71__device_stub__ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm
	.globl	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm, @function
_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm:
.LFB3660:
	.cfi_startproc
	endbr64
	jmp	_Z71__device_stub__ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm
	.cfi_endproc
.LFE3660:
	.size	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm, .-_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.globl	_Z72__device_stub__ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm
	.type	_Z72__device_stub__ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm, @function
_Z72__device_stub__ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z72__device_stub__ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm, .-_Z72__device_stub__ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm
	.globl	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm, @function
_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z72__device_stub__ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmmPfS_S_mmm
	.cfi_endproc
.LFE3662:
	.size	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm, .-_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.globl	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmmPfS_S_mmm
	.type	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmmPfS_S_mmm, @function
_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmmPfS_S_mmm:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmmPfS_S_mmm, .-_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmmPfS_S_mmm
	.globl	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm, @function
_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmmPfS_S_mmm
	.cfi_endproc
.LFE3664:
	.size	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm, .-_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.globl	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmmPfS_S_mmm
	.type	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmmPfS_S_mmm, @function
_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmmPfS_S_mmm:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L18:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmmPfS_S_mmm, .-_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmmPfS_S_mmm
	.globl	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm, @function
_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmmPfS_S_mmm
	.cfi_endproc
.LFE3666:
	.size	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm, .-_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.globl	_Z56__device_stub__ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmmPfS_S_mmm
	.type	_Z56__device_stub__ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmmPfS_S_mmm, @function
_Z56__device_stub__ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmmPfS_S_mmm:
.LFB3667:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L23:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_Z56__device_stub__ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmmPfS_S_mmm, .-_Z56__device_stub__ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmmPfS_S_mmm
	.globl	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm, @function
_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmmPfS_S_mmm
	.cfi_endproc
.LFE3668:
	.size	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm, .-_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm"
.LC1:
	.string	"_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm"
.LC2:
	.string	"_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm"
.LC3:
	.string	"_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm"
.LC4:
	.string	"_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3670:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3670:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include "../include/matrixMultiplication.cuh"

namespace blas3{

    namespace cudaBlas {

        __global__ void
        naiveMatrixMultiplication(float *MatA, float *MatB, float *result, size_t m, size_t n, size_t k) {
            unsigned int column_id = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_id = blockIdx.y * blockDim.y + threadIdx.y;

            float sum = 0.0f;

            if (row_id < m && column_id < k) {

                for (size_t i = 0; i < k; i++) {
                    sum += MatA[n * row_id + i] * MatB[i * k + column_id];
                }
                result[row_id * n + column_id] = sum;
            }
        }


        __global__ void
        sharedMatrixMultiplication(float *MatA, float *MatB, float *result, size_t M, size_t K, size_t N) {
            /*
             * Matrix Multiplication with
             * Tiling
             * Coalesced Access
             * No Bank Conflict
             * */
#define BLOCK_SIZE 32

            unsigned int block_x_id = blockIdx.x;
            unsigned int block_y_id = blockIdx.y;

            unsigned int thread_x_id = threadIdx.x;
            unsigned int thread_y_id = threadIdx.y;

            __shared__ float A_shared[BLOCK_SIZE][BLOCK_SIZE];
            __shared__ float B_shared[BLOCK_SIZE][BLOCK_SIZE];

            auto a_start_index = K * BLOCK_SIZE * block_y_id;
            auto a_end = a_start_index + K - 1;
            int a_step = BLOCK_SIZE;

            auto b_start_index = BLOCK_SIZE * block_x_id;
            auto b_step = BLOCK_SIZE * N;

            float sum = 0.0f;

            for (int a = a_start_index, b = b_start_index; a <= a_end; a += a_step, b += b_step) {
                A_shared[thread_y_id][thread_x_id] = MatA[a + K * thread_y_id + thread_x_id];
                B_shared[thread_y_id][thread_x_id] = MatB[b + N * thread_y_id + thread_x_id];

                __syncthreads();


#pragma unroll
                for (int k = 0; k < BLOCK_SIZE; k++) {
                    sum += A_shared[thread_y_id][k] * B_shared[k][thread_x_id];
                }

                __syncthreads();
            }

            auto result_index = N * BLOCK_SIZE * block_y_id + BLOCK_SIZE * block_x_id;
            result[result_index + N * thread_y_id + thread_x_id] = sum;


        }


        __global__ void
        MatrixMultiplication_reducedOps32(float *MatA, float *MatB, float *result, size_t M, size_t N, size_t K) {
            const int TILE_SIZE = 32;
            const int VECTOR_SIZE = 4;

            unsigned int block_x = blockIdx.x;
            unsigned int thread_x = threadIdx.x;
            unsigned int block_y = blockIdx.y;
            unsigned int thread_y = threadIdx.y;

            __shared__ float A_shared[TILE_SIZE * TILE_SIZE];
            float result_vector[TILE_SIZE] = {0};

            auto a_start_index = K * TILE_SIZE * block_y;
            auto a_end = a_start_index + K - 1;
            auto a_step = TILE_SIZE;

            auto b_start_index = TILE_SIZE * VECTOR_SIZE * block_x;
            auto b_step = TILE_SIZE * N;

            for (int a = a_start_index, b = b_start_index; a <= a_end; a += a_step, b += b_step) {

#pragma unroll
                for (int i = 0; i < TILE_SIZE / VECTOR_SIZE; ++i) {

                    A_shared[(i * VECTOR_SIZE + thread_y) + TILE_SIZE * thread_x] =
                            MatA[a + K * (i * VECTOR_SIZE + thread_y) + thread_x];
                }
                __syncthreads();

                float *a_shared_base = A_shared;
                float *b_base = MatB + b + TILE_SIZE * thread_y + thread_x;

#pragma unroll
                for (int i = 0; i < TILE_SIZE; i++) {
                    float b_value = *b_base;

                    result_vector[0] += a_shared_base[0] * b_value;
                    result_vector[1] += a_shared_base[1] * b_value;
                    result_vector[2] += a_shared_base[2] * b_value;
                    result_vector[3] += a_shared_base[3] * b_value;
                    result_vector[4] += a_shared_base[4] * b_value;
                    result_vector[5] += a_shared_base[5] * b_value;
                    result_vector[6] += a_shared_base[6] * b_value;
                    result_vector[7] += a_shared_base[7] * b_value;
                    result_vector[8] += a_shared_base[8] * b_value;
                    result_vector[9] += a_shared_base[9] * b_value;

                    result_vector[10] += a_shared_base[10] * b_value;
                    result_vector[11] += a_shared_base[11] * b_value;
                    result_vector[12] += a_shared_base[12] * b_value;
                    result_vector[13] += a_shared_base[13] * b_value;
                    result_vector[14] += a_shared_base[14] * b_value;
                    result_vector[15] += a_shared_base[15] * b_value;
                    result_vector[16] += a_shared_base[16] * b_value;
                    result_vector[17] += a_shared_base[17] * b_value;
                    result_vector[18] += a_shared_base[18] * b_value;
                    result_vector[19] += a_shared_base[19] * b_value;

                    result_vector[20] += a_shared_base[20] * b_value;
                    result_vector[21] += a_shared_base[21] * b_value;
                    result_vector[22] += a_shared_base[22] * b_value;
                    result_vector[23] += a_shared_base[23] * b_value;
                    result_vector[24] += a_shared_base[24] * b_value;
                    result_vector[25] += a_shared_base[25] * b_value;
                    result_vector[26] += a_shared_base[26] * b_value;
                    result_vector[27] += a_shared_base[27] * b_value;
                    result_vector[28] += a_shared_base[28] * b_value;
                    result_vector[29] += a_shared_base[29] * b_value;

                    result_vector[30] += a_shared_base[30] * b_value;
                    result_vector[31] += a_shared_base[31] * b_value;

                    a_shared_base += TILE_SIZE;
                    b_base += N;
                }
                __syncthreads();
            }

            auto c_ptr = N * TILE_SIZE * block_y + TILE_SIZE * VECTOR_SIZE * block_x;
            c_ptr += TILE_SIZE * thread_y + thread_x;

#pragma unroll
            for (int i = 0; i < TILE_SIZE; ++i) {
                result[c_ptr] = result_vector[i];
                c_ptr += N;
            }
        }


        __global__ void
        MatrixMultiplication_reducedOps16(float *MatA, float *MatB, float *result, size_t M, size_t N, size_t K) {
            const int TILE_SIZE_16 = 16;
            const int VECTOR_SIZE = 4;

            unsigned int block_x = blockIdx.x;
            unsigned int thread_x = threadIdx.x;
            unsigned int block_y = blockIdx.y;
            unsigned int thread_y = threadIdx.y;

            __shared__ float A_shared[TILE_SIZE_16 * TILE_SIZE_16];
            float result_vector[TILE_SIZE_16] = {0};

            auto a_start_index = K * TILE_SIZE_16 * block_y;
            auto a_end = a_start_index + K - 1;
            auto a_step = TILE_SIZE_16;

            auto b_start_index = TILE_SIZE_16 * VECTOR_SIZE * block_x;
            auto b_step = TILE_SIZE_16 * N;

            for (int a = a_start_index, b = b_start_index; a <= a_end; a += a_step, b += b_step) {
#pragma unroll
                for (int i = 0; i < TILE_SIZE_16 / VECTOR_SIZE; ++i) {
                    A_shared[(i * VECTOR_SIZE + thread_y) + TILE_SIZE_16 * thread_x] =
                            MatA[a + K * (i * VECTOR_SIZE + thread_y) + thread_x];
                }
                __syncthreads();

                float *a_shared_base = A_shared;
                float *b_base = MatB + b + TILE_SIZE_16 * thread_y + thread_x;

#pragma unroll
                for (int i = 0; i < TILE_SIZE_16; i++) {
                    float b_value = *b_base;
                    result_vector[0] += a_shared_base[0] * b_value;
                    result_vector[1] += a_shared_base[1] * b_value;
                    result_vector[2] += a_shared_base[2] * b_value;
                    result_vector[3] += a_shared_base[3] * b_value;
                    result_vector[4] += a_shared_base[4] * b_value;
                    result_vector[5] += a_shared_base[5] * b_value;
                    result_vector[6] += a_shared_base[6] * b_value;
                    result_vector[7] += a_shared_base[7] * b_value;
                    result_vector[8] += a_shared_base[8] * b_value;
                    result_vector[9] += a_shared_base[9] * b_value;

                    result_vector[10] += a_shared_base[10] * b_value;
                    result_vector[11] += a_shared_base[11] * b_value;
                    result_vector[12] += a_shared_base[12] * b_value;
                    result_vector[13] += a_shared_base[13] * b_value;
                    result_vector[14] += a_shared_base[14] * b_value;
                    result_vector[15] += a_shared_base[15] * b_value;

                    a_shared_base += TILE_SIZE_16;
                    b_base += N;
                }
                __syncthreads();
            }

            auto c_ptr = N * TILE_SIZE_16 * block_y + TILE_SIZE_16 * VECTOR_SIZE * block_x;
            c_ptr += TILE_SIZE_16 * thread_y + thread_x;

#pragma unroll
            for (int i = 0; i < TILE_SIZE_16; ++i) {
                result[c_ptr] = result_vector[i];
                c_ptr += N;
            }
        }

        __global__ void sharedGEMM(float *MatA, float *MatB, float *Result, size_t M, size_t N, size_t K) {
            const unsigned int TILE_SIZE = 32;

            unsigned int row_id = blockIdx.y * TILE_SIZE + threadIdx.y;
            unsigned int column_id = blockIdx.x * TILE_SIZE + threadIdx.x;

            __shared__ float A_shared[TILE_SIZE][TILE_SIZE];
            __shared__ float B_shared[TILE_SIZE][TILE_SIZE];

            float sum = 0.0f;

            for (size_t m = 0; m < (TILE_SIZE + N - 1) / TILE_SIZE; m++) {
                if (m * TILE_SIZE + threadIdx.x < N and row_id < M)
                    A_shared[threadIdx.y][threadIdx.x] = MatA[row_id * N + m * TILE_SIZE + threadIdx.x];
                else
                    A_shared[threadIdx.y][threadIdx.x] = 0.0f;

                if (m * TILE_SIZE + threadIdx.y < N && column_id < K) {
                    B_shared[threadIdx.y][threadIdx.x] = MatB[(m * TILE_SIZE + threadIdx.y) * K +
                                                              column_id]; //Coalesced ??
                } else
                    B_shared[threadIdx.y][threadIdx.x] = 0.0f;

                __syncthreads();


                for (int n = 0; n < TILE_SIZE; n++) {
                    sum += A_shared[threadIdx.y][n] * B_shared[n][threadIdx.x];
                }
                __syncthreads();
            }
            if (row_id < M and column_id < K) {
                Result[((blockIdx.y * blockDim.y + threadIdx.y) * K) +
                       blockIdx.x * blockDim.x + threadIdx.x] = sum;
            }
        }
    }

}

/*
int main(){
    size_t m = 102;
    size_t n = 604;
    size_t k = 366;

    float* h_a, *h_b, *h_c;
    float* d_a, *d_b, *d_c;

    h_a = (float*) malloc(m * n * sizeof(float ));
    h_b = (float*) malloc(n * k * sizeof(float ));
    h_c = (float*) malloc(m * k * sizeof(float ));

    cudaMalloc(&d_a, m * n * sizeof(float ));
    cudaMalloc(&d_b, n * k * sizeof(float ));
    cudaMalloc(&d_c, m * k * sizeof(float ));


    for(int i = 0; i < m * n;i++){
        h_a[i] = 1.0f;
    }

    for(int i=0; i< n*k; i++){
        h_b[i] = 1.0f;
    }

    cudaMemcpy(d_a, h_a, m * n * sizeof(float ), cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, n * k * sizeof(float ), cudaMemcpyHostToDevice);

    dim3 threads(32, 32);
    dim3 blocksPerGrid((n - 1) / threads.x + 1, (n - 1) / threads.y + 1);

    blas3::sharedGEMM<<<blocksPerGrid, threads>>>(d_a, d_b, d_c, m ,n, k);
    cudaDeviceSynchronize();
    cudaMemcpy(h_c, d_c, m * k * sizeof(float ), cudaMemcpyDeviceToHost);
    for(int i=0; i<500; i++){
        std::cout<<h_c[i]<<"  ";
    }
    std::cout<<std::endl;
}

 */
	.text
	.file	"matrixMultiplication.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm # -- Begin function _ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm,@function
_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm: # @_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm, .Lfunc_end0-_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm # -- Begin function _ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm,@function
_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm: # @_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm, .Lfunc_end1-_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm # -- Begin function _ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm,@function
_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm: # @_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm, .Lfunc_end2-_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm # -- Begin function _ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm,@function
_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm: # @_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm, .Lfunc_end3-_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm # -- Begin function _ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm
	.type	_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm,@function
_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm: # @_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm, .Lfunc_end4-_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm,@object # @_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.section	.rodata,"a",@progbits
	.globl	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.p2align	3, 0x0
_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm:
	.quad	_ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm
	.size	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm, 8

	.type	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm,@object # @_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.p2align	3, 0x0
_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm:
	.quad	_ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm
	.size	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm, 8

	.type	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm,@object # @_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.p2align	3, 0x0
_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm:
	.quad	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.size	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm, 8

	.type	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm,@object # @_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.p2align	3, 0x0
_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm:
	.quad	_ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.size	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm, 8

	.type	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm,@object # @_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.p2align	3, 0x0
_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm:
	.quad	_ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm
	.size	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm"
	.size	.L__unnamed_1, 58

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm"
	.size	.L__unnamed_2, 59

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm"
	.size	.L__unnamed_3, 66

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm"
	.size	.L__unnamed_4, 66

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm"
	.size	.L__unnamed_5, 43

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN5blas38cudaBlas40__device_stub__naiveMatrixMultiplicationEPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas41__device_stub__sharedMatrixMultiplicationEPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas48__device_stub__MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas25__device_stub__sharedGEMMEPfS1_S1_mmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.addrsig_sym _ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm ; -- Begin function _ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
	.p2align	8
	.type	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm,@function
_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm: ; @_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v4, v0, 10, 10
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s12, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s15, s12, v[4:5]
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[2:3]
	s_and_saveexec_b32 s10, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.1:
	s_load_b32 s10, s[2:3], 0xc
	s_load_b128 s[0:3], s[0:1], 0x20
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s10, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s14, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v3
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader
	v_mad_u64_u32 v[3:4], null, v2, s0, 0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v2, s1, v[4:5]
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[6:7], off
	global_load_b32 v10, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	s_add_u32 s2, s2, -1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_addc_u32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[2:3], 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v9, v10
	s_cbranch_scc0 .LBB0_3
; %bb.4:
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	global_store_b32 v[0:1], v8, off
.LBB0_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm, .Lfunc_end0-_ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm ; -- Begin function _ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
	.p2align	8
	.type	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm,@function
_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm: ; @_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 2, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s5, s15
	s_mul_hi_u32 s8, s4, s15
	s_mul_i32 s2, s4, s15
	s_add_i32 s3, s8, s3
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_lshl_b64 s[2:3], s[2:3], 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s4, s2
	s_addc_u32 s13, s5, s3
	s_add_u32 s16, s12, -1
	s_addc_u32 s17, s13, -1
	s_bfe_i64 s[18:19], s[2:3], 0x200000
	s_lshl_b32 s2, s14, 5
	v_cmp_ge_u64_e64 s3, s[16:17], s[18:19]
	s_lshl_b64 s[12:13], s[6:7], 5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_4
; %bb.1:                                ; %.lr.ph
	v_mad_u64_u32 v[8:9], null, v3, s4, 0
	v_mad_u64_u32 v[0:1], null, v3, s6, 0
	s_mov_b32 s4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v9
	v_mad_u64_u32 v[10:11], null, v3, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v3, s5, v[4:5]
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 7, v3
	v_add_nc_u32_e32 v7, v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v9, v6
	v_or_b32_e32 v6, 0x1000, v2
	v_mov_b32_e32 v1, v10
	v_lshlrev_b64 v[11:12], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, 0x800, v6
	v_lshlrev_b64 v[13:14], 2, v[0:1]
	v_add_nc_u32_e32 v8, v6, v5
	v_add_nc_u32_e32 v9, 0x400, v6
	v_add_nc_u32_e32 v15, 0xc00, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, v11, v2
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, v13, v2
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_lshl_b64 s[8:9], s[18:19], 2
	s_ashr_i32 s5, s4, 31
	v_add_co_u32 v16, vcc_lo, v11, s8
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v12, vcc_lo
	s_lshl_b64 s[8:9], s[4:5], 2
	s_add_i32 s18, s18, 32
	v_add_co_u32 v18, vcc_lo, v13, s8
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v14, vcc_lo
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	s_ashr_i32 s19, s18, 31
	s_add_i32 s4, s4, s12
	v_cmp_lt_u64_e64 s3, s[16:17], s[18:19]
	s_waitcnt vmcnt(1)
	ds_store_b32 v7, v16
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v17
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[24:25], v6 offset1:32
	ds_load_b128 v[16:19], v5
	ds_load_2addr_b32 v[26:27], v6 offset0:64 offset1:96
	ds_load_b128 v[20:23], v5 offset:16
	ds_load_2addr_b32 v[28:29], v6 offset0:128 offset1:160
	s_and_b32 vcc_lo, exec_lo, s3
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v16, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v17, v25
	ds_load_2addr_b32 v[24:25], v6 offset0:192 offset1:224
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v18, v26
	v_fmac_f32_e32 v4, v19, v27
	ds_load_2addr_b32 v[26:27], v9 offset1:32
	ds_load_b128 v[16:19], v5 offset:32
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v20, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v29
	ds_load_2addr_b32 v[28:29], v9 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v22, v24
	v_fmac_f32_e32 v4, v23, v25
	ds_load_b128 v[20:23], v5 offset:48
	ds_load_2addr_b32 v[24:25], v9 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v16, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v17, v27
	ds_load_2addr_b32 v[26:27], v9 offset0:192 offset1:224
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v18, v28
	v_fmac_f32_e32 v4, v19, v29
	ds_load_2addr_b32 v[28:29], v10 offset1:32
	ds_load_b128 v[16:19], v5 offset:64
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v20, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v25
	ds_load_2addr_b32 v[24:25], v10 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v22, v26
	v_fmac_f32_e32 v4, v23, v27
	ds_load_b128 v[20:23], v5 offset:80
	ds_load_2addr_b32 v[26:27], v10 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v16, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v17, v29
	ds_load_2addr_b32 v[28:29], v10 offset0:192 offset1:224
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v18, v24
	v_fmac_f32_e32 v4, v19, v25
	ds_load_2addr_b32 v[24:25], v15 offset1:32
	ds_load_b128 v[16:19], v5 offset:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v20, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v27
	ds_load_2addr_b32 v[26:27], v15 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v22, v28
	v_fmac_f32_e32 v4, v23, v29
	ds_load_b128 v[20:23], v5 offset:112
	ds_load_2addr_b32 v[28:29], v15 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v4, v16, v24
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v17, v25
	ds_load_2addr_b32 v[16:17], v15 offset0:192 offset1:224
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v4, v18, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v19, v27
	v_fmac_f32_e32 v4, v20, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v29
	v_fmac_f32_e32 v4, v22, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v23, v17
	s_cbranch_vccz .LBB1_2
; %bb.3:                                ; %Flow
	s_mov_b32 s3, 0
	s_branch .LBB1_5
.LBB1_4:
	s_mov_b32 s3, -1
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr0_vgpr1
.LBB1_5:                                ; %Flow138
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_7
; %bb.6:                                ; %.._crit_edge_crit_edge
	v_mad_u64_u32 v[0:1], null, v3, s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s7, v[1:2]
	v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v4, 0
.LBB1_7:                                ; %._crit_edge
	s_mul_i32 s3, s13, s15
	s_mul_hi_u32 s5, s12, s15
	s_mul_i32 s4, s12, s15
	s_add_i32 s5, s5, s3
	s_mov_b32 s3, 0
	s_lshl_b64 s[4:5], s[4:5], 2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_add_u32 s4, s0, s4
	s_addc_u32 s5, s1, s5
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm, .Lfunc_end1-_ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1028
; NumSgprs: 22
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm ; -- Begin function _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
	.p2align	8
	.type	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm,@function
_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm: ; @_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v56, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v70, 5, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s7, s15
	s_mul_hi_u32 s3, s6, s15
	s_mul_i32 s12, s6, s15
	s_add_i32 s13, s3, s2
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_lshl_b64 s[0:1], s[12:13], 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s6, s0
	s_addc_u32 s13, s7, s1
	s_add_u32 s16, s12, -1
	s_addc_u32 s17, s13, -1
	s_bfe_i64 s[18:19], s[0:1], 0x200000
	s_lshl_b32 s1, s14, 7
	v_cmp_ge_u64_e64 s12, s[16:17], s[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s12
	s_lshl_b64 s[12:13], s[4:5], 5
	s_cbranch_vccz .LBB2_4
; %bb.1:                                ; %.preheader.lr.ph
	v_mad_u64_u32 v[2:3], null, s6, v1, 0
	v_lshlrev_b32_e32 v5, 5, v56
	v_dual_mov_b32 v67, 0 :: v_dual_lshlrev_b32 v6, 7, v1
	s_lshl_b64 s[20:21], s[18:19], 2
	v_dual_mov_b32 v66, 0 :: v_dual_lshlrev_b32 v7, 2, v56
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v0, v3
	s_add_i32 s18, s0, 32
	v_dual_mov_b32 v68, 0 :: v_dual_lshlrev_b32 v69, 5, v1
	v_add_lshl_u32 v72, v1, v5, 2
	v_mad_u64_u32 v[3:4], null, s7, v1, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, s0, s10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v4, null, s11, 0, s0
	v_dual_mov_b32 v71, 0 :: v_dual_mov_b32 v64, 0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_dual_mov_b32 v65, 0 :: v_dual_mov_b32 v62, 0
	v_dual_mov_b32 v63, 0 :: v_dual_mov_b32 v60, 0
	v_dual_mov_b32 v61, 0 :: v_dual_mov_b32 v58, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v2, s20
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	v_dual_mov_b32 v59, 0 :: v_dual_mov_b32 v54, 0
	v_add_co_u32 v1, vcc_lo, v2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v73, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v74, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v2, vcc_lo
	v_dual_mov_b32 v57, 0 :: v_dual_mov_b32 v52, 0
	v_dual_mov_b32 v55, 0 :: v_dual_mov_b32 v50, 0
	v_dual_mov_b32 v53, 0 :: v_dual_mov_b32 v48, 0
	v_dual_mov_b32 v51, 0 :: v_dual_mov_b32 v46, 0
	v_dual_mov_b32 v49, 0 :: v_dual_mov_b32 v44, 0
	v_dual_mov_b32 v47, 0 :: v_dual_mov_b32 v42, 0
	v_dual_mov_b32 v45, 0 :: v_dual_mov_b32 v38, 0
	v_dual_mov_b32 v43, 0 :: v_dual_mov_b32 v40, 0
	v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v36, 0
	v_mov_b32_e32 v37, 0
	v_mov_b32_e32 v39, 0
	s_lshl_b64 s[6:7], s[6:7], 4
	s_lshl_b64 s[8:9], s[4:5], 2
	s_mov_b32 s10, s1
.LBB2_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v2, vcc_lo, v0, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	s_ashr_i32 s11, s10, 31
	global_load_b32 v4, v[0:1], off
	s_lshl_b64 s[20:21], s[10:11], 2
	global_load_b32 v7, v[2:3], off
	v_add_co_u32 v0, vcc_lo, 0x80, v0
	s_ashr_i32 s19, s18, 31
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, v73, s20
	v_cmp_ge_u64_e64 s0, s[16:17], s[18:19]
	v_add_co_ci_u32_e32 v6, vcc_lo, s21, v74, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	v_add_co_u32 v10, s0, v5, s8
	v_add_co_ci_u32_e64 v11, s0, s9, v6, s0
	global_load_b32 v18, v[2:3], off
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	v_add_co_u32 v12, s0, v10, s8
	v_add_co_ci_u32_e64 v13, s0, s9, v11, s0
	global_load_b32 v19, v[2:3], off
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	v_add_co_u32 v14, s0, v12, s8
	v_add_co_ci_u32_e64 v15, s0, s9, v13, s0
	global_load_b32 v75, v[2:3], off
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	v_add_co_u32 v20, s0, v14, s8
	v_add_co_ci_u32_e64 v21, s0, s9, v15, s0
	global_load_b32 v76, v[2:3], off
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	v_add_co_u32 v79, s0, v20, s8
	v_add_co_ci_u32_e64 v80, s0, s9, v21, s0
	global_load_b32 v77, v[2:3], off
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	v_add_co_u32 v81, s0, v79, s8
	v_add_co_ci_u32_e64 v82, s0, s9, v80, s0
	global_load_b32 v78, v[2:3], off
	v_add_co_u32 v83, s0, v81, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v84, s0, s9, v82, s0
	s_add_i32 s10, s10, s12
	v_add_co_u32 v85, s0, v83, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v86, s0, s9, v84, s0
	s_add_i32 s18, s18, 32
	v_add_co_u32 v87, s0, v85, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v88, s0, s9, v86, s0
	v_add_co_u32 v89, s0, v87, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v90, s0, s9, v88, s0
	v_add_co_u32 v91, s0, v89, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v92, s0, s9, v90, s0
	v_add_co_u32 v93, s0, v91, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v94, s0, s9, v92, s0
	v_add_co_u32 v95, s0, v93, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v96, s0, s9, v94, s0
	v_add_co_u32 v97, s0, v95, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v98, s0, s9, v96, s0
	v_add_co_u32 v34, s0, v97, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v35, s0, s9, v98, s0
	v_add_co_u32 v32, s0, v34, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v33, s0, s9, v35, s0
	v_add_co_u32 v30, s0, v32, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v31, s0, s9, v33, s0
	v_add_co_u32 v28, s0, v30, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v29, s0, s9, v31, s0
	v_add_co_u32 v26, s0, v28, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v27, s0, s9, v29, s0
	v_add_co_u32 v24, s0, v26, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v25, s0, s9, v27, s0
	v_add_co_u32 v22, s0, v24, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v23, s0, s9, v25, s0
	v_add_co_u32 v16, s0, v22, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v17, s0, s9, v23, s0
	v_add_co_u32 v8, s0, v16, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v9, s0, s9, v17, s0
	v_add_co_u32 v2, s0, v8, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s9, v9, s0
	s_waitcnt vmcnt(6)
	ds_store_2addr_b32 v72, v4, v7 offset1:4
	s_waitcnt vmcnt(4)
	ds_store_2addr_b32 v72, v18, v19 offset0:8 offset1:12
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v72, v75, v76 offset0:16 offset1:20
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v72, v77, v78 offset0:24 offset1:28
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_clause 0x3
	global_load_b32 v18, v[5:6], off
	global_load_b32 v19, v[10:11], off
	global_load_b32 v75, v[12:13], off
	global_load_b32 v99, v[14:15], off
	ds_load_b128 v[4:7], v71
	ds_load_b128 v[10:13], v71 offset:16
	s_waitcnt vmcnt(3) lgkmcnt(1)
	v_fmac_f32_e32 v68, v18, v5
	v_fmac_f32_e32 v67, v18, v4
	v_fmac_f32_e32 v65, v18, v7
	v_fmac_f32_e32 v66, v18, v6
	ds_load_b128 v[4:7], v71 offset:32
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v63, v18, v11
	v_fmac_f32_e32 v64, v18, v10
	v_fmac_f32_e32 v61, v18, v12
	v_fmac_f32_e32 v59, v18, v13
	ds_load_b128 v[10:13], v71 offset:48
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v18, v4
	v_fmac_f32_e32 v60, v18, v5
	v_fmac_f32_e32 v57, v18, v7
	v_fmac_f32_e32 v58, v18, v6
	ds_load_b128 v[4:7], v71 offset:64
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v54, v18, v11
	v_fmac_f32_e32 v55, v18, v10
	v_fmac_f32_e32 v52, v18, v13
	v_fmac_f32_e32 v53, v18, v12
	ds_load_b128 v[10:13], v71 offset:80
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v50, v18, v5
	v_fmac_f32_e32 v51, v18, v4
	v_fmac_f32_e32 v48, v18, v7
	v_fmac_f32_e32 v49, v18, v6
	ds_load_b128 v[4:7], v71 offset:96
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v46, v18, v11
	v_fmac_f32_e32 v47, v18, v10
	v_fmac_f32_e32 v44, v18, v13
	v_fmac_f32_e32 v45, v18, v12
	ds_load_b128 v[10:13], v71 offset:112
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v18, v5
	v_fmac_f32_e32 v43, v18, v4
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v39, v18, v11
	v_fmac_f32_e32 v40, v18, v12
	v_fmac_f32_e32 v37, v18, v7
	v_fmac_f32_e32 v38, v18, v10
	v_fmac_f32_e32 v41, v18, v6
	ds_load_b128 v[4:7], v71 offset:128
	v_fmac_f32_e32 v36, v18, v13
	ds_load_b128 v[10:13], v71 offset:144
	s_waitcnt vmcnt(2) lgkmcnt(1)
	v_fmac_f32_e32 v68, v19, v5
	v_fmac_f32_e32 v67, v19, v4
	v_fmac_f32_e32 v65, v19, v7
	v_fmac_f32_e32 v66, v19, v6
	ds_load_b128 v[4:7], v71 offset:160
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v63, v19, v11
	v_fmac_f32_e32 v64, v19, v10
	v_fmac_f32_e32 v61, v19, v12
	v_fmac_f32_e32 v59, v19, v13
	ds_load_b128 v[10:13], v71 offset:176
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v19, v4
	v_fmac_f32_e32 v60, v19, v5
	v_fmac_f32_e32 v57, v19, v7
	v_fmac_f32_e32 v58, v19, v6
	ds_load_b128 v[4:7], v71 offset:192
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v54, v19, v11
	v_fmac_f32_e32 v55, v19, v10
	v_fmac_f32_e32 v52, v19, v13
	v_fmac_f32_e32 v53, v19, v12
	ds_load_b128 v[10:13], v71 offset:208
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v50, v19, v5
	v_fmac_f32_e32 v51, v19, v4
	v_fmac_f32_e32 v48, v19, v7
	v_fmac_f32_e32 v49, v19, v6
	ds_load_b128 v[4:7], v71 offset:224
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v44, v19, v13
	v_fmac_f32_e32 v45, v19, v12
	ds_load_b128 v[12:15], v71 offset:240
	v_fmac_f32_e32 v46, v19, v11
	v_fmac_f32_e32 v47, v19, v10
	v_add_co_u32 v10, s0, v2, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v11, s0, s9, v3, s0
	v_add_co_u32 v18, s0, v10, s8
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v19, v5
	v_fmac_f32_e32 v43, v19, v4
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v39, v19, v13
	v_fmac_f32_e32 v40, v19, v14
	v_fmac_f32_e32 v37, v19, v7
	v_fmac_f32_e32 v38, v19, v12
	v_fmac_f32_e32 v41, v19, v6
	v_fmac_f32_e32 v36, v19, v15
	ds_load_b128 v[4:7], v71 offset:256
	ds_load_b128 v[12:15], v71 offset:272
	v_add_co_ci_u32_e64 v19, s0, s9, v11, s0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_fmac_f32_e32 v67, v75, v4
	v_fmac_f32_e32 v68, v75, v5
	v_fmac_f32_e32 v66, v75, v6
	v_fmac_f32_e32 v65, v75, v7
	ds_load_b128 v[4:7], v71 offset:288
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v64, v75, v12
	v_fmac_f32_e32 v63, v75, v13
	v_fmac_f32_e32 v61, v75, v14
	v_fmac_f32_e32 v59, v75, v15
	ds_load_b128 v[12:15], v71 offset:304
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v75, v4
	v_fmac_f32_e32 v60, v75, v5
	v_fmac_f32_e32 v58, v75, v6
	v_fmac_f32_e32 v57, v75, v7
	ds_load_b128 v[4:7], v71 offset:320
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v55, v75, v12
	v_fmac_f32_e32 v54, v75, v13
	v_fmac_f32_e32 v53, v75, v14
	v_fmac_f32_e32 v52, v75, v15
	ds_load_b128 v[12:15], v71 offset:336
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v51, v75, v4
	v_fmac_f32_e32 v50, v75, v5
	v_fmac_f32_e32 v49, v75, v6
	v_fmac_f32_e32 v48, v75, v7
	ds_load_b128 v[4:7], v71 offset:352
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v47, v75, v12
	v_fmac_f32_e32 v46, v75, v13
	v_fmac_f32_e32 v45, v75, v14
	v_fmac_f32_e32 v44, v75, v15
	ds_load_b128 v[12:15], v71 offset:368
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v43, v75, v4
	v_fmac_f32_e32 v42, v75, v5
	v_fmac_f32_e32 v41, v75, v6
	v_fmac_f32_e32 v37, v75, v7
	ds_load_b128 v[4:7], v71 offset:384
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v38, v75, v12
	v_fmac_f32_e32 v39, v75, v13
	v_fmac_f32_e32 v40, v75, v14
	v_fmac_f32_e32 v36, v75, v15
	ds_load_b128 v[12:15], v71 offset:400
	ds_load_b128 v[75:78], v71 offset:496
	s_waitcnt vmcnt(0) lgkmcnt(2)
	v_fmac_f32_e32 v67, v99, v4
	v_fmac_f32_e32 v68, v99, v5
	v_fmac_f32_e32 v66, v99, v6
	v_fmac_f32_e32 v65, v99, v7
	ds_load_b128 v[4:7], v71 offset:416
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v64, v99, v12
	v_fmac_f32_e32 v63, v99, v13
	v_fmac_f32_e32 v61, v99, v14
	v_fmac_f32_e32 v59, v99, v15
	ds_load_b128 v[12:15], v71 offset:432
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v38, v99, v75
	v_fmac_f32_e32 v39, v99, v76
	v_fmac_f32_e32 v40, v99, v77
	v_fmac_f32_e32 v36, v99, v78
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v99, v4
	v_fmac_f32_e32 v60, v99, v5
	v_fmac_f32_e32 v58, v99, v6
	v_fmac_f32_e32 v57, v99, v7
	ds_load_b128 v[4:7], v71 offset:448
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v55, v99, v12
	v_fmac_f32_e32 v54, v99, v13
	v_fmac_f32_e32 v53, v99, v14
	v_fmac_f32_e32 v52, v99, v15
	ds_load_b128 v[12:15], v71 offset:464
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v51, v99, v4
	v_fmac_f32_e32 v50, v99, v5
	v_fmac_f32_e32 v49, v99, v6
	v_fmac_f32_e32 v48, v99, v7
	ds_load_b128 v[4:7], v71 offset:480
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v45, v99, v14
	global_load_b32 v14, v[20:21], off
	global_load_b32 v79, v[79:80], off
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v43, v99, v4
	v_fmac_f32_e32 v42, v99, v5
	v_fmac_f32_e32 v41, v99, v6
	v_fmac_f32_e32 v37, v99, v7
	ds_load_b128 v[4:7], v71 offset:512
	ds_load_b128 v[75:78], v71 offset:528
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_fmac_f32_e32 v67, v14, v4
	v_fmac_f32_e32 v68, v14, v5
	v_fmac_f32_e32 v66, v14, v6
	v_fmac_f32_e32 v65, v14, v7
	ds_load_b128 v[4:7], v71 offset:544
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v64, v14, v75
	v_fmac_f32_e32 v63, v14, v76
	v_fmac_f32_e32 v61, v14, v77
	v_fmac_f32_e32 v59, v14, v78
	ds_load_b128 v[75:78], v71 offset:560
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v14, v4
	v_fmac_f32_e32 v60, v14, v5
	v_fmac_f32_e32 v58, v14, v6
	v_fmac_f32_e32 v57, v14, v7
	ds_load_b128 v[4:7], v71 offset:576
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v55, v14, v75
	v_fmac_f32_e32 v54, v14, v76
	v_fmac_f32_e32 v53, v14, v77
	v_fmac_f32_e32 v52, v14, v78
	ds_load_b128 v[75:78], v71 offset:592
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v51, v14, v4
	v_fmac_f32_e32 v50, v14, v5
	v_fmac_f32_e32 v49, v14, v6
	v_fmac_f32_e32 v48, v14, v7
	ds_load_b128 v[4:7], v71 offset:608
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v45, v14, v77 :: v_dual_fmac_f32 v44, v99, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v44, v14, v78 :: v_dual_fmac_f32 v47, v99, v12
	v_add_co_u32 v12, s0, v18, s8
	v_dual_fmac_f32 v47, v14, v75 :: v_dual_fmac_f32 v46, v99, v13
	global_load_b32 v99, v[81:82], off
	v_add_co_ci_u32_e64 v13, s0, s9, v19, s0
	v_add_co_u32 v20, s0, v12, s8
	v_fmac_f32_e32 v46, v14, v76
	ds_load_b128 v[75:78], v71 offset:624
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v43, v14, v4
	v_fmac_f32_e32 v42, v14, v5
	v_fmac_f32_e32 v41, v14, v6
	v_fmac_f32_e32 v37, v14, v7
	ds_load_b128 v[4:7], v71 offset:640
	v_add_co_ci_u32_e64 v21, s0, s9, v13, s0
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v38, v14, v75
	v_fmac_f32_e32 v39, v14, v76
	v_fmac_f32_e32 v40, v14, v77
	v_fmac_f32_e32 v36, v14, v78
	ds_load_b128 v[75:78], v71 offset:656
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_fmac_f32_e32 v67, v79, v4
	v_fmac_f32_e32 v68, v79, v5
	v_fmac_f32_e32 v66, v79, v6
	v_fmac_f32_e32 v65, v79, v7
	ds_load_b128 v[4:7], v71 offset:672
	v_add_co_u32 v14, s0, v20, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v15, s0, s9, v21, s0
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v64, v79, v75
	v_fmac_f32_e32 v63, v79, v76
	v_fmac_f32_e32 v61, v79, v77
	v_fmac_f32_e32 v59, v79, v78
	ds_load_b128 v[75:78], v71 offset:688
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v79, v4
	v_fmac_f32_e32 v60, v79, v5
	v_fmac_f32_e32 v58, v79, v6
	v_fmac_f32_e32 v57, v79, v7
	ds_load_b128 v[4:7], v71 offset:704
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v55, v79, v75
	v_fmac_f32_e32 v54, v79, v76
	v_fmac_f32_e32 v53, v79, v77
	v_fmac_f32_e32 v52, v79, v78
	ds_load_b128 v[75:78], v71 offset:720
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v51, v79, v4
	v_fmac_f32_e32 v50, v79, v5
	v_fmac_f32_e32 v49, v79, v6
	v_fmac_f32_e32 v48, v79, v7
	ds_load_b128 v[4:7], v71 offset:736
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v47, v79, v75
	v_fmac_f32_e32 v46, v79, v76
	v_fmac_f32_e32 v45, v79, v77
	v_fmac_f32_e32 v44, v79, v78
	ds_load_b128 v[75:78], v71 offset:752
	global_load_b32 v100, v[83:84], off
	global_load_b32 v101, v[85:86], off
	global_load_b32 v87, v[87:88], off
	global_load_b32 v88, v[89:90], off
	global_load_b32 v89, v[91:92], off
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v43, v79, v4
	v_fmac_f32_e32 v42, v79, v5
	v_fmac_f32_e32 v41, v79, v6
	v_fmac_f32_e32 v37, v79, v7
	global_load_b32 v90, v[93:94], off
	global_load_b32 v91, v[95:96], off
	ds_load_b128 v[83:86], v71 offset:928
	global_load_b32 v92, v[97:98], off
	global_load_b32 v93, v[34:35], off
	global_load_b32 v94, v[32:33], off
	ds_load_b128 v[32:35], v71 offset:1152
	v_add_co_u32 v4, s0, v14, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v15, s0
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v38, v79, v75
	v_fmac_f32_e32 v39, v79, v76
	v_fmac_f32_e32 v40, v79, v77
	v_fmac_f32_e32 v36, v79, v78
	ds_load_b128 v[75:78], v71 offset:768
	ds_load_b128 v[79:82], v71 offset:784
	v_add_co_u32 v6, s0, v4, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s9, v5, s0
	s_waitcnt vmcnt(10) lgkmcnt(1)
	v_fmac_f32_e32 v67, v99, v75
	v_fmac_f32_e32 v68, v99, v76
	v_fmac_f32_e32 v66, v99, v77
	v_fmac_f32_e32 v65, v99, v78
	ds_load_b128 v[75:78], v71 offset:800
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v64, v99, v79
	v_fmac_f32_e32 v63, v99, v80
	v_fmac_f32_e32 v61, v99, v81
	v_fmac_f32_e32 v59, v99, v82
	ds_load_b128 v[79:82], v71 offset:816
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v62, v99, v75
	v_fmac_f32_e32 v60, v99, v76
	v_fmac_f32_e32 v58, v99, v77
	v_fmac_f32_e32 v57, v99, v78
	ds_load_b128 v[75:78], v71 offset:832
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v55, v99, v79
	v_fmac_f32_e32 v54, v99, v80
	v_fmac_f32_e32 v53, v99, v81
	v_fmac_f32_e32 v52, v99, v82
	ds_load_b128 v[79:82], v71 offset:848
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v51, v99, v75
	v_fmac_f32_e32 v50, v99, v76
	v_fmac_f32_e32 v49, v99, v77
	v_fmac_f32_e32 v48, v99, v78
	ds_load_b128 v[75:78], v71 offset:864
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v47, v99, v79
	v_fmac_f32_e32 v46, v99, v80
	v_fmac_f32_e32 v45, v99, v81
	v_fmac_f32_e32 v44, v99, v82
	ds_load_b128 v[79:82], v71 offset:880
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v43, v99, v75
	v_fmac_f32_e32 v42, v99, v76
	v_fmac_f32_e32 v41, v99, v77
	v_fmac_f32_e32 v37, v99, v78
	ds_load_b128 v[75:78], v71 offset:896
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v38, v99, v79
	v_fmac_f32_e32 v39, v99, v80
	v_fmac_f32_e32 v40, v99, v81
	v_fmac_f32_e32 v36, v99, v82
	ds_load_b128 v[79:82], v71 offset:912
	s_waitcnt vmcnt(9) lgkmcnt(1)
	v_fmac_f32_e32 v67, v100, v75
	v_fmac_f32_e32 v68, v100, v76
	v_fmac_f32_e32 v66, v100, v77
	v_fmac_f32_e32 v65, v100, v78
	ds_load_b128 v[75:78], v71 offset:944
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v64, v100, v79
	v_fmac_f32_e32 v63, v100, v80
	v_fmac_f32_e32 v61, v100, v81
	v_fmac_f32_e32 v59, v100, v82
	ds_load_b128 v[79:82], v71 offset:960
	v_fmac_f32_e32 v62, v100, v83
	v_fmac_f32_e32 v60, v100, v84
	v_fmac_f32_e32 v58, v100, v85
	v_fmac_f32_e32 v57, v100, v86
	ds_load_b128 v[83:86], v71 offset:976
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v55, v100, v75
	v_fmac_f32_e32 v54, v100, v76
	v_fmac_f32_e32 v53, v100, v77
	v_fmac_f32_e32 v52, v100, v78
	ds_load_b128 v[75:78], v71 offset:992
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v51, v100, v79
	v_fmac_f32_e32 v50, v100, v80
	v_fmac_f32_e32 v49, v100, v81
	v_fmac_f32_e32 v48, v100, v82
	ds_load_b128 v[79:82], v71 offset:1008
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v47, v100, v83
	v_fmac_f32_e32 v46, v100, v84
	v_fmac_f32_e32 v45, v100, v85
	v_fmac_f32_e32 v44, v100, v86
	ds_load_b128 v[83:86], v71 offset:1024
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v43, v100, v75
	v_fmac_f32_e32 v42, v100, v76
	v_fmac_f32_e32 v41, v100, v77
	v_fmac_f32_e32 v37, v100, v78
	ds_load_b128 v[75:78], v71 offset:1040
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v38, v100, v79
	v_fmac_f32_e32 v39, v100, v80
	v_fmac_f32_e32 v40, v100, v81
	v_fmac_f32_e32 v36, v100, v82
	ds_load_b128 v[79:82], v71 offset:1056
	s_waitcnt vmcnt(8) lgkmcnt(2)
	v_fmac_f32_e32 v67, v101, v83
	v_fmac_f32_e32 v68, v101, v84
	v_fmac_f32_e32 v66, v101, v85
	v_fmac_f32_e32 v65, v101, v86
	ds_load_b128 v[83:86], v71 offset:1072
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v64, v101, v75
	v_fmac_f32_e32 v63, v101, v76
	v_fmac_f32_e32 v61, v101, v77
	v_fmac_f32_e32 v59, v101, v78
	ds_load_b128 v[75:78], v71 offset:1088
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v62, v101, v79
	v_fmac_f32_e32 v60, v101, v80
	v_fmac_f32_e32 v58, v101, v81
	v_fmac_f32_e32 v57, v101, v82
	ds_load_b128 v[79:82], v71 offset:1104
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v55, v101, v83
	v_fmac_f32_e32 v54, v101, v84
	v_fmac_f32_e32 v53, v101, v85
	v_fmac_f32_e32 v52, v101, v86
	ds_load_b128 v[83:86], v71 offset:1120
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v51, v101, v75
	v_fmac_f32_e32 v50, v101, v76
	v_fmac_f32_e32 v49, v101, v77
	v_fmac_f32_e32 v48, v101, v78
	ds_load_b128 v[75:78], v71 offset:1136
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v47, v101, v79
	v_fmac_f32_e32 v46, v101, v80
	v_fmac_f32_e32 v45, v101, v81
	v_fmac_f32_e32 v44, v101, v82
	ds_load_b128 v[79:82], v71 offset:1168
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v43, v101, v83
	v_fmac_f32_e32 v42, v101, v84
	v_fmac_f32_e32 v41, v101, v85
	v_fmac_f32_e32 v37, v101, v86
	s_waitcnt vmcnt(7)
	v_fmac_f32_e32 v67, v87, v32
	v_fmac_f32_e32 v68, v87, v33
	v_fmac_f32_e32 v66, v87, v34
	v_fmac_f32_e32 v65, v87, v35
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v38, v101, v75
	v_fmac_f32_e32 v39, v101, v76
	v_fmac_f32_e32 v40, v101, v77
	v_fmac_f32_e32 v36, v101, v78
	ds_load_b128 v[75:78], v71 offset:1184
	ds_load_b128 v[83:86], v71 offset:1200
	ds_load_b128 v[32:35], v71 offset:1216
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v64, v87, v79
	v_fmac_f32_e32 v61, v87, v81
	global_load_b32 v95, v[30:31], off
	global_load_b32 v96, v[28:29], off
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v62, v87, v75
	v_fmac_f32_e32 v60, v87, v76
	v_fmac_f32_e32 v58, v87, v77
	v_fmac_f32_e32 v57, v87, v78
	ds_load_b128 v[75:78], v71 offset:1248
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v55, v87, v83
	v_fmac_f32_e32 v54, v87, v84
	v_fmac_f32_e32 v53, v87, v85
	v_fmac_f32_e32 v52, v87, v86
	ds_load_b128 v[83:86], v71 offset:1264
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v43, v87, v75
	v_fmac_f32_e32 v42, v87, v76
	v_fmac_f32_e32 v41, v87, v77
	v_fmac_f32_e32 v37, v87, v78
	ds_load_b128 v[75:78], v71 offset:1312
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v38, v87, v83
	v_fmac_f32_e32 v39, v87, v84
	v_fmac_f32_e32 v40, v87, v85
	v_fmac_f32_e32 v36, v87, v86
	ds_load_b128 v[83:86], v71 offset:1328
	s_waitcnt vmcnt(8) lgkmcnt(1)
	v_fmac_f32_e32 v62, v88, v75
	v_fmac_f32_e32 v60, v88, v76
	v_fmac_f32_e32 v58, v88, v77
	v_fmac_f32_e32 v57, v88, v78
	ds_load_b128 v[75:78], v71 offset:1376
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v55, v88, v83
	v_fmac_f32_e32 v54, v88, v84
	v_fmac_f32_e32 v53, v88, v85
	v_fmac_f32_e32 v52, v88, v86
	ds_load_b128 v[83:86], v71 offset:1392
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v43, v88, v75
	v_fmac_f32_e32 v42, v88, v76
	v_fmac_f32_e32 v41, v88, v77
	v_fmac_f32_e32 v37, v88, v78
	ds_load_b128 v[75:78], v71 offset:1440
	v_fmac_f32_e32 v63, v87, v80
	v_fmac_f32_e32 v59, v87, v82
	ds_load_b128 v[79:82], v71 offset:1232
	v_fmac_f32_e32 v51, v87, v32
	v_fmac_f32_e32 v50, v87, v33
	ds_load_b128 v[30:33], v71 offset:1280
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v38, v88, v83
	v_fmac_f32_e32 v39, v88, v84
	v_fmac_f32_e32 v40, v88, v85
	v_fmac_f32_e32 v36, v88, v86
	s_waitcnt vmcnt(7) lgkmcnt(2)
	v_fmac_f32_e32 v62, v89, v75
	v_fmac_f32_e32 v60, v89, v76
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v58, v89, v77 :: v_dual_fmac_f32 v47, v87, v79
	v_fmac_f32_e32 v46, v87, v80
	v_fmac_f32_e32 v45, v87, v81
	v_fmac_f32_e32 v44, v87, v82
	ds_load_b128 v[79:82], v71 offset:1296
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v67, v88, v30
	v_fmac_f32_e32 v68, v88, v31
	v_fmac_f32_e32 v66, v88, v32
	v_fmac_f32_e32 v65, v88, v33
	ds_load_b128 v[30:33], v71 offset:1344
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v57, v89, v78 :: v_dual_fmac_f32 v64, v88, v79
	v_fmac_f32_e32 v63, v88, v80
	v_fmac_f32_e32 v61, v88, v81
	v_fmac_f32_e32 v59, v88, v82
	ds_load_b128 v[79:82], v71 offset:1360
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v50, v88, v31 :: v_dual_fmac_f32 v49, v87, v34
	v_fmac_f32_e32 v51, v88, v30
	ds_load_b128 v[28:31], v71 offset:1408
	v_dual_fmac_f32 v49, v88, v32 :: v_dual_fmac_f32 v48, v87, v35
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v48, v88, v33
	ds_load_b128 v[32:35], v71 offset:1424
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v47, v88, v79
	v_fmac_f32_e32 v46, v88, v80
	v_fmac_f32_e32 v45, v88, v81
	v_fmac_f32_e32 v44, v88, v82
	ds_load_b128 v[79:82], v71 offset:1456
	ds_load_b128 v[83:86], v71 offset:1472
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v67, v89, v28
	v_fmac_f32_e32 v68, v89, v29
	v_fmac_f32_e32 v66, v89, v30
	v_fmac_f32_e32 v65, v89, v31
	ds_load_b128 v[28:31], v71 offset:1488
	ds_load_b128 v[75:78], v71 offset:1520
	global_load_b32 v97, v[26:27], off
	global_load_b32 v98, v[24:25], off
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v64, v89, v32
	v_fmac_f32_e32 v63, v89, v33
	v_fmac_f32_e32 v61, v89, v34
	v_fmac_f32_e32 v59, v89, v35
	ds_load_b128 v[32:35], v71 offset:1504
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v55, v89, v79
	v_fmac_f32_e32 v54, v89, v80
	v_fmac_f32_e32 v53, v89, v81
	v_fmac_f32_e32 v52, v89, v82
	ds_load_b128 v[79:82], v71 offset:1536
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v51, v89, v83
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v45, v89, v30
	v_fmac_f32_e32 v44, v89, v31
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v38, v89, v75
	v_fmac_f32_e32 v39, v89, v76
	v_fmac_f32_e32 v40, v89, v77
	v_fmac_f32_e32 v36, v89, v78
	ds_load_b128 v[75:78], v71 offset:1600
	v_fmac_f32_e32 v50, v89, v84
	v_fmac_f32_e32 v49, v89, v85
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v43, v89, v32
	v_fmac_f32_e32 v42, v89, v33
	ds_load_b128 v[30:33], v71 offset:1584
	v_fmac_f32_e32 v48, v89, v86
	ds_load_b128 v[83:86], v71 offset:1552
	v_fmac_f32_e32 v47, v89, v28
	v_fmac_f32_e32 v46, v89, v29
	ds_load_b128 v[26:29], v71 offset:1568
	v_fmac_f32_e32 v41, v89, v34
	s_waitcnt vmcnt(8) lgkmcnt(3)
	v_dual_fmac_f32 v37, v89, v35 :: v_dual_fmac_f32 v48, v90, v78
	v_fmac_f32_e32 v49, v90, v77
	v_fmac_f32_e32 v50, v90, v76
	v_fmac_f32_e32 v51, v90, v75
	ds_load_b128 v[75:78], v71 offset:1696
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v52, v90, v33
	v_fmac_f32_e32 v53, v90, v32
	ds_load_b128 v[32:35], v71 offset:1680
	v_fmac_f32_e32 v54, v90, v31
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v60, v90, v27
	v_fmac_f32_e32 v59, v90, v86
	v_fmac_f32_e32 v57, v90, v29
	v_fmac_f32_e32 v58, v90, v28
	v_fmac_f32_e32 v55, v90, v30
	ds_load_b128 v[28:31], v71 offset:1664
	v_fmac_f32_e32 v63, v90, v84
	v_fmac_f32_e32 v64, v90, v83
	s_waitcnt vmcnt(7) lgkmcnt(2)
	v_fmac_f32_e32 v60, v91, v76
	v_fmac_f32_e32 v62, v90, v26
	ds_load_b128 v[24:27], v71 offset:1648
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v63, v91, v33
	v_dual_fmac_f32 v65, v90, v82 :: v_dual_fmac_f32 v64, v91, v32
	v_dual_fmac_f32 v68, v90, v80 :: v_dual_fmac_f32 v59, v91, v35
	v_dual_fmac_f32 v61, v90, v85 :: v_dual_fmac_f32 v62, v91, v75
	ds_load_b128 v[83:86], v71 offset:1632
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v65, v91, v31
	v_dual_fmac_f32 v67, v90, v79 :: v_dual_fmac_f32 v68, v91, v29
	v_fmac_f32_e32 v66, v90, v81
	ds_load_b128 v[79:82], v71 offset:1616
	v_fmac_f32_e32 v61, v91, v34
	v_fmac_f32_e32 v67, v91, v28
	v_fmac_f32_e32 v66, v91, v30
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v36, v90, v27
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v37, v90, v86
	v_fmac_f32_e32 v38, v90, v24
	v_fmac_f32_e32 v41, v90, v85
	v_fmac_f32_e32 v42, v90, v84
	v_fmac_f32_e32 v43, v90, v83
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v46, v90, v80
	v_fmac_f32_e32 v47, v90, v79
	v_fmac_f32_e32 v44, v90, v82
	v_fmac_f32_e32 v45, v90, v81
	ds_load_b128 v[79:82], v71 offset:1712
	v_fmac_f32_e32 v40, v90, v26
	v_fmac_f32_e32 v39, v90, v25
	ds_load_b128 v[24:27], v71 offset:1728
	ds_load_b128 v[83:86], v71 offset:1744
	global_load_b32 v99, v[22:23], off
	ds_load_b128 v[28:31], v71 offset:1760
	ds_load_b128 v[32:35], v71 offset:1776
	global_load_b32 v100, v[16:17], off
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v52, v91, v82
	v_fmac_f32_e32 v53, v91, v81
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v48, v91, v27
	v_fmac_f32_e32 v49, v91, v26
	v_fmac_f32_e32 v50, v91, v25
	v_fmac_f32_e32 v51, v91, v24
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v91, v35
	v_fmac_f32_e32 v37, v91, v31
	v_fmac_f32_e32 v38, v91, v32
	v_fmac_f32_e32 v41, v91, v30
	v_fmac_f32_e32 v42, v91, v29
	v_fmac_f32_e32 v43, v91, v28
	ds_load_b128 v[26:29], v71 offset:1856
	v_fmac_f32_e32 v40, v91, v34
	v_fmac_f32_e32 v39, v91, v33
	ds_load_b128 v[30:33], v71 offset:1872
	ds_load_b128 v[22:25], v71 offset:1824
	v_fmac_f32_e32 v46, v91, v84
	v_fmac_f32_e32 v47, v91, v83
	v_fmac_f32_e32 v44, v91, v86
	v_fmac_f32_e32 v45, v91, v85
	ds_load_b128 v[83:86], v71 offset:1840
	v_fmac_f32_e32 v54, v91, v80
	v_fmac_f32_e32 v57, v91, v78
	v_fmac_f32_e32 v58, v91, v77
	v_fmac_f32_e32 v55, v91, v79
	ds_load_b128 v[75:78], v71 offset:1792
	ds_load_b128 v[79:82], v71 offset:1808
	s_waitcnt vmcnt(8) lgkmcnt(5)
	v_fmac_f32_e32 v48, v92, v29
	v_fmac_f32_e32 v49, v92, v28
	v_fmac_f32_e32 v50, v92, v27
	v_fmac_f32_e32 v51, v92, v26
	ds_load_b128 v[26:29], v71 offset:1952
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v44, v92, v33
	v_fmac_f32_e32 v45, v92, v32
	v_fmac_f32_e32 v46, v92, v31
	v_fmac_f32_e32 v47, v92, v30
	ds_load_b128 v[30:33], v71 offset:1968
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v52, v92, v86
	v_fmac_f32_e32 v55, v92, v83
	v_fmac_f32_e32 v62, v92, v22
	v_fmac_f32_e32 v60, v92, v23
	v_fmac_f32_e32 v57, v92, v25
	v_fmac_f32_e32 v58, v92, v24
	ds_load_b128 v[22:25], v71 offset:1920
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v61, v92, v81
	s_waitcnt vmcnt(7) lgkmcnt(2)
	v_dual_fmac_f32 v59, v92, v82 :: v_dual_fmac_f32 v60, v93, v27
	v_fmac_f32_e32 v62, v93, v26
	v_fmac_f32_e32 v57, v93, v29
	v_fmac_f32_e32 v58, v93, v28
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v52, v93, v33
	v_dual_fmac_f32 v54, v92, v84 :: v_dual_fmac_f32 v55, v93, v30
	v_fmac_f32_e32 v53, v92, v85
	ds_load_b128 v[83:86], v71 offset:1936
	v_fmac_f32_e32 v63, v92, v80
	v_fmac_f32_e32 v66, v92, v77
	v_fmac_f32_e32 v54, v93, v31
	v_fmac_f32_e32 v53, v93, v32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v63, v93, v84
	v_dual_fmac_f32 v67, v92, v75 :: v_dual_fmac_f32 v66, v93, v24
	v_dual_fmac_f32 v68, v92, v76 :: v_dual_fmac_f32 v61, v93, v85
	v_fmac_f32_e32 v59, v93, v86
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v67, v93, v22
	v_dual_fmac_f32 v65, v92, v78 :: v_dual_fmac_f32 v68, v93, v23
	ds_load_b128 v[75:78], v71 offset:1888
	v_fmac_f32_e32 v64, v92, v79
	ds_load_b128 v[79:82], v71 offset:1904
	v_fmac_f32_e32 v65, v93, v25
	v_fmac_f32_e32 v64, v93, v83
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v92, v76
	v_fmac_f32_e32 v43, v92, v75
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v92, v79
	v_fmac_f32_e32 v41, v92, v77
	v_fmac_f32_e32 v40, v92, v81
	v_fmac_f32_e32 v37, v92, v78
	ds_load_b128 v[75:78], v71 offset:1984
	v_fmac_f32_e32 v36, v92, v82
	v_fmac_f32_e32 v39, v92, v80
	ds_load_b128 v[79:82], v71 offset:2000
	ds_load_b128 v[87:90], v71 offset:2016
	ds_load_b128 v[22:25], v71 offset:2032
	ds_load_b128 v[83:86], v71 offset:2048
	global_load_b32 v101, v[8:9], off
	ds_load_b128 v[26:29], v71 offset:2064
	ds_load_b128 v[30:33], v71 offset:2080
	global_load_b32 v102, v[2:3], off
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v48, v93, v78
	v_fmac_f32_e32 v49, v93, v77
	v_fmac_f32_e32 v50, v93, v76
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v42, v93, v88
	v_fmac_f32_e32 v43, v93, v87
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v38, v93, v22
	v_fmac_f32_e32 v41, v93, v89
	v_fmac_f32_e32 v40, v93, v24
	v_fmac_f32_e32 v37, v93, v90
	ds_load_b128 v[87:90], v71 offset:2128
	v_fmac_f32_e32 v36, v93, v25
	v_fmac_f32_e32 v39, v93, v23
	ds_load_b128 v[22:25], v71 offset:2144
	v_fmac_f32_e32 v51, v93, v75
	ds_load_b128 v[75:78], v71 offset:2096
	v_fmac_f32_e32 v44, v93, v82
	v_fmac_f32_e32 v45, v93, v81
	v_fmac_f32_e32 v46, v93, v80
	v_fmac_f32_e32 v47, v93, v79
	ds_load_b128 v[79:82], v71 offset:2112
	s_waitcnt vmcnt(8) lgkmcnt(4)
	v_fmac_f32_e32 v62, v94, v30
	v_fmac_f32_e32 v60, v94, v31
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v41, v94, v24
	v_fmac_f32_e32 v42, v94, v23
	v_fmac_f32_e32 v43, v94, v22
	v_fmac_f32_e32 v37, v94, v25
	ds_load_b128 v[22:25], v71 offset:2256
	v_fmac_f32_e32 v44, v94, v90
	v_fmac_f32_e32 v47, v94, v87
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v50, v94, v80
	v_fmac_f32_e32 v51, v94, v79
	v_fmac_f32_e32 v48, v94, v82
	v_fmac_f32_e32 v49, v94, v81
	ds_load_b128 v[79:82], v71 offset:2224
	s_waitcnt vmcnt(7) lgkmcnt(1)
	v_fmac_f32_e32 v44, v95, v25
	v_dual_fmac_f32 v46, v94, v88 :: v_dual_fmac_f32 v47, v95, v22
	v_fmac_f32_e32 v45, v94, v89
	ds_load_b128 v[87:90], v71 offset:2240
	v_fmac_f32_e32 v54, v94, v76
	v_fmac_f32_e32 v57, v94, v33
	v_fmac_f32_e32 v52, v94, v78
	v_dual_fmac_f32 v53, v94, v77 :: v_dual_fmac_f32 v46, v95, v23
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v54, v95, v80
	v_fmac_f32_e32 v58, v94, v32
	ds_load_b128 v[30:33], v71 offset:2192
	v_fmac_f32_e32 v55, v94, v75
	ds_load_b128 v[75:78], v71 offset:2208
	v_fmac_f32_e32 v63, v94, v27
	v_fmac_f32_e32 v66, v94, v85
	v_fmac_f32_e32 v61, v94, v28
	v_dual_fmac_f32 v59, v94, v29 :: v_dual_fmac_f32 v52, v95, v82
	v_fmac_f32_e32 v53, v95, v81
	v_fmac_f32_e32 v45, v95, v24
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v50, v95, v88
	v_fmac_f32_e32 v51, v95, v87
	v_fmac_f32_e32 v48, v95, v90
	v_fmac_f32_e32 v49, v95, v89
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v63, v95, v31
	v_fmac_f32_e32 v67, v94, v83
	v_fmac_f32_e32 v68, v94, v84
	v_fmac_f32_e32 v65, v94, v86
	ds_load_b128 v[83:86], v71 offset:2160
	v_fmac_f32_e32 v64, v94, v26
	ds_load_b128 v[26:29], v71 offset:2176
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v62, v95, v75
	v_fmac_f32_e32 v60, v95, v76
	v_fmac_f32_e32 v57, v95, v78
	v_fmac_f32_e32 v58, v95, v77
	v_fmac_f32_e32 v61, v95, v32
	v_fmac_f32_e32 v59, v95, v33
	v_fmac_f32_e32 v55, v95, v79
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v38, v94, v83
	v_fmac_f32_e32 v40, v94, v85
	v_fmac_f32_e32 v39, v94, v84
	v_fmac_f32_e32 v36, v94, v86
	ds_load_b128 v[83:86], v71 offset:2272
	ds_load_b128 v[91:94], v71 offset:2288
	global_load_b32 v103, v[10:11], off
	ds_load_b128 v[8:11], v71 offset:2336
	ds_load_b128 v[75:78], v71 offset:2352
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v66, v95, v28
	v_fmac_f32_e32 v67, v95, v26
	v_fmac_f32_e32 v68, v95, v27
	v_fmac_f32_e32 v65, v95, v29
	ds_load_b128 v[26:29], v71 offset:2304
	v_fmac_f32_e32 v64, v95, v30
	ds_load_b128 v[30:33], v71 offset:2320
	ds_load_b128 v[79:82], v71 offset:2368
	ds_load_b128 v[22:25], v71 offset:2384
	ds_load_b128 v[87:90], v71 offset:2416
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v36, v95, v94
	v_fmac_f32_e32 v37, v95, v86
	v_fmac_f32_e32 v38, v95, v91
	v_fmac_f32_e32 v41, v95, v85
	v_fmac_f32_e32 v42, v95, v84
	v_fmac_f32_e32 v43, v95, v83
	v_fmac_f32_e32 v40, v95, v93
	v_fmac_f32_e32 v39, v95, v92
	global_load_b32 v95, v[18:19], off
	s_waitcnt vmcnt(8) lgkmcnt(6)
	v_fmac_f32_e32 v62, v96, v8
	v_fmac_f32_e32 v60, v96, v9
	v_fmac_f32_e32 v57, v96, v11
	v_fmac_f32_e32 v58, v96, v10
	ds_load_b128 v[8:11], v71 offset:2464
	ds_load_b128 v[16:19], v71 offset:2480
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v52, v96, v78
	v_fmac_f32_e32 v53, v96, v77
	ds_load_b128 v[83:86], v71 offset:2400
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v68, v96, v27
	v_fmac_f32_e32 v67, v96, v26
	v_fmac_f32_e32 v65, v96, v29
	v_fmac_f32_e32 v66, v96, v28
	ds_load_b128 v[26:29], v71 offset:2432
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v63, v96, v31
	v_fmac_f32_e32 v64, v96, v30
	v_fmac_f32_e32 v61, v96, v32
	v_fmac_f32_e32 v59, v96, v33
	ds_load_b128 v[30:33], v71 offset:2448
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v46, v96, v23
	v_fmac_f32_e32 v47, v96, v22
	v_fmac_f32_e32 v44, v96, v25
	v_fmac_f32_e32 v45, v96, v24
	ds_load_b128 v[22:25], v71 offset:2512
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v36, v96, v90
	s_waitcnt vmcnt(7) lgkmcnt(4)
	v_fmac_f32_e32 v52, v97, v19
	v_dual_fmac_f32 v54, v96, v76 :: v_dual_fmac_f32 v53, v97, v18
	v_fmac_f32_e32 v55, v96, v75
	ds_load_b128 v[75:78], v71 offset:2496
	v_fmac_f32_e32 v50, v96, v80
	v_fmac_f32_e32 v51, v96, v79
	v_fmac_f32_e32 v48, v96, v82
	v_fmac_f32_e32 v49, v96, v81
	ds_load_b128 v[79:82], v71 offset:2528
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v42, v96, v84
	v_fmac_f32_e32 v43, v96, v83
	v_fmac_f32_e32 v38, v96, v87
	v_fmac_f32_e32 v41, v96, v85
	v_fmac_f32_e32 v39, v96, v88
	v_fmac_f32_e32 v40, v96, v89
	v_fmac_f32_e32 v37, v96, v86
	ds_load_b128 v[83:86], v71 offset:2544
	ds_load_b128 v[87:90], v71 offset:2560
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v68, v97, v27
	v_fmac_f32_e32 v67, v97, v26
	v_fmac_f32_e32 v65, v97, v29
	v_fmac_f32_e32 v66, v97, v28
	ds_load_b128 v[26:29], v71 offset:2576
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v63, v97, v31
	v_fmac_f32_e32 v64, v97, v30
	v_fmac_f32_e32 v62, v97, v8
	v_fmac_f32_e32 v59, v97, v33
	v_fmac_f32_e32 v60, v97, v9
	v_fmac_f32_e32 v61, v97, v32
	ds_load_b128 v[30:33], v71 offset:2592
	v_fmac_f32_e32 v57, v97, v11
	v_fmac_f32_e32 v58, v97, v10
	ds_load_b128 v[8:11], v71 offset:2608
	v_fmac_f32_e32 v54, v97, v17
	v_fmac_f32_e32 v55, v97, v16
	ds_load_b128 v[16:19], v71 offset:2624
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v50, v97, v76
	v_fmac_f32_e32 v51, v97, v75
	v_fmac_f32_e32 v48, v97, v78
	v_fmac_f32_e32 v49, v97, v77
	ds_load_b128 v[75:78], v71 offset:2640
	v_fmac_f32_e32 v46, v97, v23
	v_fmac_f32_e32 v47, v97, v22
	v_fmac_f32_e32 v44, v97, v25
	v_fmac_f32_e32 v45, v97, v24
	ds_load_b128 v[22:25], v71 offset:2656
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v42, v97, v80
	v_fmac_f32_e32 v43, v97, v79
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v38, v97, v83
	v_fmac_f32_e32 v41, v97, v81
	v_fmac_f32_e32 v40, v97, v85
	v_fmac_f32_e32 v37, v97, v82
	ds_load_b128 v[79:82], v71 offset:2672
	global_load_b32 v96, v[12:13], off
	v_fmac_f32_e32 v36, v97, v86
	v_fmac_f32_e32 v39, v97, v84
	ds_load_b128 v[83:86], v71 offset:2688
	s_waitcnt vmcnt(7) lgkmcnt(8)
	v_fmac_f32_e32 v68, v98, v88
	v_fmac_f32_e32 v67, v98, v87
	v_fmac_f32_e32 v65, v98, v90
	v_fmac_f32_e32 v66, v98, v89
	ds_load_b128 v[87:90], v71 offset:2704
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v62, v98, v30
	v_fmac_f32_e32 v63, v98, v27
	v_fmac_f32_e32 v64, v98, v26
	v_fmac_f32_e32 v61, v98, v28
	v_fmac_f32_e32 v60, v98, v31
	v_fmac_f32_e32 v59, v98, v29
	ds_load_b128 v[26:29], v71 offset:2720
	v_fmac_f32_e32 v57, v98, v33
	v_fmac_f32_e32 v58, v98, v32
	ds_load_b128 v[30:33], v71 offset:2736
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v54, v98, v9
	v_fmac_f32_e32 v55, v98, v8
	v_fmac_f32_e32 v52, v98, v11
	v_fmac_f32_e32 v53, v98, v10
	ds_load_b128 v[8:11], v71 offset:2752
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v50, v98, v17
	v_fmac_f32_e32 v51, v98, v16
	v_fmac_f32_e32 v48, v98, v19
	v_fmac_f32_e32 v49, v98, v18
	ds_load_b128 v[16:19], v71 offset:2768
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v44, v98, v78
	v_fmac_f32_e32 v45, v98, v77
	v_fmac_f32_e32 v46, v98, v76
	v_fmac_f32_e32 v47, v98, v75
	ds_load_b128 v[75:78], v71 offset:2784
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v40, v98, v81
	v_fmac_f32_e32 v41, v98, v24
	global_load_b32 v97, v[20:21], off
	v_fmac_f32_e32 v42, v98, v23
	v_fmac_f32_e32 v38, v98, v79
	s_waitcnt vmcnt(7) lgkmcnt(6)
	v_fmac_f32_e32 v68, v99, v84
	v_fmac_f32_e32 v67, v99, v83
	v_fmac_f32_e32 v65, v99, v86
	v_fmac_f32_e32 v66, v99, v85
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v62, v99, v26
	v_fmac_f32_e32 v63, v99, v88
	v_fmac_f32_e32 v64, v99, v87
	v_fmac_f32_e32 v61, v99, v89
	v_fmac_f32_e32 v60, v99, v27
	v_fmac_f32_e32 v59, v99, v90
	v_fmac_f32_e32 v57, v99, v29
	v_fmac_f32_e32 v58, v99, v28
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v54, v99, v31
	v_fmac_f32_e32 v55, v99, v30
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v41, v99, v77
	v_dual_fmac_f32 v43, v98, v22 :: v_dual_fmac_f32 v42, v99, v76
	ds_load_b128 v[20:23], v71 offset:2800
	v_fmac_f32_e32 v37, v98, v25
	v_fmac_f32_e32 v36, v98, v82
	v_fmac_f32_e32 v39, v98, v80
	ds_load_b128 v[79:82], v71 offset:2816
	ds_load_b128 v[91:94], v71 offset:2832
	global_load_b32 v98, v[14:15], off
	ds_load_b128 v[12:15], v71 offset:2848
	ds_load_b128 v[83:86], v71 offset:2864
	ds_load_b128 v[24:27], v71 offset:2880
	ds_load_b128 v[28:31], v71 offset:2896
	v_fmac_f32_e32 v52, v99, v33
	v_fmac_f32_e32 v53, v99, v32
	v_fmac_f32_e32 v50, v99, v9
	v_fmac_f32_e32 v51, v99, v8
	v_fmac_f32_e32 v48, v99, v11
	v_fmac_f32_e32 v49, v99, v10
	ds_load_b128 v[8:11], v71 offset:2912
	v_fmac_f32_e32 v44, v99, v19
	v_fmac_f32_e32 v45, v99, v18
	v_fmac_f32_e32 v46, v99, v17
	v_fmac_f32_e32 v47, v99, v16
	ds_load_b128 v[16:19], v71 offset:2928
	v_fmac_f32_e32 v43, v99, v75
	ds_load_b128 v[32:35], v71 offset:2944
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v38, v99, v20
	v_fmac_f32_e32 v37, v99, v78
	v_fmac_f32_e32 v40, v99, v22
	v_fmac_f32_e32 v36, v99, v23
	v_fmac_f32_e32 v39, v99, v21
	ds_load_b128 v[20:23], v71 offset:2960
	global_load_b32 v99, v[4:5], off
	global_load_b32 v2, v[6:7], off
	s_waitcnt vmcnt(9) lgkmcnt(8)
	v_fmac_f32_e32 v63, v100, v92
	v_fmac_f32_e32 v64, v100, v91
	ds_load_b128 v[3:6], v71 offset:2976
	ds_load_b128 v[75:78], v71 offset:2992
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v54, v100, v84
	v_fmac_f32_e32 v55, v100, v83
	v_fmac_f32_e32 v62, v100, v12
	v_fmac_f32_e32 v60, v100, v13
	v_fmac_f32_e32 v52, v100, v86
	v_fmac_f32_e32 v53, v100, v85
	ds_load_b128 v[83:86], v71 offset:3040
	v_fmac_f32_e32 v61, v100, v93
	v_fmac_f32_e32 v59, v100, v94
	s_waitcnt vmcnt(8) lgkmcnt(3)
	v_fmac_f32_e32 v63, v101, v21
	v_dual_fmac_f32 v65, v100, v82 :: v_dual_fmac_f32 v64, v101, v20
	v_fmac_f32_e32 v68, v100, v80
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v62, v101, v3
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v54, v101, v76
	v_fmac_f32_e32 v65, v101, v35
	v_dual_fmac_f32 v67, v100, v79 :: v_dual_fmac_f32 v68, v101, v33
	v_fmac_f32_e32 v66, v100, v81
	ds_load_b128 v[79:82], v71 offset:3008
	v_dual_fmac_f32 v58, v100, v14 :: v_dual_fmac_f32 v55, v101, v75
	v_fmac_f32_e32 v57, v100, v15
	ds_load_b128 v[12:15], v71 offset:3024
	v_fmac_f32_e32 v48, v100, v27
	v_fmac_f32_e32 v51, v100, v24
	v_fmac_f32_e32 v46, v100, v29
	v_fmac_f32_e32 v47, v100, v28
	v_fmac_f32_e32 v44, v100, v31
	v_fmac_f32_e32 v45, v100, v30
	ds_load_b128 v[28:31], v71 offset:3072
	v_fmac_f32_e32 v67, v101, v32
	v_fmac_f32_e32 v66, v101, v34
	v_fmac_f32_e32 v61, v101, v22
	v_fmac_f32_e32 v60, v101, v4
	v_fmac_f32_e32 v59, v101, v23
	ds_load_b128 v[20:23], v71 offset:3136
	ds_load_b128 v[32:35], v71 offset:3120
	v_fmac_f32_e32 v58, v101, v5
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v48, v101, v82
	v_dual_fmac_f32 v50, v100, v25 :: v_dual_fmac_f32 v51, v101, v79
	v_fmac_f32_e32 v49, v100, v26
	ds_load_b128 v[24:27], v71 offset:3056
	v_fmac_f32_e32 v36, v100, v19
	v_fmac_f32_e32 v39, v100, v17
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v46, v101, v13
	v_fmac_f32_e32 v47, v101, v12
	v_fmac_f32_e32 v44, v101, v15
	v_fmac_f32_e32 v45, v101, v14
	v_fmac_f32_e32 v57, v101, v6
	ds_load_b128 v[3:6], v71 offset:3152
	v_fmac_f32_e32 v52, v101, v78
	v_fmac_f32_e32 v53, v101, v77
	ds_load_b128 v[75:78], v71 offset:3168
	v_fmac_f32_e32 v50, v101, v80
	v_fmac_f32_e32 v49, v101, v81
	ds_load_b128 v[79:82], v71 offset:3184
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v36, v101, v27
	v_dual_fmac_f32 v40, v100, v18 :: v_dual_fmac_f32 v39, v101, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v43, v100, v8 :: v_dual_fmac_f32 v40, v101, v26
	v_dual_fmac_f32 v42, v100, v9 :: v_dual_fmac_f32 v43, v101, v83
	v_fmac_f32_e32 v41, v100, v10
	ds_load_b128 v[7:10], v71 offset:3088
	v_fmac_f32_e32 v42, v101, v84
	v_dual_fmac_f32 v38, v100, v16 :: v_dual_fmac_f32 v41, v101, v85
	v_fmac_f32_e32 v37, v100, v11
	ds_load_b128 v[11:14], v71 offset:3200
	ds_load_b128 v[16:19], v71 offset:3104
	v_fmac_f32_e32 v38, v101, v24
	ds_load_b128 v[24:27], v71 offset:3232
	v_fmac_f32_e32 v37, v101, v86
	ds_load_b128 v[83:86], v71 offset:3216
	s_waitcnt vmcnt(7) lgkmcnt(4)
	v_fmac_f32_e32 v63, v102, v8
	v_fmac_f32_e32 v66, v102, v30
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v62, v102, v16
	s_waitcnt vmcnt(6) lgkmcnt(0)
	v_dual_fmac_f32 v60, v102, v17 :: v_dual_fmac_f32 v63, v103, v84
	v_dual_fmac_f32 v67, v102, v28 :: v_dual_fmac_f32 v66, v103, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v68, v102, v29 :: v_dual_fmac_f32 v67, v103, v11
	v_dual_fmac_f32 v65, v102, v31 :: v_dual_fmac_f32 v68, v103, v12
	ds_load_b128 v[28:31], v71 offset:3248
	v_fmac_f32_e32 v64, v102, v7
	v_dual_fmac_f32 v61, v102, v9 :: v_dual_fmac_f32 v62, v103, v24
	v_dual_fmac_f32 v59, v102, v10 :: v_dual_fmac_f32 v60, v103, v25
	ds_load_b128 v[7:10], v71 offset:3264
	v_fmac_f32_e32 v57, v102, v19
	v_fmac_f32_e32 v58, v102, v18
	ds_load_b128 v[15:18], v71 offset:3280
	v_fmac_f32_e32 v48, v102, v23
	v_fmac_f32_e32 v51, v102, v20
	v_fmac_f32_e32 v54, v102, v33
	v_fmac_f32_e32 v55, v102, v32
	v_fmac_f32_e32 v52, v102, v35
	v_fmac_f32_e32 v53, v102, v34
	ds_load_b128 v[32:35], v71 offset:3296
	v_fmac_f32_e32 v46, v102, v4
	v_fmac_f32_e32 v47, v102, v3
	v_fmac_f32_e32 v44, v102, v6
	v_fmac_f32_e32 v45, v102, v5
	ds_load_b128 v[3:6], v71 offset:3328
	v_fmac_f32_e32 v65, v103, v14
	ds_load_b128 v[11:14], v71 offset:3376
	v_fmac_f32_e32 v64, v103, v83
	v_fmac_f32_e32 v61, v103, v85
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v48, v103, v10
	v_dual_fmac_f32 v50, v102, v21 :: v_dual_fmac_f32 v51, v103, v7
	v_fmac_f32_e32 v49, v102, v22
	ds_load_b128 v[19:22], v71 offset:3312
	v_fmac_f32_e32 v38, v102, v79
	v_fmac_f32_e32 v41, v102, v77
	v_fmac_f32_e32 v40, v102, v81
	v_fmac_f32_e32 v37, v102, v78
	v_fmac_f32_e32 v36, v102, v82
	v_fmac_f32_e32 v39, v102, v80
	ds_load_b128 v[79:82], v71 offset:3360
	v_fmac_f32_e32 v59, v103, v86
	ds_load_b128 v[83:86], v71 offset:3392
	v_fmac_f32_e32 v57, v103, v27
	v_fmac_f32_e32 v58, v103, v26
	ds_load_b128 v[23:26], v71 offset:3408
	v_fmac_f32_e32 v54, v103, v29
	v_fmac_f32_e32 v55, v103, v28
	v_fmac_f32_e32 v52, v103, v31
	v_fmac_f32_e32 v53, v103, v30
	ds_load_b128 v[27:30], v71 offset:3424
	v_fmac_f32_e32 v50, v103, v8
	v_fmac_f32_e32 v49, v103, v9
	ds_load_b128 v[7:10], v71 offset:3440
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v38, v103, v19
	v_dual_fmac_f32 v42, v102, v76 :: v_dual_fmac_f32 v41, v103, v34
	v_fmac_f32_e32 v43, v102, v75
	ds_load_b128 v[75:78], v71 offset:3344
	v_fmac_f32_e32 v46, v103, v16
	v_fmac_f32_e32 v42, v103, v33
	v_fmac_f32_e32 v47, v103, v15
	v_fmac_f32_e32 v44, v103, v18
	v_fmac_f32_e32 v45, v103, v17
	ds_load_b128 v[15:18], v71 offset:3456
	v_fmac_f32_e32 v43, v103, v32
	ds_load_b128 v[31:34], v71 offset:3472
	v_fmac_f32_e32 v40, v103, v21
	v_fmac_f32_e32 v36, v103, v22
	v_fmac_f32_e32 v39, v103, v20
	ds_load_b128 v[19:22], v71 offset:3488
	ds_load_b128 v[87:90], v71 offset:3504
	v_fmac_f32_e32 v37, v103, v35
	s_waitcnt vmcnt(5)
	v_fmac_f32_e32 v68, v95, v4
	v_fmac_f32_e32 v67, v95, v3
	v_fmac_f32_e32 v65, v95, v6
	v_fmac_f32_e32 v66, v95, v5
	ds_load_b128 v[3:6], v71 offset:3520
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v62, v95, v79
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v63, v95, v76
	v_fmac_f32_e32 v64, v95, v75
	v_fmac_f32_e32 v61, v95, v77
	v_fmac_f32_e32 v60, v95, v80
	v_fmac_f32_e32 v59, v95, v78
	ds_load_b128 v[75:78], v71 offset:3536
	v_fmac_f32_e32 v57, v95, v82
	v_fmac_f32_e32 v58, v95, v81
	ds_load_b128 v[79:82], v71 offset:3552
	v_fmac_f32_e32 v54, v95, v12
	v_fmac_f32_e32 v55, v95, v11
	v_fmac_f32_e32 v52, v95, v14
	v_fmac_f32_e32 v53, v95, v13
	ds_load_b128 v[11:14], v71 offset:3568
	v_fmac_f32_e32 v50, v95, v84
	v_fmac_f32_e32 v51, v95, v83
	v_fmac_f32_e32 v48, v95, v86
	v_fmac_f32_e32 v49, v95, v85
	ds_load_b128 v[83:86], v71 offset:3584
	v_fmac_f32_e32 v46, v95, v24
	v_fmac_f32_e32 v47, v95, v23
	v_fmac_f32_e32 v44, v95, v26
	v_fmac_f32_e32 v45, v95, v25
	ds_load_b128 v[23:26], v71 offset:3600
	v_fmac_f32_e32 v42, v95, v28
	v_fmac_f32_e32 v43, v95, v27
	v_fmac_f32_e32 v38, v95, v7
	v_fmac_f32_e32 v41, v95, v29
	v_fmac_f32_e32 v40, v95, v9
	v_fmac_f32_e32 v37, v95, v30
	ds_load_b128 v[27:30], v71 offset:3616
	v_fmac_f32_e32 v36, v95, v10
	v_fmac_f32_e32 v39, v95, v8
	ds_load_b128 v[7:10], v71 offset:3632
	s_waitcnt vmcnt(4) lgkmcnt(11)
	v_fmac_f32_e32 v68, v96, v16
	v_fmac_f32_e32 v67, v96, v15
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v36, v96, v14
	v_fmac_f32_e32 v65, v96, v18
	v_fmac_f32_e32 v66, v96, v17
	ds_load_b128 v[15:18], v71 offset:3648
	v_fmac_f32_e32 v63, v96, v32
	v_fmac_f32_e32 v64, v96, v31
	v_fmac_f32_e32 v62, v96, v19
	v_fmac_f32_e32 v61, v96, v33
	v_fmac_f32_e32 v60, v96, v20
	v_fmac_f32_e32 v59, v96, v34
	ds_load_b128 v[31:34], v71 offset:3664
	v_fmac_f32_e32 v57, v96, v22
	v_fmac_f32_e32 v58, v96, v21
	ds_load_b128 v[19:22], v71 offset:3680
	v_fmac_f32_e32 v54, v96, v88
	v_fmac_f32_e32 v55, v96, v87
	v_fmac_f32_e32 v52, v96, v90
	v_fmac_f32_e32 v53, v96, v89
	ds_load_b128 v[87:90], v71 offset:3696
	v_fmac_f32_e32 v50, v96, v4
	v_fmac_f32_e32 v51, v96, v3
	v_fmac_f32_e32 v48, v96, v6
	v_fmac_f32_e32 v49, v96, v5
	ds_load_b128 v[3:6], v71 offset:3712
	v_fmac_f32_e32 v46, v96, v76
	v_fmac_f32_e32 v47, v96, v75
	v_fmac_f32_e32 v44, v96, v78
	v_fmac_f32_e32 v45, v96, v77
	ds_load_b128 v[75:78], v71 offset:3728
	v_fmac_f32_e32 v42, v96, v80
	v_fmac_f32_e32 v43, v96, v79
	v_fmac_f32_e32 v38, v96, v11
	v_fmac_f32_e32 v41, v96, v81
	v_fmac_f32_e32 v39, v96, v12
	v_fmac_f32_e32 v40, v96, v13
	v_fmac_f32_e32 v37, v96, v82
	ds_load_b128 v[79:82], v71 offset:3744
	ds_load_b128 v[11:14], v71 offset:3760
	s_waitcnt vmcnt(3) lgkmcnt(11)
	v_fmac_f32_e32 v68, v97, v84
	v_fmac_f32_e32 v67, v97, v83
	v_fmac_f32_e32 v65, v97, v86
	v_fmac_f32_e32 v66, v97, v85
	ds_load_b128 v[83:86], v71 offset:3776
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v63, v97, v24
	v_fmac_f32_e32 v64, v97, v23
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v62, v97, v27
	v_fmac_f32_e32 v61, v97, v25
	v_fmac_f32_e32 v60, v97, v28
	v_fmac_f32_e32 v59, v97, v26
	ds_load_b128 v[23:26], v71 offset:3792
	v_fmac_f32_e32 v57, v97, v30
	v_fmac_f32_e32 v58, v97, v29
	ds_load_b128 v[27:30], v71 offset:3808
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v54, v97, v8
	v_fmac_f32_e32 v55, v97, v7
	v_fmac_f32_e32 v52, v97, v10
	v_fmac_f32_e32 v53, v97, v9
	ds_load_b128 v[7:10], v71 offset:3824
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v50, v97, v16
	v_fmac_f32_e32 v51, v97, v15
	v_fmac_f32_e32 v48, v97, v18
	v_fmac_f32_e32 v49, v97, v17
	ds_load_b128 v[15:18], v71 offset:3840
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v46, v97, v32
	v_fmac_f32_e32 v47, v97, v31
	v_fmac_f32_e32 v44, v97, v34
	v_fmac_f32_e32 v45, v97, v33
	ds_load_b128 v[31:34], v71 offset:3856
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v42, v97, v20
	v_fmac_f32_e32 v43, v97, v19
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v38, v97, v87
	v_fmac_f32_e32 v41, v97, v21
	v_fmac_f32_e32 v40, v97, v89
	v_fmac_f32_e32 v37, v97, v22
	ds_load_b128 v[19:22], v71 offset:3872
	v_fmac_f32_e32 v36, v97, v90
	v_fmac_f32_e32 v39, v97, v88
	ds_load_b128 v[87:90], v71 offset:3888
	s_waitcnt vmcnt(2) lgkmcnt(11)
	v_fmac_f32_e32 v68, v98, v4
	v_fmac_f32_e32 v67, v98, v3
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v36, v98, v10
	v_fmac_f32_e32 v65, v98, v6
	v_fmac_f32_e32 v66, v98, v5
	ds_load_b128 v[3:6], v71 offset:3904
	v_fmac_f32_e32 v63, v98, v76
	v_fmac_f32_e32 v64, v98, v75
	v_fmac_f32_e32 v62, v98, v79
	v_fmac_f32_e32 v61, v98, v77
	v_fmac_f32_e32 v60, v98, v80
	v_fmac_f32_e32 v59, v98, v78
	ds_load_b128 v[75:78], v71 offset:3920
	v_fmac_f32_e32 v57, v98, v82
	v_fmac_f32_e32 v58, v98, v81
	ds_load_b128 v[79:82], v71 offset:3936
	v_fmac_f32_e32 v54, v98, v12
	v_fmac_f32_e32 v55, v98, v11
	v_fmac_f32_e32 v52, v98, v14
	v_fmac_f32_e32 v53, v98, v13
	ds_load_b128 v[11:14], v71 offset:3952
	v_fmac_f32_e32 v50, v98, v84
	v_fmac_f32_e32 v51, v98, v83
	v_fmac_f32_e32 v48, v98, v86
	v_fmac_f32_e32 v49, v98, v85
	ds_load_b128 v[83:86], v71 offset:3968
	v_fmac_f32_e32 v46, v98, v24
	v_fmac_f32_e32 v47, v98, v23
	v_fmac_f32_e32 v44, v98, v26
	v_fmac_f32_e32 v45, v98, v25
	ds_load_b128 v[23:26], v71 offset:3984
	v_fmac_f32_e32 v42, v98, v28
	v_fmac_f32_e32 v43, v98, v27
	v_fmac_f32_e32 v38, v98, v7
	v_fmac_f32_e32 v41, v98, v29
	v_fmac_f32_e32 v39, v98, v8
	v_fmac_f32_e32 v40, v98, v9
	v_fmac_f32_e32 v37, v98, v30
	ds_load_b128 v[27:30], v71 offset:4000
	ds_load_b128 v[7:10], v71 offset:4016
	ds_load_b128 v[91:94], v71 offset:4032
	s_waitcnt vmcnt(1) lgkmcnt(12)
	v_fmac_f32_e32 v68, v99, v16
	v_fmac_f32_e32 v67, v99, v15
	v_fmac_f32_e32 v65, v99, v18
	v_fmac_f32_e32 v66, v99, v17
	ds_load_b128 v[15:18], v71 offset:4048
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v63, v99, v32
	v_fmac_f32_e32 v64, v99, v31
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v62, v99, v19
	v_fmac_f32_e32 v61, v99, v33
	v_fmac_f32_e32 v60, v99, v20
	v_fmac_f32_e32 v59, v99, v34
	ds_load_b128 v[31:34], v71 offset:4064
	v_fmac_f32_e32 v57, v99, v22
	v_fmac_f32_e32 v58, v99, v21
	ds_load_b128 v[19:22], v71 offset:4080
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v54, v99, v88
	v_fmac_f32_e32 v55, v99, v87
	v_fmac_f32_e32 v52, v99, v90
	v_fmac_f32_e32 v53, v99, v89
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v50, v99, v4
	v_fmac_f32_e32 v51, v99, v3
	v_fmac_f32_e32 v48, v99, v6
	v_fmac_f32_e32 v49, v99, v5
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v46, v99, v76
	v_fmac_f32_e32 v47, v99, v75
	v_fmac_f32_e32 v44, v99, v78
	v_fmac_f32_e32 v45, v99, v77
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v42, v99, v80
	v_fmac_f32_e32 v43, v99, v79
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v38, v99, v11
	v_fmac_f32_e32 v41, v99, v81
	v_fmac_f32_e32 v40, v99, v13
	v_fmac_f32_e32 v37, v99, v82
	v_fmac_f32_e32 v36, v99, v14
	v_fmac_f32_e32 v39, v99, v12
	s_waitcnt vmcnt(0) lgkmcnt(7)
	v_fmac_f32_e32 v68, v2, v84
	v_fmac_f32_e32 v67, v2, v83
	v_fmac_f32_e32 v65, v2, v86
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v2, v22
	v_fmac_f32_e32 v66, v2, v85
	v_fmac_f32_e32 v63, v2, v24
	v_fmac_f32_e32 v64, v2, v23
	v_fmac_f32_e32 v62, v2, v27
	v_fmac_f32_e32 v61, v2, v25
	v_fmac_f32_e32 v60, v2, v28
	v_fmac_f32_e32 v59, v2, v26
	v_fmac_f32_e32 v57, v2, v30
	v_fmac_f32_e32 v58, v2, v29
	v_fmac_f32_e32 v54, v2, v8
	v_fmac_f32_e32 v55, v2, v7
	v_fmac_f32_e32 v52, v2, v10
	v_fmac_f32_e32 v53, v2, v9
	v_fmac_f32_e32 v50, v2, v92
	v_fmac_f32_e32 v51, v2, v91
	v_fmac_f32_e32 v48, v2, v94
	v_fmac_f32_e32 v49, v2, v93
	v_fmac_f32_e32 v46, v2, v16
	v_fmac_f32_e32 v47, v2, v15
	v_fmac_f32_e32 v44, v2, v18
	v_fmac_f32_e32 v45, v2, v17
	v_fmac_f32_e32 v42, v2, v32
	v_fmac_f32_e32 v43, v2, v31
	v_fmac_f32_e32 v38, v2, v19
	v_fmac_f32_e32 v41, v2, v33
	v_fmac_f32_e32 v39, v2, v20
	v_fmac_f32_e32 v40, v2, v21
	v_fmac_f32_e32 v37, v2, v34
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB2_2
; %bb.3:                                ; %Flow
	s_mov_b32 s0, 0
	s_branch .LBB2_5
.LBB2_4:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr40
                                        ; implicit-def: $vgpr39
                                        ; implicit-def: $vgpr38
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr41
                                        ; implicit-def: $vgpr42
                                        ; implicit-def: $vgpr43
                                        ; implicit-def: $vgpr44
                                        ; implicit-def: $vgpr45
                                        ; implicit-def: $vgpr46
                                        ; implicit-def: $vgpr47
                                        ; implicit-def: $vgpr48
                                        ; implicit-def: $vgpr49
                                        ; implicit-def: $vgpr50
                                        ; implicit-def: $vgpr51
                                        ; implicit-def: $vgpr52
                                        ; implicit-def: $vgpr53
                                        ; implicit-def: $vgpr54
                                        ; implicit-def: $vgpr55
                                        ; implicit-def: $vgpr57
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr62
                                        ; implicit-def: $vgpr59
                                        ; implicit-def: $vgpr61
                                        ; implicit-def: $vgpr63
                                        ; implicit-def: $vgpr64
                                        ; implicit-def: $vgpr65
                                        ; implicit-def: $vgpr66
                                        ; implicit-def: $vgpr68
                                        ; implicit-def: $vgpr67
                                        ; implicit-def: $vgpr69
.LBB2_5:                                ; %Flow414
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_7
; %bb.6:                                ; %.._crit_edge_crit_edge
	v_dual_mov_b32 v67, 0 :: v_dual_mov_b32 v68, 0
	v_dual_mov_b32 v69, v70 :: v_dual_mov_b32 v66, 0
	v_dual_mov_b32 v65, 0 :: v_dual_mov_b32 v64, 0
	v_dual_mov_b32 v63, 0 :: v_dual_mov_b32 v62, 0
	v_dual_mov_b32 v61, 0 :: v_dual_mov_b32 v60, 0
	v_dual_mov_b32 v59, 0 :: v_dual_mov_b32 v58, 0
	v_dual_mov_b32 v57, 0 :: v_dual_mov_b32 v54, 0
	v_dual_mov_b32 v55, 0 :: v_dual_mov_b32 v52, 0
	v_dual_mov_b32 v53, 0 :: v_dual_mov_b32 v50, 0
	v_dual_mov_b32 v51, 0 :: v_dual_mov_b32 v48, 0
	v_dual_mov_b32 v49, 0 :: v_dual_mov_b32 v46, 0
	v_dual_mov_b32 v47, 0 :: v_dual_mov_b32 v44, 0
	v_dual_mov_b32 v45, 0 :: v_dual_mov_b32 v42, 0
	v_dual_mov_b32 v43, 0 :: v_dual_mov_b32 v38, 0
	v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v40, 0
	v_dual_mov_b32 v37, 0 :: v_dual_mov_b32 v36, 0
	v_mov_b32_e32 v39, 0
.LBB2_7:                                ; %._crit_edge
	v_add_nc_u32_e32 v0, v69, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, v0, s1
	v_add_co_ci_u32_e64 v1, null, 0, 0, s0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s12, s15, v[0:1]
	v_mov_b32_e32 v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s13, s15, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v67, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v68, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v66, off
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v65, off
	v_add_co_u32 v0, vcc_lo, v8, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	global_store_b32 v[8:9], v64, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v63, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v61, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v59, off
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v62, off
	v_add_co_u32 v0, vcc_lo, v8, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	global_store_b32 v[8:9], v60, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v58, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v57, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v55, off
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v54, off
	v_add_co_u32 v0, vcc_lo, v8, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	global_store_b32 v[8:9], v53, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v52, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v51, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v50, off
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v49, off
	v_add_co_u32 v0, vcc_lo, v8, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	global_store_b32 v[8:9], v48, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v47, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v46, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v45, off
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v44, off
	v_add_co_u32 v0, vcc_lo, v8, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	global_store_b32 v[8:9], v43, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v42, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v41, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[4:5], v37, off
	global_store_b32 v[6:7], v38, off
	global_store_b32 v[8:9], v39, off
	global_store_b32 v[0:1], v40, off
	global_store_b32 v[2:3], v36, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 104
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm, .Lfunc_end2-_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9424
; NumSgprs: 24
; NumVgprs: 104
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 104
; Occupancy: 12
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm ; -- Begin function _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
	.p2align	8
	.type	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm,@function
_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm: ; @_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v8, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v14, 4, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s7, s15
	s_mul_hi_u32 s3, s6, s15
	s_mul_i32 s12, s6, s15
	s_add_i32 s13, s3, s2
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_lshl_b64 s[0:1], s[12:13], 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s6, s0
	s_addc_u32 s13, s7, s1
	s_add_u32 s16, s12, -1
	s_addc_u32 s17, s13, -1
	s_bfe_i64 s[18:19], s[0:1], 0x200000
	s_lshl_b32 s1, s14, 6
	v_cmp_ge_u64_e64 s12, s[16:17], s[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s12
	s_lshl_b64 s[12:13], s[4:5], 4
	s_cbranch_vccz .LBB3_4
; %bb.1:                                ; %.preheader.lr.ph
	v_add_nc_u32_e32 v9, 12, v1
	v_lshlrev_b32_e32 v28, 2, v8
	v_add_nc_u32_e32 v15, 4, v1
	v_dual_mov_b32 v27, 0 :: v_dual_lshlrev_b32 v16, 4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[2:3], null, s6, v9, 0
	v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v25, 0
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v21, 0
	v_mov_b32_e32 v0, v3
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, s7, v9, v[0:1]
	v_lshlrev_b32_e32 v4, 6, v1
	v_mad_u64_u32 v[9:10], null, s6, v15, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s10, s10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v11, null, s11, 0, s10
	s_lshl_b64 s[10:11], s[18:19], 2
	v_add_co_u32 v29, vcc_lo, v3, v28
	v_mov_b32_e32 v3, v6
	v_mad_u64_u32 v[6:7], null, s6, v1, 0
	v_add_nc_u32_e32 v17, 8, v1
	v_add_co_ci_u32_e32 v30, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_mad_u64_u32 v[4:5], null, s6, v17, 0
	v_lshlrev_b32_e32 v13, 4, v8
	s_add_u32 s6, s8, s10
	s_addc_u32 s8, s9, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v32, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v33, vcc_lo, s8, v3, vcc_lo
	v_mov_b32_e32 v0, v5
	v_add_lshl_u32 v31, v1, v13, 2
	s_mov_b32 s10, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s7, v17, v[0:1]
	v_mov_b32_e32 v0, v10
	v_mad_u64_u32 v[12:13], null, s7, v15, v[0:1]
	v_mov_b32_e32 v0, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v5, v11
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v13, 0
	v_mad_u64_u32 v[17:18], null, s7, v1, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_mov_b32_e32 v10, v12
	v_mov_b32_e32 v18, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v7, v17
	v_mov_b32_e32 v17, 0
	v_lshlrev_b64 v[2:3], 2, v[9:10]
	v_add_co_u32 v34, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v35, vcc_lo, s8, v1, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v36, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v37, vcc_lo, s8, v3, vcc_lo
	v_mov_b32_e32 v10, 0
	v_add_co_u32 v38, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v39, vcc_lo, s8, v1, vcc_lo
	v_mov_b32_e32 v9, 0
	s_add_i32 s6, s0, 16
	s_lshl_b64 s[8:9], s[4:5], 2
.LBB3_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v0, vcc_lo, v38, v28
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v39, vcc_lo
	v_add_co_u32 v2, vcc_lo, v36, v28
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v37, vcc_lo
	v_add_co_u32 v4, vcc_lo, v34, v28
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v6, vcc_lo, v32, v28
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v33, vcc_lo
	global_load_b32 v64, v[0:1], off
	global_load_b32 v65, v[2:3], off
	global_load_b32 v66, v[4:5], off
	global_load_b32 v67, v[6:7], off
	v_add_co_u32 v32, vcc_lo, v32, 64
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v34, vcc_lo, v34, 64
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v36, vcc_lo, v36, 64
	s_ashr_i32 s11, s10, 31
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	s_ashr_i32 s7, s6, 31
	v_add_co_u32 v38, vcc_lo, v38, 64
	s_lshl_b64 s[18:19], s[10:11], 2
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v39, vcc_lo
	v_cmp_ge_u64_e64 s0, s[16:17], s[6:7]
	v_add_co_u32 v0, vcc_lo, v29, s18
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v30, vcc_lo
	s_add_i32 s10, s10, s12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s0
	v_add_co_u32 v2, s0, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s0, s9, v1, s0
	s_add_i32 s6, s6, 16
	v_add_co_u32 v4, s0, v2, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v3, s0
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v31, v64, v65 offset1:4
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v31, v66, v67 offset0:8 offset1:12
	v_add_co_u32 v6, s0, v4, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v7, s0, s9, v5, s0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v40, s0, v6, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v41, s0, s9, v7, s0
	s_barrier
	v_add_co_u32 v42, s0, v40, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v43, s0, s9, v41, s0
	buffer_gl0_inv
	v_add_co_u32 v44, s0, v42, s8
	v_add_co_ci_u32_e64 v45, s0, s9, v43, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s0, v44, s8
	v_add_co_ci_u32_e64 v47, s0, s9, v45, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v48, s0, v46, s8
	v_add_co_ci_u32_e64 v49, s0, s9, v47, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v50, s0, v48, s8
	v_add_co_ci_u32_e64 v51, s0, s9, v49, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v52, s0, v50, s8
	v_add_co_ci_u32_e64 v53, s0, s9, v51, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s0, v52, s8
	v_add_co_ci_u32_e64 v55, s0, s9, v53, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s0, v54, s8
	v_add_co_ci_u32_e64 v57, s0, s9, v55, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v58, s0, v56, s8
	v_add_co_ci_u32_e64 v59, s0, s9, v57, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v60, s0, v58, s8
	v_add_co_ci_u32_e64 v61, s0, s9, v59, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v62, s0, v60, s8
	v_add_co_ci_u32_e64 v63, s0, s9, v61, s0
	s_clause 0x3
	global_load_b32 v76, v[0:1], off
	global_load_b32 v80, v[2:3], off
	global_load_b32 v81, v[4:5], off
	global_load_b32 v82, v[6:7], off
	global_load_b32 v83, v[40:41], off
	global_load_b32 v84, v[42:43], off
	global_load_b32 v85, v[44:45], off
	global_load_b32 v86, v[46:47], off
	global_load_b32 v87, v[48:49], off
	global_load_b32 v88, v[50:51], off
	global_load_b32 v89, v[52:53], off
	global_load_b32 v90, v[54:55], off
	global_load_b32 v91, v[56:57], off
	global_load_b32 v92, v[58:59], off
	global_load_b32 v93, v[60:61], off
	global_load_b32 v94, v[62:63], off
	ds_load_b128 v[0:3], v27
	ds_load_b128 v[4:7], v27 offset:16
	ds_load_b128 v[40:43], v27 offset:32
	ds_load_b128 v[44:47], v27 offset:48
	ds_load_b128 v[48:51], v27 offset:64
	ds_load_b128 v[52:55], v27 offset:80
	ds_load_b128 v[56:59], v27 offset:96
	ds_load_b128 v[60:63], v27 offset:112
	ds_load_b128 v[64:67], v27 offset:128
	ds_load_b128 v[68:71], v27 offset:144
	ds_load_b128 v[72:75], v27 offset:160
	s_waitcnt vmcnt(15) lgkmcnt(8)
	v_fmac_f32_e32 v10, v76, v43
	v_fmac_f32_e32 v17, v76, v41
	v_fmac_f32_e32 v21, v76, v5
	v_fmac_f32_e32 v19, v76, v7
	v_fmac_f32_e32 v25, v76, v1
	s_waitcnt vmcnt(14) lgkmcnt(4)
	v_fmac_f32_e32 v10, v80, v59
	v_fmac_f32_e32 v15, v76, v42
	v_fmac_f32_e32 v23, v76, v3
	v_fmac_f32_e32 v19, v80, v55
	v_fmac_f32_e32 v20, v76, v6
	s_waitcnt vmcnt(13) lgkmcnt(0)
	v_dual_fmac_f32 v10, v81, v75 :: v_dual_fmac_f32 v17, v80, v57
	v_fmac_f32_e32 v18, v76, v40
	ds_load_b128 v[40:43], v27 offset:208
	v_dual_fmac_f32 v19, v81, v71 :: v_dual_fmac_f32 v20, v80, v54
	v_dual_fmac_f32 v17, v81, v73 :: v_dual_fmac_f32 v18, v80, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, v81, v70 :: v_dual_fmac_f32 v23, v80, v51
	v_dual_fmac_f32 v18, v81, v72 :: v_dual_fmac_f32 v21, v80, v53
	v_fmac_f32_e32 v22, v76, v4
	ds_load_b128 v[4:7], v27 offset:192
	v_dual_fmac_f32 v21, v81, v69 :: v_dual_fmac_f32 v22, v80, v52
	s_waitcnt vmcnt(12) lgkmcnt(1)
	v_fmac_f32_e32 v20, v82, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v22, v81, v68
	v_dual_fmac_f32 v24, v76, v2 :: v_dual_fmac_f32 v23, v81, v67
	v_fmac_f32_e32 v25, v80, v49
	v_fmac_f32_e32 v19, v82, v43
	v_fmac_f32_e32 v22, v82, v40
	v_fmac_f32_e32 v26, v76, v0
	ds_load_b128 v[0:3], v27 offset:176
	v_fmac_f32_e32 v12, v76, v45
	v_dual_fmac_f32 v24, v80, v50 :: v_dual_fmac_f32 v25, v81, v65
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v26, v80, v48 :: v_dual_fmac_f32 v23, v82, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, v80, v61
	v_dual_fmac_f32 v11, v76, v44 :: v_dual_fmac_f32 v24, v81, v66
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v9, v76, v47 :: v_dual_fmac_f32 v26, v81, v64
	v_fmac_f32_e32 v13, v76, v46
	ds_load_b128 v[44:47], v27 offset:224
	ds_load_b128 v[76:79], v27 offset:240
	ds_load_b128 v[48:51], v27 offset:256
	ds_load_b128 v[52:55], v27 offset:272
	v_dual_fmac_f32 v26, v82, v4 :: v_dual_fmac_f32 v15, v80, v58
	ds_load_b128 v[56:59], v27 offset:288
	v_fmac_f32_e32 v13, v80, v62
	v_dual_fmac_f32 v24, v82, v6 :: v_dual_fmac_f32 v9, v80, v63
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v12, v81, v1 :: v_dual_fmac_f32 v11, v80, v60
	ds_load_b128 v[60:63], v27 offset:304
	ds_load_b128 v[64:67], v27 offset:320
	ds_load_b128 v[68:71], v27 offset:336
	v_fmac_f32_e32 v25, v82, v5
	ds_load_b128 v[4:7], v27 offset:384
	v_fmac_f32_e32 v21, v82, v41
	ds_load_b128 v[40:43], v27 offset:400
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v18, v82, v44
	s_waitcnt vmcnt(11) lgkmcnt(7)
	v_dual_fmac_f32 v17, v82, v45 :: v_dual_fmac_f32 v26, v83, v48
	v_fmac_f32_e32 v15, v81, v74
	ds_load_b128 v[72:75], v27 offset:352
	v_dual_fmac_f32 v24, v83, v50 :: v_dual_fmac_f32 v11, v81, v0
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v22, v83, v52 :: v_dual_fmac_f32 v13, v81, v2
	v_dual_fmac_f32 v20, v83, v54 :: v_dual_fmac_f32 v9, v81, v3
	ds_load_b128 v[0:3], v27 offset:368
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v15, v82, v46 :: v_dual_fmac_f32 v18, v83, v56
	v_fmac_f32_e32 v10, v82, v47
	ds_load_b128 v[44:47], v27 offset:416
	v_fmac_f32_e32 v11, v82, v76
	v_fmac_f32_e32 v12, v82, v77
	v_fmac_f32_e32 v13, v82, v78
	s_waitcnt vmcnt(10) lgkmcnt(6)
	v_dual_fmac_f32 v9, v82, v79 :: v_dual_fmac_f32 v26, v84, v64
	ds_load_b128 v[76:79], v27 offset:432
	v_dual_fmac_f32 v25, v83, v49 :: v_dual_fmac_f32 v24, v84, v66
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v23, v83, v51 :: v_dual_fmac_f32 v22, v84, v68
	ds_load_b128 v[48:51], v27 offset:448
	v_dual_fmac_f32 v21, v83, v53 :: v_dual_fmac_f32 v20, v84, v70
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v19, v83, v55 :: v_dual_fmac_f32 v18, v84, v72
	ds_load_b128 v[52:55], v27 offset:464
	v_fmac_f32_e32 v10, v83, v59
	v_fmac_f32_e32 v17, v83, v57
	v_fmac_f32_e32 v12, v83, v61
	v_fmac_f32_e32 v15, v83, v58
	ds_load_b128 v[56:59], v27 offset:480
	s_waitcnt vmcnt(9)
	v_dual_fmac_f32 v11, v83, v60 :: v_dual_fmac_f32 v24, v85, v6
	v_dual_fmac_f32 v13, v83, v62 :: v_dual_fmac_f32 v26, v85, v4
	v_dual_fmac_f32 v9, v83, v63 :: v_dual_fmac_f32 v22, v85, v40
	ds_load_b128 v[60:63], v27 offset:496
	ds_load_b128 v[80:83], v27 offset:512
	v_fmac_f32_e32 v10, v84, v75
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v12, v84, v1
	v_dual_fmac_f32 v25, v84, v65 :: v_dual_fmac_f32 v20, v85, v42
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v23, v84, v67 :: v_dual_fmac_f32 v18, v85, v44
	ds_load_b128 v[64:67], v27 offset:528
	v_dual_fmac_f32 v21, v84, v69 :: v_dual_fmac_f32 v10, v85, v47
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v19, v84, v71 :: v_dual_fmac_f32 v12, v85, v77
	ds_load_b128 v[68:71], v27 offset:544
	s_waitcnt vmcnt(8) lgkmcnt(6)
	v_dual_fmac_f32 v17, v84, v73 :: v_dual_fmac_f32 v26, v86, v48
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v15, v84, v74 :: v_dual_fmac_f32 v22, v86, v52
	ds_load_b128 v[72:75], v27 offset:560
	v_dual_fmac_f32 v11, v84, v0 :: v_dual_fmac_f32 v24, v86, v50
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v13, v84, v2 :: v_dual_fmac_f32 v18, v86, v56
	v_dual_fmac_f32 v9, v84, v3 :: v_dual_fmac_f32 v20, v86, v54
	ds_load_b128 v[0:3], v27 offset:576
	v_dual_fmac_f32 v25, v85, v5 :: v_dual_fmac_f32 v10, v86, v59
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v23, v85, v7 :: v_dual_fmac_f32 v12, v86, v61
	ds_load_b128 v[4:7], v27 offset:592
	s_waitcnt vmcnt(7) lgkmcnt(5)
	v_dual_fmac_f32 v21, v85, v41 :: v_dual_fmac_f32 v26, v87, v80
	v_dual_fmac_f32 v19, v85, v43 :: v_dual_fmac_f32 v24, v87, v82
	ds_load_b128 v[40:43], v27 offset:608
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v17, v85, v45 :: v_dual_fmac_f32 v22, v87, v64
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v15, v85, v46 :: v_dual_fmac_f32 v18, v87, v68
	ds_load_b128 v[44:47], v27 offset:624
	v_dual_fmac_f32 v11, v85, v76 :: v_dual_fmac_f32 v20, v87, v66
	v_dual_fmac_f32 v13, v85, v78 :: v_dual_fmac_f32 v10, v87, v71
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v9, v85, v79 :: v_dual_fmac_f32 v12, v87, v73
	ds_load_b128 v[76:79], v27 offset:640
	s_waitcnt vmcnt(6) lgkmcnt(4)
	v_dual_fmac_f32 v25, v86, v49 :: v_dual_fmac_f32 v26, v88, v0
	v_dual_fmac_f32 v23, v86, v51 :: v_dual_fmac_f32 v24, v88, v2
	ds_load_b128 v[48:51], v27 offset:656
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v21, v86, v53 :: v_dual_fmac_f32 v22, v88, v4
	v_dual_fmac_f32 v19, v86, v55 :: v_dual_fmac_f32 v20, v88, v6
	ds_load_b128 v[52:55], v27 offset:672
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v17, v86, v57 :: v_dual_fmac_f32 v18, v88, v40
	v_dual_fmac_f32 v15, v86, v58 :: v_dual_fmac_f32 v10, v88, v43
	ds_load_b128 v[56:59], v27 offset:688
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v11, v86, v60 :: v_dual_fmac_f32 v12, v88, v45
	v_fmac_f32_e32 v13, v86, v62
	s_waitcnt vmcnt(5) lgkmcnt(3)
	v_dual_fmac_f32 v9, v86, v63 :: v_dual_fmac_f32 v24, v89, v78
	ds_load_b128 v[60:63], v27 offset:704
	v_fmac_f32_e32 v25, v87, v81
	v_fmac_f32_e32 v23, v87, v83
	ds_load_b128 v[80:83], v27 offset:720
	v_fmac_f32_e32 v21, v87, v65
	v_fmac_f32_e32 v19, v87, v67
	ds_load_b128 v[64:67], v27 offset:736
	v_dual_fmac_f32 v17, v87, v69 :: v_dual_fmac_f32 v26, v89, v76
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v10, v89, v55 :: v_dual_fmac_f32 v15, v87, v70
	ds_load_b128 v[68:71], v27 offset:752
	v_fmac_f32_e32 v11, v87, v72
	v_dual_fmac_f32 v22, v89, v48 :: v_dual_fmac_f32 v13, v87, v74
	v_dual_fmac_f32 v20, v89, v50 :: v_dual_fmac_f32 v9, v87, v75
	ds_load_b128 v[72:75], v27 offset:768
	ds_load_b128 v[84:87], v27 offset:784
	v_dual_fmac_f32 v18, v89, v52 :: v_dual_fmac_f32 v25, v88, v1
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v12, v89, v57 :: v_dual_fmac_f32 v23, v88, v3
	ds_load_b128 v[0:3], v27 offset:800
	s_waitcnt vmcnt(4) lgkmcnt(6)
	v_dual_fmac_f32 v26, v90, v60 :: v_dual_fmac_f32 v21, v88, v5
	v_fmac_f32_e32 v19, v88, v7
	ds_load_b128 v[4:7], v27 offset:816
	v_dual_fmac_f32 v24, v90, v62 :: v_dual_fmac_f32 v17, v88, v41
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v22, v90, v80 :: v_dual_fmac_f32 v15, v88, v42
	ds_load_b128 v[40:43], v27 offset:832
	v_dual_fmac_f32 v20, v90, v82 :: v_dual_fmac_f32 v11, v88, v44
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v18, v90, v64 :: v_dual_fmac_f32 v13, v88, v46
	v_dual_fmac_f32 v10, v90, v67 :: v_dual_fmac_f32 v25, v89, v77
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v12, v90, v69 :: v_dual_fmac_f32 v9, v88, v47
	ds_load_b128 v[44:47], v27 offset:848
	s_waitcnt vmcnt(3) lgkmcnt(5)
	v_dual_fmac_f32 v26, v91, v72 :: v_dual_fmac_f32 v23, v89, v79
	ds_load_b128 v[76:79], v27 offset:864
	v_dual_fmac_f32 v24, v91, v74 :: v_dual_fmac_f32 v21, v89, v49
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v22, v91, v84 :: v_dual_fmac_f32 v19, v89, v51
	ds_load_b128 v[48:51], v27 offset:880
	v_dual_fmac_f32 v20, v91, v86 :: v_dual_fmac_f32 v17, v89, v53
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v18, v91, v0 :: v_dual_fmac_f32 v15, v89, v54
	v_fmac_f32_e32 v10, v91, v3
	ds_load_b128 v[52:55], v27 offset:896
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v11, v89, v56 :: v_dual_fmac_f32 v12, v91, v5
	s_waitcnt vmcnt(2) lgkmcnt(4)
	v_dual_fmac_f32 v13, v89, v58 :: v_dual_fmac_f32 v26, v92, v40
	v_fmac_f32_e32 v24, v92, v42
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v20, v92, v46
	v_fmac_f32_e32 v22, v92, v44
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v18, v92, v76 :: v_dual_fmac_f32 v17, v90, v65
	v_dual_fmac_f32 v10, v92, v79 :: v_dual_fmac_f32 v15, v90, v66
	ds_load_b128 v[64:67], v27 offset:960
	v_fmac_f32_e32 v9, v89, v59
	ds_load_b128 v[56:59], v27 offset:912
	v_fmac_f32_e32 v25, v90, v61
	v_fmac_f32_e32 v23, v90, v63
	ds_load_b128 v[60:63], v27 offset:928
	v_fmac_f32_e32 v21, v90, v81
	v_fmac_f32_e32 v19, v90, v83
	ds_load_b128 v[80:83], v27 offset:944
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v9, v90, v71 :: v_dual_fmac_f32 v12, v92, v49
	v_fmac_f32_e32 v11, v90, v68
	v_fmac_f32_e32 v13, v90, v70
	ds_load_b128 v[68:71], v27 offset:976
	s_waitcnt vmcnt(1) lgkmcnt(5)
	v_fmac_f32_e32 v26, v93, v52
	v_dual_fmac_f32 v24, v93, v54 :: v_dual_fmac_f32 v25, v91, v73
	v_fmac_f32_e32 v13, v91, v6
	s_waitcnt vmcnt(0) lgkmcnt(4)
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_fmac_f32 v9, v91, v7 :: v_dual_fmac_f32 v24, v94, v66
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v25, v92, v41 :: v_dual_fmac_f32 v22, v93, v56
	v_fmac_f32_e32 v23, v91, v75
	ds_load_b128 v[72:75], v27 offset:992
	v_dual_fmac_f32 v20, v93, v58 :: v_dual_fmac_f32 v21, v91, v85
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v18, v93, v60 :: v_dual_fmac_f32 v19, v91, v87
	ds_load_b128 v[84:87], v27 offset:1008
	v_dual_fmac_f32 v10, v93, v63 :: v_dual_fmac_f32 v17, v91, v1
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v12, v93, v81 :: v_dual_fmac_f32 v15, v91, v2
	v_fmac_f32_e32 v11, v91, v4
	v_fmac_f32_e32 v13, v92, v50
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v9, v92, v51 :: v_dual_fmac_f32 v22, v94, v68
	v_fmac_f32_e32 v23, v92, v43
	v_dual_fmac_f32 v11, v92, v48 :: v_dual_fmac_f32 v20, v94, v70
	v_fmac_f32_e32 v21, v92, v45
	v_fmac_f32_e32 v25, v93, v53
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v23, v93, v55 :: v_dual_fmac_f32 v18, v94, v72
	v_fmac_f32_e32 v19, v92, v47
	v_dual_fmac_f32 v10, v94, v75 :: v_dual_fmac_f32 v17, v92, v77
	v_fmac_f32_e32 v21, v93, v57
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v12, v94, v85 :: v_dual_fmac_f32 v15, v92, v78
	v_fmac_f32_e32 v19, v93, v59
	v_fmac_f32_e32 v17, v93, v61
	v_fmac_f32_e32 v11, v93, v80
	v_fmac_f32_e32 v13, v93, v82
	v_fmac_f32_e32 v15, v93, v62
	v_dual_fmac_f32 v9, v93, v83 :: v_dual_fmac_f32 v26, v94, v64
	v_fmac_f32_e32 v25, v94, v65
	v_fmac_f32_e32 v23, v94, v67
	v_fmac_f32_e32 v21, v94, v69
	v_fmac_f32_e32 v19, v94, v71
	v_fmac_f32_e32 v17, v94, v73
	v_fmac_f32_e32 v15, v94, v74
	v_fmac_f32_e32 v11, v94, v84
	v_fmac_f32_e32 v13, v94, v86
	v_fmac_f32_e32 v9, v94, v87
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB3_2
; %bb.3:                                ; %Flow
	s_mov_b32 s0, 0
	s_branch .LBB3_5
.LBB3_4:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr16
.LBB3_5:                                ; %Flow186
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB3_7
; %bb.6:                                ; %.._crit_edge_crit_edge
	v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v25, 0
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v21, 0
	v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v19, 0
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v17, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v15, 0
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 0
	v_mov_b32_e32 v9, 0
.LBB3_7:                                ; %._crit_edge
	v_add_nc_u32_e32 v0, v16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, v0, s1
	v_add_co_ci_u32_e64 v1, null, 0, 0, s0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s12, s15, v[0:1]
	v_mov_b32_e32 v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s13, s15, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v26, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v25, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v24, off
	v_add_co_u32 v27, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v28, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v23, off
	v_add_co_u32 v0, vcc_lo, v27, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v28, vcc_lo
	global_store_b32 v[27:28], v22, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v21, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v20, off
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v19, off
	v_add_co_u32 v22, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v23, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v18, off
	v_add_co_u32 v0, vcc_lo, v22, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v23, vcc_lo
	global_store_b32 v[22:23], v17, off
	v_add_co_u32 v2, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v15, off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v16, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v17, vcc_lo
	global_store_b32 v[2:3], v10, off
	global_store_b32 v[4:5], v11, off
	global_store_b32 v[6:7], v12, off
	global_store_b32 v[16:17], v13, off
	global_store_b32 v[0:1], v9, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 95
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm, .Lfunc_end3-_ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3440
; NumSgprs: 22
; NumVgprs: 95
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 95
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm ; -- Begin function _ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.globl	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
	.p2align	8
	.type	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm,@function
_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm: ; @_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v10, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s15, 5, v2
	v_lshl_add_u32 v3, s14, 5, v10
	v_lshlrev_b32_e32 v9, 2, v10
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s16, 31
	s_addc_u32 s3, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s12, s[2:3], 31
	s_and_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccz .LBB4_10
; %bb.1:                                ; %.lr.ph
	v_mad_u64_u32 v[7:8], null, v0, s16, 0
	s_lshr_b64 s[12:13], s[2:3], 5
	v_or_b32_e32 v12, 0x1000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v8
	v_mad_u64_u32 v[4:5], null, v0, s17, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, v4
	v_dual_mov_b32 v6, v1 :: v_dual_lshlrev_b32 v11, 7, v2
	v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[0:1]
	v_add_nc_u32_e32 v13, v11, v9
	v_add_nc_u32_e32 v14, v12, v11
	v_cmp_le_u64_e64 s2, s[18:19], v[3:4]
	v_add_co_u32 v15, s3, s4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v16, s3, s5, v8, s3
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_co_u32 v15, s3, v15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v16, s3, 0, v16, s3
	s_mov_b64 s[4:5], 0
	v_add_co_u32 v17, s3, s6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v18, s3, s7, v8, s3
	s_xor_b32 s6, vcc_lo, -1
	s_xor_b32 s7, s2, -1
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_7 Depth 2
	s_lshl_b64 s[2:3], s[4:5], 5
	v_mov_b32_e32 v19, 0
	v_add_co_u32 v7, s20, s2, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, null, s3, 0, s20
	v_cmp_gt_u64_e32 vcc_lo, s[16:17], v[7:8]
	s_and_b32 s21, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s20, s21
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	s_lshl_b64 s[22:23], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v7, vcc_lo, v15, s22
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v16, vcc_lo
	global_load_b32 v19, v[7:8], off
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_add_co_u32 v7, s2, s2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, null, s3, 0, s2
	v_mov_b32_e32 v20, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v13, v19
	v_cmp_gt_u64_e32 vcc_lo, s[16:17], v[7:8]
	s_and_b32 s3, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB4_6
; %bb.5:                                ;   in Loop: Header=BB4_2 Depth=1
	v_mul_lo_u32 v8, v8, s18
	v_mul_lo_u32 v21, v7, s19
	v_mad_u64_u32 v[19:20], null, v7, s18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v20, v20, v21, v8
	v_lshlrev_b64 v[7:8], 2, v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v17, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v18, v8, vcc_lo
	global_load_b32 v20, v[7:8], off
.LBB4_6:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v7, v12
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v14, v20
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_7:                                ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v8, s2, v11
	s_add_i32 s2, s2, 4
	ds_load_b32 v19, v7
	ds_load_b32 v8, v8
	v_add_nc_u32_e32 v7, 0x80, v7
	s_cmpk_eq_i32 s2, 0x80
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v1, v8, v19
	s_cbranch_scc0 .LBB4_7
; %bb.8:                                ;   in Loop: Header=BB4_2 Depth=1
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[4:5], s[12:13]
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB4_2
; %bb.9:                                ; %Flow
	s_mov_b32 s2, 0
	s_branch .LBB4_11
.LBB4_10:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr5_vgpr6
.LBB4_11:                               ; %Flow80
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB4_13
; %bb.12:                               ; %.._crit_edge_crit_edge
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v6, v1
	v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0
.LBB4_13:                               ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[5:6]
	v_cmp_gt_u64_e64 s2, s[18:19], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_15
; %bb.14:
	s_load_b32 s0, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_mad_u64_u32 v[3:4], null, s15, s1, v[2:3]
	s_mov_b32 s1, 0
	s_mul_i32 s0, s14, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s18, 0
	s_addc_u32 s1, s1, s9
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v3, s19, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB4_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm, .Lfunc_end4-_ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 812
; NumSgprs: 26
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas38cudaBlas25naiveMatrixMultiplicationEPfS1_S1_mmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas38cudaBlas26sharedMatrixMultiplicationEPfS1_S1_mmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps32EPfS1_S1_mmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     104
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas38cudaBlas33MatrixMultiplication_reducedOps16EPfS1_S1_mmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     95
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas38cudaBlas10sharedGEMMEPfS1_S1_mmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
