#include "includes.h"



__device__ float fitness_function(float x[])
{
float y,yp;
float res=0;
float y1=1+(x[0]-1)/4;
float yn=1+(x[NUM_OF_DIMENSIONS-1]-1)/4;

res+=pow(sin(phi*y1),2)+pow(yn-1,2);

for(int i=0;i<NUM_OF_DIMENSIONS-1;i++)
{
y=1+(x[i]-1)/4;
yp=1+(x[i+1]-1)/4;
res+=pow(y-1,2)*(1+10*pow(sin(phi*yp),2));
}

return res;
}
__global__ void kernelUpdateGBest(float *gBest,float *pBests)
{
float temp[NUM_OF_DIMENSIONS];
for(int i=0;i<10*NUM_OF_DIMENSIONS;i+=NUM_OF_DIMENSIONS)
{
for(int k=0;k<NUM_OF_DIMENSIONS;k++)
temp[k]=pBests[i+k];

if(fitness_function(temp)<fitness_function(gBest))
{
for(int k=0;k<NUM_OF_DIMENSIONS;k++)
gBest[k]=temp[k];
}
}
}
	.file	"tmpxft_002f2fc6_00000000-6_kernelUpdateGBest.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z16fitness_functionPf
	.type	_Z16fitness_functionPf, @function
_Z16fitness_functionPf:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z16fitness_functionPf, .-_Z16fitness_functionPf
	.globl	_Z39__device_stub__Z17kernelUpdateGBestPfS_PfS_
	.type	_Z39__device_stub__Z17kernelUpdateGBestPfS_PfS_, @function
_Z39__device_stub__Z17kernelUpdateGBestPfS_PfS_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17kernelUpdateGBestPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z39__device_stub__Z17kernelUpdateGBestPfS_PfS_, .-_Z39__device_stub__Z17kernelUpdateGBestPfS_PfS_
	.globl	_Z17kernelUpdateGBestPfS_
	.type	_Z17kernelUpdateGBestPfS_, @function
_Z17kernelUpdateGBestPfS_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z17kernelUpdateGBestPfS_PfS_
	.cfi_endproc
.LFE2034:
	.size	_Z17kernelUpdateGBestPfS_, .-_Z17kernelUpdateGBestPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z17kernelUpdateGBestPfS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17kernelUpdateGBestPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"



__device__ float fitness_function(float x[])
{
float y,yp;
float res=0;
float y1=1+(x[0]-1)/4;
float yn=1+(x[NUM_OF_DIMENSIONS-1]-1)/4;

res+=pow(sin(phi*y1),2)+pow(yn-1,2);

for(int i=0;i<NUM_OF_DIMENSIONS-1;i++)
{
y=1+(x[i]-1)/4;
yp=1+(x[i+1]-1)/4;
res+=pow(y-1,2)*(1+10*pow(sin(phi*yp),2));
}

return res;
}
__global__ void kernelUpdateGBest(float *gBest,float *pBests)
{
float temp[NUM_OF_DIMENSIONS];
for(int i=0;i<10*NUM_OF_DIMENSIONS;i+=NUM_OF_DIMENSIONS)
{
for(int k=0;k<NUM_OF_DIMENSIONS;k++)
temp[k]=pBests[i+k];

if(fitness_function(temp)<fitness_function(gBest))
{
for(int k=0;k<NUM_OF_DIMENSIONS;k++)
gBest[k]=temp[k];
}
}
}
	.text
	.file	"kernelUpdateGBest.hip"
	.globl	_Z32__device_stub__kernelUpdateGBestPfS_ # -- Begin function _Z32__device_stub__kernelUpdateGBestPfS_
	.type	_Z32__device_stub__kernelUpdateGBestPfS_,@function
_Z32__device_stub__kernelUpdateGBestPfS_: # @_Z32__device_stub__kernelUpdateGBestPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17kernelUpdateGBestPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__kernelUpdateGBestPfS_, .Lfunc_end0-_Z32__device_stub__kernelUpdateGBestPfS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17kernelUpdateGBestPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17kernelUpdateGBestPfS_,@object # @_Z17kernelUpdateGBestPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z17kernelUpdateGBestPfS_
	.p2align	3, 0x0
_Z17kernelUpdateGBestPfS_:
	.quad	_Z32__device_stub__kernelUpdateGBestPfS_
	.size	_Z17kernelUpdateGBestPfS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17kernelUpdateGBestPfS_"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__kernelUpdateGBestPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17kernelUpdateGBestPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17kernelUpdateGBestPfS_ ; -- Begin function _Z17kernelUpdateGBestPfS_
	.globl	_Z17kernelUpdateGBestPfS_
	.p2align	8
	.type	_Z17kernelUpdateGBestPfS_,@function
_Z17kernelUpdateGBestPfS_:              ; @_Z17kernelUpdateGBestPfS_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, 0
	s_mov_b32 s2, 0x7fffff
	s_mov_b32 s8, 0xb94c1982
	s_mov_b32 s9, 0x37d75334
	s_mov_b32 s10, 0x3e76c4e1
.LBB0_1:                                ; %.preheader43
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
                                        ;     Child Loop BB0_8 Depth 2
                                        ;     Child Loop BB0_19 Depth 2
                                        ;     Child Loop BB0_26 Depth 2
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[0:1], s[6:7]
	s_mov_b32 s11, 0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v0, v1, s[0:1]
	s_add_i32 s12, s11, 4
	s_add_i32 s11, s11, 4
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s11, 12
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v0, s12
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	scratch_load_b32 v0, off, off offset:4
	scratch_load_b32 v4, off, off offset:12
                                        ; implicit-def: $vgpr5
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, -1.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, 0x3e800000, v0, 1.0
	v_mul_f32_e32 v2, 0x40490e56, v0
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v3, 0x7fffffff, v2
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s11, exec_lo, s1
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v13, v3, s2, 0x800000
	v_lshrrev_b32_e32 v10, 23, v3
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v13, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, 0xffffff88, v10
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v6
	v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v13, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v12, v11
	v_mov_b32_e32 v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v12
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v13, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v14, v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v0, v8 :: v_dual_cndmask_b32 v5, v7, v5
	v_cmp_lt_u32_e64 s1, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v13, v[0:1]
	v_mov_b32_e32 v0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v13, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v6, v5, s0
	v_mov_b32_e32 v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v13, v[0:1]
	v_mov_b32_e32 v0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0xa2f9836e, v13, v[0:1]
	v_cndmask_b32_e64 v0, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v13, v10, v8 :: v_dual_add_nc_u32 v0, v0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_sub_nc_u32_e32 v12, 32, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v11, v13, s0
	v_cndmask_b32_e64 v10, v10, v11, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v13, v9, s0
	v_cndmask_b32_e64 v9, v9, v6, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v10, v10, v8, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v11, s1
	v_cndmask_b32_e64 v11, v11, v9, s1
	v_cndmask_b32_e64 v5, v9, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v10, v8, v12
	v_alignbit_b32 v7, v8, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v13, v10, vcc_lo
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_alignbit_b32 v10, v11, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v0, 29, 1
	v_alignbit_b32 v8, v0, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_sub_nc_u32_e32 v9, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v10, 30
	v_alignbit_b32 v5, v10, v5, 30
	v_xor_b32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v9
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v11, v8
	v_lshlrev_b32_e32 v9, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v11, 32, v11
	v_or_b32_e32 v12, 0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v11
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v8, v8, v6, v10
	v_alignbit_b32 v5, v6, v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v13
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v10, v6
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v10
	v_alignbit_b32 v5, v6, v5, v14
	v_or_b32_e32 v6, v8, v12
	v_add_lshl_u32 v8, v10, v11, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v5, 9, v5
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v8
	v_fma_f32 v8, 0x3fc90fda, v6, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 0x33000000, v5
	v_fmac_f32_e32 v8, 0x33a22168, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v5, v9
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	v_lshrrev_b32_e32 v5, 30, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v0, v10, v8 :: v_dual_add_nc_u32 v5, v7, v5
.LBB0_5:                                ; %Flow82
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s0, s11
; %bb.6:                                ;   in Loop: Header=BB0_1 Depth=1
	v_mul_f32_e64 v0, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v0
	v_fma_f32 v0, 0xbfc90fda, v5, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0xb3a22168, v5
	v_fmac_f32_e32 v0, 0xa7c234c4, v5
	v_cvt_i32_f32_e32 v5, v5
; %bb.7:                                ; %_ZL3sinf.exit.i
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v6, v0, v0 :: v_dual_and_b32 v9, 1, v5
	v_xor_b32_e32 v3, v3, v2
	s_mov_b32 s11, -1
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v4, -1.0, v4 :: v_dual_fmaak_f32 v7, s8, v6, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_lshlrev_b32_e32 v5, 30, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v4, 0x3e800000, v4, 1.0
	v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v4, -1.0, v4 :: v_dual_and_b32 v5, 0x80000000, v5
	v_dual_fmaak_f32 v8, s9, v6, 0xbab64f3b :: v_dual_mul_f32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
	v_fmac_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v6, v8, 0xbf000004
	v_fma_f32 v6, v6, v8, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v6, v0, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	v_xor3_b32 v0, v3, v5, v0
	v_frexp_mant_f32_e64 v3, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v5, |v0|
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v2, v3, v2
	v_cndmask_b32_e64 v3, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, 1.0, v2
	v_ldexp_f32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v6
	v_dual_add_f32 v12, -1.0, v6 :: v_dual_add_f32 v7, 1.0, v3
	v_dual_add_f32 v11, -1.0, v3 :: v_dual_add_f32 v8, -1.0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, v2, v12
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v14, v11, v9
	v_mul_f32_e32 v10, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v12, -1.0, v7 :: v_dual_mul_f32 v15, v7, v14
	v_mul_f32_e32 v13, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v10, v6, -v13
	v_fmac_f32_e32 v6, v10, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, v3, v12
	v_fma_f32 v3, v14, v7, -v15
	v_add_f32_e32 v7, v13, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, v14, v2
	v_sub_f32_e32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v15, v3
	v_sub_f32_e32 v6, v13, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v11, v12
	v_dual_sub_f32 v11, v11, v16 :: v_dual_sub_f32 v2, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v2
	v_sub_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v7
	v_add_f32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v5, v2
	v_add_f32_e32 v5, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v11, v12 :: v_dual_sub_f32 v6, v5, v10
	v_sub_f32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v2, v2
	v_sub_f32_e32 v8, v12, v15
	v_sub_f32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v7
	v_add_f32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v9, v3
	v_add_f32_e32 v7, v14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v7, v14
	v_dual_mul_f32 v11, v7, v7 :: v_dual_mul_f32 v8, v5, v5
	v_sub_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v7, v7, -v11
	v_fma_f32 v9, v5, v5, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v9, v5, v10 :: v_dual_add_f32 v10, v3, v3
	v_fmac_f32_e32 v6, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v11, v6 :: v_dual_add_f32 v12, v8, v9
	v_dual_sub_f32 v11, v13, v11 :: v_dual_fmaak_f32 v10, s10, v12, 0x3e91f4c4
	v_sub_f32_e32 v8, v12, v8
	v_mul_f32_e32 v22, v7, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v6, v6, v11
	v_fmaak_f32 v10, v12, v10, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v9, v8 :: v_dual_mul_f32 v15, v12, v10
	v_fma_f32 v9, v12, v10, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v14, s10, v13, 0x3e91f4c4 :: v_dual_fmac_f32 v9, v8, v10
	v_dual_fmaak_f32 v14, v13, v14, 0x3ecccdef :: v_dual_add_f32 v11, v15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, 0x3f2aaaaa, v11
	v_dual_mul_f32 v16, v13, v14 :: v_dual_sub_f32 v15, v11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v13, v14, -v16
	v_sub_f32_e32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, 0xbf2aaaaa, v18
	v_dual_fmac_f32 v10, v6, v14 :: v_dual_add_f32 v9, 0x31739010, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v11, v15
	v_frexp_exp_i32_f32_e32 v14, v4
	v_add_f32_e32 v19, v16, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v9, v11
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, 0x3f2aaaaa, v19
	v_mul_f32_e32 v17, v5, v12
	v_dual_sub_f32 v16, v19, v16 :: v_dual_add_f32 v15, 0xbf2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, v12, v5, -v17
	v_sub_f32_e32 v10, v10, v16
	v_fma_f32 v16, v13, v7, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v11, v19, v15 :: v_dual_fmac_f32 v20, v12, v2
	v_add_f32_e32 v12, v18, v9
	v_fmac_f32_e32 v16, v13, v3
	v_ldexp_f32 v3, v3, 1
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v20, v8, v5 :: v_dual_sub_f32 v13, v18, v12
	v_ldexp_f32 v5, v5, 1
	v_cvt_f32_i32_e32 v8, v14
	v_dual_add_f32 v9, v9, v13 :: v_dual_fmac_f32 v16, v6, v7
	v_add_f32_e32 v10, 0x31739010, v10
	v_add_f32_e32 v6, v17, v20
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v11
	v_mul_f32_e32 v18, v6, v12
	v_sub_f32_e32 v17, v6, v17
	v_frexp_exp_i32_f32_e32 v11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v21, v10 :: v_dual_sub_f32 v17, v20, v17
	v_sub_f32_e32 v13, v21, v14
	v_add_f32_e32 v15, v22, v16
	v_fma_f32 v21, v6, v12, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v10, v13 :: v_dual_mul_f32 v19, v15, v14
	v_dual_sub_f32 v20, v15, v22 :: v_dual_fmac_f32 v21, v6, v9
	v_subrev_co_ci_u32_e64 v6, vcc_lo, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v13, v15, v14, -v19
	v_sub_f32_e32 v9, v16, v20
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v0|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v6, v6
	v_fmac_f32_e32 v13, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v9, v14
	v_dual_fmac_f32 v21, v17, v12 :: v_dual_add_f32 v12, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v7, v12
	v_dual_sub_f32 v7, v17, v7 :: v_dual_mul_f32 v10, 0x3f317218, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v18, v21
	v_sub_f32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v11, 0x3f317218, v8, -v10
	v_add_f32_e32 v15, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v9, v18 :: v_dual_fmac_f32 v11, 0xb102e308, v8
	v_dual_sub_f32 v18, v12, v19 :: v_dual_sub_f32 v5, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v18
	v_dual_mul_f32 v14, 0x3f317218, v6 :: v_dual_sub_f32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v13
	v_fma_f32 v9, 0x3f317218, v6, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v7
	v_dual_fmac_f32 v9, 0xb102e308, v6 :: v_dual_sub_f32 v16, v21, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v17, v3 :: v_dual_add_f32 v7, v14, v9
	v_sub_f32_e32 v17, v8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v13, v7, v8
	v_add_f32_e32 v2, v2, v16
	v_sub_f32_e32 v14, v7, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v17
	v_dual_add_f32 v2, v2, v5 :: v_dual_sub_f32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v10, v11 :: v_dual_add_f32 v6, v15, v2
	v_sub_f32_e32 v10, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v5, v6
	v_dual_sub_f32 v10, v11, v10 :: v_dual_sub_f32 v11, v6, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v12, v5 :: v_dual_sub_f32 v15, v13, v7
	v_sub_f32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v13, v15 :: v_dual_sub_f32 v14, v12, v16
	v_sub_f32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v5, v14 :: v_dual_sub_f32 v8, v8, v15
	v_dual_sub_f32 v6, v6, v16 :: v_dual_add_f32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v6, v5
	v_dual_add_f32 v11, v10, v2 :: v_dual_add_f32 v6, v9, v3
	v_add_f32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v11, v10 :: v_dual_add_f32 v7, v6, v7
	v_sub_f32_e32 v14, v6, v9
	v_dual_add_f32 v15, v12, v5 :: v_dual_sub_f32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v11, v11, v8 :: v_dual_sub_f32 v6, v6, v14
	v_dual_add_f32 v8, v13, v7 :: v_dual_sub_f32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v10, v10, v11 :: v_dual_sub_f32 v11, v15, v12
	v_dual_sub_f32 v6, v9, v6 :: v_dual_sub_f32 v9, v8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v2, v10 :: v_dual_sub_f32 v5, v5, v11
	v_dual_add_f32 v3, v3, v6 :: v_dual_add_f32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v15, v2
	v_dual_sub_f32 v6, v7, v9 :: v_dual_sub_f32 v7, v5, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v3, v6 :: v_dual_sub_f32 v2, v2, v7
	v_dual_add_f32 v6, v8, v3 :: v_dual_add_f32 v9, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v10, 0, v5 :: v_dual_add_f32 v7, v6, v6
	v_sub_f32_e32 v8, v6, v8
	v_fma_f32 v5, v5, 2.0, -v9
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_mul_f32_e32 v11, 0, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v3, v3, v8 :: v_dual_fmac_f32 v10, 2.0, v2
	v_fma_f32 v2, v6, 2.0, -v7
	v_fmac_f32_e32 v11, 2.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v5, v10 :: v_dual_add_f32 v2, v2, v11
	v_dual_add_f32 v5, v9, v3 :: v_dual_add_f32 v6, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v5, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	v_dual_sub_f32 v5, v5, v9 :: v_dual_cndmask_b32 v10, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8
	v_sub_f32_e32 v6, v6, v7
	v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v2, v2, v6 :: v_dual_sub_f32 v3, v3, v5
	v_sub_f32_e32 v13, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, 0x3fb8aa3b, v13
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_rndne_f32_e32 v20, v15
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v8, v20
	v_sub_f32_e32 v14, v10, v12
	v_fma_f32 v17, 0x3fb8aa3b, v13, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v15, v20 :: v_dual_mul_f32 v16, 0x3fb8aa3b, v14
	v_fma_f32 v18, 0x3fb8aa3b, v14, -v16
	v_rndne_f32_e32 v19, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v17, 0x32a5705f, v13 :: v_dual_fmac_f32 v18, 0x32a5705f, v14
	v_dual_sub_f32 v16, v16, v19 :: v_dual_add_f32 v15, v15, v17
	v_cvt_i32_f32_e32 v7, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v16, v18
	v_exp_f32_e32 v5, v9
	s_delay_alu instid0(VALU_DEP_3)
	v_exp_f32_e32 v9, v15
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v5, v7
	v_ldexp_f32 v6, v9, v8
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_add_f32 v2, v12, v2 :: v_dual_cndmask_b32 v5, 0, v5
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_add_f32_e32 v3, v11, v3
	v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v5, v2, v5
	v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
	v_fma_f32 v3, v6, v3, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, 0x7f800000, |v2|, s0
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v4|
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v3, 0x7f800000, |v3|, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, 0, v2, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	s_mov_b32 s0, 0
	v_cndmask_b32_e32 v2, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v2, v0
.LBB0_8:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b32 s0, s0, 2
                                        ; implicit-def: $vgpr6
	s_mov_b32 s1, exec_lo
	s_add_i32 s0, s0, 4
	scratch_load_b64 v[2:3], off, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, -1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, 0x3e800000, v0, 1.0
	v_mul_f32_e32 v3, 0x40490e56, v0
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v5, 0x7fffffff, v3
	v_cmpx_ngt_f32_e64 0x48000000, |v3|
	s_xor_b32 s12, exec_lo, s1
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v11, 23, v5
	v_and_or_b32 v14, v5, s2, 0x800000
	v_add_nc_u32_e32 v12, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v14, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v12
	v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v7 :: v_dual_add_nc_u32 v13, v13, v12
	v_mad_u64_u32 v[7:8], null, 0x3c439041, v14, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v13
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v8 :: v_dual_add_nc_u32 v15, v15, v13
	v_mad_u64_u32 v[8:9], null, 0xdb629599, v14, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v15
	v_mov_b32_e32 v0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v14, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v10 :: v_dual_cndmask_b32 v7, v9, v7
	v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v14, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v7, v6, s0
	v_mov_b32_e32 v0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0x4e441529, v14, v[0:1]
	v_mov_b32_e32 v0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[12:13], null, 0xa2f9836e, v14, v[0:1]
	v_cndmask_b32_e64 v0, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v14, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v0, v0, v15
	v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
	v_cndmask_b32_e32 v10, v10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v13, 32, v0
	v_cndmask_b32_e64 v9, v12, v14, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v12, s0
	v_cndmask_b32_e64 v12, v14, v10, s0
	v_cndmask_b32_e64 v10, v10, v7, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v9, s1
	v_cndmask_b32_e64 v9, v9, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, v10, s1
	v_cndmask_b32_e64 v6, v10, v6, s1
	v_alignbit_b32 v14, v11, v9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v8, v9, v12, v13
	v_dual_cndmask_b32 v0, v14, v11 :: v_dual_cndmask_b32 v7, v8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v11, v12, v6, v13
	v_bfe_u32 v8, v0, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v0, v7, 30
	v_cndmask_b32_e32 v11, v11, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 0, v8
	v_alignbit_b32 v7, v7, v11, 30
	v_alignbit_b32 v6, v11, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v10
	v_xor_b32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v6, v10
	v_lshrrev_b32_e32 v10, 29, v0
	v_clz_i32_u32_e32 v12, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v10, 31, v10
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v13, 0.5, v10
	v_sub_nc_u32_e32 v11, 31, v12
	v_lshlrev_b32_e32 v14, 23, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v9, v7, v11
	v_alignbit_b32 v6, v7, v6, v11
	v_sub_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v9, v6, 9
	v_lshrrev_b32_e32 v9, 9, v9
	v_clz_i32_u32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v15, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v7, v6, v15
	v_or_b32_e32 v7, v9, v13
	v_add_lshl_u32 v9, v11, v12, 23
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v7
	v_sub_nc_u32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3fc90fda, v7, -v11
	v_add_nc_u32_e32 v6, 0x33000000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, 0x33a22168, v7
	v_or_b32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, 0x3fc90fda, v6
	v_lshrrev_b32_e32 v6, 30, v0
	v_add_f32_e32 v0, v11, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v8, v6
.LBB0_10:                               ; %Flow79
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_and_not1_saveexec_b32 s0, s12
; %bb.11:                               ;   in Loop: Header=BB0_8 Depth=2
	v_mul_f32_e64 v0, 0x3f22f983, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v0
	v_fma_f32 v0, 0xbfc90fda, v6, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0xb3a22168, v6
	v_fmac_f32_e32 v0, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
; %bb.12:                               ; %_ZL3sinf.exit22.i
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v7, v0, v0 :: v_dual_and_b32 v10, 1, v6
	v_xor_b32_e32 v5, v5, v3
	s_xor_b32 s1, s11, -1
	s_mov_b32 s11, 0
	v_fmaak_f32 v8, s8, v7, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_lshlrev_b32_e32 v6, 30, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
	v_fmaak_f32 v9, s9, v7, 0xbab64f3b
	v_and_b32_e32 v6, 0x80000000, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v7, v8
	v_dual_fmaak_f32 v9, v7, v9, 0x3d2aabf7 :: v_dual_fmac_f32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v9, v7, v9, 0xbf000004
	v_fma_f32 v7, v7, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v7, v0, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
	v_xor3_b32 v0, v5, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	v_frexp_mant_f32_e64 v5, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v7, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v5, v5, v7
	v_add_f32_e32 v7, 1.0, v5
	v_add_f32_e32 v11, -1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_dual_add_f32 v2, -1.0, v2 :: v_dual_mul_f32 v13, v11, v9
	v_fma_f32 v2, 0x3e800000, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v17, v7, v13 :: v_dual_add_f32 v2, -1.0, v2
	v_add_f32_e32 v16, -1.0, v7
	v_fma_f32 v7, v13, v7, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v3, |v2|
	v_sub_f32_e32 v5, v5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
	v_fmac_f32_e32 v7, v13, v5
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v17, v7
	v_ldexp_f32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v5, v17
	v_sub_f32_e32 v16, v11, v5
	v_add_f32_e32 v6, 1.0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v10, -1.0, v3 :: v_dual_sub_f32 v11, v11, v16
	v_sub_f32_e32 v7, v17, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v5, v11, v5 :: v_dual_mul_f32 v12, v10, v8
	v_add_f32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v15, v6, v12 :: v_dual_add_f32 v14, -1.0, v6
	v_frexp_exp_i32_f32_e32 v19, v2
	v_fma_f32 v6, v12, v6, -v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v14
	v_frexp_exp_i32_f32_e32 v24, v0
	v_fmac_f32_e32 v6, v12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v15, v6
	v_sub_f32_e32 v14, v10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v3, v15 :: v_dual_sub_f32 v10, v10, v14
	v_dual_sub_f32 v6, v15, v6 :: v_dual_sub_f32 v3, v10, v3
	v_add_f32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v9, v5
	v_add_f32_e32 v7, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v7, v13
	v_sub_f32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v5, v5
	v_add_f32_e32 v3, v6, v3
	v_add_f32_e32 v3, v14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v8, v3
	v_add_f32_e32 v6, v12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, v6, v6
	v_sub_f32_e32 v8, v6, v12
	v_fma_f32 v9, v6, v6, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v8
	v_add_f32_e32 v11, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v6, v11
	v_add_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, s10, v11, 0x3e91f4c4
	v_mul_f32_e32 v8, v7, v7
	v_sub_f32_e32 v10, v11, v10
	v_fmaak_f32 v14, v11, v14, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v7, v7, -v8
	v_mul_f32_e32 v16, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v10 :: v_dual_fmac_f32 v12, v7, v13
	v_fma_f32 v10, v11, v14, -v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v9, v14
	v_mul_f32_e32 v18, v6, v11
	v_fma_f32 v14, v11, v6, -v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v8, v12 :: v_dual_fmac_f32 v14, v11, v3
	v_dual_fmaak_f32 v15, s10, v13, 0x3e91f4c4 :: v_dual_sub_f32 v8, v13, v8
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v15, v13, v15, 0x3ecccdef :: v_dual_sub_f32 v8, v12, v8
	v_mul_f32_e32 v17, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v13, v15, -v17
	v_fmac_f32_e32 v12, v8, v15
	v_add_f32_e32 v15, v16, v10
	v_fmac_f32_e32 v14, v9, v6
	v_ldexp_f32 v6, v6, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v15, v16
	v_add_f32_e32 v20, v17, v12
	v_sub_f32_e32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v22, 0x3f2aaaaa, v20 :: v_dual_mul_f32 v11, v7, v13
	v_sub_f32_e32 v17, v20, v17
	v_add_f32_e32 v21, 0x3f2aaaaa, v15
	v_add_f32_e32 v10, 0x31739010, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, v13, v7, -v11
	v_sub_f32_e32 v12, v12, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v16, 0xbf2aaaaa, v21 :: v_dual_add_f32 v17, 0xbf2aaaaa, v22
	v_dual_add_f32 v12, 0x31739010, v12 :: v_dual_fmac_f32 v23, v13, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v13, v15, v16
	v_sub_f32_e32 v15, v20, v17
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v19, vcc_lo
	v_ldexp_f32 v5, v5, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v9, v10, v13 :: v_dual_add_f32 v10, v12, v15
	v_add_f32_e32 v12, v18, v14
	v_add_f32_e32 v15, v22, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v12, v18
	v_sub_f32_e32 v20, v22, v15
	v_fmac_f32_e32 v23, v8, v7
	v_cvt_f32_i32_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v18
	v_ldexp_f32 v7, v7, 1
	v_add_f32_e32 v10, v10, v20
	v_dual_add_f32 v16, v11, v23 :: v_dual_add_f32 v13, v21, v9
	v_dual_mul_f32 v17, 0x3f317218, v8 :: v_dual_mul_f32 v22, v12, v13
	v_sub_f32_e32 v19, v21, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, v12, v13, -v22
	v_add_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v20, v12, v9
	v_mul_f32_e32 v21, v16, v15
	v_subrev_co_ci_u32_e64 v9, vcc_lo, 0, v24, s0
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	v_fmac_f32_e32 v20, v14, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v16, v15, -v21
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v12, v22, v20 :: v_dual_sub_f32 v11, v16, v11
	v_fmac_f32_e32 v19, v16, v10
	v_fma_f32 v10, 0x3f317218, v8, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, v6, v12 :: v_dual_sub_f32 v11, v23, v11
	v_sub_f32_e32 v18, v12, v22
	v_fmac_f32_e32 v10, 0xb102e308, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v6, v16, v6 :: v_dual_fmac_f32 v19, v11, v15
	v_sub_f32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v6, v12, v6 :: v_dual_add_f32 v11, v21, v19
	v_mul_f32_e32 v13, 0x3f317218, v9
	v_add_f32_e32 v3, v3, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v7, v11
	v_sub_f32_e32 v15, v11, v21
	v_add_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v6, v17, v10 :: v_dual_sub_f32 v7, v14, v7
	v_sub_f32_e32 v15, v19, v15
	v_fma_f32 v19, 0x3f317218, v9, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v11, v7
	v_add_f32_e32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, 0xb102e308, v9
	v_add_f32_e32 v9, v16, v3
	v_sub_f32_e32 v11, v6, v17
	v_add_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v9, v16
	v_sub_f32_e32 v10, v10, v11
	v_add_f32_e32 v15, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v14, v5 :: v_dual_sub_f32 v17, v15, v6
	v_dual_add_f32 v7, v13, v19 :: v_dual_sub_f32 v14, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v7, v8
	v_sub_f32_e32 v11, v7, v13
	v_sub_f32_e32 v5, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v12, v7
	v_dual_sub_f32 v18, v12, v13 :: v_dual_sub_f32 v3, v3, v16
	v_sub_f32_e32 v8, v8, v13
	v_sub_f32_e32 v16, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v7, v7, v18
	v_add_f32_e32 v13, v10, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v6, v16 :: v_dual_sub_f32 v9, v9, v17
	v_add_f32_e32 v6, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v13, v6 :: v_dual_add_f32 v7, v8, v7
	v_dual_sub_f32 v8, v13, v10 :: v_dual_sub_f32 v11, v19, v11
	v_sub_f32_e32 v13, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v10, v13
	v_add_f32_e32 v14, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v14, v7
	v_dual_add_f32 v16, v12, v7 :: v_dual_sub_f32 v3, v3, v8
	v_dual_add_f32 v8, v15, v6 :: v_dual_sub_f32 v9, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v3, v3, v10 :: v_dual_sub_f32 v14, v14, v9
	v_sub_f32_e32 v5, v5, v9
	v_sub_f32_e32 v9, v11, v14
	v_sub_f32_e32 v11, v16, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v8, v15 :: v_dual_add_f32 v5, v5, v9
	v_dual_sub_f32 v7, v7, v11 :: v_dual_sub_f32 v6, v6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v7
	v_dual_add_f32 v3, v3, v6 :: v_dual_add_f32 v6, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v6, v16
	v_dual_add_f32 v10, v6, v6 :: v_dual_add_f32 v7, v8, v3
	v_mul_f32_e32 v11, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v5, v9
	v_fma_f32 v6, v6, 2.0, -v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v7, v8
	v_mul_f32_e32 v12, 0, v7
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_fmac_f32_e32 v11, 2.0, v5
	v_sub_f32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, 2.0, v3
	v_add_f32_e32 v3, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v10, v3
	v_cndmask_b32_e32 v8, v6, v10, vcc_lo
	v_dual_sub_f32 v6, v6, v10 :: v_dual_add_f32 v9, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v6
	v_fma_f32 v5, v7, 2.0, -v9
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v12
	v_add_f32_e32 v7, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v11, v7, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8
	v_sub_f32_e32 v7, v7, v9
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v5, v7 :: v_dual_sub_f32 v14, v8, v12
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
	v_dual_mul_f32 v16, 0x3fb8aa3b, v14 :: v_dual_sub_f32 v15, v11, v13
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v18, 0x3fb8aa3b, v14, -v16
	v_mul_f32_e32 v17, 0x3fb8aa3b, v15
	v_rndne_f32_e32 v19, v16
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	v_fmac_f32_e32 v18, 0x32a5705f, v14
	v_fma_f32 v20, 0x3fb8aa3b, v15, -v17
	v_rndne_f32_e32 v21, v17
	v_sub_f32_e32 v16, v16, v19
	v_cvt_i32_f32_e32 v6, v19
	v_add_f32_e32 v3, v12, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v20, 0x32a5705f, v15 :: v_dual_sub_f32 v17, v17, v21
	v_add_f32_e32 v16, v16, v18
	v_cvt_i32_f32_e32 v7, v21
	v_add_f32_e32 v5, v13, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v17, v17, v20
	v_exp_f32_e32 v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v9, v17
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v10, v6
	v_ldexp_f32 v7, v9, v7
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v6, v3, v6
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
	v_fma_f32 v5, v7, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	v_fma_f32 v3, 0x41200000, |v3|, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
	v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_mov_b32 s0, 1
	v_cndmask_b32_e32 v2, 0, v5, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 1.0, v3, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v2, v0
	s_cbranch_vccnz .LBB0_8
; %bb.13:                               ; %_Z16fitness_functionPf.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b32 v0, v1, s[4:5]
	global_load_b32 v2, v1, s[4:5] offset:8
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, -1.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, 0x3e800000, v0, 1.0
	v_mul_f32_e32 v0, 0x40490e56, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e64 s0, 0x48000000, |v0|
	v_readfirstlane_b32 s1, v0
	s_and_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, s1, 0x7fffffff
	s_cbranch_vccz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_1 Depth=1
	s_and_b32 s1, s0, 0x7fffff
	s_lshr_b32 s11, s0, 23
	s_bitset1_b32 s1, 23
	s_addk_i32 s11, 0xff88
	s_mul_hi_u32 s12, s1, 0xfe5163ab
	s_mul_i32 s13, s1, 0x3c439041
	s_mul_hi_u32 s14, s1, 0x3c439041
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s14
	s_mul_i32 s14, s1, 0xdb629599
	s_mul_hi_u32 s15, s1, 0xdb629599
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s15
	s_mul_i32 s15, s1, 0xf534ddc0
	s_mul_hi_u32 s16, s1, 0xf534ddc0
	s_add_u32 s14, s14, s15
	s_addc_u32 s15, 0, s16
	s_mul_i32 s16, s1, 0xfc2757d1
	s_mul_hi_u32 s17, s1, 0xfc2757d1
	s_add_u32 s15, s15, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s1, 0x4e441529
	s_mul_hi_u32 s18, s1, 0x4e441529
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_cmp_gt_u32 s11, 63
	s_mul_i32 s18, s1, 0xfe5163ab
	s_mul_hi_u32 s19, s1, 0xa2f9836e
	s_mul_i32 s1, s1, 0xa2f9836e
	s_cselect_b32 s20, s13, s15
	s_cselect_b32 s12, s12, s14
	s_cselect_b32 s13, s18, s13
	s_add_u32 s1, s17, s1
	s_addc_u32 s17, 0, s19
	s_cmp_gt_u32 s11, 63
	s_cselect_b32 s18, 0xffffffc0, 0
	s_cselect_b32 s14, s14, s16
	s_cselect_b32 s1, s15, s1
	s_cselect_b32 s15, s16, s17
	s_add_i32 s18, s18, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s18, 31
	s_cselect_b32 s11, 0xffffffe0, 0
	s_cselect_b32 s16, s14, s1
	s_cselect_b32 s1, s1, s15
	s_cselect_b32 s14, s20, s14
	s_cselect_b32 s15, s12, s20
	s_cselect_b32 s12, s13, s12
	s_add_i32 s11, s11, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s11, 31
	s_cselect_b32 s13, 0xffffffe0, 0
	s_cselect_b32 s1, s16, s1
	s_cselect_b32 s16, s14, s16
	s_cselect_b32 s14, s15, s14
	s_cselect_b32 s12, s12, s15
	s_add_i32 s13, s13, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s11, 32, s13
	s_cmp_eq_u32 s13, 0
	v_mov_b32_e32 v3, s11
	s_cselect_b32 s13, -1, 0
	v_alignbit_b32 v5, s1, s16, v3
	v_alignbit_b32 v6, s16, s14, v3
	v_alignbit_b32 v3, s14, s12, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s11, v5
	v_cndmask_b32_e64 v5, v6, s16, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, s14, s13
	s_cselect_b32 s1, s1, s11
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s1, v5, 30
	s_bfe_u32 s11, s1, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v5, v5, v3, 30
	s_sub_i32 s15, 0, s11
	v_alignbit_b32 v3, v3, s12, 30
	v_xor_b32_e32 v6, s15, v6
	s_lshr_b32 s12, s1, 29
	v_xor_b32_e32 v5, s15, v5
	s_lshl_b32 s12, s12, 31
	v_xor_b32_e32 v3, s15, v3
	v_clz_i32_u32_e32 v7, v6
	s_or_b32 s13, s12, 0.5
	s_lshr_b32 s1, s1, 30
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s11, s11, s1
	v_min_u32_e32 v7, 32, v7
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, 31, v7
	v_lshlrev_b32_e32 v9, 23, v7
	v_alignbit_b32 v6, v6, v5, v8
	v_alignbit_b32 v3, v5, v3, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, s13, v9
	v_alignbit_b32 v5, v6, v3, 9
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v8, v5
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v8
	v_add_nc_u32_e32 v7, v8, v7
	v_alignbit_b32 v3, v5, v3, v10
	v_or_b32_e32 v5, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v6, 23, v7
	v_lshrrev_b32_e32 v3, 9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v6
	v_add_nc_u32_e32 v3, 0x33000000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v3, s12, v3
	v_mul_f32_e32 v7, 0x3fc90fda, v5
	v_fma_f32 v6, 0x3fc90fda, v5, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0x33a22168, v5
	v_fmac_f32_e32 v6, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v3, v7, v6
	s_branch .LBB0_16
.LBB0_15:                               ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $vgpr3
.LBB0_16:                               ; %Flow77
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v5, s11
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_1 Depth=1
	v_mul_f32_e64 v3, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v3
	v_fma_f32 v3, 0xbfc90fda, v5, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v5
	v_fmac_f32_e32 v3, 0xa7c234c4, v5
	v_cvt_i32_f32_e32 v5, v5
.LBB0_18:                               ; %_ZL3sinf.exit.i18
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v6, v3, v3 :: v_dual_lshlrev_b32 v9, 30, v5
	v_xor_b32_e32 v10, s0, v0
	s_mov_b32 s11, -1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, -1.0, v2
	v_fmaak_f32 v7, s8, v6, 0x3c0881c4
	v_and_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v2, 0x3e800000, v2, 1.0
	v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
	v_fmaak_f32 v8, s9, v6, 0xbab64f3b
	v_and_b32_e32 v9, 0x80000000, v9
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v2, -1.0, v2 :: v_dual_mul_f32 v7, v6, v7
	v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v5, |v2|
	v_dual_fmac_f32 v3, v3, v7 :: v_dual_fmaak_f32 v8, v6, v8, 0xbf000004
	v_xor_b32_e32 v7, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v6, v8, 1.0
	v_cndmask_b32_e32 v3, v6, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v7, v3
	v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v6, |v0|
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v3, v5, v3
	v_cndmask_b32_e64 v5, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, 1.0, v3
	v_ldexp_f32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v7
	v_dual_add_f32 v13, -1.0, v7 :: v_dual_add_f32 v8, 1.0, v5
	v_dual_add_f32 v12, -1.0, v5 :: v_dual_add_f32 v9, -1.0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v9, v6
	v_dual_mul_f32 v14, v7, v11 :: v_dual_mul_f32 v15, v12, v10
	v_sub_f32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v11, v7, -v14
	v_mul_f32_e32 v16, v8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v11, v3
	v_add_f32_e32 v13, -1.0, v8
	v_sub_f32_e32 v3, v5, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v5, v15, v8, -v16
	v_add_f32_e32 v8, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v5, v15, v3 :: v_dual_sub_f32 v14, v8, v14
	v_add_f32_e32 v13, v16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v14, v7
	v_sub_f32_e32 v17, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v12, v17 :: v_dual_sub_f32 v3, v9, v8
	v_sub_f32_e32 v9, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v9, v8
	v_sub_f32_e32 v9, v13, v16
	v_add_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v9, v5
	v_sub_f32_e32 v8, v12, v13
	v_add_f32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v17, v5
	v_mul_f32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v15, v5
	v_dual_add_f32 v3, v3, v7 :: v_dual_mul_f32 v12, v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v6, v3
	v_add_f32_e32 v6, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v6, v11
	v_mul_f32_e32 v9, v6, v6
	v_sub_f32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v6, v6, -v9
	v_sub_f32_e32 v7, v8, v15
	v_add_f32_e32 v11, v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v5, v7
	v_fma_f32 v7, v8, v8, -v12
	v_fmac_f32_e32 v10, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v9, v10
	v_mul_f32_e32 v18, v6, v13
	v_add_f32_e32 v11, v5, v5
	v_sub_f32_e32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v8, v11
	v_fmaak_f32 v11, s10, v13, 0x3e91f4c4
	v_dual_sub_f32 v9, v10, v9 :: v_dual_add_f32 v14, v12, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v11, v13, v11, 0x3ecccdef
	v_dual_fmaak_f32 v15, s10, v14, 0x3e91f4c4 :: v_dual_mul_f32 v16, v13, v11
	v_dual_sub_f32 v12, v14, v12 :: v_dual_mul_f32 v23, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v15, v14, v15, 0x3ecccdef
	v_fma_f32 v10, v13, v11, -v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v7, v12
	v_mul_f32_e32 v17, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v9, v11
	v_fma_f32 v11, v14, v15, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v12, v16, v10 :: v_dual_fmac_f32 v11, v7, v15
	v_add_f32_e32 v19, 0x3f2aaaaa, v12
	v_sub_f32_e32 v16, v12, v16
	v_frexp_exp_i32_f32_e32 v15, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, v17, v11
	v_sub_f32_e32 v10, v10, v16
	v_add_f32_e32 v16, 0xbf2aaaaa, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	v_dual_sub_f32 v17, v20, v17 :: v_dual_add_f32 v22, 0x3f2aaaaa, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, 0x31739010, v10
	v_dual_sub_f32 v12, v12, v16 :: v_dual_sub_f32 v11, v11, v17
	v_fma_f32 v17, v14, v8, -v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, 0xbf2aaaaa, v22
	v_dual_add_f32 v10, v10, v12 :: v_dual_add_f32 v11, 0x31739010, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v17, v14, v5 :: v_dual_sub_f32 v12, v20, v16
	v_fmac_f32_e32 v17, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v11, v11, v12
	v_ldexp_f32 v8, v8, 1
	v_frexp_exp_i32_f32_e32 v12, v0
	v_add_f32_e32 v16, v23, v17
	v_fma_f32 v21, v13, v6, -v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, v13, v3
	v_add_f32_e32 v13, v19, v10
	v_ldexp_f32 v3, v3, 1
	v_fmac_f32_e32 v21, v9, v6
	v_cvt_f32_i32_e32 v9, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v14, v19, v13 :: v_dual_add_f32 v15, v22, v11
	v_ldexp_f32 v6, v6, 1
	v_ldexp_f32 v5, v5, 1
	v_add_f32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v22, v15
	v_dual_mul_f32 v20, v16, v15 :: v_dual_add_f32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v16, v15, -v20
	v_dual_fmac_f32 v14, v16, v11 :: v_dual_mul_f32 v11, 0x3f317218, v9
	v_add_f32_e32 v7, v18, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, v7, v13
	v_sub_f32_e32 v18, v7, v18
	v_fma_f32 v22, v7, v13, -v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v22, v7, v10
	v_subrev_co_ci_u32_e64 v7, vcc_lo, 0, v12, s0
	v_fma_f32 v12, 0x3f317218, v9, -v11
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v0|
	v_cvt_f32_i32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0xb102e308, v9
	v_dual_sub_f32 v18, v21, v18 :: v_dual_sub_f32 v21, v16, v23
	v_fmac_f32_e32 v22, v18, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v17, v21
	v_fmac_f32_e32 v14, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v19, v22 :: v_dual_mul_f32 v15, 0x3f317218, v7
	v_add_f32_e32 v13, v20, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v10, v19
	v_add_f32_e32 v16, v6, v10
	v_dual_add_f32 v18, v8, v13 :: v_dual_sub_f32 v19, v13, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v6, v16, v6 :: v_dual_sub_f32 v17, v22, v17
	v_sub_f32_e32 v8, v18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v14, v19
	v_dual_sub_f32 v6, v10, v6 :: v_dual_add_f32 v3, v3, v17
	v_fma_f32 v10, 0x3f317218, v7, -v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v13, v8
	v_add_f32_e32 v5, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v3, v3, v6 :: v_dual_fmac_f32 v10, 0xb102e308, v7
	v_add_f32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v7, v16, v3 :: v_dual_add_f32 v8, v15, v10
	v_add_f32_e32 v9, v18, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v15, v8, v15 :: v_dual_sub_f32 v18, v9, v18
	v_add_f32_e32 v6, v11, v12
	v_add_f32_e32 v14, v8, v9
	v_sub_f32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v6, v7
	v_sub_f32_e32 v11, v6, v11
	v_sub_f32_e32 v17, v13, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v12, v11 :: v_dual_sub_f32 v12, v7, v16
	v_dual_sub_f32 v16, v14, v8 :: v_dual_sub_f32 v15, v13, v17
	v_sub_f32_e32 v7, v7, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v12
	v_sub_f32_e32 v12, v14, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v16 :: v_dual_sub_f32 v6, v6, v15
	v_sub_f32_e32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v11, v3
	v_add_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, v9, v8 :: v_dual_sub_f32 v9, v12, v11
	v_add_f32_e32 v6, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v12, v9
	v_dual_add_f32 v16, v13, v6 :: v_dual_sub_f32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v12 :: v_dual_sub_f32 v12, v16, v13
	v_sub_f32_e32 v5, v5, v18
	v_dual_add_f32 v3, v3, v11 :: v_dual_sub_f32 v6, v6, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v10, v5
	v_add_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v7, v10
	v_add_f32_e32 v8, v7, v8
	v_add_f32_e32 v6, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v7, v15
	v_add_f32_e32 v9, v14, v8
	v_sub_f32_e32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v11, 0, v6
	v_dual_sub_f32 v7, v10, v7 :: v_dual_sub_f32 v10, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v7
	v_dual_sub_f32 v7, v8, v10 :: v_dual_sub_f32 v8, v6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v6, v6 :: v_dual_add_f32 v5, v5, v7
	v_sub_f32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v6, v6, 2.0, -v10
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_add_f32_e32 v7, v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, 2.0, v3
	v_sub_f32_e32 v9, v7, v9
	v_add_f32_e32 v8, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v12, 0, v7 :: v_dual_sub_f32 v5, v5, v9
	v_fma_f32 v3, v7, 2.0, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, 2.0, v5 :: v_dual_add_f32 v5, v6, v11
	v_dual_add_f32 v3, v3, v12 :: v_dual_add_f32 v6, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v8, v3
	v_cndmask_b32_e32 v9, v6, v10, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v6, v6, v10 :: v_dual_cndmask_b32 v11, v7, v8
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v6
	v_sub_f32_e32 v7, v7, v8
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
	v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v14, v9, v12
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v16, 0x3fb8aa3b, v14 :: v_dual_sub_f32 v15, v11, v13
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11|
	v_fma_f32 v18, 0x3fb8aa3b, v14, -v16
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v17, 0x3fb8aa3b, v15
	v_rndne_f32_e32 v21, v16
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	v_fmac_f32_e32 v18, 0x32a5705f, v14
	v_fma_f32 v19, 0x3fb8aa3b, v15, -v17
	v_rndne_f32_e32 v20, v17
	v_sub_f32_e32 v16, v16, v21
	v_cvt_i32_f32_e32 v9, v21
	v_add_f32_e32 v3, v13, v3
	v_fmac_f32_e32 v19, 0x32a5705f, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v17, v20 :: v_dual_add_f32 v16, v16, v18
	v_cvt_i32_f32_e32 v8, v20
	v_dual_add_f32 v5, v12, v5 :: v_dual_add_f32 v10, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v6, v10
	v_exp_f32_e32 v10, v16
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v6, v8
	v_ldexp_f32 v7, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_fma_f32 v3, v6, v3, v6
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v5, v7, v5, v7
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, 0x7f800000, |v3|, s0
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
	v_cndmask_b32_e32 v0, 0, v3, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_mov_b64 s[0:1], 0
	v_cndmask_b32_e32 v2, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v2, v0
.LBB0_19:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b64 s[0:1], s[0:1], 2
	s_mov_b32 s12, -1
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
                                        ; implicit-def: $vgpr5
	global_load_b64 v[2:3], v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, -1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, 0x3e800000, v3, 1.0
	v_mul_f32_e32 v3, 0x40490e56, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v3
	v_cmp_ngt_f32_e64 s1, 0x48000000, |v3|
	s_bitset0_b32 s0, 31
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s1
                                        ; implicit-def: $sgpr1
	s_cbranch_vccz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_19 Depth=2
	s_and_b32 s1, s0, 0x7fffff
	s_lshr_b32 s12, s0, 23
	s_bitset1_b32 s1, 23
	s_addk_i32 s12, 0xff88
	s_mul_hi_u32 s13, s1, 0xfe5163ab
	s_mul_i32 s14, s1, 0x3c439041
	s_mul_hi_u32 s15, s1, 0x3c439041
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s15
	s_mul_i32 s15, s1, 0xdb629599
	s_mul_hi_u32 s16, s1, 0xdb629599
	s_add_u32 s14, s14, s15
	s_addc_u32 s15, 0, s16
	s_mul_i32 s16, s1, 0xf534ddc0
	s_mul_hi_u32 s17, s1, 0xf534ddc0
	s_add_u32 s15, s15, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s1, 0xfc2757d1
	s_mul_hi_u32 s18, s1, 0xfc2757d1
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s1, 0x4e441529
	s_mul_hi_u32 s19, s1, 0x4e441529
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_cmp_gt_u32 s12, 63
	s_mul_i32 s19, s1, 0xfe5163ab
	s_mul_hi_u32 s20, s1, 0xa2f9836e
	s_mul_i32 s1, s1, 0xa2f9836e
	s_cselect_b32 s21, s14, s16
	s_cselect_b32 s13, s13, s15
	s_cselect_b32 s14, s19, s14
	s_add_u32 s1, s18, s1
	s_addc_u32 s18, 0, s20
	s_cmp_gt_u32 s12, 63
	s_cselect_b32 s19, 0xffffffc0, 0
	s_cselect_b32 s15, s15, s17
	s_cselect_b32 s1, s16, s1
	s_cselect_b32 s16, s17, s18
	s_add_i32 s19, s19, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s19, 31
	s_cselect_b32 s12, 0xffffffe0, 0
	s_cselect_b32 s17, s15, s1
	s_cselect_b32 s1, s1, s16
	s_cselect_b32 s15, s21, s15
	s_cselect_b32 s16, s13, s21
	s_cselect_b32 s13, s14, s13
	s_add_i32 s12, s12, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s12, 31
	s_cselect_b32 s14, 0xffffffe0, 0
	s_cselect_b32 s1, s17, s1
	s_cselect_b32 s17, s15, s17
	s_cselect_b32 s15, s16, s15
	s_cselect_b32 s13, s13, s16
	s_add_i32 s14, s14, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s12, 32, s14
	s_cmp_eq_u32 s14, 0
	v_mov_b32_e32 v5, s12
	s_cselect_b32 s14, -1, 0
	v_alignbit_b32 v6, s1, s17, v5
	v_alignbit_b32 v7, s17, s15, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s12, v6
	v_cndmask_b32_e64 v6, v7, s17, s14
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s1, s1, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v7, s1, v6, 30
	s_bfe_u32 s12, s1, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s16, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v7, s16, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v8, v7
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v10, 23, v8
	v_alignbit_b32 v5, s15, s13, v5
	v_sub_nc_u32_e32 v9, 31, v8
	v_cndmask_b32_e64 v5, v5, s15, s14
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v6, v6, v5, 30
	v_alignbit_b32 v5, v5, s13, 30
	s_lshr_b32 s13, s1, 29
	s_lshr_b32 s1, s1, 30
	s_lshl_b32 s13, s13, 31
	v_xor_b32_e32 v6, s16, v6
	v_xor_b32_e32 v5, s16, v5
	s_or_b32 s14, s13, 0.5
	s_add_i32 s1, s12, s1
	v_sub_nc_u32_e32 v10, s14, v10
	v_alignbit_b32 v7, v7, v6, v9
	v_alignbit_b32 v5, v6, v5, v9
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v7, v5, 9
	v_lshrrev_b32_e32 v7, 9, v7
	v_clz_i32_u32_e32 v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v9, 32, v9
	v_sub_nc_u32_e32 v11, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v11
	v_or_b32_e32 v6, v7, v10
	v_add_nc_u32_e32 v8, v9, v8
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v8, 0x3fc90fda, v6 :: v_dual_lshlrev_b32 v7, 23, v8
	v_sub_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3fc90fda, v6, -v8
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, 0x33a22168, v6
	v_or_b32_e32 v5, s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, 0x3fc90fda, v5
	v_add_f32_e32 v5, v8, v7
.LBB0_21:                               ; %Flow75
                                        ;   in Loop: Header=BB0_19 Depth=2
	v_mov_b32_e32 v6, s1
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_19 Depth=2
	v_mul_f32_e64 v5, 0x3f22f983, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v5
	v_fma_f32 v5, 0xbfc90fda, v6, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v6
	v_fmac_f32_e32 v5, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
.LBB0_23:                               ; %_ZL3sinf.exit22.i27
                                        ;   in Loop: Header=BB0_19 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v7, v5, v5 :: v_dual_lshlrev_b32 v10, 30, v6
	v_xor_b32_e32 v11, s0, v3
	s_xor_b32 s11, s11, -1
	v_and_b32_e32 v6, 1, v6
	v_fmaak_f32 v8, s8, v7, 0x3c0881c4
	v_add_f32_e32 v2, -1.0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
	v_fmaak_f32 v9, s9, v7, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v2, 0x3e800000, v2, 1.0
	v_mul_f32_e32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v9, v7, v9, 0x3d2aabf7
	v_and_b32_e32 v10, 0x80000000, v10
	v_dual_add_f32 v2, -1.0, v2 :: v_dual_fmac_f32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v9, v7, v9, 0xbf000004
	v_xor_b32_e32 v8, v11, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_exp_i32_f32_e32 v20, v2
	v_fma_f32 v7, v7, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
	v_xor_b32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0x7fc00000, v5, vcc_lo
	v_frexp_mant_f32_e64 v5, |v2|
	v_frexp_mant_f32_e64 v6, |v3|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v6
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, 1, s0
	v_ldexp_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v6, v6, v8
	v_add_f32_e32 v7, 1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v11, -1.0, v5 :: v_dual_add_f32 v8, 1.0, v6
	v_rcp_f32_e32 v9, v7
	v_add_f32_e32 v12, -1.0, v6
	v_frexp_exp_i32_f32_e32 v25, v3
	v_add_f32_e32 v15, -1.0, v7
	v_rcp_f32_e32 v10, v8
	v_add_f32_e32 v17, -1.0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v15
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v13, v11, v9 :: v_dual_mul_f32 v14, v12, v10
	v_mul_f32_e32 v16, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v8, v14
	v_fma_f32 v7, v13, v7, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v14, v8, -v18
	v_fmac_f32_e32 v7, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v6, v17 :: v_dual_add_f32 v5, v16, v7
	v_dual_fmac_f32 v8, v14, v6 :: v_dual_sub_f32 v15, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v18, v8
	v_dual_sub_f32 v16, v5, v16 :: v_dual_sub_f32 v11, v11, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v6, v18
	v_sub_f32_e32 v17, v12, v6
	v_sub_f32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v11, v5 :: v_dual_sub_f32 v8, v18, v8
	v_add_f32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v15, v5
	v_mul_f32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v13, v5
	v_dual_sub_f32 v12, v12, v17 :: v_dual_mul_f32 v11, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v12, v6
	v_add_f32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v17, v6
	v_mul_f32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v14, v6 :: v_dual_sub_f32 v9, v7, v13
	v_dual_sub_f32 v10, v8, v14 :: v_dual_sub_f32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v6, v6, v10 :: v_dual_mul_f32 v9, v8, v8
	v_add_f32_e32 v12, v5, v5
	v_fma_f32 v10, v7, v7, -v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v8, v8, -v9
	v_fmac_f32_e32 v10, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v11, v10
	v_dual_add_f32 v14, v6, v6 :: v_dual_fmaak_f32 v15, s10, v12, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v8, v14
	v_add_f32_e32 v14, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v9, v14, v9
	v_fmaak_f32 v15, v12, v15, 0x3ecccdef
	v_dual_fmaak_f32 v16, s10, v14, 0x3e91f4c4 :: v_dual_sub_f32 v11, v12, v11
	v_mul_f32_e32 v19, v7, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v13, v9
	v_dual_mul_f32 v17, v12, v15 :: v_dual_fmaak_f32 v16, v14, v16, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v10, v11
	v_fma_f32 v11, v12, v15, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v14, v16
	v_fmac_f32_e32 v11, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v14, v16, -v18
	v_fma_f32 v15, v12, v7, -v19
	v_fmac_f32_e32 v13, v9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v15, v12, v5
	v_mul_f32_e32 v12, v8, v14
	v_add_f32_e32 v16, v17, v11
	v_ldexp_f32 v5, v5, 1
	v_add_f32_e32 v21, v18, v13
	v_fma_f32 v24, v14, v8, -v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v17, v16, v17 :: v_dual_add_f32 v22, 0x3f2aaaaa, v16
	v_dual_sub_f32 v18, v21, v18 :: v_dual_add_f32 v23, 0x3f2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, v14, v6
	v_ldexp_f32 v6, v6, 1
	v_dual_sub_f32 v13, v13, v18 :: v_dual_add_f32 v18, 0xbf2aaaaa, v23
	v_sub_f32_e32 v11, v11, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v17, 0xbf2aaaaa, v22 :: v_dual_fmac_f32 v24, v9, v8
	v_ldexp_f32 v8, v8, 1
	v_sub_f32_e32 v14, v16, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v21, v18 :: v_dual_add_f32 v11, 0x31739010, v11
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v20, vcc_lo
	v_add_f32_e32 v13, 0x31739010, v13
	v_cvt_f32_i32_e32 v9, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v15, v10, v7 :: v_dual_add_f32 v10, v11, v14
	v_add_f32_e32 v17, v12, v24
	v_ldexp_f32 v7, v7, 1
	v_mul_f32_e32 v18, 0x3f317218, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v22, v10 :: v_dual_add_f32 v11, v13, v16
	v_sub_f32_e32 v20, v22, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v16, v23, v11
	v_dual_add_f32 v13, v19, v15 :: v_dual_add_f32 v10, v10, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, v17, v16
	v_sub_f32_e32 v19, v13, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v20, v17, v16, -v22
	v_sub_f32_e32 v21, v23, v16
	v_dual_sub_f32 v12, v17, v12 :: v_dual_add_f32 v11, v11, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v23, v13, v14 :: v_dual_sub_f32 v12, v24, v12
	v_fmac_f32_e32 v20, v17, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v21, v13, v14, -v23
	v_sub_f32_e32 v15, v15, v19
	v_fma_f32 v11, 0x3f317218, v9, -v18
	v_dual_fmac_f32 v20, v12, v16 :: v_dual_fmac_f32 v21, v13, v10
	v_subrev_co_ci_u32_e64 v10, vcc_lo, 0, v25, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v11, 0xb102e308, v9 :: v_dual_add_f32 v12, v22, v20
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	v_cvt_f32_i32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v12, v22
	v_fmac_f32_e32 v21, v15, v14
	v_mul_f32_e32 v14, 0x3f317218, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v20, v16 :: v_dual_add_f32 v13, v23, v21
	v_fma_f32 v20, 0x3f317218, v10, -v14
	v_add_f32_e32 v15, v8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v6, v6, v16 :: v_dual_add_f32 v17, v7, v13
	v_dual_fmac_f32 v20, 0xb102e308, v10 :: v_dual_sub_f32 v19, v13, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v15, v8 :: v_dual_sub_f32 v7, v17, v7
	v_dual_sub_f32 v19, v21, v19 :: v_dual_sub_f32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v13, v7
	v_dual_add_f32 v5, v5, v19 :: v_dual_add_f32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, v14, v20 :: v_dual_add_f32 v5, v5, v7
	v_add_f32_e32 v7, v18, v11
	v_dual_add_f32 v9, v15, v6 :: v_dual_add_f32 v10, v17, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v12, v7, v18 :: v_dual_add_f32 v13, v8, v9
	v_add_f32_e32 v16, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v11, v11, v12 :: v_dual_sub_f32 v12, v8, v14
	v_dual_sub_f32 v14, v13, v8 :: v_dual_sub_f32 v17, v10, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v16, v7
	v_dual_sub_f32 v15, v9, v15 :: v_dual_sub_f32 v12, v20, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v5, v5, v17 :: v_dual_sub_f32 v6, v6, v15
	v_sub_f32_e32 v19, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v12, v6
	v_dual_sub_f32 v9, v9, v14 :: v_dual_add_f32 v14, v11, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v19
	v_dual_sub_f32 v17, v16, v18 :: v_dual_add_f32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v10, v10, v18 :: v_dual_sub_f32 v7, v7, v17
	v_sub_f32_e32 v9, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v10, v7
	v_add_f32_e32 v7, v14, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v14, v9
	v_sub_f32_e32 v10, v15, v12
	v_add_f32_e32 v8, v15, v8
	v_sub_f32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v15, v10
	v_dual_add_f32 v17, v13, v8 :: v_dual_sub_f32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v12, v15
	v_sub_f32_e32 v12, v17, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v5, v9 :: v_dual_add_f32 v6, v6, v10
	v_sub_f32_e32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v16, v7 :: v_dual_add_f32 v6, v6, v8
	v_sub_f32_e32 v13, v9, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v11
	v_sub_f32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v7
	v_add_f32_e32 v7, v17, v6
	v_sub_f32_e32 v10, v7, v17
	v_mul_f32_e32 v12, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v10
	v_fmac_f32_e32 v12, 2.0, v6
	v_add_f32_e32 v8, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v8, v8
	v_sub_f32_e32 v9, v8, v9
	v_mul_f32_e32 v13, 0, v8
	v_fma_f32 v6, v8, 2.0, -v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v9
	v_fmac_f32_e32 v13, 2.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v6, v13 :: v_dual_add_f32 v11, v7, v7
	v_add_f32_e32 v8, v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v7, 2.0, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	v_add_f32_e32 v5, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v11, v5
	v_cndmask_b32_e32 v9, v7, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_cndmask_b32_e32 v12, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
	v_dual_sub_f32 v8, v8, v10 :: v_dual_sub_f32 v7, v7, v11
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_sub_f32_e32 v6, v6, v8
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v12, v14
	v_mul_f32_e32 v18, 0x3fb8aa3b, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v21, 0x3fb8aa3b, v16, -v18
	v_rndne_f32_e32 v22, v18
	v_dual_fmac_f32 v21, 0x32a5705f, v16 :: v_dual_sub_f32 v18, v18, v22
	v_sub_f32_e32 v5, v5, v7
	v_cvt_i32_f32_e32 v8, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v18, v21
	v_sub_f32_e32 v15, v9, v13
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
	v_exp_f32_e32 v10, v18
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
	v_mul_f32_e32 v17, 0x3fb8aa3b, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v5, v13, v5 :: v_dual_cndmask_b32 v6, 0, v6
	v_fma_f32 v19, 0x3fb8aa3b, v15, -v17
	v_rndne_f32_e32 v20, v17
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f32 v8, v10, v8
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	v_dual_add_f32 v6, v14, v6 :: v_dual_fmac_f32 v19, 0x32a5705f, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v17, v20
	v_cvt_i32_f32_e32 v7, v20
	v_add_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v11, v17
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v11, v7
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	v_fma_f32 v5, v7, v5, v7
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v6, v8, v6, v8
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v5, 0x41200000, |v5|, 1.0
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v3|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, 0x7f800000, |v6|, s0
	v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_mov_b64 s[0:1], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 1.0, v5, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_mov_b32 s11, 0
	v_fmac_f32_e32 v0, v2, v3
	s_cbranch_vccnz .LBB0_19
; %bb.24:                               ; %_Z16fitness_functionPf.exit35
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 v4, v0
	s_cbranch_execz .LBB0_27
; %bb.25:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v0, 4
	s_mov_b64 s[0:1], 0
.LBB0_26:                               ; %.preheader
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v2, v0, off
	s_add_u32 s12, s4, s0
	v_add_nc_u32_e32 v0, 4, v0
	s_addc_u32 s13, s5, s1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 12
	s_waitcnt vmcnt(0)
	global_store_b32 v1, v2, s[12:13]
	s_cbranch_scc1 .LBB0_26
.LBB0_27:                               ; %Flow74
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_add_i32 s0, s3, 3
	s_add_u32 s6, s6, 12
	s_addc_u32 s7, s7, 0
	s_cmp_gt_u32 s3, 26
	s_mov_b32 s3, s0
	s_cbranch_scc0 .LBB0_1
; %bb.28:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17kernelUpdateGBestPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 16
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17kernelUpdateGBestPfS_, .Lfunc_end0-_Z17kernelUpdateGBestPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11272
; NumSgprs: 24
; NumVgprs: 26
; ScratchSize: 16
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17kernelUpdateGBestPfS_
    .private_segment_fixed_size: 16
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z17kernelUpdateGBestPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
