#include <stdio.h>
#include <iostream>
#include <iomanip>
#include <string>
#include <stdlib.h>
#include <math.h>
#include <vector>

using namespace std;

#define N_IN 4
#define N_REC 8
#define N_WINDOW 20
#define TIMESTEPS 20

#define THRESHOLD 0.3
#define VOLT_TAU 20.0
#define VOLT_COEFF exp(-1.0/VOLT_TAU)
#define REF_PERIOD 2

#define W_IN_SIZE N_IN*N_REC
#define W_REC_SIZE N_REC*N_REC
#define NET_STATE_SIZE N_WINDOW*N_REC

float uniform(float low, float high) {
    return low + (static_cast<float>(rand())/RAND_MAX)*(high - low);
}

__global__ void network_step(float voltages[NET_STATE_SIZE],
                             float spike_trains[NET_STATE_SIZE],
                             int refractory_periods[NET_STATE_SIZE],
                             float in_currents[N_WINDOW*N_IN],
                             float weight_in[W_IN_SIZE],
                             float weight_rec[W_REC_SIZE],
                             int t) {

    int pre = blockIdx.x*blockDim.x + threadIdx.x;
    int post = blockIdx.y*blockDim.y + threadIdx.y;

    int last_t = (t - 1)%N_WINDOW;

    //compute recurrent synapses
    __shared__ float rec_synapses[W_REC_SIZE];
    if(pre < N_REC && post < N_REC) {
        float last_spike = spike_trains[N_REC*last_t + pre];
        rec_synapses[N_REC*pre + post] = last_spike*weight_rec[N_REC*pre + post];
    }
    __syncthreads();

    //compute input synapses
    __shared__ float in_synapses[W_IN_SIZE];
    if(pre < N_IN && post < N_REC) {
        int tn = t%N_WINDOW;
        float current_current = in_currents[N_IN*tn + pre];
        in_synapses[N_REC*pre + post] = current_current*weight_in[N_REC*pre + post];
    }
    __syncthreads();

    //printf("%d  %d  %f\n", row, col, elmntwise_mul[N_REC*row + col]);

    //compute new voltages and spikes
    if(pre == 0 && post < N_REC) {

        int tm = t % N_WINDOW;
        int index = N_REC*tm + post;
        int last_index = N_REC*last_t + post;

        //if a spike occurred in the last step, or we are in the refractory period, clamp the voltage and spike trains to 0
        if(spike_trains[last_index] > 0.5 || refractory_periods[last_index] > 0) {
            voltages[index] = 0.0;
            spike_trains[index] = 0.0;
            refractory_periods[index] = (1 + refractory_periods[N_REC*last_t + post])%REF_PERIOD;
        }

        //otherwise sum the synaptic potentials and possibly generate a spike
        else {

            voltages[index] = VOLT_COEFF*voltages[N_REC*last_t + post];

            for(size_t pre_ = 0; pre_ < N_REC; ++pre_) {
                voltages[index] += rec_synapses[N_REC*pre_ + post];
            }

            for(size_t pre_ = 0; pre_ < N_IN; ++pre_) {
                voltages[index] += in_synapses[N_REC*pre_ + post];
            }

            spike_trains[index] = voltages[index] > THRESHOLD ? 1.0 : 0.0;
        }
    }
}

__global__ void stepLIF(float* voltages,
                        float* spike_trains,
                        int* refractory_buffer,
                        float* in_currents,
                        float* weights_in,
                        float* weights_rec,
                        int t) {

    int post = blockIdx.x*blockDim.x + threadIdx.x;

    //compute new voltages and spikes
    if(post < N_REC) {

        int last_t = (t - 1)%N_WINDOW;
        int tm = t%N_WINDOW;
        int index = N_REC*tm + post;
        int last_index = N_REC*last_t + post;

        //if a spike occurred in the last step, or we are in the refractory period, clamp the voltage and spike trains to 0
        if(spike_trains[last_index] > 0.5 || refractory_buffer[last_index] > 0) {
            voltages[index] = 0.0;
            spike_trains[index] = 0.0;
            refractory_buffer[index] = (1 + refractory_buffer[last_index])%REF_PERIOD;
        }

        //otherwise sum the synaptic potentials and possibly generate a spike
        else {

            voltages[index] = VOLT_COEFF*voltages[last_index];

            //recurrent
            for(size_t pre_ = 0; pre_ < N_REC; ++pre_) {
                voltages[index] += weights_rec[N_REC*pre_ + post]*spike_trains[N_REC*last_t + pre_]; 
            }

            //input
            for(size_t pre_ = 0; pre_ < N_IN; ++pre_) {
                voltages[index] += weights_in[N_REC*pre_ + post]*in_currents[N_IN*last_t + pre_];
            }

            spike_trains[index] = voltages[index] > THRESHOLD ? 1.0 : 0.0;
        }
    }
}

int main() {

    float w_rec[W_REC_SIZE];
    for(size_t i = 0; i < N_REC; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            w_rec[N_REC*i + j] = uniform(-1.0, 1.0);
        }
    //printf("\n");
    }
    
    float w_in[W_IN_SIZE];
    for(size_t i = 0; i < N_IN; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            w_in[N_REC*i + j] = uniform(0.0, 1.0);
        }
    //printf("\n");
    }

    float volts[NET_STATE_SIZE];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            volts[N_REC*i + j] = uniform(-1.0, 1.0);
        }
    }

    float spikes[NET_STATE_SIZE];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            spikes[N_REC*i + j] = 0.0;
        }
    }

    float in_currents[N_WINDOW*N_IN];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            in_currents[N_REC*i + j] = uniform(0.0, 0.3);
        }
    }

    int ref_periods[NET_STATE_SIZE];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            ref_periods[N_REC*i + j] = 0;
        }
    }

    //printf("\n");
    float* w_in_gpu;
    float* w_rec_gpu;
    float* volts_gpu;
    float* spikes_gpu;
    int* ref_periods_gpu;
    float* in_currents_gpu; //pre-determined current so that we don't have to genereate it every time step

    cudaMalloc(&w_in_gpu, W_IN_SIZE*sizeof(float));
    cudaMalloc(&w_rec_gpu, W_REC_SIZE*sizeof(float));
    cudaMalloc(&volts_gpu, NET_STATE_SIZE*sizeof(float));
    cudaMalloc(&spikes_gpu, NET_STATE_SIZE*sizeof(float));
    cudaMalloc(&ref_periods_gpu, NET_STATE_SIZE*sizeof(int));
    cudaMalloc(&in_currents_gpu, N_IN*N_WINDOW*sizeof(float));

    cudaMemcpy(w_in_gpu, w_in, W_IN_SIZE*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(w_rec_gpu, w_rec, W_REC_SIZE*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(volts_gpu, volts, NET_STATE_SIZE*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(spikes_gpu, spikes, NET_STATE_SIZE*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(ref_periods_gpu, ref_periods, NET_STATE_SIZE*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(in_currents_gpu, in_currents, N_WINDOW*N_IN*sizeof(float), cudaMemcpyHostToDevice);

    for(int time = 1; time < TIMESTEPS; ++time) {

        
        if(time%N_WINDOW == 0) {
            for(size_t i = 0; i < N_WINDOW; ++i) {
                for(size_t j = 0; j < N_REC; ++j) {
                    in_currents[N_REC*i + j] = 0.0;//uniform(0.0, 1.0);
                }
            }
            cudaMemcpy(in_currents_gpu, in_currents, N_WINDOW*N_IN*sizeof(float), cudaMemcpyHostToDevice);
        }
        

        stepLIF<<<4, N_REC/3>>>(volts_gpu, spikes_gpu, ref_periods_gpu, in_currents_gpu, w_in_gpu, w_rec_gpu, time);
    }

    cudaMemcpy(w_in, w_in_gpu, W_IN_SIZE*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(w_rec, w_rec_gpu, W_REC_SIZE*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(volts, volts_gpu, NET_STATE_SIZE*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(spikes, spikes_gpu, NET_STATE_SIZE*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(ref_periods, ref_periods_gpu, NET_STATE_SIZE*sizeof(float), cudaMemcpyDeviceToHost);

    cudaFree(w_in_gpu);
    cudaFree(w_rec_gpu);
    cudaFree(volts_gpu);
    cudaFree(spikes_gpu);
    cudaFree(ref_periods_gpu);
    cudaFree(in_currents_gpu);

    for(size_t i = 0; i < N_WINDOW; ++i) {
        //printf("%2d", i);
        cout << setw(5) << i;
        for(size_t j = 0; j < N_REC; ++j) {
            //printf("  ");
            //printf("%4.2f", volts[N_REC*i + j]);
            cout << "  ";
            cout << fixed << setprecision(2) << setw(5) << volts[N_REC*i + j];
        }
        //printf("    ");
        cout << "    ";
        for(size_t j = 0; j < N_REC; ++j) {
            //printf("  ");
            //printf("%4.2f", spikes[N_REC*i + j]);
            cout << "  ";
            cout << fixed << setprecision(2) << setw(5) << spikes[N_REC*i + j];
        }
        cout << endl;
    }

    return 0;

}

	.file	"tmpxft_00229b06_00000000-6_test.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.section	.text._ZSt5fixedRSt8ios_base,"axG",@progbits,_ZSt5fixedRSt8ios_base,comdat
	.weak	_ZSt5fixedRSt8ios_base
	.type	_ZSt5fixedRSt8ios_base, @function
_ZSt5fixedRSt8ios_base:
.LFB3285:
	.cfi_startproc
	endbr64
	movl	24(%rdi), %edx
	movq	%rdi, %rax
	andl	$-261, %edx
	orl	$4, %edx
	movl	%edx, 24(%rdi)
	ret
	.cfi_endproc
.LFE3285:
	.size	_ZSt5fixedRSt8ios_base, .-_ZSt5fixedRSt8ios_base
	.text
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4282:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4282:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7uniformff
	.type	_Z7uniformff, @function
_Z7uniformff:
.LFB4278:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	call	rand@PLT
	movss	12(%rsp), %xmm2
	movss	8(%rsp), %xmm1
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	subss	%xmm2, %xmm1
	mulss	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	ret
	.cfi_endproc
.LFE4278:
	.size	_Z7uniformff, .-_Z7uniformff
	.globl	_Z43__device_stub__Z12network_stepPfS_PiS_S_S_iPfS_PiS_S_S_i
	.type	_Z43__device_stub__Z12network_stepPfS_PiS_S_S_iPfS_PiS_S_S_i, @function
_Z43__device_stub__Z12network_stepPfS_PiS_S_S_iPfS_PiS_S_S_i:
.LFB4304:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L5
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12network_stepPfS_PiS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L5:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L7
	call	__stack_chk_fail@PLT
.L7:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4304:
	.size	_Z43__device_stub__Z12network_stepPfS_PiS_S_S_iPfS_PiS_S_S_i, .-_Z43__device_stub__Z12network_stepPfS_PiS_S_S_iPfS_PiS_S_S_i
	.globl	_Z12network_stepPfS_PiS_S_S_i
	.type	_Z12network_stepPfS_PiS_S_S_i, @function
_Z12network_stepPfS_PiS_S_S_i:
.LFB4305:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z12network_stepPfS_PiS_S_S_iPfS_PiS_S_S_i
	.cfi_endproc
.LFE4305:
	.size	_Z12network_stepPfS_PiS_S_S_i, .-_Z12network_stepPfS_PiS_S_S_i
	.globl	_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i
	.type	_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i, @function
_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i:
.LFB4306:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7stepLIFPfS_PiS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L11:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4306:
	.size	_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i, .-_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i
	.globl	_Z7stepLIFPfS_PiS_S_S_i
	.type	_Z7stepLIFPfS_PiS_S_S_i, @function
_Z7stepLIFPfS_PiS_S_S_i:
.LFB4307:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i
	.cfi_endproc
.LFE4307:
	.size	_Z7stepLIFPfS_PiS_S_S_i, .-_Z7stepLIFPfS_PiS_S_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC5:
	.string	"  "
.LC6:
	.string	"    "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4279:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$2728, %rsp
	.cfi_def_cfa_offset 2784
	movq	%fs:40, %rax
	movq	%rax, 2712(%rsp)
	xorl	%eax, %eax
	leaq	216(%rsp), %rbp
	movq	%rbp, (%rsp)
.L17:
	xorl	%ebx, %ebx
.L18:
	movss	.LC1(%rip), %xmm1
	movss	.LC2(%rip), %xmm0
	call	_Z7uniformff
	movss	%xmm0, 0(%rbp,%rbx,4)
	incq	%rbx
	cmpq	$8, %rbx
	jne	.L18
	addq	$8, %r12
	addq	$32, %rbp
	cmpq	$64, %r12
	jne	.L17
	leaq	88(%rsp), %rbp
	xorl	%r12d, %r12d
	movq	%rbp, %r14
.L19:
	xorl	%ebx, %ebx
.L20:
	movss	.LC1(%rip), %xmm1
	xorps	%xmm0, %xmm0
	call	_Z7uniformff
	movss	%xmm0, 0(%rbp,%rbx,4)
	incq	%rbx
	cmpq	$8, %rbx
	jne	.L20
	addq	$8, %r12
	addq	$32, %rbp
	cmpq	$32, %r12
	jne	.L19
	leaq	792(%rsp), %rbp
	xorl	%r12d, %r12d
	movq	%rbp, %r15
.L23:
	xorl	%ebx, %ebx
.L22:
	movss	.LC1(%rip), %xmm1
	movss	.LC2(%rip), %xmm0
	call	_Z7uniformff
	movss	%xmm0, (%r15,%rbx,4)
	incq	%rbx
	cmpq	$8, %rbx
	jne	.L22
	addq	$8, %r12
	addq	$32, %r15
	cmpq	$160, %r12
	jne	.L23
	leaq	1432(%rsp), %rbx
	xorl	%eax, %eax
	movq	%r12, %rcx
	xorl	%r15d, %r15d
	movq	%rbx, %rdi
	leaq	472(%rsp), %r13
	rep stosl
	movq	%r13, 8(%rsp)
.L24:
	xorl	%r12d, %r12d
.L25:
	movss	.LC4(%rip), %xmm1
	xorps	%xmm0, %xmm0
	call	_Z7uniformff
	movss	%xmm0, 0(%r13,%r12,4)
	incq	%r12
	cmpq	$8, %r12
	jne	.L25
	addq	$8, %r15
	addq	$32, %r13
	cmpq	$160, %r15
	jne	.L24
	leaq	2072(%rsp), %rax
	movq	%r15, %rcx
	movl	$128, %esi
	movl	$1, %r12d
	movabsq	$4294967298, %r15
	movq	%rax, %r13
	xorl	%eax, %eax
	movq	%r13, %rdi
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$640, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$640, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$640, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$320, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$128, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$640, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$640, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$640, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movl	$320, %edx
	call	cudaMemcpy@PLT
.L26:
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r15, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	%rax
	.cfi_def_cfa_offset 2792
	pushq	%r12
	.cfi_def_cfa_offset 2800
	movq	40(%rsp), %r9
	movq	32(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z37__device_stub__Z7stepLIFPfS_PiS_S_S_iPfS_PiS_S_S_i
	popq	%rdx
	.cfi_def_cfa_offset 2792
	popq	%rcx
	.cfi_def_cfa_offset 2784
.L27:
	incl	%r12d
	cmpl	$20, %r12d
	jne	.L26
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$128, %edx
	movq	%r14, %rdi
	leaq	_ZSt4cout(%rip), %r12
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$640, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$640, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	movl	$640, %edx
	xorl	%r13d, %r13d
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
.L30:
	movq	(%r12), %rax
	movq	%r13, %r15
	movq	%r13, %rsi
	movq	%r12, %rdi
	salq	$5, %r15
	xorl	%r14d, %r14d
	movq	-24(%rax), %rax
	addq	%rbp, %r15
	movq	$5, 16(%r12,%rax)
	call	_ZNSo9_M_insertImEERSoT_@PLT
.L28:
	movl	$2, %edx
	leaq	.LC5(%rip), %rsi
	movq	%r12, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	leaq	_ZSt5fixedRSt8ios_base(%rip), %rsi
	movq	%r12, %rdi
	call	_ZNSolsEPFRSt8ios_baseS0_E@PLT
	cvtss2sd	(%r15,%r14,4), %xmm0
	incq	%r14
	movq	%rax, %rdi
	movq	(%rax), %rax
	movq	-24(%rax), %rdx
	movq	$2, 8(%rdi,%rdx)
	movq	-24(%rax), %rax
	movq	$5, 16(%rdi,%rax)
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	cmpq	$8, %r14
	jne	.L28
	movl	$4, %edx
	leaq	.LC6(%rip), %rsi
	movq	%r12, %rdi
	xorl	%r14d, %r14d
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L29:
	movl	$2, %edx
	leaq	.LC5(%rip), %rsi
	movq	%r12, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	leaq	_ZSt5fixedRSt8ios_base(%rip), %rsi
	movq	%r12, %rdi
	call	_ZNSolsEPFRSt8ios_baseS0_E@PLT
	cvtss2sd	(%rbx,%r14,4), %xmm0
	incq	%r14
	movq	%rax, %rdi
	movq	(%rax), %rax
	movq	-24(%rax), %rdx
	movq	$2, 8(%rdi,%rdx)
	movq	-24(%rax), %rax
	movq	$5, 16(%rdi,%rax)
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	cmpq	$8, %r14
	jne	.L29
	movq	%r12, %rdi
	incq	%r13
	addq	$32, %rbx
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$20, %r13
	jne	.L30
	movq	2712(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$2728, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4279:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z7stepLIFPfS_PiS_S_S_i"
.LC8:
	.string	"_Z12network_stepPfS_PiS_S_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4309:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7stepLIFPfS_PiS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12network_stepPfS_PiS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4309:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	-1082130432
	.align 4
.LC4:
	.long	1050253722
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <iomanip>
#include <string>
#include <stdlib.h>
#include <math.h>
#include <vector>

using namespace std;

#define N_IN 4
#define N_REC 8
#define N_WINDOW 20
#define TIMESTEPS 20

#define THRESHOLD 0.3
#define VOLT_TAU 20.0
#define VOLT_COEFF exp(-1.0/VOLT_TAU)
#define REF_PERIOD 2

#define W_IN_SIZE N_IN*N_REC
#define W_REC_SIZE N_REC*N_REC
#define NET_STATE_SIZE N_WINDOW*N_REC

float uniform(float low, float high) {
    return low + (static_cast<float>(rand())/RAND_MAX)*(high - low);
}

__global__ void network_step(float voltages[NET_STATE_SIZE],
                             float spike_trains[NET_STATE_SIZE],
                             int refractory_periods[NET_STATE_SIZE],
                             float in_currents[N_WINDOW*N_IN],
                             float weight_in[W_IN_SIZE],
                             float weight_rec[W_REC_SIZE],
                             int t) {

    int pre = blockIdx.x*blockDim.x + threadIdx.x;
    int post = blockIdx.y*blockDim.y + threadIdx.y;

    int last_t = (t - 1)%N_WINDOW;

    //compute recurrent synapses
    __shared__ float rec_synapses[W_REC_SIZE];
    if(pre < N_REC && post < N_REC) {
        float last_spike = spike_trains[N_REC*last_t + pre];
        rec_synapses[N_REC*pre + post] = last_spike*weight_rec[N_REC*pre + post];
    }
    __syncthreads();

    //compute input synapses
    __shared__ float in_synapses[W_IN_SIZE];
    if(pre < N_IN && post < N_REC) {
        int tn = t%N_WINDOW;
        float current_current = in_currents[N_IN*tn + pre];
        in_synapses[N_REC*pre + post] = current_current*weight_in[N_REC*pre + post];
    }
    __syncthreads();

    //printf("%d  %d  %f\n", row, col, elmntwise_mul[N_REC*row + col]);

    //compute new voltages and spikes
    if(pre == 0 && post < N_REC) {

        int tm = t % N_WINDOW;
        int index = N_REC*tm + post;
        int last_index = N_REC*last_t + post;

        //if a spike occurred in the last step, or we are in the refractory period, clamp the voltage and spike trains to 0
        if(spike_trains[last_index] > 0.5 || refractory_periods[last_index] > 0) {
            voltages[index] = 0.0;
            spike_trains[index] = 0.0;
            refractory_periods[index] = (1 + refractory_periods[N_REC*last_t + post])%REF_PERIOD;
        }

        //otherwise sum the synaptic potentials and possibly generate a spike
        else {

            voltages[index] = VOLT_COEFF*voltages[N_REC*last_t + post];

            for(size_t pre_ = 0; pre_ < N_REC; ++pre_) {
                voltages[index] += rec_synapses[N_REC*pre_ + post];
            }

            for(size_t pre_ = 0; pre_ < N_IN; ++pre_) {
                voltages[index] += in_synapses[N_REC*pre_ + post];
            }

            spike_trains[index] = voltages[index] > THRESHOLD ? 1.0 : 0.0;
        }
    }
}

__global__ void stepLIF(float* voltages,
                        float* spike_trains,
                        int* refractory_buffer,
                        float* in_currents,
                        float* weights_in,
                        float* weights_rec,
                        int t) {

    int post = blockIdx.x*blockDim.x + threadIdx.x;

    //compute new voltages and spikes
    if(post < N_REC) {

        int last_t = (t - 1)%N_WINDOW;
        int tm = t%N_WINDOW;
        int index = N_REC*tm + post;
        int last_index = N_REC*last_t + post;

        //if a spike occurred in the last step, or we are in the refractory period, clamp the voltage and spike trains to 0
        if(spike_trains[last_index] > 0.5 || refractory_buffer[last_index] > 0) {
            voltages[index] = 0.0;
            spike_trains[index] = 0.0;
            refractory_buffer[index] = (1 + refractory_buffer[last_index])%REF_PERIOD;
        }

        //otherwise sum the synaptic potentials and possibly generate a spike
        else {

            voltages[index] = VOLT_COEFF*voltages[last_index];

            //recurrent
            for(size_t pre_ = 0; pre_ < N_REC; ++pre_) {
                voltages[index] += weights_rec[N_REC*pre_ + post]*spike_trains[N_REC*last_t + pre_]; 
            }

            //input
            for(size_t pre_ = 0; pre_ < N_IN; ++pre_) {
                voltages[index] += weights_in[N_REC*pre_ + post]*in_currents[N_IN*last_t + pre_];
            }

            spike_trains[index] = voltages[index] > THRESHOLD ? 1.0 : 0.0;
        }
    }
}

int main() {

    float w_rec[W_REC_SIZE];
    for(size_t i = 0; i < N_REC; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            w_rec[N_REC*i + j] = uniform(-1.0, 1.0);
        }
    //printf("\n");
    }
    
    float w_in[W_IN_SIZE];
    for(size_t i = 0; i < N_IN; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            w_in[N_REC*i + j] = uniform(0.0, 1.0);
        }
    //printf("\n");
    }

    float volts[NET_STATE_SIZE];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            volts[N_REC*i + j] = uniform(-1.0, 1.0);
        }
    }

    float spikes[NET_STATE_SIZE];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            spikes[N_REC*i + j] = 0.0;
        }
    }

    float in_currents[N_WINDOW*N_IN];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            in_currents[N_REC*i + j] = uniform(0.0, 0.3);
        }
    }

    int ref_periods[NET_STATE_SIZE];
    for(size_t i = 0; i < N_WINDOW; ++i) {
        for(size_t j = 0; j < N_REC; ++j) {
            ref_periods[N_REC*i + j] = 0;
        }
    }

    //printf("\n");
    float* w_in_gpu;
    float* w_rec_gpu;
    float* volts_gpu;
    float* spikes_gpu;
    int* ref_periods_gpu;
    float* in_currents_gpu; //pre-determined current so that we don't have to genereate it every time step

    hipMalloc(&w_in_gpu, W_IN_SIZE*sizeof(float));
    hipMalloc(&w_rec_gpu, W_REC_SIZE*sizeof(float));
    hipMalloc(&volts_gpu, NET_STATE_SIZE*sizeof(float));
    hipMalloc(&spikes_gpu, NET_STATE_SIZE*sizeof(float));
    hipMalloc(&ref_periods_gpu, NET_STATE_SIZE*sizeof(int));
    hipMalloc(&in_currents_gpu, N_IN*N_WINDOW*sizeof(float));

    hipMemcpy(w_in_gpu, w_in, W_IN_SIZE*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(w_rec_gpu, w_rec, W_REC_SIZE*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(volts_gpu, volts, NET_STATE_SIZE*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(spikes_gpu, spikes, NET_STATE_SIZE*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(ref_periods_gpu, ref_periods, NET_STATE_SIZE*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(in_currents_gpu, in_currents, N_WINDOW*N_IN*sizeof(float), hipMemcpyHostToDevice);

    for(int time = 1; time < TIMESTEPS; ++time) {

        
        if(time%N_WINDOW == 0) {
            for(size_t i = 0; i < N_WINDOW; ++i) {
                for(size_t j = 0; j < N_REC; ++j) {
                    in_currents[N_REC*i + j] = 0.0;//uniform(0.0, 1.0);
                }
            }
            hipMemcpy(in_currents_gpu, in_currents, N_WINDOW*N_IN*sizeof(float), hipMemcpyHostToDevice);
        }
        

        stepLIF<<<4, N_REC/3>>>(volts_gpu, spikes_gpu, ref_periods_gpu, in_currents_gpu, w_in_gpu, w_rec_gpu, time);
    }

    hipMemcpy(w_in, w_in_gpu, W_IN_SIZE*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(w_rec, w_rec_gpu, W_REC_SIZE*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(volts, volts_gpu, NET_STATE_SIZE*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(spikes, spikes_gpu, NET_STATE_SIZE*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(ref_periods, ref_periods_gpu, NET_STATE_SIZE*sizeof(float), hipMemcpyDeviceToHost);

    hipFree(w_in_gpu);
    hipFree(w_rec_gpu);
    hipFree(volts_gpu);
    hipFree(spikes_gpu);
    hipFree(ref_periods_gpu);
    hipFree(in_currents_gpu);

    for(size_t i = 0; i < N_WINDOW; ++i) {
        //printf("%2d", i);
        cout << setw(5) << i;
        for(size_t j = 0; j < N_REC; ++j) {
            //printf("  ");
            //printf("%4.2f", volts[N_REC*i + j]);
            cout << "  ";
            cout << fixed << setprecision(2) << setw(5) << volts[N_REC*i + j];
        }
        //printf("    ");
        cout << "    ";
        for(size_t j = 0; j < N_REC; ++j) {
            //printf("  ");
            //printf("%4.2f", spikes[N_REC*i + j]);
            cout << "  ";
            cout << fixed << setprecision(2) << setw(5) << spikes[N_REC*i + j];
        }
        cout << endl;
    }

    return 0;

}

	.text
	.file	"test.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z7uniformff
.LCPI0_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	_Z7uniformff
	.type	_Z7uniformff,@function
_Z7uniformff:                           # @_Z7uniformff
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	callq	rand
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	mulss	.LCPI0_0(%rip), %xmm1
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	(%rsp), %xmm2                   # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	subss	%xmm2, %xmm0
	mulss	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7uniformff, .Lfunc_end0-_Z7uniformff
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__network_stepPfS_PiS_S_S_i # -- Begin function _Z27__device_stub__network_stepPfS_PiS_S_S_i
	.type	_Z27__device_stub__network_stepPfS_PiS_S_S_i,@function
_Z27__device_stub__network_stepPfS_PiS_S_S_i: # @_Z27__device_stub__network_stepPfS_PiS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12network_stepPfS_PiS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__network_stepPfS_PiS_S_S_i, .Lfunc_end1-_Z27__device_stub__network_stepPfS_PiS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__stepLIFPfS_PiS_S_S_i # -- Begin function _Z22__device_stub__stepLIFPfS_PiS_S_S_i
	.type	_Z22__device_stub__stepLIFPfS_PiS_S_S_i,@function
_Z22__device_stub__stepLIFPfS_PiS_S_S_i: # @_Z22__device_stub__stepLIFPfS_PiS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7stepLIFPfS_PiS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__stepLIFPfS_PiS_S_S_i, .Lfunc_end2-_Z22__device_stub__stepLIFPfS_PiS_S_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI3_1:
	.long	0xbf800000                      # float -1
.LCPI3_2:
	.long	0x3e99999a                      # float 0.300000012
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$2696, %rsp                     # imm = 0xA88
	.cfi_def_cfa_offset 2752
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	192(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB3_1:                                # %.preheader89
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%r15d, %r15d
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movss	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	.LCPI3_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	addss	%xmm0, %xmm0
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%r14
	addq	$32, %rbx
	cmpq	$8, %r14
	jne	.LBB3_1
# %bb.4:
	leaq	64(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB3_5:                                # %.preheader88
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
	xorl	%r15d, %r15d
.LBB3_6:                                #   Parent Loop BB3_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	xorps	%xmm1, %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB3_6
# %bb.7:                                #   in Loop: Header=BB3_5 Depth=1
	incq	%r14
	addq	$32, %rbx
	cmpq	$4, %r14
	jne	.LBB3_5
# %bb.8:
	leaq	2048(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB3_9:                                # %.preheader87
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_10 Depth 2
	xorl	%r15d, %r15d
.LBB3_10:                               #   Parent Loop BB3_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	addss	%xmm0, %xmm0
	addss	.LCPI3_1(%rip), %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB3_10
# %bb.11:                               #   in Loop: Header=BB3_9 Depth=1
	incq	%r14
	addq	$32, %rbx
	cmpq	$20, %r14
	jne	.LBB3_9
# %bb.12:
	leaq	1408(%rsp), %rdi
	xorl	%ebx, %ebx
	movl	$640, %edx                      # imm = 0x280
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	448(%rsp), %r14
.LBB3_13:                               # %.preheader85
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_14 Depth 2
	xorl	%r15d, %r15d
.LBB3_14:                               #   Parent Loop BB3_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movss	.LCPI3_2(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	mulss	%xmm1, %xmm0
	xorps	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%r15,4)
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB3_14
# %bb.15:                               #   in Loop: Header=BB3_13 Depth=1
	incq	%rbx
	addq	$32, %r14
	cmpq	$20, %rbx
	jne	.LBB3_13
# %bb.16:
	movabsq	$4294967298, %r15               # imm = 0x100000002
	leaq	768(%rsp), %rdi
	movl	$640, %edx                      # imm = 0x280
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	56(%rsp), %r13
	movl	$128, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	48(%rsp), %r12
	movl	$256, %esi                      # imm = 0x100
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rbx
	movl	$640, %esi                      # imm = 0x280
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r14
	movl	$640, %esi                      # imm = 0x280
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rbp
	movl	$640, %esi                      # imm = 0x280
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$320, %esi                      # imm = 0x140
	callq	hipMalloc
	movq	(%r13), %rdi
	leaq	64(%rsp), %rsi
	movl	$1, %r13d
	movl	$128, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	192(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	leaq	2048(%rsp), %rbx
	movl	$640, %edx                      # imm = 0x280
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	leaq	1408(%rsp), %r14
	movl	$640, %edx                      # imm = 0x280
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$640, %edx                      # imm = 0x280
	leaq	768(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	leaq	448(%rsp), %rsi
	movl	$320, %edx                      # imm = 0x140
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	2(%r15), %r12
.LBB3_17:                               # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_19
# %bb.18:                               #   in Loop: Header=BB3_17 Depth=1
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	56(%rsp), %r8
	movq	48(%rsp), %r9
	movl	%r13d, (%rsp)
	callq	_Z22__device_stub__stepLIFPfS_PiS_S_S_i
.LBB3_19:                               #   in Loop: Header=BB3_17 Depth=1
	incl	%r13d
	cmpl	$20, %r13d
	jne	.LBB3_17
# %bb.20:
	movq	56(%rsp), %rsi
	leaq	64(%rsp), %rdi
	movl	$128, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rsi
	leaq	192(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movl	$640, %edx                      # imm = 0x280
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movl	$640, %edx                      # imm = 0x280
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	leaq	768(%rsp), %rdi
	movl	$640, %edx                      # imm = 0x280
	movl	$2, %ecx
	callq	hipMemcpy
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%r15d, %r15d
	movl	$_ZSt4cout, %r12d
	movl	$-261, %ebp                     # imm = 0xFEFB
.LBB3_21:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_22 Depth 2
                                        #     Child Loop BB3_24 Depth 2
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	movq	$5, _ZSt4cout+16(%rax)
	movl	$_ZSt4cout, %edi
	movq	%r15, %rsi
	callq	_ZNSo9_M_insertImEERSoT_
	xorl	%r13d, %r13d
.LBB3_22:                               #   Parent Loop BB3_21 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rcx
	movl	_ZSt4cout+24(%rcx), %edx
	andl	%ebp, %edx
	orl	$4, %edx
	movl	%edx, _ZSt4cout+24(%rcx)
	movq	-24(%rax), %rcx
	movq	$2, _ZSt4cout+8(%rcx)
	movq	-24(%rax), %rax
	movq	$5, _ZSt4cout+16(%rax)
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r13,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	incq	%r13
	cmpq	$8, %r13
	jne	.LBB3_22
# %bb.23:                               #   in Loop: Header=BB3_21 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%r13d, %r13d
.LBB3_24:                               #   Parent Loop BB3_21 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rcx
	movl	_ZSt4cout+24(%rcx), %edx
	andl	%ebp, %edx
	orl	$4, %edx
	movl	%edx, _ZSt4cout+24(%rcx)
	movq	-24(%rax), %rcx
	movq	$2, _ZSt4cout+8(%rcx)
	movq	-24(%rax), %rax
	movq	$5, _ZSt4cout+16(%rax)
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r13,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	incq	%r13
	cmpq	$8, %r13
	jne	.LBB3_24
# %bb.25:                               #   in Loop: Header=BB3_21 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r15
	addq	$32, %rbx
	addq	$32, %r14
	cmpq	$20, %r15
	jne	.LBB3_21
# %bb.26:
	xorl	%eax, %eax
	addq	$2696, %rsp                     # imm = 0xA88
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12network_stepPfS_PiS_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7stepLIFPfS_PiS_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12network_stepPfS_PiS_S_S_i,@object # @_Z12network_stepPfS_PiS_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z12network_stepPfS_PiS_S_S_i
	.p2align	3, 0x0
_Z12network_stepPfS_PiS_S_S_i:
	.quad	_Z27__device_stub__network_stepPfS_PiS_S_S_i
	.size	_Z12network_stepPfS_PiS_S_S_i, 8

	.type	_Z7stepLIFPfS_PiS_S_S_i,@object # @_Z7stepLIFPfS_PiS_S_S_i
	.globl	_Z7stepLIFPfS_PiS_S_S_i
	.p2align	3, 0x0
_Z7stepLIFPfS_PiS_S_S_i:
	.quad	_Z22__device_stub__stepLIFPfS_PiS_S_S_i
	.size	_Z7stepLIFPfS_PiS_S_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"  "
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"    "
	.size	.L.str.1, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12network_stepPfS_PiS_S_S_i"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7stepLIFPfS_PiS_S_S_i"
	.size	.L__unnamed_2, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__network_stepPfS_PiS_S_S_i
	.addrsig_sym _Z22__device_stub__stepLIFPfS_PiS_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12network_stepPfS_PiS_S_S_i
	.addrsig_sym _Z7stepLIFPfS_PiS_S_S_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12network_stepPfS_PiS_S_S_i ; -- Begin function _Z12network_stepPfS_PiS_S_S_i
	.globl	_Z12network_stepPfS_PiS_S_S_i
	.p2align	8
	.type	_Z12network_stepPfS_PiS_S_S_i,@function
_Z12network_stepPfS_PiS_S_S_i:          ; @_Z12network_stepPfS_PiS_S_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s3, s[0:1], 0x44
	s_load_b32 s2, s[0:1], 0x30
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s3, 16
	s_and_b32 s1, s3, 0xffff
	s_add_i32 s3, s2, -1
	v_mad_u64_u32 v[2:3], null, s14, s1, v[1:2]
	v_mad_u64_u32 v[0:1], null, s15, s0, v[4:5]
	s_mul_hi_i32 s0, s3, 0x66666667
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 31
	s_ashr_i32 s0, s0, 3
	s_add_i32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, 8, v2
	v_cmp_gt_i32_e32 vcc_lo, 8, v0
	v_lshl_add_u32 v3, v2, 3, v0
	s_mul_i32 s1, s1, 20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_sub_i32 s1, s3, s1
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshl_add_u32 v5, s1, 3, v2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v6, s0, s18, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s0, s19, v8, s0
	v_add_co_u32 v4, s0, s6, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
	global_load_b32 v1, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v1, v4, v1 :: v_dual_lshlrev_b32 v4, 2, v3
	ds_store_b32 v4, v1
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_i32_e64 s0, 4, v2
	s_mul_hi_i32 s3, s2, 0x66666667
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_lshr_b32 s0, s3, 31
	s_ashr_i32 s13, s3, 3
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s0, s13, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, 20
	s_sub_i32 s0, s2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_lshl_add_u32 v5, s0, 2, v2
	v_lshlrev_b32_e32 v3, 2, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v6, s0, s16, v7
	v_add_co_ci_u32_e64 v7, s0, s17, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s10, v4
	v_add_co_ci_u32_e64 v5, s0, s11, v5, s0
	global_load_b32 v1, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v1, v4, v1
	ds_store_b32 v3, v1 offset:256
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_eq_u32_e64 s0, 0, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_13
; %bb.5:
	v_lshl_add_u32 v1, s1, 3, v0
	s_lshr_b32 s0, s3, 31
	s_lshr_b32 s1, s3, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s0, s1, s0
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s0, s0, 20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s1, s2, s0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v1, v[4:5], off
	global_load_b32 v4, v[6:7], off
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f32_e32 vcc_lo, 0.5, v1
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e64 s0, 1, v4
	v_lshl_add_u32 v1, s1, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB0_11
; %bb.6:
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s0, 0xb0a726a6
	s_mov_b32 s1, 0x3fee7078
	v_lshlrev_b32_e32 v0, 2, v0
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], s[0:1]
	s_mov_b64 s[0:1], 8
	v_cvt_f32_f64_e32 v3, v[2:3]
	v_mov_b32_e32 v2, v0
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v4, v2
	s_add_u32 s0, s0, -1
	v_add_nc_u32_e32 v2, 32, v2
	s_addc_u32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[0:1], 0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v4, v3
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ; %.preheader.preheader
	v_add_nc_u32_e32 v0, 0x100, v0
	s_mov_b64 s[0:1], 4
.LBB0_9:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v2, v0
	s_add_u32 s0, s0, -1
	v_add_nc_u32_e32 v0, 32, v0
	s_addc_u32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[0:1], 0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v2, v3
	s_cbranch_scc0 .LBB0_9
; %bb.10:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v3
	s_mov_b32 s0, 0x33333333
	s_mov_b32 s1, 0x3fd33333
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[4:5]
	v_mov_b32_e32 v4, 0
	v_cndmask_b32_e64 v5, 0, 0x3ff00000, vcc_lo
	v_cvt_f32_f64_e32 v6, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[4:5], v3, off
	global_store_b32 v[0:1], v6, off
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr4
.LBB0_11:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_13
; %bb.12:                               ; %._crit_edge
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, 1, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v3, 31, v6
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v3
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_and_b32_e32 v8, -2, v4
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[2:3], v7, off
	global_store_b32 v[4:5], v7, off
	global_store_b32 v[0:1], v6, off
.LBB0_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12network_stepPfS_PiS_S_S_i
		.amdhsa_group_segment_fixed_size 384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12network_stepPfS_PiS_S_S_i, .Lfunc_end0-_Z12network_stepPfS_PiS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1052
; NumSgprs: 22
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 384 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7stepLIFPfS_PiS_S_S_i ; -- Begin function _Z7stepLIFPfS_PiS_S_S_i
	.globl	_Z7stepLIFPfS_PiS_S_S_i
	.p2align	8
	.type	_Z7stepLIFPfS_PiS_S_S_i,@function
_Z7stepLIFPfS_PiS_S_S_i:                ; @_Z7stepLIFPfS_PiS_S_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 8, v2
	s_cbranch_execz .LBB1_9
; %bb.1:
	s_load_b32 s2, s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_i32 s4, s3, 0x66666667
	s_lshr_b32 s5, s4, 31
	s_ashr_i32 s4, s4, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s5
	s_mul_i32 s12, s4, 20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_sub_i32 s15, s3, s12
	s_mul_hi_i32 s3, s2, 0x66666667
	s_lshl_b32 s12, s15, 3
	s_lshr_b32 s13, s3, 31
	v_add_nc_u32_e32 v0, s12, v2
	s_lshr_b32 s3, s3, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s3, s3, s13
	v_ashrrev_i32_e32 v1, 31, v0
	s_mul_i32 s3, s3, 20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s2, s2, s3
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	global_load_b32 v1, v[0:1], off
	global_load_b32 v5, v[5:6], off
	v_lshl_add_u32 v0, s2, 3, v2
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f32_e32 vcc_lo, 0.5, v1
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e64 s2, 1, v5
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s3
	s_cbranch_execz .LBB1_7
; %bb.2:
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s2, 0xb0a726a6
	s_mov_b32 s3, 0x3fee7078
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	global_load_b32 v3, v[3:4], off
	s_ashr_i32 s13, s12, 31
	v_mov_b32_e32 v9, 0
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[3:4], v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], s[2:3]
	s_load_b128 s[0:3], s[0:1], 0x20
	v_cvt_f32_f64_e32 v8, v[3:4]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v5, vcc_lo
	s_lshl_b64 s[2:3], s[12:13], 2
	s_add_u32 s12, s6, s2
	s_addc_u32 s13, s7, s3
	s_mov_b64 s[2:3], 0
	global_store_b32 v[2:3], v8, off
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_add_u32 s16, s12, s2
	s_addc_u32 s17, s13, s3
	global_load_b32 v10, v[6:7], off
	global_load_b32 v11, v9, s[16:17]
	v_add_co_u32 v6, vcc_lo, v6, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[2:3], 32
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v10, v11
	global_store_b32 v[2:3], v8, off
	s_cbranch_scc0 .LBB1_3
; %bb.4:                                ; %.preheader
	s_lshl_b32 s2, s15, 2
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_ashr_i32 s3, s2, 31
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s2, s10, s0
	s_addc_u32 s3, s11, s1
	s_mov_b64 s[0:1], 0
.LBB1_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s10, s2, s0
	s_addc_u32 s11, s3, s1
	global_load_b32 v7, v[4:5], off
	global_load_b32 v9, v6, s[10:11]
	v_add_co_u32 v4, vcc_lo, v4, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[0:1], 16
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v7, v9
	global_store_b32 v[2:3], v8, off
	s_cbranch_scc0 .LBB1_5
; %bb.6:
	v_cvt_f64_f32_e32 v[2:3], v8
	s_mov_b32 s0, 0x33333333
	s_mov_b32 s1, 0x3fd33333
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[2:3]
	v_mov_b32_e32 v2, 0
	v_cndmask_b32_e64 v3, 0, 0x3ff00000, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f32_f64_e32 v2, v[2:3]
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr0
.LBB1_7:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s14
	s_cbranch_execz .LBB1_9
; %bb.8:                                ; %._crit_edge
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, 1, v5
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 31, v6
	v_add_nc_u32_e32 v4, v6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_and_b32_e32 v8, -2, v4
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[2:3], v7, off
	global_store_b32 v[4:5], v7, off
	global_store_b32 v[0:1], v6, off
.LBB1_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7stepLIFPfS_PiS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7stepLIFPfS_PiS_S_S_i, .Lfunc_end1-_Z7stepLIFPfS_PiS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 804
; NumSgprs: 20
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12network_stepPfS_PiS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z12network_stepPfS_PiS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7stepLIFPfS_PiS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z7stepLIFPfS_PiS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
