#include "device_launch_parameters.h"
#include <stdio.h>
/*
enum Type {
	NOT_NODE = 0,
	AND_NODE,
	IMPLIES_NODE,
	UNIVERSAL_NODE,
	EXISTENTIAL_NODE,
	BFUNC_NODE,
	EMPTY_NODE,
	SAME,
	SZ_SPD_CLOSE,
	SZ_LOC_CLOSE,
	SZ_LOC_DIST,
	SZ_LOC_DIST_NEQ ,
	SZ_LOC_RANGE,
	OR_NODE
};*/

#define NOT_NODE 0
#define AND_NODE 1
#define IMPLIES_NODE 2
#define UNIVERSAL_NODE 3
#define EXISTENTIAL_NODE 4
#define BFUNC_NODE 5
#define EMPTY_NODE 6
#define SAME 7
#define SZ_SPD_CLOSE 8
#define SZ_LOC_CLOSE 9
#define SZ_LOC_DIST 10
#define SZ_LOC_DIST_NEQ 11
#define SZ_LOC_RANGE 12
#define OR_NODE 13

#define MAX_PARAM_NUM 2
#define MAX_CCT_SIZE 3000000
#define MAX_LINK_SIZE 5000
#define DEBUG

struct Context{
	int id;
	double latitude;
	double longitude;
	double speed;
	int plateNumber;
};

struct Node {
	Node *next;
	Node *tail;
	int params[MAX_PARAM_NUM];
};


__device__ bool truth_values[MAX_CCT_SIZE];
__device__ Node links[MAX_CCT_SIZE];

extern "C"
__device__ bool same(Context c1, Context c2){
	return (c1.plateNumber == c2.plateNumber);
}

extern "C"
__device__ bool sz_spd_close(Context c1, Context c2){
	return ((c1.speed - c2.speed) >= -50.0 && (c1.speed - c2.speed) <= 50.0);
}

extern "C"
__device__ bool sz_loc_close(Context c1, Context c2){
	return ((c1.latitude - c2.latitude) * (c1.latitude - c2.latitude) + (c1.longitude - c2.longitude) * (c1.longitude - c2.longitude)) <= 0.000001;
}

extern "C"
__device__ bool sz_loc_dist(Context c1, Context c2){
	return ((c1.latitude - c2.latitude) * (c1.latitude - c2.latitude) + (c1.longitude - c2.longitude) * (c1.longitude - c2.longitude)) <= 0.000625;
}

extern "C"
__device__ bool sz_loc_dist_neq(Context c1, Context c2){
	double dist = ((c1.latitude - c2.latitude) * (c1.latitude - c2.latitude) + (c1.longitude - c2.longitude) * (c1.longitude - c2.longitude));
	bool result = true;
    if (dist > 0.000625 || dist == 0) {
    	result = false;
    }
    return result;
	//return (dist <= 0.000625) && (dist != 0);
}

extern "C"
__device__ bool sz_loc_range(Context c){
	return c.longitude >= 112.0 && c.longitude <= 116.0 && c.latitude >=20.0 && c.latitude <= 24.0;
}

extern "C"
__device__ void init_node(Node *n){
	n->next = NULL;
	n->tail = n;
	for (int i = 0; i < MAX_PARAM_NUM; i++) {
		n->params[i] = -1;
	}
}

extern "C"
__device__ bool is_null_node(Node *n){
	bool res = true;
	for (int i = 0; i < MAX_PARAM_NUM; i++) {
		res = res && (n->params[i] == -1);
	}
	return res;
}


extern "C"
__device__ void linkHelper(Node *link1, Node *link2) {
	//inital and assumpt that link1 != null, links != null
	if (is_null_node(link1)) {
		for (int i = 0; i < MAX_PARAM_NUM; i++) {
			link1->params[i] = link2->params[i];
		}
		link1->next = NULL;
		link1->tail = link1;

		
		if(link2->next != NULL) {
			link2->next->tail = link2->tail;
		}
		link2 = link2->next;
	}

	if (link2 == NULL) {
		return;
	}

	link1->tail->next = link2;
	link1->tail = link2->tail;
}

extern "C"
__device__ int calc_offset(	int node, int tid, Context *params,
							int *parent, int *left_child, int *right_child, int *node_type, int *pattern_idx,
							int *pattern_begin, int *pattern_length, int *pattern,
							double *longitude, double *latitude, double *speed, int *plateNumber, // contexts
							int *branch_size) {

	int offset = branch_size[node];
	int current_node = node;
	int index = 0, tmp = tid;
	while (parent[current_node] != -1) {
		int type = node_type[parent[current_node]];
		if (type == EXISTENTIAL_NODE || type == UNIVERSAL_NODE) {
			int len = pattern_length[pattern_idx[parent[current_node]]];
			int branch_idx = tmp % len;
			tmp /= len;

			params[index].id = pattern[pattern_begin[pattern_idx[parent[current_node]]] + branch_idx];//(pattern + pattern_idx[parent[current_node]] * MAX_PATTERN_SIZE)[(branch_idx + pattern_begin[pattern_idx[parent[current_node]]]) % MAX_PATTERN_SIZE];
			params[index].latitude = latitude[params[index].id];
			params[index].longitude = longitude[params[index].id];
			params[index].speed = speed[params[index].id];
			params[index].plateNumber = plateNumber[params[index].id];

			offset += branch_idx * branch_size[current_node] ;
//			printf("branch_idx = %d, branch_size = %d\n", branch_idx, branch_size[current_node]);
			index++;
		}
		else if (type == AND_NODE || type == IMPLIES_NODE || type == OR_NODE) {
			if (right_child[parent[current_node]] == current_node) {
				offset += branch_size[left_child[parent[current_node]]];
			}
		}
		else {
		    offset += 0;
		}
		current_node = parent[current_node];
	}
	return offset - 1;
}

extern "C"
__global__ void evaluation(int *parent, int *left_child, int *right_child, int *node_type, int *pattern_idx, //constraint rule
                          	 int *branch_size, int cunit_begin, int cunit_end,//cunit_end is the root of cunit
                          	 int *pattern_begin, int *pattern_length, int *pattern, //patterns
                          	 double *longitude, double *latitude, double *speed,int *plateNumber,// contexts
                          	 short *truth_value_result,
                          	 int *link_result, int *link_num, int *cur_link_size,
                          	 int last_cunit_root,
                          	 int ccopy_num) {
	
	
	int tid = threadIdx.x + blockDim.x * blockIdx.x;
	if(tid < ccopy_num) {

		Context params[MAX_PARAM_NUM];
		for (int i = 0; i < MAX_PARAM_NUM; i++) {
            params[i].id = -1;
         }
		int ccopy_root_offset = calc_offset(cunit_end, tid, params,
											parent, left_child, right_child, node_type, pattern_idx,
											pattern_begin, pattern_length, pattern,
											longitude, latitude, speed, plateNumber,
											branch_size);

//#ifdef DEBUG
//		printf("root = %d, ccopynum = %d, offset = %d\n",cunit_end, ccopy_num, ccopy_root_offset);
//#endif
		for (int node = cunit_begin; node <= cunit_end; node++) {
			int offset = ccopy_root_offset - (cunit_end - node);
			int type = node_type[node];
			bool value;

			Node* cur_links = &links[offset];
			init_node(cur_links);

			switch(type) {
				case UNIVERSAL_NODE: {
					int step = branch_size[left_child[node]];
					value = true;
					bool first = true;
					for (int i = 0; i < pattern_length[pattern_idx[node]]; i++) {
						value = value && truth_values[offset - (i * step + 1)];
						if(!truth_values[offset - (i * step + 1)]) {
							if(first) {
								init_node(cur_links);
								first = false;
							}
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
						else if(value) {
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
					}

					break;
				}

				case EXISTENTIAL_NODE: {
					int step = branch_size[left_child[node]];
					value = false;
					bool first = true;
					for (int i = 0; i < pattern_length[pattern_idx[node]]; i++) {
						value = value || truth_values[offset - (i * step + 1)];
						if(truth_values[offset - (i * step + 1)]) {
							if(first) {
								init_node(cur_links);
								first = false;
							}
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
						else if(!value) {
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
					}
					break;
				}

				case AND_NODE: {
					//right && left
					value = truth_values[offset - 1] && truth_values[offset - (branch_size[right_child[node]] + 1)];

					if (truth_values[offset - 1] == value) {
						linkHelper(cur_links, &(links[offset - 1]));
					}

					if (truth_values[offset - (branch_size[right_child[node]] + 1)] == value) {
						linkHelper(cur_links, &(links[offset - (branch_size[right_child[node]] + 1)]));
					}

					break;
				}
				case OR_NODE: {
					//right || left
					value = truth_values[offset - 1] || truth_values[offset - (branch_size[right_child[node]] + 1)];

					if (truth_values[offset - 1] == value) {
						linkHelper(cur_links, &(links[offset - 1]));
					}

					if (truth_values[offset - (branch_size[right_child[node]] + 1)] == value) {
						linkHelper(cur_links, &(links[offset - (branch_size[right_child[node]] + 1)]));
					}

					break;
				}

				case IMPLIES_NODE: {
					//!left || right
					value = !truth_values[offset - (branch_size[right_child[node]] + 1)] || truth_values[offset - 1];

					if(value) {
	                   linkHelper(cur_links, &(links[offset - 1]));
	                   linkHelper(cur_links, &(links[offset - (branch_size[right_child[node]] + 1)]));
					}
					else {
					   linkHelper(cur_links, &(links[offset - 1]));
					}

					break;
				}

				case NOT_NODE: {
					value = !truth_values[offset - 1];
					linkHelper(cur_links, &(links[offset - 1]));
					break;
				}

				default : { //BFUNC
					switch(type) {
						case SAME: {
							value = same(params[0], params[1]);
							break;
						}

						case SZ_SPD_CLOSE: {
							value = sz_spd_close(params[0], params[1]);
							break;
						}

						case SZ_LOC_CLOSE: {
							value = sz_loc_close(params[0], params[1]);
							break;
						}

						case SZ_LOC_DIST: {
							value = sz_loc_dist(params[0], params[1]);
							break;
						}

						case SZ_LOC_DIST_NEQ: {
							value = sz_loc_dist_neq(params[0], params[1]);
							break;
						}

						case SZ_LOC_RANGE: {
							value = sz_loc_range(params[0]);
							break;
						}
					}

			
					for (int i = 0; i < MAX_PARAM_NUM; i++) {
						cur_links->params[i] = params[i].id;
					}
					break;
				}

				
			}

			truth_values[offset] = value;
		}

		if (last_cunit_root == cunit_end ) {
		    *truth_value_result = truth_values[ccopy_root_offset];
		    if(!truth_values[ccopy_root_offset]) {
            
         		int len = 0;
                for(Node *head = &links[ccopy_root_offset]; head != NULL; head = head ->next) {
                
                	if(len < MAX_LINK_SIZE) {
	                	for(int j = 0; j < MAX_PARAM_NUM; j++) {
	                         link_result[MAX_PARAM_NUM * len + j] = head->params[j];
	                    }
                	}

                    len++;
                }
                
                *cur_link_size = len;
                *link_num = len > MAX_LINK_SIZE ? MAX_LINK_SIZE : len;
         	}
        }
	}

 }

	.file	"tmpxft_0035bc0d_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	same
	.type	same, @function
same:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	same, .-same
	.globl	sz_spd_close
	.type	sz_spd_close, @function
sz_spd_close:
.LFB2181:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2181:
	.size	sz_spd_close, .-sz_spd_close
	.globl	sz_loc_close
	.type	sz_loc_close, @function
sz_loc_close:
.LFB2183:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2183:
	.size	sz_loc_close, .-sz_loc_close
	.globl	sz_loc_dist
	.type	sz_loc_dist, @function
sz_loc_dist:
.LFB2185:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2185:
	.size	sz_loc_dist, .-sz_loc_dist
	.globl	sz_loc_dist_neq
	.type	sz_loc_dist_neq, @function
sz_loc_dist_neq:
.LFB2187:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2187:
	.size	sz_loc_dist_neq, .-sz_loc_dist_neq
	.globl	sz_loc_range
	.type	sz_loc_range, @function
sz_loc_range:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2032:
	.size	sz_loc_range, .-sz_loc_range
	.globl	init_node
	.type	init_node, @function
init_node:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	init_node, .-init_node
	.globl	is_null_node
	.type	is_null_node, @function
is_null_node:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2034:
	.size	is_null_node, .-is_null_node
	.globl	linkHelper
	.type	linkHelper, @function
linkHelper:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2035:
	.size	linkHelper, .-linkHelper
	.globl	calc_offset
	.type	calc_offset, @function
calc_offset:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2036:
	.size	calc_offset, .-calc_offset
	.globl	_Z68__device_stub__Z10evaluationPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_iiPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_ii
	.type	_Z68__device_stub__Z10evaluationPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_iiPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_ii, @function
_Z68__device_stub__Z10evaluationPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_iiPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_ii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$392, %rsp
	.cfi_def_cfa_offset 400
	movq	416(%rsp), %rax
	movq	%rdi, 136(%rsp)
	leaq	160(%rsp), %rdi
	movq	%rsi, 128(%rsp)
	leaq	172(%rsp), %rsi
	movq	%rax, 88(%rsp)
	movq	424(%rsp), %rax
	movq	%rdx, 120(%rsp)
	leaq	144(%rsp), %rdx
	movq	%rax, 80(%rsp)
	movq	432(%rsp), %rax
	movq	%rcx, 112(%rsp)
	leaq	152(%rsp), %rcx
	movq	%rax, 72(%rsp)
	movq	440(%rsp), %rax
	movq	%r8, 104(%rsp)
	movq	%rax, 64(%rsp)
	movq	448(%rsp), %rax
	movq	%r9, 96(%rsp)
	movq	%rax, 56(%rsp)
	movq	456(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	464(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	472(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	480(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	488(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	496(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 376(%rsp)
	xorl	%eax, %eax
	leaq	136(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	504(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	512(%rsp), %rax
	movq	%rax, 368(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 160(%rsp)
	movl	$1, 168(%rsp)
	movq	%rax, 172(%rsp)
	movl	$1, 180(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	152(%rsp)
	.cfi_def_cfa_offset 408
	leaq	evaluation(%rip), %rdi
	pushq	152(%rsp)
	.cfi_def_cfa_offset 416
	movq	188(%rsp), %rcx
	movl	196(%rsp), %r8d
	movq	176(%rsp), %rsi
	movl	184(%rsp), %edx
	leaq	224(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 408
	popq	%rdx
	.cfi_def_cfa_offset 400
.L22:
	movq	376(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$392, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z68__device_stub__Z10evaluationPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_iiPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_ii, .-_Z68__device_stub__Z10evaluationPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_iiPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_ii
	.globl	evaluation
	.type	evaluation, @function
evaluation:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z10evaluationPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_iiPiS_S_S_S_S_iiS_S_S_PdS0_S0_S_PsS_S_S_ii
	.cfi_endproc
.LFE2062:
	.size	evaluation, .-evaluation
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"evaluation"
.LC1:
	.string	"truth_values"
.LC2:
	.string	"links"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	evaluation(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$3000000, %r9d
	leaq	_ZL12truth_values(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72000000, %r9d
	leaq	_ZL5links(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5links
	.comm	_ZL5links,72000000,32
	.local	_ZL12truth_values
	.comm	_ZL12truth_values,3000000,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

#include <stdio.h>
/*
enum Type {
	NOT_NODE = 0,
	AND_NODE,
	IMPLIES_NODE,
	UNIVERSAL_NODE,
	EXISTENTIAL_NODE,
	BFUNC_NODE,
	EMPTY_NODE,
	SAME,
	SZ_SPD_CLOSE,
	SZ_LOC_CLOSE,
	SZ_LOC_DIST,
	SZ_LOC_DIST_NEQ ,
	SZ_LOC_RANGE,
	OR_NODE
};*/

#define NOT_NODE 0
#define AND_NODE 1
#define IMPLIES_NODE 2
#define UNIVERSAL_NODE 3
#define EXISTENTIAL_NODE 4
#define BFUNC_NODE 5
#define EMPTY_NODE 6
#define SAME 7
#define SZ_SPD_CLOSE 8
#define SZ_LOC_CLOSE 9
#define SZ_LOC_DIST 10
#define SZ_LOC_DIST_NEQ 11
#define SZ_LOC_RANGE 12
#define OR_NODE 13

#define MAX_PARAM_NUM 2
#define MAX_CCT_SIZE 3000000
#define MAX_LINK_SIZE 5000
#define DEBUG

struct Context{
	int id;
	double latitude;
	double longitude;
	double speed;
	int plateNumber;
};

struct Node {
	Node *next;
	Node *tail;
	int params[MAX_PARAM_NUM];
};


__device__ bool truth_values[MAX_CCT_SIZE];
__device__ Node links[MAX_CCT_SIZE];

extern "C"
__device__ bool same(Context c1, Context c2){
	return (c1.plateNumber == c2.plateNumber);
}

extern "C"
__device__ bool sz_spd_close(Context c1, Context c2){
	return ((c1.speed - c2.speed) >= -50.0 && (c1.speed - c2.speed) <= 50.0);
}

extern "C"
__device__ bool sz_loc_close(Context c1, Context c2){
	return ((c1.latitude - c2.latitude) * (c1.latitude - c2.latitude) + (c1.longitude - c2.longitude) * (c1.longitude - c2.longitude)) <= 0.000001;
}

extern "C"
__device__ bool sz_loc_dist(Context c1, Context c2){
	return ((c1.latitude - c2.latitude) * (c1.latitude - c2.latitude) + (c1.longitude - c2.longitude) * (c1.longitude - c2.longitude)) <= 0.000625;
}

extern "C"
__device__ bool sz_loc_dist_neq(Context c1, Context c2){
	double dist = ((c1.latitude - c2.latitude) * (c1.latitude - c2.latitude) + (c1.longitude - c2.longitude) * (c1.longitude - c2.longitude));
	bool result = true;
    if (dist > 0.000625 || dist == 0) {
    	result = false;
    }
    return result;
	//return (dist <= 0.000625) && (dist != 0);
}

extern "C"
__device__ bool sz_loc_range(Context c){
	return c.longitude >= 112.0 && c.longitude <= 116.0 && c.latitude >=20.0 && c.latitude <= 24.0;
}

extern "C"
__device__ void init_node(Node *n){
	n->next = NULL;
	n->tail = n;
	for (int i = 0; i < MAX_PARAM_NUM; i++) {
		n->params[i] = -1;
	}
}

extern "C"
__device__ bool is_null_node(Node *n){
	bool res = true;
	for (int i = 0; i < MAX_PARAM_NUM; i++) {
		res = res && (n->params[i] == -1);
	}
	return res;
}


extern "C"
__device__ void linkHelper(Node *link1, Node *link2) {
	//inital and assumpt that link1 != null, links != null
	if (is_null_node(link1)) {
		for (int i = 0; i < MAX_PARAM_NUM; i++) {
			link1->params[i] = link2->params[i];
		}
		link1->next = NULL;
		link1->tail = link1;

		
		if(link2->next != NULL) {
			link2->next->tail = link2->tail;
		}
		link2 = link2->next;
	}

	if (link2 == NULL) {
		return;
	}

	link1->tail->next = link2;
	link1->tail = link2->tail;
}

extern "C"
__device__ int calc_offset(	int node, int tid, Context *params,
							int *parent, int *left_child, int *right_child, int *node_type, int *pattern_idx,
							int *pattern_begin, int *pattern_length, int *pattern,
							double *longitude, double *latitude, double *speed, int *plateNumber, // contexts
							int *branch_size) {

	int offset = branch_size[node];
	int current_node = node;
	int index = 0, tmp = tid;
	while (parent[current_node] != -1) {
		int type = node_type[parent[current_node]];
		if (type == EXISTENTIAL_NODE || type == UNIVERSAL_NODE) {
			int len = pattern_length[pattern_idx[parent[current_node]]];
			int branch_idx = tmp % len;
			tmp /= len;

			params[index].id = pattern[pattern_begin[pattern_idx[parent[current_node]]] + branch_idx];//(pattern + pattern_idx[parent[current_node]] * MAX_PATTERN_SIZE)[(branch_idx + pattern_begin[pattern_idx[parent[current_node]]]) % MAX_PATTERN_SIZE];
			params[index].latitude = latitude[params[index].id];
			params[index].longitude = longitude[params[index].id];
			params[index].speed = speed[params[index].id];
			params[index].plateNumber = plateNumber[params[index].id];

			offset += branch_idx * branch_size[current_node] ;
//			printf("branch_idx = %d, branch_size = %d\n", branch_idx, branch_size[current_node]);
			index++;
		}
		else if (type == AND_NODE || type == IMPLIES_NODE || type == OR_NODE) {
			if (right_child[parent[current_node]] == current_node) {
				offset += branch_size[left_child[parent[current_node]]];
			}
		}
		else {
		    offset += 0;
		}
		current_node = parent[current_node];
	}
	return offset - 1;
}

extern "C"
__global__ void evaluation(int *parent, int *left_child, int *right_child, int *node_type, int *pattern_idx, //constraint rule
                          	 int *branch_size, int cunit_begin, int cunit_end,//cunit_end is the root of cunit
                          	 int *pattern_begin, int *pattern_length, int *pattern, //patterns
                          	 double *longitude, double *latitude, double *speed,int *plateNumber,// contexts
                          	 short *truth_value_result,
                          	 int *link_result, int *link_num, int *cur_link_size,
                          	 int last_cunit_root,
                          	 int ccopy_num) {
	
	
	int tid = threadIdx.x + blockDim.x * blockIdx.x;
	if(tid < ccopy_num) {

		Context params[MAX_PARAM_NUM];
		for (int i = 0; i < MAX_PARAM_NUM; i++) {
            params[i].id = -1;
         }
		int ccopy_root_offset = calc_offset(cunit_end, tid, params,
											parent, left_child, right_child, node_type, pattern_idx,
											pattern_begin, pattern_length, pattern,
											longitude, latitude, speed, plateNumber,
											branch_size);

//#ifdef DEBUG
//		printf("root = %d, ccopynum = %d, offset = %d\n",cunit_end, ccopy_num, ccopy_root_offset);
//#endif
		for (int node = cunit_begin; node <= cunit_end; node++) {
			int offset = ccopy_root_offset - (cunit_end - node);
			int type = node_type[node];
			bool value;

			Node* cur_links = &links[offset];
			init_node(cur_links);

			switch(type) {
				case UNIVERSAL_NODE: {
					int step = branch_size[left_child[node]];
					value = true;
					bool first = true;
					for (int i = 0; i < pattern_length[pattern_idx[node]]; i++) {
						value = value && truth_values[offset - (i * step + 1)];
						if(!truth_values[offset - (i * step + 1)]) {
							if(first) {
								init_node(cur_links);
								first = false;
							}
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
						else if(value) {
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
					}

					break;
				}

				case EXISTENTIAL_NODE: {
					int step = branch_size[left_child[node]];
					value = false;
					bool first = true;
					for (int i = 0; i < pattern_length[pattern_idx[node]]; i++) {
						value = value || truth_values[offset - (i * step + 1)];
						if(truth_values[offset - (i * step + 1)]) {
							if(first) {
								init_node(cur_links);
								first = false;
							}
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
						else if(!value) {
							linkHelper(cur_links, &(links[offset - (i * step + 1)]));
						}
					}
					break;
				}

				case AND_NODE: {
					//right && left
					value = truth_values[offset - 1] && truth_values[offset - (branch_size[right_child[node]] + 1)];

					if (truth_values[offset - 1] == value) {
						linkHelper(cur_links, &(links[offset - 1]));
					}

					if (truth_values[offset - (branch_size[right_child[node]] + 1)] == value) {
						linkHelper(cur_links, &(links[offset - (branch_size[right_child[node]] + 1)]));
					}

					break;
				}
				case OR_NODE: {
					//right || left
					value = truth_values[offset - 1] || truth_values[offset - (branch_size[right_child[node]] + 1)];

					if (truth_values[offset - 1] == value) {
						linkHelper(cur_links, &(links[offset - 1]));
					}

					if (truth_values[offset - (branch_size[right_child[node]] + 1)] == value) {
						linkHelper(cur_links, &(links[offset - (branch_size[right_child[node]] + 1)]));
					}

					break;
				}

				case IMPLIES_NODE: {
					//!left || right
					value = !truth_values[offset - (branch_size[right_child[node]] + 1)] || truth_values[offset - 1];

					if(value) {
	                   linkHelper(cur_links, &(links[offset - 1]));
	                   linkHelper(cur_links, &(links[offset - (branch_size[right_child[node]] + 1)]));
					}
					else {
					   linkHelper(cur_links, &(links[offset - 1]));
					}

					break;
				}

				case NOT_NODE: {
					value = !truth_values[offset - 1];
					linkHelper(cur_links, &(links[offset - 1]));
					break;
				}

				default : { //BFUNC
					switch(type) {
						case SAME: {
							value = same(params[0], params[1]);
							break;
						}

						case SZ_SPD_CLOSE: {
							value = sz_spd_close(params[0], params[1]);
							break;
						}

						case SZ_LOC_CLOSE: {
							value = sz_loc_close(params[0], params[1]);
							break;
						}

						case SZ_LOC_DIST: {
							value = sz_loc_dist(params[0], params[1]);
							break;
						}

						case SZ_LOC_DIST_NEQ: {
							value = sz_loc_dist_neq(params[0], params[1]);
							break;
						}

						case SZ_LOC_RANGE: {
							value = sz_loc_range(params[0]);
							break;
						}
					}

			
					for (int i = 0; i < MAX_PARAM_NUM; i++) {
						cur_links->params[i] = params[i].id;
					}
					break;
				}

				
			}

			truth_values[offset] = value;
		}

		if (last_cunit_root == cunit_end ) {
		    *truth_value_result = truth_values[ccopy_root_offset];
		    if(!truth_values[ccopy_root_offset]) {
            
         		int len = 0;
                for(Node *head = &links[ccopy_root_offset]; head != NULL; head = head ->next) {
                
                	if(len < MAX_LINK_SIZE) {
	                	for(int j = 0; j < MAX_PARAM_NUM; j++) {
	                         link_result[MAX_PARAM_NUM * len + j] = head->params[j];
	                    }
                	}

                    len++;
                }
                
                *cur_link_size = len;
                *link_num = len > MAX_LINK_SIZE ? MAX_LINK_SIZE : len;
         	}
        }
	}

 }

	.text
	.file	"kernel.hip"
	.globl	__device_stub__evaluation       # -- Begin function __device_stub__evaluation
	.type	__device_stub__evaluation,@function
__device_stub__evaluation:              # @__device_stub__evaluation
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$evaluation, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__evaluation, .Lfunc_end0-__device_stub__evaluation
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$evaluation, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$truth_values, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$3000000, %r9d                  # imm = 0x2DC6C0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$links, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$72000000, %r9d                 # imm = 0x44AA200
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	truth_values,@object            # @truth_values
	.local	truth_values
	.comm	truth_values,3000000,16
	.type	links,@object                   # @links
	.local	links
	.comm	links,72000000,16
	.type	evaluation,@object              # @evaluation
	.section	.rodata,"a",@progbits
	.globl	evaluation
	.p2align	3, 0x0
evaluation:
	.quad	__device_stub__evaluation
	.size	evaluation, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"evaluation"
	.size	.L__unnamed_1, 11

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"truth_values"
	.size	.L__unnamed_2, 13

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"links"
	.size	.L__unnamed_3, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__evaluation
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym truth_values
	.addrsig_sym links
	.addrsig_sym evaluation
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	evaluation              ; -- Begin function evaluation
	.globl	evaluation
	.p2align	8
	.type	evaluation,@function
evaluation:                             ; @evaluation
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0xa4
	s_load_b64 s[34:35], s[0:1], 0x90
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s35, v1
	s_cbranch_execz .LBB0_184
; %bb.1:
	s_clause 0x2
	s_load_b64 s[36:37], s[0:1], 0x30
	s_load_b128 s[28:31], s[0:1], 0x20
	s_load_b256 s[20:27], s[0:1], 0x0
	v_mov_b32_e32 v0, -1
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s37, 31
	s_mov_b32 s2, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[2:3], 2
	s_add_u32 s6, s30, s4
	s_addc_u32 s7, s31, s5
	s_add_u32 s4, s20, s4
	s_load_b32 s33, s[6:7], 0x0
	s_addc_u32 s5, s21, s5
	s_load_b32 s40, s[4:5], 0x0
	s_load_b512 s[4:19], s[0:1], 0x38
	s_clause 0x1
	scratch_store_b32 off, v0, off offset:16
	scratch_store_b32 off, v0, off offset:56
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v4, s33
	s_cmp_eq_u32 s40, -1
	s_cbranch_scc1 .LBB0_18
; %bb.2:                                ; %.lr.ph.i.preheader
	v_mov_b32_e32 v0, s33
	s_mov_b32 s33, 0
	s_mov_b32 s35, s37
.LBB0_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s38, s40
	s_ashr_i32 s39, s40, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[40:41], s[38:39], 2
	s_add_u32 s42, s26, s40
	s_addc_u32 s43, s27, s41
	s_load_b32 s43, s[42:43], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s42, s43, -3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s42, 1
	s_cbranch_scc0 .LBB0_6
; %bb.4:                                ; %NodeBlock
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_cmp_lt_i32 s43, 13
	s_cbranch_scc1 .LBB0_7
; %bb.5:                                ; %LeafBlock595
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_cmp_eq_u32 s43, 13
	s_mov_b32 s44, 0
	s_cselect_b32 s42, -1, 0
	s_branch .LBB0_8
.LBB0_6:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s35, -1
                                        ; implicit-def: $vgpr4
	s_branch .LBB0_14
.LBB0_7:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s44, -1
	s_mov_b32 s42, 0
.LBB0_8:                                ; %Flow696
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s44
	s_cbranch_vccnz .LBB0_10
; %bb.9:                                ; %LeafBlock
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s43, s43, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s43, 2
	s_cselect_b32 s42, -1, 0
.LBB0_10:                               ; %Flow697
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v4, v0
	s_and_not1_b32 vcc_lo, exec_lo, s42
	s_cbranch_vccnz .LBB0_13
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s42, s24, s40
	s_addc_u32 s43, s25, s41
	v_mov_b32_e32 v4, v0
	s_load_b32 s42, s[42:43], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s42, s35
	s_cbranch_scc1 .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s42, s22, s40
	s_addc_u32 s43, s23, s41
	s_load_b32 s42, s[42:43], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s43, s42, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[42:43], s[42:43], 2
	s_add_u32 s42, s30, s42
	s_addc_u32 s43, s31, s43
	s_load_b32 s35, s[42:43], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, s35, v0
.LBB0_13:                               ; %Flow698
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s35, 0
.LBB0_14:                               ; %Flow699
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s35
	s_cbranch_vccz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s42, s28, s40
	s_addc_u32 s43, s29, s41
	v_ashrrev_i32_e32 v4, 31, v1
	s_load_b32 s42, s[42:43], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v1, v4
	v_xor_b32_e32 v5, v5, v4
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s43, s42, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[42:43], s[42:43], 2
	s_add_u32 s44, s6, s42
	s_addc_u32 s45, s7, s43
	s_load_b32 s35, s[44:45], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s44, s35, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s45, s35, s44
	v_xor_b32_e32 v4, s44, v4
	s_xor_b32 s45, s45, s44
	v_cvt_f32_u32_e32 v2, s45
	s_sub_i32 s46, 0, s45
	s_add_u32 s42, s4, s42
	s_addc_u32 s43, s5, s43
	s_lshl_b64 s[2:3], s[2:3], 2
	v_rcp_iflag_f32_e32 v2, v2
	s_load_b32 s42, s[42:43], 0x0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v3, s46, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v3
	v_add_nc_u32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v5, v2
	v_mul_lo_u32 v3, v2, s45
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v5, v3
	v_add_nc_u32_e32 v5, 1, v2
	v_subrev_nc_u32_e32 v6, s45, v3
	v_cmp_le_u32_e32 vcc_lo, s45, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v2, v2, v5
	v_cmp_le_u32_e32 vcc_lo, s45, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, 1, v2
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v4
	v_sub_nc_u32_e32 v14, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, v14, s35
	s_mul_i32 s35, s33, 40
	s_add_i32 s35, s35, 16
	s_add_u32 s2, s30, s2
	s_addc_u32 s3, s31, s3
	s_add_i32 s33, s33, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v1, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, s42, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_co_u32 v8, vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v3, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v7, vcc_lo
	global_load_b64 v[6:7], v[8:9], off
	global_load_b64 v[8:9], v[10:11], off
	global_load_b64 v[10:11], v[3:4], off
	global_load_b32 v3, v[12:13], off
	s_load_b32 s2, s[2:3], 0x0
	scratch_store_b32 off, v2, s35
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[6:9], s35 offset:8
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[10:11], s35 offset:24
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v3, s35 offset:32
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[4:5], null, s2, v15, v[0:1]
	v_mov_b32_e32 v1, v14
.LBB0_16:                               ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s2, s20, s40
	s_addc_u32 s3, s21, s41
	s_load_b32 s40, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s40, -1
	s_cbranch_scc0 .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v0, v4
	s_mov_b64 s[2:3], s[38:39]
	s_mov_b32 s35, s38
	s_branch .LBB0_3
.LBB0_18:                               ; %calc_offset.exit
	s_cmp_gt_i32 s36, s37
	s_cbranch_scc1 .LBB0_175
; %bb.19:                               ; %.lr.ph401
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, s36, v4
	v_dual_mov_b32 v5, -1 :: v_dual_add_nc_u32 v16, -1, v4
	s_mov_b32 s8, 0x47ae147b
	s_delay_alu instid0(VALU_DEP_2)
	v_subrev_nc_u32_e32 v1, s37, v1
	s_mov_b32 s10, 0xa0b5ed8d
	s_mov_b32 s9, 0x3f447ae1
	s_mov_b32 s11, 0x3eb0c6f7
                                        ; implicit-def: $sgpr16
	s_getpc_b64 s[42:43]
	s_add_u32 s42, s42, links@rel32@lo+12
	s_addc_u32 s43, s43, links@rel32@hi+20
	v_add_nc_u32_e32 v17, -2, v1
.LBB0_20:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
	s_ashr_i32 s13, s36, 31
	s_mov_b32 s12, s36
	s_sub_i32 s4, s36, s37
	s_lshl_b64 s[14:15], s[12:13], 2
	v_dual_mov_b32 v1, v0 :: v_dual_add_nc_u32 v18, s4, v16
	s_add_u32 s2, s26, s14
	s_addc_u32 s3, s27, s15
	v_mov_b32_e32 v6, v5
	global_load_b32 v7, v0, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, links@rel32@lo+4
	s_addc_u32 s3, s3, links@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, links@rel32@lo+20
	s_addc_u32 s5, s5, links@rel32@hi+28
	v_mad_i64_i32 v[2:3], null, v18, 24, s[2:3]
	v_mad_i64_i32 v[8:9], null, v18, 24, s[4:5]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, links@rel32@lo+12
	s_addc_u32 s3, s3, links@rel32@hi+20
	s_clause 0x1
	global_store_b128 v[2:3], v[0:3], off
	global_store_b64 v[8:9], v[5:6], off
	v_ashrrev_i32_e32 v19, 31, v18
	s_mov_b32 s5, 0
	s_mov_b32 s20, 0
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v7
	v_mad_i64_i32 v[6:7], null, v18, 24, s[2:3]
	s_mov_b32 s2, -1
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_lt_i32 s13, 8
	s_cbranch_scc1 .LBB0_60
; %bb.21:                               ; %NodeBlock621
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 10
	s_cbranch_scc0 .LBB0_40
; %bb.22:                               ; %NodeBlock619
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 11
	s_cbranch_scc0 .LBB0_41
; %bb.23:                               ; %NodeBlock617
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 12
	s_cbranch_scc0 .LBB0_42
; %bb.24:                               ; %LeafBlock615
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_eq_u32 s13, 13
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr17
	s_cbranch_scc0 .LBB0_39
; %bb.25:                               ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+3
	s_addc_u32 s3, s3, truth_values@rel32@hi+11
	v_add_co_u32 v10, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v19, vcc_lo
	s_mov_b32 s17, -1
	s_mov_b32 s2, exec_lo
	global_load_u8 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v1
	s_cbranch_execz .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s20, s24, s14
	s_addc_u32 s21, s25, s15
	global_load_b32 v10, v0, s[20:21]
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, truth_values@rel32@lo+4
	s_addc_u32 s21, s21, truth_values@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s30, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s31, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_xad_u32 v10, v10, -1, v18
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v10, vcc_lo, v10, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	global_load_u8 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v10
	s_or_not1_b32 s17, vcc_lo, exec_lo
.LBB0_27:                               ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cndmask_b32_e64 v14, 0, 1, s17
	v_dual_mov_b32 v11, -1 :: v_dual_mov_b32 v10, -1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_eq_u16_e64 v1, v14
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %is_null_node.exit.i350
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v[2:3], off offset:-24
	global_load_b64 v[10:11], v[8:9], off offset:-24
	v_mov_b32_e32 v1, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b64 v[8:9], v[10:11], off
	global_store_b128 v[2:3], v[0:3], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_30
; %bb.29:                               ; %.critedge.i348
                                        ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[20:21], v[6:7], off offset:-24
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[20:21] offset:8
	global_load_b64 v[22:23], v[6:7], off
	s_waitcnt vmcnt(0)
	flat_store_b64 v[22:23], v[12:13]
	global_store_b64 v[6:7], v[20:21], off
.LBB0_30:                               ; %Flow630
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_31:                               ; %linkHelper.exit353
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_add_u32 s2, s24, s14
	s_addc_u32 s3, s25, s15
	global_load_b32 v12, v0, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+4
	s_addc_u32 s3, s3, truth_values@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s30, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s31, v13, vcc_lo
	global_load_b32 v1, v[12:13], off
	s_waitcnt vmcnt(0)
	v_xad_u32 v15, v1, -1, v18
	v_ashrrev_i32_e32 v1, 31, v15
	v_add_co_u32 v12, vcc_lo, v15, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
	global_load_u8 v1, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v1, v14
	s_cbranch_execz .LBB0_38
; %bb.32:                               ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, links@rel32@lo+4
	s_addc_u32 s21, s21, links@rel32@hi+12
	v_and_b32_e32 v1, v10, v11
	v_mad_i64_i32 v[10:11], null, v15, 24, s[20:21]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_eq_u32_e32 -1, v1
	s_cbranch_execz .LBB0_36
; %bb.33:                               ; %.preheader.preheader.i357
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, links@rel32@lo+20
	s_addc_u32 s21, s21, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[20:21], null, v15, 24, s[20:21]
	s_mov_b32 s4, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[12:13], v[10:11], off
	global_load_b64 v[20:21], v[20:21], off
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[20:21], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, links@rel32@lo+12
	s_addc_u32 s21, s21, links@rel32@hi+20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[10:11], null, v15, 24, s[20:21]
	global_load_b64 v[14:15], v[10:11], off
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[14:15] offset:8
.LBB0_35:                               ; %Flow628
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_36:                               ; %.critedge.i354
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_ne_u64_e32 vcc_lo, 0, v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[12:13], v[6:7], off
	flat_load_b64 v[14:15], v[10:11] offset:8
	s_waitcnt vmcnt(1)
	flat_store_b64 v[12:13], v[10:11]
	s_waitcnt vmcnt(0) lgkmcnt(1)
	global_store_b64 v[6:7], v[14:15], off
.LBB0_38:                               ; %Flow629
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s20, 0
.LBB0_39:                               ; %Flow678
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s21, s16
	s_branch .LBB0_43
.LBB0_40:                               ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr17
	s_branch .LBB0_49
.LBB0_41:                               ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr17
	s_branch .LBB0_46
.LBB0_42:                               ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr17
.LBB0_43:                               ; %Flow677
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_20 Depth=1
	scratch_load_b128 v[10:13], off, off offset:24
	s_mov_b32 s20, -1
	s_and_not1_b32 s17, s17, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_le_f64_e32 vcc_lo, 0x405c0000, v[12:13]
	v_cmp_le_f64_e64 s2, 0x40340000, v[10:11]
	v_cmp_ge_f64_e64 s3, 0x405d0000, v[12:13]
	v_cmp_ge_f64_e64 s4, 0x40380000, v[10:11]
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_not1_b32 s3, s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s4
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s21, s3, s2
.LBB0_45:                               ; %Flow679
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
.LBB0_46:                               ; %Flow676
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:24
	scratch_load_b128 v[20:23], off, off offset:64
	s_and_not1_b32 s3, s21, exec_lo
	s_mov_b32 s20, -1
	s_and_not1_b32 s17, s17, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[12:13], v[12:13]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[8:9], v[10:11]
	v_cmp_neq_f64_e64 s2, 0, v[10:11]
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s21, s3, s2
.LBB0_48:                               ; %Flow680
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
.LBB0_49:                               ; %Flow675
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_59
; %bb.50:                               ; %NodeBlock613
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_lt_i32 s13, 9
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr21
	s_cbranch_scc1 .LBB0_56
; %bb.51:                               ; %NodeBlock611
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 9
                                        ; implicit-def: $sgpr21
	s_cbranch_scc0 .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:24
	scratch_load_b128 v[20:23], off, off offset:64
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[12:13], v[12:13]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f64_e32 vcc_lo, s[8:9], v[10:11]
	s_and_b32 s21, vcc_lo, exec_lo
.LBB0_53:                               ; %Flow631
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:24
	scratch_load_b128 v[20:23], off, off offset:64
	s_and_not1_b32 s2, s21, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[12:13], v[12:13]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_f64_e32 vcc_lo, s[10:11], v[10:11]
	s_and_b32 s3, vcc_lo, exec_lo
	s_or_b32 s21, s2, s3
.LBB0_55:                               ; %Flow632
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
.LBB0_56:                               ; %Flow633
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	scratch_load_b64 v[10:11], off, off offset:40
	scratch_load_b64 v[12:13], off, off offset:80
	s_and_not1_b32 s3, s21, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_f64_e32 vcc_lo, 0xc0490000, v[10:11]
	v_cmp_ge_f64_e64 s2, 0x40490000, v[10:11]
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s21, s3, s2
.LBB0_58:                               ; %Flow634
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr17
.LBB0_59:                               ; %Flow681
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
.LBB0_60:                               ; %Flow674
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_168
; %bb.61:                               ; %NodeBlock609
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 2
	s_mov_b32 s2, -1
	s_cbranch_scc0 .LBB0_96
; %bb.62:                               ; %NodeBlock607
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 3
	s_cbranch_scc0 .LBB0_97
; %bb.63:                               ; %NodeBlock605
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 6
                                        ; implicit-def: $sgpr21
	s_cbranch_scc0 .LBB0_65
; %bb.64:                               ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	scratch_load_b32 v1, off, off offset:48
	scratch_load_b32 v10, off, off offset:88
	s_mov_b32 s2, 0
	s_mov_b32 s20, -1
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v10
	s_and_b32 s21, vcc_lo, exec_lo
.LBB0_65:                               ; %Flow685
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
                                        ; implicit-def: $sgpr17
	s_cbranch_vccnz .LBB0_95
; %bb.66:                               ; %LeafBlock603
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_eq_u32 s13, 4
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr17
	s_cbranch_scc0 .LBB0_94
; %bb.67:                               ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s2, s28, s14
	s_addc_u32 s3, s29, s15
	s_mov_b32 s20, 0
	global_load_b32 v10, v0, s[2:3]
	s_mov_b32 s17, 0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	s_cbranch_vccnz .LBB0_94
; %bb.68:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s4, s22, s14
	s_addc_u32 s5, s23, s15
	global_load_b32 v10, v0, s[4:5]
	s_mov_b32 s4, 0
	s_mov_b32 s5, -1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s30, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s31, v11, vcc_lo
	global_load_b32 v20, v[10:11], off
	v_mov_b32_e32 v11, -1
	v_dual_mov_b32 v21, v17 :: v_dual_mov_b32 v10, v11
	v_mov_b32_e32 v13, v11
	v_mov_b32_e32 v12, v11
.LBB0_69:                               ; %.lr.ph
                                        ;   Parent Loop BB0_20 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v21
	s_xor_b32 s33, s17, -1
	s_or_b32 s17, s17, exec_lo
	s_and_saveexec_b32 s21, s33
	s_cbranch_execz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_69 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, truth_values@rel32@lo+4
	s_addc_u32 s39, s39, truth_values@rel32@hi+12
	v_add_co_u32 v14, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v15, vcc_lo, s39, v1, vcc_lo
	s_and_not1_b32 s17, s17, exec_lo
	global_load_u8 v14, v[14:15], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v14
	s_and_b32 s33, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s17, s17, s33
.LBB0_71:                               ; %.lr.ph._crit_edge
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, truth_values@rel32@lo+4
	s_addc_u32 s39, s39, truth_values@rel32@hi+12
	v_add_co_u32 v14, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v15, vcc_lo, s39, v1, vcc_lo
	s_mov_b32 s33, 0
	s_mov_b32 s35, exec_lo
                                        ; implicit-def: $sgpr21
	global_load_u8 v1, v[14:15], off
                                        ; implicit-def: $vgpr14_vgpr15
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v1
	s_xor_b32 s35, exec_lo, s35
	s_cbranch_execz .LBB0_81
; %bb.72:                               ;   in Loop: Header=BB0_69 Depth=2
	s_and_saveexec_b32 s21, s5
; %bb.73:                               ;   in Loop: Header=BB0_69 Depth=2
	v_dual_mov_b32 v10, -1 :: v_dual_mov_b32 v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v11, v10
	v_mov_b32_e32 v13, v10
	v_mov_b32_e32 v12, v10
	s_clause 0x1
	global_store_b128 v[2:3], v[0:3], off
	global_store_b64 v[8:9], v[10:11], off
; %bb.74:                               ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+4
	s_addc_u32 s39, s39, links@rel32@hi+12
	s_mov_b32 s21, exec_lo
	v_mad_i64_i32 v[14:15], null, v21, 24, s[38:39]
	v_cmpx_eq_u32_e32 -1, v12
	s_cbranch_execz .LBB0_80
; %bb.75:                               ; %is_null_node.exit.i326
                                        ;   in Loop: Header=BB0_69 Depth=2
	v_mov_b32_e32 v12, -1
	s_mov_b32 s33, exec_lo
	v_cmpx_eq_u32_e32 -1, v13
	s_cbranch_execz .LBB0_79
; %bb.76:                               ; %.preheader.preheader.i327
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+20
	s_addc_u32 s39, s39, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[12:13], null, v21, 24, s[38:39]
	s_mov_b32 s36, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[10:11], v[14:15], off
	global_load_b64 v[12:13], v[12:13], off
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[12:13], off
	v_cmpx_ne_u64_e32 0, v[10:11]
	s_cbranch_execz .LBB0_78
; %bb.77:                               ;   in Loop: Header=BB0_69 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+12
	s_addc_u32 s39, s39, links@rel32@hi+20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[14:15], null, v21, 24, s[38:39]
	global_load_b64 v[22:23], v[14:15], off
	v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
	s_waitcnt vmcnt(0)
	flat_store_b64 v[10:11], v[22:23] offset:8
.LBB0_78:                               ; %Flow635
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s36
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
.LBB0_79:                               ; %Flow636
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s33
.LBB0_80:                               ; %.critedge.i324
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s21
	v_cmp_ne_u64_e32 vcc_lo, 0, v[14:15]
	s_mov_b32 s21, 0
	s_and_b32 s33, vcc_lo, exec_lo
.LBB0_81:                               ; %Flow641
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_saveexec_b32 s35, s35
	v_mov_b32_e32 v1, v12
	s_mov_b32 s36, s21
	s_xor_b32 exec_lo, exec_lo, s35
	s_cbranch_execz .LBB0_91
; %bb.82:                               ;   in Loop: Header=BB0_69 Depth=2
	s_xor_b32 s40, s17, -1
	s_mov_b32 s38, s33
                                        ; implicit-def: $sgpr39
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s36, s40
	s_cbranch_execz .LBB0_90
; %bb.83:                               ;   in Loop: Header=BB0_69 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+4
	s_addc_u32 s39, s39, links@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[14:15], null, v21, 24, s[38:39]
	s_mov_b32 s38, exec_lo
	v_cmpx_eq_u32_e32 -1, v10
	s_cbranch_execz .LBB0_89
; %bb.84:                               ; %is_null_node.exit.i332
                                        ;   in Loop: Header=BB0_69 Depth=2
	v_mov_b32_e32 v10, -1
	s_mov_b32 s39, exec_lo
	v_cmpx_eq_u32_e32 -1, v11
	s_cbranch_execz .LBB0_88
; %bb.85:                               ; %.preheader.preheader.i333
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_getpc_b64 s[40:41]
	s_add_u32 s40, s40, links@rel32@lo+20
	s_addc_u32 s41, s41, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[10:11], null, v21, 24, s[40:41]
	s_mov_b32 s40, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[12:13], v[14:15], off
	global_load_b64 v[10:11], v[10:11], off
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[10:11], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_69 Depth=2
	v_mad_i64_i32 v[14:15], null, v21, 24, s[42:43]
	global_load_b64 v[22:23], v[14:15], off
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[22:23] offset:8
.LBB0_87:                               ; %Flow637
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s40
.LBB0_88:                               ; %Flow638
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s39
	v_mov_b32_e32 v13, v11
.LBB0_89:                               ; %.critedge.i330
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s38
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u64_e32 vcc_lo, 0, v[14:15]
	v_mov_b32_e32 v12, v10
	s_and_not1_b32 s38, s33, exec_lo
	s_and_b32 s39, s5, exec_lo
	s_and_b32 s40, vcc_lo, exec_lo
	s_or_b32 s38, s38, s40
.LBB0_90:                               ; %Flow643
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s36
	v_dual_mov_b32 v1, v12 :: v_dual_mov_b32 v12, v10
	s_and_not1_b32 s21, s21, exec_lo
	s_and_b32 s36, s39, exec_lo
	s_and_b32 s5, s5, exec_lo
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s38, s38, exec_lo
	s_or_b32 s36, s21, s36
	s_or_b32 s21, s21, s5
	s_or_b32 s33, s33, s38
.LBB0_91:                               ; %Flow642
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s35
	s_and_saveexec_b32 s5, s33
	s_cbranch_execz .LBB0_93
; %bb.92:                               ; %linkHelper.exit329.sink.split
                                        ;   in Loop: Header=BB0_69 Depth=2
	global_load_b64 v[22:23], v[6:7], off
	flat_load_b64 v[24:25], v[14:15] offset:8
	v_mov_b32_e32 v1, v12
	s_and_not1_b32 s21, s21, exec_lo
	s_and_b32 s33, s36, exec_lo
	s_waitcnt vmcnt(1)
	flat_store_b64 v[22:23], v[14:15]
	s_waitcnt vmcnt(0) lgkmcnt(1)
	global_store_b64 v[6:7], v[24:25], off
	s_or_b32 s21, s21, s33
.LBB0_93:                               ; %linkHelper.exit329
                                        ;   in Loop: Header=BB0_69 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b32 v14, v0, s[2:3]
	s_add_i32 s4, s4, 1
	v_sub_nc_u32_e32 v21, v21, v20
	s_mov_b32 s5, s21
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v12, v[14:15], off
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s4, v12
	v_mov_b32_e32 v12, v1
	s_cbranch_vccz .LBB0_69
.LBB0_94:                               ; %Flow687
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s21, s16
.LBB0_95:                               ; %Flow686
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
	s_branch .LBB0_98
.LBB0_96:                               ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr17
	s_branch .LBB0_129
.LBB0_97:                               ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr17
.LBB0_98:                               ; %Flow684
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_128
; %bb.99:                               ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s2, s28, s14
	s_addc_u32 s3, s29, s15
	global_load_b32 v10, v0, s[2:3]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	s_cbranch_vccnz .LBB0_126
; %bb.100:                              ; %.lr.ph395.preheader
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s4, s22, s14
	s_addc_u32 s5, s23, s15
	s_mov_b32 s17, -1
	global_load_b32 v10, v0, s[4:5]
	s_mov_b32 s4, 0
	s_mov_b32 s5, -1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s30, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s31, v11, vcc_lo
	global_load_b32 v20, v[10:11], off
	v_mov_b32_e32 v11, -1
	v_dual_mov_b32 v21, v17 :: v_dual_mov_b32 v10, v11
	v_mov_b32_e32 v13, v11
	v_mov_b32_e32 v12, v11
.LBB0_101:                              ; %.lr.ph395
                                        ;   Parent Loop BB0_20 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v21
	s_mov_b32 s33, s17
	s_and_not1_b32 s17, s17, exec_lo
	s_and_saveexec_b32 s21, s33
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_101 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, truth_values@rel32@lo+4
	s_addc_u32 s39, s39, truth_values@rel32@hi+12
	v_add_co_u32 v14, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v15, vcc_lo, s39, v1, vcc_lo
	s_and_not1_b32 s17, s17, exec_lo
	global_load_u8 v14, v[14:15], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v14
	s_and_b32 s33, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s17, s17, s33
.LBB0_103:                              ; %.lr.ph395._crit_edge
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, truth_values@rel32@lo+4
	s_addc_u32 s39, s39, truth_values@rel32@hi+12
	v_add_co_u32 v14, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v15, vcc_lo, s39, v1, vcc_lo
	s_mov_b32 s35, 0
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr33
	global_load_u8 v1, v[14:15], off
                                        ; implicit-def: $vgpr14_vgpr15
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v1
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s36, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s36, exec_lo, s36
	s_cbranch_execz .LBB0_113
; %bb.104:                              ;   in Loop: Header=BB0_101 Depth=2
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s21, s17
	s_cbranch_execz .LBB0_112
; %bb.105:                              ;   in Loop: Header=BB0_101 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+4
	s_addc_u32 s39, s39, links@rel32@hi+12
	s_mov_b32 s33, exec_lo
	v_mad_i64_i32 v[14:15], null, v21, 24, s[38:39]
	v_cmpx_eq_u32_e32 -1, v12
	s_cbranch_execz .LBB0_111
; %bb.106:                              ; %is_null_node.exit.i320
                                        ;   in Loop: Header=BB0_101 Depth=2
	v_mov_b32_e32 v12, -1
	s_mov_b32 s35, exec_lo
	v_cmpx_eq_u32_e32 -1, v13
	s_cbranch_execz .LBB0_110
; %bb.107:                              ; %.preheader.preheader.i321
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+20
	s_addc_u32 s39, s39, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[12:13], null, v21, 24, s[38:39]
	s_mov_b32 s38, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[10:11], v[14:15], off
	global_load_b64 v[12:13], v[12:13], off
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[12:13], off
	v_cmpx_ne_u64_e32 0, v[10:11]
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_101 Depth=2
	s_getpc_b64 s[40:41]
	s_add_u32 s40, s40, links@rel32@lo+12
	s_addc_u32 s41, s41, links@rel32@hi+20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[14:15], null, v21, 24, s[40:41]
	global_load_b64 v[22:23], v[14:15], off
	v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
	s_waitcnt vmcnt(0)
	flat_store_b64 v[10:11], v[22:23] offset:8
.LBB0_109:                              ; %Flow647
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s38
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
.LBB0_110:                              ; %Flow648
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s35
.LBB0_111:                              ; %.critedge.i318
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s33
	v_cmp_ne_u64_e32 vcc_lo, 0, v[14:15]
	v_mov_b32_e32 v1, v12
	s_and_b32 s33, s5, exec_lo
	s_and_b32 s35, vcc_lo, exec_lo
.LBB0_112:                              ; %Flow654
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s33, s33, exec_lo
	s_and_b32 s21, s5, exec_lo
	s_and_b32 s35, s35, exec_lo
.LBB0_113:                              ; %Flow653
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_and_not1_saveexec_b32 s36, s36
	s_cbranch_execz .LBB0_123
; %bb.114:                              ;   in Loop: Header=BB0_101 Depth=2
	s_and_saveexec_b32 s38, s5
; %bb.115:                              ;   in Loop: Header=BB0_101 Depth=2
	v_dual_mov_b32 v10, -1 :: v_dual_mov_b32 v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v11, v10
	v_mov_b32_e32 v13, v10
	s_clause 0x1
	global_store_b128 v[2:3], v[0:3], off
	global_store_b64 v[8:9], v[10:11], off
; %bb.116:                              ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s38
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+4
	s_addc_u32 s39, s39, links@rel32@hi+12
	s_mov_b32 s5, exec_lo
	v_mad_i64_i32 v[14:15], null, v21, 24, s[38:39]
	v_cmpx_eq_u32_e32 -1, v10
	s_cbranch_execz .LBB0_122
; %bb.117:                              ; %is_null_node.exit.i
                                        ;   in Loop: Header=BB0_101 Depth=2
	v_mov_b32_e32 v10, -1
	s_mov_b32 s38, exec_lo
	v_cmpx_eq_u32_e32 -1, v11
	s_cbranch_execz .LBB0_121
; %bb.118:                              ; %.preheader.preheader.i
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_getpc_b64 s[40:41]
	s_add_u32 s40, s40, links@rel32@lo+20
	s_addc_u32 s41, s41, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[10:11], null, v21, 24, s[40:41]
	s_mov_b32 s39, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[12:13], v[14:15], off
	global_load_b64 v[10:11], v[10:11], off
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[10:11], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_120
; %bb.119:                              ;   in Loop: Header=BB0_101 Depth=2
	s_getpc_b64 s[40:41]
	s_add_u32 s40, s40, links@rel32@lo+12
	s_addc_u32 s41, s41, links@rel32@hi+20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[14:15], null, v21, 24, s[40:41]
	global_load_b64 v[22:23], v[14:15], off
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[22:23] offset:8
.LBB0_120:                              ; %Flow649
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s39
.LBB0_121:                              ; %Flow650
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s38
	v_mov_b32_e32 v13, v11
.LBB0_122:                              ; %.critedge.i
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u64_e32 vcc_lo, 0, v[14:15]
	v_mov_b32_e32 v1, v10
	v_mov_b32_e32 v12, v10
	s_and_not1_b32 s5, s35, exec_lo
	s_and_not1_b32 s33, s33, exec_lo
	s_and_not1_b32 s21, s21, exec_lo
	s_and_b32 s35, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s35, s5, s35
.LBB0_123:                              ; %Flow655
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s36
	s_and_saveexec_b32 s5, s35
	s_cbranch_execz .LBB0_125
; %bb.124:                              ; %linkHelper.exit.sink.split
                                        ;   in Loop: Header=BB0_101 Depth=2
	global_load_b64 v[22:23], v[6:7], off
	flat_load_b64 v[24:25], v[14:15] offset:8
	v_mov_b32_e32 v12, v1
	s_and_not1_b32 s21, s21, exec_lo
	s_and_b32 s33, s33, exec_lo
	s_waitcnt vmcnt(1)
	flat_store_b64 v[22:23], v[14:15]
	s_waitcnt vmcnt(0) lgkmcnt(1)
	global_store_b64 v[6:7], v[24:25], off
	s_or_b32 s21, s21, s33
.LBB0_125:                              ; %linkHelper.exit
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b32 v14, v0, s[2:3]
	s_add_i32 s4, s4, 1
	v_sub_nc_u32_e32 v21, v21, v20
	s_mov_b32 s5, s21
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v1, v[14:15], off
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s4, v1
	s_cbranch_vccz .LBB0_101
	s_branch .LBB0_127
.LBB0_126:                              ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s17, -1
.LBB0_127:                              ; %Flow658
                                        ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
.LBB0_128:                              ; %Flow688
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
.LBB0_129:                              ; %Flow683
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_mov_b32 s5, 0
	s_cbranch_vccz .LBB0_168
; %bb.130:                              ; %NodeBlock601
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 0
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr17
	s_cbranch_scc0 .LBB0_165
; %bb.131:                              ; %NodeBlock599
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_gt_i32 s13, 1
                                        ; implicit-def: $sgpr17
	s_cbranch_scc0 .LBB0_149
; %bb.132:                              ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s4, s24, s14
	s_addc_u32 s5, s25, s15
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+4
	s_addc_u32 s3, s3, truth_values@rel32@hi+12
	global_load_b32 v10, v0, s[4:5]
                                        ; implicit-def: $sgpr17
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s30, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s31, v11, vcc_lo
	global_load_b32 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_xad_u32 v1, v1, -1, v18
	v_ashrrev_i32_e32 v11, 31, v1
	v_add_co_u32 v10, vcc_lo, v1, s2
	s_mov_b32 s2, -1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_mov_b32 s3, exec_lo
	global_load_u8 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v1
	s_cbranch_execz .LBB0_138
; %bb.133:                              ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, truth_values@rel32@lo+3
	s_addc_u32 s39, s39, truth_values@rel32@hi+11
	v_add_co_u32 v10, vcc_lo, v18, s38
	v_add_co_ci_u32_e32 v11, vcc_lo, s39, v19, vcc_lo
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $sgpr17
	global_load_u8 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v1
	v_cmpx_eq_u16_e32 0, v1
	s_cbranch_execz .LBB0_137
; %bb.134:                              ; %is_null_node.exit.i374
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	global_load_b64 v[10:11], v[2:3], off offset:-24
	global_load_b64 v[12:13], v[8:9], off offset:-24
	v_mov_b32_e32 v1, v0
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b64 v[8:9], v[12:13], off
	global_store_b128 v[2:3], v[0:3], off
	v_cmp_ne_u64_e64 s2, 0, v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_136
; %bb.135:                              ; %.critedge.i372
                                        ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[12:13], v[6:7], off offset:-24
	s_waitcnt vmcnt(0)
	flat_store_b64 v[10:11], v[12:13] offset:8
	global_load_b64 v[14:15], v[6:7], off
	s_waitcnt vmcnt(0)
	flat_store_b64 v[14:15], v[10:11]
	global_store_b64 v[6:7], v[12:13], off
.LBB0_136:                              ; %Flow659
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s17, 0
.LBB0_137:                              ; %Flow664
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s2, vcc_lo, exec_lo
.LBB0_138:                              ; %Flow663
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB0_148
; %bb.139:                              ; %is_null_node.exit.i362
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v[2:3], off offset:-24
	global_load_b64 v[10:11], v[8:9], off offset:-24
	v_mov_b32_e32 v1, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b64 v[8:9], v[10:11], off
	global_store_b128 v[2:3], v[0:3], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_141
; %bb.140:                              ; %.critedge.i360
                                        ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[14:15], v[6:7], off offset:-24
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[14:15] offset:8
	global_load_b64 v[20:21], v[6:7], off
	s_waitcnt vmcnt(0)
	flat_store_b64 v[20:21], v[12:13]
	global_store_b64 v[6:7], v[14:15], off
.LBB0_141:                              ; %linkHelper.exit365
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v12, v0, s[4:5]
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, links@rel32@lo+4
	s_addc_u32 s5, s5, links@rel32@hi+12
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s30, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s31, v13, vcc_lo
	global_load_b32 v1, v[12:13], off
	s_waitcnt vmcnt(0)
	v_xad_u32 v14, v1, -1, v18
	v_and_b32_e32 v1, v10, v11
	v_mad_i64_i32 v[10:11], null, v14, 24, s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_eq_u32_e32 -1, v1
	s_cbranch_execz .LBB0_145
; %bb.142:                              ; %.preheader.preheader.i369
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, links@rel32@lo+20
	s_addc_u32 s5, s5, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[20:21], null, v14, 24, s[4:5]
	s_mov_b32 s4, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[12:13], v[10:11], off
	global_load_b64 v[20:21], v[20:21], off
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[20:21], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_144
; %bb.143:                              ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, links@rel32@lo+12
	s_addc_u32 s39, s39, links@rel32@hi+20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[10:11], null, v14, 24, s[38:39]
	global_load_b64 v[14:15], v[10:11], off
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[14:15] offset:8
.LBB0_144:                              ; %Flow662
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_145:                              ; %.critedge.i366
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ne_u64_e32 0, v[10:11]
	s_cbranch_execz .LBB0_147
; %bb.146:                              ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[12:13], v[6:7], off
	flat_load_b64 v[14:15], v[10:11] offset:8
	s_waitcnt vmcnt(1)
	flat_store_b64 v[12:13], v[10:11]
	s_waitcnt vmcnt(0) lgkmcnt(1)
	global_store_b64 v[6:7], v[14:15], off
.LBB0_147:                              ; %Flow661
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s17, s17, exec_lo
.LBB0_148:                              ; %Flow665
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, 0
.LBB0_149:                              ; %Flow671
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_164
; %bb.150:                              ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+3
	s_addc_u32 s3, s3, truth_values@rel32@hi+11
	v_add_co_u32 v10, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v19, vcc_lo
	s_mov_b32 s17, 0
	s_mov_b32 s2, exec_lo
	global_load_u8 v1, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v1
	s_cbranch_execz .LBB0_152
; %bb.151:                              ;   in Loop: Header=BB0_20 Depth=1
	s_add_u32 s4, s24, s14
	s_addc_u32 s5, s25, s15
	global_load_b32 v10, v0, s[4:5]
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, truth_values@rel32@lo+4
	s_addc_u32 s5, s5, truth_values@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s30, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v11, vcc_lo, s31, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_xad_u32 v10, v10, -1, v18
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v10, vcc_lo, v10, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	global_load_u8 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v10
	s_and_b32 s17, vcc_lo, exec_lo
.LBB0_152:                              ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cndmask_b32_e64 v14, 0, 1, s17
	v_dual_mov_b32 v11, -1 :: v_dual_mov_b32 v10, -1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_eq_u16_e64 v1, v14
	s_cbranch_execz .LBB0_156
; %bb.153:                              ; %is_null_node.exit.i338
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v[2:3], off offset:-24
	global_load_b64 v[10:11], v[8:9], off offset:-24
	v_mov_b32_e32 v1, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b64 v[8:9], v[10:11], off
	global_store_b128 v[2:3], v[0:3], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_155
; %bb.154:                              ; %.critedge.i336
                                        ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[20:21], v[6:7], off offset:-24
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[20:21] offset:8
	global_load_b64 v[22:23], v[6:7], off
	s_waitcnt vmcnt(0)
	flat_store_b64 v[22:23], v[12:13]
	global_store_b64 v[6:7], v[20:21], off
.LBB0_155:                              ; %Flow670
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_156:                              ; %linkHelper.exit341
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_add_u32 s2, s24, s14
	s_addc_u32 s3, s25, s15
	global_load_b32 v12, v0, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+4
	s_addc_u32 s3, s3, truth_values@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s30, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s31, v13, vcc_lo
	global_load_b32 v1, v[12:13], off
	s_waitcnt vmcnt(0)
	v_xad_u32 v15, v1, -1, v18
	v_ashrrev_i32_e32 v1, 31, v15
	v_add_co_u32 v12, vcc_lo, v15, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
	global_load_u8 v1, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v1, v14
	s_cbranch_execz .LBB0_163
; %bb.157:                              ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, links@rel32@lo+4
	s_addc_u32 s5, s5, links@rel32@hi+12
	v_and_b32_e32 v1, v10, v11
	v_mad_i64_i32 v[10:11], null, v15, 24, s[4:5]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_eq_u32_e32 -1, v1
	s_cbranch_execz .LBB0_161
; %bb.158:                              ; %.preheader.preheader.i345
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, links@rel32@lo+20
	s_addc_u32 s5, s5, links@rel32@hi+28
	v_mov_b32_e32 v1, v0
	v_mad_i64_i32 v[20:21], null, v15, 24, s[4:5]
	s_mov_b32 s4, exec_lo
	global_store_b128 v[2:3], v[0:3], off
	s_clause 0x1
	global_load_b64 v[12:13], v[10:11], off
	global_load_b64 v[20:21], v[20:21], off
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[20:21], off
	v_cmpx_ne_u64_e32 0, v[12:13]
	s_cbranch_execz .LBB0_160
; %bb.159:                              ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, links@rel32@lo+12
	s_addc_u32 s15, s15, links@rel32@hi+20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[10:11], null, v15, 24, s[14:15]
	global_load_b64 v[14:15], v[10:11], off
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_waitcnt vmcnt(0)
	flat_store_b64 v[12:13], v[14:15] offset:8
.LBB0_160:                              ; %Flow668
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_161:                              ; %.critedge.i342
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_ne_u64_e32 vcc_lo, 0, v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_163
; %bb.162:                              ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[12:13], v[6:7], off
	flat_load_b64 v[14:15], v[10:11] offset:8
	s_waitcnt vmcnt(1)
	flat_store_b64 v[12:13], v[10:11]
	s_waitcnt vmcnt(0) lgkmcnt(1)
	global_store_b64 v[6:7], v[14:15], off
.LBB0_163:                              ; %Flow669
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_164:                              ; %Flow672
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_mov_b32 s2, 0
.LBB0_165:                              ; %Flow690
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b32 s5, 0
	s_cbranch_vccnz .LBB0_167
; %bb.166:                              ; %LeafBlock597
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_cmp_lg_u32 s13, 0
	s_mov_b32 s5, -1
	s_cselect_b32 s20, -1, 0
	s_and_not1_b32 s17, s17, exec_lo
	s_and_b32 s21, s16, exec_lo
	s_branch .LBB0_168
.LBB0_167:                              ;   in Loop: Header=BB0_20 Depth=1
                                        ; implicit-def: $sgpr21
.LBB0_168:                              ; %Flow682
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_and_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccz .LBB0_170
; %bb.169:                              ; %linkHelper.exit347.loopexit
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_clause 0x1
	scratch_load_b32 v10, off, off offset:16
	scratch_load_b32 v11, off, off offset:56
	s_and_not1_b32 s2, s17, exec_lo
	s_and_b32 s3, s21, exec_lo
	s_mov_b32 s5, 0
	s_or_b32 s17, s2, s3
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[10:11], off
.LBB0_170:                              ; %Flow692
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_174
; %bb.171:                              ; %is_null_node.exit.i380
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+3
	s_addc_u32 s3, s3, truth_values@rel32@hi+11
	v_add_co_u32 v12, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v19, vcc_lo
	v_mov_b32_e32 v1, v0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[10:11], v[2:3], off offset:-24
	global_load_u8 v14, v[12:13], off
	global_load_b64 v[12:13], v[8:9], off offset:-24
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b64 v[8:9], v[12:13], off
	global_store_b128 v[2:3], v[0:3], off
	v_cmp_eq_u16_e64 s17, 0, v14
	v_cmpx_ne_u64_e32 0, v[10:11]
	s_cbranch_execz .LBB0_173
; %bb.172:                              ; %.critedge.i378
                                        ;   in Loop: Header=BB0_20 Depth=1
	global_load_b64 v[1:2], v[6:7], off offset:-24
	s_waitcnt vmcnt(0)
	flat_store_b64 v[10:11], v[1:2] offset:8
	global_load_b64 v[8:9], v[6:7], off
	s_waitcnt vmcnt(0)
	flat_store_b64 v[8:9], v[10:11]
	global_store_b64 v[6:7], v[1:2], off
.LBB0_173:                              ; %Flow673
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_174:                              ; %linkHelper.exit347
                                        ;   in Loop: Header=BB0_20 Depth=1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+4
	s_addc_u32 s3, s3, truth_values@rel32@hi+12
	v_add_co_u32 v1, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v19, vcc_lo
	v_cndmask_b32_e64 v3, 0, 1, s17
	v_add_nc_u32_e32 v17, 1, v17
	s_add_i32 s36, s12, 1
	s_cmp_ge_i32 s12, s37
	s_mov_b32 s16, s17
	global_store_b8 v[1:2], v3, off
	s_cbranch_scc0 .LBB0_20
.LBB0_175:                              ; %._crit_edge
	s_cmp_eq_u32 s34, s37
	s_cbranch_scc0 .LBB0_184
; %bb.176:
	v_ashrrev_i32_e32 v1, 31, v4
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, truth_values@rel32@lo+3
	s_addc_u32 s3, s3, truth_values@rel32@hi+11
	v_add_co_u32 v0, vcc_lo, v4, s2
	v_mov_b32_e32 v2, 0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_u8 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v0
	global_store_b16 v2, v0, s[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_184
; %bb.177:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x78
	s_load_b64 s[0:1], s[0:1], 0x88
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, links@rel32@lo-20
	s_addc_u32 s3, s3, links@rel32@hi-12
	s_mov_b32 s8, exec_lo
	v_mad_i64_i32 v[0:1], null, v4, 24, s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execz .LBB0_183
; %bb.178:                              ; %.lr.ph407.preheader
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s4, 4
	s_addc_u32 s3, s5, 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB0_179:                              ; %.lr.ph407
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_gt_u32 s5, 0x1387
	s_cbranch_scc1 .LBB0_181
; %bb.180:                              ; %.preheader
                                        ;   in Loop: Header=BB0_179 Depth=1
	flat_load_b32 v2, v[0:1] offset:16
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b32 v3, v2, s[2:3] offset:-4
	flat_load_b32 v2, v[0:1] offset:20
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b32 v3, v2, s[2:3]
.LBB0_181:                              ; %.loopexit
                                        ;   in Loop: Header=BB0_179 Depth=1
	flat_load_b64 v[0:1], v[0:1]
	s_add_i32 s5, s5, 1
	s_add_u32 s2, s2, 8
	v_mov_b32_e32 v2, s5
	s_addc_u32 s3, s3, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_179
; %bb.182:                              ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_183:                              ; %Flow625
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v0, 0
	v_min_u32_e32 v1, 0x1388, v2
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v0, v2, s[0:1]
	global_store_b32 v0, v1, s[6:7]
.LBB0_184:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel evaluation
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 96
		.amdhsa_kernarg_size 408
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 47
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	evaluation, .Lfunc_end0-evaluation
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7184
; NumSgprs: 49
; NumVgprs: 26
; ScratchSize: 96
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 49
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	truth_values            ; @truth_values
	.type	truth_values,@object
	.section	.bss,"aw",@nobits
	.globl	truth_values
	.p2align	4, 0x0
truth_values:
	.zero	3000000
	.size	truth_values, 3000000

	.protected	links                   ; @links
	.type	links,@object
	.globl	links
	.p2align	4, 0x0
links:
	.zero	72000000
	.size	links, 72000000

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym truth_values
	.addrsig_sym links
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         128
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         136
        .size:           8
        .value_kind:     global_buffer
      - .offset:         144
        .size:           4
        .value_kind:     by_value
      - .offset:         148
        .size:           4
        .value_kind:     by_value
      - .offset:         152
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         156
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         160
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         164
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         166
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         168
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         170
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         172
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         174
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         200
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         208
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         216
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 408
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           evaluation
    .private_segment_fixed_size: 96
    .sgpr_count:     49
    .sgpr_spill_count: 0
    .symbol:         evaluation.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
