#include "includes.h"

//original c by brade conte, ported to CUDA by jody

#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word


#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))

#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))

typedef struct{
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;

__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};

SHA256_CTX *cpuSHA_CTX;
SHA256_CTX *gpuSHA_CTX;

int BLOCKS = 10;
int THREADS = 500;

extern "C"

extern "C"
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];

for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];

a = ctx[q].state[0];
b = ctx[q].state[1];
c = ctx[q].state[2];
d = ctx[q].state[3];
e = ctx[q].state[4];
f = ctx[q].state[5];
g = ctx[q].state[6];
h = ctx[q].state[7];

for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}

ctx[q].state[0] += a;
ctx[q].state[1] += b;
ctx[q].state[2] += c;
ctx[q].state[3] += d;
ctx[q].state[4] += e;
ctx[q].state[5] += f;
ctx[q].state[6] += g;
ctx[q].state[7] += h;
}
__global__ void sha256_update(SHA256_CTX *ctx, uchar *data, uint len)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
uint i;

for (i=0; i < len; ++i) {
ctx[q].data[ctx[q].datalen] = data[i];
ctx[q].datalen++;
if (ctx[q].datalen == 64) {
sha256_transform(ctx,ctx[q].data);
DBL_INT_ADD(ctx[q].bitlen[0],ctx[q].bitlen[1],512);
ctx[q].datalen = 0;
}
}
}
	.file	"tmpxft_00297c4b_00000000-6_sha256_update.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	sha256_transform
	.type	sha256_transform, @function
sha256_transform:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	sha256_transform, .-sha256_transform
	.globl	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj
	.type	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj, @function
_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z13sha256_updateP10SHA256_CTXPhj(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L4:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj, .-_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj
	.globl	_Z13sha256_updateP10SHA256_CTXPhj
	.type	_Z13sha256_updateP10SHA256_CTXPhj, @function
_Z13sha256_updateP10SHA256_CTXPhj:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj
	.cfi_endproc
.LFE2034:
	.size	_Z13sha256_updateP10SHA256_CTXPhj, .-_Z13sha256_updateP10SHA256_CTXPhj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13sha256_updateP10SHA256_CTXPhj"
.LC1:
	.string	"k"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13sha256_updateP10SHA256_CTXPhj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$256, %r9d
	leaq	_ZL1k(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	THREADS
	.data
	.align 4
	.type	THREADS, @object
	.size	THREADS, 4
THREADS:
	.long	500
	.globl	BLOCKS
	.align 4
	.type	BLOCKS, @object
	.size	BLOCKS, 4
BLOCKS:
	.long	10
	.globl	gpuSHA_CTX
	.bss
	.align 8
	.type	gpuSHA_CTX, @object
	.size	gpuSHA_CTX, 8
gpuSHA_CTX:
	.zero	8
	.globl	cpuSHA_CTX
	.align 8
	.type	cpuSHA_CTX, @object
	.size	cpuSHA_CTX, 8
cpuSHA_CTX:
	.zero	8
	.local	_ZL1k
	.comm	_ZL1k,256,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

//original c by brade conte, ported to CUDA by jody

#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word


#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))

#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))

typedef struct{
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;

__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};

SHA256_CTX *cpuSHA_CTX;
SHA256_CTX *gpuSHA_CTX;

int BLOCKS = 10;
int THREADS = 500;

extern "C"

extern "C"
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];

for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];

a = ctx[q].state[0];
b = ctx[q].state[1];
c = ctx[q].state[2];
d = ctx[q].state[3];
e = ctx[q].state[4];
f = ctx[q].state[5];
g = ctx[q].state[6];
h = ctx[q].state[7];

for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}

ctx[q].state[0] += a;
ctx[q].state[1] += b;
ctx[q].state[2] += c;
ctx[q].state[3] += d;
ctx[q].state[4] += e;
ctx[q].state[5] += f;
ctx[q].state[6] += g;
ctx[q].state[7] += h;
}
__global__ void sha256_update(SHA256_CTX *ctx, uchar *data, uint len)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
uint i;

for (i=0; i < len; ++i) {
ctx[q].data[ctx[q].datalen] = data[i];
ctx[q].datalen++;
if (ctx[q].datalen == 64) {
sha256_transform(ctx,ctx[q].data);
DBL_INT_ADD(ctx[q].bitlen[0],ctx[q].bitlen[1],512);
ctx[q].datalen = 0;
}
}
}
	.text
	.file	"sha256_update.hip"
	.globl	_Z28__device_stub__sha256_updateP10SHA256_CTXPhj # -- Begin function _Z28__device_stub__sha256_updateP10SHA256_CTXPhj
	.type	_Z28__device_stub__sha256_updateP10SHA256_CTXPhj,@function
_Z28__device_stub__sha256_updateP10SHA256_CTXPhj: # @_Z28__device_stub__sha256_updateP10SHA256_CTXPhj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13sha256_updateP10SHA256_CTXPhj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__sha256_updateP10SHA256_CTXPhj, .Lfunc_end0-_Z28__device_stub__sha256_updateP10SHA256_CTXPhj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13sha256_updateP10SHA256_CTXPhj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$k, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	k,@object                       # @k
	.local	k
	.comm	k,256,16
	.type	cpuSHA_CTX,@object              # @cpuSHA_CTX
	.bss
	.globl	cpuSHA_CTX
	.p2align	3, 0x0
cpuSHA_CTX:
	.quad	0
	.size	cpuSHA_CTX, 8

	.type	gpuSHA_CTX,@object              # @gpuSHA_CTX
	.globl	gpuSHA_CTX
	.p2align	3, 0x0
gpuSHA_CTX:
	.quad	0
	.size	gpuSHA_CTX, 8

	.type	BLOCKS,@object                  # @BLOCKS
	.data
	.globl	BLOCKS
	.p2align	2, 0x0
BLOCKS:
	.long	10                              # 0xa
	.size	BLOCKS, 4

	.type	THREADS,@object                 # @THREADS
	.globl	THREADS
	.p2align	2, 0x0
THREADS:
	.long	500                             # 0x1f4
	.size	THREADS, 4

	.type	_Z13sha256_updateP10SHA256_CTXPhj,@object # @_Z13sha256_updateP10SHA256_CTXPhj
	.section	.rodata,"a",@progbits
	.globl	_Z13sha256_updateP10SHA256_CTXPhj
	.p2align	3, 0x0
_Z13sha256_updateP10SHA256_CTXPhj:
	.quad	_Z28__device_stub__sha256_updateP10SHA256_CTXPhj
	.size	_Z13sha256_updateP10SHA256_CTXPhj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13sha256_updateP10SHA256_CTXPhj"
	.size	.L__unnamed_1, 34

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"k"
	.size	.L__unnamed_2, 2

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__sha256_updateP10SHA256_CTXPhj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym k
	.addrsig_sym _Z13sha256_updateP10SHA256_CTXPhj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13sha256_updateP10SHA256_CTXPhj ; -- Begin function _Z13sha256_updateP10SHA256_CTXPhj
	.globl	_Z13sha256_updateP10SHA256_CTXPhj
	.p2align	8
	.type	_Z13sha256_updateP10SHA256_CTXPhj,@function
_Z13sha256_updateP10SHA256_CTXPhj:      ; @_Z13sha256_updateP10SHA256_CTXPhj
; %bb.0:
	s_load_b32 s4, s[0:1], 0x10
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s4, 0
	s_cbranch_scc1 .LBB0_13
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x24
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 16
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
	v_mad_i64_i32 v[8:9], null, 0x6c, v1, s[0:1]
	global_load_b32 v0, v[8:9], off offset:64
	v_add_co_u32 v10, vcc_lo, v8, 64
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, 0x4c, v8
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v14, vcc_lo, 0x44, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v16, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v9, vcc_lo
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_6 Depth 2
                                        ;     Child Loop BB0_8 Depth 2
	v_mov_b32_e32 v1, s5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v8, v0
	s_mov_b32 s6, exec_lo
	global_load_u8 v2, v1, s[2:3]
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
	global_load_b32 v0, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, 1, v0
	global_store_b32 v[10:11], v0, off
	v_cmpx_eq_u32_e32 64, v0
	s_cbranch_execz .LBB0_12
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
	s_mov_b32 s0, 0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v[0:1], off offset:-1
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 64
	s_waitcnt vmcnt(0)
	v_perm_b32 v2, v2, v2, 0x4050607
	scratch_store_b32 off, v2, s1
	s_cbranch_scc0 .LBB0_4
; %bb.5:                                ; %.preheader.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	scratch_load_b32 v0, off, off offset:16
	s_mov_b32 s0, 0
.LBB0_6:                                ; %.lr.ph.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s1, v19
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s1, s1, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s7, s1, 56
	s_add_i32 s9, s1, 4
	s_add_i32 s8, s1, 36
	s_clause 0x2
	scratch_load_b32 v1, off, s7
	scratch_load_b32 v2, off, s9
	scratch_load_b32 v3, off, s8
	s_add_i32 s1, s1, 64
	s_cmpk_lg_i32 s0, 0xc0
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v4, v1, v1, 17
	v_alignbit_b32 v5, v1, v1, 19
	v_lshrrev_b32_e32 v1, 10, v1
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v6, v2, v2, 7
	v_alignbit_b32 v7, v2, v2, 18
	v_lshrrev_b32_e32 v20, 3, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v3, v0
	v_xor3_b32 v1, v4, v5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v3, v6, v7, v20
	v_add3_u32 v1, v0, v1, v3
	v_mov_b32_e32 v0, v2
	scratch_store_b32 off, v1, s1
	s_cbranch_scc1 .LBB0_6
; %bb.7:                                ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b128 v[0:3], v[12:13], off
	global_load_b128 v[4:7], v[12:13], off offset:16
	s_mov_b32 s7, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, k@rel32@lo+4
	s_addc_u32 s1, s1, k@rel32@hi+12
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v27, v0 :: v_dual_mov_b32 v20, v1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v26, v7 :: v_dual_mov_b32 v29, v6
	v_dual_mov_b32 v31, v5 :: v_dual_mov_b32 v28, v4
	v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v30, v2
.LBB0_8:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s8, s7, 16
	global_load_b32 v32, v18, s[0:1]
	scratch_load_b32 v33, off, s8
	v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v23, v31
	v_dual_mov_b32 v24, v28 :: v_dual_mov_b32 v21, v30
	v_dual_mov_b32 v22, v29 :: v_dual_mov_b32 v25, v20
	v_mov_b32_e32 v20, v27
	s_delay_alu instid0(VALU_DEP_3)
	v_alignbit_b32 v27, v24, v24, 6
	v_alignbit_b32 v28, v24, v24, 11
	v_alignbit_b32 v29, v24, v24, 25
	v_and_b32_e32 v30, v24, v23
	v_not_b32_e32 v31, v24
	v_xor_b32_e32 v37, v21, v25
	s_add_i32 s7, s7, 4
	v_xor3_b32 v27, v27, v28, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v29, v23 :: v_dual_and_b32 v28, v22, v31
	v_add_nc_u32_e32 v26, v30, v26
	v_and_b32_e32 v31, v21, v25
	v_alignbit_b32 v35, v20, v20, 2
	v_alignbit_b32 v36, v20, v20, 13
	v_alignbit_b32 v30, v20, v20, 22
	v_and_b32_e32 v37, v37, v20
	v_add3_u32 v26, v26, v28, v27
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	v_xor3_b32 v27, v35, v36, v30
	v_mov_b32_e32 v30, v25
	s_cmpk_lg_i32 s7, 0x100
	s_waitcnt vmcnt(0)
	v_add3_u32 v32, v26, v32, v33
	v_mov_b32_e32 v26, v22
	v_xor_b32_e32 v35, v37, v31
	v_mov_b32_e32 v31, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, v32, v34
	v_add3_u32 v27, v35, v27, v32
	s_cbranch_scc1 .LBB0_8
; %bb.9:                                ; %sha256_transform.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v26, v[14:15], off
	v_add_nc_u32_e32 v0, v27, v0
	v_add_nc_u32_e32 v1, v20, v1
	v_add_nc_u32_e32 v2, v25, v2
	v_add_nc_u32_e32 v3, v21, v3
	v_add_nc_u32_e32 v4, v28, v4
	v_add_nc_u32_e32 v5, v24, v5
	v_add_nc_u32_e32 v6, v23, v6
	v_add_nc_u32_e32 v7, v22, v7
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	global_store_b128 v[12:13], v[0:3], off
	global_store_b128 v[12:13], v[4:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u32_e32 0xfffffdff, v26
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v0, v[14:15], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, 1, v0
	global_store_b32 v[14:15], v0, off offset:4
.LBB0_11:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, 0x200, v26
	global_store_b64 v[10:11], v[0:1], off
.LBB0_12:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s5, s4
	s_cbranch_scc1 .LBB0_2
.LBB0_13:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13sha256_updateP10SHA256_CTXPhj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13sha256_updateP10SHA256_CTXPhj, .Lfunc_end0-_Z13sha256_updateP10SHA256_CTXPhj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 940
; NumSgprs: 18
; NumVgprs: 38
; ScratchSize: 272
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	k                       ; @k
	.type	k,@object
	.data
	.globl	k
	.p2align	4, 0x0
k:
	.long	1116352408                      ; 0x428a2f98
	.long	1899447441                      ; 0x71374491
	.long	3049323471                      ; 0xb5c0fbcf
	.long	3921009573                      ; 0xe9b5dba5
	.long	961987163                       ; 0x3956c25b
	.long	1508970993                      ; 0x59f111f1
	.long	2453635748                      ; 0x923f82a4
	.long	2870763221                      ; 0xab1c5ed5
	.long	3624381080                      ; 0xd807aa98
	.long	310598401                       ; 0x12835b01
	.long	607225278                       ; 0x243185be
	.long	1426881987                      ; 0x550c7dc3
	.long	1925078388                      ; 0x72be5d74
	.long	2162078206                      ; 0x80deb1fe
	.long	2614888103                      ; 0x9bdc06a7
	.long	3248222580                      ; 0xc19bf174
	.long	3835390401                      ; 0xe49b69c1
	.long	4022224774                      ; 0xefbe4786
	.long	264347078                       ; 0xfc19dc6
	.long	604807628                       ; 0x240ca1cc
	.long	770255983                       ; 0x2de92c6f
	.long	1249150122                      ; 0x4a7484aa
	.long	1555081692                      ; 0x5cb0a9dc
	.long	1996064986                      ; 0x76f988da
	.long	2554220882                      ; 0x983e5152
	.long	2821834349                      ; 0xa831c66d
	.long	2952996808                      ; 0xb00327c8
	.long	3210313671                      ; 0xbf597fc7
	.long	3336571891                      ; 0xc6e00bf3
	.long	3584528711                      ; 0xd5a79147
	.long	113926993                       ; 0x6ca6351
	.long	338241895                       ; 0x14292967
	.long	666307205                       ; 0x27b70a85
	.long	773529912                       ; 0x2e1b2138
	.long	1294757372                      ; 0x4d2c6dfc
	.long	1396182291                      ; 0x53380d13
	.long	1695183700                      ; 0x650a7354
	.long	1986661051                      ; 0x766a0abb
	.long	2177026350                      ; 0x81c2c92e
	.long	2456956037                      ; 0x92722c85
	.long	2730485921                      ; 0xa2bfe8a1
	.long	2820302411                      ; 0xa81a664b
	.long	3259730800                      ; 0xc24b8b70
	.long	3345764771                      ; 0xc76c51a3
	.long	3516065817                      ; 0xd192e819
	.long	3600352804                      ; 0xd6990624
	.long	4094571909                      ; 0xf40e3585
	.long	275423344                       ; 0x106aa070
	.long	430227734                       ; 0x19a4c116
	.long	506948616                       ; 0x1e376c08
	.long	659060556                       ; 0x2748774c
	.long	883997877                       ; 0x34b0bcb5
	.long	958139571                       ; 0x391c0cb3
	.long	1322822218                      ; 0x4ed8aa4a
	.long	1537002063                      ; 0x5b9cca4f
	.long	1747873779                      ; 0x682e6ff3
	.long	1955562222                      ; 0x748f82ee
	.long	2024104815                      ; 0x78a5636f
	.long	2227730452                      ; 0x84c87814
	.long	2361852424                      ; 0x8cc70208
	.long	2428436474                      ; 0x90befffa
	.long	2756734187                      ; 0xa4506ceb
	.long	3204031479                      ; 0xbef9a3f7
	.long	3329325298                      ; 0xc67178f2
	.size	k, 256

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym k
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13sha256_updateP10SHA256_CTXPhj
    .private_segment_fixed_size: 272
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13sha256_updateP10SHA256_CTXPhj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
